2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
41 #include <asm/perf_event.h>
42 #include <asm/tlbflush.h>
44 #include <asm/debugreg.h>
45 #include <asm/kvm_para.h>
46 #include <asm/irq_remapping.h>
48 #include <asm/virtext.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id svm_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_SVM),
60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62 #define IOPM_ALLOC_ORDER 2
63 #define MSRPM_ALLOC_ORDER 1
65 #define SEG_TYPE_LDT 2
66 #define SEG_TYPE_BUSY_TSS16 3
68 #define SVM_FEATURE_NPT (1 << 0)
69 #define SVM_FEATURE_LBRV (1 << 1)
70 #define SVM_FEATURE_SVML (1 << 2)
71 #define SVM_FEATURE_NRIP (1 << 3)
72 #define SVM_FEATURE_TSC_RATE (1 << 4)
73 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
74 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
75 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
76 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
78 #define SVM_AVIC_DOORBELL 0xc001011b
80 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
81 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
82 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
86 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
87 #define TSC_RATIO_MIN 0x0000000000000001ULL
88 #define TSC_RATIO_MAX 0x000000ffffffffffULL
90 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
93 * 0xff is broadcast, so the max index allowed for physical APIC ID
94 * table is 0xfe. APIC IDs above 0xff are reserved.
96 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
102 /* AVIC GATAG is encoded using VM and VCPU IDs */
103 #define AVIC_VCPU_ID_BITS 8
104 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
106 #define AVIC_VM_ID_BITS 24
107 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
108 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
110 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
111 (y & AVIC_VCPU_ID_MASK))
112 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
113 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
115 static bool erratum_383_found __read_mostly;
117 static const u32 host_save_user_msrs[] = {
119 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
122 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
130 struct nested_state {
136 /* These are the merged vectors */
139 /* gpa pointers to the real vectors */
143 /* A VMEXIT is required but not yet emulated */
146 /* cache for intercepts of the guest */
149 u32 intercept_exceptions;
152 /* Nested Paging related state */
156 #define MSRPM_OFFSETS 16
157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
160 * Set osvw_len to higher value when updated Revision Guides
161 * are published and we know what the new status bits are
163 static uint64_t osvw_len = 4, osvw_status;
166 struct kvm_vcpu vcpu;
168 unsigned long vmcb_pa;
169 struct svm_cpu_data *svm_data;
170 uint64_t asid_generation;
171 uint64_t sysenter_esp;
172 uint64_t sysenter_eip;
177 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
189 struct nested_state nested;
193 unsigned int3_injected;
194 unsigned long int3_rip;
197 /* cached guest cpuid flags for faster access */
198 bool nrips_enabled : 1;
201 struct page *avic_backing_page;
202 u64 *avic_physical_id_cache;
203 bool avic_is_running;
206 * Per-vcpu list of struct amd_svm_iommu_ir:
207 * This is used mainly to store interrupt remapping information used
208 * when update the vcpu affinity. This avoids the need to scan for
209 * IRTE and try to match ga_tag in the IOMMU driver.
211 struct list_head ir_list;
212 spinlock_t ir_list_lock;
216 * This is a wrapper of struct amd_iommu_ir_data.
218 struct amd_svm_iommu_ir {
219 struct list_head node; /* Used by SVM for per-vcpu ir_list */
220 void *data; /* Storing pointer to struct amd_ir_data */
223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
232 #define TSC_RATIO_DEFAULT 0x0100000000ULL
234 #define MSR_INVALID 0xffffffffU
236 static const struct svm_direct_access_msrs {
237 u32 index; /* Index of the MSR */
238 bool always; /* True if intercept is always on */
239 } direct_access_msrs[] = {
240 { .index = MSR_STAR, .always = true },
241 { .index = MSR_IA32_SYSENTER_CS, .always = true },
243 { .index = MSR_GS_BASE, .always = true },
244 { .index = MSR_FS_BASE, .always = true },
245 { .index = MSR_KERNEL_GS_BASE, .always = true },
246 { .index = MSR_LSTAR, .always = true },
247 { .index = MSR_CSTAR, .always = true },
248 { .index = MSR_SYSCALL_MASK, .always = true },
250 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
251 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
252 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
253 { .index = MSR_IA32_LASTINTTOIP, .always = false },
254 { .index = MSR_INVALID, .always = false },
257 /* enable NPT for AMD64 and X86 with PAE */
258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
259 static bool npt_enabled = true;
261 static bool npt_enabled;
264 /* allow nested paging (virtualized MMU) for all guests */
265 static int npt = true;
266 module_param(npt, int, S_IRUGO);
268 /* allow nested virtualization in KVM/SVM */
269 static int nested = true;
270 module_param(nested, int, S_IRUGO);
272 /* enable / disable AVIC */
274 #ifdef CONFIG_X86_LOCAL_APIC
275 module_param(avic, int, S_IRUGO);
278 /* AVIC VM ID bit masks and lock */
279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
280 static DEFINE_SPINLOCK(avic_vm_id_lock);
282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
284 static void svm_complete_interrupts(struct vcpu_svm *svm);
286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
287 static int nested_svm_intercept(struct vcpu_svm *svm);
288 static int nested_svm_vmexit(struct vcpu_svm *svm);
289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
290 bool has_error_code, u32 error_code);
293 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
294 pause filter count */
295 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
296 VMCB_ASID, /* ASID */
297 VMCB_INTR, /* int_ctl, int_vector */
298 VMCB_NPT, /* npt_en, nCR3, gPAT */
299 VMCB_CR, /* CR0, CR3, CR4, EFER */
300 VMCB_DR, /* DR6, DR7 */
301 VMCB_DT, /* GDT, IDT */
302 VMCB_SEG, /* CS, DS, SS, ES, CPL */
303 VMCB_CR2, /* CR2 only */
304 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
305 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
306 * AVIC PHYSICAL_TABLE pointer,
307 * AVIC LOGICAL_TABLE pointer
312 /* TPR and CR2 are always written before VMRUN */
313 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
315 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
317 static inline void mark_all_dirty(struct vmcb *vmcb)
319 vmcb->control.clean = 0;
322 static inline void mark_all_clean(struct vmcb *vmcb)
324 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
325 & ~VMCB_ALWAYS_DIRTY_MASK;
328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
330 vmcb->control.clean &= ~(1 << bit);
333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
335 return container_of(vcpu, struct vcpu_svm, vcpu);
338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
340 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
341 mark_dirty(svm->vmcb, VMCB_AVIC);
344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
346 struct vcpu_svm *svm = to_svm(vcpu);
347 u64 *entry = svm->avic_physical_id_cache;
352 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
355 static void recalc_intercepts(struct vcpu_svm *svm)
357 struct vmcb_control_area *c, *h;
358 struct nested_state *g;
360 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
362 if (!is_guest_mode(&svm->vcpu))
365 c = &svm->vmcb->control;
366 h = &svm->nested.hsave->control;
369 c->intercept_cr = h->intercept_cr | g->intercept_cr;
370 c->intercept_dr = h->intercept_dr | g->intercept_dr;
371 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
372 c->intercept = h->intercept | g->intercept;
375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
377 if (is_guest_mode(&svm->vcpu))
378 return svm->nested.hsave;
383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
385 struct vmcb *vmcb = get_host_vmcb(svm);
387 vmcb->control.intercept_cr |= (1U << bit);
389 recalc_intercepts(svm);
392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
394 struct vmcb *vmcb = get_host_vmcb(svm);
396 vmcb->control.intercept_cr &= ~(1U << bit);
398 recalc_intercepts(svm);
401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
403 struct vmcb *vmcb = get_host_vmcb(svm);
405 return vmcb->control.intercept_cr & (1U << bit);
408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
410 struct vmcb *vmcb = get_host_vmcb(svm);
412 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
413 | (1 << INTERCEPT_DR1_READ)
414 | (1 << INTERCEPT_DR2_READ)
415 | (1 << INTERCEPT_DR3_READ)
416 | (1 << INTERCEPT_DR4_READ)
417 | (1 << INTERCEPT_DR5_READ)
418 | (1 << INTERCEPT_DR6_READ)
419 | (1 << INTERCEPT_DR7_READ)
420 | (1 << INTERCEPT_DR0_WRITE)
421 | (1 << INTERCEPT_DR1_WRITE)
422 | (1 << INTERCEPT_DR2_WRITE)
423 | (1 << INTERCEPT_DR3_WRITE)
424 | (1 << INTERCEPT_DR4_WRITE)
425 | (1 << INTERCEPT_DR5_WRITE)
426 | (1 << INTERCEPT_DR6_WRITE)
427 | (1 << INTERCEPT_DR7_WRITE);
429 recalc_intercepts(svm);
432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
434 struct vmcb *vmcb = get_host_vmcb(svm);
436 vmcb->control.intercept_dr = 0;
438 recalc_intercepts(svm);
441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
443 struct vmcb *vmcb = get_host_vmcb(svm);
445 vmcb->control.intercept_exceptions |= (1U << bit);
447 recalc_intercepts(svm);
450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
452 struct vmcb *vmcb = get_host_vmcb(svm);
454 vmcb->control.intercept_exceptions &= ~(1U << bit);
456 recalc_intercepts(svm);
459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
461 struct vmcb *vmcb = get_host_vmcb(svm);
463 vmcb->control.intercept |= (1ULL << bit);
465 recalc_intercepts(svm);
468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
470 struct vmcb *vmcb = get_host_vmcb(svm);
472 vmcb->control.intercept &= ~(1ULL << bit);
474 recalc_intercepts(svm);
477 static inline void enable_gif(struct vcpu_svm *svm)
479 svm->vcpu.arch.hflags |= HF_GIF_MASK;
482 static inline void disable_gif(struct vcpu_svm *svm)
484 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
487 static inline bool gif_set(struct vcpu_svm *svm)
489 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
492 static unsigned long iopm_base;
494 struct kvm_ldttss_desc {
497 unsigned base1:8, type:5, dpl:2, p:1;
498 unsigned limit1:4, zero0:3, g:1, base2:8;
501 } __attribute__((packed));
503 struct svm_cpu_data {
509 struct kvm_ldttss_desc *tss_desc;
511 struct page *save_area;
514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
516 struct svm_init_data {
521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
524 #define MSRS_RANGE_SIZE 2048
525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
527 static u32 svm_msrpm_offset(u32 msr)
532 for (i = 0; i < NUM_MSR_MAPS; i++) {
533 if (msr < msrpm_ranges[i] ||
534 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
537 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
538 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
540 /* Now we have the u8 offset - but need the u32 offset */
544 /* MSR not in any range */
548 #define MAX_INST_SIZE 15
550 static inline void clgi(void)
552 asm volatile (__ex(SVM_CLGI));
555 static inline void stgi(void)
557 asm volatile (__ex(SVM_STGI));
560 static inline void invlpga(unsigned long addr, u32 asid)
562 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
565 static int get_npt_level(void)
568 return PT64_ROOT_LEVEL;
570 return PT32E_ROOT_LEVEL;
574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
576 vcpu->arch.efer = efer;
577 if (!npt_enabled && !(efer & EFER_LMA))
580 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
581 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
584 static int is_external_interrupt(u32 info)
586 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
587 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
592 struct vcpu_svm *svm = to_svm(vcpu);
595 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
596 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
602 struct vcpu_svm *svm = to_svm(vcpu);
605 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
607 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
613 struct vcpu_svm *svm = to_svm(vcpu);
615 if (svm->vmcb->control.next_rip != 0) {
616 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
617 svm->next_rip = svm->vmcb->control.next_rip;
620 if (!svm->next_rip) {
621 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
623 printk(KERN_DEBUG "%s: NOP\n", __func__);
626 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
627 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
628 __func__, kvm_rip_read(vcpu), svm->next_rip);
630 kvm_rip_write(vcpu, svm->next_rip);
631 svm_set_interrupt_shadow(vcpu, 0);
634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
635 bool has_error_code, u32 error_code,
638 struct vcpu_svm *svm = to_svm(vcpu);
641 * If we are within a nested VM we'd better #VMEXIT and let the guest
642 * handle the exception
645 nested_svm_check_exception(svm, nr, has_error_code, error_code))
648 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
649 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
652 * For guest debugging where we have to reinject #BP if some
653 * INT3 is guest-owned:
654 * Emulate nRIP by moving RIP forward. Will fail if injection
655 * raises a fault that is not intercepted. Still better than
656 * failing in all cases.
658 skip_emulated_instruction(&svm->vcpu);
659 rip = kvm_rip_read(&svm->vcpu);
660 svm->int3_rip = rip + svm->vmcb->save.cs.base;
661 svm->int3_injected = rip - old_rip;
664 svm->vmcb->control.event_inj = nr
666 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
667 | SVM_EVTINJ_TYPE_EXEPT;
668 svm->vmcb->control.event_inj_err = error_code;
671 static void svm_init_erratum_383(void)
677 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
680 /* Use _safe variants to not break nested virtualization */
681 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
687 low = lower_32_bits(val);
688 high = upper_32_bits(val);
690 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
692 erratum_383_found = true;
695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
698 * Guests should see errata 400 and 415 as fixed (assuming that
699 * HLT and IO instructions are intercepted).
701 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
702 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
705 * By increasing VCPU's osvw.length to 3 we are telling the guest that
706 * all osvw.status bits inside that length, including bit 0 (which is
707 * reserved for erratum 298), are valid. However, if host processor's
708 * osvw_len is 0 then osvw_status[0] carries no information. We need to
709 * be conservative here and therefore we tell the guest that erratum 298
710 * is present (because we really don't know).
712 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
713 vcpu->arch.osvw.status |= 1;
716 static int has_svm(void)
720 if (!cpu_has_svm(&msg)) {
721 printk(KERN_INFO "has_svm: %s\n", msg);
728 static void svm_hardware_disable(void)
730 /* Make sure we clean up behind us */
731 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
732 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
736 amd_pmu_disable_virt();
739 static int svm_hardware_enable(void)
742 struct svm_cpu_data *sd;
744 struct desc_ptr gdt_descr;
745 struct desc_struct *gdt;
746 int me = raw_smp_processor_id();
748 rdmsrl(MSR_EFER, efer);
749 if (efer & EFER_SVME)
753 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
756 sd = per_cpu(svm_data, me);
758 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
762 sd->asid_generation = 1;
763 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
764 sd->next_asid = sd->max_asid + 1;
766 native_store_gdt(&gdt_descr);
767 gdt = (struct desc_struct *)gdt_descr.address;
768 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
770 wrmsrl(MSR_EFER, efer | EFER_SVME);
772 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
774 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
775 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
776 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
783 * Note that it is possible to have a system with mixed processor
784 * revisions and therefore different OSVW bits. If bits are not the same
785 * on different processors then choose the worst case (i.e. if erratum
786 * is present on one processor and not on another then assume that the
787 * erratum is present everywhere).
789 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
790 uint64_t len, status = 0;
793 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
795 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
799 osvw_status = osvw_len = 0;
803 osvw_status |= status;
804 osvw_status &= (1ULL << osvw_len) - 1;
807 osvw_status = osvw_len = 0;
809 svm_init_erratum_383();
811 amd_pmu_enable_virt();
816 static void svm_cpu_uninit(int cpu)
818 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
823 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
824 __free_page(sd->save_area);
828 static int svm_cpu_init(int cpu)
830 struct svm_cpu_data *sd;
833 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
837 sd->save_area = alloc_page(GFP_KERNEL);
842 per_cpu(svm_data, cpu) = sd;
852 static bool valid_msr_intercept(u32 index)
856 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
857 if (direct_access_msrs[i].index == index)
863 static void set_msr_interception(u32 *msrpm, unsigned msr,
866 u8 bit_read, bit_write;
871 * If this warning triggers extend the direct_access_msrs list at the
872 * beginning of the file
874 WARN_ON(!valid_msr_intercept(msr));
876 offset = svm_msrpm_offset(msr);
877 bit_read = 2 * (msr & 0x0f);
878 bit_write = 2 * (msr & 0x0f) + 1;
881 BUG_ON(offset == MSR_INVALID);
883 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
884 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
889 static void svm_vcpu_init_msrpm(u32 *msrpm)
893 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
895 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
896 if (!direct_access_msrs[i].always)
899 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
903 static void add_msr_offset(u32 offset)
907 for (i = 0; i < MSRPM_OFFSETS; ++i) {
909 /* Offset already in list? */
910 if (msrpm_offsets[i] == offset)
913 /* Slot used by another offset? */
914 if (msrpm_offsets[i] != MSR_INVALID)
917 /* Add offset to list */
918 msrpm_offsets[i] = offset;
924 * If this BUG triggers the msrpm_offsets table has an overflow. Just
925 * increase MSRPM_OFFSETS in this case.
930 static void init_msrpm_offsets(void)
934 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
936 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
939 offset = svm_msrpm_offset(direct_access_msrs[i].index);
940 BUG_ON(offset == MSR_INVALID);
942 add_msr_offset(offset);
946 static void svm_enable_lbrv(struct vcpu_svm *svm)
948 u32 *msrpm = svm->msrpm;
950 svm->vmcb->control.lbr_ctl = 1;
951 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
952 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
953 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
954 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
957 static void svm_disable_lbrv(struct vcpu_svm *svm)
959 u32 *msrpm = svm->msrpm;
961 svm->vmcb->control.lbr_ctl = 0;
962 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
963 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
964 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
965 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
969 * This hash table is used to map VM_ID to a struct kvm_arch,
970 * when handling AMD IOMMU GALOG notification to schedule in
973 #define SVM_VM_DATA_HASH_BITS 8
974 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
975 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
978 * This function is called from IOMMU driver to notify
979 * SVM to schedule in a particular vCPU of a particular VM.
981 static int avic_ga_log_notifier(u32 ga_tag)
984 struct kvm_arch *ka = NULL;
985 struct kvm_vcpu *vcpu = NULL;
986 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
987 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
989 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
991 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
992 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
993 struct kvm *kvm = container_of(ka, struct kvm, arch);
994 struct kvm_arch *vm_data = &kvm->arch;
996 if (vm_data->avic_vm_id != vm_id)
998 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1001 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1007 * At this point, the IOMMU should have already set the pending
1008 * bit in the vAPIC backing page. So, we just need to schedule
1011 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1012 kvm_vcpu_wake_up(vcpu);
1017 static __init int svm_hardware_setup(void)
1020 struct page *iopm_pages;
1024 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1029 iopm_va = page_address(iopm_pages);
1030 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1031 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1033 init_msrpm_offsets();
1035 if (boot_cpu_has(X86_FEATURE_NX))
1036 kvm_enable_efer_bits(EFER_NX);
1038 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1039 kvm_enable_efer_bits(EFER_FFXSR);
1041 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1042 kvm_has_tsc_control = true;
1043 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1044 kvm_tsc_scaling_ratio_frac_bits = 32;
1048 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1049 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1052 for_each_possible_cpu(cpu) {
1053 r = svm_cpu_init(cpu);
1058 if (!boot_cpu_has(X86_FEATURE_NPT))
1059 npt_enabled = false;
1061 if (npt_enabled && !npt) {
1062 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1063 npt_enabled = false;
1067 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1074 !boot_cpu_has(X86_FEATURE_AVIC) ||
1075 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1078 pr_info("AVIC enabled\n");
1080 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1087 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1092 static __exit void svm_hardware_unsetup(void)
1096 for_each_possible_cpu(cpu)
1097 svm_cpu_uninit(cpu);
1099 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1103 static void init_seg(struct vmcb_seg *seg)
1106 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1107 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1108 seg->limit = 0xffff;
1112 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1115 seg->attrib = SVM_SELECTOR_P_MASK | type;
1116 seg->limit = 0xffff;
1120 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1122 struct vcpu_svm *svm = to_svm(vcpu);
1123 u64 g_tsc_offset = 0;
1125 if (is_guest_mode(vcpu)) {
1126 g_tsc_offset = svm->vmcb->control.tsc_offset -
1127 svm->nested.hsave->control.tsc_offset;
1128 svm->nested.hsave->control.tsc_offset = offset;
1130 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1131 svm->vmcb->control.tsc_offset,
1134 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1136 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1139 static void avic_init_vmcb(struct vcpu_svm *svm)
1141 struct vmcb *vmcb = svm->vmcb;
1142 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1143 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1144 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1145 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1147 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1148 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1149 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1150 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1151 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1152 svm->vcpu.arch.apicv_active = true;
1155 static void init_vmcb(struct vcpu_svm *svm)
1157 struct vmcb_control_area *control = &svm->vmcb->control;
1158 struct vmcb_save_area *save = &svm->vmcb->save;
1160 svm->vcpu.arch.hflags = 0;
1162 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1163 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1164 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1165 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1166 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1167 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1168 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1169 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1171 set_dr_intercepts(svm);
1173 set_exception_intercept(svm, PF_VECTOR);
1174 set_exception_intercept(svm, UD_VECTOR);
1175 set_exception_intercept(svm, MC_VECTOR);
1176 set_exception_intercept(svm, AC_VECTOR);
1177 set_exception_intercept(svm, DB_VECTOR);
1179 set_intercept(svm, INTERCEPT_INTR);
1180 set_intercept(svm, INTERCEPT_NMI);
1181 set_intercept(svm, INTERCEPT_SMI);
1182 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1183 set_intercept(svm, INTERCEPT_RDPMC);
1184 set_intercept(svm, INTERCEPT_CPUID);
1185 set_intercept(svm, INTERCEPT_INVD);
1186 set_intercept(svm, INTERCEPT_HLT);
1187 set_intercept(svm, INTERCEPT_INVLPG);
1188 set_intercept(svm, INTERCEPT_INVLPGA);
1189 set_intercept(svm, INTERCEPT_IOIO_PROT);
1190 set_intercept(svm, INTERCEPT_MSR_PROT);
1191 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1192 set_intercept(svm, INTERCEPT_SHUTDOWN);
1193 set_intercept(svm, INTERCEPT_VMRUN);
1194 set_intercept(svm, INTERCEPT_VMMCALL);
1195 set_intercept(svm, INTERCEPT_VMLOAD);
1196 set_intercept(svm, INTERCEPT_VMSAVE);
1197 set_intercept(svm, INTERCEPT_STGI);
1198 set_intercept(svm, INTERCEPT_CLGI);
1199 set_intercept(svm, INTERCEPT_SKINIT);
1200 set_intercept(svm, INTERCEPT_WBINVD);
1201 set_intercept(svm, INTERCEPT_MONITOR);
1202 set_intercept(svm, INTERCEPT_MWAIT);
1203 set_intercept(svm, INTERCEPT_XSETBV);
1205 control->iopm_base_pa = iopm_base;
1206 control->msrpm_base_pa = __pa(svm->msrpm);
1207 control->int_ctl = V_INTR_MASKING_MASK;
1209 init_seg(&save->es);
1210 init_seg(&save->ss);
1211 init_seg(&save->ds);
1212 init_seg(&save->fs);
1213 init_seg(&save->gs);
1215 save->cs.selector = 0xf000;
1216 save->cs.base = 0xffff0000;
1217 /* Executable/Readable Code Segment */
1218 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1219 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1220 save->cs.limit = 0xffff;
1222 save->gdtr.limit = 0xffff;
1223 save->idtr.limit = 0xffff;
1225 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1226 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1228 svm_set_efer(&svm->vcpu, 0);
1229 save->dr6 = 0xffff0ff0;
1230 kvm_set_rflags(&svm->vcpu, 2);
1231 save->rip = 0x0000fff0;
1232 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1235 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1236 * It also updates the guest-visible cr0 value.
1238 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1239 kvm_mmu_reset_context(&svm->vcpu);
1241 save->cr4 = X86_CR4_PAE;
1245 /* Setup VMCB for Nested Paging */
1246 control->nested_ctl = 1;
1247 clr_intercept(svm, INTERCEPT_INVLPG);
1248 clr_exception_intercept(svm, PF_VECTOR);
1249 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1250 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1251 save->g_pat = svm->vcpu.arch.pat;
1255 svm->asid_generation = 0;
1257 svm->nested.vmcb = 0;
1258 svm->vcpu.arch.hflags = 0;
1260 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1261 control->pause_filter_count = 3000;
1262 set_intercept(svm, INTERCEPT_PAUSE);
1266 avic_init_vmcb(svm);
1268 mark_all_dirty(svm->vmcb);
1274 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1276 u64 *avic_physical_id_table;
1277 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1279 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1282 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1284 return &avic_physical_id_table[index];
1289 * AVIC hardware walks the nested page table to check permissions,
1290 * but does not use the SPA address specified in the leaf page
1291 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1292 * field of the VMCB. Therefore, we set up the
1293 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1295 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1297 struct kvm *kvm = vcpu->kvm;
1300 if (kvm->arch.apic_access_page_done)
1303 ret = x86_set_memory_region(kvm,
1304 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1305 APIC_DEFAULT_PHYS_BASE,
1310 kvm->arch.apic_access_page_done = true;
1314 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1317 u64 *entry, new_entry;
1318 int id = vcpu->vcpu_id;
1319 struct vcpu_svm *svm = to_svm(vcpu);
1321 ret = avic_init_access_page(vcpu);
1325 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1328 if (!svm->vcpu.arch.apic->regs)
1331 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1333 /* Setting AVIC backing page address in the phy APIC ID table */
1334 entry = avic_get_physical_id_entry(vcpu, id);
1338 new_entry = READ_ONCE(*entry);
1339 new_entry = (page_to_phys(svm->avic_backing_page) &
1340 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1341 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1342 WRITE_ONCE(*entry, new_entry);
1344 svm->avic_physical_id_cache = entry;
1349 static inline int avic_get_next_vm_id(void)
1353 spin_lock(&avic_vm_id_lock);
1355 /* AVIC VM ID is one-based. */
1356 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1357 if (id <= AVIC_VM_ID_MASK)
1358 __set_bit(id, avic_vm_id_bitmap);
1362 spin_unlock(&avic_vm_id_lock);
1366 static inline int avic_free_vm_id(int id)
1368 if (id <= 0 || id > AVIC_VM_ID_MASK)
1371 spin_lock(&avic_vm_id_lock);
1372 __clear_bit(id, avic_vm_id_bitmap);
1373 spin_unlock(&avic_vm_id_lock);
1377 static void avic_vm_destroy(struct kvm *kvm)
1379 unsigned long flags;
1380 struct kvm_arch *vm_data = &kvm->arch;
1382 avic_free_vm_id(vm_data->avic_vm_id);
1384 if (vm_data->avic_logical_id_table_page)
1385 __free_page(vm_data->avic_logical_id_table_page);
1386 if (vm_data->avic_physical_id_table_page)
1387 __free_page(vm_data->avic_physical_id_table_page);
1389 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1390 hash_del(&vm_data->hnode);
1391 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1394 static int avic_vm_init(struct kvm *kvm)
1396 unsigned long flags;
1397 int vm_id, err = -ENOMEM;
1398 struct kvm_arch *vm_data = &kvm->arch;
1399 struct page *p_page;
1400 struct page *l_page;
1405 vm_id = avic_get_next_vm_id();
1408 vm_data->avic_vm_id = (u32)vm_id;
1410 /* Allocating physical APIC ID table (4KB) */
1411 p_page = alloc_page(GFP_KERNEL);
1415 vm_data->avic_physical_id_table_page = p_page;
1416 clear_page(page_address(p_page));
1418 /* Allocating logical APIC ID table (4KB) */
1419 l_page = alloc_page(GFP_KERNEL);
1423 vm_data->avic_logical_id_table_page = l_page;
1424 clear_page(page_address(l_page));
1426 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1427 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1428 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1433 avic_vm_destroy(kvm);
1438 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1441 unsigned long flags;
1442 struct amd_svm_iommu_ir *ir;
1443 struct vcpu_svm *svm = to_svm(vcpu);
1445 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1449 * Here, we go through the per-vcpu ir_list to update all existing
1450 * interrupt remapping table entry targeting this vcpu.
1452 spin_lock_irqsave(&svm->ir_list_lock, flags);
1454 if (list_empty(&svm->ir_list))
1457 list_for_each_entry(ir, &svm->ir_list, node) {
1458 ret = amd_iommu_update_ga(cpu, r, ir->data);
1463 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1467 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1470 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1471 int h_physical_id = kvm_cpu_get_apicid(cpu);
1472 struct vcpu_svm *svm = to_svm(vcpu);
1474 if (!kvm_vcpu_apicv_active(vcpu))
1477 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1480 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1481 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1483 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1484 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1486 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1487 if (svm->avic_is_running)
1488 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1490 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1491 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1492 svm->avic_is_running);
1495 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1498 struct vcpu_svm *svm = to_svm(vcpu);
1500 if (!kvm_vcpu_apicv_active(vcpu))
1503 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1504 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1505 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1507 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1508 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1512 * This function is called during VCPU halt/unhalt.
1514 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1516 struct vcpu_svm *svm = to_svm(vcpu);
1518 svm->avic_is_running = is_run;
1520 avic_vcpu_load(vcpu, vcpu->cpu);
1522 avic_vcpu_put(vcpu);
1525 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1527 struct vcpu_svm *svm = to_svm(vcpu);
1532 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1533 MSR_IA32_APICBASE_ENABLE;
1534 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1535 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1539 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1540 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1542 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1543 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1546 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1548 struct vcpu_svm *svm;
1550 struct page *msrpm_pages;
1551 struct page *hsave_page;
1552 struct page *nested_msrpm_pages;
1555 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1561 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1566 page = alloc_page(GFP_KERNEL);
1570 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1574 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1575 if (!nested_msrpm_pages)
1578 hsave_page = alloc_page(GFP_KERNEL);
1583 err = avic_init_backing_page(&svm->vcpu);
1587 INIT_LIST_HEAD(&svm->ir_list);
1588 spin_lock_init(&svm->ir_list_lock);
1591 /* We initialize this flag to true to make sure that the is_running
1592 * bit would be set the first time the vcpu is loaded.
1594 svm->avic_is_running = true;
1596 svm->nested.hsave = page_address(hsave_page);
1598 svm->msrpm = page_address(msrpm_pages);
1599 svm_vcpu_init_msrpm(svm->msrpm);
1601 svm->nested.msrpm = page_address(nested_msrpm_pages);
1602 svm_vcpu_init_msrpm(svm->nested.msrpm);
1604 svm->vmcb = page_address(page);
1605 clear_page(svm->vmcb);
1606 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1607 svm->asid_generation = 0;
1610 svm_init_osvw(&svm->vcpu);
1615 __free_page(hsave_page);
1617 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1619 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1623 kvm_vcpu_uninit(&svm->vcpu);
1625 kmem_cache_free(kvm_vcpu_cache, svm);
1627 return ERR_PTR(err);
1630 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1632 struct vcpu_svm *svm = to_svm(vcpu);
1634 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1635 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1636 __free_page(virt_to_page(svm->nested.hsave));
1637 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1638 kvm_vcpu_uninit(vcpu);
1639 kmem_cache_free(kvm_vcpu_cache, svm);
1642 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1644 struct vcpu_svm *svm = to_svm(vcpu);
1647 if (unlikely(cpu != vcpu->cpu)) {
1648 svm->asid_generation = 0;
1649 mark_all_dirty(svm->vmcb);
1652 #ifdef CONFIG_X86_64
1653 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1655 savesegment(fs, svm->host.fs);
1656 savesegment(gs, svm->host.gs);
1657 svm->host.ldt = kvm_read_ldt();
1659 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1660 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1662 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1663 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1664 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1665 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1666 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1669 /* This assumes that the kernel never uses MSR_TSC_AUX */
1670 if (static_cpu_has(X86_FEATURE_RDTSCP))
1671 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1673 avic_vcpu_load(vcpu, cpu);
1676 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1678 struct vcpu_svm *svm = to_svm(vcpu);
1681 avic_vcpu_put(vcpu);
1683 ++vcpu->stat.host_state_reload;
1684 kvm_load_ldt(svm->host.ldt);
1685 #ifdef CONFIG_X86_64
1686 loadsegment(fs, svm->host.fs);
1687 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1688 load_gs_index(svm->host.gs);
1690 #ifdef CONFIG_X86_32_LAZY_GS
1691 loadsegment(gs, svm->host.gs);
1694 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1695 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1698 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1700 avic_set_running(vcpu, false);
1703 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1705 avic_set_running(vcpu, true);
1708 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1710 return to_svm(vcpu)->vmcb->save.rflags;
1713 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1716 * Any change of EFLAGS.VM is accompanied by a reload of SS
1717 * (caused by either a task switch or an inter-privilege IRET),
1718 * so we do not need to update the CPL here.
1720 to_svm(vcpu)->vmcb->save.rflags = rflags;
1723 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1728 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1731 case VCPU_EXREG_PDPTR:
1732 BUG_ON(!npt_enabled);
1733 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1740 static void svm_set_vintr(struct vcpu_svm *svm)
1742 set_intercept(svm, INTERCEPT_VINTR);
1745 static void svm_clear_vintr(struct vcpu_svm *svm)
1747 clr_intercept(svm, INTERCEPT_VINTR);
1750 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1752 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1755 case VCPU_SREG_CS: return &save->cs;
1756 case VCPU_SREG_DS: return &save->ds;
1757 case VCPU_SREG_ES: return &save->es;
1758 case VCPU_SREG_FS: return &save->fs;
1759 case VCPU_SREG_GS: return &save->gs;
1760 case VCPU_SREG_SS: return &save->ss;
1761 case VCPU_SREG_TR: return &save->tr;
1762 case VCPU_SREG_LDTR: return &save->ldtr;
1768 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1770 struct vmcb_seg *s = svm_seg(vcpu, seg);
1775 static void svm_get_segment(struct kvm_vcpu *vcpu,
1776 struct kvm_segment *var, int seg)
1778 struct vmcb_seg *s = svm_seg(vcpu, seg);
1780 var->base = s->base;
1781 var->limit = s->limit;
1782 var->selector = s->selector;
1783 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1784 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1785 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1786 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1787 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1788 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1789 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1792 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1793 * However, the SVM spec states that the G bit is not observed by the
1794 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1795 * So let's synthesize a legal G bit for all segments, this helps
1796 * running KVM nested. It also helps cross-vendor migration, because
1797 * Intel's vmentry has a check on the 'G' bit.
1799 var->g = s->limit > 0xfffff;
1802 * AMD's VMCB does not have an explicit unusable field, so emulate it
1803 * for cross vendor migration purposes by "not present"
1805 var->unusable = !var->present || (var->type == 0);
1810 * Work around a bug where the busy flag in the tr selector
1820 * The accessed bit must always be set in the segment
1821 * descriptor cache, although it can be cleared in the
1822 * descriptor, the cached bit always remains at 1. Since
1823 * Intel has a check on this, set it here to support
1824 * cross-vendor migration.
1831 * On AMD CPUs sometimes the DB bit in the segment
1832 * descriptor is left as 1, although the whole segment has
1833 * been made unusable. Clear it here to pass an Intel VMX
1834 * entry check when cross vendor migrating.
1838 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1843 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1845 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1850 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1852 struct vcpu_svm *svm = to_svm(vcpu);
1854 dt->size = svm->vmcb->save.idtr.limit;
1855 dt->address = svm->vmcb->save.idtr.base;
1858 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1860 struct vcpu_svm *svm = to_svm(vcpu);
1862 svm->vmcb->save.idtr.limit = dt->size;
1863 svm->vmcb->save.idtr.base = dt->address ;
1864 mark_dirty(svm->vmcb, VMCB_DT);
1867 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1869 struct vcpu_svm *svm = to_svm(vcpu);
1871 dt->size = svm->vmcb->save.gdtr.limit;
1872 dt->address = svm->vmcb->save.gdtr.base;
1875 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1877 struct vcpu_svm *svm = to_svm(vcpu);
1879 svm->vmcb->save.gdtr.limit = dt->size;
1880 svm->vmcb->save.gdtr.base = dt->address ;
1881 mark_dirty(svm->vmcb, VMCB_DT);
1884 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1888 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1892 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1896 static void update_cr0_intercept(struct vcpu_svm *svm)
1898 ulong gcr0 = svm->vcpu.arch.cr0;
1899 u64 *hcr0 = &svm->vmcb->save.cr0;
1901 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1902 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1904 mark_dirty(svm->vmcb, VMCB_CR);
1906 if (gcr0 == *hcr0) {
1907 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1908 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1910 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1911 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1915 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1917 struct vcpu_svm *svm = to_svm(vcpu);
1919 #ifdef CONFIG_X86_64
1920 if (vcpu->arch.efer & EFER_LME) {
1921 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1922 vcpu->arch.efer |= EFER_LMA;
1923 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1926 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1927 vcpu->arch.efer &= ~EFER_LMA;
1928 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1932 vcpu->arch.cr0 = cr0;
1935 cr0 |= X86_CR0_PG | X86_CR0_WP;
1938 * re-enable caching here because the QEMU bios
1939 * does not do it - this results in some delay at
1942 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1943 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1944 svm->vmcb->save.cr0 = cr0;
1945 mark_dirty(svm->vmcb, VMCB_CR);
1946 update_cr0_intercept(svm);
1949 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1951 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1952 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1954 if (cr4 & X86_CR4_VMXE)
1957 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1958 svm_flush_tlb(vcpu);
1960 vcpu->arch.cr4 = cr4;
1963 cr4 |= host_cr4_mce;
1964 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1965 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1969 static void svm_set_segment(struct kvm_vcpu *vcpu,
1970 struct kvm_segment *var, int seg)
1972 struct vcpu_svm *svm = to_svm(vcpu);
1973 struct vmcb_seg *s = svm_seg(vcpu, seg);
1975 s->base = var->base;
1976 s->limit = var->limit;
1977 s->selector = var->selector;
1981 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1982 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1983 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1984 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1985 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1986 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1987 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1988 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1992 * This is always accurate, except if SYSRET returned to a segment
1993 * with SS.DPL != 3. Intel does not have this quirk, and always
1994 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1995 * would entail passing the CPL to userspace and back.
1997 if (seg == VCPU_SREG_SS)
1998 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2000 mark_dirty(svm->vmcb, VMCB_SEG);
2003 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2005 struct vcpu_svm *svm = to_svm(vcpu);
2007 clr_exception_intercept(svm, BP_VECTOR);
2009 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2010 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2011 set_exception_intercept(svm, BP_VECTOR);
2013 vcpu->guest_debug = 0;
2016 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2018 if (sd->next_asid > sd->max_asid) {
2019 ++sd->asid_generation;
2021 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2024 svm->asid_generation = sd->asid_generation;
2025 svm->vmcb->control.asid = sd->next_asid++;
2027 mark_dirty(svm->vmcb, VMCB_ASID);
2030 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2032 return to_svm(vcpu)->vmcb->save.dr6;
2035 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2037 struct vcpu_svm *svm = to_svm(vcpu);
2039 svm->vmcb->save.dr6 = value;
2040 mark_dirty(svm->vmcb, VMCB_DR);
2043 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2045 struct vcpu_svm *svm = to_svm(vcpu);
2047 get_debugreg(vcpu->arch.db[0], 0);
2048 get_debugreg(vcpu->arch.db[1], 1);
2049 get_debugreg(vcpu->arch.db[2], 2);
2050 get_debugreg(vcpu->arch.db[3], 3);
2051 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2052 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2054 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2055 set_dr_intercepts(svm);
2058 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2060 struct vcpu_svm *svm = to_svm(vcpu);
2062 svm->vmcb->save.dr7 = value;
2063 mark_dirty(svm->vmcb, VMCB_DR);
2066 static int pf_interception(struct vcpu_svm *svm)
2068 u64 fault_address = svm->vmcb->control.exit_info_2;
2072 switch (svm->apf_reason) {
2074 error_code = svm->vmcb->control.exit_info_1;
2076 trace_kvm_page_fault(fault_address, error_code);
2077 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2078 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2079 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2080 svm->vmcb->control.insn_bytes,
2081 svm->vmcb->control.insn_len);
2083 case KVM_PV_REASON_PAGE_NOT_PRESENT:
2084 svm->apf_reason = 0;
2085 local_irq_disable();
2086 kvm_async_pf_task_wait(fault_address);
2089 case KVM_PV_REASON_PAGE_READY:
2090 svm->apf_reason = 0;
2091 local_irq_disable();
2092 kvm_async_pf_task_wake(fault_address);
2099 static int db_interception(struct vcpu_svm *svm)
2101 struct kvm_run *kvm_run = svm->vcpu.run;
2103 if (!(svm->vcpu.guest_debug &
2104 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2105 !svm->nmi_singlestep) {
2106 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2110 if (svm->nmi_singlestep) {
2111 svm->nmi_singlestep = false;
2112 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2113 svm->vmcb->save.rflags &=
2114 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2117 if (svm->vcpu.guest_debug &
2118 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2119 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2120 kvm_run->debug.arch.pc =
2121 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2122 kvm_run->debug.arch.exception = DB_VECTOR;
2129 static int bp_interception(struct vcpu_svm *svm)
2131 struct kvm_run *kvm_run = svm->vcpu.run;
2133 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2134 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2135 kvm_run->debug.arch.exception = BP_VECTOR;
2139 static int ud_interception(struct vcpu_svm *svm)
2143 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2144 if (er != EMULATE_DONE)
2145 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2149 static int ac_interception(struct vcpu_svm *svm)
2151 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2155 static bool is_erratum_383(void)
2160 if (!erratum_383_found)
2163 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2167 /* Bit 62 may or may not be set for this mce */
2168 value &= ~(1ULL << 62);
2170 if (value != 0xb600000000010015ULL)
2173 /* Clear MCi_STATUS registers */
2174 for (i = 0; i < 6; ++i)
2175 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2177 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2181 value &= ~(1ULL << 2);
2182 low = lower_32_bits(value);
2183 high = upper_32_bits(value);
2185 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2188 /* Flush tlb to evict multi-match entries */
2194 static void svm_handle_mce(struct vcpu_svm *svm)
2196 if (is_erratum_383()) {
2198 * Erratum 383 triggered. Guest state is corrupt so kill the
2201 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2203 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2209 * On an #MC intercept the MCE handler is not called automatically in
2210 * the host. So do it by hand here.
2214 /* not sure if we ever come back to this point */
2219 static int mc_interception(struct vcpu_svm *svm)
2224 static int shutdown_interception(struct vcpu_svm *svm)
2226 struct kvm_run *kvm_run = svm->vcpu.run;
2229 * VMCB is undefined after a SHUTDOWN intercept
2230 * so reinitialize it.
2232 clear_page(svm->vmcb);
2235 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2239 static int io_interception(struct vcpu_svm *svm)
2241 struct kvm_vcpu *vcpu = &svm->vcpu;
2242 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2243 int size, in, string;
2246 ++svm->vcpu.stat.io_exits;
2247 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2248 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2250 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2252 port = io_info >> 16;
2253 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2254 svm->next_rip = svm->vmcb->control.exit_info_2;
2255 skip_emulated_instruction(&svm->vcpu);
2257 return in ? kvm_fast_pio_in(vcpu, size, port)
2258 : kvm_fast_pio_out(vcpu, size, port);
2261 static int nmi_interception(struct vcpu_svm *svm)
2266 static int intr_interception(struct vcpu_svm *svm)
2268 ++svm->vcpu.stat.irq_exits;
2272 static int nop_on_interception(struct vcpu_svm *svm)
2277 static int halt_interception(struct vcpu_svm *svm)
2279 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2280 return kvm_emulate_halt(&svm->vcpu);
2283 static int vmmcall_interception(struct vcpu_svm *svm)
2285 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2286 return kvm_emulate_hypercall(&svm->vcpu);
2289 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2291 struct vcpu_svm *svm = to_svm(vcpu);
2293 return svm->nested.nested_cr3;
2296 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2298 struct vcpu_svm *svm = to_svm(vcpu);
2299 u64 cr3 = svm->nested.nested_cr3;
2303 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2304 offset_in_page(cr3) + index * 8, 8);
2310 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2313 struct vcpu_svm *svm = to_svm(vcpu);
2315 svm->vmcb->control.nested_cr3 = root;
2316 mark_dirty(svm->vmcb, VMCB_NPT);
2317 svm_flush_tlb(vcpu);
2320 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2321 struct x86_exception *fault)
2323 struct vcpu_svm *svm = to_svm(vcpu);
2325 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2327 * TODO: track the cause of the nested page fault, and
2328 * correctly fill in the high bits of exit_info_1.
2330 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2331 svm->vmcb->control.exit_code_hi = 0;
2332 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2333 svm->vmcb->control.exit_info_2 = fault->address;
2336 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2337 svm->vmcb->control.exit_info_1 |= fault->error_code;
2340 * The present bit is always zero for page structure faults on real
2343 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2344 svm->vmcb->control.exit_info_1 &= ~1;
2346 nested_svm_vmexit(svm);
2349 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2351 WARN_ON(mmu_is_nested(vcpu));
2352 kvm_init_shadow_mmu(vcpu);
2353 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2354 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2355 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2356 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2357 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2358 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2359 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2362 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2364 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2367 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2369 if (!(svm->vcpu.arch.efer & EFER_SVME)
2370 || !is_paging(&svm->vcpu)) {
2371 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2375 if (svm->vmcb->save.cpl) {
2376 kvm_inject_gp(&svm->vcpu, 0);
2383 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2384 bool has_error_code, u32 error_code)
2388 if (!is_guest_mode(&svm->vcpu))
2391 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2392 svm->vmcb->control.exit_code_hi = 0;
2393 svm->vmcb->control.exit_info_1 = error_code;
2394 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2396 vmexit = nested_svm_intercept(svm);
2397 if (vmexit == NESTED_EXIT_DONE)
2398 svm->nested.exit_required = true;
2403 /* This function returns true if it is save to enable the irq window */
2404 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2406 if (!is_guest_mode(&svm->vcpu))
2409 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2412 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2416 * if vmexit was already requested (by intercepted exception
2417 * for instance) do not overwrite it with "external interrupt"
2420 if (svm->nested.exit_required)
2423 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2424 svm->vmcb->control.exit_info_1 = 0;
2425 svm->vmcb->control.exit_info_2 = 0;
2427 if (svm->nested.intercept & 1ULL) {
2429 * The #vmexit can't be emulated here directly because this
2430 * code path runs with irqs and preemption disabled. A
2431 * #vmexit emulation might sleep. Only signal request for
2434 svm->nested.exit_required = true;
2435 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2442 /* This function returns true if it is save to enable the nmi window */
2443 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2445 if (!is_guest_mode(&svm->vcpu))
2448 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2451 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2452 svm->nested.exit_required = true;
2457 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2463 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2464 if (is_error_page(page))
2472 kvm_inject_gp(&svm->vcpu, 0);
2477 static void nested_svm_unmap(struct page *page)
2480 kvm_release_page_dirty(page);
2483 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2485 unsigned port, size, iopm_len;
2490 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2491 return NESTED_EXIT_HOST;
2493 port = svm->vmcb->control.exit_info_1 >> 16;
2494 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2495 SVM_IOIO_SIZE_SHIFT;
2496 gpa = svm->nested.vmcb_iopm + (port / 8);
2497 start_bit = port % 8;
2498 iopm_len = (start_bit + size > 8) ? 2 : 1;
2499 mask = (0xf >> (4 - size)) << start_bit;
2502 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2503 return NESTED_EXIT_DONE;
2505 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2508 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2510 u32 offset, msr, value;
2513 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2514 return NESTED_EXIT_HOST;
2516 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2517 offset = svm_msrpm_offset(msr);
2518 write = svm->vmcb->control.exit_info_1 & 1;
2519 mask = 1 << ((2 * (msr & 0xf)) + write);
2521 if (offset == MSR_INVALID)
2522 return NESTED_EXIT_DONE;
2524 /* Offset is in 32 bit units but need in 8 bit units */
2527 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2528 return NESTED_EXIT_DONE;
2530 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2533 static int nested_svm_exit_special(struct vcpu_svm *svm)
2535 u32 exit_code = svm->vmcb->control.exit_code;
2537 switch (exit_code) {
2540 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2541 return NESTED_EXIT_HOST;
2543 /* For now we are always handling NPFs when using them */
2545 return NESTED_EXIT_HOST;
2547 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2548 /* When we're shadowing, trap PFs, but not async PF */
2549 if (!npt_enabled && svm->apf_reason == 0)
2550 return NESTED_EXIT_HOST;
2556 return NESTED_EXIT_CONTINUE;
2560 * If this function returns true, this #vmexit was already handled
2562 static int nested_svm_intercept(struct vcpu_svm *svm)
2564 u32 exit_code = svm->vmcb->control.exit_code;
2565 int vmexit = NESTED_EXIT_HOST;
2567 switch (exit_code) {
2569 vmexit = nested_svm_exit_handled_msr(svm);
2572 vmexit = nested_svm_intercept_ioio(svm);
2574 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2575 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2576 if (svm->nested.intercept_cr & bit)
2577 vmexit = NESTED_EXIT_DONE;
2580 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2581 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2582 if (svm->nested.intercept_dr & bit)
2583 vmexit = NESTED_EXIT_DONE;
2586 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2587 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2588 if (svm->nested.intercept_exceptions & excp_bits)
2589 vmexit = NESTED_EXIT_DONE;
2590 /* async page fault always cause vmexit */
2591 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2592 svm->apf_reason != 0)
2593 vmexit = NESTED_EXIT_DONE;
2596 case SVM_EXIT_ERR: {
2597 vmexit = NESTED_EXIT_DONE;
2601 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2602 if (svm->nested.intercept & exit_bits)
2603 vmexit = NESTED_EXIT_DONE;
2610 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2614 vmexit = nested_svm_intercept(svm);
2616 if (vmexit == NESTED_EXIT_DONE)
2617 nested_svm_vmexit(svm);
2622 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2624 struct vmcb_control_area *dst = &dst_vmcb->control;
2625 struct vmcb_control_area *from = &from_vmcb->control;
2627 dst->intercept_cr = from->intercept_cr;
2628 dst->intercept_dr = from->intercept_dr;
2629 dst->intercept_exceptions = from->intercept_exceptions;
2630 dst->intercept = from->intercept;
2631 dst->iopm_base_pa = from->iopm_base_pa;
2632 dst->msrpm_base_pa = from->msrpm_base_pa;
2633 dst->tsc_offset = from->tsc_offset;
2634 dst->asid = from->asid;
2635 dst->tlb_ctl = from->tlb_ctl;
2636 dst->int_ctl = from->int_ctl;
2637 dst->int_vector = from->int_vector;
2638 dst->int_state = from->int_state;
2639 dst->exit_code = from->exit_code;
2640 dst->exit_code_hi = from->exit_code_hi;
2641 dst->exit_info_1 = from->exit_info_1;
2642 dst->exit_info_2 = from->exit_info_2;
2643 dst->exit_int_info = from->exit_int_info;
2644 dst->exit_int_info_err = from->exit_int_info_err;
2645 dst->nested_ctl = from->nested_ctl;
2646 dst->event_inj = from->event_inj;
2647 dst->event_inj_err = from->event_inj_err;
2648 dst->nested_cr3 = from->nested_cr3;
2649 dst->lbr_ctl = from->lbr_ctl;
2652 static int nested_svm_vmexit(struct vcpu_svm *svm)
2654 struct vmcb *nested_vmcb;
2655 struct vmcb *hsave = svm->nested.hsave;
2656 struct vmcb *vmcb = svm->vmcb;
2659 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2660 vmcb->control.exit_info_1,
2661 vmcb->control.exit_info_2,
2662 vmcb->control.exit_int_info,
2663 vmcb->control.exit_int_info_err,
2666 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2670 /* Exit Guest-Mode */
2671 leave_guest_mode(&svm->vcpu);
2672 svm->nested.vmcb = 0;
2674 /* Give the current vmcb to the guest */
2677 nested_vmcb->save.es = vmcb->save.es;
2678 nested_vmcb->save.cs = vmcb->save.cs;
2679 nested_vmcb->save.ss = vmcb->save.ss;
2680 nested_vmcb->save.ds = vmcb->save.ds;
2681 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2682 nested_vmcb->save.idtr = vmcb->save.idtr;
2683 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2684 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2685 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2686 nested_vmcb->save.cr2 = vmcb->save.cr2;
2687 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2688 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2689 nested_vmcb->save.rip = vmcb->save.rip;
2690 nested_vmcb->save.rsp = vmcb->save.rsp;
2691 nested_vmcb->save.rax = vmcb->save.rax;
2692 nested_vmcb->save.dr7 = vmcb->save.dr7;
2693 nested_vmcb->save.dr6 = vmcb->save.dr6;
2694 nested_vmcb->save.cpl = vmcb->save.cpl;
2696 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2697 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2698 nested_vmcb->control.int_state = vmcb->control.int_state;
2699 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2700 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2701 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2702 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2703 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2704 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2706 if (svm->nrips_enabled)
2707 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2710 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2711 * to make sure that we do not lose injected events. So check event_inj
2712 * here and copy it to exit_int_info if it is valid.
2713 * Exit_int_info and event_inj can't be both valid because the case
2714 * below only happens on a VMRUN instruction intercept which has
2715 * no valid exit_int_info set.
2717 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2718 struct vmcb_control_area *nc = &nested_vmcb->control;
2720 nc->exit_int_info = vmcb->control.event_inj;
2721 nc->exit_int_info_err = vmcb->control.event_inj_err;
2724 nested_vmcb->control.tlb_ctl = 0;
2725 nested_vmcb->control.event_inj = 0;
2726 nested_vmcb->control.event_inj_err = 0;
2728 /* We always set V_INTR_MASKING and remember the old value in hflags */
2729 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2730 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2732 /* Restore the original control entries */
2733 copy_vmcb_control_area(vmcb, hsave);
2735 kvm_clear_exception_queue(&svm->vcpu);
2736 kvm_clear_interrupt_queue(&svm->vcpu);
2738 svm->nested.nested_cr3 = 0;
2740 /* Restore selected save entries */
2741 svm->vmcb->save.es = hsave->save.es;
2742 svm->vmcb->save.cs = hsave->save.cs;
2743 svm->vmcb->save.ss = hsave->save.ss;
2744 svm->vmcb->save.ds = hsave->save.ds;
2745 svm->vmcb->save.gdtr = hsave->save.gdtr;
2746 svm->vmcb->save.idtr = hsave->save.idtr;
2747 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2748 svm_set_efer(&svm->vcpu, hsave->save.efer);
2749 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2750 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2752 svm->vmcb->save.cr3 = hsave->save.cr3;
2753 svm->vcpu.arch.cr3 = hsave->save.cr3;
2755 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2757 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2758 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2759 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2760 svm->vmcb->save.dr7 = 0;
2761 svm->vmcb->save.cpl = 0;
2762 svm->vmcb->control.exit_int_info = 0;
2764 mark_all_dirty(svm->vmcb);
2766 nested_svm_unmap(page);
2768 nested_svm_uninit_mmu_context(&svm->vcpu);
2769 kvm_mmu_reset_context(&svm->vcpu);
2770 kvm_mmu_load(&svm->vcpu);
2775 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2778 * This function merges the msr permission bitmaps of kvm and the
2779 * nested vmcb. It is optimized in that it only merges the parts where
2780 * the kvm msr permission bitmap may contain zero bits
2784 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2787 for (i = 0; i < MSRPM_OFFSETS; i++) {
2791 if (msrpm_offsets[i] == 0xffffffff)
2794 p = msrpm_offsets[i];
2795 offset = svm->nested.vmcb_msrpm + (p * 4);
2797 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2800 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2803 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2808 static bool nested_vmcb_checks(struct vmcb *vmcb)
2810 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2813 if (vmcb->control.asid == 0)
2816 if (vmcb->control.nested_ctl && !npt_enabled)
2822 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2824 struct vmcb *nested_vmcb;
2825 struct vmcb *hsave = svm->nested.hsave;
2826 struct vmcb *vmcb = svm->vmcb;
2830 vmcb_gpa = svm->vmcb->save.rax;
2832 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2836 if (!nested_vmcb_checks(nested_vmcb)) {
2837 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2838 nested_vmcb->control.exit_code_hi = 0;
2839 nested_vmcb->control.exit_info_1 = 0;
2840 nested_vmcb->control.exit_info_2 = 0;
2842 nested_svm_unmap(page);
2847 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2848 nested_vmcb->save.rip,
2849 nested_vmcb->control.int_ctl,
2850 nested_vmcb->control.event_inj,
2851 nested_vmcb->control.nested_ctl);
2853 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2854 nested_vmcb->control.intercept_cr >> 16,
2855 nested_vmcb->control.intercept_exceptions,
2856 nested_vmcb->control.intercept);
2858 /* Clear internal status */
2859 kvm_clear_exception_queue(&svm->vcpu);
2860 kvm_clear_interrupt_queue(&svm->vcpu);
2863 * Save the old vmcb, so we don't need to pick what we save, but can
2864 * restore everything when a VMEXIT occurs
2866 hsave->save.es = vmcb->save.es;
2867 hsave->save.cs = vmcb->save.cs;
2868 hsave->save.ss = vmcb->save.ss;
2869 hsave->save.ds = vmcb->save.ds;
2870 hsave->save.gdtr = vmcb->save.gdtr;
2871 hsave->save.idtr = vmcb->save.idtr;
2872 hsave->save.efer = svm->vcpu.arch.efer;
2873 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2874 hsave->save.cr4 = svm->vcpu.arch.cr4;
2875 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2876 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2877 hsave->save.rsp = vmcb->save.rsp;
2878 hsave->save.rax = vmcb->save.rax;
2880 hsave->save.cr3 = vmcb->save.cr3;
2882 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2884 copy_vmcb_control_area(hsave, vmcb);
2886 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2887 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2889 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2891 if (nested_vmcb->control.nested_ctl) {
2892 kvm_mmu_unload(&svm->vcpu);
2893 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2894 nested_svm_init_mmu_context(&svm->vcpu);
2897 /* Load the nested guest state */
2898 svm->vmcb->save.es = nested_vmcb->save.es;
2899 svm->vmcb->save.cs = nested_vmcb->save.cs;
2900 svm->vmcb->save.ss = nested_vmcb->save.ss;
2901 svm->vmcb->save.ds = nested_vmcb->save.ds;
2902 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2903 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2904 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2905 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2906 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2907 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2909 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2910 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2912 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2914 /* Guest paging mode is active - reset mmu */
2915 kvm_mmu_reset_context(&svm->vcpu);
2917 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2918 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2919 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2920 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2922 /* In case we don't even reach vcpu_run, the fields are not updated */
2923 svm->vmcb->save.rax = nested_vmcb->save.rax;
2924 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2925 svm->vmcb->save.rip = nested_vmcb->save.rip;
2926 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2927 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2928 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2930 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2931 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2933 /* cache intercepts */
2934 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2935 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2936 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2937 svm->nested.intercept = nested_vmcb->control.intercept;
2939 svm_flush_tlb(&svm->vcpu);
2940 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2941 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2942 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2944 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2946 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2947 /* We only want the cr8 intercept bits of the guest */
2948 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2949 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2952 /* We don't want to see VMMCALLs from a nested guest */
2953 clr_intercept(svm, INTERCEPT_VMMCALL);
2955 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2956 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2957 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2958 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2959 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2960 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2962 nested_svm_unmap(page);
2964 /* Enter Guest-Mode */
2965 enter_guest_mode(&svm->vcpu);
2968 * Merge guest and host intercepts - must be called with vcpu in
2969 * guest-mode to take affect here
2971 recalc_intercepts(svm);
2973 svm->nested.vmcb = vmcb_gpa;
2977 mark_all_dirty(svm->vmcb);
2982 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2984 to_vmcb->save.fs = from_vmcb->save.fs;
2985 to_vmcb->save.gs = from_vmcb->save.gs;
2986 to_vmcb->save.tr = from_vmcb->save.tr;
2987 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2988 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2989 to_vmcb->save.star = from_vmcb->save.star;
2990 to_vmcb->save.lstar = from_vmcb->save.lstar;
2991 to_vmcb->save.cstar = from_vmcb->save.cstar;
2992 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2993 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2994 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2995 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2998 static int vmload_interception(struct vcpu_svm *svm)
3000 struct vmcb *nested_vmcb;
3003 if (nested_svm_check_permissions(svm))
3006 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3010 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3011 skip_emulated_instruction(&svm->vcpu);
3013 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3014 nested_svm_unmap(page);
3019 static int vmsave_interception(struct vcpu_svm *svm)
3021 struct vmcb *nested_vmcb;
3024 if (nested_svm_check_permissions(svm))
3027 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3031 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3032 skip_emulated_instruction(&svm->vcpu);
3034 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3035 nested_svm_unmap(page);
3040 static int vmrun_interception(struct vcpu_svm *svm)
3042 if (nested_svm_check_permissions(svm))
3045 /* Save rip after vmrun instruction */
3046 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3048 if (!nested_svm_vmrun(svm))
3051 if (!nested_svm_vmrun_msrpm(svm))
3058 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3059 svm->vmcb->control.exit_code_hi = 0;
3060 svm->vmcb->control.exit_info_1 = 0;
3061 svm->vmcb->control.exit_info_2 = 0;
3063 nested_svm_vmexit(svm);
3068 static int stgi_interception(struct vcpu_svm *svm)
3070 if (nested_svm_check_permissions(svm))
3073 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3074 skip_emulated_instruction(&svm->vcpu);
3075 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3082 static int clgi_interception(struct vcpu_svm *svm)
3084 if (nested_svm_check_permissions(svm))
3087 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3088 skip_emulated_instruction(&svm->vcpu);
3092 /* After a CLGI no interrupts should come */
3093 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3094 svm_clear_vintr(svm);
3095 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3096 mark_dirty(svm->vmcb, VMCB_INTR);
3102 static int invlpga_interception(struct vcpu_svm *svm)
3104 struct kvm_vcpu *vcpu = &svm->vcpu;
3106 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3107 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3109 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3110 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3112 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3113 skip_emulated_instruction(&svm->vcpu);
3117 static int skinit_interception(struct vcpu_svm *svm)
3119 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3121 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3125 static int wbinvd_interception(struct vcpu_svm *svm)
3127 return kvm_emulate_wbinvd(&svm->vcpu);
3130 static int xsetbv_interception(struct vcpu_svm *svm)
3132 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3133 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3135 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3136 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3137 skip_emulated_instruction(&svm->vcpu);
3143 static int task_switch_interception(struct vcpu_svm *svm)
3147 int int_type = svm->vmcb->control.exit_int_info &
3148 SVM_EXITINTINFO_TYPE_MASK;
3149 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3151 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3153 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3154 bool has_error_code = false;
3157 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3159 if (svm->vmcb->control.exit_info_2 &
3160 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3161 reason = TASK_SWITCH_IRET;
3162 else if (svm->vmcb->control.exit_info_2 &
3163 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3164 reason = TASK_SWITCH_JMP;
3166 reason = TASK_SWITCH_GATE;
3168 reason = TASK_SWITCH_CALL;
3170 if (reason == TASK_SWITCH_GATE) {
3172 case SVM_EXITINTINFO_TYPE_NMI:
3173 svm->vcpu.arch.nmi_injected = false;
3175 case SVM_EXITINTINFO_TYPE_EXEPT:
3176 if (svm->vmcb->control.exit_info_2 &
3177 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3178 has_error_code = true;
3180 (u32)svm->vmcb->control.exit_info_2;
3182 kvm_clear_exception_queue(&svm->vcpu);
3184 case SVM_EXITINTINFO_TYPE_INTR:
3185 kvm_clear_interrupt_queue(&svm->vcpu);
3192 if (reason != TASK_SWITCH_GATE ||
3193 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3194 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3195 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3196 skip_emulated_instruction(&svm->vcpu);
3198 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3201 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3202 has_error_code, error_code) == EMULATE_FAIL) {
3203 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3204 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3205 svm->vcpu.run->internal.ndata = 0;
3211 static int cpuid_interception(struct vcpu_svm *svm)
3213 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3214 return kvm_emulate_cpuid(&svm->vcpu);
3217 static int iret_interception(struct vcpu_svm *svm)
3219 ++svm->vcpu.stat.nmi_window_exits;
3220 clr_intercept(svm, INTERCEPT_IRET);
3221 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3222 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3223 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3227 static int invlpg_interception(struct vcpu_svm *svm)
3229 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3230 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3232 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3233 skip_emulated_instruction(&svm->vcpu);
3237 static int emulate_on_interception(struct vcpu_svm *svm)
3239 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3242 static int rdpmc_interception(struct vcpu_svm *svm)
3246 if (!static_cpu_has(X86_FEATURE_NRIPS))
3247 return emulate_on_interception(svm);
3249 err = kvm_rdpmc(&svm->vcpu);
3250 return kvm_complete_insn_gp(&svm->vcpu, err);
3253 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3256 unsigned long cr0 = svm->vcpu.arch.cr0;
3260 intercept = svm->nested.intercept;
3262 if (!is_guest_mode(&svm->vcpu) ||
3263 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3266 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3267 val &= ~SVM_CR0_SELECTIVE_MASK;
3270 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3271 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3277 #define CR_VALID (1ULL << 63)
3279 static int cr_interception(struct vcpu_svm *svm)
3285 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3286 return emulate_on_interception(svm);
3288 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3289 return emulate_on_interception(svm);
3291 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3292 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3293 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3295 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3298 if (cr >= 16) { /* mov to cr */
3300 val = kvm_register_read(&svm->vcpu, reg);
3303 if (!check_selective_cr0_intercepted(svm, val))
3304 err = kvm_set_cr0(&svm->vcpu, val);
3310 err = kvm_set_cr3(&svm->vcpu, val);
3313 err = kvm_set_cr4(&svm->vcpu, val);
3316 err = kvm_set_cr8(&svm->vcpu, val);
3319 WARN(1, "unhandled write to CR%d", cr);
3320 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3323 } else { /* mov from cr */
3326 val = kvm_read_cr0(&svm->vcpu);
3329 val = svm->vcpu.arch.cr2;
3332 val = kvm_read_cr3(&svm->vcpu);
3335 val = kvm_read_cr4(&svm->vcpu);
3338 val = kvm_get_cr8(&svm->vcpu);
3341 WARN(1, "unhandled read from CR%d", cr);
3342 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3345 kvm_register_write(&svm->vcpu, reg, val);
3347 return kvm_complete_insn_gp(&svm->vcpu, err);
3350 static int dr_interception(struct vcpu_svm *svm)
3355 if (svm->vcpu.guest_debug == 0) {
3357 * No more DR vmexits; force a reload of the debug registers
3358 * and reenter on this instruction. The next vmexit will
3359 * retrieve the full state of the debug registers.
3361 clr_dr_intercepts(svm);
3362 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3366 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3367 return emulate_on_interception(svm);
3369 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3370 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3372 if (dr >= 16) { /* mov to DRn */
3373 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3375 val = kvm_register_read(&svm->vcpu, reg);
3376 kvm_set_dr(&svm->vcpu, dr - 16, val);
3378 if (!kvm_require_dr(&svm->vcpu, dr))
3380 kvm_get_dr(&svm->vcpu, dr, &val);
3381 kvm_register_write(&svm->vcpu, reg, val);
3384 skip_emulated_instruction(&svm->vcpu);
3389 static int cr8_write_interception(struct vcpu_svm *svm)
3391 struct kvm_run *kvm_run = svm->vcpu.run;
3394 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3395 /* instruction emulation calls kvm_set_cr8() */
3396 r = cr_interception(svm);
3397 if (lapic_in_kernel(&svm->vcpu))
3399 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3401 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3405 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3407 struct vcpu_svm *svm = to_svm(vcpu);
3409 switch (msr_info->index) {
3410 case MSR_IA32_TSC: {
3411 msr_info->data = svm->vmcb->control.tsc_offset +
3412 kvm_scale_tsc(vcpu, rdtsc());
3417 msr_info->data = svm->vmcb->save.star;
3419 #ifdef CONFIG_X86_64
3421 msr_info->data = svm->vmcb->save.lstar;
3424 msr_info->data = svm->vmcb->save.cstar;
3426 case MSR_KERNEL_GS_BASE:
3427 msr_info->data = svm->vmcb->save.kernel_gs_base;
3429 case MSR_SYSCALL_MASK:
3430 msr_info->data = svm->vmcb->save.sfmask;
3433 case MSR_IA32_SYSENTER_CS:
3434 msr_info->data = svm->vmcb->save.sysenter_cs;
3436 case MSR_IA32_SYSENTER_EIP:
3437 msr_info->data = svm->sysenter_eip;
3439 case MSR_IA32_SYSENTER_ESP:
3440 msr_info->data = svm->sysenter_esp;
3443 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3445 msr_info->data = svm->tsc_aux;
3448 * Nobody will change the following 5 values in the VMCB so we can
3449 * safely return them on rdmsr. They will always be 0 until LBRV is
3452 case MSR_IA32_DEBUGCTLMSR:
3453 msr_info->data = svm->vmcb->save.dbgctl;
3455 case MSR_IA32_LASTBRANCHFROMIP:
3456 msr_info->data = svm->vmcb->save.br_from;
3458 case MSR_IA32_LASTBRANCHTOIP:
3459 msr_info->data = svm->vmcb->save.br_to;
3461 case MSR_IA32_LASTINTFROMIP:
3462 msr_info->data = svm->vmcb->save.last_excp_from;
3464 case MSR_IA32_LASTINTTOIP:
3465 msr_info->data = svm->vmcb->save.last_excp_to;
3467 case MSR_VM_HSAVE_PA:
3468 msr_info->data = svm->nested.hsave_msr;
3471 msr_info->data = svm->nested.vm_cr_msr;
3473 case MSR_IA32_UCODE_REV:
3474 msr_info->data = 0x01000065;
3476 case MSR_F15H_IC_CFG: {
3480 family = guest_cpuid_family(vcpu);
3481 model = guest_cpuid_model(vcpu);
3483 if (family < 0 || model < 0)
3484 return kvm_get_msr_common(vcpu, msr_info);
3488 if (family == 0x15 &&
3489 (model >= 0x2 && model < 0x20))
3490 msr_info->data = 0x1E;
3494 return kvm_get_msr_common(vcpu, msr_info);
3499 static int rdmsr_interception(struct vcpu_svm *svm)
3501 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3502 struct msr_data msr_info;
3504 msr_info.index = ecx;
3505 msr_info.host_initiated = false;
3506 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3507 trace_kvm_msr_read_ex(ecx);
3508 kvm_inject_gp(&svm->vcpu, 0);
3510 trace_kvm_msr_read(ecx, msr_info.data);
3512 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3513 msr_info.data & 0xffffffff);
3514 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3515 msr_info.data >> 32);
3516 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3517 skip_emulated_instruction(&svm->vcpu);
3522 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3524 struct vcpu_svm *svm = to_svm(vcpu);
3525 int svm_dis, chg_mask;
3527 if (data & ~SVM_VM_CR_VALID_MASK)
3530 chg_mask = SVM_VM_CR_VALID_MASK;
3532 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3533 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3535 svm->nested.vm_cr_msr &= ~chg_mask;
3536 svm->nested.vm_cr_msr |= (data & chg_mask);
3538 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3540 /* check for svm_disable while efer.svme is set */
3541 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3547 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3549 struct vcpu_svm *svm = to_svm(vcpu);
3551 u32 ecx = msr->index;
3552 u64 data = msr->data;
3555 kvm_write_tsc(vcpu, msr);
3558 svm->vmcb->save.star = data;
3560 #ifdef CONFIG_X86_64
3562 svm->vmcb->save.lstar = data;
3565 svm->vmcb->save.cstar = data;
3567 case MSR_KERNEL_GS_BASE:
3568 svm->vmcb->save.kernel_gs_base = data;
3570 case MSR_SYSCALL_MASK:
3571 svm->vmcb->save.sfmask = data;
3574 case MSR_IA32_SYSENTER_CS:
3575 svm->vmcb->save.sysenter_cs = data;
3577 case MSR_IA32_SYSENTER_EIP:
3578 svm->sysenter_eip = data;
3579 svm->vmcb->save.sysenter_eip = data;
3581 case MSR_IA32_SYSENTER_ESP:
3582 svm->sysenter_esp = data;
3583 svm->vmcb->save.sysenter_esp = data;
3586 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3590 * This is rare, so we update the MSR here instead of using
3591 * direct_access_msrs. Doing that would require a rdmsr in
3594 svm->tsc_aux = data;
3595 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3597 case MSR_IA32_DEBUGCTLMSR:
3598 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3599 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3603 if (data & DEBUGCTL_RESERVED_BITS)
3606 svm->vmcb->save.dbgctl = data;
3607 mark_dirty(svm->vmcb, VMCB_LBR);
3608 if (data & (1ULL<<0))
3609 svm_enable_lbrv(svm);
3611 svm_disable_lbrv(svm);
3613 case MSR_VM_HSAVE_PA:
3614 svm->nested.hsave_msr = data;
3617 return svm_set_vm_cr(vcpu, data);
3619 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3621 case MSR_IA32_APICBASE:
3622 if (kvm_vcpu_apicv_active(vcpu))
3623 avic_update_vapic_bar(to_svm(vcpu), data);
3624 /* Follow through */
3626 return kvm_set_msr_common(vcpu, msr);
3631 static int wrmsr_interception(struct vcpu_svm *svm)
3633 struct msr_data msr;
3634 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3635 u64 data = kvm_read_edx_eax(&svm->vcpu);
3639 msr.host_initiated = false;
3641 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3642 if (kvm_set_msr(&svm->vcpu, &msr)) {
3643 trace_kvm_msr_write_ex(ecx, data);
3644 kvm_inject_gp(&svm->vcpu, 0);
3646 trace_kvm_msr_write(ecx, data);
3647 skip_emulated_instruction(&svm->vcpu);
3652 static int msr_interception(struct vcpu_svm *svm)
3654 if (svm->vmcb->control.exit_info_1)
3655 return wrmsr_interception(svm);
3657 return rdmsr_interception(svm);
3660 static int interrupt_window_interception(struct vcpu_svm *svm)
3662 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3663 svm_clear_vintr(svm);
3664 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3665 mark_dirty(svm->vmcb, VMCB_INTR);
3666 ++svm->vcpu.stat.irq_window_exits;
3670 static int pause_interception(struct vcpu_svm *svm)
3672 kvm_vcpu_on_spin(&(svm->vcpu));
3676 static int nop_interception(struct vcpu_svm *svm)
3678 skip_emulated_instruction(&(svm->vcpu));
3682 static int monitor_interception(struct vcpu_svm *svm)
3684 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3685 return nop_interception(svm);
3688 static int mwait_interception(struct vcpu_svm *svm)
3690 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3691 return nop_interception(svm);
3694 enum avic_ipi_failure_cause {
3695 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3696 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3697 AVIC_IPI_FAILURE_INVALID_TARGET,
3698 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3701 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3703 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3704 u32 icrl = svm->vmcb->control.exit_info_1;
3705 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3706 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3707 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3709 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3712 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3714 * AVIC hardware handles the generation of
3715 * IPIs when the specified Message Type is Fixed
3716 * (also known as fixed delivery mode) and
3717 * the Trigger Mode is edge-triggered. The hardware
3718 * also supports self and broadcast delivery modes
3719 * specified via the Destination Shorthand(DSH)
3720 * field of the ICRL. Logical and physical APIC ID
3721 * formats are supported. All other IPI types cause
3722 * a #VMEXIT, which needs to emulated.
3724 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3725 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3727 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3729 struct kvm_vcpu *vcpu;
3730 struct kvm *kvm = svm->vcpu.kvm;
3731 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3734 * At this point, we expect that the AVIC HW has already
3735 * set the appropriate IRR bits on the valid target
3736 * vcpus. So, we just need to kick the appropriate vcpu.
3738 kvm_for_each_vcpu(i, vcpu, kvm) {
3739 bool m = kvm_apic_match_dest(vcpu, apic,
3740 icrl & KVM_APIC_SHORT_MASK,
3741 GET_APIC_DEST_FIELD(icrh),
3742 icrl & KVM_APIC_DEST_MASK);
3744 if (m && !avic_vcpu_is_running(vcpu))
3745 kvm_vcpu_wake_up(vcpu);
3749 case AVIC_IPI_FAILURE_INVALID_TARGET:
3751 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3752 WARN_ONCE(1, "Invalid backing page\n");
3755 pr_err("Unknown IPI interception\n");
3761 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3763 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3765 u32 *logical_apic_id_table;
3766 int dlid = GET_APIC_LOGICAL_ID(ldr);
3771 if (flat) { /* flat */
3772 index = ffs(dlid) - 1;
3775 } else { /* cluster */
3776 int cluster = (dlid & 0xf0) >> 4;
3777 int apic = ffs(dlid & 0x0f) - 1;
3779 if ((apic < 0) || (apic > 7) ||
3782 index = (cluster << 2) + apic;
3785 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3787 return &logical_apic_id_table[index];
3790 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3794 u32 *entry, new_entry;
3796 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3797 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3801 new_entry = READ_ONCE(*entry);
3802 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3803 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3805 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3807 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3808 WRITE_ONCE(*entry, new_entry);
3813 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3816 struct vcpu_svm *svm = to_svm(vcpu);
3817 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3822 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3823 if (ret && svm->ldr_reg) {
3824 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3832 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3835 struct vcpu_svm *svm = to_svm(vcpu);
3836 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3837 u32 id = (apic_id_reg >> 24) & 0xff;
3839 if (vcpu->vcpu_id == id)
3842 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3843 new = avic_get_physical_id_entry(vcpu, id);
3847 /* We need to move physical_id_entry to new offset */
3850 to_svm(vcpu)->avic_physical_id_cache = new;
3853 * Also update the guest physical APIC ID in the logical
3854 * APIC ID table entry if already setup the LDR.
3857 avic_handle_ldr_update(vcpu);
3862 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3864 struct vcpu_svm *svm = to_svm(vcpu);
3865 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3866 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3867 u32 mod = (dfr >> 28) & 0xf;
3870 * We assume that all local APICs are using the same type.
3871 * If this changes, we need to flush the AVIC logical
3874 if (vm_data->ldr_mode == mod)
3877 clear_page(page_address(vm_data->avic_logical_id_table_page));
3878 vm_data->ldr_mode = mod;
3881 avic_handle_ldr_update(vcpu);
3885 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3887 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3888 u32 offset = svm->vmcb->control.exit_info_1 &
3889 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3893 if (avic_handle_apic_id_update(&svm->vcpu))
3897 if (avic_handle_ldr_update(&svm->vcpu))
3901 avic_handle_dfr_update(&svm->vcpu);
3907 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3912 static bool is_avic_unaccelerated_access_trap(u32 offset)
3941 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3944 u32 offset = svm->vmcb->control.exit_info_1 &
3945 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3946 u32 vector = svm->vmcb->control.exit_info_2 &
3947 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3948 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3949 AVIC_UNACCEL_ACCESS_WRITE_MASK;
3950 bool trap = is_avic_unaccelerated_access_trap(offset);
3952 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3953 trap, write, vector);
3956 WARN_ONCE(!write, "svm: Handling trap read.\n");
3957 ret = avic_unaccel_trap_write(svm);
3959 /* Handling Fault */
3960 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3966 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3967 [SVM_EXIT_READ_CR0] = cr_interception,
3968 [SVM_EXIT_READ_CR3] = cr_interception,
3969 [SVM_EXIT_READ_CR4] = cr_interception,
3970 [SVM_EXIT_READ_CR8] = cr_interception,
3971 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3972 [SVM_EXIT_WRITE_CR0] = cr_interception,
3973 [SVM_EXIT_WRITE_CR3] = cr_interception,
3974 [SVM_EXIT_WRITE_CR4] = cr_interception,
3975 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3976 [SVM_EXIT_READ_DR0] = dr_interception,
3977 [SVM_EXIT_READ_DR1] = dr_interception,
3978 [SVM_EXIT_READ_DR2] = dr_interception,
3979 [SVM_EXIT_READ_DR3] = dr_interception,
3980 [SVM_EXIT_READ_DR4] = dr_interception,
3981 [SVM_EXIT_READ_DR5] = dr_interception,
3982 [SVM_EXIT_READ_DR6] = dr_interception,
3983 [SVM_EXIT_READ_DR7] = dr_interception,
3984 [SVM_EXIT_WRITE_DR0] = dr_interception,
3985 [SVM_EXIT_WRITE_DR1] = dr_interception,
3986 [SVM_EXIT_WRITE_DR2] = dr_interception,
3987 [SVM_EXIT_WRITE_DR3] = dr_interception,
3988 [SVM_EXIT_WRITE_DR4] = dr_interception,
3989 [SVM_EXIT_WRITE_DR5] = dr_interception,
3990 [SVM_EXIT_WRITE_DR6] = dr_interception,
3991 [SVM_EXIT_WRITE_DR7] = dr_interception,
3992 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3993 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3994 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3995 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3996 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3997 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3998 [SVM_EXIT_INTR] = intr_interception,
3999 [SVM_EXIT_NMI] = nmi_interception,
4000 [SVM_EXIT_SMI] = nop_on_interception,
4001 [SVM_EXIT_INIT] = nop_on_interception,
4002 [SVM_EXIT_VINTR] = interrupt_window_interception,
4003 [SVM_EXIT_RDPMC] = rdpmc_interception,
4004 [SVM_EXIT_CPUID] = cpuid_interception,
4005 [SVM_EXIT_IRET] = iret_interception,
4006 [SVM_EXIT_INVD] = emulate_on_interception,
4007 [SVM_EXIT_PAUSE] = pause_interception,
4008 [SVM_EXIT_HLT] = halt_interception,
4009 [SVM_EXIT_INVLPG] = invlpg_interception,
4010 [SVM_EXIT_INVLPGA] = invlpga_interception,
4011 [SVM_EXIT_IOIO] = io_interception,
4012 [SVM_EXIT_MSR] = msr_interception,
4013 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4014 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4015 [SVM_EXIT_VMRUN] = vmrun_interception,
4016 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4017 [SVM_EXIT_VMLOAD] = vmload_interception,
4018 [SVM_EXIT_VMSAVE] = vmsave_interception,
4019 [SVM_EXIT_STGI] = stgi_interception,
4020 [SVM_EXIT_CLGI] = clgi_interception,
4021 [SVM_EXIT_SKINIT] = skinit_interception,
4022 [SVM_EXIT_WBINVD] = wbinvd_interception,
4023 [SVM_EXIT_MONITOR] = monitor_interception,
4024 [SVM_EXIT_MWAIT] = mwait_interception,
4025 [SVM_EXIT_XSETBV] = xsetbv_interception,
4026 [SVM_EXIT_NPF] = pf_interception,
4027 [SVM_EXIT_RSM] = emulate_on_interception,
4028 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4029 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4032 static void dump_vmcb(struct kvm_vcpu *vcpu)
4034 struct vcpu_svm *svm = to_svm(vcpu);
4035 struct vmcb_control_area *control = &svm->vmcb->control;
4036 struct vmcb_save_area *save = &svm->vmcb->save;
4038 pr_err("VMCB Control Area:\n");
4039 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4040 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4041 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4042 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4043 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4044 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4045 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4046 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4047 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4048 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4049 pr_err("%-20s%d\n", "asid:", control->asid);
4050 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4051 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4052 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4053 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4054 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4055 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4056 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4057 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4058 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4059 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4060 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4061 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4062 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4063 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4064 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4065 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4066 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4067 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4068 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4069 pr_err("VMCB State Save Area:\n");
4070 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4072 save->es.selector, save->es.attrib,
4073 save->es.limit, save->es.base);
4074 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4076 save->cs.selector, save->cs.attrib,
4077 save->cs.limit, save->cs.base);
4078 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4080 save->ss.selector, save->ss.attrib,
4081 save->ss.limit, save->ss.base);
4082 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4084 save->ds.selector, save->ds.attrib,
4085 save->ds.limit, save->ds.base);
4086 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4088 save->fs.selector, save->fs.attrib,
4089 save->fs.limit, save->fs.base);
4090 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4092 save->gs.selector, save->gs.attrib,
4093 save->gs.limit, save->gs.base);
4094 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4096 save->gdtr.selector, save->gdtr.attrib,
4097 save->gdtr.limit, save->gdtr.base);
4098 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4100 save->ldtr.selector, save->ldtr.attrib,
4101 save->ldtr.limit, save->ldtr.base);
4102 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4104 save->idtr.selector, save->idtr.attrib,
4105 save->idtr.limit, save->idtr.base);
4106 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4108 save->tr.selector, save->tr.attrib,
4109 save->tr.limit, save->tr.base);
4110 pr_err("cpl: %d efer: %016llx\n",
4111 save->cpl, save->efer);
4112 pr_err("%-15s %016llx %-13s %016llx\n",
4113 "cr0:", save->cr0, "cr2:", save->cr2);
4114 pr_err("%-15s %016llx %-13s %016llx\n",
4115 "cr3:", save->cr3, "cr4:", save->cr4);
4116 pr_err("%-15s %016llx %-13s %016llx\n",
4117 "dr6:", save->dr6, "dr7:", save->dr7);
4118 pr_err("%-15s %016llx %-13s %016llx\n",
4119 "rip:", save->rip, "rflags:", save->rflags);
4120 pr_err("%-15s %016llx %-13s %016llx\n",
4121 "rsp:", save->rsp, "rax:", save->rax);
4122 pr_err("%-15s %016llx %-13s %016llx\n",
4123 "star:", save->star, "lstar:", save->lstar);
4124 pr_err("%-15s %016llx %-13s %016llx\n",
4125 "cstar:", save->cstar, "sfmask:", save->sfmask);
4126 pr_err("%-15s %016llx %-13s %016llx\n",
4127 "kernel_gs_base:", save->kernel_gs_base,
4128 "sysenter_cs:", save->sysenter_cs);
4129 pr_err("%-15s %016llx %-13s %016llx\n",
4130 "sysenter_esp:", save->sysenter_esp,
4131 "sysenter_eip:", save->sysenter_eip);
4132 pr_err("%-15s %016llx %-13s %016llx\n",
4133 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4134 pr_err("%-15s %016llx %-13s %016llx\n",
4135 "br_from:", save->br_from, "br_to:", save->br_to);
4136 pr_err("%-15s %016llx %-13s %016llx\n",
4137 "excp_from:", save->last_excp_from,
4138 "excp_to:", save->last_excp_to);
4141 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4143 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4145 *info1 = control->exit_info_1;
4146 *info2 = control->exit_info_2;
4149 static int handle_exit(struct kvm_vcpu *vcpu)
4151 struct vcpu_svm *svm = to_svm(vcpu);
4152 struct kvm_run *kvm_run = vcpu->run;
4153 u32 exit_code = svm->vmcb->control.exit_code;
4155 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4157 vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4159 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4160 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4162 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4164 if (unlikely(svm->nested.exit_required)) {
4165 nested_svm_vmexit(svm);
4166 svm->nested.exit_required = false;
4171 if (is_guest_mode(vcpu)) {
4174 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4175 svm->vmcb->control.exit_info_1,
4176 svm->vmcb->control.exit_info_2,
4177 svm->vmcb->control.exit_int_info,
4178 svm->vmcb->control.exit_int_info_err,
4181 vmexit = nested_svm_exit_special(svm);
4183 if (vmexit == NESTED_EXIT_CONTINUE)
4184 vmexit = nested_svm_exit_handled(svm);
4186 if (vmexit == NESTED_EXIT_DONE)
4190 svm_complete_interrupts(svm);
4192 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4193 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4194 kvm_run->fail_entry.hardware_entry_failure_reason
4195 = svm->vmcb->control.exit_code;
4196 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4201 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4202 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4203 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4204 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4205 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4207 __func__, svm->vmcb->control.exit_int_info,
4210 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4211 || !svm_exit_handlers[exit_code]) {
4212 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4213 kvm_queue_exception(vcpu, UD_VECTOR);
4217 return svm_exit_handlers[exit_code](svm);
4220 static void reload_tss(struct kvm_vcpu *vcpu)
4222 int cpu = raw_smp_processor_id();
4224 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4225 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4229 static void pre_svm_run(struct vcpu_svm *svm)
4231 int cpu = raw_smp_processor_id();
4233 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4235 /* FIXME: handle wraparound of asid_generation */
4236 if (svm->asid_generation != sd->asid_generation)
4240 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4242 struct vcpu_svm *svm = to_svm(vcpu);
4244 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4245 vcpu->arch.hflags |= HF_NMI_MASK;
4246 set_intercept(svm, INTERCEPT_IRET);
4247 ++vcpu->stat.nmi_injections;
4250 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4252 struct vmcb_control_area *control;
4254 /* The following fields are ignored when AVIC is enabled */
4255 control = &svm->vmcb->control;
4256 control->int_vector = irq;
4257 control->int_ctl &= ~V_INTR_PRIO_MASK;
4258 control->int_ctl |= V_IRQ_MASK |
4259 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4260 mark_dirty(svm->vmcb, VMCB_INTR);
4263 static void svm_set_irq(struct kvm_vcpu *vcpu)
4265 struct vcpu_svm *svm = to_svm(vcpu);
4267 BUG_ON(!(gif_set(svm)));
4269 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4270 ++vcpu->stat.irq_injections;
4272 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4273 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4276 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4278 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4281 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4283 struct vcpu_svm *svm = to_svm(vcpu);
4285 if (svm_nested_virtualize_tpr(vcpu) ||
4286 kvm_vcpu_apicv_active(vcpu))
4289 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4295 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4298 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4303 static bool svm_get_enable_apicv(void)
4308 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4312 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4316 /* Note: Currently only used by Hyper-V. */
4317 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4319 struct vcpu_svm *svm = to_svm(vcpu);
4320 struct vmcb *vmcb = svm->vmcb;
4325 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4326 mark_dirty(vmcb, VMCB_INTR);
4329 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4334 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4336 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4337 smp_mb__after_atomic();
4339 if (avic_vcpu_is_running(vcpu))
4340 wrmsrl(SVM_AVIC_DOORBELL,
4341 kvm_cpu_get_apicid(vcpu->cpu));
4343 kvm_vcpu_wake_up(vcpu);
4346 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4348 unsigned long flags;
4349 struct amd_svm_iommu_ir *cur;
4351 spin_lock_irqsave(&svm->ir_list_lock, flags);
4352 list_for_each_entry(cur, &svm->ir_list, node) {
4353 if (cur->data != pi->ir_data)
4355 list_del(&cur->node);
4359 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4362 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4365 unsigned long flags;
4366 struct amd_svm_iommu_ir *ir;
4369 * In some cases, the existing irte is updaed and re-set,
4370 * so we need to check here if it's already been * added
4373 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4374 struct kvm *kvm = svm->vcpu.kvm;
4375 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4376 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4377 struct vcpu_svm *prev_svm;
4384 prev_svm = to_svm(prev_vcpu);
4385 svm_ir_list_del(prev_svm, pi);
4389 * Allocating new amd_iommu_pi_data, which will get
4390 * add to the per-vcpu ir_list.
4392 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4397 ir->data = pi->ir_data;
4399 spin_lock_irqsave(&svm->ir_list_lock, flags);
4400 list_add(&ir->node, &svm->ir_list);
4401 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4408 * The HW cannot support posting multicast/broadcast
4409 * interrupts to a vCPU. So, we still use legacy interrupt
4410 * remapping for these kind of interrupts.
4412 * For lowest-priority interrupts, we only support
4413 * those with single CPU as the destination, e.g. user
4414 * configures the interrupts via /proc/irq or uses
4415 * irqbalance to make the interrupts single-CPU.
4418 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4419 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4421 struct kvm_lapic_irq irq;
4422 struct kvm_vcpu *vcpu = NULL;
4424 kvm_set_msi_irq(kvm, e, &irq);
4426 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4427 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4428 __func__, irq.vector);
4432 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4434 *svm = to_svm(vcpu);
4435 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4436 vcpu_info->vector = irq.vector;
4442 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4445 * @host_irq: host irq of the interrupt
4446 * @guest_irq: gsi of the interrupt
4447 * @set: set or unset PI
4448 * returns 0 on success, < 0 on failure
4450 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4451 uint32_t guest_irq, bool set)
4453 struct kvm_kernel_irq_routing_entry *e;
4454 struct kvm_irq_routing_table *irq_rt;
4455 int idx, ret = -EINVAL;
4457 if (!kvm_arch_has_assigned_device(kvm) ||
4458 !irq_remapping_cap(IRQ_POSTING_CAP))
4461 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4462 __func__, host_irq, guest_irq, set);
4464 idx = srcu_read_lock(&kvm->irq_srcu);
4465 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4466 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4468 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4469 struct vcpu_data vcpu_info;
4470 struct vcpu_svm *svm = NULL;
4472 if (e->type != KVM_IRQ_ROUTING_MSI)
4476 * Here, we setup with legacy mode in the following cases:
4477 * 1. When cannot target interrupt to a specific vcpu.
4478 * 2. Unsetting posted interrupt.
4479 * 3. APIC virtialization is disabled for the vcpu.
4481 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4482 kvm_vcpu_apicv_active(&svm->vcpu)) {
4483 struct amd_iommu_pi_data pi;
4485 /* Try to enable guest_mode in IRTE */
4486 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4487 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4489 pi.is_guest_mode = true;
4490 pi.vcpu_data = &vcpu_info;
4491 ret = irq_set_vcpu_affinity(host_irq, &pi);
4494 * Here, we successfully setting up vcpu affinity in
4495 * IOMMU guest mode. Now, we need to store the posted
4496 * interrupt information in a per-vcpu ir_list so that
4497 * we can reference to them directly when we update vcpu
4498 * scheduling information in IOMMU irte.
4500 if (!ret && pi.is_guest_mode)
4501 svm_ir_list_add(svm, &pi);
4503 /* Use legacy mode in IRTE */
4504 struct amd_iommu_pi_data pi;
4507 * Here, pi is used to:
4508 * - Tell IOMMU to use legacy mode for this interrupt.
4509 * - Retrieve ga_tag of prior interrupt remapping data.
4511 pi.is_guest_mode = false;
4512 ret = irq_set_vcpu_affinity(host_irq, &pi);
4515 * Check if the posted interrupt was previously
4516 * setup with the guest_mode by checking if the ga_tag
4517 * was cached. If so, we need to clean up the per-vcpu
4520 if (!ret && pi.prev_ga_tag) {
4521 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4522 struct kvm_vcpu *vcpu;
4524 vcpu = kvm_get_vcpu_by_id(kvm, id);
4526 svm_ir_list_del(to_svm(vcpu), &pi);
4531 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4534 vcpu_info.pi_desc_addr, set);
4538 pr_err("%s: failed to update PI IRTE\n", __func__);
4545 srcu_read_unlock(&kvm->irq_srcu, idx);
4549 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4551 struct vcpu_svm *svm = to_svm(vcpu);
4552 struct vmcb *vmcb = svm->vmcb;
4554 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4555 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4556 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4561 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4563 struct vcpu_svm *svm = to_svm(vcpu);
4565 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4568 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4570 struct vcpu_svm *svm = to_svm(vcpu);
4573 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4574 set_intercept(svm, INTERCEPT_IRET);
4576 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4577 clr_intercept(svm, INTERCEPT_IRET);
4581 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4583 struct vcpu_svm *svm = to_svm(vcpu);
4584 struct vmcb *vmcb = svm->vmcb;
4587 if (!gif_set(svm) ||
4588 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4591 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4593 if (is_guest_mode(vcpu))
4594 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4599 static void enable_irq_window(struct kvm_vcpu *vcpu)
4601 struct vcpu_svm *svm = to_svm(vcpu);
4603 if (kvm_vcpu_apicv_active(vcpu))
4607 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4608 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4609 * get that intercept, this function will be called again though and
4610 * we'll get the vintr intercept.
4612 if (gif_set(svm) && nested_svm_intr(svm)) {
4614 svm_inject_irq(svm, 0x0);
4618 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4620 struct vcpu_svm *svm = to_svm(vcpu);
4622 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4624 return; /* IRET will cause a vm exit */
4627 * Something prevents NMI from been injected. Single step over possible
4628 * problem (IRET or exception injection or interrupt shadow)
4630 svm->nmi_singlestep = true;
4631 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4634 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4639 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4641 struct vcpu_svm *svm = to_svm(vcpu);
4643 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4644 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4646 svm->asid_generation--;
4649 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4653 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4655 struct vcpu_svm *svm = to_svm(vcpu);
4657 if (svm_nested_virtualize_tpr(vcpu))
4660 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4661 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4662 kvm_set_cr8(vcpu, cr8);
4666 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4668 struct vcpu_svm *svm = to_svm(vcpu);
4671 if (svm_nested_virtualize_tpr(vcpu) ||
4672 kvm_vcpu_apicv_active(vcpu))
4675 cr8 = kvm_get_cr8(vcpu);
4676 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4677 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4680 static void svm_complete_interrupts(struct vcpu_svm *svm)
4684 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4685 unsigned int3_injected = svm->int3_injected;
4687 svm->int3_injected = 0;
4690 * If we've made progress since setting HF_IRET_MASK, we've
4691 * executed an IRET and can allow NMI injection.
4693 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4694 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4695 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4696 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4699 svm->vcpu.arch.nmi_injected = false;
4700 kvm_clear_exception_queue(&svm->vcpu);
4701 kvm_clear_interrupt_queue(&svm->vcpu);
4703 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4706 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4708 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4709 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4712 case SVM_EXITINTINFO_TYPE_NMI:
4713 svm->vcpu.arch.nmi_injected = true;
4715 case SVM_EXITINTINFO_TYPE_EXEPT:
4717 * In case of software exceptions, do not reinject the vector,
4718 * but re-execute the instruction instead. Rewind RIP first
4719 * if we emulated INT3 before.
4721 if (kvm_exception_is_soft(vector)) {
4722 if (vector == BP_VECTOR && int3_injected &&
4723 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4724 kvm_rip_write(&svm->vcpu,
4725 kvm_rip_read(&svm->vcpu) -
4729 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4730 u32 err = svm->vmcb->control.exit_int_info_err;
4731 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4734 kvm_requeue_exception(&svm->vcpu, vector);
4736 case SVM_EXITINTINFO_TYPE_INTR:
4737 kvm_queue_interrupt(&svm->vcpu, vector, false);
4744 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4746 struct vcpu_svm *svm = to_svm(vcpu);
4747 struct vmcb_control_area *control = &svm->vmcb->control;
4749 control->exit_int_info = control->event_inj;
4750 control->exit_int_info_err = control->event_inj_err;
4751 control->event_inj = 0;
4752 svm_complete_interrupts(svm);
4755 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4757 struct vcpu_svm *svm = to_svm(vcpu);
4759 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4760 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4761 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4764 * A vmexit emulation is required before the vcpu can be executed
4767 if (unlikely(svm->nested.exit_required))
4772 sync_lapic_to_cr8(vcpu);
4774 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4781 "push %%" _ASM_BP "; \n\t"
4782 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4783 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4784 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4785 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4786 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4787 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4788 #ifdef CONFIG_X86_64
4789 "mov %c[r8](%[svm]), %%r8 \n\t"
4790 "mov %c[r9](%[svm]), %%r9 \n\t"
4791 "mov %c[r10](%[svm]), %%r10 \n\t"
4792 "mov %c[r11](%[svm]), %%r11 \n\t"
4793 "mov %c[r12](%[svm]), %%r12 \n\t"
4794 "mov %c[r13](%[svm]), %%r13 \n\t"
4795 "mov %c[r14](%[svm]), %%r14 \n\t"
4796 "mov %c[r15](%[svm]), %%r15 \n\t"
4799 /* Enter guest mode */
4800 "push %%" _ASM_AX " \n\t"
4801 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4802 __ex(SVM_VMLOAD) "\n\t"
4803 __ex(SVM_VMRUN) "\n\t"
4804 __ex(SVM_VMSAVE) "\n\t"
4805 "pop %%" _ASM_AX " \n\t"
4807 /* Save guest registers, load host registers */
4808 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4809 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4810 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4811 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4812 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4813 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4814 #ifdef CONFIG_X86_64
4815 "mov %%r8, %c[r8](%[svm]) \n\t"
4816 "mov %%r9, %c[r9](%[svm]) \n\t"
4817 "mov %%r10, %c[r10](%[svm]) \n\t"
4818 "mov %%r11, %c[r11](%[svm]) \n\t"
4819 "mov %%r12, %c[r12](%[svm]) \n\t"
4820 "mov %%r13, %c[r13](%[svm]) \n\t"
4821 "mov %%r14, %c[r14](%[svm]) \n\t"
4822 "mov %%r15, %c[r15](%[svm]) \n\t"
4827 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4828 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4829 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4830 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4831 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4832 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4833 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4834 #ifdef CONFIG_X86_64
4835 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4836 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4837 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4838 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4839 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4840 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4841 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4842 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4845 #ifdef CONFIG_X86_64
4846 , "rbx", "rcx", "rdx", "rsi", "rdi"
4847 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4849 , "ebx", "ecx", "edx", "esi", "edi"
4853 #ifdef CONFIG_X86_64
4854 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4856 loadsegment(fs, svm->host.fs);
4857 #ifndef CONFIG_X86_32_LAZY_GS
4858 loadsegment(gs, svm->host.gs);
4864 local_irq_disable();
4866 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4867 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4868 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4869 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4871 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4872 kvm_before_handle_nmi(&svm->vcpu);
4876 /* Any pending NMI will happen here */
4878 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4879 kvm_after_handle_nmi(&svm->vcpu);
4881 sync_cr8_to_lapic(vcpu);
4885 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4887 /* if exit due to PF check for async PF */
4888 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4889 svm->apf_reason = kvm_read_and_reset_pf_reason();
4892 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4893 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4897 * We need to handle MC intercepts here before the vcpu has a chance to
4898 * change the physical cpu
4900 if (unlikely(svm->vmcb->control.exit_code ==
4901 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4902 svm_handle_mce(svm);
4904 mark_all_clean(svm->vmcb);
4907 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4909 struct vcpu_svm *svm = to_svm(vcpu);
4911 svm->vmcb->save.cr3 = root;
4912 mark_dirty(svm->vmcb, VMCB_CR);
4913 svm_flush_tlb(vcpu);
4916 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4918 struct vcpu_svm *svm = to_svm(vcpu);
4920 svm->vmcb->control.nested_cr3 = root;
4921 mark_dirty(svm->vmcb, VMCB_NPT);
4923 /* Also sync guest cr3 here in case we live migrate */
4924 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4925 mark_dirty(svm->vmcb, VMCB_CR);
4927 svm_flush_tlb(vcpu);
4930 static int is_disabled(void)
4934 rdmsrl(MSR_VM_CR, vm_cr);
4935 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4942 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4945 * Patch in the VMMCALL instruction:
4947 hypercall[0] = 0x0f;
4948 hypercall[1] = 0x01;
4949 hypercall[2] = 0xd9;
4952 static void svm_check_processor_compat(void *rtn)
4957 static bool svm_cpu_has_accelerated_tpr(void)
4962 static bool svm_has_high_real_mode_segbase(void)
4967 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4972 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4974 struct vcpu_svm *svm = to_svm(vcpu);
4975 struct kvm_cpuid_entry2 *entry;
4977 /* Update nrips enabled cache */
4978 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4980 if (!kvm_vcpu_apicv_active(vcpu))
4983 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
4985 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4988 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4993 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4997 entry->ecx |= (1 << 2); /* Set SVM bit */
5000 entry->eax = 1; /* SVM revision 1 */
5001 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5002 ASID emulation to nested SVM */
5003 entry->ecx = 0; /* Reserved */
5004 entry->edx = 0; /* Per default do not support any
5005 additional features */
5007 /* Support next_rip if host supports it */
5008 if (boot_cpu_has(X86_FEATURE_NRIPS))
5009 entry->edx |= SVM_FEATURE_NRIP;
5011 /* Support NPT for the guest if enabled */
5013 entry->edx |= SVM_FEATURE_NPT;
5019 static int svm_get_lpage_level(void)
5021 return PT_PDPE_LEVEL;
5024 static bool svm_rdtscp_supported(void)
5026 return boot_cpu_has(X86_FEATURE_RDTSCP);
5029 static bool svm_invpcid_supported(void)
5034 static bool svm_mpx_supported(void)
5039 static bool svm_xsaves_supported(void)
5044 static bool svm_has_wbinvd_exit(void)
5049 #define PRE_EX(exit) { .exit_code = (exit), \
5050 .stage = X86_ICPT_PRE_EXCEPT, }
5051 #define POST_EX(exit) { .exit_code = (exit), \
5052 .stage = X86_ICPT_POST_EXCEPT, }
5053 #define POST_MEM(exit) { .exit_code = (exit), \
5054 .stage = X86_ICPT_POST_MEMACCESS, }
5056 static const struct __x86_intercept {
5058 enum x86_intercept_stage stage;
5059 } x86_intercept_map[] = {
5060 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5061 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5062 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5063 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5064 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5065 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5066 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5067 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5068 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5069 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5070 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5071 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5072 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5073 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5074 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5075 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5076 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5077 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5078 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5079 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5080 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5081 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5082 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5083 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5084 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5085 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5086 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5087 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5088 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5089 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5090 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5091 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5092 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5093 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5094 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5095 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5096 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5097 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5098 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5099 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5100 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5101 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5102 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5103 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5104 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5105 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5112 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5113 struct x86_instruction_info *info,
5114 enum x86_intercept_stage stage)
5116 struct vcpu_svm *svm = to_svm(vcpu);
5117 int vmexit, ret = X86EMUL_CONTINUE;
5118 struct __x86_intercept icpt_info;
5119 struct vmcb *vmcb = svm->vmcb;
5121 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5124 icpt_info = x86_intercept_map[info->intercept];
5126 if (stage != icpt_info.stage)
5129 switch (icpt_info.exit_code) {
5130 case SVM_EXIT_READ_CR0:
5131 if (info->intercept == x86_intercept_cr_read)
5132 icpt_info.exit_code += info->modrm_reg;
5134 case SVM_EXIT_WRITE_CR0: {
5135 unsigned long cr0, val;
5138 if (info->intercept == x86_intercept_cr_write)
5139 icpt_info.exit_code += info->modrm_reg;
5141 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5142 info->intercept == x86_intercept_clts)
5145 intercept = svm->nested.intercept;
5147 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5150 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5151 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5153 if (info->intercept == x86_intercept_lmsw) {
5156 /* lmsw can't clear PE - catch this here */
5157 if (cr0 & X86_CR0_PE)
5162 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5166 case SVM_EXIT_READ_DR0:
5167 case SVM_EXIT_WRITE_DR0:
5168 icpt_info.exit_code += info->modrm_reg;
5171 if (info->intercept == x86_intercept_wrmsr)
5172 vmcb->control.exit_info_1 = 1;
5174 vmcb->control.exit_info_1 = 0;
5176 case SVM_EXIT_PAUSE:
5178 * We get this for NOP only, but pause
5179 * is rep not, check this here
5181 if (info->rep_prefix != REPE_PREFIX)
5183 case SVM_EXIT_IOIO: {
5187 if (info->intercept == x86_intercept_in ||
5188 info->intercept == x86_intercept_ins) {
5189 exit_info = ((info->src_val & 0xffff) << 16) |
5191 bytes = info->dst_bytes;
5193 exit_info = (info->dst_val & 0xffff) << 16;
5194 bytes = info->src_bytes;
5197 if (info->intercept == x86_intercept_outs ||
5198 info->intercept == x86_intercept_ins)
5199 exit_info |= SVM_IOIO_STR_MASK;
5201 if (info->rep_prefix)
5202 exit_info |= SVM_IOIO_REP_MASK;
5204 bytes = min(bytes, 4u);
5206 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5208 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5210 vmcb->control.exit_info_1 = exit_info;
5211 vmcb->control.exit_info_2 = info->next_rip;
5219 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5220 if (static_cpu_has(X86_FEATURE_NRIPS))
5221 vmcb->control.next_rip = info->next_rip;
5222 vmcb->control.exit_code = icpt_info.exit_code;
5223 vmexit = nested_svm_exit_handled(svm);
5225 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5232 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5236 * We must have an instruction with interrupts enabled, so
5237 * the timer interrupt isn't delayed by the interrupt shadow.
5240 local_irq_disable();
5243 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5247 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5249 if (avic_handle_apic_id_update(vcpu) != 0)
5251 if (avic_handle_dfr_update(vcpu) != 0)
5253 avic_handle_ldr_update(vcpu);
5256 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5257 .cpu_has_kvm_support = has_svm,
5258 .disabled_by_bios = is_disabled,
5259 .hardware_setup = svm_hardware_setup,
5260 .hardware_unsetup = svm_hardware_unsetup,
5261 .check_processor_compatibility = svm_check_processor_compat,
5262 .hardware_enable = svm_hardware_enable,
5263 .hardware_disable = svm_hardware_disable,
5264 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5265 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5267 .vcpu_create = svm_create_vcpu,
5268 .vcpu_free = svm_free_vcpu,
5269 .vcpu_reset = svm_vcpu_reset,
5271 .vm_init = avic_vm_init,
5272 .vm_destroy = avic_vm_destroy,
5274 .prepare_guest_switch = svm_prepare_guest_switch,
5275 .vcpu_load = svm_vcpu_load,
5276 .vcpu_put = svm_vcpu_put,
5277 .vcpu_blocking = svm_vcpu_blocking,
5278 .vcpu_unblocking = svm_vcpu_unblocking,
5280 .update_bp_intercept = update_bp_intercept,
5281 .get_msr = svm_get_msr,
5282 .set_msr = svm_set_msr,
5283 .get_segment_base = svm_get_segment_base,
5284 .get_segment = svm_get_segment,
5285 .set_segment = svm_set_segment,
5286 .get_cpl = svm_get_cpl,
5287 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5288 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5289 .decache_cr3 = svm_decache_cr3,
5290 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5291 .set_cr0 = svm_set_cr0,
5292 .set_cr3 = svm_set_cr3,
5293 .set_cr4 = svm_set_cr4,
5294 .set_efer = svm_set_efer,
5295 .get_idt = svm_get_idt,
5296 .set_idt = svm_set_idt,
5297 .get_gdt = svm_get_gdt,
5298 .set_gdt = svm_set_gdt,
5299 .get_dr6 = svm_get_dr6,
5300 .set_dr6 = svm_set_dr6,
5301 .set_dr7 = svm_set_dr7,
5302 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5303 .cache_reg = svm_cache_reg,
5304 .get_rflags = svm_get_rflags,
5305 .set_rflags = svm_set_rflags,
5307 .get_pkru = svm_get_pkru,
5309 .tlb_flush = svm_flush_tlb,
5311 .run = svm_vcpu_run,
5312 .handle_exit = handle_exit,
5313 .skip_emulated_instruction = skip_emulated_instruction,
5314 .set_interrupt_shadow = svm_set_interrupt_shadow,
5315 .get_interrupt_shadow = svm_get_interrupt_shadow,
5316 .patch_hypercall = svm_patch_hypercall,
5317 .set_irq = svm_set_irq,
5318 .set_nmi = svm_inject_nmi,
5319 .queue_exception = svm_queue_exception,
5320 .cancel_injection = svm_cancel_injection,
5321 .interrupt_allowed = svm_interrupt_allowed,
5322 .nmi_allowed = svm_nmi_allowed,
5323 .get_nmi_mask = svm_get_nmi_mask,
5324 .set_nmi_mask = svm_set_nmi_mask,
5325 .enable_nmi_window = enable_nmi_window,
5326 .enable_irq_window = enable_irq_window,
5327 .update_cr8_intercept = update_cr8_intercept,
5328 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5329 .get_enable_apicv = svm_get_enable_apicv,
5330 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5331 .load_eoi_exitmap = svm_load_eoi_exitmap,
5332 .hwapic_irr_update = svm_hwapic_irr_update,
5333 .hwapic_isr_update = svm_hwapic_isr_update,
5334 .apicv_post_state_restore = avic_post_state_restore,
5336 .set_tss_addr = svm_set_tss_addr,
5337 .get_tdp_level = get_npt_level,
5338 .get_mt_mask = svm_get_mt_mask,
5340 .get_exit_info = svm_get_exit_info,
5342 .get_lpage_level = svm_get_lpage_level,
5344 .cpuid_update = svm_cpuid_update,
5346 .rdtscp_supported = svm_rdtscp_supported,
5347 .invpcid_supported = svm_invpcid_supported,
5348 .mpx_supported = svm_mpx_supported,
5349 .xsaves_supported = svm_xsaves_supported,
5351 .set_supported_cpuid = svm_set_supported_cpuid,
5353 .has_wbinvd_exit = svm_has_wbinvd_exit,
5355 .write_tsc_offset = svm_write_tsc_offset,
5357 .set_tdp_cr3 = set_tdp_cr3,
5359 .check_intercept = svm_check_intercept,
5360 .handle_external_intr = svm_handle_external_intr,
5362 .sched_in = svm_sched_in,
5364 .pmu_ops = &amd_pmu_ops,
5365 .deliver_posted_interrupt = svm_deliver_avic_intr,
5366 .update_pi_irte = svm_update_pi_irte,
5369 static int __init svm_init(void)
5371 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5372 __alignof__(struct vcpu_svm), THIS_MODULE);
5375 static void __exit svm_exit(void)
5380 module_init(svm_init)
5381 module_exit(svm_exit)