2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
41 #include <asm/perf_event.h>
42 #include <asm/tlbflush.h>
44 #include <asm/debugreg.h>
45 #include <asm/kvm_para.h>
46 #include <asm/irq_remapping.h>
48 #include <asm/virtext.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id svm_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_SVM),
60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62 #define IOPM_ALLOC_ORDER 2
63 #define MSRPM_ALLOC_ORDER 1
65 #define SEG_TYPE_LDT 2
66 #define SEG_TYPE_BUSY_TSS16 3
68 #define SVM_FEATURE_NPT (1 << 0)
69 #define SVM_FEATURE_LBRV (1 << 1)
70 #define SVM_FEATURE_SVML (1 << 2)
71 #define SVM_FEATURE_NRIP (1 << 3)
72 #define SVM_FEATURE_TSC_RATE (1 << 4)
73 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
74 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
75 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
76 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
78 #define SVM_AVIC_DOORBELL 0xc001011b
80 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
81 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
82 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
86 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
87 #define TSC_RATIO_MIN 0x0000000000000001ULL
88 #define TSC_RATIO_MAX 0x000000ffffffffffULL
90 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
93 * 0xff is broadcast, so the max index allowed for physical APIC ID
94 * table is 0xfe. APIC IDs above 0xff are reserved.
96 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
102 /* AVIC GATAG is encoded using VM and VCPU IDs */
103 #define AVIC_VCPU_ID_BITS 8
104 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
106 #define AVIC_VM_ID_BITS 24
107 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
108 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
110 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
111 (y & AVIC_VCPU_ID_MASK))
112 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
113 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
115 static bool erratum_383_found __read_mostly;
117 static const u32 host_save_user_msrs[] = {
119 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
122 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
130 struct nested_state {
136 /* These are the merged vectors */
139 /* gpa pointers to the real vectors */
143 /* A VMEXIT is required but not yet emulated */
146 /* cache for intercepts of the guest */
149 u32 intercept_exceptions;
152 /* Nested Paging related state */
156 #define MSRPM_OFFSETS 16
157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
160 * Set osvw_len to higher value when updated Revision Guides
161 * are published and we know what the new status bits are
163 static uint64_t osvw_len = 4, osvw_status;
166 struct kvm_vcpu vcpu;
168 unsigned long vmcb_pa;
169 struct svm_cpu_data *svm_data;
170 uint64_t asid_generation;
171 uint64_t sysenter_esp;
172 uint64_t sysenter_eip;
177 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
189 struct nested_state nested;
193 unsigned int3_injected;
194 unsigned long int3_rip;
197 /* cached guest cpuid flags for faster access */
198 bool nrips_enabled : 1;
201 struct page *avic_backing_page;
202 u64 *avic_physical_id_cache;
203 bool avic_is_running;
206 * Per-vcpu list of struct amd_svm_iommu_ir:
207 * This is used mainly to store interrupt remapping information used
208 * when update the vcpu affinity. This avoids the need to scan for
209 * IRTE and try to match ga_tag in the IOMMU driver.
211 struct list_head ir_list;
212 spinlock_t ir_list_lock;
216 * This is a wrapper of struct amd_iommu_ir_data.
218 struct amd_svm_iommu_ir {
219 struct list_head node; /* Used by SVM for per-vcpu ir_list */
220 void *data; /* Storing pointer to struct amd_ir_data */
223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
232 #define TSC_RATIO_DEFAULT 0x0100000000ULL
234 #define MSR_INVALID 0xffffffffU
236 static const struct svm_direct_access_msrs {
237 u32 index; /* Index of the MSR */
238 bool always; /* True if intercept is always on */
239 } direct_access_msrs[] = {
240 { .index = MSR_STAR, .always = true },
241 { .index = MSR_IA32_SYSENTER_CS, .always = true },
243 { .index = MSR_GS_BASE, .always = true },
244 { .index = MSR_FS_BASE, .always = true },
245 { .index = MSR_KERNEL_GS_BASE, .always = true },
246 { .index = MSR_LSTAR, .always = true },
247 { .index = MSR_CSTAR, .always = true },
248 { .index = MSR_SYSCALL_MASK, .always = true },
250 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
251 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
252 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
253 { .index = MSR_IA32_LASTINTTOIP, .always = false },
254 { .index = MSR_INVALID, .always = false },
257 /* enable NPT for AMD64 and X86 with PAE */
258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
259 static bool npt_enabled = true;
261 static bool npt_enabled;
264 /* allow nested paging (virtualized MMU) for all guests */
265 static int npt = true;
266 module_param(npt, int, S_IRUGO);
268 /* allow nested virtualization in KVM/SVM */
269 static int nested = true;
270 module_param(nested, int, S_IRUGO);
272 /* enable / disable AVIC */
274 #ifdef CONFIG_X86_LOCAL_APIC
275 module_param(avic, int, S_IRUGO);
278 /* AVIC VM ID bit masks and lock */
279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
280 static DEFINE_SPINLOCK(avic_vm_id_lock);
282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
284 static void svm_complete_interrupts(struct vcpu_svm *svm);
286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
287 static int nested_svm_intercept(struct vcpu_svm *svm);
288 static int nested_svm_vmexit(struct vcpu_svm *svm);
289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
290 bool has_error_code, u32 error_code);
293 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
294 pause filter count */
295 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
296 VMCB_ASID, /* ASID */
297 VMCB_INTR, /* int_ctl, int_vector */
298 VMCB_NPT, /* npt_en, nCR3, gPAT */
299 VMCB_CR, /* CR0, CR3, CR4, EFER */
300 VMCB_DR, /* DR6, DR7 */
301 VMCB_DT, /* GDT, IDT */
302 VMCB_SEG, /* CS, DS, SS, ES, CPL */
303 VMCB_CR2, /* CR2 only */
304 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
305 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
306 * AVIC PHYSICAL_TABLE pointer,
307 * AVIC LOGICAL_TABLE pointer
312 /* TPR and CR2 are always written before VMRUN */
313 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
315 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
317 static inline void mark_all_dirty(struct vmcb *vmcb)
319 vmcb->control.clean = 0;
322 static inline void mark_all_clean(struct vmcb *vmcb)
324 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
325 & ~VMCB_ALWAYS_DIRTY_MASK;
328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
330 vmcb->control.clean &= ~(1 << bit);
333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
335 return container_of(vcpu, struct vcpu_svm, vcpu);
338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
340 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
341 mark_dirty(svm->vmcb, VMCB_AVIC);
344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
346 struct vcpu_svm *svm = to_svm(vcpu);
347 u64 *entry = svm->avic_physical_id_cache;
352 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
355 static void recalc_intercepts(struct vcpu_svm *svm)
357 struct vmcb_control_area *c, *h;
358 struct nested_state *g;
360 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
362 if (!is_guest_mode(&svm->vcpu))
365 c = &svm->vmcb->control;
366 h = &svm->nested.hsave->control;
369 c->intercept_cr = h->intercept_cr | g->intercept_cr;
370 c->intercept_dr = h->intercept_dr | g->intercept_dr;
371 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
372 c->intercept = h->intercept | g->intercept;
375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
377 if (is_guest_mode(&svm->vcpu))
378 return svm->nested.hsave;
383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
385 struct vmcb *vmcb = get_host_vmcb(svm);
387 vmcb->control.intercept_cr |= (1U << bit);
389 recalc_intercepts(svm);
392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
394 struct vmcb *vmcb = get_host_vmcb(svm);
396 vmcb->control.intercept_cr &= ~(1U << bit);
398 recalc_intercepts(svm);
401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
403 struct vmcb *vmcb = get_host_vmcb(svm);
405 return vmcb->control.intercept_cr & (1U << bit);
408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
410 struct vmcb *vmcb = get_host_vmcb(svm);
412 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
413 | (1 << INTERCEPT_DR1_READ)
414 | (1 << INTERCEPT_DR2_READ)
415 | (1 << INTERCEPT_DR3_READ)
416 | (1 << INTERCEPT_DR4_READ)
417 | (1 << INTERCEPT_DR5_READ)
418 | (1 << INTERCEPT_DR6_READ)
419 | (1 << INTERCEPT_DR7_READ)
420 | (1 << INTERCEPT_DR0_WRITE)
421 | (1 << INTERCEPT_DR1_WRITE)
422 | (1 << INTERCEPT_DR2_WRITE)
423 | (1 << INTERCEPT_DR3_WRITE)
424 | (1 << INTERCEPT_DR4_WRITE)
425 | (1 << INTERCEPT_DR5_WRITE)
426 | (1 << INTERCEPT_DR6_WRITE)
427 | (1 << INTERCEPT_DR7_WRITE);
429 recalc_intercepts(svm);
432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
434 struct vmcb *vmcb = get_host_vmcb(svm);
436 vmcb->control.intercept_dr = 0;
438 recalc_intercepts(svm);
441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
443 struct vmcb *vmcb = get_host_vmcb(svm);
445 vmcb->control.intercept_exceptions |= (1U << bit);
447 recalc_intercepts(svm);
450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
452 struct vmcb *vmcb = get_host_vmcb(svm);
454 vmcb->control.intercept_exceptions &= ~(1U << bit);
456 recalc_intercepts(svm);
459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
461 struct vmcb *vmcb = get_host_vmcb(svm);
463 vmcb->control.intercept |= (1ULL << bit);
465 recalc_intercepts(svm);
468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
470 struct vmcb *vmcb = get_host_vmcb(svm);
472 vmcb->control.intercept &= ~(1ULL << bit);
474 recalc_intercepts(svm);
477 static inline void enable_gif(struct vcpu_svm *svm)
479 svm->vcpu.arch.hflags |= HF_GIF_MASK;
482 static inline void disable_gif(struct vcpu_svm *svm)
484 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
487 static inline bool gif_set(struct vcpu_svm *svm)
489 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
492 static unsigned long iopm_base;
494 struct kvm_ldttss_desc {
497 unsigned base1:8, type:5, dpl:2, p:1;
498 unsigned limit1:4, zero0:3, g:1, base2:8;
501 } __attribute__((packed));
503 struct svm_cpu_data {
509 struct kvm_ldttss_desc *tss_desc;
511 struct page *save_area;
514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
516 struct svm_init_data {
521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
524 #define MSRS_RANGE_SIZE 2048
525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
527 static u32 svm_msrpm_offset(u32 msr)
532 for (i = 0; i < NUM_MSR_MAPS; i++) {
533 if (msr < msrpm_ranges[i] ||
534 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
537 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
538 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
540 /* Now we have the u8 offset - but need the u32 offset */
544 /* MSR not in any range */
548 #define MAX_INST_SIZE 15
550 static inline void clgi(void)
552 asm volatile (__ex(SVM_CLGI));
555 static inline void stgi(void)
557 asm volatile (__ex(SVM_STGI));
560 static inline void invlpga(unsigned long addr, u32 asid)
562 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
565 static int get_npt_level(void)
568 return PT64_ROOT_LEVEL;
570 return PT32E_ROOT_LEVEL;
574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
576 vcpu->arch.efer = efer;
577 if (!npt_enabled && !(efer & EFER_LMA))
580 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
581 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
584 static int is_external_interrupt(u32 info)
586 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
587 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
592 struct vcpu_svm *svm = to_svm(vcpu);
595 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
596 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
602 struct vcpu_svm *svm = to_svm(vcpu);
605 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
607 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
613 struct vcpu_svm *svm = to_svm(vcpu);
615 if (svm->vmcb->control.next_rip != 0) {
616 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
617 svm->next_rip = svm->vmcb->control.next_rip;
620 if (!svm->next_rip) {
621 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
623 printk(KERN_DEBUG "%s: NOP\n", __func__);
626 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
627 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
628 __func__, kvm_rip_read(vcpu), svm->next_rip);
630 kvm_rip_write(vcpu, svm->next_rip);
631 svm_set_interrupt_shadow(vcpu, 0);
634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
635 bool has_error_code, u32 error_code,
638 struct vcpu_svm *svm = to_svm(vcpu);
641 * If we are within a nested VM we'd better #VMEXIT and let the guest
642 * handle the exception
645 nested_svm_check_exception(svm, nr, has_error_code, error_code))
648 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
649 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
652 * For guest debugging where we have to reinject #BP if some
653 * INT3 is guest-owned:
654 * Emulate nRIP by moving RIP forward. Will fail if injection
655 * raises a fault that is not intercepted. Still better than
656 * failing in all cases.
658 skip_emulated_instruction(&svm->vcpu);
659 rip = kvm_rip_read(&svm->vcpu);
660 svm->int3_rip = rip + svm->vmcb->save.cs.base;
661 svm->int3_injected = rip - old_rip;
664 svm->vmcb->control.event_inj = nr
666 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
667 | SVM_EVTINJ_TYPE_EXEPT;
668 svm->vmcb->control.event_inj_err = error_code;
671 static void svm_init_erratum_383(void)
677 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
680 /* Use _safe variants to not break nested virtualization */
681 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
687 low = lower_32_bits(val);
688 high = upper_32_bits(val);
690 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
692 erratum_383_found = true;
695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
698 * Guests should see errata 400 and 415 as fixed (assuming that
699 * HLT and IO instructions are intercepted).
701 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
702 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
705 * By increasing VCPU's osvw.length to 3 we are telling the guest that
706 * all osvw.status bits inside that length, including bit 0 (which is
707 * reserved for erratum 298), are valid. However, if host processor's
708 * osvw_len is 0 then osvw_status[0] carries no information. We need to
709 * be conservative here and therefore we tell the guest that erratum 298
710 * is present (because we really don't know).
712 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
713 vcpu->arch.osvw.status |= 1;
716 static int has_svm(void)
720 if (!cpu_has_svm(&msg)) {
721 printk(KERN_INFO "has_svm: %s\n", msg);
728 static void svm_hardware_disable(void)
730 /* Make sure we clean up behind us */
731 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
732 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
736 amd_pmu_disable_virt();
739 static int svm_hardware_enable(void)
742 struct svm_cpu_data *sd;
744 struct desc_struct *gdt;
745 int me = raw_smp_processor_id();
747 rdmsrl(MSR_EFER, efer);
748 if (efer & EFER_SVME)
752 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
755 sd = per_cpu(svm_data, me);
757 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
761 sd->asid_generation = 1;
762 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
763 sd->next_asid = sd->max_asid + 1;
765 gdt = get_current_gdt_rw();
766 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
768 wrmsrl(MSR_EFER, efer | EFER_SVME);
770 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
772 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
773 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
774 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
781 * Note that it is possible to have a system with mixed processor
782 * revisions and therefore different OSVW bits. If bits are not the same
783 * on different processors then choose the worst case (i.e. if erratum
784 * is present on one processor and not on another then assume that the
785 * erratum is present everywhere).
787 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
788 uint64_t len, status = 0;
791 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
793 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
797 osvw_status = osvw_len = 0;
801 osvw_status |= status;
802 osvw_status &= (1ULL << osvw_len) - 1;
805 osvw_status = osvw_len = 0;
807 svm_init_erratum_383();
809 amd_pmu_enable_virt();
814 static void svm_cpu_uninit(int cpu)
816 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
821 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
822 __free_page(sd->save_area);
826 static int svm_cpu_init(int cpu)
828 struct svm_cpu_data *sd;
831 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
835 sd->save_area = alloc_page(GFP_KERNEL);
840 per_cpu(svm_data, cpu) = sd;
850 static bool valid_msr_intercept(u32 index)
854 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
855 if (direct_access_msrs[i].index == index)
861 static void set_msr_interception(u32 *msrpm, unsigned msr,
864 u8 bit_read, bit_write;
869 * If this warning triggers extend the direct_access_msrs list at the
870 * beginning of the file
872 WARN_ON(!valid_msr_intercept(msr));
874 offset = svm_msrpm_offset(msr);
875 bit_read = 2 * (msr & 0x0f);
876 bit_write = 2 * (msr & 0x0f) + 1;
879 BUG_ON(offset == MSR_INVALID);
881 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
882 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
887 static void svm_vcpu_init_msrpm(u32 *msrpm)
891 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
893 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
894 if (!direct_access_msrs[i].always)
897 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
901 static void add_msr_offset(u32 offset)
905 for (i = 0; i < MSRPM_OFFSETS; ++i) {
907 /* Offset already in list? */
908 if (msrpm_offsets[i] == offset)
911 /* Slot used by another offset? */
912 if (msrpm_offsets[i] != MSR_INVALID)
915 /* Add offset to list */
916 msrpm_offsets[i] = offset;
922 * If this BUG triggers the msrpm_offsets table has an overflow. Just
923 * increase MSRPM_OFFSETS in this case.
928 static void init_msrpm_offsets(void)
932 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
934 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
937 offset = svm_msrpm_offset(direct_access_msrs[i].index);
938 BUG_ON(offset == MSR_INVALID);
940 add_msr_offset(offset);
944 static void svm_enable_lbrv(struct vcpu_svm *svm)
946 u32 *msrpm = svm->msrpm;
948 svm->vmcb->control.lbr_ctl = 1;
949 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
950 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
951 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
952 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
955 static void svm_disable_lbrv(struct vcpu_svm *svm)
957 u32 *msrpm = svm->msrpm;
959 svm->vmcb->control.lbr_ctl = 0;
960 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
961 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
962 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
963 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
967 * This hash table is used to map VM_ID to a struct kvm_arch,
968 * when handling AMD IOMMU GALOG notification to schedule in
971 #define SVM_VM_DATA_HASH_BITS 8
972 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
973 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
976 * This function is called from IOMMU driver to notify
977 * SVM to schedule in a particular vCPU of a particular VM.
979 static int avic_ga_log_notifier(u32 ga_tag)
982 struct kvm_arch *ka = NULL;
983 struct kvm_vcpu *vcpu = NULL;
984 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
985 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
987 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
989 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
990 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
991 struct kvm *kvm = container_of(ka, struct kvm, arch);
992 struct kvm_arch *vm_data = &kvm->arch;
994 if (vm_data->avic_vm_id != vm_id)
996 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
999 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1005 * At this point, the IOMMU should have already set the pending
1006 * bit in the vAPIC backing page. So, we just need to schedule
1009 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1010 kvm_vcpu_wake_up(vcpu);
1015 static __init int svm_hardware_setup(void)
1018 struct page *iopm_pages;
1022 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1027 iopm_va = page_address(iopm_pages);
1028 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1029 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1031 init_msrpm_offsets();
1033 if (boot_cpu_has(X86_FEATURE_NX))
1034 kvm_enable_efer_bits(EFER_NX);
1036 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1037 kvm_enable_efer_bits(EFER_FFXSR);
1039 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1040 kvm_has_tsc_control = true;
1041 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1042 kvm_tsc_scaling_ratio_frac_bits = 32;
1046 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1047 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1050 for_each_possible_cpu(cpu) {
1051 r = svm_cpu_init(cpu);
1056 if (!boot_cpu_has(X86_FEATURE_NPT))
1057 npt_enabled = false;
1059 if (npt_enabled && !npt) {
1060 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1061 npt_enabled = false;
1065 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1072 !boot_cpu_has(X86_FEATURE_AVIC) ||
1073 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1076 pr_info("AVIC enabled\n");
1078 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1085 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1090 static __exit void svm_hardware_unsetup(void)
1094 for_each_possible_cpu(cpu)
1095 svm_cpu_uninit(cpu);
1097 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1101 static void init_seg(struct vmcb_seg *seg)
1104 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1105 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1106 seg->limit = 0xffff;
1110 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1113 seg->attrib = SVM_SELECTOR_P_MASK | type;
1114 seg->limit = 0xffff;
1118 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1120 struct vcpu_svm *svm = to_svm(vcpu);
1121 u64 g_tsc_offset = 0;
1123 if (is_guest_mode(vcpu)) {
1124 g_tsc_offset = svm->vmcb->control.tsc_offset -
1125 svm->nested.hsave->control.tsc_offset;
1126 svm->nested.hsave->control.tsc_offset = offset;
1128 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1129 svm->vmcb->control.tsc_offset,
1132 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1134 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1137 static void avic_init_vmcb(struct vcpu_svm *svm)
1139 struct vmcb *vmcb = svm->vmcb;
1140 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1141 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1142 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1143 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1145 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1146 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1147 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1148 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1149 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1150 svm->vcpu.arch.apicv_active = true;
1153 static void init_vmcb(struct vcpu_svm *svm)
1155 struct vmcb_control_area *control = &svm->vmcb->control;
1156 struct vmcb_save_area *save = &svm->vmcb->save;
1158 svm->vcpu.arch.hflags = 0;
1160 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1161 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1162 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1163 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1164 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1165 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1166 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1167 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1169 set_dr_intercepts(svm);
1171 set_exception_intercept(svm, PF_VECTOR);
1172 set_exception_intercept(svm, UD_VECTOR);
1173 set_exception_intercept(svm, MC_VECTOR);
1174 set_exception_intercept(svm, AC_VECTOR);
1175 set_exception_intercept(svm, DB_VECTOR);
1177 set_intercept(svm, INTERCEPT_INTR);
1178 set_intercept(svm, INTERCEPT_NMI);
1179 set_intercept(svm, INTERCEPT_SMI);
1180 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1181 set_intercept(svm, INTERCEPT_RDPMC);
1182 set_intercept(svm, INTERCEPT_CPUID);
1183 set_intercept(svm, INTERCEPT_INVD);
1184 set_intercept(svm, INTERCEPT_HLT);
1185 set_intercept(svm, INTERCEPT_INVLPG);
1186 set_intercept(svm, INTERCEPT_INVLPGA);
1187 set_intercept(svm, INTERCEPT_IOIO_PROT);
1188 set_intercept(svm, INTERCEPT_MSR_PROT);
1189 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1190 set_intercept(svm, INTERCEPT_SHUTDOWN);
1191 set_intercept(svm, INTERCEPT_VMRUN);
1192 set_intercept(svm, INTERCEPT_VMMCALL);
1193 set_intercept(svm, INTERCEPT_VMLOAD);
1194 set_intercept(svm, INTERCEPT_VMSAVE);
1195 set_intercept(svm, INTERCEPT_STGI);
1196 set_intercept(svm, INTERCEPT_CLGI);
1197 set_intercept(svm, INTERCEPT_SKINIT);
1198 set_intercept(svm, INTERCEPT_WBINVD);
1199 set_intercept(svm, INTERCEPT_MONITOR);
1200 set_intercept(svm, INTERCEPT_MWAIT);
1201 set_intercept(svm, INTERCEPT_XSETBV);
1203 control->iopm_base_pa = iopm_base;
1204 control->msrpm_base_pa = __pa(svm->msrpm);
1205 control->int_ctl = V_INTR_MASKING_MASK;
1207 init_seg(&save->es);
1208 init_seg(&save->ss);
1209 init_seg(&save->ds);
1210 init_seg(&save->fs);
1211 init_seg(&save->gs);
1213 save->cs.selector = 0xf000;
1214 save->cs.base = 0xffff0000;
1215 /* Executable/Readable Code Segment */
1216 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1217 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1218 save->cs.limit = 0xffff;
1220 save->gdtr.limit = 0xffff;
1221 save->idtr.limit = 0xffff;
1223 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1224 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1226 svm_set_efer(&svm->vcpu, 0);
1227 save->dr6 = 0xffff0ff0;
1228 kvm_set_rflags(&svm->vcpu, 2);
1229 save->rip = 0x0000fff0;
1230 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1233 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1234 * It also updates the guest-visible cr0 value.
1236 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1237 kvm_mmu_reset_context(&svm->vcpu);
1239 save->cr4 = X86_CR4_PAE;
1243 /* Setup VMCB for Nested Paging */
1244 control->nested_ctl = 1;
1245 clr_intercept(svm, INTERCEPT_INVLPG);
1246 clr_exception_intercept(svm, PF_VECTOR);
1247 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1248 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1249 save->g_pat = svm->vcpu.arch.pat;
1253 svm->asid_generation = 0;
1255 svm->nested.vmcb = 0;
1256 svm->vcpu.arch.hflags = 0;
1258 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1259 control->pause_filter_count = 3000;
1260 set_intercept(svm, INTERCEPT_PAUSE);
1264 avic_init_vmcb(svm);
1266 mark_all_dirty(svm->vmcb);
1272 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1274 u64 *avic_physical_id_table;
1275 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1277 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1280 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1282 return &avic_physical_id_table[index];
1287 * AVIC hardware walks the nested page table to check permissions,
1288 * but does not use the SPA address specified in the leaf page
1289 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1290 * field of the VMCB. Therefore, we set up the
1291 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1293 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1295 struct kvm *kvm = vcpu->kvm;
1298 if (kvm->arch.apic_access_page_done)
1301 ret = x86_set_memory_region(kvm,
1302 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1303 APIC_DEFAULT_PHYS_BASE,
1308 kvm->arch.apic_access_page_done = true;
1312 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1315 u64 *entry, new_entry;
1316 int id = vcpu->vcpu_id;
1317 struct vcpu_svm *svm = to_svm(vcpu);
1319 ret = avic_init_access_page(vcpu);
1323 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1326 if (!svm->vcpu.arch.apic->regs)
1329 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1331 /* Setting AVIC backing page address in the phy APIC ID table */
1332 entry = avic_get_physical_id_entry(vcpu, id);
1336 new_entry = READ_ONCE(*entry);
1337 new_entry = (page_to_phys(svm->avic_backing_page) &
1338 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1339 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1340 WRITE_ONCE(*entry, new_entry);
1342 svm->avic_physical_id_cache = entry;
1347 static inline int avic_get_next_vm_id(void)
1351 spin_lock(&avic_vm_id_lock);
1353 /* AVIC VM ID is one-based. */
1354 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1355 if (id <= AVIC_VM_ID_MASK)
1356 __set_bit(id, avic_vm_id_bitmap);
1360 spin_unlock(&avic_vm_id_lock);
1364 static inline int avic_free_vm_id(int id)
1366 if (id <= 0 || id > AVIC_VM_ID_MASK)
1369 spin_lock(&avic_vm_id_lock);
1370 __clear_bit(id, avic_vm_id_bitmap);
1371 spin_unlock(&avic_vm_id_lock);
1375 static void avic_vm_destroy(struct kvm *kvm)
1377 unsigned long flags;
1378 struct kvm_arch *vm_data = &kvm->arch;
1380 avic_free_vm_id(vm_data->avic_vm_id);
1382 if (vm_data->avic_logical_id_table_page)
1383 __free_page(vm_data->avic_logical_id_table_page);
1384 if (vm_data->avic_physical_id_table_page)
1385 __free_page(vm_data->avic_physical_id_table_page);
1387 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1388 hash_del(&vm_data->hnode);
1389 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1392 static int avic_vm_init(struct kvm *kvm)
1394 unsigned long flags;
1395 int vm_id, err = -ENOMEM;
1396 struct kvm_arch *vm_data = &kvm->arch;
1397 struct page *p_page;
1398 struct page *l_page;
1403 vm_id = avic_get_next_vm_id();
1406 vm_data->avic_vm_id = (u32)vm_id;
1408 /* Allocating physical APIC ID table (4KB) */
1409 p_page = alloc_page(GFP_KERNEL);
1413 vm_data->avic_physical_id_table_page = p_page;
1414 clear_page(page_address(p_page));
1416 /* Allocating logical APIC ID table (4KB) */
1417 l_page = alloc_page(GFP_KERNEL);
1421 vm_data->avic_logical_id_table_page = l_page;
1422 clear_page(page_address(l_page));
1424 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1425 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1426 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1431 avic_vm_destroy(kvm);
1436 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1439 unsigned long flags;
1440 struct amd_svm_iommu_ir *ir;
1441 struct vcpu_svm *svm = to_svm(vcpu);
1443 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1447 * Here, we go through the per-vcpu ir_list to update all existing
1448 * interrupt remapping table entry targeting this vcpu.
1450 spin_lock_irqsave(&svm->ir_list_lock, flags);
1452 if (list_empty(&svm->ir_list))
1455 list_for_each_entry(ir, &svm->ir_list, node) {
1456 ret = amd_iommu_update_ga(cpu, r, ir->data);
1461 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1465 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1468 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1469 int h_physical_id = kvm_cpu_get_apicid(cpu);
1470 struct vcpu_svm *svm = to_svm(vcpu);
1472 if (!kvm_vcpu_apicv_active(vcpu))
1475 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1478 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1479 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1481 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1482 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1484 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1485 if (svm->avic_is_running)
1486 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1488 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1489 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1490 svm->avic_is_running);
1493 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1496 struct vcpu_svm *svm = to_svm(vcpu);
1498 if (!kvm_vcpu_apicv_active(vcpu))
1501 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1502 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1503 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1505 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1506 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1510 * This function is called during VCPU halt/unhalt.
1512 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1514 struct vcpu_svm *svm = to_svm(vcpu);
1516 svm->avic_is_running = is_run;
1518 avic_vcpu_load(vcpu, vcpu->cpu);
1520 avic_vcpu_put(vcpu);
1523 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1525 struct vcpu_svm *svm = to_svm(vcpu);
1530 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1531 MSR_IA32_APICBASE_ENABLE;
1532 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1533 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1537 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1538 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1540 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1541 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1544 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1546 struct vcpu_svm *svm;
1548 struct page *msrpm_pages;
1549 struct page *hsave_page;
1550 struct page *nested_msrpm_pages;
1553 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1559 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1564 page = alloc_page(GFP_KERNEL);
1568 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1572 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1573 if (!nested_msrpm_pages)
1576 hsave_page = alloc_page(GFP_KERNEL);
1581 err = avic_init_backing_page(&svm->vcpu);
1585 INIT_LIST_HEAD(&svm->ir_list);
1586 spin_lock_init(&svm->ir_list_lock);
1589 /* We initialize this flag to true to make sure that the is_running
1590 * bit would be set the first time the vcpu is loaded.
1592 svm->avic_is_running = true;
1594 svm->nested.hsave = page_address(hsave_page);
1596 svm->msrpm = page_address(msrpm_pages);
1597 svm_vcpu_init_msrpm(svm->msrpm);
1599 svm->nested.msrpm = page_address(nested_msrpm_pages);
1600 svm_vcpu_init_msrpm(svm->nested.msrpm);
1602 svm->vmcb = page_address(page);
1603 clear_page(svm->vmcb);
1604 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1605 svm->asid_generation = 0;
1608 svm_init_osvw(&svm->vcpu);
1613 __free_page(hsave_page);
1615 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1617 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1621 kvm_vcpu_uninit(&svm->vcpu);
1623 kmem_cache_free(kvm_vcpu_cache, svm);
1625 return ERR_PTR(err);
1628 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1630 struct vcpu_svm *svm = to_svm(vcpu);
1632 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1633 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1634 __free_page(virt_to_page(svm->nested.hsave));
1635 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1636 kvm_vcpu_uninit(vcpu);
1637 kmem_cache_free(kvm_vcpu_cache, svm);
1640 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1642 struct vcpu_svm *svm = to_svm(vcpu);
1645 if (unlikely(cpu != vcpu->cpu)) {
1646 svm->asid_generation = 0;
1647 mark_all_dirty(svm->vmcb);
1650 #ifdef CONFIG_X86_64
1651 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1653 savesegment(fs, svm->host.fs);
1654 savesegment(gs, svm->host.gs);
1655 svm->host.ldt = kvm_read_ldt();
1657 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1658 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1660 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1661 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1662 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1663 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1664 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1667 /* This assumes that the kernel never uses MSR_TSC_AUX */
1668 if (static_cpu_has(X86_FEATURE_RDTSCP))
1669 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1671 avic_vcpu_load(vcpu, cpu);
1674 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1676 struct vcpu_svm *svm = to_svm(vcpu);
1679 avic_vcpu_put(vcpu);
1681 ++vcpu->stat.host_state_reload;
1682 kvm_load_ldt(svm->host.ldt);
1683 #ifdef CONFIG_X86_64
1684 loadsegment(fs, svm->host.fs);
1685 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1686 load_gs_index(svm->host.gs);
1688 #ifdef CONFIG_X86_32_LAZY_GS
1689 loadsegment(gs, svm->host.gs);
1692 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1693 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1696 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1698 avic_set_running(vcpu, false);
1701 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1703 avic_set_running(vcpu, true);
1706 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1708 return to_svm(vcpu)->vmcb->save.rflags;
1711 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1714 * Any change of EFLAGS.VM is accompanied by a reload of SS
1715 * (caused by either a task switch or an inter-privilege IRET),
1716 * so we do not need to update the CPL here.
1718 to_svm(vcpu)->vmcb->save.rflags = rflags;
1721 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1726 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1729 case VCPU_EXREG_PDPTR:
1730 BUG_ON(!npt_enabled);
1731 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1738 static void svm_set_vintr(struct vcpu_svm *svm)
1740 set_intercept(svm, INTERCEPT_VINTR);
1743 static void svm_clear_vintr(struct vcpu_svm *svm)
1745 clr_intercept(svm, INTERCEPT_VINTR);
1748 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1750 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1753 case VCPU_SREG_CS: return &save->cs;
1754 case VCPU_SREG_DS: return &save->ds;
1755 case VCPU_SREG_ES: return &save->es;
1756 case VCPU_SREG_FS: return &save->fs;
1757 case VCPU_SREG_GS: return &save->gs;
1758 case VCPU_SREG_SS: return &save->ss;
1759 case VCPU_SREG_TR: return &save->tr;
1760 case VCPU_SREG_LDTR: return &save->ldtr;
1766 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1768 struct vmcb_seg *s = svm_seg(vcpu, seg);
1773 static void svm_get_segment(struct kvm_vcpu *vcpu,
1774 struct kvm_segment *var, int seg)
1776 struct vmcb_seg *s = svm_seg(vcpu, seg);
1778 var->base = s->base;
1779 var->limit = s->limit;
1780 var->selector = s->selector;
1781 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1782 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1783 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1784 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1785 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1786 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1787 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1790 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1791 * However, the SVM spec states that the G bit is not observed by the
1792 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1793 * So let's synthesize a legal G bit for all segments, this helps
1794 * running KVM nested. It also helps cross-vendor migration, because
1795 * Intel's vmentry has a check on the 'G' bit.
1797 var->g = s->limit > 0xfffff;
1800 * AMD's VMCB does not have an explicit unusable field, so emulate it
1801 * for cross vendor migration purposes by "not present"
1803 var->unusable = !var->present || (var->type == 0);
1808 * Work around a bug where the busy flag in the tr selector
1818 * The accessed bit must always be set in the segment
1819 * descriptor cache, although it can be cleared in the
1820 * descriptor, the cached bit always remains at 1. Since
1821 * Intel has a check on this, set it here to support
1822 * cross-vendor migration.
1829 * On AMD CPUs sometimes the DB bit in the segment
1830 * descriptor is left as 1, although the whole segment has
1831 * been made unusable. Clear it here to pass an Intel VMX
1832 * entry check when cross vendor migrating.
1836 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1841 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1843 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1848 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1850 struct vcpu_svm *svm = to_svm(vcpu);
1852 dt->size = svm->vmcb->save.idtr.limit;
1853 dt->address = svm->vmcb->save.idtr.base;
1856 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1858 struct vcpu_svm *svm = to_svm(vcpu);
1860 svm->vmcb->save.idtr.limit = dt->size;
1861 svm->vmcb->save.idtr.base = dt->address ;
1862 mark_dirty(svm->vmcb, VMCB_DT);
1865 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1867 struct vcpu_svm *svm = to_svm(vcpu);
1869 dt->size = svm->vmcb->save.gdtr.limit;
1870 dt->address = svm->vmcb->save.gdtr.base;
1873 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1875 struct vcpu_svm *svm = to_svm(vcpu);
1877 svm->vmcb->save.gdtr.limit = dt->size;
1878 svm->vmcb->save.gdtr.base = dt->address ;
1879 mark_dirty(svm->vmcb, VMCB_DT);
1882 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1886 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1890 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1894 static void update_cr0_intercept(struct vcpu_svm *svm)
1896 ulong gcr0 = svm->vcpu.arch.cr0;
1897 u64 *hcr0 = &svm->vmcb->save.cr0;
1899 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1900 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1902 mark_dirty(svm->vmcb, VMCB_CR);
1904 if (gcr0 == *hcr0) {
1905 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1906 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1908 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1909 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1913 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1915 struct vcpu_svm *svm = to_svm(vcpu);
1917 #ifdef CONFIG_X86_64
1918 if (vcpu->arch.efer & EFER_LME) {
1919 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1920 vcpu->arch.efer |= EFER_LMA;
1921 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1924 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1925 vcpu->arch.efer &= ~EFER_LMA;
1926 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1930 vcpu->arch.cr0 = cr0;
1933 cr0 |= X86_CR0_PG | X86_CR0_WP;
1936 * re-enable caching here because the QEMU bios
1937 * does not do it - this results in some delay at
1940 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1941 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1942 svm->vmcb->save.cr0 = cr0;
1943 mark_dirty(svm->vmcb, VMCB_CR);
1944 update_cr0_intercept(svm);
1947 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1949 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1950 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1952 if (cr4 & X86_CR4_VMXE)
1955 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1956 svm_flush_tlb(vcpu);
1958 vcpu->arch.cr4 = cr4;
1961 cr4 |= host_cr4_mce;
1962 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1963 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1967 static void svm_set_segment(struct kvm_vcpu *vcpu,
1968 struct kvm_segment *var, int seg)
1970 struct vcpu_svm *svm = to_svm(vcpu);
1971 struct vmcb_seg *s = svm_seg(vcpu, seg);
1973 s->base = var->base;
1974 s->limit = var->limit;
1975 s->selector = var->selector;
1979 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1980 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1981 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1982 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1983 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1984 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1985 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1986 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1990 * This is always accurate, except if SYSRET returned to a segment
1991 * with SS.DPL != 3. Intel does not have this quirk, and always
1992 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1993 * would entail passing the CPL to userspace and back.
1995 if (seg == VCPU_SREG_SS)
1996 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1998 mark_dirty(svm->vmcb, VMCB_SEG);
2001 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2003 struct vcpu_svm *svm = to_svm(vcpu);
2005 clr_exception_intercept(svm, BP_VECTOR);
2007 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2008 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2009 set_exception_intercept(svm, BP_VECTOR);
2011 vcpu->guest_debug = 0;
2014 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2016 if (sd->next_asid > sd->max_asid) {
2017 ++sd->asid_generation;
2019 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2022 svm->asid_generation = sd->asid_generation;
2023 svm->vmcb->control.asid = sd->next_asid++;
2025 mark_dirty(svm->vmcb, VMCB_ASID);
2028 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2030 return to_svm(vcpu)->vmcb->save.dr6;
2033 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2035 struct vcpu_svm *svm = to_svm(vcpu);
2037 svm->vmcb->save.dr6 = value;
2038 mark_dirty(svm->vmcb, VMCB_DR);
2041 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2043 struct vcpu_svm *svm = to_svm(vcpu);
2045 get_debugreg(vcpu->arch.db[0], 0);
2046 get_debugreg(vcpu->arch.db[1], 1);
2047 get_debugreg(vcpu->arch.db[2], 2);
2048 get_debugreg(vcpu->arch.db[3], 3);
2049 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2050 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2052 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2053 set_dr_intercepts(svm);
2056 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2058 struct vcpu_svm *svm = to_svm(vcpu);
2060 svm->vmcb->save.dr7 = value;
2061 mark_dirty(svm->vmcb, VMCB_DR);
2064 static int pf_interception(struct vcpu_svm *svm)
2066 u64 fault_address = svm->vmcb->control.exit_info_2;
2070 switch (svm->apf_reason) {
2072 error_code = svm->vmcb->control.exit_info_1;
2074 trace_kvm_page_fault(fault_address, error_code);
2075 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2076 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2077 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2078 svm->vmcb->control.insn_bytes,
2079 svm->vmcb->control.insn_len);
2081 case KVM_PV_REASON_PAGE_NOT_PRESENT:
2082 svm->apf_reason = 0;
2083 local_irq_disable();
2084 kvm_async_pf_task_wait(fault_address);
2087 case KVM_PV_REASON_PAGE_READY:
2088 svm->apf_reason = 0;
2089 local_irq_disable();
2090 kvm_async_pf_task_wake(fault_address);
2097 static int db_interception(struct vcpu_svm *svm)
2099 struct kvm_run *kvm_run = svm->vcpu.run;
2101 if (!(svm->vcpu.guest_debug &
2102 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2103 !svm->nmi_singlestep) {
2104 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2108 if (svm->nmi_singlestep) {
2109 svm->nmi_singlestep = false;
2110 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2111 svm->vmcb->save.rflags &=
2112 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2115 if (svm->vcpu.guest_debug &
2116 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2117 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2118 kvm_run->debug.arch.pc =
2119 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2120 kvm_run->debug.arch.exception = DB_VECTOR;
2127 static int bp_interception(struct vcpu_svm *svm)
2129 struct kvm_run *kvm_run = svm->vcpu.run;
2131 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2132 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2133 kvm_run->debug.arch.exception = BP_VECTOR;
2137 static int ud_interception(struct vcpu_svm *svm)
2141 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2142 if (er != EMULATE_DONE)
2143 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2147 static int ac_interception(struct vcpu_svm *svm)
2149 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2153 static bool is_erratum_383(void)
2158 if (!erratum_383_found)
2161 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2165 /* Bit 62 may or may not be set for this mce */
2166 value &= ~(1ULL << 62);
2168 if (value != 0xb600000000010015ULL)
2171 /* Clear MCi_STATUS registers */
2172 for (i = 0; i < 6; ++i)
2173 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2175 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2179 value &= ~(1ULL << 2);
2180 low = lower_32_bits(value);
2181 high = upper_32_bits(value);
2183 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2186 /* Flush tlb to evict multi-match entries */
2192 static void svm_handle_mce(struct vcpu_svm *svm)
2194 if (is_erratum_383()) {
2196 * Erratum 383 triggered. Guest state is corrupt so kill the
2199 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2201 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2207 * On an #MC intercept the MCE handler is not called automatically in
2208 * the host. So do it by hand here.
2212 /* not sure if we ever come back to this point */
2217 static int mc_interception(struct vcpu_svm *svm)
2222 static int shutdown_interception(struct vcpu_svm *svm)
2224 struct kvm_run *kvm_run = svm->vcpu.run;
2227 * VMCB is undefined after a SHUTDOWN intercept
2228 * so reinitialize it.
2230 clear_page(svm->vmcb);
2233 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2237 static int io_interception(struct vcpu_svm *svm)
2239 struct kvm_vcpu *vcpu = &svm->vcpu;
2240 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2241 int size, in, string;
2244 ++svm->vcpu.stat.io_exits;
2245 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2246 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2248 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2250 port = io_info >> 16;
2251 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2252 svm->next_rip = svm->vmcb->control.exit_info_2;
2253 skip_emulated_instruction(&svm->vcpu);
2255 return in ? kvm_fast_pio_in(vcpu, size, port)
2256 : kvm_fast_pio_out(vcpu, size, port);
2259 static int nmi_interception(struct vcpu_svm *svm)
2264 static int intr_interception(struct vcpu_svm *svm)
2266 ++svm->vcpu.stat.irq_exits;
2270 static int nop_on_interception(struct vcpu_svm *svm)
2275 static int halt_interception(struct vcpu_svm *svm)
2277 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2278 return kvm_emulate_halt(&svm->vcpu);
2281 static int vmmcall_interception(struct vcpu_svm *svm)
2283 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2284 return kvm_emulate_hypercall(&svm->vcpu);
2287 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2289 struct vcpu_svm *svm = to_svm(vcpu);
2291 return svm->nested.nested_cr3;
2294 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2296 struct vcpu_svm *svm = to_svm(vcpu);
2297 u64 cr3 = svm->nested.nested_cr3;
2301 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2302 offset_in_page(cr3) + index * 8, 8);
2308 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2311 struct vcpu_svm *svm = to_svm(vcpu);
2313 svm->vmcb->control.nested_cr3 = root;
2314 mark_dirty(svm->vmcb, VMCB_NPT);
2315 svm_flush_tlb(vcpu);
2318 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2319 struct x86_exception *fault)
2321 struct vcpu_svm *svm = to_svm(vcpu);
2323 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2325 * TODO: track the cause of the nested page fault, and
2326 * correctly fill in the high bits of exit_info_1.
2328 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2329 svm->vmcb->control.exit_code_hi = 0;
2330 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2331 svm->vmcb->control.exit_info_2 = fault->address;
2334 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2335 svm->vmcb->control.exit_info_1 |= fault->error_code;
2338 * The present bit is always zero for page structure faults on real
2341 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2342 svm->vmcb->control.exit_info_1 &= ~1;
2344 nested_svm_vmexit(svm);
2347 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2349 WARN_ON(mmu_is_nested(vcpu));
2350 kvm_init_shadow_mmu(vcpu);
2351 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2352 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2353 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2354 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2355 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2356 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2357 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2360 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2362 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2365 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2367 if (!(svm->vcpu.arch.efer & EFER_SVME)
2368 || !is_paging(&svm->vcpu)) {
2369 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2373 if (svm->vmcb->save.cpl) {
2374 kvm_inject_gp(&svm->vcpu, 0);
2381 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2382 bool has_error_code, u32 error_code)
2386 if (!is_guest_mode(&svm->vcpu))
2389 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2390 svm->vmcb->control.exit_code_hi = 0;
2391 svm->vmcb->control.exit_info_1 = error_code;
2392 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2394 vmexit = nested_svm_intercept(svm);
2395 if (vmexit == NESTED_EXIT_DONE)
2396 svm->nested.exit_required = true;
2401 /* This function returns true if it is save to enable the irq window */
2402 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2404 if (!is_guest_mode(&svm->vcpu))
2407 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2410 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2414 * if vmexit was already requested (by intercepted exception
2415 * for instance) do not overwrite it with "external interrupt"
2418 if (svm->nested.exit_required)
2421 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2422 svm->vmcb->control.exit_info_1 = 0;
2423 svm->vmcb->control.exit_info_2 = 0;
2425 if (svm->nested.intercept & 1ULL) {
2427 * The #vmexit can't be emulated here directly because this
2428 * code path runs with irqs and preemption disabled. A
2429 * #vmexit emulation might sleep. Only signal request for
2432 svm->nested.exit_required = true;
2433 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2440 /* This function returns true if it is save to enable the nmi window */
2441 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2443 if (!is_guest_mode(&svm->vcpu))
2446 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2449 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2450 svm->nested.exit_required = true;
2455 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2461 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2462 if (is_error_page(page))
2470 kvm_inject_gp(&svm->vcpu, 0);
2475 static void nested_svm_unmap(struct page *page)
2478 kvm_release_page_dirty(page);
2481 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2483 unsigned port, size, iopm_len;
2488 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2489 return NESTED_EXIT_HOST;
2491 port = svm->vmcb->control.exit_info_1 >> 16;
2492 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2493 SVM_IOIO_SIZE_SHIFT;
2494 gpa = svm->nested.vmcb_iopm + (port / 8);
2495 start_bit = port % 8;
2496 iopm_len = (start_bit + size > 8) ? 2 : 1;
2497 mask = (0xf >> (4 - size)) << start_bit;
2500 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2501 return NESTED_EXIT_DONE;
2503 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2506 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2508 u32 offset, msr, value;
2511 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2512 return NESTED_EXIT_HOST;
2514 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2515 offset = svm_msrpm_offset(msr);
2516 write = svm->vmcb->control.exit_info_1 & 1;
2517 mask = 1 << ((2 * (msr & 0xf)) + write);
2519 if (offset == MSR_INVALID)
2520 return NESTED_EXIT_DONE;
2522 /* Offset is in 32 bit units but need in 8 bit units */
2525 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2526 return NESTED_EXIT_DONE;
2528 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2531 static int nested_svm_exit_special(struct vcpu_svm *svm)
2533 u32 exit_code = svm->vmcb->control.exit_code;
2535 switch (exit_code) {
2538 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2539 return NESTED_EXIT_HOST;
2541 /* For now we are always handling NPFs when using them */
2543 return NESTED_EXIT_HOST;
2545 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2546 /* When we're shadowing, trap PFs, but not async PF */
2547 if (!npt_enabled && svm->apf_reason == 0)
2548 return NESTED_EXIT_HOST;
2554 return NESTED_EXIT_CONTINUE;
2558 * If this function returns true, this #vmexit was already handled
2560 static int nested_svm_intercept(struct vcpu_svm *svm)
2562 u32 exit_code = svm->vmcb->control.exit_code;
2563 int vmexit = NESTED_EXIT_HOST;
2565 switch (exit_code) {
2567 vmexit = nested_svm_exit_handled_msr(svm);
2570 vmexit = nested_svm_intercept_ioio(svm);
2572 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2573 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2574 if (svm->nested.intercept_cr & bit)
2575 vmexit = NESTED_EXIT_DONE;
2578 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2579 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2580 if (svm->nested.intercept_dr & bit)
2581 vmexit = NESTED_EXIT_DONE;
2584 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2585 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2586 if (svm->nested.intercept_exceptions & excp_bits)
2587 vmexit = NESTED_EXIT_DONE;
2588 /* async page fault always cause vmexit */
2589 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2590 svm->apf_reason != 0)
2591 vmexit = NESTED_EXIT_DONE;
2594 case SVM_EXIT_ERR: {
2595 vmexit = NESTED_EXIT_DONE;
2599 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2600 if (svm->nested.intercept & exit_bits)
2601 vmexit = NESTED_EXIT_DONE;
2608 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2612 vmexit = nested_svm_intercept(svm);
2614 if (vmexit == NESTED_EXIT_DONE)
2615 nested_svm_vmexit(svm);
2620 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2622 struct vmcb_control_area *dst = &dst_vmcb->control;
2623 struct vmcb_control_area *from = &from_vmcb->control;
2625 dst->intercept_cr = from->intercept_cr;
2626 dst->intercept_dr = from->intercept_dr;
2627 dst->intercept_exceptions = from->intercept_exceptions;
2628 dst->intercept = from->intercept;
2629 dst->iopm_base_pa = from->iopm_base_pa;
2630 dst->msrpm_base_pa = from->msrpm_base_pa;
2631 dst->tsc_offset = from->tsc_offset;
2632 dst->asid = from->asid;
2633 dst->tlb_ctl = from->tlb_ctl;
2634 dst->int_ctl = from->int_ctl;
2635 dst->int_vector = from->int_vector;
2636 dst->int_state = from->int_state;
2637 dst->exit_code = from->exit_code;
2638 dst->exit_code_hi = from->exit_code_hi;
2639 dst->exit_info_1 = from->exit_info_1;
2640 dst->exit_info_2 = from->exit_info_2;
2641 dst->exit_int_info = from->exit_int_info;
2642 dst->exit_int_info_err = from->exit_int_info_err;
2643 dst->nested_ctl = from->nested_ctl;
2644 dst->event_inj = from->event_inj;
2645 dst->event_inj_err = from->event_inj_err;
2646 dst->nested_cr3 = from->nested_cr3;
2647 dst->lbr_ctl = from->lbr_ctl;
2650 static int nested_svm_vmexit(struct vcpu_svm *svm)
2652 struct vmcb *nested_vmcb;
2653 struct vmcb *hsave = svm->nested.hsave;
2654 struct vmcb *vmcb = svm->vmcb;
2657 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2658 vmcb->control.exit_info_1,
2659 vmcb->control.exit_info_2,
2660 vmcb->control.exit_int_info,
2661 vmcb->control.exit_int_info_err,
2664 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2668 /* Exit Guest-Mode */
2669 leave_guest_mode(&svm->vcpu);
2670 svm->nested.vmcb = 0;
2672 /* Give the current vmcb to the guest */
2675 nested_vmcb->save.es = vmcb->save.es;
2676 nested_vmcb->save.cs = vmcb->save.cs;
2677 nested_vmcb->save.ss = vmcb->save.ss;
2678 nested_vmcb->save.ds = vmcb->save.ds;
2679 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2680 nested_vmcb->save.idtr = vmcb->save.idtr;
2681 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2682 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2683 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2684 nested_vmcb->save.cr2 = vmcb->save.cr2;
2685 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2686 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2687 nested_vmcb->save.rip = vmcb->save.rip;
2688 nested_vmcb->save.rsp = vmcb->save.rsp;
2689 nested_vmcb->save.rax = vmcb->save.rax;
2690 nested_vmcb->save.dr7 = vmcb->save.dr7;
2691 nested_vmcb->save.dr6 = vmcb->save.dr6;
2692 nested_vmcb->save.cpl = vmcb->save.cpl;
2694 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2695 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2696 nested_vmcb->control.int_state = vmcb->control.int_state;
2697 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2698 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2699 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2700 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2701 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2702 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2704 if (svm->nrips_enabled)
2705 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2708 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2709 * to make sure that we do not lose injected events. So check event_inj
2710 * here and copy it to exit_int_info if it is valid.
2711 * Exit_int_info and event_inj can't be both valid because the case
2712 * below only happens on a VMRUN instruction intercept which has
2713 * no valid exit_int_info set.
2715 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2716 struct vmcb_control_area *nc = &nested_vmcb->control;
2718 nc->exit_int_info = vmcb->control.event_inj;
2719 nc->exit_int_info_err = vmcb->control.event_inj_err;
2722 nested_vmcb->control.tlb_ctl = 0;
2723 nested_vmcb->control.event_inj = 0;
2724 nested_vmcb->control.event_inj_err = 0;
2726 /* We always set V_INTR_MASKING and remember the old value in hflags */
2727 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2728 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2730 /* Restore the original control entries */
2731 copy_vmcb_control_area(vmcb, hsave);
2733 kvm_clear_exception_queue(&svm->vcpu);
2734 kvm_clear_interrupt_queue(&svm->vcpu);
2736 svm->nested.nested_cr3 = 0;
2738 /* Restore selected save entries */
2739 svm->vmcb->save.es = hsave->save.es;
2740 svm->vmcb->save.cs = hsave->save.cs;
2741 svm->vmcb->save.ss = hsave->save.ss;
2742 svm->vmcb->save.ds = hsave->save.ds;
2743 svm->vmcb->save.gdtr = hsave->save.gdtr;
2744 svm->vmcb->save.idtr = hsave->save.idtr;
2745 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2746 svm_set_efer(&svm->vcpu, hsave->save.efer);
2747 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2748 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2750 svm->vmcb->save.cr3 = hsave->save.cr3;
2751 svm->vcpu.arch.cr3 = hsave->save.cr3;
2753 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2755 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2756 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2757 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2758 svm->vmcb->save.dr7 = 0;
2759 svm->vmcb->save.cpl = 0;
2760 svm->vmcb->control.exit_int_info = 0;
2762 mark_all_dirty(svm->vmcb);
2764 nested_svm_unmap(page);
2766 nested_svm_uninit_mmu_context(&svm->vcpu);
2767 kvm_mmu_reset_context(&svm->vcpu);
2768 kvm_mmu_load(&svm->vcpu);
2773 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2776 * This function merges the msr permission bitmaps of kvm and the
2777 * nested vmcb. It is optimized in that it only merges the parts where
2778 * the kvm msr permission bitmap may contain zero bits
2782 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2785 for (i = 0; i < MSRPM_OFFSETS; i++) {
2789 if (msrpm_offsets[i] == 0xffffffff)
2792 p = msrpm_offsets[i];
2793 offset = svm->nested.vmcb_msrpm + (p * 4);
2795 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2798 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2801 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2806 static bool nested_vmcb_checks(struct vmcb *vmcb)
2808 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2811 if (vmcb->control.asid == 0)
2814 if (vmcb->control.nested_ctl && !npt_enabled)
2820 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2822 struct vmcb *nested_vmcb;
2823 struct vmcb *hsave = svm->nested.hsave;
2824 struct vmcb *vmcb = svm->vmcb;
2828 vmcb_gpa = svm->vmcb->save.rax;
2830 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2834 if (!nested_vmcb_checks(nested_vmcb)) {
2835 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2836 nested_vmcb->control.exit_code_hi = 0;
2837 nested_vmcb->control.exit_info_1 = 0;
2838 nested_vmcb->control.exit_info_2 = 0;
2840 nested_svm_unmap(page);
2845 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2846 nested_vmcb->save.rip,
2847 nested_vmcb->control.int_ctl,
2848 nested_vmcb->control.event_inj,
2849 nested_vmcb->control.nested_ctl);
2851 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2852 nested_vmcb->control.intercept_cr >> 16,
2853 nested_vmcb->control.intercept_exceptions,
2854 nested_vmcb->control.intercept);
2856 /* Clear internal status */
2857 kvm_clear_exception_queue(&svm->vcpu);
2858 kvm_clear_interrupt_queue(&svm->vcpu);
2861 * Save the old vmcb, so we don't need to pick what we save, but can
2862 * restore everything when a VMEXIT occurs
2864 hsave->save.es = vmcb->save.es;
2865 hsave->save.cs = vmcb->save.cs;
2866 hsave->save.ss = vmcb->save.ss;
2867 hsave->save.ds = vmcb->save.ds;
2868 hsave->save.gdtr = vmcb->save.gdtr;
2869 hsave->save.idtr = vmcb->save.idtr;
2870 hsave->save.efer = svm->vcpu.arch.efer;
2871 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2872 hsave->save.cr4 = svm->vcpu.arch.cr4;
2873 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2874 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2875 hsave->save.rsp = vmcb->save.rsp;
2876 hsave->save.rax = vmcb->save.rax;
2878 hsave->save.cr3 = vmcb->save.cr3;
2880 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2882 copy_vmcb_control_area(hsave, vmcb);
2884 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2885 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2887 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2889 if (nested_vmcb->control.nested_ctl) {
2890 kvm_mmu_unload(&svm->vcpu);
2891 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2892 nested_svm_init_mmu_context(&svm->vcpu);
2895 /* Load the nested guest state */
2896 svm->vmcb->save.es = nested_vmcb->save.es;
2897 svm->vmcb->save.cs = nested_vmcb->save.cs;
2898 svm->vmcb->save.ss = nested_vmcb->save.ss;
2899 svm->vmcb->save.ds = nested_vmcb->save.ds;
2900 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2901 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2902 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2903 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2904 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2905 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2907 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2908 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2910 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2912 /* Guest paging mode is active - reset mmu */
2913 kvm_mmu_reset_context(&svm->vcpu);
2915 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2916 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2917 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2918 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2920 /* In case we don't even reach vcpu_run, the fields are not updated */
2921 svm->vmcb->save.rax = nested_vmcb->save.rax;
2922 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2923 svm->vmcb->save.rip = nested_vmcb->save.rip;
2924 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2925 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2926 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2928 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2929 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2931 /* cache intercepts */
2932 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2933 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2934 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2935 svm->nested.intercept = nested_vmcb->control.intercept;
2937 svm_flush_tlb(&svm->vcpu);
2938 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2939 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2940 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2942 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2944 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2945 /* We only want the cr8 intercept bits of the guest */
2946 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2947 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2950 /* We don't want to see VMMCALLs from a nested guest */
2951 clr_intercept(svm, INTERCEPT_VMMCALL);
2953 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2954 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2955 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2956 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2957 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2958 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2960 nested_svm_unmap(page);
2962 /* Enter Guest-Mode */
2963 enter_guest_mode(&svm->vcpu);
2966 * Merge guest and host intercepts - must be called with vcpu in
2967 * guest-mode to take affect here
2969 recalc_intercepts(svm);
2971 svm->nested.vmcb = vmcb_gpa;
2975 mark_all_dirty(svm->vmcb);
2980 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2982 to_vmcb->save.fs = from_vmcb->save.fs;
2983 to_vmcb->save.gs = from_vmcb->save.gs;
2984 to_vmcb->save.tr = from_vmcb->save.tr;
2985 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2986 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2987 to_vmcb->save.star = from_vmcb->save.star;
2988 to_vmcb->save.lstar = from_vmcb->save.lstar;
2989 to_vmcb->save.cstar = from_vmcb->save.cstar;
2990 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2991 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2992 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2993 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2996 static int vmload_interception(struct vcpu_svm *svm)
2998 struct vmcb *nested_vmcb;
3001 if (nested_svm_check_permissions(svm))
3004 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3008 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3009 skip_emulated_instruction(&svm->vcpu);
3011 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3012 nested_svm_unmap(page);
3017 static int vmsave_interception(struct vcpu_svm *svm)
3019 struct vmcb *nested_vmcb;
3022 if (nested_svm_check_permissions(svm))
3025 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3029 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3030 skip_emulated_instruction(&svm->vcpu);
3032 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3033 nested_svm_unmap(page);
3038 static int vmrun_interception(struct vcpu_svm *svm)
3040 if (nested_svm_check_permissions(svm))
3043 /* Save rip after vmrun instruction */
3044 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3046 if (!nested_svm_vmrun(svm))
3049 if (!nested_svm_vmrun_msrpm(svm))
3056 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3057 svm->vmcb->control.exit_code_hi = 0;
3058 svm->vmcb->control.exit_info_1 = 0;
3059 svm->vmcb->control.exit_info_2 = 0;
3061 nested_svm_vmexit(svm);
3066 static int stgi_interception(struct vcpu_svm *svm)
3068 if (nested_svm_check_permissions(svm))
3071 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3072 skip_emulated_instruction(&svm->vcpu);
3073 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3080 static int clgi_interception(struct vcpu_svm *svm)
3082 if (nested_svm_check_permissions(svm))
3085 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3086 skip_emulated_instruction(&svm->vcpu);
3090 /* After a CLGI no interrupts should come */
3091 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3092 svm_clear_vintr(svm);
3093 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3094 mark_dirty(svm->vmcb, VMCB_INTR);
3100 static int invlpga_interception(struct vcpu_svm *svm)
3102 struct kvm_vcpu *vcpu = &svm->vcpu;
3104 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3105 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3107 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3108 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3110 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3111 skip_emulated_instruction(&svm->vcpu);
3115 static int skinit_interception(struct vcpu_svm *svm)
3117 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3119 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3123 static int wbinvd_interception(struct vcpu_svm *svm)
3125 return kvm_emulate_wbinvd(&svm->vcpu);
3128 static int xsetbv_interception(struct vcpu_svm *svm)
3130 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3131 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3133 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3134 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3135 skip_emulated_instruction(&svm->vcpu);
3141 static int task_switch_interception(struct vcpu_svm *svm)
3145 int int_type = svm->vmcb->control.exit_int_info &
3146 SVM_EXITINTINFO_TYPE_MASK;
3147 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3149 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3151 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3152 bool has_error_code = false;
3155 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3157 if (svm->vmcb->control.exit_info_2 &
3158 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3159 reason = TASK_SWITCH_IRET;
3160 else if (svm->vmcb->control.exit_info_2 &
3161 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3162 reason = TASK_SWITCH_JMP;
3164 reason = TASK_SWITCH_GATE;
3166 reason = TASK_SWITCH_CALL;
3168 if (reason == TASK_SWITCH_GATE) {
3170 case SVM_EXITINTINFO_TYPE_NMI:
3171 svm->vcpu.arch.nmi_injected = false;
3173 case SVM_EXITINTINFO_TYPE_EXEPT:
3174 if (svm->vmcb->control.exit_info_2 &
3175 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3176 has_error_code = true;
3178 (u32)svm->vmcb->control.exit_info_2;
3180 kvm_clear_exception_queue(&svm->vcpu);
3182 case SVM_EXITINTINFO_TYPE_INTR:
3183 kvm_clear_interrupt_queue(&svm->vcpu);
3190 if (reason != TASK_SWITCH_GATE ||
3191 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3192 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3193 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3194 skip_emulated_instruction(&svm->vcpu);
3196 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3199 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3200 has_error_code, error_code) == EMULATE_FAIL) {
3201 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3202 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3203 svm->vcpu.run->internal.ndata = 0;
3209 static int cpuid_interception(struct vcpu_svm *svm)
3211 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3212 return kvm_emulate_cpuid(&svm->vcpu);
3215 static int iret_interception(struct vcpu_svm *svm)
3217 ++svm->vcpu.stat.nmi_window_exits;
3218 clr_intercept(svm, INTERCEPT_IRET);
3219 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3220 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3221 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3225 static int invlpg_interception(struct vcpu_svm *svm)
3227 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3228 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3230 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3231 skip_emulated_instruction(&svm->vcpu);
3235 static int emulate_on_interception(struct vcpu_svm *svm)
3237 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3240 static int rdpmc_interception(struct vcpu_svm *svm)
3244 if (!static_cpu_has(X86_FEATURE_NRIPS))
3245 return emulate_on_interception(svm);
3247 err = kvm_rdpmc(&svm->vcpu);
3248 return kvm_complete_insn_gp(&svm->vcpu, err);
3251 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3254 unsigned long cr0 = svm->vcpu.arch.cr0;
3258 intercept = svm->nested.intercept;
3260 if (!is_guest_mode(&svm->vcpu) ||
3261 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3264 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3265 val &= ~SVM_CR0_SELECTIVE_MASK;
3268 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3269 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3275 #define CR_VALID (1ULL << 63)
3277 static int cr_interception(struct vcpu_svm *svm)
3283 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3284 return emulate_on_interception(svm);
3286 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3287 return emulate_on_interception(svm);
3289 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3290 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3291 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3293 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3296 if (cr >= 16) { /* mov to cr */
3298 val = kvm_register_read(&svm->vcpu, reg);
3301 if (!check_selective_cr0_intercepted(svm, val))
3302 err = kvm_set_cr0(&svm->vcpu, val);
3308 err = kvm_set_cr3(&svm->vcpu, val);
3311 err = kvm_set_cr4(&svm->vcpu, val);
3314 err = kvm_set_cr8(&svm->vcpu, val);
3317 WARN(1, "unhandled write to CR%d", cr);
3318 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3321 } else { /* mov from cr */
3324 val = kvm_read_cr0(&svm->vcpu);
3327 val = svm->vcpu.arch.cr2;
3330 val = kvm_read_cr3(&svm->vcpu);
3333 val = kvm_read_cr4(&svm->vcpu);
3336 val = kvm_get_cr8(&svm->vcpu);
3339 WARN(1, "unhandled read from CR%d", cr);
3340 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3343 kvm_register_write(&svm->vcpu, reg, val);
3345 return kvm_complete_insn_gp(&svm->vcpu, err);
3348 static int dr_interception(struct vcpu_svm *svm)
3353 if (svm->vcpu.guest_debug == 0) {
3355 * No more DR vmexits; force a reload of the debug registers
3356 * and reenter on this instruction. The next vmexit will
3357 * retrieve the full state of the debug registers.
3359 clr_dr_intercepts(svm);
3360 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3364 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3365 return emulate_on_interception(svm);
3367 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3368 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3370 if (dr >= 16) { /* mov to DRn */
3371 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3373 val = kvm_register_read(&svm->vcpu, reg);
3374 kvm_set_dr(&svm->vcpu, dr - 16, val);
3376 if (!kvm_require_dr(&svm->vcpu, dr))
3378 kvm_get_dr(&svm->vcpu, dr, &val);
3379 kvm_register_write(&svm->vcpu, reg, val);
3382 skip_emulated_instruction(&svm->vcpu);
3387 static int cr8_write_interception(struct vcpu_svm *svm)
3389 struct kvm_run *kvm_run = svm->vcpu.run;
3392 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3393 /* instruction emulation calls kvm_set_cr8() */
3394 r = cr_interception(svm);
3395 if (lapic_in_kernel(&svm->vcpu))
3397 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3399 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3403 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3405 struct vcpu_svm *svm = to_svm(vcpu);
3407 switch (msr_info->index) {
3408 case MSR_IA32_TSC: {
3409 msr_info->data = svm->vmcb->control.tsc_offset +
3410 kvm_scale_tsc(vcpu, rdtsc());
3415 msr_info->data = svm->vmcb->save.star;
3417 #ifdef CONFIG_X86_64
3419 msr_info->data = svm->vmcb->save.lstar;
3422 msr_info->data = svm->vmcb->save.cstar;
3424 case MSR_KERNEL_GS_BASE:
3425 msr_info->data = svm->vmcb->save.kernel_gs_base;
3427 case MSR_SYSCALL_MASK:
3428 msr_info->data = svm->vmcb->save.sfmask;
3431 case MSR_IA32_SYSENTER_CS:
3432 msr_info->data = svm->vmcb->save.sysenter_cs;
3434 case MSR_IA32_SYSENTER_EIP:
3435 msr_info->data = svm->sysenter_eip;
3437 case MSR_IA32_SYSENTER_ESP:
3438 msr_info->data = svm->sysenter_esp;
3441 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3443 msr_info->data = svm->tsc_aux;
3446 * Nobody will change the following 5 values in the VMCB so we can
3447 * safely return them on rdmsr. They will always be 0 until LBRV is
3450 case MSR_IA32_DEBUGCTLMSR:
3451 msr_info->data = svm->vmcb->save.dbgctl;
3453 case MSR_IA32_LASTBRANCHFROMIP:
3454 msr_info->data = svm->vmcb->save.br_from;
3456 case MSR_IA32_LASTBRANCHTOIP:
3457 msr_info->data = svm->vmcb->save.br_to;
3459 case MSR_IA32_LASTINTFROMIP:
3460 msr_info->data = svm->vmcb->save.last_excp_from;
3462 case MSR_IA32_LASTINTTOIP:
3463 msr_info->data = svm->vmcb->save.last_excp_to;
3465 case MSR_VM_HSAVE_PA:
3466 msr_info->data = svm->nested.hsave_msr;
3469 msr_info->data = svm->nested.vm_cr_msr;
3471 case MSR_IA32_UCODE_REV:
3472 msr_info->data = 0x01000065;
3474 case MSR_F15H_IC_CFG: {
3478 family = guest_cpuid_family(vcpu);
3479 model = guest_cpuid_model(vcpu);
3481 if (family < 0 || model < 0)
3482 return kvm_get_msr_common(vcpu, msr_info);
3486 if (family == 0x15 &&
3487 (model >= 0x2 && model < 0x20))
3488 msr_info->data = 0x1E;
3492 return kvm_get_msr_common(vcpu, msr_info);
3497 static int rdmsr_interception(struct vcpu_svm *svm)
3499 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3500 struct msr_data msr_info;
3502 msr_info.index = ecx;
3503 msr_info.host_initiated = false;
3504 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3505 trace_kvm_msr_read_ex(ecx);
3506 kvm_inject_gp(&svm->vcpu, 0);
3508 trace_kvm_msr_read(ecx, msr_info.data);
3510 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3511 msr_info.data & 0xffffffff);
3512 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3513 msr_info.data >> 32);
3514 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3515 skip_emulated_instruction(&svm->vcpu);
3520 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3522 struct vcpu_svm *svm = to_svm(vcpu);
3523 int svm_dis, chg_mask;
3525 if (data & ~SVM_VM_CR_VALID_MASK)
3528 chg_mask = SVM_VM_CR_VALID_MASK;
3530 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3531 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3533 svm->nested.vm_cr_msr &= ~chg_mask;
3534 svm->nested.vm_cr_msr |= (data & chg_mask);
3536 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3538 /* check for svm_disable while efer.svme is set */
3539 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3545 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3547 struct vcpu_svm *svm = to_svm(vcpu);
3549 u32 ecx = msr->index;
3550 u64 data = msr->data;
3553 kvm_write_tsc(vcpu, msr);
3556 svm->vmcb->save.star = data;
3558 #ifdef CONFIG_X86_64
3560 svm->vmcb->save.lstar = data;
3563 svm->vmcb->save.cstar = data;
3565 case MSR_KERNEL_GS_BASE:
3566 svm->vmcb->save.kernel_gs_base = data;
3568 case MSR_SYSCALL_MASK:
3569 svm->vmcb->save.sfmask = data;
3572 case MSR_IA32_SYSENTER_CS:
3573 svm->vmcb->save.sysenter_cs = data;
3575 case MSR_IA32_SYSENTER_EIP:
3576 svm->sysenter_eip = data;
3577 svm->vmcb->save.sysenter_eip = data;
3579 case MSR_IA32_SYSENTER_ESP:
3580 svm->sysenter_esp = data;
3581 svm->vmcb->save.sysenter_esp = data;
3584 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3588 * This is rare, so we update the MSR here instead of using
3589 * direct_access_msrs. Doing that would require a rdmsr in
3592 svm->tsc_aux = data;
3593 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3595 case MSR_IA32_DEBUGCTLMSR:
3596 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3597 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3601 if (data & DEBUGCTL_RESERVED_BITS)
3604 svm->vmcb->save.dbgctl = data;
3605 mark_dirty(svm->vmcb, VMCB_LBR);
3606 if (data & (1ULL<<0))
3607 svm_enable_lbrv(svm);
3609 svm_disable_lbrv(svm);
3611 case MSR_VM_HSAVE_PA:
3612 svm->nested.hsave_msr = data;
3615 return svm_set_vm_cr(vcpu, data);
3617 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3619 case MSR_IA32_APICBASE:
3620 if (kvm_vcpu_apicv_active(vcpu))
3621 avic_update_vapic_bar(to_svm(vcpu), data);
3622 /* Follow through */
3624 return kvm_set_msr_common(vcpu, msr);
3629 static int wrmsr_interception(struct vcpu_svm *svm)
3631 struct msr_data msr;
3632 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3633 u64 data = kvm_read_edx_eax(&svm->vcpu);
3637 msr.host_initiated = false;
3639 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3640 if (kvm_set_msr(&svm->vcpu, &msr)) {
3641 trace_kvm_msr_write_ex(ecx, data);
3642 kvm_inject_gp(&svm->vcpu, 0);
3644 trace_kvm_msr_write(ecx, data);
3645 skip_emulated_instruction(&svm->vcpu);
3650 static int msr_interception(struct vcpu_svm *svm)
3652 if (svm->vmcb->control.exit_info_1)
3653 return wrmsr_interception(svm);
3655 return rdmsr_interception(svm);
3658 static int interrupt_window_interception(struct vcpu_svm *svm)
3660 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3661 svm_clear_vintr(svm);
3662 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3663 mark_dirty(svm->vmcb, VMCB_INTR);
3664 ++svm->vcpu.stat.irq_window_exits;
3668 static int pause_interception(struct vcpu_svm *svm)
3670 kvm_vcpu_on_spin(&(svm->vcpu));
3674 static int nop_interception(struct vcpu_svm *svm)
3676 skip_emulated_instruction(&(svm->vcpu));
3680 static int monitor_interception(struct vcpu_svm *svm)
3682 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3683 return nop_interception(svm);
3686 static int mwait_interception(struct vcpu_svm *svm)
3688 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3689 return nop_interception(svm);
3692 enum avic_ipi_failure_cause {
3693 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3694 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3695 AVIC_IPI_FAILURE_INVALID_TARGET,
3696 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3699 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3701 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3702 u32 icrl = svm->vmcb->control.exit_info_1;
3703 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3704 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3705 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3707 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3710 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3712 * AVIC hardware handles the generation of
3713 * IPIs when the specified Message Type is Fixed
3714 * (also known as fixed delivery mode) and
3715 * the Trigger Mode is edge-triggered. The hardware
3716 * also supports self and broadcast delivery modes
3717 * specified via the Destination Shorthand(DSH)
3718 * field of the ICRL. Logical and physical APIC ID
3719 * formats are supported. All other IPI types cause
3720 * a #VMEXIT, which needs to emulated.
3722 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3723 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3725 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3727 struct kvm_vcpu *vcpu;
3728 struct kvm *kvm = svm->vcpu.kvm;
3729 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3732 * At this point, we expect that the AVIC HW has already
3733 * set the appropriate IRR bits on the valid target
3734 * vcpus. So, we just need to kick the appropriate vcpu.
3736 kvm_for_each_vcpu(i, vcpu, kvm) {
3737 bool m = kvm_apic_match_dest(vcpu, apic,
3738 icrl & KVM_APIC_SHORT_MASK,
3739 GET_APIC_DEST_FIELD(icrh),
3740 icrl & KVM_APIC_DEST_MASK);
3742 if (m && !avic_vcpu_is_running(vcpu))
3743 kvm_vcpu_wake_up(vcpu);
3747 case AVIC_IPI_FAILURE_INVALID_TARGET:
3749 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3750 WARN_ONCE(1, "Invalid backing page\n");
3753 pr_err("Unknown IPI interception\n");
3759 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3761 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3763 u32 *logical_apic_id_table;
3764 int dlid = GET_APIC_LOGICAL_ID(ldr);
3769 if (flat) { /* flat */
3770 index = ffs(dlid) - 1;
3773 } else { /* cluster */
3774 int cluster = (dlid & 0xf0) >> 4;
3775 int apic = ffs(dlid & 0x0f) - 1;
3777 if ((apic < 0) || (apic > 7) ||
3780 index = (cluster << 2) + apic;
3783 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3785 return &logical_apic_id_table[index];
3788 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3792 u32 *entry, new_entry;
3794 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3795 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3799 new_entry = READ_ONCE(*entry);
3800 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3801 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3803 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3805 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3806 WRITE_ONCE(*entry, new_entry);
3811 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3814 struct vcpu_svm *svm = to_svm(vcpu);
3815 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3820 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3821 if (ret && svm->ldr_reg) {
3822 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3830 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3833 struct vcpu_svm *svm = to_svm(vcpu);
3834 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3835 u32 id = (apic_id_reg >> 24) & 0xff;
3837 if (vcpu->vcpu_id == id)
3840 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3841 new = avic_get_physical_id_entry(vcpu, id);
3845 /* We need to move physical_id_entry to new offset */
3848 to_svm(vcpu)->avic_physical_id_cache = new;
3851 * Also update the guest physical APIC ID in the logical
3852 * APIC ID table entry if already setup the LDR.
3855 avic_handle_ldr_update(vcpu);
3860 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3862 struct vcpu_svm *svm = to_svm(vcpu);
3863 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3864 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3865 u32 mod = (dfr >> 28) & 0xf;
3868 * We assume that all local APICs are using the same type.
3869 * If this changes, we need to flush the AVIC logical
3872 if (vm_data->ldr_mode == mod)
3875 clear_page(page_address(vm_data->avic_logical_id_table_page));
3876 vm_data->ldr_mode = mod;
3879 avic_handle_ldr_update(vcpu);
3883 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3885 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3886 u32 offset = svm->vmcb->control.exit_info_1 &
3887 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3891 if (avic_handle_apic_id_update(&svm->vcpu))
3895 if (avic_handle_ldr_update(&svm->vcpu))
3899 avic_handle_dfr_update(&svm->vcpu);
3905 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3910 static bool is_avic_unaccelerated_access_trap(u32 offset)
3939 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3942 u32 offset = svm->vmcb->control.exit_info_1 &
3943 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3944 u32 vector = svm->vmcb->control.exit_info_2 &
3945 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3946 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3947 AVIC_UNACCEL_ACCESS_WRITE_MASK;
3948 bool trap = is_avic_unaccelerated_access_trap(offset);
3950 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3951 trap, write, vector);
3954 WARN_ONCE(!write, "svm: Handling trap read.\n");
3955 ret = avic_unaccel_trap_write(svm);
3957 /* Handling Fault */
3958 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3964 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3965 [SVM_EXIT_READ_CR0] = cr_interception,
3966 [SVM_EXIT_READ_CR3] = cr_interception,
3967 [SVM_EXIT_READ_CR4] = cr_interception,
3968 [SVM_EXIT_READ_CR8] = cr_interception,
3969 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3970 [SVM_EXIT_WRITE_CR0] = cr_interception,
3971 [SVM_EXIT_WRITE_CR3] = cr_interception,
3972 [SVM_EXIT_WRITE_CR4] = cr_interception,
3973 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3974 [SVM_EXIT_READ_DR0] = dr_interception,
3975 [SVM_EXIT_READ_DR1] = dr_interception,
3976 [SVM_EXIT_READ_DR2] = dr_interception,
3977 [SVM_EXIT_READ_DR3] = dr_interception,
3978 [SVM_EXIT_READ_DR4] = dr_interception,
3979 [SVM_EXIT_READ_DR5] = dr_interception,
3980 [SVM_EXIT_READ_DR6] = dr_interception,
3981 [SVM_EXIT_READ_DR7] = dr_interception,
3982 [SVM_EXIT_WRITE_DR0] = dr_interception,
3983 [SVM_EXIT_WRITE_DR1] = dr_interception,
3984 [SVM_EXIT_WRITE_DR2] = dr_interception,
3985 [SVM_EXIT_WRITE_DR3] = dr_interception,
3986 [SVM_EXIT_WRITE_DR4] = dr_interception,
3987 [SVM_EXIT_WRITE_DR5] = dr_interception,
3988 [SVM_EXIT_WRITE_DR6] = dr_interception,
3989 [SVM_EXIT_WRITE_DR7] = dr_interception,
3990 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3991 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3992 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3993 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3994 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3995 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3996 [SVM_EXIT_INTR] = intr_interception,
3997 [SVM_EXIT_NMI] = nmi_interception,
3998 [SVM_EXIT_SMI] = nop_on_interception,
3999 [SVM_EXIT_INIT] = nop_on_interception,
4000 [SVM_EXIT_VINTR] = interrupt_window_interception,
4001 [SVM_EXIT_RDPMC] = rdpmc_interception,
4002 [SVM_EXIT_CPUID] = cpuid_interception,
4003 [SVM_EXIT_IRET] = iret_interception,
4004 [SVM_EXIT_INVD] = emulate_on_interception,
4005 [SVM_EXIT_PAUSE] = pause_interception,
4006 [SVM_EXIT_HLT] = halt_interception,
4007 [SVM_EXIT_INVLPG] = invlpg_interception,
4008 [SVM_EXIT_INVLPGA] = invlpga_interception,
4009 [SVM_EXIT_IOIO] = io_interception,
4010 [SVM_EXIT_MSR] = msr_interception,
4011 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4012 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4013 [SVM_EXIT_VMRUN] = vmrun_interception,
4014 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4015 [SVM_EXIT_VMLOAD] = vmload_interception,
4016 [SVM_EXIT_VMSAVE] = vmsave_interception,
4017 [SVM_EXIT_STGI] = stgi_interception,
4018 [SVM_EXIT_CLGI] = clgi_interception,
4019 [SVM_EXIT_SKINIT] = skinit_interception,
4020 [SVM_EXIT_WBINVD] = wbinvd_interception,
4021 [SVM_EXIT_MONITOR] = monitor_interception,
4022 [SVM_EXIT_MWAIT] = mwait_interception,
4023 [SVM_EXIT_XSETBV] = xsetbv_interception,
4024 [SVM_EXIT_NPF] = pf_interception,
4025 [SVM_EXIT_RSM] = emulate_on_interception,
4026 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4027 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4030 static void dump_vmcb(struct kvm_vcpu *vcpu)
4032 struct vcpu_svm *svm = to_svm(vcpu);
4033 struct vmcb_control_area *control = &svm->vmcb->control;
4034 struct vmcb_save_area *save = &svm->vmcb->save;
4036 pr_err("VMCB Control Area:\n");
4037 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4038 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4039 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4040 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4041 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4042 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4043 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4044 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4045 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4046 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4047 pr_err("%-20s%d\n", "asid:", control->asid);
4048 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4049 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4050 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4051 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4052 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4053 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4054 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4055 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4056 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4057 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4058 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4059 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4060 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4061 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4062 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4063 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4064 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4065 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4066 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4067 pr_err("VMCB State Save Area:\n");
4068 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4070 save->es.selector, save->es.attrib,
4071 save->es.limit, save->es.base);
4072 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4074 save->cs.selector, save->cs.attrib,
4075 save->cs.limit, save->cs.base);
4076 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4078 save->ss.selector, save->ss.attrib,
4079 save->ss.limit, save->ss.base);
4080 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4082 save->ds.selector, save->ds.attrib,
4083 save->ds.limit, save->ds.base);
4084 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4086 save->fs.selector, save->fs.attrib,
4087 save->fs.limit, save->fs.base);
4088 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4090 save->gs.selector, save->gs.attrib,
4091 save->gs.limit, save->gs.base);
4092 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4094 save->gdtr.selector, save->gdtr.attrib,
4095 save->gdtr.limit, save->gdtr.base);
4096 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4098 save->ldtr.selector, save->ldtr.attrib,
4099 save->ldtr.limit, save->ldtr.base);
4100 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4102 save->idtr.selector, save->idtr.attrib,
4103 save->idtr.limit, save->idtr.base);
4104 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4106 save->tr.selector, save->tr.attrib,
4107 save->tr.limit, save->tr.base);
4108 pr_err("cpl: %d efer: %016llx\n",
4109 save->cpl, save->efer);
4110 pr_err("%-15s %016llx %-13s %016llx\n",
4111 "cr0:", save->cr0, "cr2:", save->cr2);
4112 pr_err("%-15s %016llx %-13s %016llx\n",
4113 "cr3:", save->cr3, "cr4:", save->cr4);
4114 pr_err("%-15s %016llx %-13s %016llx\n",
4115 "dr6:", save->dr6, "dr7:", save->dr7);
4116 pr_err("%-15s %016llx %-13s %016llx\n",
4117 "rip:", save->rip, "rflags:", save->rflags);
4118 pr_err("%-15s %016llx %-13s %016llx\n",
4119 "rsp:", save->rsp, "rax:", save->rax);
4120 pr_err("%-15s %016llx %-13s %016llx\n",
4121 "star:", save->star, "lstar:", save->lstar);
4122 pr_err("%-15s %016llx %-13s %016llx\n",
4123 "cstar:", save->cstar, "sfmask:", save->sfmask);
4124 pr_err("%-15s %016llx %-13s %016llx\n",
4125 "kernel_gs_base:", save->kernel_gs_base,
4126 "sysenter_cs:", save->sysenter_cs);
4127 pr_err("%-15s %016llx %-13s %016llx\n",
4128 "sysenter_esp:", save->sysenter_esp,
4129 "sysenter_eip:", save->sysenter_eip);
4130 pr_err("%-15s %016llx %-13s %016llx\n",
4131 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4132 pr_err("%-15s %016llx %-13s %016llx\n",
4133 "br_from:", save->br_from, "br_to:", save->br_to);
4134 pr_err("%-15s %016llx %-13s %016llx\n",
4135 "excp_from:", save->last_excp_from,
4136 "excp_to:", save->last_excp_to);
4139 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4141 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4143 *info1 = control->exit_info_1;
4144 *info2 = control->exit_info_2;
4147 static int handle_exit(struct kvm_vcpu *vcpu)
4149 struct vcpu_svm *svm = to_svm(vcpu);
4150 struct kvm_run *kvm_run = vcpu->run;
4151 u32 exit_code = svm->vmcb->control.exit_code;
4153 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4155 vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4157 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4158 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4160 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4162 if (unlikely(svm->nested.exit_required)) {
4163 nested_svm_vmexit(svm);
4164 svm->nested.exit_required = false;
4169 if (is_guest_mode(vcpu)) {
4172 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4173 svm->vmcb->control.exit_info_1,
4174 svm->vmcb->control.exit_info_2,
4175 svm->vmcb->control.exit_int_info,
4176 svm->vmcb->control.exit_int_info_err,
4179 vmexit = nested_svm_exit_special(svm);
4181 if (vmexit == NESTED_EXIT_CONTINUE)
4182 vmexit = nested_svm_exit_handled(svm);
4184 if (vmexit == NESTED_EXIT_DONE)
4188 svm_complete_interrupts(svm);
4190 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4191 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4192 kvm_run->fail_entry.hardware_entry_failure_reason
4193 = svm->vmcb->control.exit_code;
4194 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4199 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4200 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4201 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4202 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4203 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4205 __func__, svm->vmcb->control.exit_int_info,
4208 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4209 || !svm_exit_handlers[exit_code]) {
4210 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4211 kvm_queue_exception(vcpu, UD_VECTOR);
4215 return svm_exit_handlers[exit_code](svm);
4218 static void reload_tss(struct kvm_vcpu *vcpu)
4220 int cpu = raw_smp_processor_id();
4222 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4223 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4227 static void pre_svm_run(struct vcpu_svm *svm)
4229 int cpu = raw_smp_processor_id();
4231 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4233 /* FIXME: handle wraparound of asid_generation */
4234 if (svm->asid_generation != sd->asid_generation)
4238 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4240 struct vcpu_svm *svm = to_svm(vcpu);
4242 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4243 vcpu->arch.hflags |= HF_NMI_MASK;
4244 set_intercept(svm, INTERCEPT_IRET);
4245 ++vcpu->stat.nmi_injections;
4248 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4250 struct vmcb_control_area *control;
4252 /* The following fields are ignored when AVIC is enabled */
4253 control = &svm->vmcb->control;
4254 control->int_vector = irq;
4255 control->int_ctl &= ~V_INTR_PRIO_MASK;
4256 control->int_ctl |= V_IRQ_MASK |
4257 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4258 mark_dirty(svm->vmcb, VMCB_INTR);
4261 static void svm_set_irq(struct kvm_vcpu *vcpu)
4263 struct vcpu_svm *svm = to_svm(vcpu);
4265 BUG_ON(!(gif_set(svm)));
4267 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4268 ++vcpu->stat.irq_injections;
4270 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4271 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4274 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4276 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4279 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4281 struct vcpu_svm *svm = to_svm(vcpu);
4283 if (svm_nested_virtualize_tpr(vcpu) ||
4284 kvm_vcpu_apicv_active(vcpu))
4287 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4293 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4296 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4301 static bool svm_get_enable_apicv(void)
4306 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4310 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4314 /* Note: Currently only used by Hyper-V. */
4315 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4317 struct vcpu_svm *svm = to_svm(vcpu);
4318 struct vmcb *vmcb = svm->vmcb;
4323 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4324 mark_dirty(vmcb, VMCB_INTR);
4327 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4332 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4334 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4335 smp_mb__after_atomic();
4337 if (avic_vcpu_is_running(vcpu))
4338 wrmsrl(SVM_AVIC_DOORBELL,
4339 kvm_cpu_get_apicid(vcpu->cpu));
4341 kvm_vcpu_wake_up(vcpu);
4344 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4346 unsigned long flags;
4347 struct amd_svm_iommu_ir *cur;
4349 spin_lock_irqsave(&svm->ir_list_lock, flags);
4350 list_for_each_entry(cur, &svm->ir_list, node) {
4351 if (cur->data != pi->ir_data)
4353 list_del(&cur->node);
4357 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4360 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4363 unsigned long flags;
4364 struct amd_svm_iommu_ir *ir;
4367 * In some cases, the existing irte is updaed and re-set,
4368 * so we need to check here if it's already been * added
4371 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4372 struct kvm *kvm = svm->vcpu.kvm;
4373 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4374 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4375 struct vcpu_svm *prev_svm;
4382 prev_svm = to_svm(prev_vcpu);
4383 svm_ir_list_del(prev_svm, pi);
4387 * Allocating new amd_iommu_pi_data, which will get
4388 * add to the per-vcpu ir_list.
4390 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4395 ir->data = pi->ir_data;
4397 spin_lock_irqsave(&svm->ir_list_lock, flags);
4398 list_add(&ir->node, &svm->ir_list);
4399 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4406 * The HW cannot support posting multicast/broadcast
4407 * interrupts to a vCPU. So, we still use legacy interrupt
4408 * remapping for these kind of interrupts.
4410 * For lowest-priority interrupts, we only support
4411 * those with single CPU as the destination, e.g. user
4412 * configures the interrupts via /proc/irq or uses
4413 * irqbalance to make the interrupts single-CPU.
4416 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4417 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4419 struct kvm_lapic_irq irq;
4420 struct kvm_vcpu *vcpu = NULL;
4422 kvm_set_msi_irq(kvm, e, &irq);
4424 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4425 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4426 __func__, irq.vector);
4430 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4432 *svm = to_svm(vcpu);
4433 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4434 vcpu_info->vector = irq.vector;
4440 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4443 * @host_irq: host irq of the interrupt
4444 * @guest_irq: gsi of the interrupt
4445 * @set: set or unset PI
4446 * returns 0 on success, < 0 on failure
4448 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4449 uint32_t guest_irq, bool set)
4451 struct kvm_kernel_irq_routing_entry *e;
4452 struct kvm_irq_routing_table *irq_rt;
4453 int idx, ret = -EINVAL;
4455 if (!kvm_arch_has_assigned_device(kvm) ||
4456 !irq_remapping_cap(IRQ_POSTING_CAP))
4459 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4460 __func__, host_irq, guest_irq, set);
4462 idx = srcu_read_lock(&kvm->irq_srcu);
4463 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4464 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4466 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4467 struct vcpu_data vcpu_info;
4468 struct vcpu_svm *svm = NULL;
4470 if (e->type != KVM_IRQ_ROUTING_MSI)
4474 * Here, we setup with legacy mode in the following cases:
4475 * 1. When cannot target interrupt to a specific vcpu.
4476 * 2. Unsetting posted interrupt.
4477 * 3. APIC virtialization is disabled for the vcpu.
4479 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4480 kvm_vcpu_apicv_active(&svm->vcpu)) {
4481 struct amd_iommu_pi_data pi;
4483 /* Try to enable guest_mode in IRTE */
4484 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4485 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4487 pi.is_guest_mode = true;
4488 pi.vcpu_data = &vcpu_info;
4489 ret = irq_set_vcpu_affinity(host_irq, &pi);
4492 * Here, we successfully setting up vcpu affinity in
4493 * IOMMU guest mode. Now, we need to store the posted
4494 * interrupt information in a per-vcpu ir_list so that
4495 * we can reference to them directly when we update vcpu
4496 * scheduling information in IOMMU irte.
4498 if (!ret && pi.is_guest_mode)
4499 svm_ir_list_add(svm, &pi);
4501 /* Use legacy mode in IRTE */
4502 struct amd_iommu_pi_data pi;
4505 * Here, pi is used to:
4506 * - Tell IOMMU to use legacy mode for this interrupt.
4507 * - Retrieve ga_tag of prior interrupt remapping data.
4509 pi.is_guest_mode = false;
4510 ret = irq_set_vcpu_affinity(host_irq, &pi);
4513 * Check if the posted interrupt was previously
4514 * setup with the guest_mode by checking if the ga_tag
4515 * was cached. If so, we need to clean up the per-vcpu
4518 if (!ret && pi.prev_ga_tag) {
4519 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4520 struct kvm_vcpu *vcpu;
4522 vcpu = kvm_get_vcpu_by_id(kvm, id);
4524 svm_ir_list_del(to_svm(vcpu), &pi);
4529 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4532 vcpu_info.pi_desc_addr, set);
4536 pr_err("%s: failed to update PI IRTE\n", __func__);
4543 srcu_read_unlock(&kvm->irq_srcu, idx);
4547 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4549 struct vcpu_svm *svm = to_svm(vcpu);
4550 struct vmcb *vmcb = svm->vmcb;
4552 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4553 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4554 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4559 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4561 struct vcpu_svm *svm = to_svm(vcpu);
4563 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4566 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4568 struct vcpu_svm *svm = to_svm(vcpu);
4571 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4572 set_intercept(svm, INTERCEPT_IRET);
4574 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4575 clr_intercept(svm, INTERCEPT_IRET);
4579 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4581 struct vcpu_svm *svm = to_svm(vcpu);
4582 struct vmcb *vmcb = svm->vmcb;
4585 if (!gif_set(svm) ||
4586 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4589 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4591 if (is_guest_mode(vcpu))
4592 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4597 static void enable_irq_window(struct kvm_vcpu *vcpu)
4599 struct vcpu_svm *svm = to_svm(vcpu);
4601 if (kvm_vcpu_apicv_active(vcpu))
4605 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4606 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4607 * get that intercept, this function will be called again though and
4608 * we'll get the vintr intercept.
4610 if (gif_set(svm) && nested_svm_intr(svm)) {
4612 svm_inject_irq(svm, 0x0);
4616 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4618 struct vcpu_svm *svm = to_svm(vcpu);
4620 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4622 return; /* IRET will cause a vm exit */
4625 * Something prevents NMI from been injected. Single step over possible
4626 * problem (IRET or exception injection or interrupt shadow)
4628 svm->nmi_singlestep = true;
4629 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4632 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4637 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4639 struct vcpu_svm *svm = to_svm(vcpu);
4641 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4642 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4644 svm->asid_generation--;
4647 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4651 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4653 struct vcpu_svm *svm = to_svm(vcpu);
4655 if (svm_nested_virtualize_tpr(vcpu))
4658 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4659 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4660 kvm_set_cr8(vcpu, cr8);
4664 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4666 struct vcpu_svm *svm = to_svm(vcpu);
4669 if (svm_nested_virtualize_tpr(vcpu) ||
4670 kvm_vcpu_apicv_active(vcpu))
4673 cr8 = kvm_get_cr8(vcpu);
4674 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4675 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4678 static void svm_complete_interrupts(struct vcpu_svm *svm)
4682 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4683 unsigned int3_injected = svm->int3_injected;
4685 svm->int3_injected = 0;
4688 * If we've made progress since setting HF_IRET_MASK, we've
4689 * executed an IRET and can allow NMI injection.
4691 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4692 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4693 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4694 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4697 svm->vcpu.arch.nmi_injected = false;
4698 kvm_clear_exception_queue(&svm->vcpu);
4699 kvm_clear_interrupt_queue(&svm->vcpu);
4701 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4704 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4706 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4707 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4710 case SVM_EXITINTINFO_TYPE_NMI:
4711 svm->vcpu.arch.nmi_injected = true;
4713 case SVM_EXITINTINFO_TYPE_EXEPT:
4715 * In case of software exceptions, do not reinject the vector,
4716 * but re-execute the instruction instead. Rewind RIP first
4717 * if we emulated INT3 before.
4719 if (kvm_exception_is_soft(vector)) {
4720 if (vector == BP_VECTOR && int3_injected &&
4721 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4722 kvm_rip_write(&svm->vcpu,
4723 kvm_rip_read(&svm->vcpu) -
4727 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4728 u32 err = svm->vmcb->control.exit_int_info_err;
4729 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4732 kvm_requeue_exception(&svm->vcpu, vector);
4734 case SVM_EXITINTINFO_TYPE_INTR:
4735 kvm_queue_interrupt(&svm->vcpu, vector, false);
4742 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4744 struct vcpu_svm *svm = to_svm(vcpu);
4745 struct vmcb_control_area *control = &svm->vmcb->control;
4747 control->exit_int_info = control->event_inj;
4748 control->exit_int_info_err = control->event_inj_err;
4749 control->event_inj = 0;
4750 svm_complete_interrupts(svm);
4753 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4755 struct vcpu_svm *svm = to_svm(vcpu);
4757 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4758 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4759 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4762 * A vmexit emulation is required before the vcpu can be executed
4765 if (unlikely(svm->nested.exit_required))
4770 sync_lapic_to_cr8(vcpu);
4772 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4779 "push %%" _ASM_BP "; \n\t"
4780 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4781 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4782 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4783 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4784 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4785 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4786 #ifdef CONFIG_X86_64
4787 "mov %c[r8](%[svm]), %%r8 \n\t"
4788 "mov %c[r9](%[svm]), %%r9 \n\t"
4789 "mov %c[r10](%[svm]), %%r10 \n\t"
4790 "mov %c[r11](%[svm]), %%r11 \n\t"
4791 "mov %c[r12](%[svm]), %%r12 \n\t"
4792 "mov %c[r13](%[svm]), %%r13 \n\t"
4793 "mov %c[r14](%[svm]), %%r14 \n\t"
4794 "mov %c[r15](%[svm]), %%r15 \n\t"
4797 /* Enter guest mode */
4798 "push %%" _ASM_AX " \n\t"
4799 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4800 __ex(SVM_VMLOAD) "\n\t"
4801 __ex(SVM_VMRUN) "\n\t"
4802 __ex(SVM_VMSAVE) "\n\t"
4803 "pop %%" _ASM_AX " \n\t"
4805 /* Save guest registers, load host registers */
4806 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4807 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4808 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4809 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4810 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4811 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4812 #ifdef CONFIG_X86_64
4813 "mov %%r8, %c[r8](%[svm]) \n\t"
4814 "mov %%r9, %c[r9](%[svm]) \n\t"
4815 "mov %%r10, %c[r10](%[svm]) \n\t"
4816 "mov %%r11, %c[r11](%[svm]) \n\t"
4817 "mov %%r12, %c[r12](%[svm]) \n\t"
4818 "mov %%r13, %c[r13](%[svm]) \n\t"
4819 "mov %%r14, %c[r14](%[svm]) \n\t"
4820 "mov %%r15, %c[r15](%[svm]) \n\t"
4825 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4826 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4827 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4828 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4829 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4830 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4831 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4832 #ifdef CONFIG_X86_64
4833 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4834 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4835 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4836 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4837 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4838 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4839 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4840 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4843 #ifdef CONFIG_X86_64
4844 , "rbx", "rcx", "rdx", "rsi", "rdi"
4845 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4847 , "ebx", "ecx", "edx", "esi", "edi"
4851 #ifdef CONFIG_X86_64
4852 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4854 loadsegment(fs, svm->host.fs);
4855 #ifndef CONFIG_X86_32_LAZY_GS
4856 loadsegment(gs, svm->host.gs);
4862 local_irq_disable();
4864 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4865 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4866 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4867 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4869 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4870 kvm_before_handle_nmi(&svm->vcpu);
4874 /* Any pending NMI will happen here */
4876 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4877 kvm_after_handle_nmi(&svm->vcpu);
4879 sync_cr8_to_lapic(vcpu);
4883 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4885 /* if exit due to PF check for async PF */
4886 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4887 svm->apf_reason = kvm_read_and_reset_pf_reason();
4890 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4891 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4895 * We need to handle MC intercepts here before the vcpu has a chance to
4896 * change the physical cpu
4898 if (unlikely(svm->vmcb->control.exit_code ==
4899 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4900 svm_handle_mce(svm);
4902 mark_all_clean(svm->vmcb);
4905 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4907 struct vcpu_svm *svm = to_svm(vcpu);
4909 svm->vmcb->save.cr3 = root;
4910 mark_dirty(svm->vmcb, VMCB_CR);
4911 svm_flush_tlb(vcpu);
4914 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4916 struct vcpu_svm *svm = to_svm(vcpu);
4918 svm->vmcb->control.nested_cr3 = root;
4919 mark_dirty(svm->vmcb, VMCB_NPT);
4921 /* Also sync guest cr3 here in case we live migrate */
4922 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4923 mark_dirty(svm->vmcb, VMCB_CR);
4925 svm_flush_tlb(vcpu);
4928 static int is_disabled(void)
4932 rdmsrl(MSR_VM_CR, vm_cr);
4933 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4940 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4943 * Patch in the VMMCALL instruction:
4945 hypercall[0] = 0x0f;
4946 hypercall[1] = 0x01;
4947 hypercall[2] = 0xd9;
4950 static void svm_check_processor_compat(void *rtn)
4955 static bool svm_cpu_has_accelerated_tpr(void)
4960 static bool svm_has_high_real_mode_segbase(void)
4965 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4970 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4972 struct vcpu_svm *svm = to_svm(vcpu);
4973 struct kvm_cpuid_entry2 *entry;
4975 /* Update nrips enabled cache */
4976 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4978 if (!kvm_vcpu_apicv_active(vcpu))
4981 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
4983 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4986 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4991 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4995 entry->ecx |= (1 << 2); /* Set SVM bit */
4998 entry->eax = 1; /* SVM revision 1 */
4999 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5000 ASID emulation to nested SVM */
5001 entry->ecx = 0; /* Reserved */
5002 entry->edx = 0; /* Per default do not support any
5003 additional features */
5005 /* Support next_rip if host supports it */
5006 if (boot_cpu_has(X86_FEATURE_NRIPS))
5007 entry->edx |= SVM_FEATURE_NRIP;
5009 /* Support NPT for the guest if enabled */
5011 entry->edx |= SVM_FEATURE_NPT;
5017 static int svm_get_lpage_level(void)
5019 return PT_PDPE_LEVEL;
5022 static bool svm_rdtscp_supported(void)
5024 return boot_cpu_has(X86_FEATURE_RDTSCP);
5027 static bool svm_invpcid_supported(void)
5032 static bool svm_mpx_supported(void)
5037 static bool svm_xsaves_supported(void)
5042 static bool svm_has_wbinvd_exit(void)
5047 #define PRE_EX(exit) { .exit_code = (exit), \
5048 .stage = X86_ICPT_PRE_EXCEPT, }
5049 #define POST_EX(exit) { .exit_code = (exit), \
5050 .stage = X86_ICPT_POST_EXCEPT, }
5051 #define POST_MEM(exit) { .exit_code = (exit), \
5052 .stage = X86_ICPT_POST_MEMACCESS, }
5054 static const struct __x86_intercept {
5056 enum x86_intercept_stage stage;
5057 } x86_intercept_map[] = {
5058 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5059 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5060 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5061 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5062 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5063 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5064 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5065 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5066 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5067 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5068 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5069 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5070 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5071 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5072 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5073 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5074 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5075 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5076 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5077 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5078 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5079 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5080 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5081 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5082 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5083 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5084 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5085 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5086 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5087 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5088 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5089 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5090 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5091 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5092 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5093 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5094 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5095 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5096 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5097 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5098 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5099 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5100 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5101 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5102 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5103 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5110 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5111 struct x86_instruction_info *info,
5112 enum x86_intercept_stage stage)
5114 struct vcpu_svm *svm = to_svm(vcpu);
5115 int vmexit, ret = X86EMUL_CONTINUE;
5116 struct __x86_intercept icpt_info;
5117 struct vmcb *vmcb = svm->vmcb;
5119 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5122 icpt_info = x86_intercept_map[info->intercept];
5124 if (stage != icpt_info.stage)
5127 switch (icpt_info.exit_code) {
5128 case SVM_EXIT_READ_CR0:
5129 if (info->intercept == x86_intercept_cr_read)
5130 icpt_info.exit_code += info->modrm_reg;
5132 case SVM_EXIT_WRITE_CR0: {
5133 unsigned long cr0, val;
5136 if (info->intercept == x86_intercept_cr_write)
5137 icpt_info.exit_code += info->modrm_reg;
5139 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5140 info->intercept == x86_intercept_clts)
5143 intercept = svm->nested.intercept;
5145 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5148 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5149 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5151 if (info->intercept == x86_intercept_lmsw) {
5154 /* lmsw can't clear PE - catch this here */
5155 if (cr0 & X86_CR0_PE)
5160 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5164 case SVM_EXIT_READ_DR0:
5165 case SVM_EXIT_WRITE_DR0:
5166 icpt_info.exit_code += info->modrm_reg;
5169 if (info->intercept == x86_intercept_wrmsr)
5170 vmcb->control.exit_info_1 = 1;
5172 vmcb->control.exit_info_1 = 0;
5174 case SVM_EXIT_PAUSE:
5176 * We get this for NOP only, but pause
5177 * is rep not, check this here
5179 if (info->rep_prefix != REPE_PREFIX)
5181 case SVM_EXIT_IOIO: {
5185 if (info->intercept == x86_intercept_in ||
5186 info->intercept == x86_intercept_ins) {
5187 exit_info = ((info->src_val & 0xffff) << 16) |
5189 bytes = info->dst_bytes;
5191 exit_info = (info->dst_val & 0xffff) << 16;
5192 bytes = info->src_bytes;
5195 if (info->intercept == x86_intercept_outs ||
5196 info->intercept == x86_intercept_ins)
5197 exit_info |= SVM_IOIO_STR_MASK;
5199 if (info->rep_prefix)
5200 exit_info |= SVM_IOIO_REP_MASK;
5202 bytes = min(bytes, 4u);
5204 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5206 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5208 vmcb->control.exit_info_1 = exit_info;
5209 vmcb->control.exit_info_2 = info->next_rip;
5217 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5218 if (static_cpu_has(X86_FEATURE_NRIPS))
5219 vmcb->control.next_rip = info->next_rip;
5220 vmcb->control.exit_code = icpt_info.exit_code;
5221 vmexit = nested_svm_exit_handled(svm);
5223 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5230 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5234 * We must have an instruction with interrupts enabled, so
5235 * the timer interrupt isn't delayed by the interrupt shadow.
5238 local_irq_disable();
5241 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5245 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5247 if (avic_handle_apic_id_update(vcpu) != 0)
5249 if (avic_handle_dfr_update(vcpu) != 0)
5251 avic_handle_ldr_update(vcpu);
5254 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5255 .cpu_has_kvm_support = has_svm,
5256 .disabled_by_bios = is_disabled,
5257 .hardware_setup = svm_hardware_setup,
5258 .hardware_unsetup = svm_hardware_unsetup,
5259 .check_processor_compatibility = svm_check_processor_compat,
5260 .hardware_enable = svm_hardware_enable,
5261 .hardware_disable = svm_hardware_disable,
5262 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5263 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5265 .vcpu_create = svm_create_vcpu,
5266 .vcpu_free = svm_free_vcpu,
5267 .vcpu_reset = svm_vcpu_reset,
5269 .vm_init = avic_vm_init,
5270 .vm_destroy = avic_vm_destroy,
5272 .prepare_guest_switch = svm_prepare_guest_switch,
5273 .vcpu_load = svm_vcpu_load,
5274 .vcpu_put = svm_vcpu_put,
5275 .vcpu_blocking = svm_vcpu_blocking,
5276 .vcpu_unblocking = svm_vcpu_unblocking,
5278 .update_bp_intercept = update_bp_intercept,
5279 .get_msr = svm_get_msr,
5280 .set_msr = svm_set_msr,
5281 .get_segment_base = svm_get_segment_base,
5282 .get_segment = svm_get_segment,
5283 .set_segment = svm_set_segment,
5284 .get_cpl = svm_get_cpl,
5285 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5286 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5287 .decache_cr3 = svm_decache_cr3,
5288 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5289 .set_cr0 = svm_set_cr0,
5290 .set_cr3 = svm_set_cr3,
5291 .set_cr4 = svm_set_cr4,
5292 .set_efer = svm_set_efer,
5293 .get_idt = svm_get_idt,
5294 .set_idt = svm_set_idt,
5295 .get_gdt = svm_get_gdt,
5296 .set_gdt = svm_set_gdt,
5297 .get_dr6 = svm_get_dr6,
5298 .set_dr6 = svm_set_dr6,
5299 .set_dr7 = svm_set_dr7,
5300 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5301 .cache_reg = svm_cache_reg,
5302 .get_rflags = svm_get_rflags,
5303 .set_rflags = svm_set_rflags,
5305 .get_pkru = svm_get_pkru,
5307 .tlb_flush = svm_flush_tlb,
5309 .run = svm_vcpu_run,
5310 .handle_exit = handle_exit,
5311 .skip_emulated_instruction = skip_emulated_instruction,
5312 .set_interrupt_shadow = svm_set_interrupt_shadow,
5313 .get_interrupt_shadow = svm_get_interrupt_shadow,
5314 .patch_hypercall = svm_patch_hypercall,
5315 .set_irq = svm_set_irq,
5316 .set_nmi = svm_inject_nmi,
5317 .queue_exception = svm_queue_exception,
5318 .cancel_injection = svm_cancel_injection,
5319 .interrupt_allowed = svm_interrupt_allowed,
5320 .nmi_allowed = svm_nmi_allowed,
5321 .get_nmi_mask = svm_get_nmi_mask,
5322 .set_nmi_mask = svm_set_nmi_mask,
5323 .enable_nmi_window = enable_nmi_window,
5324 .enable_irq_window = enable_irq_window,
5325 .update_cr8_intercept = update_cr8_intercept,
5326 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5327 .get_enable_apicv = svm_get_enable_apicv,
5328 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5329 .load_eoi_exitmap = svm_load_eoi_exitmap,
5330 .hwapic_irr_update = svm_hwapic_irr_update,
5331 .hwapic_isr_update = svm_hwapic_isr_update,
5332 .apicv_post_state_restore = avic_post_state_restore,
5334 .set_tss_addr = svm_set_tss_addr,
5335 .get_tdp_level = get_npt_level,
5336 .get_mt_mask = svm_get_mt_mask,
5338 .get_exit_info = svm_get_exit_info,
5340 .get_lpage_level = svm_get_lpage_level,
5342 .cpuid_update = svm_cpuid_update,
5344 .rdtscp_supported = svm_rdtscp_supported,
5345 .invpcid_supported = svm_invpcid_supported,
5346 .mpx_supported = svm_mpx_supported,
5347 .xsaves_supported = svm_xsaves_supported,
5349 .set_supported_cpuid = svm_set_supported_cpuid,
5351 .has_wbinvd_exit = svm_has_wbinvd_exit,
5353 .write_tsc_offset = svm_write_tsc_offset,
5355 .set_tdp_cr3 = set_tdp_cr3,
5357 .check_intercept = svm_check_intercept,
5358 .handle_external_intr = svm_handle_external_intr,
5360 .sched_in = svm_sched_in,
5362 .pmu_ops = &amd_pmu_ops,
5363 .deliver_posted_interrupt = svm_deliver_avic_intr,
5364 .update_pi_irte = svm_update_pi_irte,
5367 static int __init svm_init(void)
5369 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5370 __alignof__(struct vcpu_svm), THIS_MODULE);
5373 static void __exit svm_exit(void)
5378 module_init(svm_init)
5379 module_exit(svm_exit)