arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39
  40 #include <asm/apic.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/desc.h>
  44 #include <asm/debugreg.h>
  45 #include <asm/kvm_para.h>
  46 #include <asm/irq_remapping.h>
  47
  48 #include <asm/virtext.h>
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id svm_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  61
  62 #define IOPM_ALLOC_ORDER 2
  63 #define MSRPM_ALLOC_ORDER 1
  64
  65 #define SEG_TYPE_LDT 2
  66 #define SEG_TYPE_BUSY_TSS16 3
  67
  68 #define SVM_FEATURE_NPT            (1 <<  0)
  69 #define SVM_FEATURE_LBRV           (1 <<  1)
  70 #define SVM_FEATURE_SVML           (1 <<  2)
  71 #define SVM_FEATURE_NRIP           (1 <<  3)
  72 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  73 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  74 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  75 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  76 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  77
  78 #define SVM_AVIC_DOORBELL       0xc001011b
  79
  80 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  81 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  82 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  83
  84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  85
  86 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  87 #define TSC_RATIO_MIN           0x0000000000000001ULL
  88 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  89
  90 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  91
  92 /*
  93  * 0xff is broadcast, so the max index allowed for physical APIC ID
  94  * table is 0xfe.  APIC IDs above 0xff are reserved.
  95  */
  96 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  97
  98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
  99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 101
 102 /* AVIC GATAG is encoded using VM and VCPU IDs */
 103 #define AVIC_VCPU_ID_BITS               8
 104 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 105
 106 #define AVIC_VM_ID_BITS                 24
 107 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 108 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 109
 110 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 111                                                 (y & AVIC_VCPU_ID_MASK))
 112 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 113 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 114
 115 static bool erratum_383_found __read_mostly;
 116
 117 static const u32 host_save_user_msrs[] = {
 118 #ifdef CONFIG_X86_64
 119         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 120         MSR_FS_BASE,
 121 #endif
 122         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 123         MSR_TSC_AUX,
 124 };
 125
 126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 127
 128 struct kvm_vcpu;
 129
 130 struct nested_state {
 131         struct vmcb *hsave;
 132         u64 hsave_msr;
 133         u64 vm_cr_msr;
 134         u64 vmcb;
 135
 136         /* These are the merged vectors */
 137         u32 *msrpm;
 138
 139         /* gpa pointers to the real vectors */
 140         u64 vmcb_msrpm;
 141         u64 vmcb_iopm;
 142
 143         /* A VMEXIT is required but not yet emulated */
 144         bool exit_required;
 145
 146         /* cache for intercepts of the guest */
 147         u32 intercept_cr;
 148         u32 intercept_dr;
 149         u32 intercept_exceptions;
 150         u64 intercept;
 151
 152         /* Nested Paging related state */
 153         u64 nested_cr3;
 154 };
 155
 156 #define MSRPM_OFFSETS   16
 157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 158
 159 /*
 160  * Set osvw_len to higher value when updated Revision Guides
 161  * are published and we know what the new status bits are
 162  */
 163 static uint64_t osvw_len = 4, osvw_status;
 164
 165 struct vcpu_svm {
 166         struct kvm_vcpu vcpu;
 167         struct vmcb *vmcb;
 168         unsigned long vmcb_pa;
 169         struct svm_cpu_data *svm_data;
 170         uint64_t asid_generation;
 171         uint64_t sysenter_esp;
 172         uint64_t sysenter_eip;
 173         uint64_t tsc_aux;
 174
 175         u64 next_rip;
 176
 177         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 178         struct {
 179                 u16 fs;
 180                 u16 gs;
 181                 u16 ldt;
 182                 u64 gs_base;
 183         } host;
 184
 185         u32 *msrpm;
 186
 187         ulong nmi_iret_rip;
 188
 189         struct nested_state nested;
 190
 191         bool nmi_singlestep;
 192
 193         unsigned int3_injected;
 194         unsigned long int3_rip;
 195         u32 apf_reason;
 196
 197         /* cached guest cpuid flags for faster access */
 198         bool nrips_enabled      : 1;
 199
 200         u32 ldr_reg;
 201         struct page *avic_backing_page;
 202         u64 *avic_physical_id_cache;
 203         bool avic_is_running;
 204
 205         /*
 206          * Per-vcpu list of struct amd_svm_iommu_ir:
 207          * This is used mainly to store interrupt remapping information used
 208          * when update the vcpu affinity. This avoids the need to scan for
 209          * IRTE and try to match ga_tag in the IOMMU driver.
 210          */
 211         struct list_head ir_list;
 212         spinlock_t ir_list_lock;
 213 };
 214
 215 /*
 216  * This is a wrapper of struct amd_iommu_ir_data.
 217  */
 218 struct amd_svm_iommu_ir {
 219         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 220         void *data;             /* Storing pointer to struct amd_ir_data */
 221 };
 222
 223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 225
 226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 230
 231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 232 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 233
 234 #define MSR_INVALID                     0xffffffffU
 235
 236 static const struct svm_direct_access_msrs {
 237         u32 index;   /* Index of the MSR */
 238         bool always; /* True if intercept is always on */
 239 } direct_access_msrs[] = {
 240         { .index = MSR_STAR,                            .always = true  },
 241         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 242 #ifdef CONFIG_X86_64
 243         { .index = MSR_GS_BASE,                         .always = true  },
 244         { .index = MSR_FS_BASE,                         .always = true  },
 245         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 246         { .index = MSR_LSTAR,                           .always = true  },
 247         { .index = MSR_CSTAR,                           .always = true  },
 248         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 249 #endif
 250         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 251         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 252         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 253         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 254         { .index = MSR_INVALID,                         .always = false },
 255 };
 256
 257 /* enable NPT for AMD64 and X86 with PAE */
 258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 259 static bool npt_enabled = true;
 260 #else
 261 static bool npt_enabled;
 262 #endif
 263
 264 /* allow nested paging (virtualized MMU) for all guests */
 265 static int npt = true;
 266 module_param(npt, int, S_IRUGO);
 267
 268 /* allow nested virtualization in KVM/SVM */
 269 static int nested = true;
 270 module_param(nested, int, S_IRUGO);
 271
 272 /* enable / disable AVIC */
 273 static int avic;
 274 #ifdef CONFIG_X86_LOCAL_APIC
 275 module_param(avic, int, S_IRUGO);
 276 #endif
 277
 278 /* AVIC VM ID bit masks and lock */
 279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
 280 static DEFINE_SPINLOCK(avic_vm_id_lock);
 281
 282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 284 static void svm_complete_interrupts(struct vcpu_svm *svm);
 285
 286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 287 static int nested_svm_intercept(struct vcpu_svm *svm);
 288 static int nested_svm_vmexit(struct vcpu_svm *svm);
 289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 290                                       bool has_error_code, u32 error_code);
 291
 292 enum {
 293         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 294                             pause filter count */
 295         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 296         VMCB_ASID,       /* ASID */
 297         VMCB_INTR,       /* int_ctl, int_vector */
 298         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 299         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 300         VMCB_DR,         /* DR6, DR7 */
 301         VMCB_DT,         /* GDT, IDT */
 302         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 303         VMCB_CR2,        /* CR2 only */
 304         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 305         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 306                           * AVIC PHYSICAL_TABLE pointer,
 307                           * AVIC LOGICAL_TABLE pointer
 308                           */
 309         VMCB_DIRTY_MAX,
 310 };
 311
 312 /* TPR and CR2 are always written before VMRUN */
 313 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 314
 315 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 316
 317 static inline void mark_all_dirty(struct vmcb *vmcb)
 318 {
 319         vmcb->control.clean = 0;
 320 }
 321
 322 static inline void mark_all_clean(struct vmcb *vmcb)
 323 {
 324         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 325                                & ~VMCB_ALWAYS_DIRTY_MASK;
 326 }
 327
 328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 329 {
 330         vmcb->control.clean &= ~(1 << bit);
 331 }
 332
 333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 334 {
 335         return container_of(vcpu, struct vcpu_svm, vcpu);
 336 }
 337
 338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 339 {
 340         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 341         mark_dirty(svm->vmcb, VMCB_AVIC);
 342 }
 343
 344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 345 {
 346         struct vcpu_svm *svm = to_svm(vcpu);
 347         u64 *entry = svm->avic_physical_id_cache;
 348
 349         if (!entry)
 350                 return false;
 351
 352         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 353 }
 354
 355 static void recalc_intercepts(struct vcpu_svm *svm)
 356 {
 357         struct vmcb_control_area *c, *h;
 358         struct nested_state *g;
 359
 360         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 361
 362         if (!is_guest_mode(&svm->vcpu))
 363                 return;
 364
 365         c = &svm->vmcb->control;
 366         h = &svm->nested.hsave->control;
 367         g = &svm->nested;
 368
 369         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 370         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 371         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 372         c->intercept = h->intercept | g->intercept;
 373 }
 374
 375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 376 {
 377         if (is_guest_mode(&svm->vcpu))
 378                 return svm->nested.hsave;
 379         else
 380                 return svm->vmcb;
 381 }
 382
 383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 384 {
 385         struct vmcb *vmcb = get_host_vmcb(svm);
 386
 387         vmcb->control.intercept_cr |= (1U << bit);
 388
 389         recalc_intercepts(svm);
 390 }
 391
 392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 393 {
 394         struct vmcb *vmcb = get_host_vmcb(svm);
 395
 396         vmcb->control.intercept_cr &= ~(1U << bit);
 397
 398         recalc_intercepts(svm);
 399 }
 400
 401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 402 {
 403         struct vmcb *vmcb = get_host_vmcb(svm);
 404
 405         return vmcb->control.intercept_cr & (1U << bit);
 406 }
 407
 408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 409 {
 410         struct vmcb *vmcb = get_host_vmcb(svm);
 411
 412         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 413                 | (1 << INTERCEPT_DR1_READ)
 414                 | (1 << INTERCEPT_DR2_READ)
 415                 | (1 << INTERCEPT_DR3_READ)
 416                 | (1 << INTERCEPT_DR4_READ)
 417                 | (1 << INTERCEPT_DR5_READ)
 418                 | (1 << INTERCEPT_DR6_READ)
 419                 | (1 << INTERCEPT_DR7_READ)
 420                 | (1 << INTERCEPT_DR0_WRITE)
 421                 | (1 << INTERCEPT_DR1_WRITE)
 422                 | (1 << INTERCEPT_DR2_WRITE)
 423                 | (1 << INTERCEPT_DR3_WRITE)
 424                 | (1 << INTERCEPT_DR4_WRITE)
 425                 | (1 << INTERCEPT_DR5_WRITE)
 426                 | (1 << INTERCEPT_DR6_WRITE)
 427                 | (1 << INTERCEPT_DR7_WRITE);
 428
 429         recalc_intercepts(svm);
 430 }
 431
 432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 433 {
 434         struct vmcb *vmcb = get_host_vmcb(svm);
 435
 436         vmcb->control.intercept_dr = 0;
 437
 438         recalc_intercepts(svm);
 439 }
 440
 441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 442 {
 443         struct vmcb *vmcb = get_host_vmcb(svm);
 444
 445         vmcb->control.intercept_exceptions |= (1U << bit);
 446
 447         recalc_intercepts(svm);
 448 }
 449
 450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 451 {
 452         struct vmcb *vmcb = get_host_vmcb(svm);
 453
 454         vmcb->control.intercept_exceptions &= ~(1U << bit);
 455
 456         recalc_intercepts(svm);
 457 }
 458
 459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 460 {
 461         struct vmcb *vmcb = get_host_vmcb(svm);
 462
 463         vmcb->control.intercept |= (1ULL << bit);
 464
 465         recalc_intercepts(svm);
 466 }
 467
 468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 469 {
 470         struct vmcb *vmcb = get_host_vmcb(svm);
 471
 472         vmcb->control.intercept &= ~(1ULL << bit);
 473
 474         recalc_intercepts(svm);
 475 }
 476
 477 static inline void enable_gif(struct vcpu_svm *svm)
 478 {
 479         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 480 }
 481
 482 static inline void disable_gif(struct vcpu_svm *svm)
 483 {
 484         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 485 }
 486
 487 static inline bool gif_set(struct vcpu_svm *svm)
 488 {
 489         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 490 }
 491
 492 static unsigned long iopm_base;
 493
 494 struct kvm_ldttss_desc {
 495         u16 limit0;
 496         u16 base0;
 497         unsigned base1:8, type:5, dpl:2, p:1;
 498         unsigned limit1:4, zero0:3, g:1, base2:8;
 499         u32 base3;
 500         u32 zero1;
 501 } __attribute__((packed));
 502
 503 struct svm_cpu_data {
 504         int cpu;
 505
 506         u64 asid_generation;
 507         u32 max_asid;
 508         u32 next_asid;
 509         struct kvm_ldttss_desc *tss_desc;
 510
 511         struct page *save_area;
 512 };
 513
 514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 515
 516 struct svm_init_data {
 517         int cpu;
 518         int r;
 519 };
 520
 521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 522
 523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 524 #define MSRS_RANGE_SIZE 2048
 525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 526
 527 static u32 svm_msrpm_offset(u32 msr)
 528 {
 529         u32 offset;
 530         int i;
 531
 532         for (i = 0; i < NUM_MSR_MAPS; i++) {
 533                 if (msr < msrpm_ranges[i] ||
 534                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 535                         continue;
 536
 537                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 538                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 539
 540                 /* Now we have the u8 offset - but need the u32 offset */
 541                 return offset / 4;
 542         }
 543
 544         /* MSR not in any range */
 545         return MSR_INVALID;
 546 }
 547
 548 #define MAX_INST_SIZE 15
 549
 550 static inline void clgi(void)
 551 {
 552         asm volatile (__ex(SVM_CLGI));
 553 }
 554
 555 static inline void stgi(void)
 556 {
 557         asm volatile (__ex(SVM_STGI));
 558 }
 559
 560 static inline void invlpga(unsigned long addr, u32 asid)
 561 {
 562         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 563 }
 564
 565 static int get_npt_level(void)
 566 {
 567 #ifdef CONFIG_X86_64
 568         return PT64_ROOT_LEVEL;
 569 #else
 570         return PT32E_ROOT_LEVEL;
 571 #endif
 572 }
 573
 574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 575 {
 576         vcpu->arch.efer = efer;
 577         if (!npt_enabled && !(efer & EFER_LMA))
 578                 efer &= ~EFER_LME;
 579
 580         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 581         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 582 }
 583
 584 static int is_external_interrupt(u32 info)
 585 {
 586         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 587         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 588 }
 589
 590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 591 {
 592         struct vcpu_svm *svm = to_svm(vcpu);
 593         u32 ret = 0;
 594
 595         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 596                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 597         return ret;
 598 }
 599
 600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         if (mask == 0)
 605                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 606         else
 607                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 608
 609 }
 610
 611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         if (svm->vmcb->control.next_rip != 0) {
 616                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 617                 svm->next_rip = svm->vmcb->control.next_rip;
 618         }
 619
 620         if (!svm->next_rip) {
 621                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 622                                 EMULATE_DONE)
 623                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 624                 return;
 625         }
 626         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 627                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 628                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 629
 630         kvm_rip_write(vcpu, svm->next_rip);
 631         svm_set_interrupt_shadow(vcpu, 0);
 632 }
 633
 634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 635                                 bool has_error_code, u32 error_code,
 636                                 bool reinject)
 637 {
 638         struct vcpu_svm *svm = to_svm(vcpu);
 639
 640         /*
 641          * If we are within a nested VM we'd better #VMEXIT and let the guest
 642          * handle the exception
 643          */
 644         if (!reinject &&
 645             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 646                 return;
 647
 648         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 649                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 650
 651                 /*
 652                  * For guest debugging where we have to reinject #BP if some
 653                  * INT3 is guest-owned:
 654                  * Emulate nRIP by moving RIP forward. Will fail if injection
 655                  * raises a fault that is not intercepted. Still better than
 656                  * failing in all cases.
 657                  */
 658                 skip_emulated_instruction(&svm->vcpu);
 659                 rip = kvm_rip_read(&svm->vcpu);
 660                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 661                 svm->int3_injected = rip - old_rip;
 662         }
 663
 664         svm->vmcb->control.event_inj = nr
 665                 | SVM_EVTINJ_VALID
 666                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 667                 | SVM_EVTINJ_TYPE_EXEPT;
 668         svm->vmcb->control.event_inj_err = error_code;
 669 }
 670
 671 static void svm_init_erratum_383(void)
 672 {
 673         u32 low, high;
 674         int err;
 675         u64 val;
 676
 677         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 678                 return;
 679
 680         /* Use _safe variants to not break nested virtualization */
 681         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 682         if (err)
 683                 return;
 684
 685         val |= (1ULL << 47);
 686
 687         low  = lower_32_bits(val);
 688         high = upper_32_bits(val);
 689
 690         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 691
 692         erratum_383_found = true;
 693 }
 694
 695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 696 {
 697         /*
 698          * Guests should see errata 400 and 415 as fixed (assuming that
 699          * HLT and IO instructions are intercepted).
 700          */
 701         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 702         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 703
 704         /*
 705          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 706          * all osvw.status bits inside that length, including bit 0 (which is
 707          * reserved for erratum 298), are valid. However, if host processor's
 708          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 709          * be conservative here and therefore we tell the guest that erratum 298
 710          * is present (because we really don't know).
 711          */
 712         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 713                 vcpu->arch.osvw.status |= 1;
 714 }
 715
 716 static int has_svm(void)
 717 {
 718         const char *msg;
 719
 720         if (!cpu_has_svm(&msg)) {
 721                 printk(KERN_INFO "has_svm: %s\n", msg);
 722                 return 0;
 723         }
 724
 725         return 1;
 726 }
 727
 728 static void svm_hardware_disable(void)
 729 {
 730         /* Make sure we clean up behind us */
 731         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 732                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 733
 734         cpu_svm_disable();
 735
 736         amd_pmu_disable_virt();
 737 }
 738
 739 static int svm_hardware_enable(void)
 740 {
 741
 742         struct svm_cpu_data *sd;
 743         uint64_t efer;
 744         struct desc_ptr gdt_descr;
 745         struct desc_struct *gdt;
 746         int me = raw_smp_processor_id();
 747
 748         rdmsrl(MSR_EFER, efer);
 749         if (efer & EFER_SVME)
 750                 return -EBUSY;
 751
 752         if (!has_svm()) {
 753                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 754                 return -EINVAL;
 755         }
 756         sd = per_cpu(svm_data, me);
 757         if (!sd) {
 758                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 759                 return -EINVAL;
 760         }
 761
 762         sd->asid_generation = 1;
 763         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 764         sd->next_asid = sd->max_asid + 1;
 765
 766         native_store_gdt(&gdt_descr);
 767         gdt = (struct desc_struct *)gdt_descr.address;
 768         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 769
 770         wrmsrl(MSR_EFER, efer | EFER_SVME);
 771
 772         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 773
 774         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 775                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 776                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 777         }
 778
 779
 780         /*
 781          * Get OSVW bits.
 782          *
 783          * Note that it is possible to have a system with mixed processor
 784          * revisions and therefore different OSVW bits. If bits are not the same
 785          * on different processors then choose the worst case (i.e. if erratum
 786          * is present on one processor and not on another then assume that the
 787          * erratum is present everywhere).
 788          */
 789         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 790                 uint64_t len, status = 0;
 791                 int err;
 792
 793                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 794                 if (!err)
 795                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 796                                                       &err);
 797
 798                 if (err)
 799                         osvw_status = osvw_len = 0;
 800                 else {
 801                         if (len < osvw_len)
 802                                 osvw_len = len;
 803                         osvw_status |= status;
 804                         osvw_status &= (1ULL << osvw_len) - 1;
 805                 }
 806         } else
 807                 osvw_status = osvw_len = 0;
 808
 809         svm_init_erratum_383();
 810
 811         amd_pmu_enable_virt();
 812
 813         return 0;
 814 }
 815
 816 static void svm_cpu_uninit(int cpu)
 817 {
 818         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 819
 820         if (!sd)
 821                 return;
 822
 823         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 824         __free_page(sd->save_area);
 825         kfree(sd);
 826 }
 827
 828 static int svm_cpu_init(int cpu)
 829 {
 830         struct svm_cpu_data *sd;
 831         int r;
 832
 833         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 834         if (!sd)
 835                 return -ENOMEM;
 836         sd->cpu = cpu;
 837         sd->save_area = alloc_page(GFP_KERNEL);
 838         r = -ENOMEM;
 839         if (!sd->save_area)
 840                 goto err_1;
 841
 842         per_cpu(svm_data, cpu) = sd;
 843
 844         return 0;
 845
 846 err_1:
 847         kfree(sd);
 848         return r;
 849
 850 }
 851
 852 static bool valid_msr_intercept(u32 index)
 853 {
 854         int i;
 855
 856         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 857                 if (direct_access_msrs[i].index == index)
 858                         return true;
 859
 860         return false;
 861 }
 862
 863 static void set_msr_interception(u32 *msrpm, unsigned msr,
 864                                  int read, int write)
 865 {
 866         u8 bit_read, bit_write;
 867         unsigned long tmp;
 868         u32 offset;
 869
 870         /*
 871          * If this warning triggers extend the direct_access_msrs list at the
 872          * beginning of the file
 873          */
 874         WARN_ON(!valid_msr_intercept(msr));
 875
 876         offset    = svm_msrpm_offset(msr);
 877         bit_read  = 2 * (msr & 0x0f);
 878         bit_write = 2 * (msr & 0x0f) + 1;
 879         tmp       = msrpm[offset];
 880
 881         BUG_ON(offset == MSR_INVALID);
 882
 883         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 884         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 885
 886         msrpm[offset] = tmp;
 887 }
 888
 889 static void svm_vcpu_init_msrpm(u32 *msrpm)
 890 {
 891         int i;
 892
 893         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 894
 895         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 896                 if (!direct_access_msrs[i].always)
 897                         continue;
 898
 899                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 900         }
 901 }
 902
 903 static void add_msr_offset(u32 offset)
 904 {
 905         int i;
 906
 907         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 908
 909                 /* Offset already in list? */
 910                 if (msrpm_offsets[i] == offset)
 911                         return;
 912
 913                 /* Slot used by another offset? */
 914                 if (msrpm_offsets[i] != MSR_INVALID)
 915                         continue;
 916
 917                 /* Add offset to list */
 918                 msrpm_offsets[i] = offset;
 919
 920                 return;
 921         }
 922
 923         /*
 924          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 925          * increase MSRPM_OFFSETS in this case.
 926          */
 927         BUG();
 928 }
 929
 930 static void init_msrpm_offsets(void)
 931 {
 932         int i;
 933
 934         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 935
 936         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 937                 u32 offset;
 938
 939                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 940                 BUG_ON(offset == MSR_INVALID);
 941
 942                 add_msr_offset(offset);
 943         }
 944 }
 945
 946 static void svm_enable_lbrv(struct vcpu_svm *svm)
 947 {
 948         u32 *msrpm = svm->msrpm;
 949
 950         svm->vmcb->control.lbr_ctl = 1;
 951         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 952         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 953         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 954         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 955 }
 956
 957 static void svm_disable_lbrv(struct vcpu_svm *svm)
 958 {
 959         u32 *msrpm = svm->msrpm;
 960
 961         svm->vmcb->control.lbr_ctl = 0;
 962         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 963         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 964         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 965         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 966 }
 967
 968 /* Note:
 969  * This hash table is used to map VM_ID to a struct kvm_arch,
 970  * when handling AMD IOMMU GALOG notification to schedule in
 971  * a particular vCPU.
 972  */
 973 #define SVM_VM_DATA_HASH_BITS   8
 974 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
 975 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
 976
 977 /* Note:
 978  * This function is called from IOMMU driver to notify
 979  * SVM to schedule in a particular vCPU of a particular VM.
 980  */
 981 static int avic_ga_log_notifier(u32 ga_tag)
 982 {
 983         unsigned long flags;
 984         struct kvm_arch *ka = NULL;
 985         struct kvm_vcpu *vcpu = NULL;
 986         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
 987         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
 988
 989         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
 990
 991         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
 992         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
 993                 struct kvm *kvm = container_of(ka, struct kvm, arch);
 994                 struct kvm_arch *vm_data = &kvm->arch;
 995
 996                 if (vm_data->avic_vm_id != vm_id)
 997                         continue;
 998                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
 999                 break;
1000         }
1001         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1002
1003         if (!vcpu)
1004                 return 0;
1005
1006         /* Note:
1007          * At this point, the IOMMU should have already set the pending
1008          * bit in the vAPIC backing page. So, we just need to schedule
1009          * in the vcpu.
1010          */
1011         if (vcpu->mode == OUTSIDE_GUEST_MODE)
1012                 kvm_vcpu_wake_up(vcpu);
1013
1014         return 0;
1015 }
1016
1017 static __init int svm_hardware_setup(void)
1018 {
1019         int cpu;
1020         struct page *iopm_pages;
1021         void *iopm_va;
1022         int r;
1023
1024         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1025
1026         if (!iopm_pages)
1027                 return -ENOMEM;
1028
1029         iopm_va = page_address(iopm_pages);
1030         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1031         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1032
1033         init_msrpm_offsets();
1034
1035         if (boot_cpu_has(X86_FEATURE_NX))
1036                 kvm_enable_efer_bits(EFER_NX);
1037
1038         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1039                 kvm_enable_efer_bits(EFER_FFXSR);
1040
1041         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1042                 kvm_has_tsc_control = true;
1043                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1044                 kvm_tsc_scaling_ratio_frac_bits = 32;
1045         }
1046
1047         if (nested) {
1048                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1049                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1050         }
1051
1052         for_each_possible_cpu(cpu) {
1053                 r = svm_cpu_init(cpu);
1054                 if (r)
1055                         goto err;
1056         }
1057
1058         if (!boot_cpu_has(X86_FEATURE_NPT))
1059                 npt_enabled = false;
1060
1061         if (npt_enabled && !npt) {
1062                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1063                 npt_enabled = false;
1064         }
1065
1066         if (npt_enabled) {
1067                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1068                 kvm_enable_tdp();
1069         } else
1070                 kvm_disable_tdp();
1071
1072         if (avic) {
1073                 if (!npt_enabled ||
1074                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1075                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1076                         avic = false;
1077                 } else {
1078                         pr_info("AVIC enabled\n");
1079
1080                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1081                 }
1082         }
1083
1084         return 0;
1085
1086 err:
1087         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1088         iopm_base = 0;
1089         return r;
1090 }
1091
1092 static __exit void svm_hardware_unsetup(void)
1093 {
1094         int cpu;
1095
1096         for_each_possible_cpu(cpu)
1097                 svm_cpu_uninit(cpu);
1098
1099         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1100         iopm_base = 0;
1101 }
1102
1103 static void init_seg(struct vmcb_seg *seg)
1104 {
1105         seg->selector = 0;
1106         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1107                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1108         seg->limit = 0xffff;
1109         seg->base = 0;
1110 }
1111
1112 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1113 {
1114         seg->selector = 0;
1115         seg->attrib = SVM_SELECTOR_P_MASK | type;
1116         seg->limit = 0xffff;
1117         seg->base = 0;
1118 }
1119
1120 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1121 {
1122         struct vcpu_svm *svm = to_svm(vcpu);
1123         u64 g_tsc_offset = 0;
1124
1125         if (is_guest_mode(vcpu)) {
1126                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1127                                svm->nested.hsave->control.tsc_offset;
1128                 svm->nested.hsave->control.tsc_offset = offset;
1129         } else
1130                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1131                                            svm->vmcb->control.tsc_offset,
1132                                            offset);
1133
1134         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1135
1136         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1137 }
1138
1139 static void avic_init_vmcb(struct vcpu_svm *svm)
1140 {
1141         struct vmcb *vmcb = svm->vmcb;
1142         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1143         phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1144         phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1145         phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1146
1147         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1148         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1149         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1150         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1151         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1152         svm->vcpu.arch.apicv_active = true;
1153 }
1154
1155 static void init_vmcb(struct vcpu_svm *svm)
1156 {
1157         struct vmcb_control_area *control = &svm->vmcb->control;
1158         struct vmcb_save_area *save = &svm->vmcb->save;
1159
1160         svm->vcpu.arch.hflags = 0;
1161
1162         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1163         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1164         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1165         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1166         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1167         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1168         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1169                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1170
1171         set_dr_intercepts(svm);
1172
1173         set_exception_intercept(svm, PF_VECTOR);
1174         set_exception_intercept(svm, UD_VECTOR);
1175         set_exception_intercept(svm, MC_VECTOR);
1176         set_exception_intercept(svm, AC_VECTOR);
1177         set_exception_intercept(svm, DB_VECTOR);
1178
1179         set_intercept(svm, INTERCEPT_INTR);
1180         set_intercept(svm, INTERCEPT_NMI);
1181         set_intercept(svm, INTERCEPT_SMI);
1182         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1183         set_intercept(svm, INTERCEPT_RDPMC);
1184         set_intercept(svm, INTERCEPT_CPUID);
1185         set_intercept(svm, INTERCEPT_INVD);
1186         set_intercept(svm, INTERCEPT_HLT);
1187         set_intercept(svm, INTERCEPT_INVLPG);
1188         set_intercept(svm, INTERCEPT_INVLPGA);
1189         set_intercept(svm, INTERCEPT_IOIO_PROT);
1190         set_intercept(svm, INTERCEPT_MSR_PROT);
1191         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1192         set_intercept(svm, INTERCEPT_SHUTDOWN);
1193         set_intercept(svm, INTERCEPT_VMRUN);
1194         set_intercept(svm, INTERCEPT_VMMCALL);
1195         set_intercept(svm, INTERCEPT_VMLOAD);
1196         set_intercept(svm, INTERCEPT_VMSAVE);
1197         set_intercept(svm, INTERCEPT_STGI);
1198         set_intercept(svm, INTERCEPT_CLGI);
1199         set_intercept(svm, INTERCEPT_SKINIT);
1200         set_intercept(svm, INTERCEPT_WBINVD);
1201         set_intercept(svm, INTERCEPT_MONITOR);
1202         set_intercept(svm, INTERCEPT_MWAIT);
1203         set_intercept(svm, INTERCEPT_XSETBV);
1204
1205         control->iopm_base_pa = iopm_base;
1206         control->msrpm_base_pa = __pa(svm->msrpm);
1207         control->int_ctl = V_INTR_MASKING_MASK;
1208
1209         init_seg(&save->es);
1210         init_seg(&save->ss);
1211         init_seg(&save->ds);
1212         init_seg(&save->fs);
1213         init_seg(&save->gs);
1214
1215         save->cs.selector = 0xf000;
1216         save->cs.base = 0xffff0000;
1217         /* Executable/Readable Code Segment */
1218         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1219                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1220         save->cs.limit = 0xffff;
1221
1222         save->gdtr.limit = 0xffff;
1223         save->idtr.limit = 0xffff;
1224
1225         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1226         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1227
1228         svm_set_efer(&svm->vcpu, 0);
1229         save->dr6 = 0xffff0ff0;
1230         kvm_set_rflags(&svm->vcpu, 2);
1231         save->rip = 0x0000fff0;
1232         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1233
1234         /*
1235          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1236          * It also updates the guest-visible cr0 value.
1237          */
1238         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1239         kvm_mmu_reset_context(&svm->vcpu);
1240
1241         save->cr4 = X86_CR4_PAE;
1242         /* rdx = ?? */
1243
1244         if (npt_enabled) {
1245                 /* Setup VMCB for Nested Paging */
1246                 control->nested_ctl = 1;
1247                 clr_intercept(svm, INTERCEPT_INVLPG);
1248                 clr_exception_intercept(svm, PF_VECTOR);
1249                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1250                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1251                 save->g_pat = svm->vcpu.arch.pat;
1252                 save->cr3 = 0;
1253                 save->cr4 = 0;
1254         }
1255         svm->asid_generation = 0;
1256
1257         svm->nested.vmcb = 0;
1258         svm->vcpu.arch.hflags = 0;
1259
1260         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1261                 control->pause_filter_count = 3000;
1262                 set_intercept(svm, INTERCEPT_PAUSE);
1263         }
1264
1265         if (avic)
1266                 avic_init_vmcb(svm);
1267
1268         mark_all_dirty(svm->vmcb);
1269
1270         enable_gif(svm);
1271
1272 }
1273
1274 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1275 {
1276         u64 *avic_physical_id_table;
1277         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1278
1279         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1280                 return NULL;
1281
1282         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1283
1284         return &avic_physical_id_table[index];
1285 }
1286
1287 /**
1288  * Note:
1289  * AVIC hardware walks the nested page table to check permissions,
1290  * but does not use the SPA address specified in the leaf page
1291  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1292  * field of the VMCB. Therefore, we set up the
1293  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1294  */
1295 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1296 {
1297         struct kvm *kvm = vcpu->kvm;
1298         int ret;
1299
1300         if (kvm->arch.apic_access_page_done)
1301                 return 0;
1302
1303         ret = x86_set_memory_region(kvm,
1304                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1305                                     APIC_DEFAULT_PHYS_BASE,
1306                                     PAGE_SIZE);
1307         if (ret)
1308                 return ret;
1309
1310         kvm->arch.apic_access_page_done = true;
1311         return 0;
1312 }
1313
1314 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1315 {
1316         int ret;
1317         u64 *entry, new_entry;
1318         int id = vcpu->vcpu_id;
1319         struct vcpu_svm *svm = to_svm(vcpu);
1320
1321         ret = avic_init_access_page(vcpu);
1322         if (ret)
1323                 return ret;
1324
1325         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1326                 return -EINVAL;
1327
1328         if (!svm->vcpu.arch.apic->regs)
1329                 return -EINVAL;
1330
1331         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1332
1333         /* Setting AVIC backing page address in the phy APIC ID table */
1334         entry = avic_get_physical_id_entry(vcpu, id);
1335         if (!entry)
1336                 return -EINVAL;
1337
1338         new_entry = READ_ONCE(*entry);
1339         new_entry = (page_to_phys(svm->avic_backing_page) &
1340                      AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1341                      AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1342         WRITE_ONCE(*entry, new_entry);
1343
1344         svm->avic_physical_id_cache = entry;
1345
1346         return 0;
1347 }
1348
1349 static inline int avic_get_next_vm_id(void)
1350 {
1351         int id;
1352
1353         spin_lock(&avic_vm_id_lock);
1354
1355         /* AVIC VM ID is one-based. */
1356         id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1357         if (id <= AVIC_VM_ID_MASK)
1358                 __set_bit(id, avic_vm_id_bitmap);
1359         else
1360                 id = -EAGAIN;
1361
1362         spin_unlock(&avic_vm_id_lock);
1363         return id;
1364 }
1365
1366 static inline int avic_free_vm_id(int id)
1367 {
1368         if (id <= 0 || id > AVIC_VM_ID_MASK)
1369                 return -EINVAL;
1370
1371         spin_lock(&avic_vm_id_lock);
1372         __clear_bit(id, avic_vm_id_bitmap);
1373         spin_unlock(&avic_vm_id_lock);
1374         return 0;
1375 }
1376
1377 static void avic_vm_destroy(struct kvm *kvm)
1378 {
1379         unsigned long flags;
1380         struct kvm_arch *vm_data = &kvm->arch;
1381
1382         avic_free_vm_id(vm_data->avic_vm_id);
1383
1384         if (vm_data->avic_logical_id_table_page)
1385                 __free_page(vm_data->avic_logical_id_table_page);
1386         if (vm_data->avic_physical_id_table_page)
1387                 __free_page(vm_data->avic_physical_id_table_page);
1388
1389         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1390         hash_del(&vm_data->hnode);
1391         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1392 }
1393
1394 static int avic_vm_init(struct kvm *kvm)
1395 {
1396         unsigned long flags;
1397         int vm_id, err = -ENOMEM;
1398         struct kvm_arch *vm_data = &kvm->arch;
1399         struct page *p_page;
1400         struct page *l_page;
1401
1402         if (!avic)
1403                 return 0;
1404
1405         vm_id = avic_get_next_vm_id();
1406         if (vm_id < 0)
1407                 return vm_id;
1408         vm_data->avic_vm_id = (u32)vm_id;
1409
1410         /* Allocating physical APIC ID table (4KB) */
1411         p_page = alloc_page(GFP_KERNEL);
1412         if (!p_page)
1413                 goto free_avic;
1414
1415         vm_data->avic_physical_id_table_page = p_page;
1416         clear_page(page_address(p_page));
1417
1418         /* Allocating logical APIC ID table (4KB) */
1419         l_page = alloc_page(GFP_KERNEL);
1420         if (!l_page)
1421                 goto free_avic;
1422
1423         vm_data->avic_logical_id_table_page = l_page;
1424         clear_page(page_address(l_page));
1425
1426         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1427         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1428         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1429
1430         return 0;
1431
1432 free_avic:
1433         avic_vm_destroy(kvm);
1434         return err;
1435 }
1436
1437 static inline int
1438 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1439 {
1440         int ret = 0;
1441         unsigned long flags;
1442         struct amd_svm_iommu_ir *ir;
1443         struct vcpu_svm *svm = to_svm(vcpu);
1444
1445         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1446                 return 0;
1447
1448         /*
1449          * Here, we go through the per-vcpu ir_list to update all existing
1450          * interrupt remapping table entry targeting this vcpu.
1451          */
1452         spin_lock_irqsave(&svm->ir_list_lock, flags);
1453
1454         if (list_empty(&svm->ir_list))
1455                 goto out;
1456
1457         list_for_each_entry(ir, &svm->ir_list, node) {
1458                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1459                 if (ret)
1460                         break;
1461         }
1462 out:
1463         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1464         return ret;
1465 }
1466
1467 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1468 {
1469         u64 entry;
1470         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1471         int h_physical_id = kvm_cpu_get_apicid(cpu);
1472         struct vcpu_svm *svm = to_svm(vcpu);
1473
1474         if (!kvm_vcpu_apicv_active(vcpu))
1475                 return;
1476
1477         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1478                 return;
1479
1480         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1481         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1482
1483         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1484         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1485
1486         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1487         if (svm->avic_is_running)
1488                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1489
1490         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1491         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1492                                         svm->avic_is_running);
1493 }
1494
1495 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1496 {
1497         u64 entry;
1498         struct vcpu_svm *svm = to_svm(vcpu);
1499
1500         if (!kvm_vcpu_apicv_active(vcpu))
1501                 return;
1502
1503         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1504         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1505                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1506
1507         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1508         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1509 }
1510
1511 /**
1512  * This function is called during VCPU halt/unhalt.
1513  */
1514 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1515 {
1516         struct vcpu_svm *svm = to_svm(vcpu);
1517
1518         svm->avic_is_running = is_run;
1519         if (is_run)
1520                 avic_vcpu_load(vcpu, vcpu->cpu);
1521         else
1522                 avic_vcpu_put(vcpu);
1523 }
1524
1525 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1526 {
1527         struct vcpu_svm *svm = to_svm(vcpu);
1528         u32 dummy;
1529         u32 eax = 1;
1530
1531         if (!init_event) {
1532                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1533                                            MSR_IA32_APICBASE_ENABLE;
1534                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1535                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1536         }
1537         init_vmcb(svm);
1538
1539         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1540         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1541
1542         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1543                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1544 }
1545
1546 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1547 {
1548         struct vcpu_svm *svm;
1549         struct page *page;
1550         struct page *msrpm_pages;
1551         struct page *hsave_page;
1552         struct page *nested_msrpm_pages;
1553         int err;
1554
1555         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1556         if (!svm) {
1557                 err = -ENOMEM;
1558                 goto out;
1559         }
1560
1561         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1562         if (err)
1563                 goto free_svm;
1564
1565         err = -ENOMEM;
1566         page = alloc_page(GFP_KERNEL);
1567         if (!page)
1568                 goto uninit;
1569
1570         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1571         if (!msrpm_pages)
1572                 goto free_page1;
1573
1574         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1575         if (!nested_msrpm_pages)
1576                 goto free_page2;
1577
1578         hsave_page = alloc_page(GFP_KERNEL);
1579         if (!hsave_page)
1580                 goto free_page3;
1581
1582         if (avic) {
1583                 err = avic_init_backing_page(&svm->vcpu);
1584                 if (err)
1585                         goto free_page4;
1586
1587                 INIT_LIST_HEAD(&svm->ir_list);
1588                 spin_lock_init(&svm->ir_list_lock);
1589         }
1590
1591         /* We initialize this flag to true to make sure that the is_running
1592          * bit would be set the first time the vcpu is loaded.
1593          */
1594         svm->avic_is_running = true;
1595
1596         svm->nested.hsave = page_address(hsave_page);
1597
1598         svm->msrpm = page_address(msrpm_pages);
1599         svm_vcpu_init_msrpm(svm->msrpm);
1600
1601         svm->nested.msrpm = page_address(nested_msrpm_pages);
1602         svm_vcpu_init_msrpm(svm->nested.msrpm);
1603
1604         svm->vmcb = page_address(page);
1605         clear_page(svm->vmcb);
1606         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1607         svm->asid_generation = 0;
1608         init_vmcb(svm);
1609
1610         svm_init_osvw(&svm->vcpu);
1611
1612         return &svm->vcpu;
1613
1614 free_page4:
1615         __free_page(hsave_page);
1616 free_page3:
1617         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1618 free_page2:
1619         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1620 free_page1:
1621         __free_page(page);
1622 uninit:
1623         kvm_vcpu_uninit(&svm->vcpu);
1624 free_svm:
1625         kmem_cache_free(kvm_vcpu_cache, svm);
1626 out:
1627         return ERR_PTR(err);
1628 }
1629
1630 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1631 {
1632         struct vcpu_svm *svm = to_svm(vcpu);
1633
1634         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1635         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1636         __free_page(virt_to_page(svm->nested.hsave));
1637         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1638         kvm_vcpu_uninit(vcpu);
1639         kmem_cache_free(kvm_vcpu_cache, svm);
1640 }
1641
1642 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1643 {
1644         struct vcpu_svm *svm = to_svm(vcpu);
1645         int i;
1646
1647         if (unlikely(cpu != vcpu->cpu)) {
1648                 svm->asid_generation = 0;
1649                 mark_all_dirty(svm->vmcb);
1650         }
1651
1652 #ifdef CONFIG_X86_64
1653         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1654 #endif
1655         savesegment(fs, svm->host.fs);
1656         savesegment(gs, svm->host.gs);
1657         svm->host.ldt = kvm_read_ldt();
1658
1659         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1660                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1661
1662         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1663                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1664                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1665                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1666                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1667                 }
1668         }
1669         /* This assumes that the kernel never uses MSR_TSC_AUX */
1670         if (static_cpu_has(X86_FEATURE_RDTSCP))
1671                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1672
1673         avic_vcpu_load(vcpu, cpu);
1674 }
1675
1676 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1677 {
1678         struct vcpu_svm *svm = to_svm(vcpu);
1679         int i;
1680
1681         avic_vcpu_put(vcpu);
1682
1683         ++vcpu->stat.host_state_reload;
1684         kvm_load_ldt(svm->host.ldt);
1685 #ifdef CONFIG_X86_64
1686         loadsegment(fs, svm->host.fs);
1687         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1688         load_gs_index(svm->host.gs);
1689 #else
1690 #ifdef CONFIG_X86_32_LAZY_GS
1691         loadsegment(gs, svm->host.gs);
1692 #endif
1693 #endif
1694         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1695                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1696 }
1697
1698 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1699 {
1700         avic_set_running(vcpu, false);
1701 }
1702
1703 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1704 {
1705         avic_set_running(vcpu, true);
1706 }
1707
1708 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1709 {
1710         return to_svm(vcpu)->vmcb->save.rflags;
1711 }
1712
1713 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1714 {
1715        /*
1716         * Any change of EFLAGS.VM is accompanied by a reload of SS
1717         * (caused by either a task switch or an inter-privilege IRET),
1718         * so we do not need to update the CPL here.
1719         */
1720         to_svm(vcpu)->vmcb->save.rflags = rflags;
1721 }
1722
1723 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1724 {
1725         return 0;
1726 }
1727
1728 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1729 {
1730         switch (reg) {
1731         case VCPU_EXREG_PDPTR:
1732                 BUG_ON(!npt_enabled);
1733                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1734                 break;
1735         default:
1736                 BUG();
1737         }
1738 }
1739
1740 static void svm_set_vintr(struct vcpu_svm *svm)
1741 {
1742         set_intercept(svm, INTERCEPT_VINTR);
1743 }
1744
1745 static void svm_clear_vintr(struct vcpu_svm *svm)
1746 {
1747         clr_intercept(svm, INTERCEPT_VINTR);
1748 }
1749
1750 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1751 {
1752         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1753
1754         switch (seg) {
1755         case VCPU_SREG_CS: return &save->cs;
1756         case VCPU_SREG_DS: return &save->ds;
1757         case VCPU_SREG_ES: return &save->es;
1758         case VCPU_SREG_FS: return &save->fs;
1759         case VCPU_SREG_GS: return &save->gs;
1760         case VCPU_SREG_SS: return &save->ss;
1761         case VCPU_SREG_TR: return &save->tr;
1762         case VCPU_SREG_LDTR: return &save->ldtr;
1763         }
1764         BUG();
1765         return NULL;
1766 }
1767
1768 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1769 {
1770         struct vmcb_seg *s = svm_seg(vcpu, seg);
1771
1772         return s->base;
1773 }
1774
1775 static void svm_get_segment(struct kvm_vcpu *vcpu,
1776                             struct kvm_segment *var, int seg)
1777 {
1778         struct vmcb_seg *s = svm_seg(vcpu, seg);
1779
1780         var->base = s->base;
1781         var->limit = s->limit;
1782         var->selector = s->selector;
1783         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1784         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1785         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1786         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1787         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1788         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1789         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1790
1791         /*
1792          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1793          * However, the SVM spec states that the G bit is not observed by the
1794          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1795          * So let's synthesize a legal G bit for all segments, this helps
1796          * running KVM nested. It also helps cross-vendor migration, because
1797          * Intel's vmentry has a check on the 'G' bit.
1798          */
1799         var->g = s->limit > 0xfffff;
1800
1801         /*
1802          * AMD's VMCB does not have an explicit unusable field, so emulate it
1803          * for cross vendor migration purposes by "not present"
1804          */
1805         var->unusable = !var->present || (var->type == 0);
1806
1807         switch (seg) {
1808         case VCPU_SREG_TR:
1809                 /*
1810                  * Work around a bug where the busy flag in the tr selector
1811                  * isn't exposed
1812                  */
1813                 var->type |= 0x2;
1814                 break;
1815         case VCPU_SREG_DS:
1816         case VCPU_SREG_ES:
1817         case VCPU_SREG_FS:
1818         case VCPU_SREG_GS:
1819                 /*
1820                  * The accessed bit must always be set in the segment
1821                  * descriptor cache, although it can be cleared in the
1822                  * descriptor, the cached bit always remains at 1. Since
1823                  * Intel has a check on this, set it here to support
1824                  * cross-vendor migration.
1825                  */
1826                 if (!var->unusable)
1827                         var->type |= 0x1;
1828                 break;
1829         case VCPU_SREG_SS:
1830                 /*
1831                  * On AMD CPUs sometimes the DB bit in the segment
1832                  * descriptor is left as 1, although the whole segment has
1833                  * been made unusable. Clear it here to pass an Intel VMX
1834                  * entry check when cross vendor migrating.
1835                  */
1836                 if (var->unusable)
1837                         var->db = 0;
1838                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1839                 break;
1840         }
1841 }
1842
1843 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1844 {
1845         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1846
1847         return save->cpl;
1848 }
1849
1850 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1851 {
1852         struct vcpu_svm *svm = to_svm(vcpu);
1853
1854         dt->size = svm->vmcb->save.idtr.limit;
1855         dt->address = svm->vmcb->save.idtr.base;
1856 }
1857
1858 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1859 {
1860         struct vcpu_svm *svm = to_svm(vcpu);
1861
1862         svm->vmcb->save.idtr.limit = dt->size;
1863         svm->vmcb->save.idtr.base = dt->address ;
1864         mark_dirty(svm->vmcb, VMCB_DT);
1865 }
1866
1867 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1868 {
1869         struct vcpu_svm *svm = to_svm(vcpu);
1870
1871         dt->size = svm->vmcb->save.gdtr.limit;
1872         dt->address = svm->vmcb->save.gdtr.base;
1873 }
1874
1875 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1876 {
1877         struct vcpu_svm *svm = to_svm(vcpu);
1878
1879         svm->vmcb->save.gdtr.limit = dt->size;
1880         svm->vmcb->save.gdtr.base = dt->address ;
1881         mark_dirty(svm->vmcb, VMCB_DT);
1882 }
1883
1884 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1885 {
1886 }
1887
1888 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1889 {
1890 }
1891
1892 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1893 {
1894 }
1895
1896 static void update_cr0_intercept(struct vcpu_svm *svm)
1897 {
1898         ulong gcr0 = svm->vcpu.arch.cr0;
1899         u64 *hcr0 = &svm->vmcb->save.cr0;
1900
1901         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1902                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1903
1904         mark_dirty(svm->vmcb, VMCB_CR);
1905
1906         if (gcr0 == *hcr0) {
1907                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1908                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1909         } else {
1910                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1911                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1912         }
1913 }
1914
1915 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1916 {
1917         struct vcpu_svm *svm = to_svm(vcpu);
1918
1919 #ifdef CONFIG_X86_64
1920         if (vcpu->arch.efer & EFER_LME) {
1921                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1922                         vcpu->arch.efer |= EFER_LMA;
1923                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1924                 }
1925
1926                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1927                         vcpu->arch.efer &= ~EFER_LMA;
1928                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1929                 }
1930         }
1931 #endif
1932         vcpu->arch.cr0 = cr0;
1933
1934         if (!npt_enabled)
1935                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1936
1937         /*
1938          * re-enable caching here because the QEMU bios
1939          * does not do it - this results in some delay at
1940          * reboot
1941          */
1942         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1943                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1944         svm->vmcb->save.cr0 = cr0;
1945         mark_dirty(svm->vmcb, VMCB_CR);
1946         update_cr0_intercept(svm);
1947 }
1948
1949 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1950 {
1951         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1952         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1953
1954         if (cr4 & X86_CR4_VMXE)
1955                 return 1;
1956
1957         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1958                 svm_flush_tlb(vcpu);
1959
1960         vcpu->arch.cr4 = cr4;
1961         if (!npt_enabled)
1962                 cr4 |= X86_CR4_PAE;
1963         cr4 |= host_cr4_mce;
1964         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1965         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1966         return 0;
1967 }
1968
1969 static void svm_set_segment(struct kvm_vcpu *vcpu,
1970                             struct kvm_segment *var, int seg)
1971 {
1972         struct vcpu_svm *svm = to_svm(vcpu);
1973         struct vmcb_seg *s = svm_seg(vcpu, seg);
1974
1975         s->base = var->base;
1976         s->limit = var->limit;
1977         s->selector = var->selector;
1978         if (var->unusable)
1979                 s->attrib = 0;
1980         else {
1981                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1982                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1983                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1984                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1985                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1986                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1987                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1988                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1989         }
1990
1991         /*
1992          * This is always accurate, except if SYSRET returned to a segment
1993          * with SS.DPL != 3.  Intel does not have this quirk, and always
1994          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1995          * would entail passing the CPL to userspace and back.
1996          */
1997         if (seg == VCPU_SREG_SS)
1998                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1999
2000         mark_dirty(svm->vmcb, VMCB_SEG);
2001 }
2002
2003 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2004 {
2005         struct vcpu_svm *svm = to_svm(vcpu);
2006
2007         clr_exception_intercept(svm, BP_VECTOR);
2008
2009         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2010                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2011                         set_exception_intercept(svm, BP_VECTOR);
2012         } else
2013                 vcpu->guest_debug = 0;
2014 }
2015
2016 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2017 {
2018         if (sd->next_asid > sd->max_asid) {
2019                 ++sd->asid_generation;
2020                 sd->next_asid = 1;
2021                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2022         }
2023
2024         svm->asid_generation = sd->asid_generation;
2025         svm->vmcb->control.asid = sd->next_asid++;
2026
2027         mark_dirty(svm->vmcb, VMCB_ASID);
2028 }
2029
2030 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2031 {
2032         return to_svm(vcpu)->vmcb->save.dr6;
2033 }
2034
2035 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2036 {
2037         struct vcpu_svm *svm = to_svm(vcpu);
2038
2039         svm->vmcb->save.dr6 = value;
2040         mark_dirty(svm->vmcb, VMCB_DR);
2041 }
2042
2043 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2044 {
2045         struct vcpu_svm *svm = to_svm(vcpu);
2046
2047         get_debugreg(vcpu->arch.db[0], 0);
2048         get_debugreg(vcpu->arch.db[1], 1);
2049         get_debugreg(vcpu->arch.db[2], 2);
2050         get_debugreg(vcpu->arch.db[3], 3);
2051         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2052         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2053
2054         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2055         set_dr_intercepts(svm);
2056 }
2057
2058 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2059 {
2060         struct vcpu_svm *svm = to_svm(vcpu);
2061
2062         svm->vmcb->save.dr7 = value;
2063         mark_dirty(svm->vmcb, VMCB_DR);
2064 }
2065
2066 static int pf_interception(struct vcpu_svm *svm)
2067 {
2068         u64 fault_address = svm->vmcb->control.exit_info_2;
2069         u64 error_code;
2070         int r = 1;
2071
2072         switch (svm->apf_reason) {
2073         default:
2074                 error_code = svm->vmcb->control.exit_info_1;
2075
2076                 trace_kvm_page_fault(fault_address, error_code);
2077                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2078                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2079                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2080                         svm->vmcb->control.insn_bytes,
2081                         svm->vmcb->control.insn_len);
2082                 break;
2083         case KVM_PV_REASON_PAGE_NOT_PRESENT:
2084                 svm->apf_reason = 0;
2085                 local_irq_disable();
2086                 kvm_async_pf_task_wait(fault_address);
2087                 local_irq_enable();
2088                 break;
2089         case KVM_PV_REASON_PAGE_READY:
2090                 svm->apf_reason = 0;
2091                 local_irq_disable();
2092                 kvm_async_pf_task_wake(fault_address);
2093                 local_irq_enable();
2094                 break;
2095         }
2096         return r;
2097 }
2098
2099 static int db_interception(struct vcpu_svm *svm)
2100 {
2101         struct kvm_run *kvm_run = svm->vcpu.run;
2102
2103         if (!(svm->vcpu.guest_debug &
2104               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2105                 !svm->nmi_singlestep) {
2106                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2107                 return 1;
2108         }
2109
2110         if (svm->nmi_singlestep) {
2111                 svm->nmi_singlestep = false;
2112                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2113                         svm->vmcb->save.rflags &=
2114                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2115         }
2116
2117         if (svm->vcpu.guest_debug &
2118             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2119                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2120                 kvm_run->debug.arch.pc =
2121                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2122                 kvm_run->debug.arch.exception = DB_VECTOR;
2123                 return 0;
2124         }
2125
2126         return 1;
2127 }
2128
2129 static int bp_interception(struct vcpu_svm *svm)
2130 {
2131         struct kvm_run *kvm_run = svm->vcpu.run;
2132
2133         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2134         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2135         kvm_run->debug.arch.exception = BP_VECTOR;
2136         return 0;
2137 }
2138
2139 static int ud_interception(struct vcpu_svm *svm)
2140 {
2141         int er;
2142
2143         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2144         if (er != EMULATE_DONE)
2145                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2146         return 1;
2147 }
2148
2149 static int ac_interception(struct vcpu_svm *svm)
2150 {
2151         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2152         return 1;
2153 }
2154
2155 static bool is_erratum_383(void)
2156 {
2157         int err, i;
2158         u64 value;
2159
2160         if (!erratum_383_found)
2161                 return false;
2162
2163         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2164         if (err)
2165                 return false;
2166
2167         /* Bit 62 may or may not be set for this mce */
2168         value &= ~(1ULL << 62);
2169
2170         if (value != 0xb600000000010015ULL)
2171                 return false;
2172
2173         /* Clear MCi_STATUS registers */
2174         for (i = 0; i < 6; ++i)
2175                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2176
2177         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2178         if (!err) {
2179                 u32 low, high;
2180
2181                 value &= ~(1ULL << 2);
2182                 low    = lower_32_bits(value);
2183                 high   = upper_32_bits(value);
2184
2185                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2186         }
2187
2188         /* Flush tlb to evict multi-match entries */
2189         __flush_tlb_all();
2190
2191         return true;
2192 }
2193
2194 static void svm_handle_mce(struct vcpu_svm *svm)
2195 {
2196         if (is_erratum_383()) {
2197                 /*
2198                  * Erratum 383 triggered. Guest state is corrupt so kill the
2199                  * guest.
2200                  */
2201                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2202
2203                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2204
2205                 return;
2206         }
2207
2208         /*
2209          * On an #MC intercept the MCE handler is not called automatically in
2210          * the host. So do it by hand here.
2211          */
2212         asm volatile (
2213                 "int $0x12\n");
2214         /* not sure if we ever come back to this point */
2215
2216         return;
2217 }
2218
2219 static int mc_interception(struct vcpu_svm *svm)
2220 {
2221         return 1;
2222 }
2223
2224 static int shutdown_interception(struct vcpu_svm *svm)
2225 {
2226         struct kvm_run *kvm_run = svm->vcpu.run;
2227
2228         /*
2229          * VMCB is undefined after a SHUTDOWN intercept
2230          * so reinitialize it.
2231          */
2232         clear_page(svm->vmcb);
2233         init_vmcb(svm);
2234
2235         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2236         return 0;
2237 }
2238
2239 static int io_interception(struct vcpu_svm *svm)
2240 {
2241         struct kvm_vcpu *vcpu = &svm->vcpu;
2242         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2243         int size, in, string;
2244         unsigned port;
2245
2246         ++svm->vcpu.stat.io_exits;
2247         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2248         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2249         if (string)
2250                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2251
2252         port = io_info >> 16;
2253         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2254         svm->next_rip = svm->vmcb->control.exit_info_2;
2255         skip_emulated_instruction(&svm->vcpu);
2256
2257         return in ? kvm_fast_pio_in(vcpu, size, port)
2258                   : kvm_fast_pio_out(vcpu, size, port);
2259 }
2260
2261 static int nmi_interception(struct vcpu_svm *svm)
2262 {
2263         return 1;
2264 }
2265
2266 static int intr_interception(struct vcpu_svm *svm)
2267 {
2268         ++svm->vcpu.stat.irq_exits;
2269         return 1;
2270 }
2271
2272 static int nop_on_interception(struct vcpu_svm *svm)
2273 {
2274         return 1;
2275 }
2276
2277 static int halt_interception(struct vcpu_svm *svm)
2278 {
2279         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2280         return kvm_emulate_halt(&svm->vcpu);
2281 }
2282
2283 static int vmmcall_interception(struct vcpu_svm *svm)
2284 {
2285         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2286         return kvm_emulate_hypercall(&svm->vcpu);
2287 }
2288
2289 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2290 {
2291         struct vcpu_svm *svm = to_svm(vcpu);
2292
2293         return svm->nested.nested_cr3;
2294 }
2295
2296 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2297 {
2298         struct vcpu_svm *svm = to_svm(vcpu);
2299         u64 cr3 = svm->nested.nested_cr3;
2300         u64 pdpte;
2301         int ret;
2302
2303         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2304                                        offset_in_page(cr3) + index * 8, 8);
2305         if (ret)
2306                 return 0;
2307         return pdpte;
2308 }
2309
2310 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2311                                    unsigned long root)
2312 {
2313         struct vcpu_svm *svm = to_svm(vcpu);
2314
2315         svm->vmcb->control.nested_cr3 = root;
2316         mark_dirty(svm->vmcb, VMCB_NPT);
2317         svm_flush_tlb(vcpu);
2318 }
2319
2320 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2321                                        struct x86_exception *fault)
2322 {
2323         struct vcpu_svm *svm = to_svm(vcpu);
2324
2325         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2326                 /*
2327                  * TODO: track the cause of the nested page fault, and
2328                  * correctly fill in the high bits of exit_info_1.
2329                  */
2330                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2331                 svm->vmcb->control.exit_code_hi = 0;
2332                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2333                 svm->vmcb->control.exit_info_2 = fault->address;
2334         }
2335
2336         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2337         svm->vmcb->control.exit_info_1 |= fault->error_code;
2338
2339         /*
2340          * The present bit is always zero for page structure faults on real
2341          * hardware.
2342          */
2343         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2344                 svm->vmcb->control.exit_info_1 &= ~1;
2345
2346         nested_svm_vmexit(svm);
2347 }
2348
2349 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2350 {
2351         WARN_ON(mmu_is_nested(vcpu));
2352         kvm_init_shadow_mmu(vcpu);
2353         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2354         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2355         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2356         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2357         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2358         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2359         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2360 }
2361
2362 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2363 {
2364         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2365 }
2366
2367 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2368 {
2369         if (!(svm->vcpu.arch.efer & EFER_SVME)
2370             || !is_paging(&svm->vcpu)) {
2371                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2372                 return 1;
2373         }
2374
2375         if (svm->vmcb->save.cpl) {
2376                 kvm_inject_gp(&svm->vcpu, 0);
2377                 return 1;
2378         }
2379
2380        return 0;
2381 }
2382
2383 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2384                                       bool has_error_code, u32 error_code)
2385 {
2386         int vmexit;
2387
2388         if (!is_guest_mode(&svm->vcpu))
2389                 return 0;
2390
2391         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2392         svm->vmcb->control.exit_code_hi = 0;
2393         svm->vmcb->control.exit_info_1 = error_code;
2394         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2395
2396         vmexit = nested_svm_intercept(svm);
2397         if (vmexit == NESTED_EXIT_DONE)
2398                 svm->nested.exit_required = true;
2399
2400         return vmexit;
2401 }
2402
2403 /* This function returns true if it is save to enable the irq window */
2404 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2405 {
2406         if (!is_guest_mode(&svm->vcpu))
2407                 return true;
2408
2409         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2410                 return true;
2411
2412         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2413                 return false;
2414
2415         /*
2416          * if vmexit was already requested (by intercepted exception
2417          * for instance) do not overwrite it with "external interrupt"
2418          * vmexit.
2419          */
2420         if (svm->nested.exit_required)
2421                 return false;
2422
2423         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2424         svm->vmcb->control.exit_info_1 = 0;
2425         svm->vmcb->control.exit_info_2 = 0;
2426
2427         if (svm->nested.intercept & 1ULL) {
2428                 /*
2429                  * The #vmexit can't be emulated here directly because this
2430                  * code path runs with irqs and preemption disabled. A
2431                  * #vmexit emulation might sleep. Only signal request for
2432                  * the #vmexit here.
2433                  */
2434                 svm->nested.exit_required = true;
2435                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2436                 return false;
2437         }
2438
2439         return true;
2440 }
2441
2442 /* This function returns true if it is save to enable the nmi window */
2443 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2444 {
2445         if (!is_guest_mode(&svm->vcpu))
2446                 return true;
2447
2448         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2449                 return true;
2450
2451         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2452         svm->nested.exit_required = true;
2453
2454         return false;
2455 }
2456
2457 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2458 {
2459         struct page *page;
2460
2461         might_sleep();
2462
2463         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2464         if (is_error_page(page))
2465                 goto error;
2466
2467         *_page = page;
2468
2469         return kmap(page);
2470
2471 error:
2472         kvm_inject_gp(&svm->vcpu, 0);
2473
2474         return NULL;
2475 }
2476
2477 static void nested_svm_unmap(struct page *page)
2478 {
2479         kunmap(page);
2480         kvm_release_page_dirty(page);
2481 }
2482
2483 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2484 {
2485         unsigned port, size, iopm_len;
2486         u16 val, mask;
2487         u8 start_bit;
2488         u64 gpa;
2489
2490         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2491                 return NESTED_EXIT_HOST;
2492
2493         port = svm->vmcb->control.exit_info_1 >> 16;
2494         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2495                 SVM_IOIO_SIZE_SHIFT;
2496         gpa  = svm->nested.vmcb_iopm + (port / 8);
2497         start_bit = port % 8;
2498         iopm_len = (start_bit + size > 8) ? 2 : 1;
2499         mask = (0xf >> (4 - size)) << start_bit;
2500         val = 0;
2501
2502         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2503                 return NESTED_EXIT_DONE;
2504
2505         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2506 }
2507
2508 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2509 {
2510         u32 offset, msr, value;
2511         int write, mask;
2512
2513         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2514                 return NESTED_EXIT_HOST;
2515
2516         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2517         offset = svm_msrpm_offset(msr);
2518         write  = svm->vmcb->control.exit_info_1 & 1;
2519         mask   = 1 << ((2 * (msr & 0xf)) + write);
2520
2521         if (offset == MSR_INVALID)
2522                 return NESTED_EXIT_DONE;
2523
2524         /* Offset is in 32 bit units but need in 8 bit units */
2525         offset *= 4;
2526
2527         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2528                 return NESTED_EXIT_DONE;
2529
2530         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2531 }
2532
2533 static int nested_svm_exit_special(struct vcpu_svm *svm)
2534 {
2535         u32 exit_code = svm->vmcb->control.exit_code;
2536
2537         switch (exit_code) {
2538         case SVM_EXIT_INTR:
2539         case SVM_EXIT_NMI:
2540         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2541                 return NESTED_EXIT_HOST;
2542         case SVM_EXIT_NPF:
2543                 /* For now we are always handling NPFs when using them */
2544                 if (npt_enabled)
2545                         return NESTED_EXIT_HOST;
2546                 break;
2547         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2548                 /* When we're shadowing, trap PFs, but not async PF */
2549                 if (!npt_enabled && svm->apf_reason == 0)
2550                         return NESTED_EXIT_HOST;
2551                 break;
2552         default:
2553                 break;
2554         }
2555
2556         return NESTED_EXIT_CONTINUE;
2557 }
2558
2559 /*
2560  * If this function returns true, this #vmexit was already handled
2561  */
2562 static int nested_svm_intercept(struct vcpu_svm *svm)
2563 {
2564         u32 exit_code = svm->vmcb->control.exit_code;
2565         int vmexit = NESTED_EXIT_HOST;
2566
2567         switch (exit_code) {
2568         case SVM_EXIT_MSR:
2569                 vmexit = nested_svm_exit_handled_msr(svm);
2570                 break;
2571         case SVM_EXIT_IOIO:
2572                 vmexit = nested_svm_intercept_ioio(svm);
2573                 break;
2574         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2575                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2576                 if (svm->nested.intercept_cr & bit)
2577                         vmexit = NESTED_EXIT_DONE;
2578                 break;
2579         }
2580         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2581                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2582                 if (svm->nested.intercept_dr & bit)
2583                         vmexit = NESTED_EXIT_DONE;
2584                 break;
2585         }
2586         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2587                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2588                 if (svm->nested.intercept_exceptions & excp_bits)
2589                         vmexit = NESTED_EXIT_DONE;
2590                 /* async page fault always cause vmexit */
2591                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2592                          svm->apf_reason != 0)
2593                         vmexit = NESTED_EXIT_DONE;
2594                 break;
2595         }
2596         case SVM_EXIT_ERR: {
2597                 vmexit = NESTED_EXIT_DONE;
2598                 break;
2599         }
2600         default: {
2601                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2602                 if (svm->nested.intercept & exit_bits)
2603                         vmexit = NESTED_EXIT_DONE;
2604         }
2605         }
2606
2607         return vmexit;
2608 }
2609
2610 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2611 {
2612         int vmexit;
2613
2614         vmexit = nested_svm_intercept(svm);
2615
2616         if (vmexit == NESTED_EXIT_DONE)
2617                 nested_svm_vmexit(svm);
2618
2619         return vmexit;
2620 }
2621
2622 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2623 {
2624         struct vmcb_control_area *dst  = &dst_vmcb->control;
2625         struct vmcb_control_area *from = &from_vmcb->control;
2626
2627         dst->intercept_cr         = from->intercept_cr;
2628         dst->intercept_dr         = from->intercept_dr;
2629         dst->intercept_exceptions = from->intercept_exceptions;
2630         dst->intercept            = from->intercept;
2631         dst->iopm_base_pa         = from->iopm_base_pa;
2632         dst->msrpm_base_pa        = from->msrpm_base_pa;
2633         dst->tsc_offset           = from->tsc_offset;
2634         dst->asid                 = from->asid;
2635         dst->tlb_ctl              = from->tlb_ctl;
2636         dst->int_ctl              = from->int_ctl;
2637         dst->int_vector           = from->int_vector;
2638         dst->int_state            = from->int_state;
2639         dst->exit_code            = from->exit_code;
2640         dst->exit_code_hi         = from->exit_code_hi;
2641         dst->exit_info_1          = from->exit_info_1;
2642         dst->exit_info_2          = from->exit_info_2;
2643         dst->exit_int_info        = from->exit_int_info;
2644         dst->exit_int_info_err    = from->exit_int_info_err;
2645         dst->nested_ctl           = from->nested_ctl;
2646         dst->event_inj            = from->event_inj;
2647         dst->event_inj_err        = from->event_inj_err;
2648         dst->nested_cr3           = from->nested_cr3;
2649         dst->lbr_ctl              = from->lbr_ctl;
2650 }
2651
2652 static int nested_svm_vmexit(struct vcpu_svm *svm)
2653 {
2654         struct vmcb *nested_vmcb;
2655         struct vmcb *hsave = svm->nested.hsave;
2656         struct vmcb *vmcb = svm->vmcb;
2657         struct page *page;
2658
2659         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2660                                        vmcb->control.exit_info_1,
2661                                        vmcb->control.exit_info_2,
2662                                        vmcb->control.exit_int_info,
2663                                        vmcb->control.exit_int_info_err,
2664                                        KVM_ISA_SVM);
2665
2666         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2667         if (!nested_vmcb)
2668                 return 1;
2669
2670         /* Exit Guest-Mode */
2671         leave_guest_mode(&svm->vcpu);
2672         svm->nested.vmcb = 0;
2673
2674         /* Give the current vmcb to the guest */
2675         disable_gif(svm);
2676
2677         nested_vmcb->save.es     = vmcb->save.es;
2678         nested_vmcb->save.cs     = vmcb->save.cs;
2679         nested_vmcb->save.ss     = vmcb->save.ss;
2680         nested_vmcb->save.ds     = vmcb->save.ds;
2681         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2682         nested_vmcb->save.idtr   = vmcb->save.idtr;
2683         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2684         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2685         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2686         nested_vmcb->save.cr2    = vmcb->save.cr2;
2687         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2688         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2689         nested_vmcb->save.rip    = vmcb->save.rip;
2690         nested_vmcb->save.rsp    = vmcb->save.rsp;
2691         nested_vmcb->save.rax    = vmcb->save.rax;
2692         nested_vmcb->save.dr7    = vmcb->save.dr7;
2693         nested_vmcb->save.dr6    = vmcb->save.dr6;
2694         nested_vmcb->save.cpl    = vmcb->save.cpl;
2695
2696         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2697         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2698         nested_vmcb->control.int_state         = vmcb->control.int_state;
2699         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2700         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2701         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2702         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2703         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2704         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2705
2706         if (svm->nrips_enabled)
2707                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2708
2709         /*
2710          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2711          * to make sure that we do not lose injected events. So check event_inj
2712          * here and copy it to exit_int_info if it is valid.
2713          * Exit_int_info and event_inj can't be both valid because the case
2714          * below only happens on a VMRUN instruction intercept which has
2715          * no valid exit_int_info set.
2716          */
2717         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2718                 struct vmcb_control_area *nc = &nested_vmcb->control;
2719
2720                 nc->exit_int_info     = vmcb->control.event_inj;
2721                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2722         }
2723
2724         nested_vmcb->control.tlb_ctl           = 0;
2725         nested_vmcb->control.event_inj         = 0;
2726         nested_vmcb->control.event_inj_err     = 0;
2727
2728         /* We always set V_INTR_MASKING and remember the old value in hflags */
2729         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2730                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2731
2732         /* Restore the original control entries */
2733         copy_vmcb_control_area(vmcb, hsave);
2734
2735         kvm_clear_exception_queue(&svm->vcpu);
2736         kvm_clear_interrupt_queue(&svm->vcpu);
2737
2738         svm->nested.nested_cr3 = 0;
2739
2740         /* Restore selected save entries */
2741         svm->vmcb->save.es = hsave->save.es;
2742         svm->vmcb->save.cs = hsave->save.cs;
2743         svm->vmcb->save.ss = hsave->save.ss;
2744         svm->vmcb->save.ds = hsave->save.ds;
2745         svm->vmcb->save.gdtr = hsave->save.gdtr;
2746         svm->vmcb->save.idtr = hsave->save.idtr;
2747         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2748         svm_set_efer(&svm->vcpu, hsave->save.efer);
2749         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2750         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2751         if (npt_enabled) {
2752                 svm->vmcb->save.cr3 = hsave->save.cr3;
2753                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2754         } else {
2755                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2756         }
2757         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2758         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2759         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2760         svm->vmcb->save.dr7 = 0;
2761         svm->vmcb->save.cpl = 0;
2762         svm->vmcb->control.exit_int_info = 0;
2763
2764         mark_all_dirty(svm->vmcb);
2765
2766         nested_svm_unmap(page);
2767
2768         nested_svm_uninit_mmu_context(&svm->vcpu);
2769         kvm_mmu_reset_context(&svm->vcpu);
2770         kvm_mmu_load(&svm->vcpu);
2771
2772         return 0;
2773 }
2774
2775 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2776 {
2777         /*
2778          * This function merges the msr permission bitmaps of kvm and the
2779          * nested vmcb. It is optimized in that it only merges the parts where
2780          * the kvm msr permission bitmap may contain zero bits
2781          */
2782         int i;
2783
2784         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2785                 return true;
2786
2787         for (i = 0; i < MSRPM_OFFSETS; i++) {
2788                 u32 value, p;
2789                 u64 offset;
2790
2791                 if (msrpm_offsets[i] == 0xffffffff)
2792                         break;
2793
2794                 p      = msrpm_offsets[i];
2795                 offset = svm->nested.vmcb_msrpm + (p * 4);
2796
2797                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2798                         return false;
2799
2800                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2801         }
2802
2803         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2804
2805         return true;
2806 }
2807
2808 static bool nested_vmcb_checks(struct vmcb *vmcb)
2809 {
2810         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2811                 return false;
2812
2813         if (vmcb->control.asid == 0)
2814                 return false;
2815
2816         if (vmcb->control.nested_ctl && !npt_enabled)
2817                 return false;
2818
2819         return true;
2820 }
2821
2822 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2823 {
2824         struct vmcb *nested_vmcb;
2825         struct vmcb *hsave = svm->nested.hsave;
2826         struct vmcb *vmcb = svm->vmcb;
2827         struct page *page;
2828         u64 vmcb_gpa;
2829
2830         vmcb_gpa = svm->vmcb->save.rax;
2831
2832         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2833         if (!nested_vmcb)
2834                 return false;
2835
2836         if (!nested_vmcb_checks(nested_vmcb)) {
2837                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2838                 nested_vmcb->control.exit_code_hi = 0;
2839                 nested_vmcb->control.exit_info_1  = 0;
2840                 nested_vmcb->control.exit_info_2  = 0;
2841
2842                 nested_svm_unmap(page);
2843
2844                 return false;
2845         }
2846
2847         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2848                                nested_vmcb->save.rip,
2849                                nested_vmcb->control.int_ctl,
2850                                nested_vmcb->control.event_inj,
2851                                nested_vmcb->control.nested_ctl);
2852
2853         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2854                                     nested_vmcb->control.intercept_cr >> 16,
2855                                     nested_vmcb->control.intercept_exceptions,
2856                                     nested_vmcb->control.intercept);
2857
2858         /* Clear internal status */
2859         kvm_clear_exception_queue(&svm->vcpu);
2860         kvm_clear_interrupt_queue(&svm->vcpu);
2861
2862         /*
2863          * Save the old vmcb, so we don't need to pick what we save, but can
2864          * restore everything when a VMEXIT occurs
2865          */
2866         hsave->save.es     = vmcb->save.es;
2867         hsave->save.cs     = vmcb->save.cs;
2868         hsave->save.ss     = vmcb->save.ss;
2869         hsave->save.ds     = vmcb->save.ds;
2870         hsave->save.gdtr   = vmcb->save.gdtr;
2871         hsave->save.idtr   = vmcb->save.idtr;
2872         hsave->save.efer   = svm->vcpu.arch.efer;
2873         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2874         hsave->save.cr4    = svm->vcpu.arch.cr4;
2875         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2876         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2877         hsave->save.rsp    = vmcb->save.rsp;
2878         hsave->save.rax    = vmcb->save.rax;
2879         if (npt_enabled)
2880                 hsave->save.cr3    = vmcb->save.cr3;
2881         else
2882                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2883
2884         copy_vmcb_control_area(hsave, vmcb);
2885
2886         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2887                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2888         else
2889                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2890
2891         if (nested_vmcb->control.nested_ctl) {
2892                 kvm_mmu_unload(&svm->vcpu);
2893                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2894                 nested_svm_init_mmu_context(&svm->vcpu);
2895         }
2896
2897         /* Load the nested guest state */
2898         svm->vmcb->save.es = nested_vmcb->save.es;
2899         svm->vmcb->save.cs = nested_vmcb->save.cs;
2900         svm->vmcb->save.ss = nested_vmcb->save.ss;
2901         svm->vmcb->save.ds = nested_vmcb->save.ds;
2902         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2903         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2904         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2905         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2906         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2907         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2908         if (npt_enabled) {
2909                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2910                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2911         } else
2912                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2913
2914         /* Guest paging mode is active - reset mmu */
2915         kvm_mmu_reset_context(&svm->vcpu);
2916
2917         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2918         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2919         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2920         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2921
2922         /* In case we don't even reach vcpu_run, the fields are not updated */
2923         svm->vmcb->save.rax = nested_vmcb->save.rax;
2924         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2925         svm->vmcb->save.rip = nested_vmcb->save.rip;
2926         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2927         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2928         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2929
2930         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2931         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2932
2933         /* cache intercepts */
2934         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2935         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2936         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2937         svm->nested.intercept            = nested_vmcb->control.intercept;
2938
2939         svm_flush_tlb(&svm->vcpu);
2940         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2941         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2942                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2943         else
2944                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2945
2946         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2947                 /* We only want the cr8 intercept bits of the guest */
2948                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2949                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2950         }
2951
2952         /* We don't want to see VMMCALLs from a nested guest */
2953         clr_intercept(svm, INTERCEPT_VMMCALL);
2954
2955         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2956         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2957         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2958         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2959         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2960         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2961
2962         nested_svm_unmap(page);
2963
2964         /* Enter Guest-Mode */
2965         enter_guest_mode(&svm->vcpu);
2966
2967         /*
2968          * Merge guest and host intercepts - must be called  with vcpu in
2969          * guest-mode to take affect here
2970          */
2971         recalc_intercepts(svm);
2972
2973         svm->nested.vmcb = vmcb_gpa;
2974
2975         enable_gif(svm);
2976
2977         mark_all_dirty(svm->vmcb);
2978
2979         return true;
2980 }
2981
2982 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2983 {
2984         to_vmcb->save.fs = from_vmcb->save.fs;
2985         to_vmcb->save.gs = from_vmcb->save.gs;
2986         to_vmcb->save.tr = from_vmcb->save.tr;
2987         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2988         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2989         to_vmcb->save.star = from_vmcb->save.star;
2990         to_vmcb->save.lstar = from_vmcb->save.lstar;
2991         to_vmcb->save.cstar = from_vmcb->save.cstar;
2992         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2993         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2994         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2995         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2996 }
2997
2998 static int vmload_interception(struct vcpu_svm *svm)
2999 {
3000         struct vmcb *nested_vmcb;
3001         struct page *page;
3002
3003         if (nested_svm_check_permissions(svm))
3004                 return 1;
3005
3006         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3007         if (!nested_vmcb)
3008                 return 1;
3009
3010         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3011         skip_emulated_instruction(&svm->vcpu);
3012
3013         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3014         nested_svm_unmap(page);
3015
3016         return 1;
3017 }
3018
3019 static int vmsave_interception(struct vcpu_svm *svm)
3020 {
3021         struct vmcb *nested_vmcb;
3022         struct page *page;
3023
3024         if (nested_svm_check_permissions(svm))
3025                 return 1;
3026
3027         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3028         if (!nested_vmcb)
3029                 return 1;
3030
3031         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3032         skip_emulated_instruction(&svm->vcpu);
3033
3034         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3035         nested_svm_unmap(page);
3036
3037         return 1;
3038 }
3039
3040 static int vmrun_interception(struct vcpu_svm *svm)
3041 {
3042         if (nested_svm_check_permissions(svm))
3043                 return 1;
3044
3045         /* Save rip after vmrun instruction */
3046         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3047
3048         if (!nested_svm_vmrun(svm))
3049                 return 1;
3050
3051         if (!nested_svm_vmrun_msrpm(svm))
3052                 goto failed;
3053
3054         return 1;
3055
3056 failed:
3057
3058         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3059         svm->vmcb->control.exit_code_hi = 0;
3060         svm->vmcb->control.exit_info_1  = 0;
3061         svm->vmcb->control.exit_info_2  = 0;
3062
3063         nested_svm_vmexit(svm);
3064
3065         return 1;
3066 }
3067
3068 static int stgi_interception(struct vcpu_svm *svm)
3069 {
3070         if (nested_svm_check_permissions(svm))
3071                 return 1;
3072
3073         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3074         skip_emulated_instruction(&svm->vcpu);
3075         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3076
3077         enable_gif(svm);
3078
3079         return 1;
3080 }
3081
3082 static int clgi_interception(struct vcpu_svm *svm)
3083 {
3084         if (nested_svm_check_permissions(svm))
3085                 return 1;
3086
3087         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3088         skip_emulated_instruction(&svm->vcpu);
3089
3090         disable_gif(svm);
3091
3092         /* After a CLGI no interrupts should come */
3093         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3094                 svm_clear_vintr(svm);
3095                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3096                 mark_dirty(svm->vmcb, VMCB_INTR);
3097         }
3098
3099         return 1;
3100 }
3101
3102 static int invlpga_interception(struct vcpu_svm *svm)
3103 {
3104         struct kvm_vcpu *vcpu = &svm->vcpu;
3105
3106         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3107                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3108
3109         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3110         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3111
3112         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3113         skip_emulated_instruction(&svm->vcpu);
3114         return 1;
3115 }
3116
3117 static int skinit_interception(struct vcpu_svm *svm)
3118 {
3119         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3120
3121         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3122         return 1;
3123 }
3124
3125 static int wbinvd_interception(struct vcpu_svm *svm)
3126 {
3127         return kvm_emulate_wbinvd(&svm->vcpu);
3128 }
3129
3130 static int xsetbv_interception(struct vcpu_svm *svm)
3131 {
3132         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3133         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3134
3135         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3136                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3137                 skip_emulated_instruction(&svm->vcpu);
3138         }
3139
3140         return 1;
3141 }
3142
3143 static int task_switch_interception(struct vcpu_svm *svm)
3144 {
3145         u16 tss_selector;
3146         int reason;
3147         int int_type = svm->vmcb->control.exit_int_info &
3148                 SVM_EXITINTINFO_TYPE_MASK;
3149         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3150         uint32_t type =
3151                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3152         uint32_t idt_v =
3153                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3154         bool has_error_code = false;
3155         u32 error_code = 0;
3156
3157         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3158
3159         if (svm->vmcb->control.exit_info_2 &
3160             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3161                 reason = TASK_SWITCH_IRET;
3162         else if (svm->vmcb->control.exit_info_2 &
3163                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3164                 reason = TASK_SWITCH_JMP;
3165         else if (idt_v)
3166                 reason = TASK_SWITCH_GATE;
3167         else
3168                 reason = TASK_SWITCH_CALL;
3169
3170         if (reason == TASK_SWITCH_GATE) {
3171                 switch (type) {
3172                 case SVM_EXITINTINFO_TYPE_NMI:
3173                         svm->vcpu.arch.nmi_injected = false;
3174                         break;
3175                 case SVM_EXITINTINFO_TYPE_EXEPT:
3176                         if (svm->vmcb->control.exit_info_2 &
3177                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3178                                 has_error_code = true;
3179                                 error_code =
3180                                         (u32)svm->vmcb->control.exit_info_2;
3181                         }
3182                         kvm_clear_exception_queue(&svm->vcpu);
3183                         break;
3184                 case SVM_EXITINTINFO_TYPE_INTR:
3185                         kvm_clear_interrupt_queue(&svm->vcpu);
3186                         break;
3187                 default:
3188                         break;
3189                 }
3190         }
3191
3192         if (reason != TASK_SWITCH_GATE ||
3193             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3194             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3195              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3196                 skip_emulated_instruction(&svm->vcpu);
3197
3198         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3199                 int_vec = -1;
3200
3201         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3202                                 has_error_code, error_code) == EMULATE_FAIL) {
3203                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3204                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3205                 svm->vcpu.run->internal.ndata = 0;
3206                 return 0;
3207         }
3208         return 1;
3209 }
3210
3211 static int cpuid_interception(struct vcpu_svm *svm)
3212 {
3213         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3214         return kvm_emulate_cpuid(&svm->vcpu);
3215 }
3216
3217 static int iret_interception(struct vcpu_svm *svm)
3218 {
3219         ++svm->vcpu.stat.nmi_window_exits;
3220         clr_intercept(svm, INTERCEPT_IRET);
3221         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3222         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3223         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3224         return 1;
3225 }
3226
3227 static int invlpg_interception(struct vcpu_svm *svm)
3228 {
3229         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3230                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3231
3232         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3233         skip_emulated_instruction(&svm->vcpu);
3234         return 1;
3235 }
3236
3237 static int emulate_on_interception(struct vcpu_svm *svm)
3238 {
3239         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3240 }
3241
3242 static int rdpmc_interception(struct vcpu_svm *svm)
3243 {
3244         int err;
3245
3246         if (!static_cpu_has(X86_FEATURE_NRIPS))
3247                 return emulate_on_interception(svm);
3248
3249         err = kvm_rdpmc(&svm->vcpu);
3250         return kvm_complete_insn_gp(&svm->vcpu, err);
3251 }
3252
3253 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3254                                             unsigned long val)
3255 {
3256         unsigned long cr0 = svm->vcpu.arch.cr0;
3257         bool ret = false;
3258         u64 intercept;
3259
3260         intercept = svm->nested.intercept;
3261
3262         if (!is_guest_mode(&svm->vcpu) ||
3263             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3264                 return false;
3265
3266         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3267         val &= ~SVM_CR0_SELECTIVE_MASK;
3268
3269         if (cr0 ^ val) {
3270                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3271                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3272         }
3273
3274         return ret;
3275 }
3276
3277 #define CR_VALID (1ULL << 63)
3278
3279 static int cr_interception(struct vcpu_svm *svm)
3280 {
3281         int reg, cr;
3282         unsigned long val;
3283         int err;
3284
3285         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3286                 return emulate_on_interception(svm);
3287
3288         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3289                 return emulate_on_interception(svm);
3290
3291         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3292         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3293                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3294         else
3295                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3296
3297         err = 0;
3298         if (cr >= 16) { /* mov to cr */
3299                 cr -= 16;
3300                 val = kvm_register_read(&svm->vcpu, reg);
3301                 switch (cr) {
3302                 case 0:
3303                         if (!check_selective_cr0_intercepted(svm, val))
3304                                 err = kvm_set_cr0(&svm->vcpu, val);
3305                         else
3306                                 return 1;
3307
3308                         break;
3309                 case 3:
3310                         err = kvm_set_cr3(&svm->vcpu, val);
3311                         break;
3312                 case 4:
3313                         err = kvm_set_cr4(&svm->vcpu, val);
3314                         break;
3315                 case 8:
3316                         err = kvm_set_cr8(&svm->vcpu, val);
3317                         break;
3318                 default:
3319                         WARN(1, "unhandled write to CR%d", cr);
3320                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3321                         return 1;
3322                 }
3323         } else { /* mov from cr */
3324                 switch (cr) {
3325                 case 0:
3326                         val = kvm_read_cr0(&svm->vcpu);
3327                         break;
3328                 case 2:
3329                         val = svm->vcpu.arch.cr2;
3330                         break;
3331                 case 3:
3332                         val = kvm_read_cr3(&svm->vcpu);
3333                         break;
3334                 case 4:
3335                         val = kvm_read_cr4(&svm->vcpu);
3336                         break;
3337                 case 8:
3338                         val = kvm_get_cr8(&svm->vcpu);
3339                         break;
3340                 default:
3341                         WARN(1, "unhandled read from CR%d", cr);
3342                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3343                         return 1;
3344                 }
3345                 kvm_register_write(&svm->vcpu, reg, val);
3346         }
3347         return kvm_complete_insn_gp(&svm->vcpu, err);
3348 }
3349
3350 static int dr_interception(struct vcpu_svm *svm)
3351 {
3352         int reg, dr;
3353         unsigned long val;
3354
3355         if (svm->vcpu.guest_debug == 0) {
3356                 /*
3357                  * No more DR vmexits; force a reload of the debug registers
3358                  * and reenter on this instruction.  The next vmexit will
3359                  * retrieve the full state of the debug registers.
3360                  */
3361                 clr_dr_intercepts(svm);
3362                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3363                 return 1;
3364         }
3365
3366         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3367                 return emulate_on_interception(svm);
3368
3369         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3370         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3371
3372         if (dr >= 16) { /* mov to DRn */
3373                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3374                         return 1;
3375                 val = kvm_register_read(&svm->vcpu, reg);
3376                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3377         } else {
3378                 if (!kvm_require_dr(&svm->vcpu, dr))
3379                         return 1;
3380                 kvm_get_dr(&svm->vcpu, dr, &val);
3381                 kvm_register_write(&svm->vcpu, reg, val);
3382         }
3383
3384         skip_emulated_instruction(&svm->vcpu);
3385
3386         return 1;
3387 }
3388
3389 static int cr8_write_interception(struct vcpu_svm *svm)
3390 {
3391         struct kvm_run *kvm_run = svm->vcpu.run;
3392         int r;
3393
3394         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3395         /* instruction emulation calls kvm_set_cr8() */
3396         r = cr_interception(svm);
3397         if (lapic_in_kernel(&svm->vcpu))
3398                 return r;
3399         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3400                 return r;
3401         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3402         return 0;
3403 }
3404
3405 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3406 {
3407         struct vcpu_svm *svm = to_svm(vcpu);
3408
3409         switch (msr_info->index) {
3410         case MSR_IA32_TSC: {
3411                 msr_info->data = svm->vmcb->control.tsc_offset +
3412                         kvm_scale_tsc(vcpu, rdtsc());
3413
3414                 break;
3415         }
3416         case MSR_STAR:
3417                 msr_info->data = svm->vmcb->save.star;
3418                 break;
3419 #ifdef CONFIG_X86_64
3420         case MSR_LSTAR:
3421                 msr_info->data = svm->vmcb->save.lstar;
3422                 break;
3423         case MSR_CSTAR:
3424                 msr_info->data = svm->vmcb->save.cstar;
3425                 break;
3426         case MSR_KERNEL_GS_BASE:
3427                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3428                 break;
3429         case MSR_SYSCALL_MASK:
3430                 msr_info->data = svm->vmcb->save.sfmask;
3431                 break;
3432 #endif
3433         case MSR_IA32_SYSENTER_CS:
3434                 msr_info->data = svm->vmcb->save.sysenter_cs;
3435                 break;
3436         case MSR_IA32_SYSENTER_EIP:
3437                 msr_info->data = svm->sysenter_eip;
3438                 break;
3439         case MSR_IA32_SYSENTER_ESP:
3440                 msr_info->data = svm->sysenter_esp;
3441                 break;
3442         case MSR_TSC_AUX:
3443                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3444                         return 1;
3445                 msr_info->data = svm->tsc_aux;
3446                 break;
3447         /*
3448          * Nobody will change the following 5 values in the VMCB so we can
3449          * safely return them on rdmsr. They will always be 0 until LBRV is
3450          * implemented.
3451          */
3452         case MSR_IA32_DEBUGCTLMSR:
3453                 msr_info->data = svm->vmcb->save.dbgctl;
3454                 break;
3455         case MSR_IA32_LASTBRANCHFROMIP:
3456                 msr_info->data = svm->vmcb->save.br_from;
3457                 break;
3458         case MSR_IA32_LASTBRANCHTOIP:
3459                 msr_info->data = svm->vmcb->save.br_to;
3460                 break;
3461         case MSR_IA32_LASTINTFROMIP:
3462                 msr_info->data = svm->vmcb->save.last_excp_from;
3463                 break;
3464         case MSR_IA32_LASTINTTOIP:
3465                 msr_info->data = svm->vmcb->save.last_excp_to;
3466                 break;
3467         case MSR_VM_HSAVE_PA:
3468                 msr_info->data = svm->nested.hsave_msr;
3469                 break;
3470         case MSR_VM_CR:
3471                 msr_info->data = svm->nested.vm_cr_msr;
3472                 break;
3473         case MSR_IA32_UCODE_REV:
3474                 msr_info->data = 0x01000065;
3475                 break;
3476         case MSR_F15H_IC_CFG: {
3477
3478                 int family, model;
3479
3480                 family = guest_cpuid_family(vcpu);
3481                 model  = guest_cpuid_model(vcpu);
3482
3483                 if (family < 0 || model < 0)
3484                         return kvm_get_msr_common(vcpu, msr_info);
3485
3486                 msr_info->data = 0;
3487
3488                 if (family == 0x15 &&
3489                     (model >= 0x2 && model < 0x20))
3490                         msr_info->data = 0x1E;
3491                 }
3492                 break;
3493         default:
3494                 return kvm_get_msr_common(vcpu, msr_info);
3495         }
3496         return 0;
3497 }
3498
3499 static int rdmsr_interception(struct vcpu_svm *svm)
3500 {
3501         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3502         struct msr_data msr_info;
3503
3504         msr_info.index = ecx;
3505         msr_info.host_initiated = false;
3506         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3507                 trace_kvm_msr_read_ex(ecx);
3508                 kvm_inject_gp(&svm->vcpu, 0);
3509         } else {
3510                 trace_kvm_msr_read(ecx, msr_info.data);
3511
3512                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3513                                    msr_info.data & 0xffffffff);
3514                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3515                                    msr_info.data >> 32);
3516                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3517                 skip_emulated_instruction(&svm->vcpu);
3518         }
3519         return 1;
3520 }
3521
3522 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3523 {
3524         struct vcpu_svm *svm = to_svm(vcpu);
3525         int svm_dis, chg_mask;
3526
3527         if (data & ~SVM_VM_CR_VALID_MASK)
3528                 return 1;
3529
3530         chg_mask = SVM_VM_CR_VALID_MASK;
3531
3532         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3533                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3534
3535         svm->nested.vm_cr_msr &= ~chg_mask;
3536         svm->nested.vm_cr_msr |= (data & chg_mask);
3537
3538         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3539
3540         /* check for svm_disable while efer.svme is set */
3541         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3542                 return 1;
3543
3544         return 0;
3545 }
3546
3547 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3548 {
3549         struct vcpu_svm *svm = to_svm(vcpu);
3550
3551         u32 ecx = msr->index;
3552         u64 data = msr->data;
3553         switch (ecx) {
3554         case MSR_IA32_TSC:
3555                 kvm_write_tsc(vcpu, msr);
3556                 break;
3557         case MSR_STAR:
3558                 svm->vmcb->save.star = data;
3559                 break;
3560 #ifdef CONFIG_X86_64
3561         case MSR_LSTAR:
3562                 svm->vmcb->save.lstar = data;
3563                 break;
3564         case MSR_CSTAR:
3565                 svm->vmcb->save.cstar = data;
3566                 break;
3567         case MSR_KERNEL_GS_BASE:
3568                 svm->vmcb->save.kernel_gs_base = data;
3569                 break;
3570         case MSR_SYSCALL_MASK:
3571                 svm->vmcb->save.sfmask = data;
3572                 break;
3573 #endif
3574         case MSR_IA32_SYSENTER_CS:
3575                 svm->vmcb->save.sysenter_cs = data;
3576                 break;
3577         case MSR_IA32_SYSENTER_EIP:
3578                 svm->sysenter_eip = data;
3579                 svm->vmcb->save.sysenter_eip = data;
3580                 break;
3581         case MSR_IA32_SYSENTER_ESP:
3582                 svm->sysenter_esp = data;
3583                 svm->vmcb->save.sysenter_esp = data;
3584                 break;
3585         case MSR_TSC_AUX:
3586                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3587                         return 1;
3588
3589                 /*
3590                  * This is rare, so we update the MSR here instead of using
3591                  * direct_access_msrs.  Doing that would require a rdmsr in
3592                  * svm_vcpu_put.
3593                  */
3594                 svm->tsc_aux = data;
3595                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3596                 break;
3597         case MSR_IA32_DEBUGCTLMSR:
3598                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3599                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3600                                     __func__, data);
3601                         break;
3602                 }
3603                 if (data & DEBUGCTL_RESERVED_BITS)
3604                         return 1;
3605
3606                 svm->vmcb->save.dbgctl = data;
3607                 mark_dirty(svm->vmcb, VMCB_LBR);
3608                 if (data & (1ULL<<0))
3609                         svm_enable_lbrv(svm);
3610                 else
3611                         svm_disable_lbrv(svm);
3612                 break;
3613         case MSR_VM_HSAVE_PA:
3614                 svm->nested.hsave_msr = data;
3615                 break;
3616         case MSR_VM_CR:
3617                 return svm_set_vm_cr(vcpu, data);
3618         case MSR_VM_IGNNE:
3619                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3620                 break;
3621         case MSR_IA32_APICBASE:
3622                 if (kvm_vcpu_apicv_active(vcpu))
3623                         avic_update_vapic_bar(to_svm(vcpu), data);
3624                 /* Follow through */
3625         default:
3626                 return kvm_set_msr_common(vcpu, msr);
3627         }
3628         return 0;
3629 }
3630
3631 static int wrmsr_interception(struct vcpu_svm *svm)
3632 {
3633         struct msr_data msr;
3634         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3635         u64 data = kvm_read_edx_eax(&svm->vcpu);
3636
3637         msr.data = data;
3638         msr.index = ecx;
3639         msr.host_initiated = false;
3640
3641         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3642         if (kvm_set_msr(&svm->vcpu, &msr)) {
3643                 trace_kvm_msr_write_ex(ecx, data);
3644                 kvm_inject_gp(&svm->vcpu, 0);
3645         } else {
3646                 trace_kvm_msr_write(ecx, data);
3647                 skip_emulated_instruction(&svm->vcpu);
3648         }
3649         return 1;
3650 }
3651
3652 static int msr_interception(struct vcpu_svm *svm)
3653 {
3654         if (svm->vmcb->control.exit_info_1)
3655                 return wrmsr_interception(svm);
3656         else
3657                 return rdmsr_interception(svm);
3658 }
3659
3660 static int interrupt_window_interception(struct vcpu_svm *svm)
3661 {
3662         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3663         svm_clear_vintr(svm);
3664         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3665         mark_dirty(svm->vmcb, VMCB_INTR);
3666         ++svm->vcpu.stat.irq_window_exits;
3667         return 1;
3668 }
3669
3670 static int pause_interception(struct vcpu_svm *svm)
3671 {
3672         kvm_vcpu_on_spin(&(svm->vcpu));
3673         return 1;
3674 }
3675
3676 static int nop_interception(struct vcpu_svm *svm)
3677 {
3678         skip_emulated_instruction(&(svm->vcpu));
3679         return 1;
3680 }
3681
3682 static int monitor_interception(struct vcpu_svm *svm)
3683 {
3684         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3685         return nop_interception(svm);
3686 }
3687
3688 static int mwait_interception(struct vcpu_svm *svm)
3689 {
3690         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3691         return nop_interception(svm);
3692 }
3693
3694 enum avic_ipi_failure_cause {
3695         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3696         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3697         AVIC_IPI_FAILURE_INVALID_TARGET,
3698         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3699 };
3700
3701 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3702 {
3703         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3704         u32 icrl = svm->vmcb->control.exit_info_1;
3705         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3706         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3707         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3708
3709         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3710
3711         switch (id) {
3712         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3713                 /*
3714                  * AVIC hardware handles the generation of
3715                  * IPIs when the specified Message Type is Fixed
3716                  * (also known as fixed delivery mode) and
3717                  * the Trigger Mode is edge-triggered. The hardware
3718                  * also supports self and broadcast delivery modes
3719                  * specified via the Destination Shorthand(DSH)
3720                  * field of the ICRL. Logical and physical APIC ID
3721                  * formats are supported. All other IPI types cause
3722                  * a #VMEXIT, which needs to emulated.
3723                  */
3724                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3725                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3726                 break;
3727         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3728                 int i;
3729                 struct kvm_vcpu *vcpu;
3730                 struct kvm *kvm = svm->vcpu.kvm;
3731                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3732
3733                 /*
3734                  * At this point, we expect that the AVIC HW has already
3735                  * set the appropriate IRR bits on the valid target
3736                  * vcpus. So, we just need to kick the appropriate vcpu.
3737                  */
3738                 kvm_for_each_vcpu(i, vcpu, kvm) {
3739                         bool m = kvm_apic_match_dest(vcpu, apic,
3740                                                      icrl & KVM_APIC_SHORT_MASK,
3741                                                      GET_APIC_DEST_FIELD(icrh),
3742                                                      icrl & KVM_APIC_DEST_MASK);
3743
3744                         if (m && !avic_vcpu_is_running(vcpu))
3745                                 kvm_vcpu_wake_up(vcpu);
3746                 }
3747                 break;
3748         }
3749         case AVIC_IPI_FAILURE_INVALID_TARGET:
3750                 break;
3751         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3752                 WARN_ONCE(1, "Invalid backing page\n");
3753                 break;
3754         default:
3755                 pr_err("Unknown IPI interception\n");
3756         }
3757
3758         return 1;
3759 }
3760
3761 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3762 {
3763         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3764         int index;
3765         u32 *logical_apic_id_table;
3766         int dlid = GET_APIC_LOGICAL_ID(ldr);
3767
3768         if (!dlid)
3769                 return NULL;
3770
3771         if (flat) { /* flat */
3772                 index = ffs(dlid) - 1;
3773                 if (index > 7)
3774                         return NULL;
3775         } else { /* cluster */
3776                 int cluster = (dlid & 0xf0) >> 4;
3777                 int apic = ffs(dlid & 0x0f) - 1;
3778
3779                 if ((apic < 0) || (apic > 7) ||
3780                     (cluster >= 0xf))
3781                         return NULL;
3782                 index = (cluster << 2) + apic;
3783         }
3784
3785         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3786
3787         return &logical_apic_id_table[index];
3788 }
3789
3790 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3791                           bool valid)
3792 {
3793         bool flat;
3794         u32 *entry, new_entry;
3795
3796         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3797         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3798         if (!entry)
3799                 return -EINVAL;
3800
3801         new_entry = READ_ONCE(*entry);
3802         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3803         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3804         if (valid)
3805                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3806         else
3807                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3808         WRITE_ONCE(*entry, new_entry);
3809
3810         return 0;
3811 }
3812
3813 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3814 {
3815         int ret;
3816         struct vcpu_svm *svm = to_svm(vcpu);
3817         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3818
3819         if (!ldr)
3820                 return 1;
3821
3822         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3823         if (ret && svm->ldr_reg) {
3824                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3825                 svm->ldr_reg = 0;
3826         } else {
3827                 svm->ldr_reg = ldr;
3828         }
3829         return ret;
3830 }
3831
3832 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3833 {
3834         u64 *old, *new;
3835         struct vcpu_svm *svm = to_svm(vcpu);
3836         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3837         u32 id = (apic_id_reg >> 24) & 0xff;
3838
3839         if (vcpu->vcpu_id == id)
3840                 return 0;
3841
3842         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3843         new = avic_get_physical_id_entry(vcpu, id);
3844         if (!new || !old)
3845                 return 1;
3846
3847         /* We need to move physical_id_entry to new offset */
3848         *new = *old;
3849         *old = 0ULL;
3850         to_svm(vcpu)->avic_physical_id_cache = new;
3851
3852         /*
3853          * Also update the guest physical APIC ID in the logical
3854          * APIC ID table entry if already setup the LDR.
3855          */
3856         if (svm->ldr_reg)
3857                 avic_handle_ldr_update(vcpu);
3858
3859         return 0;
3860 }
3861
3862 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3863 {
3864         struct vcpu_svm *svm = to_svm(vcpu);
3865         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3866         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3867         u32 mod = (dfr >> 28) & 0xf;
3868
3869         /*
3870          * We assume that all local APICs are using the same type.
3871          * If this changes, we need to flush the AVIC logical
3872          * APID id table.
3873          */
3874         if (vm_data->ldr_mode == mod)
3875                 return 0;
3876
3877         clear_page(page_address(vm_data->avic_logical_id_table_page));
3878         vm_data->ldr_mode = mod;
3879
3880         if (svm->ldr_reg)
3881                 avic_handle_ldr_update(vcpu);
3882         return 0;
3883 }
3884
3885 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3886 {
3887         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3888         u32 offset = svm->vmcb->control.exit_info_1 &
3889                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3890
3891         switch (offset) {
3892         case APIC_ID:
3893                 if (avic_handle_apic_id_update(&svm->vcpu))
3894                         return 0;
3895                 break;
3896         case APIC_LDR:
3897                 if (avic_handle_ldr_update(&svm->vcpu))
3898                         return 0;
3899                 break;
3900         case APIC_DFR:
3901                 avic_handle_dfr_update(&svm->vcpu);
3902                 break;
3903         default:
3904                 break;
3905         }
3906
3907         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3908
3909         return 1;
3910 }
3911
3912 static bool is_avic_unaccelerated_access_trap(u32 offset)
3913 {
3914         bool ret = false;
3915
3916         switch (offset) {
3917         case APIC_ID:
3918         case APIC_EOI:
3919         case APIC_RRR:
3920         case APIC_LDR:
3921         case APIC_DFR:
3922         case APIC_SPIV:
3923         case APIC_ESR:
3924         case APIC_ICR:
3925         case APIC_LVTT:
3926         case APIC_LVTTHMR:
3927         case APIC_LVTPC:
3928         case APIC_LVT0:
3929         case APIC_LVT1:
3930         case APIC_LVTERR:
3931         case APIC_TMICT:
3932         case APIC_TDCR:
3933                 ret = true;
3934                 break;
3935         default:
3936                 break;
3937         }
3938         return ret;
3939 }
3940
3941 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3942 {
3943         int ret = 0;
3944         u32 offset = svm->vmcb->control.exit_info_1 &
3945                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3946         u32 vector = svm->vmcb->control.exit_info_2 &
3947                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3948         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3949                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
3950         bool trap = is_avic_unaccelerated_access_trap(offset);
3951
3952         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3953                                             trap, write, vector);
3954         if (trap) {
3955                 /* Handling Trap */
3956                 WARN_ONCE(!write, "svm: Handling trap read.\n");
3957                 ret = avic_unaccel_trap_write(svm);
3958         } else {
3959                 /* Handling Fault */
3960                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3961         }
3962
3963         return ret;
3964 }
3965
3966 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3967         [SVM_EXIT_READ_CR0]                     = cr_interception,
3968         [SVM_EXIT_READ_CR3]                     = cr_interception,
3969         [SVM_EXIT_READ_CR4]                     = cr_interception,
3970         [SVM_EXIT_READ_CR8]                     = cr_interception,
3971         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3972         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3973         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3974         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3975         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3976         [SVM_EXIT_READ_DR0]                     = dr_interception,
3977         [SVM_EXIT_READ_DR1]                     = dr_interception,
3978         [SVM_EXIT_READ_DR2]                     = dr_interception,
3979         [SVM_EXIT_READ_DR3]                     = dr_interception,
3980         [SVM_EXIT_READ_DR4]                     = dr_interception,
3981         [SVM_EXIT_READ_DR5]                     = dr_interception,
3982         [SVM_EXIT_READ_DR6]                     = dr_interception,
3983         [SVM_EXIT_READ_DR7]                     = dr_interception,
3984         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3985         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3986         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3987         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3988         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3989         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3990         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3991         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3992         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3993         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3994         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3995         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3996         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3997         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3998         [SVM_EXIT_INTR]                         = intr_interception,
3999         [SVM_EXIT_NMI]                          = nmi_interception,
4000         [SVM_EXIT_SMI]                          = nop_on_interception,
4001         [SVM_EXIT_INIT]                         = nop_on_interception,
4002         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4003         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4004         [SVM_EXIT_CPUID]                        = cpuid_interception,
4005         [SVM_EXIT_IRET]                         = iret_interception,
4006         [SVM_EXIT_INVD]                         = emulate_on_interception,
4007         [SVM_EXIT_PAUSE]                        = pause_interception,
4008         [SVM_EXIT_HLT]                          = halt_interception,
4009         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4010         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4011         [SVM_EXIT_IOIO]                         = io_interception,
4012         [SVM_EXIT_MSR]                          = msr_interception,
4013         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4014         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4015         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4016         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4017         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4018         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4019         [SVM_EXIT_STGI]                         = stgi_interception,
4020         [SVM_EXIT_CLGI]                         = clgi_interception,
4021         [SVM_EXIT_SKINIT]                       = skinit_interception,
4022         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4023         [SVM_EXIT_MONITOR]                      = monitor_interception,
4024         [SVM_EXIT_MWAIT]                        = mwait_interception,
4025         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4026         [SVM_EXIT_NPF]                          = pf_interception,
4027         [SVM_EXIT_RSM]                          = emulate_on_interception,
4028         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4029         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4030 };
4031
4032 static void dump_vmcb(struct kvm_vcpu *vcpu)
4033 {
4034         struct vcpu_svm *svm = to_svm(vcpu);
4035         struct vmcb_control_area *control = &svm->vmcb->control;
4036         struct vmcb_save_area *save = &svm->vmcb->save;
4037
4038         pr_err("VMCB Control Area:\n");
4039         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4040         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4041         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4042         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4043         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4044         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4045         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4046         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4047         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4048         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4049         pr_err("%-20s%d\n", "asid:", control->asid);
4050         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4051         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4052         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4053         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4054         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4055         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4056         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4057         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4058         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4059         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4060         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4061         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4062         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4063         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4064         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4065         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4066         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4067         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4068         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4069         pr_err("VMCB State Save Area:\n");
4070         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4071                "es:",
4072                save->es.selector, save->es.attrib,
4073                save->es.limit, save->es.base);
4074         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4075                "cs:",
4076                save->cs.selector, save->cs.attrib,
4077                save->cs.limit, save->cs.base);
4078         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4079                "ss:",
4080                save->ss.selector, save->ss.attrib,
4081                save->ss.limit, save->ss.base);
4082         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4083                "ds:",
4084                save->ds.selector, save->ds.attrib,
4085                save->ds.limit, save->ds.base);
4086         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4087                "fs:",
4088                save->fs.selector, save->fs.attrib,
4089                save->fs.limit, save->fs.base);
4090         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4091                "gs:",
4092                save->gs.selector, save->gs.attrib,
4093                save->gs.limit, save->gs.base);
4094         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4095                "gdtr:",
4096                save->gdtr.selector, save->gdtr.attrib,
4097                save->gdtr.limit, save->gdtr.base);
4098         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4099                "ldtr:",
4100                save->ldtr.selector, save->ldtr.attrib,
4101                save->ldtr.limit, save->ldtr.base);
4102         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4103                "idtr:",
4104                save->idtr.selector, save->idtr.attrib,
4105                save->idtr.limit, save->idtr.base);
4106         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4107                "tr:",
4108                save->tr.selector, save->tr.attrib,
4109                save->tr.limit, save->tr.base);
4110         pr_err("cpl:            %d                efer:         %016llx\n",
4111                 save->cpl, save->efer);
4112         pr_err("%-15s %016llx %-13s %016llx\n",
4113                "cr0:", save->cr0, "cr2:", save->cr2);
4114         pr_err("%-15s %016llx %-13s %016llx\n",
4115                "cr3:", save->cr3, "cr4:", save->cr4);
4116         pr_err("%-15s %016llx %-13s %016llx\n",
4117                "dr6:", save->dr6, "dr7:", save->dr7);
4118         pr_err("%-15s %016llx %-13s %016llx\n",
4119                "rip:", save->rip, "rflags:", save->rflags);
4120         pr_err("%-15s %016llx %-13s %016llx\n",
4121                "rsp:", save->rsp, "rax:", save->rax);
4122         pr_err("%-15s %016llx %-13s %016llx\n",
4123                "star:", save->star, "lstar:", save->lstar);
4124         pr_err("%-15s %016llx %-13s %016llx\n",
4125                "cstar:", save->cstar, "sfmask:", save->sfmask);
4126         pr_err("%-15s %016llx %-13s %016llx\n",
4127                "kernel_gs_base:", save->kernel_gs_base,
4128                "sysenter_cs:", save->sysenter_cs);
4129         pr_err("%-15s %016llx %-13s %016llx\n",
4130                "sysenter_esp:", save->sysenter_esp,
4131                "sysenter_eip:", save->sysenter_eip);
4132         pr_err("%-15s %016llx %-13s %016llx\n",
4133                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4134         pr_err("%-15s %016llx %-13s %016llx\n",
4135                "br_from:", save->br_from, "br_to:", save->br_to);
4136         pr_err("%-15s %016llx %-13s %016llx\n",
4137                "excp_from:", save->last_excp_from,
4138                "excp_to:", save->last_excp_to);
4139 }
4140
4141 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4142 {
4143         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4144
4145         *info1 = control->exit_info_1;
4146         *info2 = control->exit_info_2;
4147 }
4148
4149 static int handle_exit(struct kvm_vcpu *vcpu)
4150 {
4151         struct vcpu_svm *svm = to_svm(vcpu);
4152         struct kvm_run *kvm_run = vcpu->run;
4153         u32 exit_code = svm->vmcb->control.exit_code;
4154
4155         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4156
4157         vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4158
4159         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4160                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4161         if (npt_enabled)
4162                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4163
4164         if (unlikely(svm->nested.exit_required)) {
4165                 nested_svm_vmexit(svm);
4166                 svm->nested.exit_required = false;
4167
4168                 return 1;
4169         }
4170
4171         if (is_guest_mode(vcpu)) {
4172                 int vmexit;
4173
4174                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4175                                         svm->vmcb->control.exit_info_1,
4176                                         svm->vmcb->control.exit_info_2,
4177                                         svm->vmcb->control.exit_int_info,
4178                                         svm->vmcb->control.exit_int_info_err,
4179                                         KVM_ISA_SVM);
4180
4181                 vmexit = nested_svm_exit_special(svm);
4182
4183                 if (vmexit == NESTED_EXIT_CONTINUE)
4184                         vmexit = nested_svm_exit_handled(svm);
4185
4186                 if (vmexit == NESTED_EXIT_DONE)
4187                         return 1;
4188         }
4189
4190         svm_complete_interrupts(svm);
4191
4192         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4193                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4194                 kvm_run->fail_entry.hardware_entry_failure_reason
4195                         = svm->vmcb->control.exit_code;
4196                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4197                 dump_vmcb(vcpu);
4198                 return 0;
4199         }
4200
4201         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4202             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4203             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4204             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4205                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4206                        "exit_code 0x%x\n",
4207                        __func__, svm->vmcb->control.exit_int_info,
4208                        exit_code);
4209
4210         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4211             || !svm_exit_handlers[exit_code]) {
4212                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4213                 kvm_queue_exception(vcpu, UD_VECTOR);
4214                 return 1;
4215         }
4216
4217         return svm_exit_handlers[exit_code](svm);
4218 }
4219
4220 static void reload_tss(struct kvm_vcpu *vcpu)
4221 {
4222         int cpu = raw_smp_processor_id();
4223
4224         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4225         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4226         load_TR_desc();
4227 }
4228
4229 static void pre_svm_run(struct vcpu_svm *svm)
4230 {
4231         int cpu = raw_smp_processor_id();
4232
4233         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4234
4235         /* FIXME: handle wraparound of asid_generation */
4236         if (svm->asid_generation != sd->asid_generation)
4237                 new_asid(svm, sd);
4238 }
4239
4240 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4241 {
4242         struct vcpu_svm *svm = to_svm(vcpu);
4243
4244         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4245         vcpu->arch.hflags |= HF_NMI_MASK;
4246         set_intercept(svm, INTERCEPT_IRET);
4247         ++vcpu->stat.nmi_injections;
4248 }
4249
4250 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4251 {
4252         struct vmcb_control_area *control;
4253
4254         /* The following fields are ignored when AVIC is enabled */
4255         control = &svm->vmcb->control;
4256         control->int_vector = irq;
4257         control->int_ctl &= ~V_INTR_PRIO_MASK;
4258         control->int_ctl |= V_IRQ_MASK |
4259                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4260         mark_dirty(svm->vmcb, VMCB_INTR);
4261 }
4262
4263 static void svm_set_irq(struct kvm_vcpu *vcpu)
4264 {
4265         struct vcpu_svm *svm = to_svm(vcpu);
4266
4267         BUG_ON(!(gif_set(svm)));
4268
4269         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4270         ++vcpu->stat.irq_injections;
4271
4272         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4273                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4274 }
4275
4276 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4277 {
4278         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4279 }
4280
4281 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4282 {
4283         struct vcpu_svm *svm = to_svm(vcpu);
4284
4285         if (svm_nested_virtualize_tpr(vcpu) ||
4286             kvm_vcpu_apicv_active(vcpu))
4287                 return;
4288
4289         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4290
4291         if (irr == -1)
4292                 return;
4293
4294         if (tpr >= irr)
4295                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4296 }
4297
4298 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4299 {
4300         return;
4301 }
4302
4303 static bool svm_get_enable_apicv(void)
4304 {
4305         return avic;
4306 }
4307
4308 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4309 {
4310 }
4311
4312 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4313 {
4314 }
4315
4316 /* Note: Currently only used by Hyper-V. */
4317 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4318 {
4319         struct vcpu_svm *svm = to_svm(vcpu);
4320         struct vmcb *vmcb = svm->vmcb;
4321
4322         if (!avic)
4323                 return;
4324
4325         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4326         mark_dirty(vmcb, VMCB_INTR);
4327 }
4328
4329 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4330 {
4331         return;
4332 }
4333
4334 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4335 {
4336         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4337         smp_mb__after_atomic();
4338
4339         if (avic_vcpu_is_running(vcpu))
4340                 wrmsrl(SVM_AVIC_DOORBELL,
4341                        kvm_cpu_get_apicid(vcpu->cpu));
4342         else
4343                 kvm_vcpu_wake_up(vcpu);
4344 }
4345
4346 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4347 {
4348         unsigned long flags;
4349         struct amd_svm_iommu_ir *cur;
4350
4351         spin_lock_irqsave(&svm->ir_list_lock, flags);
4352         list_for_each_entry(cur, &svm->ir_list, node) {
4353                 if (cur->data != pi->ir_data)
4354                         continue;
4355                 list_del(&cur->node);
4356                 kfree(cur);
4357                 break;
4358         }
4359         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4360 }
4361
4362 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4363 {
4364         int ret = 0;
4365         unsigned long flags;
4366         struct amd_svm_iommu_ir *ir;
4367
4368         /**
4369          * In some cases, the existing irte is updaed and re-set,
4370          * so we need to check here if it's already been * added
4371          * to the ir_list.
4372          */
4373         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4374                 struct kvm *kvm = svm->vcpu.kvm;
4375                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4376                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4377                 struct vcpu_svm *prev_svm;
4378
4379                 if (!prev_vcpu) {
4380                         ret = -EINVAL;
4381                         goto out;
4382                 }
4383
4384                 prev_svm = to_svm(prev_vcpu);
4385                 svm_ir_list_del(prev_svm, pi);
4386         }
4387
4388         /**
4389          * Allocating new amd_iommu_pi_data, which will get
4390          * add to the per-vcpu ir_list.
4391          */
4392         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4393         if (!ir) {
4394                 ret = -ENOMEM;
4395                 goto out;
4396         }
4397         ir->data = pi->ir_data;
4398
4399         spin_lock_irqsave(&svm->ir_list_lock, flags);
4400         list_add(&ir->node, &svm->ir_list);
4401         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4402 out:
4403         return ret;
4404 }
4405
4406 /**
4407  * Note:
4408  * The HW cannot support posting multicast/broadcast
4409  * interrupts to a vCPU. So, we still use legacy interrupt
4410  * remapping for these kind of interrupts.
4411  *
4412  * For lowest-priority interrupts, we only support
4413  * those with single CPU as the destination, e.g. user
4414  * configures the interrupts via /proc/irq or uses
4415  * irqbalance to make the interrupts single-CPU.
4416  */
4417 static int
4418 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4419                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4420 {
4421         struct kvm_lapic_irq irq;
4422         struct kvm_vcpu *vcpu = NULL;
4423
4424         kvm_set_msi_irq(kvm, e, &irq);
4425
4426         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4427                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4428                          __func__, irq.vector);
4429                 return -1;
4430         }
4431
4432         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4433                  irq.vector);
4434         *svm = to_svm(vcpu);
4435         vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4436         vcpu_info->vector = irq.vector;
4437
4438         return 0;
4439 }
4440
4441 /*
4442  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4443  *
4444  * @kvm: kvm
4445  * @host_irq: host irq of the interrupt
4446  * @guest_irq: gsi of the interrupt
4447  * @set: set or unset PI
4448  * returns 0 on success, < 0 on failure
4449  */
4450 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4451                               uint32_t guest_irq, bool set)
4452 {
4453         struct kvm_kernel_irq_routing_entry *e;
4454         struct kvm_irq_routing_table *irq_rt;
4455         int idx, ret = -EINVAL;
4456
4457         if (!kvm_arch_has_assigned_device(kvm) ||
4458             !irq_remapping_cap(IRQ_POSTING_CAP))
4459                 return 0;
4460
4461         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4462                  __func__, host_irq, guest_irq, set);
4463
4464         idx = srcu_read_lock(&kvm->irq_srcu);
4465         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4466         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4467
4468         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4469                 struct vcpu_data vcpu_info;
4470                 struct vcpu_svm *svm = NULL;
4471
4472                 if (e->type != KVM_IRQ_ROUTING_MSI)
4473                         continue;
4474
4475                 /**
4476                  * Here, we setup with legacy mode in the following cases:
4477                  * 1. When cannot target interrupt to a specific vcpu.
4478                  * 2. Unsetting posted interrupt.
4479                  * 3. APIC virtialization is disabled for the vcpu.
4480                  */
4481                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4482                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4483                         struct amd_iommu_pi_data pi;
4484
4485                         /* Try to enable guest_mode in IRTE */
4486                         pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4487                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4488                                                      svm->vcpu.vcpu_id);
4489                         pi.is_guest_mode = true;
4490                         pi.vcpu_data = &vcpu_info;
4491                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4492
4493                         /**
4494                          * Here, we successfully setting up vcpu affinity in
4495                          * IOMMU guest mode. Now, we need to store the posted
4496                          * interrupt information in a per-vcpu ir_list so that
4497                          * we can reference to them directly when we update vcpu
4498                          * scheduling information in IOMMU irte.
4499                          */
4500                         if (!ret && pi.is_guest_mode)
4501                                 svm_ir_list_add(svm, &pi);
4502                 } else {
4503                         /* Use legacy mode in IRTE */
4504                         struct amd_iommu_pi_data pi;
4505
4506                         /**
4507                          * Here, pi is used to:
4508                          * - Tell IOMMU to use legacy mode for this interrupt.
4509                          * - Retrieve ga_tag of prior interrupt remapping data.
4510                          */
4511                         pi.is_guest_mode = false;
4512                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4513
4514                         /**
4515                          * Check if the posted interrupt was previously
4516                          * setup with the guest_mode by checking if the ga_tag
4517                          * was cached. If so, we need to clean up the per-vcpu
4518                          * ir_list.
4519                          */
4520                         if (!ret && pi.prev_ga_tag) {
4521                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4522                                 struct kvm_vcpu *vcpu;
4523
4524                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4525                                 if (vcpu)
4526                                         svm_ir_list_del(to_svm(vcpu), &pi);
4527                         }
4528                 }
4529
4530                 if (!ret && svm) {
4531                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4532                                                  host_irq, e->gsi,
4533                                                  vcpu_info.vector,
4534                                                  vcpu_info.pi_desc_addr, set);
4535                 }
4536
4537                 if (ret < 0) {
4538                         pr_err("%s: failed to update PI IRTE\n", __func__);
4539                         goto out;
4540                 }
4541         }
4542
4543         ret = 0;
4544 out:
4545         srcu_read_unlock(&kvm->irq_srcu, idx);
4546         return ret;
4547 }
4548
4549 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4550 {
4551         struct vcpu_svm *svm = to_svm(vcpu);
4552         struct vmcb *vmcb = svm->vmcb;
4553         int ret;
4554         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4555               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4556         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4557
4558         return ret;
4559 }
4560
4561 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4562 {
4563         struct vcpu_svm *svm = to_svm(vcpu);
4564
4565         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4566 }
4567
4568 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4569 {
4570         struct vcpu_svm *svm = to_svm(vcpu);
4571
4572         if (masked) {
4573                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4574                 set_intercept(svm, INTERCEPT_IRET);
4575         } else {
4576                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4577                 clr_intercept(svm, INTERCEPT_IRET);
4578         }
4579 }
4580
4581 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4582 {
4583         struct vcpu_svm *svm = to_svm(vcpu);
4584         struct vmcb *vmcb = svm->vmcb;
4585         int ret;
4586
4587         if (!gif_set(svm) ||
4588              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4589                 return 0;
4590
4591         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4592
4593         if (is_guest_mode(vcpu))
4594                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4595
4596         return ret;
4597 }
4598
4599 static void enable_irq_window(struct kvm_vcpu *vcpu)
4600 {
4601         struct vcpu_svm *svm = to_svm(vcpu);
4602
4603         if (kvm_vcpu_apicv_active(vcpu))
4604                 return;
4605
4606         /*
4607          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4608          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4609          * get that intercept, this function will be called again though and
4610          * we'll get the vintr intercept.
4611          */
4612         if (gif_set(svm) && nested_svm_intr(svm)) {
4613                 svm_set_vintr(svm);
4614                 svm_inject_irq(svm, 0x0);
4615         }
4616 }
4617
4618 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4619 {
4620         struct vcpu_svm *svm = to_svm(vcpu);
4621
4622         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4623             == HF_NMI_MASK)
4624                 return; /* IRET will cause a vm exit */
4625
4626         /*
4627          * Something prevents NMI from been injected. Single step over possible
4628          * problem (IRET or exception injection or interrupt shadow)
4629          */
4630         svm->nmi_singlestep = true;
4631         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4632 }
4633
4634 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4635 {
4636         return 0;
4637 }
4638
4639 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4640 {
4641         struct vcpu_svm *svm = to_svm(vcpu);
4642
4643         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4644                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4645         else
4646                 svm->asid_generation--;
4647 }
4648
4649 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4650 {
4651 }
4652
4653 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4654 {
4655         struct vcpu_svm *svm = to_svm(vcpu);
4656
4657         if (svm_nested_virtualize_tpr(vcpu))
4658                 return;
4659
4660         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4661                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4662                 kvm_set_cr8(vcpu, cr8);
4663         }
4664 }
4665
4666 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4667 {
4668         struct vcpu_svm *svm = to_svm(vcpu);
4669         u64 cr8;
4670
4671         if (svm_nested_virtualize_tpr(vcpu) ||
4672             kvm_vcpu_apicv_active(vcpu))
4673                 return;
4674
4675         cr8 = kvm_get_cr8(vcpu);
4676         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4677         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4678 }
4679
4680 static void svm_complete_interrupts(struct vcpu_svm *svm)
4681 {
4682         u8 vector;
4683         int type;
4684         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4685         unsigned int3_injected = svm->int3_injected;
4686
4687         svm->int3_injected = 0;
4688
4689         /*
4690          * If we've made progress since setting HF_IRET_MASK, we've
4691          * executed an IRET and can allow NMI injection.
4692          */
4693         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4694             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4695                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4696                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4697         }
4698
4699         svm->vcpu.arch.nmi_injected = false;
4700         kvm_clear_exception_queue(&svm->vcpu);
4701         kvm_clear_interrupt_queue(&svm->vcpu);
4702
4703         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4704                 return;
4705
4706         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4707
4708         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4709         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4710
4711         switch (type) {
4712         case SVM_EXITINTINFO_TYPE_NMI:
4713                 svm->vcpu.arch.nmi_injected = true;
4714                 break;
4715         case SVM_EXITINTINFO_TYPE_EXEPT:
4716                 /*
4717                  * In case of software exceptions, do not reinject the vector,
4718                  * but re-execute the instruction instead. Rewind RIP first
4719                  * if we emulated INT3 before.
4720                  */
4721                 if (kvm_exception_is_soft(vector)) {
4722                         if (vector == BP_VECTOR && int3_injected &&
4723                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4724                                 kvm_rip_write(&svm->vcpu,
4725                                               kvm_rip_read(&svm->vcpu) -
4726                                               int3_injected);
4727                         break;
4728                 }
4729                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4730                         u32 err = svm->vmcb->control.exit_int_info_err;
4731                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4732
4733                 } else
4734                         kvm_requeue_exception(&svm->vcpu, vector);
4735                 break;
4736         case SVM_EXITINTINFO_TYPE_INTR:
4737                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4738                 break;
4739         default:
4740                 break;
4741         }
4742 }
4743
4744 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4745 {
4746         struct vcpu_svm *svm = to_svm(vcpu);
4747         struct vmcb_control_area *control = &svm->vmcb->control;
4748
4749         control->exit_int_info = control->event_inj;
4750         control->exit_int_info_err = control->event_inj_err;
4751         control->event_inj = 0;
4752         svm_complete_interrupts(svm);
4753 }
4754
4755 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4756 {
4757         struct vcpu_svm *svm = to_svm(vcpu);
4758
4759         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4760         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4761         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4762
4763         /*
4764          * A vmexit emulation is required before the vcpu can be executed
4765          * again.
4766          */
4767         if (unlikely(svm->nested.exit_required))
4768                 return;
4769
4770         pre_svm_run(svm);
4771
4772         sync_lapic_to_cr8(vcpu);
4773
4774         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4775
4776         clgi();
4777
4778         local_irq_enable();
4779
4780         asm volatile (
4781                 "push %%" _ASM_BP "; \n\t"
4782                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4783                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4784                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4785                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4786                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4787                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4788 #ifdef CONFIG_X86_64
4789                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4790                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4791                 "mov %c[r10](%[svm]), %%r10 \n\t"
4792                 "mov %c[r11](%[svm]), %%r11 \n\t"
4793                 "mov %c[r12](%[svm]), %%r12 \n\t"
4794                 "mov %c[r13](%[svm]), %%r13 \n\t"
4795                 "mov %c[r14](%[svm]), %%r14 \n\t"
4796                 "mov %c[r15](%[svm]), %%r15 \n\t"
4797 #endif
4798
4799                 /* Enter guest mode */
4800                 "push %%" _ASM_AX " \n\t"
4801                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4802                 __ex(SVM_VMLOAD) "\n\t"
4803                 __ex(SVM_VMRUN) "\n\t"
4804                 __ex(SVM_VMSAVE) "\n\t"
4805                 "pop %%" _ASM_AX " \n\t"
4806
4807                 /* Save guest registers, load host registers */
4808                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4809                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4810                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4811                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4812                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4813                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4814 #ifdef CONFIG_X86_64
4815                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4816                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4817                 "mov %%r10, %c[r10](%[svm]) \n\t"
4818                 "mov %%r11, %c[r11](%[svm]) \n\t"
4819                 "mov %%r12, %c[r12](%[svm]) \n\t"
4820                 "mov %%r13, %c[r13](%[svm]) \n\t"
4821                 "mov %%r14, %c[r14](%[svm]) \n\t"
4822                 "mov %%r15, %c[r15](%[svm]) \n\t"
4823 #endif
4824                 "pop %%" _ASM_BP
4825                 :
4826                 : [svm]"a"(svm),
4827                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4828                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4829                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4830                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4831                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4832                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4833                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4834 #ifdef CONFIG_X86_64
4835                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4836                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4837                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4838                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4839                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4840                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4841                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4842                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4843 #endif
4844                 : "cc", "memory"
4845 #ifdef CONFIG_X86_64
4846                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4847                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4848 #else
4849                 , "ebx", "ecx", "edx", "esi", "edi"
4850 #endif
4851                 );
4852
4853 #ifdef CONFIG_X86_64
4854         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4855 #else
4856         loadsegment(fs, svm->host.fs);
4857 #ifndef CONFIG_X86_32_LAZY_GS
4858         loadsegment(gs, svm->host.gs);
4859 #endif
4860 #endif
4861
4862         reload_tss(vcpu);
4863
4864         local_irq_disable();
4865
4866         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4867         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4868         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4869         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4870
4871         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4872                 kvm_before_handle_nmi(&svm->vcpu);
4873
4874         stgi();
4875
4876         /* Any pending NMI will happen here */
4877
4878         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4879                 kvm_after_handle_nmi(&svm->vcpu);
4880
4881         sync_cr8_to_lapic(vcpu);
4882
4883         svm->next_rip = 0;
4884
4885         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4886
4887         /* if exit due to PF check for async PF */
4888         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4889                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4890
4891         if (npt_enabled) {
4892                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4893                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4894         }
4895
4896         /*
4897          * We need to handle MC intercepts here before the vcpu has a chance to
4898          * change the physical cpu
4899          */
4900         if (unlikely(svm->vmcb->control.exit_code ==
4901                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4902                 svm_handle_mce(svm);
4903
4904         mark_all_clean(svm->vmcb);
4905 }
4906
4907 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4908 {
4909         struct vcpu_svm *svm = to_svm(vcpu);
4910
4911         svm->vmcb->save.cr3 = root;
4912         mark_dirty(svm->vmcb, VMCB_CR);
4913         svm_flush_tlb(vcpu);
4914 }
4915
4916 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4917 {
4918         struct vcpu_svm *svm = to_svm(vcpu);
4919
4920         svm->vmcb->control.nested_cr3 = root;
4921         mark_dirty(svm->vmcb, VMCB_NPT);
4922
4923         /* Also sync guest cr3 here in case we live migrate */
4924         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4925         mark_dirty(svm->vmcb, VMCB_CR);
4926
4927         svm_flush_tlb(vcpu);
4928 }
4929
4930 static int is_disabled(void)
4931 {
4932         u64 vm_cr;
4933
4934         rdmsrl(MSR_VM_CR, vm_cr);
4935         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4936                 return 1;
4937
4938         return 0;
4939 }
4940
4941 static void
4942 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4943 {
4944         /*
4945          * Patch in the VMMCALL instruction:
4946          */
4947         hypercall[0] = 0x0f;
4948         hypercall[1] = 0x01;
4949         hypercall[2] = 0xd9;
4950 }
4951
4952 static void svm_check_processor_compat(void *rtn)
4953 {
4954         *(int *)rtn = 0;
4955 }
4956
4957 static bool svm_cpu_has_accelerated_tpr(void)
4958 {
4959         return false;
4960 }
4961
4962 static bool svm_has_high_real_mode_segbase(void)
4963 {
4964         return true;
4965 }
4966
4967 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4968 {
4969         return 0;
4970 }
4971
4972 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4973 {
4974         struct vcpu_svm *svm = to_svm(vcpu);
4975         struct kvm_cpuid_entry2 *entry;
4976
4977         /* Update nrips enabled cache */
4978         svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4979
4980         if (!kvm_vcpu_apicv_active(vcpu))
4981                 return;
4982
4983         entry = kvm_find_cpuid_entry(vcpu, 1, 0);
4984         if (entry)
4985                 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4986 }
4987
4988 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4989 {
4990         switch (func) {
4991         case 0x1:
4992                 if (avic)
4993                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4994                 break;
4995         case 0x80000001:
4996                 if (nested)
4997                         entry->ecx |= (1 << 2); /* Set SVM bit */
4998                 break;
4999         case 0x8000000A:
5000                 entry->eax = 1; /* SVM revision 1 */
5001                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5002                                    ASID emulation to nested SVM */
5003                 entry->ecx = 0; /* Reserved */
5004                 entry->edx = 0; /* Per default do not support any
5005                                    additional features */
5006
5007                 /* Support next_rip if host supports it */
5008                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5009                         entry->edx |= SVM_FEATURE_NRIP;
5010
5011                 /* Support NPT for the guest if enabled */
5012                 if (npt_enabled)
5013                         entry->edx |= SVM_FEATURE_NPT;
5014
5015                 break;
5016         }
5017 }
5018
5019 static int svm_get_lpage_level(void)
5020 {
5021         return PT_PDPE_LEVEL;
5022 }
5023
5024 static bool svm_rdtscp_supported(void)
5025 {
5026         return boot_cpu_has(X86_FEATURE_RDTSCP);
5027 }
5028
5029 static bool svm_invpcid_supported(void)
5030 {
5031         return false;
5032 }
5033
5034 static bool svm_mpx_supported(void)
5035 {
5036         return false;
5037 }
5038
5039 static bool svm_xsaves_supported(void)
5040 {
5041         return false;
5042 }
5043
5044 static bool svm_has_wbinvd_exit(void)
5045 {
5046         return true;
5047 }
5048
5049 #define PRE_EX(exit)  { .exit_code = (exit), \
5050                         .stage = X86_ICPT_PRE_EXCEPT, }
5051 #define POST_EX(exit) { .exit_code = (exit), \
5052                         .stage = X86_ICPT_POST_EXCEPT, }
5053 #define POST_MEM(exit) { .exit_code = (exit), \
5054                         .stage = X86_ICPT_POST_MEMACCESS, }
5055
5056 static const struct __x86_intercept {
5057         u32 exit_code;
5058         enum x86_intercept_stage stage;
5059 } x86_intercept_map[] = {
5060         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5061         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5062         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5063         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5064         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5065         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5066         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5067         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5068         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5069         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5070         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5071         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5072         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5073         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5074         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5075         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5076         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5077         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5078         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5079         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5080         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5081         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5082         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5083         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5084         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5085         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5086         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5087         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5088         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5089         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5090         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5091         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5092         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5093         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5094         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5095         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5096         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5097         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5098         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5099         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5100         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5101         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5102         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5103         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5104         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5105         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5106 };
5107
5108 #undef PRE_EX
5109 #undef POST_EX
5110 #undef POST_MEM
5111
5112 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5113                                struct x86_instruction_info *info,
5114                                enum x86_intercept_stage stage)
5115 {
5116         struct vcpu_svm *svm = to_svm(vcpu);
5117         int vmexit, ret = X86EMUL_CONTINUE;
5118         struct __x86_intercept icpt_info;
5119         struct vmcb *vmcb = svm->vmcb;
5120
5121         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5122                 goto out;
5123
5124         icpt_info = x86_intercept_map[info->intercept];
5125
5126         if (stage != icpt_info.stage)
5127                 goto out;
5128
5129         switch (icpt_info.exit_code) {
5130         case SVM_EXIT_READ_CR0:
5131                 if (info->intercept == x86_intercept_cr_read)
5132                         icpt_info.exit_code += info->modrm_reg;
5133                 break;
5134         case SVM_EXIT_WRITE_CR0: {
5135                 unsigned long cr0, val;
5136                 u64 intercept;
5137
5138                 if (info->intercept == x86_intercept_cr_write)
5139                         icpt_info.exit_code += info->modrm_reg;
5140
5141                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5142                     info->intercept == x86_intercept_clts)
5143                         break;
5144
5145                 intercept = svm->nested.intercept;
5146
5147                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5148                         break;
5149
5150                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5151                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5152
5153                 if (info->intercept == x86_intercept_lmsw) {
5154                         cr0 &= 0xfUL;
5155                         val &= 0xfUL;
5156                         /* lmsw can't clear PE - catch this here */
5157                         if (cr0 & X86_CR0_PE)
5158                                 val |= X86_CR0_PE;
5159                 }
5160
5161                 if (cr0 ^ val)
5162                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5163
5164                 break;
5165         }
5166         case SVM_EXIT_READ_DR0:
5167         case SVM_EXIT_WRITE_DR0:
5168                 icpt_info.exit_code += info->modrm_reg;
5169                 break;
5170         case SVM_EXIT_MSR:
5171                 if (info->intercept == x86_intercept_wrmsr)
5172                         vmcb->control.exit_info_1 = 1;
5173                 else
5174                         vmcb->control.exit_info_1 = 0;
5175                 break;
5176         case SVM_EXIT_PAUSE:
5177                 /*
5178                  * We get this for NOP only, but pause
5179                  * is rep not, check this here
5180                  */
5181                 if (info->rep_prefix != REPE_PREFIX)
5182                         goto out;
5183         case SVM_EXIT_IOIO: {
5184                 u64 exit_info;
5185                 u32 bytes;
5186
5187                 if (info->intercept == x86_intercept_in ||
5188                     info->intercept == x86_intercept_ins) {
5189                         exit_info = ((info->src_val & 0xffff) << 16) |
5190                                 SVM_IOIO_TYPE_MASK;
5191                         bytes = info->dst_bytes;
5192                 } else {
5193                         exit_info = (info->dst_val & 0xffff) << 16;
5194                         bytes = info->src_bytes;
5195                 }
5196
5197                 if (info->intercept == x86_intercept_outs ||
5198                     info->intercept == x86_intercept_ins)
5199                         exit_info |= SVM_IOIO_STR_MASK;
5200
5201                 if (info->rep_prefix)
5202                         exit_info |= SVM_IOIO_REP_MASK;
5203
5204                 bytes = min(bytes, 4u);
5205
5206                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5207
5208                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5209
5210                 vmcb->control.exit_info_1 = exit_info;
5211                 vmcb->control.exit_info_2 = info->next_rip;
5212
5213                 break;
5214         }
5215         default:
5216                 break;
5217         }
5218
5219         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5220         if (static_cpu_has(X86_FEATURE_NRIPS))
5221                 vmcb->control.next_rip  = info->next_rip;
5222         vmcb->control.exit_code = icpt_info.exit_code;
5223         vmexit = nested_svm_exit_handled(svm);
5224
5225         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5226                                            : X86EMUL_CONTINUE;
5227
5228 out:
5229         return ret;
5230 }
5231
5232 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5233 {
5234         local_irq_enable();
5235         /*
5236          * We must have an instruction with interrupts enabled, so
5237          * the timer interrupt isn't delayed by the interrupt shadow.
5238          */
5239         asm("nop");
5240         local_irq_disable();
5241 }
5242
5243 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5244 {
5245 }
5246
5247 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5248 {
5249         if (avic_handle_apic_id_update(vcpu) != 0)
5250                 return;
5251         if (avic_handle_dfr_update(vcpu) != 0)
5252                 return;
5253         avic_handle_ldr_update(vcpu);
5254 }
5255
5256 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5257         .cpu_has_kvm_support = has_svm,
5258         .disabled_by_bios = is_disabled,
5259         .hardware_setup = svm_hardware_setup,
5260         .hardware_unsetup = svm_hardware_unsetup,
5261         .check_processor_compatibility = svm_check_processor_compat,
5262         .hardware_enable = svm_hardware_enable,
5263         .hardware_disable = svm_hardware_disable,
5264         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5265         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5266
5267         .vcpu_create = svm_create_vcpu,
5268         .vcpu_free = svm_free_vcpu,
5269         .vcpu_reset = svm_vcpu_reset,
5270
5271         .vm_init = avic_vm_init,
5272         .vm_destroy = avic_vm_destroy,
5273
5274         .prepare_guest_switch = svm_prepare_guest_switch,
5275         .vcpu_load = svm_vcpu_load,
5276         .vcpu_put = svm_vcpu_put,
5277         .vcpu_blocking = svm_vcpu_blocking,
5278         .vcpu_unblocking = svm_vcpu_unblocking,
5279
5280         .update_bp_intercept = update_bp_intercept,
5281         .get_msr = svm_get_msr,
5282         .set_msr = svm_set_msr,
5283         .get_segment_base = svm_get_segment_base,
5284         .get_segment = svm_get_segment,
5285         .set_segment = svm_set_segment,
5286         .get_cpl = svm_get_cpl,
5287         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5288         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5289         .decache_cr3 = svm_decache_cr3,
5290         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5291         .set_cr0 = svm_set_cr0,
5292         .set_cr3 = svm_set_cr3,
5293         .set_cr4 = svm_set_cr4,
5294         .set_efer = svm_set_efer,
5295         .get_idt = svm_get_idt,
5296         .set_idt = svm_set_idt,
5297         .get_gdt = svm_get_gdt,
5298         .set_gdt = svm_set_gdt,
5299         .get_dr6 = svm_get_dr6,
5300         .set_dr6 = svm_set_dr6,
5301         .set_dr7 = svm_set_dr7,
5302         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5303         .cache_reg = svm_cache_reg,
5304         .get_rflags = svm_get_rflags,
5305         .set_rflags = svm_set_rflags,
5306
5307         .get_pkru = svm_get_pkru,
5308
5309         .tlb_flush = svm_flush_tlb,
5310
5311         .run = svm_vcpu_run,
5312         .handle_exit = handle_exit,
5313         .skip_emulated_instruction = skip_emulated_instruction,
5314         .set_interrupt_shadow = svm_set_interrupt_shadow,
5315         .get_interrupt_shadow = svm_get_interrupt_shadow,
5316         .patch_hypercall = svm_patch_hypercall,
5317         .set_irq = svm_set_irq,
5318         .set_nmi = svm_inject_nmi,
5319         .queue_exception = svm_queue_exception,
5320         .cancel_injection = svm_cancel_injection,
5321         .interrupt_allowed = svm_interrupt_allowed,
5322         .nmi_allowed = svm_nmi_allowed,
5323         .get_nmi_mask = svm_get_nmi_mask,
5324         .set_nmi_mask = svm_set_nmi_mask,
5325         .enable_nmi_window = enable_nmi_window,
5326         .enable_irq_window = enable_irq_window,
5327         .update_cr8_intercept = update_cr8_intercept,
5328         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5329         .get_enable_apicv = svm_get_enable_apicv,
5330         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5331         .load_eoi_exitmap = svm_load_eoi_exitmap,
5332         .hwapic_irr_update = svm_hwapic_irr_update,
5333         .hwapic_isr_update = svm_hwapic_isr_update,
5334         .apicv_post_state_restore = avic_post_state_restore,
5335
5336         .set_tss_addr = svm_set_tss_addr,
5337         .get_tdp_level = get_npt_level,
5338         .get_mt_mask = svm_get_mt_mask,
5339
5340         .get_exit_info = svm_get_exit_info,
5341
5342         .get_lpage_level = svm_get_lpage_level,
5343
5344         .cpuid_update = svm_cpuid_update,
5345
5346         .rdtscp_supported = svm_rdtscp_supported,
5347         .invpcid_supported = svm_invpcid_supported,
5348         .mpx_supported = svm_mpx_supported,
5349         .xsaves_supported = svm_xsaves_supported,
5350
5351         .set_supported_cpuid = svm_set_supported_cpuid,
5352
5353         .has_wbinvd_exit = svm_has_wbinvd_exit,
5354
5355         .write_tsc_offset = svm_write_tsc_offset,
5356
5357         .set_tdp_cr3 = set_tdp_cr3,
5358
5359         .check_intercept = svm_check_intercept,
5360         .handle_external_intr = svm_handle_external_intr,
5361
5362         .sched_in = svm_sched_in,
5363
5364         .pmu_ops = &amd_pmu_ops,
5365         .deliver_posted_interrupt = svm_deliver_avic_intr,
5366         .update_pi_irte = svm_update_pi_irte,
5367 };
5368
5369 static int __init svm_init(void)
5370 {
5371         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5372                         __alignof__(struct vcpu_svm), THIS_MODULE);
5373 }
5374
5375 static void __exit svm_exit(void)
5376 {
5377         kvm_exit();
5378 }
5379
5380 module_init(svm_init)
5381 module_exit(svm_exit)