2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74 #define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
77 (X86_CR0_WP | X86_CR0_NE)
78 #define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
80 #define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
100 #define KVM_VMX_DEFAULT_PLE_GAP 41
101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103 module_param(ple_gap, int, S_IRUGO);
105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106 module_param(ple_window, int, S_IRUGO);
108 #define NR_AUTOLOAD_MSRS 1
116 struct shared_msr_entry {
123 struct kvm_vcpu vcpu;
124 struct list_head local_vcpus_link;
125 unsigned long host_rsp;
128 u32 idt_vectoring_info;
129 struct shared_msr_entry *guest_msrs;
133 u64 msr_host_kernel_gs_base;
134 u64 msr_guest_kernel_gs_base;
137 struct msr_autoload {
139 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
140 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
144 u16 fs_sel, gs_sel, ldt_sel;
145 int gs_ldt_reload_needed;
146 int fs_reload_needed;
151 struct kvm_save_segment {
156 } tr, es, ds, fs, gs;
164 bool emulation_required;
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
169 s64 vnmi_blocked_time;
175 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
177 return container_of(vcpu, struct vcpu_vmx, vcpu);
180 static int init_rmode(struct kvm *kvm);
181 static u64 construct_eptp(unsigned long root_hpa);
182 static void kvm_cpu_vmxon(u64 addr);
183 static void kvm_cpu_vmxoff(void);
185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
190 static unsigned long *vmx_io_bitmap_a;
191 static unsigned long *vmx_io_bitmap_b;
192 static unsigned long *vmx_msr_bitmap_legacy;
193 static unsigned long *vmx_msr_bitmap_longmode;
195 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
196 static DEFINE_SPINLOCK(vmx_vpid_lock);
198 static struct vmcs_config {
202 u32 pin_based_exec_ctrl;
203 u32 cpu_based_exec_ctrl;
204 u32 cpu_based_2nd_exec_ctrl;
209 static struct vmx_capability {
214 #define VMX_SEGMENT_FIELD(seg) \
215 [VCPU_SREG_##seg] = { \
216 .selector = GUEST_##seg##_SELECTOR, \
217 .base = GUEST_##seg##_BASE, \
218 .limit = GUEST_##seg##_LIMIT, \
219 .ar_bytes = GUEST_##seg##_AR_BYTES, \
222 static struct kvm_vmx_segment_field {
227 } kvm_vmx_segment_fields[] = {
228 VMX_SEGMENT_FIELD(CS),
229 VMX_SEGMENT_FIELD(DS),
230 VMX_SEGMENT_FIELD(ES),
231 VMX_SEGMENT_FIELD(FS),
232 VMX_SEGMENT_FIELD(GS),
233 VMX_SEGMENT_FIELD(SS),
234 VMX_SEGMENT_FIELD(TR),
235 VMX_SEGMENT_FIELD(LDTR),
238 static u64 host_efer;
240 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
243 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
244 * away by decrementing the array size.
246 static const u32 vmx_msr_index[] = {
248 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
250 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
252 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
254 static inline bool is_page_fault(u32 intr_info)
256 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
257 INTR_INFO_VALID_MASK)) ==
258 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
261 static inline bool is_no_device(u32 intr_info)
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
265 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
268 static inline bool is_invalid_opcode(u32 intr_info)
270 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
271 INTR_INFO_VALID_MASK)) ==
272 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
275 static inline bool is_external_interrupt(u32 intr_info)
277 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
278 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
281 static inline bool is_machine_check(u32 intr_info)
283 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
284 INTR_INFO_VALID_MASK)) ==
285 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
288 static inline bool cpu_has_vmx_msr_bitmap(void)
290 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
293 static inline bool cpu_has_vmx_tpr_shadow(void)
295 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
298 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
300 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
303 static inline bool cpu_has_secondary_exec_ctrls(void)
305 return vmcs_config.cpu_based_exec_ctrl &
306 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
309 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
311 return vmcs_config.cpu_based_2nd_exec_ctrl &
312 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
315 static inline bool cpu_has_vmx_flexpriority(void)
317 return cpu_has_vmx_tpr_shadow() &&
318 cpu_has_vmx_virtualize_apic_accesses();
321 static inline bool cpu_has_vmx_ept_execute_only(void)
323 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
326 static inline bool cpu_has_vmx_eptp_uncacheable(void)
328 return vmx_capability.ept & VMX_EPTP_UC_BIT;
331 static inline bool cpu_has_vmx_eptp_writeback(void)
333 return vmx_capability.ept & VMX_EPTP_WB_BIT;
336 static inline bool cpu_has_vmx_ept_2m_page(void)
338 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
341 static inline bool cpu_has_vmx_ept_1g_page(void)
343 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
346 static inline bool cpu_has_vmx_ept_4levels(void)
348 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
351 static inline bool cpu_has_vmx_invept_individual_addr(void)
353 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
356 static inline bool cpu_has_vmx_invept_context(void)
358 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
361 static inline bool cpu_has_vmx_invept_global(void)
363 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
366 static inline bool cpu_has_vmx_invvpid_single(void)
368 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
371 static inline bool cpu_has_vmx_invvpid_global(void)
373 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
376 static inline bool cpu_has_vmx_ept(void)
378 return vmcs_config.cpu_based_2nd_exec_ctrl &
379 SECONDARY_EXEC_ENABLE_EPT;
382 static inline bool cpu_has_vmx_unrestricted_guest(void)
384 return vmcs_config.cpu_based_2nd_exec_ctrl &
385 SECONDARY_EXEC_UNRESTRICTED_GUEST;
388 static inline bool cpu_has_vmx_ple(void)
390 return vmcs_config.cpu_based_2nd_exec_ctrl &
391 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
394 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
396 return flexpriority_enabled && irqchip_in_kernel(kvm);
399 static inline bool cpu_has_vmx_vpid(void)
401 return vmcs_config.cpu_based_2nd_exec_ctrl &
402 SECONDARY_EXEC_ENABLE_VPID;
405 static inline bool cpu_has_vmx_rdtscp(void)
407 return vmcs_config.cpu_based_2nd_exec_ctrl &
408 SECONDARY_EXEC_RDTSCP;
411 static inline bool cpu_has_virtual_nmis(void)
413 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
416 static inline bool cpu_has_vmx_wbinvd_exit(void)
418 return vmcs_config.cpu_based_2nd_exec_ctrl &
419 SECONDARY_EXEC_WBINVD_EXITING;
422 static inline bool report_flexpriority(void)
424 return flexpriority_enabled;
427 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
431 for (i = 0; i < vmx->nmsrs; ++i)
432 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
437 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
443 } operand = { vpid, 0, gva };
445 asm volatile (__ex(ASM_VMX_INVVPID)
446 /* CF==1 or ZF==1 --> rc = -1 */
448 : : "a"(&operand), "c"(ext) : "cc", "memory");
451 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
455 } operand = {eptp, gpa};
457 asm volatile (__ex(ASM_VMX_INVEPT)
458 /* CF==1 or ZF==1 --> rc = -1 */
459 "; ja 1f ; ud2 ; 1:\n"
460 : : "a" (&operand), "c" (ext) : "cc", "memory");
463 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
467 i = __find_msr_index(vmx, msr);
469 return &vmx->guest_msrs[i];
473 static void vmcs_clear(struct vmcs *vmcs)
475 u64 phys_addr = __pa(vmcs);
478 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
479 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
482 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
486 static void vmcs_load(struct vmcs *vmcs)
488 u64 phys_addr = __pa(vmcs);
491 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
492 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
495 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
499 static void __vcpu_clear(void *arg)
501 struct vcpu_vmx *vmx = arg;
502 int cpu = raw_smp_processor_id();
504 if (vmx->vcpu.cpu == cpu)
505 vmcs_clear(vmx->vmcs);
506 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
507 per_cpu(current_vmcs, cpu) = NULL;
508 rdtscll(vmx->vcpu.arch.host_tsc);
509 list_del(&vmx->local_vcpus_link);
514 static void vcpu_clear(struct vcpu_vmx *vmx)
516 if (vmx->vcpu.cpu == -1)
518 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
530 static inline void vpid_sync_vcpu_global(void)
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
538 if (cpu_has_vmx_invvpid_single())
539 vpid_sync_vcpu_single(vmx);
541 vpid_sync_vcpu_global();
544 static inline void ept_sync_global(void)
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
550 static inline void ept_sync_context(u64 eptp)
553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
567 ept_sync_context(eptp);
571 static unsigned long vmcs_readl(unsigned long field)
575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
576 : "=a"(value) : "d"(field) : "cc");
580 static u16 vmcs_read16(unsigned long field)
582 return vmcs_readl(field);
585 static u32 vmcs_read32(unsigned long field)
587 return vmcs_readl(field);
590 static u64 vmcs_read64(unsigned long field)
593 return vmcs_readl(field);
595 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
601 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
602 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
606 static void vmcs_writel(unsigned long field, unsigned long value)
610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
611 : "=q"(error) : "a"(value), "d"(field) : "cc");
613 vmwrite_error(field, value);
616 static void vmcs_write16(unsigned long field, u16 value)
618 vmcs_writel(field, value);
621 static void vmcs_write32(unsigned long field, u32 value)
623 vmcs_writel(field, value);
626 static void vmcs_write64(unsigned long field, u64 value)
628 vmcs_writel(field, value);
629 #ifndef CONFIG_X86_64
631 vmcs_writel(field+1, value >> 32);
635 static void vmcs_clear_bits(unsigned long field, u32 mask)
637 vmcs_writel(field, vmcs_readl(field) & ~mask);
640 static void vmcs_set_bits(unsigned long field, u32 mask)
642 vmcs_writel(field, vmcs_readl(field) | mask);
645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
649 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
650 (1u << NM_VECTOR) | (1u << DB_VECTOR);
651 if ((vcpu->guest_debug &
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
654 eb |= 1u << BP_VECTOR;
655 if (to_vmx(vcpu)->rmode.vm86_active)
658 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
659 if (vcpu->fpu_active)
660 eb &= ~(1u << NM_VECTOR);
661 vmcs_write32(EXCEPTION_BITMAP, eb);
664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
667 struct msr_autoload *m = &vmx->msr_autoload;
669 for (i = 0; i < m->nr; ++i)
670 if (m->guest[i].index == msr)
676 m->guest[i] = m->guest[m->nr];
677 m->host[i] = m->host[m->nr];
678 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
679 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
682 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
683 u64 guest_val, u64 host_val)
686 struct msr_autoload *m = &vmx->msr_autoload;
688 for (i = 0; i < m->nr; ++i)
689 if (m->guest[i].index == msr)
694 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
695 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
698 m->guest[i].index = msr;
699 m->guest[i].value = guest_val;
700 m->host[i].index = msr;
701 m->host[i].value = host_val;
704 static void reload_tss(void)
707 * VT restores TR but not its size. Useless.
710 struct desc_struct *descs;
712 native_store_gdt(&gdt);
713 descs = (void *)gdt.address;
714 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
718 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
723 guest_efer = vmx->vcpu.arch.efer;
726 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
729 ignore_bits = EFER_NX | EFER_SCE;
731 ignore_bits |= EFER_LMA | EFER_LME;
732 /* SCE is meaningful only in long mode on Intel */
733 if (guest_efer & EFER_LMA)
734 ignore_bits &= ~(u64)EFER_SCE;
736 guest_efer &= ~ignore_bits;
737 guest_efer |= host_efer & ignore_bits;
738 vmx->guest_msrs[efer_offset].data = guest_efer;
739 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
741 clear_atomic_switch_msr(vmx, MSR_EFER);
742 /* On ept, can't emulate nx, and must switch nx atomically */
743 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
744 guest_efer = vmx->vcpu.arch.efer;
745 if (!(guest_efer & EFER_LMA))
746 guest_efer &= ~EFER_LME;
747 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
754 static unsigned long segment_base(u16 selector)
757 struct desc_struct *d;
758 unsigned long table_base;
761 if (!(selector & ~3))
764 native_store_gdt(&gdt);
765 table_base = gdt.address;
767 if (selector & 4) { /* from ldt */
768 u16 ldt_selector = kvm_read_ldt();
770 if (!(ldt_selector & ~3))
773 table_base = segment_base(ldt_selector);
775 d = (struct desc_struct *)(table_base + (selector & ~7));
776 v = get_desc_base(d);
778 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
779 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
784 static inline unsigned long kvm_read_tr_base(void)
787 asm("str %0" : "=g"(tr));
788 return segment_base(tr);
791 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
793 struct vcpu_vmx *vmx = to_vmx(vcpu);
796 if (vmx->host_state.loaded)
799 vmx->host_state.loaded = 1;
801 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
802 * allow segment selectors with cpl > 0 or ti == 1.
804 vmx->host_state.ldt_sel = kvm_read_ldt();
805 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
806 vmx->host_state.fs_sel = kvm_read_fs();
807 if (!(vmx->host_state.fs_sel & 7)) {
808 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
809 vmx->host_state.fs_reload_needed = 0;
811 vmcs_write16(HOST_FS_SELECTOR, 0);
812 vmx->host_state.fs_reload_needed = 1;
814 vmx->host_state.gs_sel = kvm_read_gs();
815 if (!(vmx->host_state.gs_sel & 7))
816 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
818 vmcs_write16(HOST_GS_SELECTOR, 0);
819 vmx->host_state.gs_ldt_reload_needed = 1;
823 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
824 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
826 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
827 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
831 if (is_long_mode(&vmx->vcpu)) {
832 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
833 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
836 for (i = 0; i < vmx->save_nmsrs; ++i)
837 kvm_set_shared_msr(vmx->guest_msrs[i].index,
838 vmx->guest_msrs[i].data,
839 vmx->guest_msrs[i].mask);
842 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
846 if (!vmx->host_state.loaded)
849 ++vmx->vcpu.stat.host_state_reload;
850 vmx->host_state.loaded = 0;
851 if (vmx->host_state.fs_reload_needed)
852 kvm_load_fs(vmx->host_state.fs_sel);
853 if (vmx->host_state.gs_ldt_reload_needed) {
854 kvm_load_ldt(vmx->host_state.ldt_sel);
856 * If we have to reload gs, we must take care to
857 * preserve our gs base.
859 local_irq_save(flags);
860 kvm_load_gs(vmx->host_state.gs_sel);
862 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
864 local_irq_restore(flags);
868 if (is_long_mode(&vmx->vcpu)) {
869 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
870 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
873 if (current_thread_info()->status & TS_USEDFPU)
875 load_gdt(&__get_cpu_var(host_gdt));
878 static void vmx_load_host_state(struct vcpu_vmx *vmx)
881 __vmx_load_host_state(vmx);
886 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
887 * vcpu mutex is already taken.
889 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
891 struct vcpu_vmx *vmx = to_vmx(vcpu);
892 u64 tsc_this, delta, new_offset;
893 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
896 kvm_cpu_vmxon(phys_addr);
897 else if (vcpu->cpu != cpu)
900 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
901 per_cpu(current_vmcs, cpu) = vmx->vmcs;
902 vmcs_load(vmx->vmcs);
905 if (vcpu->cpu != cpu) {
907 unsigned long sysenter_esp;
909 kvm_migrate_timers(vcpu);
910 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
912 list_add(&vmx->local_vcpus_link,
913 &per_cpu(vcpus_on_cpu, cpu));
918 * Linux uses per-cpu TSS and GDT, so set these when switching
921 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
922 native_store_gdt(&dt);
923 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
925 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
926 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
929 * Make sure the time stamp counter is monotonous.
932 if (tsc_this < vcpu->arch.host_tsc) {
933 delta = vcpu->arch.host_tsc - tsc_this;
934 new_offset = vmcs_read64(TSC_OFFSET) + delta;
935 vmcs_write64(TSC_OFFSET, new_offset);
940 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
942 __vmx_load_host_state(to_vmx(vcpu));
943 if (!vmm_exclusive) {
944 __vcpu_clear(to_vmx(vcpu));
949 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
953 if (vcpu->fpu_active)
955 vcpu->fpu_active = 1;
956 cr0 = vmcs_readl(GUEST_CR0);
957 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
958 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
959 vmcs_writel(GUEST_CR0, cr0);
960 update_exception_bitmap(vcpu);
961 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
962 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
965 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
967 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
969 vmx_decache_cr0_guest_bits(vcpu);
970 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
971 update_exception_bitmap(vcpu);
972 vcpu->arch.cr0_guest_owned_bits = 0;
973 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
974 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
977 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
979 unsigned long rflags, save_rflags;
981 rflags = vmcs_readl(GUEST_RFLAGS);
982 if (to_vmx(vcpu)->rmode.vm86_active) {
983 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
984 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
985 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
990 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
992 if (to_vmx(vcpu)->rmode.vm86_active) {
993 to_vmx(vcpu)->rmode.save_rflags = rflags;
994 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
996 vmcs_writel(GUEST_RFLAGS, rflags);
999 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1001 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1004 if (interruptibility & GUEST_INTR_STATE_STI)
1005 ret |= KVM_X86_SHADOW_INT_STI;
1006 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1007 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1012 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1014 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1015 u32 interruptibility = interruptibility_old;
1017 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1019 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1020 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1021 else if (mask & KVM_X86_SHADOW_INT_STI)
1022 interruptibility |= GUEST_INTR_STATE_STI;
1024 if ((interruptibility != interruptibility_old))
1025 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1028 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1032 rip = kvm_rip_read(vcpu);
1033 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1034 kvm_rip_write(vcpu, rip);
1036 /* skipping an emulated instruction also counts */
1037 vmx_set_interrupt_shadow(vcpu, 0);
1040 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1041 bool has_error_code, u32 error_code,
1044 struct vcpu_vmx *vmx = to_vmx(vcpu);
1045 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1047 if (has_error_code) {
1048 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1049 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1052 if (vmx->rmode.vm86_active) {
1053 vmx->rmode.irq.pending = true;
1054 vmx->rmode.irq.vector = nr;
1055 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1056 if (kvm_exception_is_soft(nr))
1057 vmx->rmode.irq.rip +=
1058 vmx->vcpu.arch.event_exit_inst_len;
1059 intr_info |= INTR_TYPE_SOFT_INTR;
1060 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1061 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1062 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1066 if (kvm_exception_is_soft(nr)) {
1067 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1068 vmx->vcpu.arch.event_exit_inst_len);
1069 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1071 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1073 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1076 static bool vmx_rdtscp_supported(void)
1078 return cpu_has_vmx_rdtscp();
1082 * Swap MSR entry in host/guest MSR entry array.
1084 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1086 struct shared_msr_entry tmp;
1088 tmp = vmx->guest_msrs[to];
1089 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1090 vmx->guest_msrs[from] = tmp;
1094 * Set up the vmcs to automatically save and restore system
1095 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1096 * mode, as fiddling with msrs is very expensive.
1098 static void setup_msrs(struct vcpu_vmx *vmx)
1100 int save_nmsrs, index;
1101 unsigned long *msr_bitmap;
1103 vmx_load_host_state(vmx);
1105 #ifdef CONFIG_X86_64
1106 if (is_long_mode(&vmx->vcpu)) {
1107 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1109 move_msr_up(vmx, index, save_nmsrs++);
1110 index = __find_msr_index(vmx, MSR_LSTAR);
1112 move_msr_up(vmx, index, save_nmsrs++);
1113 index = __find_msr_index(vmx, MSR_CSTAR);
1115 move_msr_up(vmx, index, save_nmsrs++);
1116 index = __find_msr_index(vmx, MSR_TSC_AUX);
1117 if (index >= 0 && vmx->rdtscp_enabled)
1118 move_msr_up(vmx, index, save_nmsrs++);
1120 * MSR_K6_STAR is only needed on long mode guests, and only
1121 * if efer.sce is enabled.
1123 index = __find_msr_index(vmx, MSR_K6_STAR);
1124 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1125 move_msr_up(vmx, index, save_nmsrs++);
1128 index = __find_msr_index(vmx, MSR_EFER);
1129 if (index >= 0 && update_transition_efer(vmx, index))
1130 move_msr_up(vmx, index, save_nmsrs++);
1132 vmx->save_nmsrs = save_nmsrs;
1134 if (cpu_has_vmx_msr_bitmap()) {
1135 if (is_long_mode(&vmx->vcpu))
1136 msr_bitmap = vmx_msr_bitmap_longmode;
1138 msr_bitmap = vmx_msr_bitmap_legacy;
1140 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1145 * reads and returns guest's timestamp counter "register"
1146 * guest_tsc = host_tsc + tsc_offset -- 21.3
1148 static u64 guest_read_tsc(void)
1150 u64 host_tsc, tsc_offset;
1153 tsc_offset = vmcs_read64(TSC_OFFSET);
1154 return host_tsc + tsc_offset;
1158 * writes 'guest_tsc' into guest's timestamp counter "register"
1159 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1161 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1163 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1167 * Reads an msr value (of 'msr_index') into 'pdata'.
1168 * Returns 0 on success, non-0 otherwise.
1169 * Assumes vcpu_load() was already called.
1171 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1174 struct shared_msr_entry *msr;
1177 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1181 switch (msr_index) {
1182 #ifdef CONFIG_X86_64
1184 data = vmcs_readl(GUEST_FS_BASE);
1187 data = vmcs_readl(GUEST_GS_BASE);
1189 case MSR_KERNEL_GS_BASE:
1190 vmx_load_host_state(to_vmx(vcpu));
1191 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1195 return kvm_get_msr_common(vcpu, msr_index, pdata);
1197 data = guest_read_tsc();
1199 case MSR_IA32_SYSENTER_CS:
1200 data = vmcs_read32(GUEST_SYSENTER_CS);
1202 case MSR_IA32_SYSENTER_EIP:
1203 data = vmcs_readl(GUEST_SYSENTER_EIP);
1205 case MSR_IA32_SYSENTER_ESP:
1206 data = vmcs_readl(GUEST_SYSENTER_ESP);
1209 if (!to_vmx(vcpu)->rdtscp_enabled)
1211 /* Otherwise falls through */
1213 vmx_load_host_state(to_vmx(vcpu));
1214 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1216 vmx_load_host_state(to_vmx(vcpu));
1220 return kvm_get_msr_common(vcpu, msr_index, pdata);
1228 * Writes msr value into into the appropriate "register".
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1232 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1234 struct vcpu_vmx *vmx = to_vmx(vcpu);
1235 struct shared_msr_entry *msr;
1239 switch (msr_index) {
1241 vmx_load_host_state(vmx);
1242 ret = kvm_set_msr_common(vcpu, msr_index, data);
1244 #ifdef CONFIG_X86_64
1246 vmcs_writel(GUEST_FS_BASE, data);
1249 vmcs_writel(GUEST_GS_BASE, data);
1251 case MSR_KERNEL_GS_BASE:
1252 vmx_load_host_state(vmx);
1253 vmx->msr_guest_kernel_gs_base = data;
1256 case MSR_IA32_SYSENTER_CS:
1257 vmcs_write32(GUEST_SYSENTER_CS, data);
1259 case MSR_IA32_SYSENTER_EIP:
1260 vmcs_writel(GUEST_SYSENTER_EIP, data);
1262 case MSR_IA32_SYSENTER_ESP:
1263 vmcs_writel(GUEST_SYSENTER_ESP, data);
1267 guest_write_tsc(data, host_tsc);
1269 case MSR_IA32_CR_PAT:
1270 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1271 vmcs_write64(GUEST_IA32_PAT, data);
1272 vcpu->arch.pat = data;
1275 ret = kvm_set_msr_common(vcpu, msr_index, data);
1278 if (!vmx->rdtscp_enabled)
1280 /* Check reserved bit, higher 32 bits should be zero */
1281 if ((data >> 32) != 0)
1283 /* Otherwise falls through */
1285 msr = find_msr_entry(vmx, msr_index);
1287 vmx_load_host_state(vmx);
1291 ret = kvm_set_msr_common(vcpu, msr_index, data);
1297 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1299 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1302 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1305 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1307 case VCPU_EXREG_PDPTR:
1309 ept_save_pdptrs(vcpu);
1316 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1318 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1319 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1321 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1323 update_exception_bitmap(vcpu);
1326 static __init int cpu_has_kvm_support(void)
1328 return cpu_has_vmx();
1331 static __init int vmx_disabled_by_bios(void)
1335 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1336 if (msr & FEATURE_CONTROL_LOCKED) {
1337 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1340 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1341 && !tboot_enabled())
1346 /* locked but not enabled */
1349 static void kvm_cpu_vmxon(u64 addr)
1351 asm volatile (ASM_VMX_VMXON_RAX
1352 : : "a"(&addr), "m"(addr)
1356 static int hardware_enable(void *garbage)
1358 int cpu = raw_smp_processor_id();
1359 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1362 if (read_cr4() & X86_CR4_VMXE)
1365 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1366 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1368 test_bits = FEATURE_CONTROL_LOCKED;
1369 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1370 if (tboot_enabled())
1371 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1373 if ((old & test_bits) != test_bits) {
1374 /* enable and lock */
1375 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1377 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1379 if (vmm_exclusive) {
1380 kvm_cpu_vmxon(phys_addr);
1384 store_gdt(&__get_cpu_var(host_gdt));
1389 static void vmclear_local_vcpus(void)
1391 int cpu = raw_smp_processor_id();
1392 struct vcpu_vmx *vmx, *n;
1394 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1400 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1403 static void kvm_cpu_vmxoff(void)
1405 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1408 static void hardware_disable(void *garbage)
1410 if (vmm_exclusive) {
1411 vmclear_local_vcpus();
1414 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1417 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1418 u32 msr, u32 *result)
1420 u32 vmx_msr_low, vmx_msr_high;
1421 u32 ctl = ctl_min | ctl_opt;
1423 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1425 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1426 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1428 /* Ensure minimum (required) set of control bits are supported. */
1436 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1438 u32 vmx_msr_low, vmx_msr_high;
1439 u32 min, opt, min2, opt2;
1440 u32 _pin_based_exec_control = 0;
1441 u32 _cpu_based_exec_control = 0;
1442 u32 _cpu_based_2nd_exec_control = 0;
1443 u32 _vmexit_control = 0;
1444 u32 _vmentry_control = 0;
1446 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1447 opt = PIN_BASED_VIRTUAL_NMIS;
1448 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1449 &_pin_based_exec_control) < 0)
1452 min = CPU_BASED_HLT_EXITING |
1453 #ifdef CONFIG_X86_64
1454 CPU_BASED_CR8_LOAD_EXITING |
1455 CPU_BASED_CR8_STORE_EXITING |
1457 CPU_BASED_CR3_LOAD_EXITING |
1458 CPU_BASED_CR3_STORE_EXITING |
1459 CPU_BASED_USE_IO_BITMAPS |
1460 CPU_BASED_MOV_DR_EXITING |
1461 CPU_BASED_USE_TSC_OFFSETING |
1462 CPU_BASED_MWAIT_EXITING |
1463 CPU_BASED_MONITOR_EXITING |
1464 CPU_BASED_INVLPG_EXITING;
1465 opt = CPU_BASED_TPR_SHADOW |
1466 CPU_BASED_USE_MSR_BITMAPS |
1467 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1469 &_cpu_based_exec_control) < 0)
1471 #ifdef CONFIG_X86_64
1472 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1473 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1474 ~CPU_BASED_CR8_STORE_EXITING;
1476 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1478 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1479 SECONDARY_EXEC_WBINVD_EXITING |
1480 SECONDARY_EXEC_ENABLE_VPID |
1481 SECONDARY_EXEC_ENABLE_EPT |
1482 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1483 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1484 SECONDARY_EXEC_RDTSCP;
1485 if (adjust_vmx_controls(min2, opt2,
1486 MSR_IA32_VMX_PROCBASED_CTLS2,
1487 &_cpu_based_2nd_exec_control) < 0)
1490 #ifndef CONFIG_X86_64
1491 if (!(_cpu_based_2nd_exec_control &
1492 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1493 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1495 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1496 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1498 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1499 CPU_BASED_CR3_STORE_EXITING |
1500 CPU_BASED_INVLPG_EXITING);
1501 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1502 vmx_capability.ept, vmx_capability.vpid);
1506 #ifdef CONFIG_X86_64
1507 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1509 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1510 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1511 &_vmexit_control) < 0)
1515 opt = VM_ENTRY_LOAD_IA32_PAT;
1516 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1517 &_vmentry_control) < 0)
1520 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1522 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1523 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1526 #ifdef CONFIG_X86_64
1527 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1528 if (vmx_msr_high & (1u<<16))
1532 /* Require Write-Back (WB) memory type for VMCS accesses. */
1533 if (((vmx_msr_high >> 18) & 15) != 6)
1536 vmcs_conf->size = vmx_msr_high & 0x1fff;
1537 vmcs_conf->order = get_order(vmcs_config.size);
1538 vmcs_conf->revision_id = vmx_msr_low;
1540 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1541 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1542 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1543 vmcs_conf->vmexit_ctrl = _vmexit_control;
1544 vmcs_conf->vmentry_ctrl = _vmentry_control;
1549 static struct vmcs *alloc_vmcs_cpu(int cpu)
1551 int node = cpu_to_node(cpu);
1555 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1558 vmcs = page_address(pages);
1559 memset(vmcs, 0, vmcs_config.size);
1560 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1564 static struct vmcs *alloc_vmcs(void)
1566 return alloc_vmcs_cpu(raw_smp_processor_id());
1569 static void free_vmcs(struct vmcs *vmcs)
1571 free_pages((unsigned long)vmcs, vmcs_config.order);
1574 static void free_kvm_area(void)
1578 for_each_possible_cpu(cpu) {
1579 free_vmcs(per_cpu(vmxarea, cpu));
1580 per_cpu(vmxarea, cpu) = NULL;
1584 static __init int alloc_kvm_area(void)
1588 for_each_possible_cpu(cpu) {
1591 vmcs = alloc_vmcs_cpu(cpu);
1597 per_cpu(vmxarea, cpu) = vmcs;
1602 static __init int hardware_setup(void)
1604 if (setup_vmcs_config(&vmcs_config) < 0)
1607 if (boot_cpu_has(X86_FEATURE_NX))
1608 kvm_enable_efer_bits(EFER_NX);
1610 if (!cpu_has_vmx_vpid())
1613 if (!cpu_has_vmx_ept() ||
1614 !cpu_has_vmx_ept_4levels()) {
1616 enable_unrestricted_guest = 0;
1619 if (!cpu_has_vmx_unrestricted_guest())
1620 enable_unrestricted_guest = 0;
1622 if (!cpu_has_vmx_flexpriority())
1623 flexpriority_enabled = 0;
1625 if (!cpu_has_vmx_tpr_shadow())
1626 kvm_x86_ops->update_cr8_intercept = NULL;
1628 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1629 kvm_disable_largepages();
1631 if (!cpu_has_vmx_ple())
1634 return alloc_kvm_area();
1637 static __exit void hardware_unsetup(void)
1642 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1644 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1646 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1647 vmcs_write16(sf->selector, save->selector);
1648 vmcs_writel(sf->base, save->base);
1649 vmcs_write32(sf->limit, save->limit);
1650 vmcs_write32(sf->ar_bytes, save->ar);
1652 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1654 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1658 static void enter_pmode(struct kvm_vcpu *vcpu)
1660 unsigned long flags;
1661 struct vcpu_vmx *vmx = to_vmx(vcpu);
1663 vmx->emulation_required = 1;
1664 vmx->rmode.vm86_active = 0;
1666 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1667 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1668 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1670 flags = vmcs_readl(GUEST_RFLAGS);
1671 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1672 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1673 vmcs_writel(GUEST_RFLAGS, flags);
1675 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1676 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1678 update_exception_bitmap(vcpu);
1680 if (emulate_invalid_guest_state)
1683 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1684 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1685 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1686 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1688 vmcs_write16(GUEST_SS_SELECTOR, 0);
1689 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1691 vmcs_write16(GUEST_CS_SELECTOR,
1692 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1693 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1696 static gva_t rmode_tss_base(struct kvm *kvm)
1698 if (!kvm->arch.tss_addr) {
1699 struct kvm_memslots *slots;
1702 slots = kvm_memslots(kvm);
1703 base_gfn = slots->memslots[0].base_gfn +
1704 kvm->memslots->memslots[0].npages - 3;
1705 return base_gfn << PAGE_SHIFT;
1707 return kvm->arch.tss_addr;
1710 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1712 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1714 save->selector = vmcs_read16(sf->selector);
1715 save->base = vmcs_readl(sf->base);
1716 save->limit = vmcs_read32(sf->limit);
1717 save->ar = vmcs_read32(sf->ar_bytes);
1718 vmcs_write16(sf->selector, save->base >> 4);
1719 vmcs_write32(sf->base, save->base & 0xfffff);
1720 vmcs_write32(sf->limit, 0xffff);
1721 vmcs_write32(sf->ar_bytes, 0xf3);
1724 static void enter_rmode(struct kvm_vcpu *vcpu)
1726 unsigned long flags;
1727 struct vcpu_vmx *vmx = to_vmx(vcpu);
1729 if (enable_unrestricted_guest)
1732 vmx->emulation_required = 1;
1733 vmx->rmode.vm86_active = 1;
1735 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1736 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1738 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1739 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1741 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1742 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1744 flags = vmcs_readl(GUEST_RFLAGS);
1745 vmx->rmode.save_rflags = flags;
1747 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1749 vmcs_writel(GUEST_RFLAGS, flags);
1750 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1751 update_exception_bitmap(vcpu);
1753 if (emulate_invalid_guest_state)
1754 goto continue_rmode;
1756 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1757 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1758 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1760 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1761 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1762 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1763 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1764 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1766 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1767 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1768 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1769 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1772 kvm_mmu_reset_context(vcpu);
1773 init_rmode(vcpu->kvm);
1776 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1778 struct vcpu_vmx *vmx = to_vmx(vcpu);
1779 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1785 * Force kernel_gs_base reloading before EFER changes, as control
1786 * of this msr depends on is_long_mode().
1788 vmx_load_host_state(to_vmx(vcpu));
1789 vcpu->arch.efer = efer;
1790 if (efer & EFER_LMA) {
1791 vmcs_write32(VM_ENTRY_CONTROLS,
1792 vmcs_read32(VM_ENTRY_CONTROLS) |
1793 VM_ENTRY_IA32E_MODE);
1796 vmcs_write32(VM_ENTRY_CONTROLS,
1797 vmcs_read32(VM_ENTRY_CONTROLS) &
1798 ~VM_ENTRY_IA32E_MODE);
1800 msr->data = efer & ~EFER_LME;
1805 #ifdef CONFIG_X86_64
1807 static void enter_lmode(struct kvm_vcpu *vcpu)
1811 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1812 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1813 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1815 vmcs_write32(GUEST_TR_AR_BYTES,
1816 (guest_tr_ar & ~AR_TYPE_MASK)
1817 | AR_TYPE_BUSY_64_TSS);
1819 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1822 static void exit_lmode(struct kvm_vcpu *vcpu)
1824 vmcs_write32(VM_ENTRY_CONTROLS,
1825 vmcs_read32(VM_ENTRY_CONTROLS)
1826 & ~VM_ENTRY_IA32E_MODE);
1827 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1832 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1834 vpid_sync_context(to_vmx(vcpu));
1836 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1838 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1842 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1844 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1846 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1847 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1850 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1852 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1854 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1855 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1858 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1860 if (!test_bit(VCPU_EXREG_PDPTR,
1861 (unsigned long *)&vcpu->arch.regs_dirty))
1864 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1865 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1866 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1867 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1868 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1872 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1874 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1875 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1876 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1877 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1878 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1881 __set_bit(VCPU_EXREG_PDPTR,
1882 (unsigned long *)&vcpu->arch.regs_avail);
1883 __set_bit(VCPU_EXREG_PDPTR,
1884 (unsigned long *)&vcpu->arch.regs_dirty);
1887 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1889 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1891 struct kvm_vcpu *vcpu)
1893 if (!(cr0 & X86_CR0_PG)) {
1894 /* From paging/starting to nonpaging */
1895 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1896 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1897 (CPU_BASED_CR3_LOAD_EXITING |
1898 CPU_BASED_CR3_STORE_EXITING));
1899 vcpu->arch.cr0 = cr0;
1900 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1901 } else if (!is_paging(vcpu)) {
1902 /* From nonpaging to paging */
1903 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1904 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1905 ~(CPU_BASED_CR3_LOAD_EXITING |
1906 CPU_BASED_CR3_STORE_EXITING));
1907 vcpu->arch.cr0 = cr0;
1908 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1911 if (!(cr0 & X86_CR0_WP))
1912 *hw_cr0 &= ~X86_CR0_WP;
1915 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1917 struct vcpu_vmx *vmx = to_vmx(vcpu);
1918 unsigned long hw_cr0;
1920 if (enable_unrestricted_guest)
1921 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1922 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1924 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1926 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1929 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1932 #ifdef CONFIG_X86_64
1933 if (vcpu->arch.efer & EFER_LME) {
1934 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1936 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1942 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1944 if (!vcpu->fpu_active)
1945 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1947 vmcs_writel(CR0_READ_SHADOW, cr0);
1948 vmcs_writel(GUEST_CR0, hw_cr0);
1949 vcpu->arch.cr0 = cr0;
1952 static u64 construct_eptp(unsigned long root_hpa)
1956 /* TODO write the value reading from MSR */
1957 eptp = VMX_EPT_DEFAULT_MT |
1958 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1959 eptp |= (root_hpa & PAGE_MASK);
1964 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1966 unsigned long guest_cr3;
1971 eptp = construct_eptp(cr3);
1972 vmcs_write64(EPT_POINTER, eptp);
1973 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1974 vcpu->kvm->arch.ept_identity_map_addr;
1975 ept_load_pdptrs(vcpu);
1978 vmx_flush_tlb(vcpu);
1979 vmcs_writel(GUEST_CR3, guest_cr3);
1982 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1984 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1985 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1987 vcpu->arch.cr4 = cr4;
1989 if (!is_paging(vcpu)) {
1990 hw_cr4 &= ~X86_CR4_PAE;
1991 hw_cr4 |= X86_CR4_PSE;
1992 } else if (!(cr4 & X86_CR4_PAE)) {
1993 hw_cr4 &= ~X86_CR4_PAE;
1997 vmcs_writel(CR4_READ_SHADOW, cr4);
1998 vmcs_writel(GUEST_CR4, hw_cr4);
2001 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2003 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2005 return vmcs_readl(sf->base);
2008 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2009 struct kvm_segment *var, int seg)
2011 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2014 var->base = vmcs_readl(sf->base);
2015 var->limit = vmcs_read32(sf->limit);
2016 var->selector = vmcs_read16(sf->selector);
2017 ar = vmcs_read32(sf->ar_bytes);
2018 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2020 var->type = ar & 15;
2021 var->s = (ar >> 4) & 1;
2022 var->dpl = (ar >> 5) & 3;
2023 var->present = (ar >> 7) & 1;
2024 var->avl = (ar >> 12) & 1;
2025 var->l = (ar >> 13) & 1;
2026 var->db = (ar >> 14) & 1;
2027 var->g = (ar >> 15) & 1;
2028 var->unusable = (ar >> 16) & 1;
2031 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2033 if (!is_protmode(vcpu))
2036 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2039 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2042 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2049 ar = var->type & 15;
2050 ar |= (var->s & 1) << 4;
2051 ar |= (var->dpl & 3) << 5;
2052 ar |= (var->present & 1) << 7;
2053 ar |= (var->avl & 1) << 12;
2054 ar |= (var->l & 1) << 13;
2055 ar |= (var->db & 1) << 14;
2056 ar |= (var->g & 1) << 15;
2058 if (ar == 0) /* a 0 value means unusable */
2059 ar = AR_UNUSABLE_MASK;
2064 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2065 struct kvm_segment *var, int seg)
2067 struct vcpu_vmx *vmx = to_vmx(vcpu);
2068 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2071 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2072 vmx->rmode.tr.selector = var->selector;
2073 vmx->rmode.tr.base = var->base;
2074 vmx->rmode.tr.limit = var->limit;
2075 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2078 vmcs_writel(sf->base, var->base);
2079 vmcs_write32(sf->limit, var->limit);
2080 vmcs_write16(sf->selector, var->selector);
2081 if (vmx->rmode.vm86_active && var->s) {
2083 * Hack real-mode segments into vm86 compatibility.
2085 if (var->base == 0xffff0000 && var->selector == 0xf000)
2086 vmcs_writel(sf->base, 0xf0000);
2089 ar = vmx_segment_access_rights(var);
2092 * Fix the "Accessed" bit in AR field of segment registers for older
2094 * IA32 arch specifies that at the time of processor reset the
2095 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2096 * is setting it to 0 in the usedland code. This causes invalid guest
2097 * state vmexit when "unrestricted guest" mode is turned on.
2098 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2099 * tree. Newer qemu binaries with that qemu fix would not need this
2102 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2103 ar |= 0x1; /* Accessed */
2105 vmcs_write32(sf->ar_bytes, ar);
2108 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2110 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2112 *db = (ar >> 14) & 1;
2113 *l = (ar >> 13) & 1;
2116 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2118 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2119 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2122 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2124 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2125 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2128 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2130 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2131 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2134 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2136 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2137 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2140 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2142 struct kvm_segment var;
2145 vmx_get_segment(vcpu, &var, seg);
2146 ar = vmx_segment_access_rights(&var);
2148 if (var.base != (var.selector << 4))
2150 if (var.limit != 0xffff)
2158 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2160 struct kvm_segment cs;
2161 unsigned int cs_rpl;
2163 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2164 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2168 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2172 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2173 if (cs.dpl > cs_rpl)
2176 if (cs.dpl != cs_rpl)
2182 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2186 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2188 struct kvm_segment ss;
2189 unsigned int ss_rpl;
2191 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2192 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2196 if (ss.type != 3 && ss.type != 7)
2200 if (ss.dpl != ss_rpl) /* DPL != RPL */
2208 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2210 struct kvm_segment var;
2213 vmx_get_segment(vcpu, &var, seg);
2214 rpl = var.selector & SELECTOR_RPL_MASK;
2222 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2223 if (var.dpl < rpl) /* DPL < RPL */
2227 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2233 static bool tr_valid(struct kvm_vcpu *vcpu)
2235 struct kvm_segment tr;
2237 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2241 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2243 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2251 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2253 struct kvm_segment ldtr;
2255 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2259 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2269 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2271 struct kvm_segment cs, ss;
2273 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2274 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2276 return ((cs.selector & SELECTOR_RPL_MASK) ==
2277 (ss.selector & SELECTOR_RPL_MASK));
2281 * Check if guest state is valid. Returns true if valid, false if
2283 * We assume that registers are always usable
2285 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2287 /* real mode guest state checks */
2288 if (!is_protmode(vcpu)) {
2289 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2291 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2293 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2295 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2297 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2299 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2302 /* protected mode guest state checks */
2303 if (!cs_ss_rpl_check(vcpu))
2305 if (!code_segment_valid(vcpu))
2307 if (!stack_segment_valid(vcpu))
2309 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2311 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2313 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2315 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2317 if (!tr_valid(vcpu))
2319 if (!ldtr_valid(vcpu))
2323 * - Add checks on RIP
2324 * - Add checks on RFLAGS
2330 static int init_rmode_tss(struct kvm *kvm)
2332 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2337 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2340 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2341 r = kvm_write_guest_page(kvm, fn++, &data,
2342 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2345 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2348 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2352 r = kvm_write_guest_page(kvm, fn, &data,
2353 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2363 static int init_rmode_identity_map(struct kvm *kvm)
2366 pfn_t identity_map_pfn;
2371 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2372 printk(KERN_ERR "EPT: identity-mapping pagetable "
2373 "haven't been allocated!\n");
2376 if (likely(kvm->arch.ept_identity_pagetable_done))
2379 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2380 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2383 /* Set up identity-mapping pagetable for EPT in real mode */
2384 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2385 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2386 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2387 r = kvm_write_guest_page(kvm, identity_map_pfn,
2388 &tmp, i * sizeof(tmp), sizeof(tmp));
2392 kvm->arch.ept_identity_pagetable_done = true;
2398 static void seg_setup(int seg)
2400 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2403 vmcs_write16(sf->selector, 0);
2404 vmcs_writel(sf->base, 0);
2405 vmcs_write32(sf->limit, 0xffff);
2406 if (enable_unrestricted_guest) {
2408 if (seg == VCPU_SREG_CS)
2409 ar |= 0x08; /* code segment */
2413 vmcs_write32(sf->ar_bytes, ar);
2416 static int alloc_apic_access_page(struct kvm *kvm)
2418 struct kvm_userspace_memory_region kvm_userspace_mem;
2421 mutex_lock(&kvm->slots_lock);
2422 if (kvm->arch.apic_access_page)
2424 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2425 kvm_userspace_mem.flags = 0;
2426 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2427 kvm_userspace_mem.memory_size = PAGE_SIZE;
2428 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2432 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2434 mutex_unlock(&kvm->slots_lock);
2438 static int alloc_identity_pagetable(struct kvm *kvm)
2440 struct kvm_userspace_memory_region kvm_userspace_mem;
2443 mutex_lock(&kvm->slots_lock);
2444 if (kvm->arch.ept_identity_pagetable)
2446 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2447 kvm_userspace_mem.flags = 0;
2448 kvm_userspace_mem.guest_phys_addr =
2449 kvm->arch.ept_identity_map_addr;
2450 kvm_userspace_mem.memory_size = PAGE_SIZE;
2451 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2455 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2456 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2458 mutex_unlock(&kvm->slots_lock);
2462 static void allocate_vpid(struct vcpu_vmx *vmx)
2469 spin_lock(&vmx_vpid_lock);
2470 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2471 if (vpid < VMX_NR_VPIDS) {
2473 __set_bit(vpid, vmx_vpid_bitmap);
2475 spin_unlock(&vmx_vpid_lock);
2478 static void free_vpid(struct vcpu_vmx *vmx)
2482 spin_lock(&vmx_vpid_lock);
2484 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2485 spin_unlock(&vmx_vpid_lock);
2488 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2490 int f = sizeof(unsigned long);
2492 if (!cpu_has_vmx_msr_bitmap())
2496 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2497 * have the write-low and read-high bitmap offsets the wrong way round.
2498 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2500 if (msr <= 0x1fff) {
2501 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2502 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2503 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2505 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2506 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2510 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2513 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2514 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2518 * Sets up the vmcs for emulated real mode.
2520 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2522 u32 host_sysenter_cs, msr_low, msr_high;
2524 u64 host_pat, tsc_this, tsc_base;
2528 unsigned long kvm_vmx_return;
2532 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2533 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2535 if (cpu_has_vmx_msr_bitmap())
2536 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2538 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2541 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2542 vmcs_config.pin_based_exec_ctrl);
2544 exec_control = vmcs_config.cpu_based_exec_ctrl;
2545 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2546 exec_control &= ~CPU_BASED_TPR_SHADOW;
2547 #ifdef CONFIG_X86_64
2548 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2549 CPU_BASED_CR8_LOAD_EXITING;
2553 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2554 CPU_BASED_CR3_LOAD_EXITING |
2555 CPU_BASED_INVLPG_EXITING;
2556 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2558 if (cpu_has_secondary_exec_ctrls()) {
2559 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2560 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2562 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2564 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2566 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2567 enable_unrestricted_guest = 0;
2569 if (!enable_unrestricted_guest)
2570 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2572 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2573 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2577 vmcs_write32(PLE_GAP, ple_gap);
2578 vmcs_write32(PLE_WINDOW, ple_window);
2581 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2582 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2583 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2585 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2586 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2587 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2589 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2590 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2591 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2592 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2593 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2594 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2595 #ifdef CONFIG_X86_64
2596 rdmsrl(MSR_FS_BASE, a);
2597 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2598 rdmsrl(MSR_GS_BASE, a);
2599 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2601 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2602 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2605 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2607 native_store_idt(&dt);
2608 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2610 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2611 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2612 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2613 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2614 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2615 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2616 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2618 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2619 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2620 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2621 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2622 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2623 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2625 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2626 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2627 host_pat = msr_low | ((u64) msr_high << 32);
2628 vmcs_write64(HOST_IA32_PAT, host_pat);
2630 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2631 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2632 host_pat = msr_low | ((u64) msr_high << 32);
2633 /* Write the default value follow host pat */
2634 vmcs_write64(GUEST_IA32_PAT, host_pat);
2635 /* Keep arch.pat sync with GUEST_IA32_PAT */
2636 vmx->vcpu.arch.pat = host_pat;
2639 for (i = 0; i < NR_VMX_MSR; ++i) {
2640 u32 index = vmx_msr_index[i];
2641 u32 data_low, data_high;
2644 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2646 if (wrmsr_safe(index, data_low, data_high) < 0)
2648 vmx->guest_msrs[j].index = i;
2649 vmx->guest_msrs[j].data = 0;
2650 vmx->guest_msrs[j].mask = -1ull;
2654 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2656 /* 22.2.1, 20.8.1 */
2657 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2659 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2660 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2662 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2663 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2665 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2667 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2668 tsc_base = tsc_this;
2670 guest_write_tsc(0, tsc_base);
2675 static int init_rmode(struct kvm *kvm)
2679 idx = srcu_read_lock(&kvm->srcu);
2680 if (!init_rmode_tss(kvm))
2682 if (!init_rmode_identity_map(kvm))
2687 srcu_read_unlock(&kvm->srcu, idx);
2691 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2693 struct vcpu_vmx *vmx = to_vmx(vcpu);
2697 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2698 if (!init_rmode(vmx->vcpu.kvm)) {
2703 vmx->rmode.vm86_active = 0;
2705 vmx->soft_vnmi_blocked = 0;
2707 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2708 kvm_set_cr8(&vmx->vcpu, 0);
2709 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2710 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2711 msr |= MSR_IA32_APICBASE_BSP;
2712 kvm_set_apic_base(&vmx->vcpu, msr);
2714 ret = fx_init(&vmx->vcpu);
2718 seg_setup(VCPU_SREG_CS);
2720 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2721 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2723 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2724 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2725 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2727 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2728 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2731 seg_setup(VCPU_SREG_DS);
2732 seg_setup(VCPU_SREG_ES);
2733 seg_setup(VCPU_SREG_FS);
2734 seg_setup(VCPU_SREG_GS);
2735 seg_setup(VCPU_SREG_SS);
2737 vmcs_write16(GUEST_TR_SELECTOR, 0);
2738 vmcs_writel(GUEST_TR_BASE, 0);
2739 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2740 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2742 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2743 vmcs_writel(GUEST_LDTR_BASE, 0);
2744 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2745 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2747 vmcs_write32(GUEST_SYSENTER_CS, 0);
2748 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2749 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2751 vmcs_writel(GUEST_RFLAGS, 0x02);
2752 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2753 kvm_rip_write(vcpu, 0xfff0);
2755 kvm_rip_write(vcpu, 0);
2756 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2758 vmcs_writel(GUEST_DR7, 0x400);
2760 vmcs_writel(GUEST_GDTR_BASE, 0);
2761 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2763 vmcs_writel(GUEST_IDTR_BASE, 0);
2764 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2766 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2767 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2768 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2770 /* Special registers */
2771 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2775 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2777 if (cpu_has_vmx_tpr_shadow()) {
2778 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2779 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2780 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2781 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2782 vmcs_write32(TPR_THRESHOLD, 0);
2785 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2786 vmcs_write64(APIC_ACCESS_ADDR,
2787 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2790 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2792 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2793 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2794 vmx_set_cr4(&vmx->vcpu, 0);
2795 vmx_set_efer(&vmx->vcpu, 0);
2796 vmx_fpu_activate(&vmx->vcpu);
2797 update_exception_bitmap(&vmx->vcpu);
2799 vpid_sync_context(vmx);
2803 /* HACK: Don't enable emulation on guest boot/reset */
2804 vmx->emulation_required = 0;
2810 static void enable_irq_window(struct kvm_vcpu *vcpu)
2812 u32 cpu_based_vm_exec_control;
2814 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2815 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2816 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2819 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2821 u32 cpu_based_vm_exec_control;
2823 if (!cpu_has_virtual_nmis()) {
2824 enable_irq_window(vcpu);
2828 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2829 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2830 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2833 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2835 struct vcpu_vmx *vmx = to_vmx(vcpu);
2837 int irq = vcpu->arch.interrupt.nr;
2839 trace_kvm_inj_virq(irq);
2841 ++vcpu->stat.irq_injections;
2842 if (vmx->rmode.vm86_active) {
2843 vmx->rmode.irq.pending = true;
2844 vmx->rmode.irq.vector = irq;
2845 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2846 if (vcpu->arch.interrupt.soft)
2847 vmx->rmode.irq.rip +=
2848 vmx->vcpu.arch.event_exit_inst_len;
2849 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2850 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2851 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2852 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2855 intr = irq | INTR_INFO_VALID_MASK;
2856 if (vcpu->arch.interrupt.soft) {
2857 intr |= INTR_TYPE_SOFT_INTR;
2858 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2859 vmx->vcpu.arch.event_exit_inst_len);
2861 intr |= INTR_TYPE_EXT_INTR;
2862 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2865 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2867 struct vcpu_vmx *vmx = to_vmx(vcpu);
2869 if (!cpu_has_virtual_nmis()) {
2871 * Tracking the NMI-blocked state in software is built upon
2872 * finding the next open IRQ window. This, in turn, depends on
2873 * well-behaving guests: They have to keep IRQs disabled at
2874 * least as long as the NMI handler runs. Otherwise we may
2875 * cause NMI nesting, maybe breaking the guest. But as this is
2876 * highly unlikely, we can live with the residual risk.
2878 vmx->soft_vnmi_blocked = 1;
2879 vmx->vnmi_blocked_time = 0;
2882 ++vcpu->stat.nmi_injections;
2883 if (vmx->rmode.vm86_active) {
2884 vmx->rmode.irq.pending = true;
2885 vmx->rmode.irq.vector = NMI_VECTOR;
2886 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2887 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2888 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2889 INTR_INFO_VALID_MASK);
2890 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2891 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2894 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2895 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2898 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2900 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2903 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2904 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2907 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2909 if (!cpu_has_virtual_nmis())
2910 return to_vmx(vcpu)->soft_vnmi_blocked;
2911 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2914 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2916 struct vcpu_vmx *vmx = to_vmx(vcpu);
2918 if (!cpu_has_virtual_nmis()) {
2919 if (vmx->soft_vnmi_blocked != masked) {
2920 vmx->soft_vnmi_blocked = masked;
2921 vmx->vnmi_blocked_time = 0;
2925 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2926 GUEST_INTR_STATE_NMI);
2928 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2929 GUEST_INTR_STATE_NMI);
2933 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2935 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2936 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2937 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2940 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2943 struct kvm_userspace_memory_region tss_mem = {
2944 .slot = TSS_PRIVATE_MEMSLOT,
2945 .guest_phys_addr = addr,
2946 .memory_size = PAGE_SIZE * 3,
2950 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2953 kvm->arch.tss_addr = addr;
2957 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2958 int vec, u32 err_code)
2961 * Instruction with address size override prefix opcode 0x67
2962 * Cause the #SS fault with 0 error code in VM86 mode.
2964 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2965 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2968 * Forward all other exceptions that are valid in real mode.
2969 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2970 * the required debugging infrastructure rework.
2974 if (vcpu->guest_debug &
2975 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2977 kvm_queue_exception(vcpu, vec);
2981 * Update instruction length as we may reinject the exception
2982 * from user space while in guest debugging mode.
2984 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2985 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2997 kvm_queue_exception(vcpu, vec);
3004 * Trigger machine check on the host. We assume all the MSRs are already set up
3005 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3006 * We pass a fake environment to the machine check handler because we want
3007 * the guest to be always treated like user space, no matter what context
3008 * it used internally.
3010 static void kvm_machine_check(void)
3012 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3013 struct pt_regs regs = {
3014 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3015 .flags = X86_EFLAGS_IF,
3018 do_machine_check(®s, 0);
3022 static int handle_machine_check(struct kvm_vcpu *vcpu)
3024 /* already handled by vcpu_run */
3028 static int handle_exception(struct kvm_vcpu *vcpu)
3030 struct vcpu_vmx *vmx = to_vmx(vcpu);
3031 struct kvm_run *kvm_run = vcpu->run;
3032 u32 intr_info, ex_no, error_code;
3033 unsigned long cr2, rip, dr6;
3035 enum emulation_result er;
3037 vect_info = vmx->idt_vectoring_info;
3038 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3040 if (is_machine_check(intr_info))
3041 return handle_machine_check(vcpu);
3043 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3044 !is_page_fault(intr_info)) {
3045 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3046 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3047 vcpu->run->internal.ndata = 2;
3048 vcpu->run->internal.data[0] = vect_info;
3049 vcpu->run->internal.data[1] = intr_info;
3053 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3054 return 1; /* already handled by vmx_vcpu_run() */
3056 if (is_no_device(intr_info)) {
3057 vmx_fpu_activate(vcpu);
3061 if (is_invalid_opcode(intr_info)) {
3062 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3063 if (er != EMULATE_DONE)
3064 kvm_queue_exception(vcpu, UD_VECTOR);
3069 rip = kvm_rip_read(vcpu);
3070 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3071 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3072 if (is_page_fault(intr_info)) {
3073 /* EPT won't cause page fault directly */
3076 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3077 trace_kvm_page_fault(cr2, error_code);
3079 if (kvm_event_needs_reinjection(vcpu))
3080 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3081 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3084 if (vmx->rmode.vm86_active &&
3085 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3087 if (vcpu->arch.halt_request) {
3088 vcpu->arch.halt_request = 0;
3089 return kvm_emulate_halt(vcpu);
3094 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3097 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3098 if (!(vcpu->guest_debug &
3099 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3100 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3101 kvm_queue_exception(vcpu, DB_VECTOR);
3104 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3105 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3109 * Update instruction length as we may reinject #BP from
3110 * user space while in guest debugging mode. Reading it for
3111 * #DB as well causes no harm, it is not used in that case.
3113 vmx->vcpu.arch.event_exit_inst_len =
3114 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3115 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3116 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3117 kvm_run->debug.arch.exception = ex_no;
3120 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3121 kvm_run->ex.exception = ex_no;
3122 kvm_run->ex.error_code = error_code;
3128 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3130 ++vcpu->stat.irq_exits;
3134 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3136 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3140 static int handle_io(struct kvm_vcpu *vcpu)
3142 unsigned long exit_qualification;
3143 int size, in, string;
3146 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3147 string = (exit_qualification & 16) != 0;
3148 in = (exit_qualification & 8) != 0;
3150 ++vcpu->stat.io_exits;
3153 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3155 port = exit_qualification >> 16;
3156 size = (exit_qualification & 7) + 1;
3157 skip_emulated_instruction(vcpu);
3159 return kvm_fast_pio_out(vcpu, size, port);
3163 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3166 * Patch in the VMCALL instruction:
3168 hypercall[0] = 0x0f;
3169 hypercall[1] = 0x01;
3170 hypercall[2] = 0xc1;
3173 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3176 kvm_inject_gp(vcpu, 0);
3178 skip_emulated_instruction(vcpu);
3181 static int handle_cr(struct kvm_vcpu *vcpu)
3183 unsigned long exit_qualification, val;
3188 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3189 cr = exit_qualification & 15;
3190 reg = (exit_qualification >> 8) & 15;
3191 switch ((exit_qualification >> 4) & 3) {
3192 case 0: /* mov to cr */
3193 val = kvm_register_read(vcpu, reg);
3194 trace_kvm_cr_write(cr, val);
3197 err = kvm_set_cr0(vcpu, val);
3198 complete_insn_gp(vcpu, err);
3201 err = kvm_set_cr3(vcpu, val);
3202 complete_insn_gp(vcpu, err);
3205 err = kvm_set_cr4(vcpu, val);
3206 complete_insn_gp(vcpu, err);
3209 u8 cr8_prev = kvm_get_cr8(vcpu);
3210 u8 cr8 = kvm_register_read(vcpu, reg);
3211 kvm_set_cr8(vcpu, cr8);
3212 skip_emulated_instruction(vcpu);
3213 if (irqchip_in_kernel(vcpu->kvm))
3215 if (cr8_prev <= cr8)
3217 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3223 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3224 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3225 skip_emulated_instruction(vcpu);
3226 vmx_fpu_activate(vcpu);
3228 case 1: /*mov from cr*/
3231 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3232 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3233 skip_emulated_instruction(vcpu);
3236 val = kvm_get_cr8(vcpu);
3237 kvm_register_write(vcpu, reg, val);
3238 trace_kvm_cr_read(cr, val);
3239 skip_emulated_instruction(vcpu);
3244 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3245 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3246 kvm_lmsw(vcpu, val);
3248 skip_emulated_instruction(vcpu);
3253 vcpu->run->exit_reason = 0;
3254 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3255 (int)(exit_qualification >> 4) & 3, cr);
3259 static int handle_dr(struct kvm_vcpu *vcpu)
3261 unsigned long exit_qualification;
3264 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3265 if (!kvm_require_cpl(vcpu, 0))
3267 dr = vmcs_readl(GUEST_DR7);
3270 * As the vm-exit takes precedence over the debug trap, we
3271 * need to emulate the latter, either for the host or the
3272 * guest debugging itself.
3274 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3275 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3276 vcpu->run->debug.arch.dr7 = dr;
3277 vcpu->run->debug.arch.pc =
3278 vmcs_readl(GUEST_CS_BASE) +
3279 vmcs_readl(GUEST_RIP);
3280 vcpu->run->debug.arch.exception = DB_VECTOR;
3281 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3284 vcpu->arch.dr7 &= ~DR7_GD;
3285 vcpu->arch.dr6 |= DR6_BD;
3286 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3287 kvm_queue_exception(vcpu, DB_VECTOR);
3292 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3293 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3294 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3295 if (exit_qualification & TYPE_MOV_FROM_DR) {
3297 if (!kvm_get_dr(vcpu, dr, &val))
3298 kvm_register_write(vcpu, reg, val);
3300 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3301 skip_emulated_instruction(vcpu);
3305 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3307 vmcs_writel(GUEST_DR7, val);
3310 static int handle_cpuid(struct kvm_vcpu *vcpu)
3312 kvm_emulate_cpuid(vcpu);
3316 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3318 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3321 if (vmx_get_msr(vcpu, ecx, &data)) {
3322 trace_kvm_msr_read_ex(ecx);
3323 kvm_inject_gp(vcpu, 0);
3327 trace_kvm_msr_read(ecx, data);
3329 /* FIXME: handling of bits 32:63 of rax, rdx */
3330 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3331 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3332 skip_emulated_instruction(vcpu);
3336 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3338 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3339 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3340 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3342 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3343 trace_kvm_msr_write_ex(ecx, data);
3344 kvm_inject_gp(vcpu, 0);
3348 trace_kvm_msr_write(ecx, data);
3349 skip_emulated_instruction(vcpu);
3353 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3358 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3360 u32 cpu_based_vm_exec_control;
3362 /* clear pending irq */
3363 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3364 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3365 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3367 ++vcpu->stat.irq_window_exits;
3370 * If the user space waits to inject interrupts, exit as soon as
3373 if (!irqchip_in_kernel(vcpu->kvm) &&
3374 vcpu->run->request_interrupt_window &&
3375 !kvm_cpu_has_interrupt(vcpu)) {
3376 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3382 static int handle_halt(struct kvm_vcpu *vcpu)
3384 skip_emulated_instruction(vcpu);
3385 return kvm_emulate_halt(vcpu);
3388 static int handle_vmcall(struct kvm_vcpu *vcpu)
3390 skip_emulated_instruction(vcpu);
3391 kvm_emulate_hypercall(vcpu);
3395 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3397 kvm_queue_exception(vcpu, UD_VECTOR);
3401 static int handle_invlpg(struct kvm_vcpu *vcpu)
3403 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3405 kvm_mmu_invlpg(vcpu, exit_qualification);
3406 skip_emulated_instruction(vcpu);
3410 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3412 skip_emulated_instruction(vcpu);
3413 kvm_emulate_wbinvd(vcpu);
3417 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3419 u64 new_bv = kvm_read_edx_eax(vcpu);
3420 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3422 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3423 skip_emulated_instruction(vcpu);
3427 static int handle_apic_access(struct kvm_vcpu *vcpu)
3429 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3432 static int handle_task_switch(struct kvm_vcpu *vcpu)
3434 struct vcpu_vmx *vmx = to_vmx(vcpu);
3435 unsigned long exit_qualification;
3436 bool has_error_code = false;
3439 int reason, type, idt_v;
3441 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3442 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3444 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3446 reason = (u32)exit_qualification >> 30;
3447 if (reason == TASK_SWITCH_GATE && idt_v) {
3449 case INTR_TYPE_NMI_INTR:
3450 vcpu->arch.nmi_injected = false;
3451 if (cpu_has_virtual_nmis())
3452 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3453 GUEST_INTR_STATE_NMI);
3455 case INTR_TYPE_EXT_INTR:
3456 case INTR_TYPE_SOFT_INTR:
3457 kvm_clear_interrupt_queue(vcpu);
3459 case INTR_TYPE_HARD_EXCEPTION:
3460 if (vmx->idt_vectoring_info &
3461 VECTORING_INFO_DELIVER_CODE_MASK) {
3462 has_error_code = true;
3464 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3467 case INTR_TYPE_SOFT_EXCEPTION:
3468 kvm_clear_exception_queue(vcpu);
3474 tss_selector = exit_qualification;
3476 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3477 type != INTR_TYPE_EXT_INTR &&
3478 type != INTR_TYPE_NMI_INTR))
3479 skip_emulated_instruction(vcpu);
3481 if (kvm_task_switch(vcpu, tss_selector, reason,
3482 has_error_code, error_code) == EMULATE_FAIL) {
3483 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3484 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3485 vcpu->run->internal.ndata = 0;
3489 /* clear all local breakpoint enable flags */
3490 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3493 * TODO: What about debug traps on tss switch?
3494 * Are we supposed to inject them and update dr6?
3500 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3502 unsigned long exit_qualification;
3506 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3508 if (exit_qualification & (1 << 6)) {
3509 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3513 gla_validity = (exit_qualification >> 7) & 0x3;
3514 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3515 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3516 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3517 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3518 vmcs_readl(GUEST_LINEAR_ADDRESS));
3519 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3520 (long unsigned int)exit_qualification);
3521 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3522 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3526 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3527 trace_kvm_page_fault(gpa, exit_qualification);
3528 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3531 static u64 ept_rsvd_mask(u64 spte, int level)
3536 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3537 mask |= (1ULL << i);
3540 /* bits 7:3 reserved */
3542 else if (level == 2) {
3543 if (spte & (1ULL << 7))
3544 /* 2MB ref, bits 20:12 reserved */
3547 /* bits 6:3 reserved */
3554 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3557 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3559 /* 010b (write-only) */
3560 WARN_ON((spte & 0x7) == 0x2);
3562 /* 110b (write/execute) */
3563 WARN_ON((spte & 0x7) == 0x6);
3565 /* 100b (execute-only) and value not supported by logical processor */
3566 if (!cpu_has_vmx_ept_execute_only())
3567 WARN_ON((spte & 0x7) == 0x4);
3571 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3573 if (rsvd_bits != 0) {
3574 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3575 __func__, rsvd_bits);
3579 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3580 u64 ept_mem_type = (spte & 0x38) >> 3;
3582 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3583 ept_mem_type == 7) {
3584 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3585 __func__, ept_mem_type);
3592 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3598 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3600 printk(KERN_ERR "EPT: Misconfiguration.\n");
3601 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3603 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3605 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3606 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3608 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3609 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3614 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3616 u32 cpu_based_vm_exec_control;
3618 /* clear pending NMI */
3619 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3620 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3621 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3622 ++vcpu->stat.nmi_window_exits;
3627 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3629 struct vcpu_vmx *vmx = to_vmx(vcpu);
3630 enum emulation_result err = EMULATE_DONE;
3633 while (!guest_state_valid(vcpu)) {
3634 err = emulate_instruction(vcpu, 0, 0, 0);
3636 if (err == EMULATE_DO_MMIO) {
3641 if (err != EMULATE_DONE)
3644 if (signal_pending(current))
3650 vmx->emulation_required = 0;
3656 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3657 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3659 static int handle_pause(struct kvm_vcpu *vcpu)
3661 skip_emulated_instruction(vcpu);
3662 kvm_vcpu_on_spin(vcpu);
3667 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3669 kvm_queue_exception(vcpu, UD_VECTOR);
3674 * The exit handlers return 1 if the exit was handled fully and guest execution
3675 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3676 * to be done to userspace and return 0.
3678 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3679 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3680 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3681 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3682 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3683 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3684 [EXIT_REASON_CR_ACCESS] = handle_cr,
3685 [EXIT_REASON_DR_ACCESS] = handle_dr,
3686 [EXIT_REASON_CPUID] = handle_cpuid,
3687 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3688 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3689 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3690 [EXIT_REASON_HLT] = handle_halt,
3691 [EXIT_REASON_INVLPG] = handle_invlpg,
3692 [EXIT_REASON_VMCALL] = handle_vmcall,
3693 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3694 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3695 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3696 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3697 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3698 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3699 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3700 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3701 [EXIT_REASON_VMON] = handle_vmx_insn,
3702 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3703 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3704 [EXIT_REASON_WBINVD] = handle_wbinvd,
3705 [EXIT_REASON_XSETBV] = handle_xsetbv,
3706 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3707 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3708 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3709 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3710 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3711 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3712 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3715 static const int kvm_vmx_max_exit_handlers =
3716 ARRAY_SIZE(kvm_vmx_exit_handlers);
3719 * The guest has exited. See if we can fix it or if we need userspace
3722 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3725 u32 exit_reason = vmx->exit_reason;
3726 u32 vectoring_info = vmx->idt_vectoring_info;
3728 trace_kvm_exit(exit_reason, vcpu);
3730 /* If guest state is invalid, start emulating */
3731 if (vmx->emulation_required && emulate_invalid_guest_state)
3732 return handle_invalid_guest_state(vcpu);
3734 /* Access CR3 don't cause VMExit in paging mode, so we need
3735 * to sync with guest real CR3. */
3736 if (enable_ept && is_paging(vcpu))
3737 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3739 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3740 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3741 vcpu->run->fail_entry.hardware_entry_failure_reason
3746 if (unlikely(vmx->fail)) {
3747 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3748 vcpu->run->fail_entry.hardware_entry_failure_reason
3749 = vmcs_read32(VM_INSTRUCTION_ERROR);
3753 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3754 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3755 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3756 exit_reason != EXIT_REASON_TASK_SWITCH))
3757 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3758 "(0x%x) and exit reason is 0x%x\n",
3759 __func__, vectoring_info, exit_reason);
3761 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3762 if (vmx_interrupt_allowed(vcpu)) {
3763 vmx->soft_vnmi_blocked = 0;
3764 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3765 vcpu->arch.nmi_pending) {
3767 * This CPU don't support us in finding the end of an
3768 * NMI-blocked window if the guest runs with IRQs
3769 * disabled. So we pull the trigger after 1 s of
3770 * futile waiting, but inform the user about this.
3772 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3773 "state on VCPU %d after 1 s timeout\n",
3774 __func__, vcpu->vcpu_id);
3775 vmx->soft_vnmi_blocked = 0;
3779 if (exit_reason < kvm_vmx_max_exit_handlers
3780 && kvm_vmx_exit_handlers[exit_reason])
3781 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3783 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3784 vcpu->run->hw.hardware_exit_reason = exit_reason;
3789 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3791 if (irr == -1 || tpr < irr) {
3792 vmcs_write32(TPR_THRESHOLD, 0);
3796 vmcs_write32(TPR_THRESHOLD, irr);
3799 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3802 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3806 bool idtv_info_valid;
3808 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3810 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3812 /* Handle machine checks before interrupts are enabled */
3813 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3814 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3815 && is_machine_check(exit_intr_info)))
3816 kvm_machine_check();
3818 /* We need to handle NMIs before interrupts are enabled */
3819 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3820 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3821 kvm_before_handle_nmi(&vmx->vcpu);
3823 kvm_after_handle_nmi(&vmx->vcpu);
3826 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3828 if (cpu_has_virtual_nmis()) {
3829 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3830 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3832 * SDM 3: 27.7.1.2 (September 2008)
3833 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3834 * a guest IRET fault.
3835 * SDM 3: 23.2.2 (September 2008)
3836 * Bit 12 is undefined in any of the following cases:
3837 * If the VM exit sets the valid bit in the IDT-vectoring
3838 * information field.
3839 * If the VM exit is due to a double fault.
3841 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3842 vector != DF_VECTOR && !idtv_info_valid)
3843 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3844 GUEST_INTR_STATE_NMI);
3845 } else if (unlikely(vmx->soft_vnmi_blocked))
3846 vmx->vnmi_blocked_time +=
3847 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3849 vmx->vcpu.arch.nmi_injected = false;
3850 kvm_clear_exception_queue(&vmx->vcpu);
3851 kvm_clear_interrupt_queue(&vmx->vcpu);
3853 if (!idtv_info_valid)
3856 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3857 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3860 case INTR_TYPE_NMI_INTR:
3861 vmx->vcpu.arch.nmi_injected = true;
3863 * SDM 3: 27.7.1.2 (September 2008)
3864 * Clear bit "block by NMI" before VM entry if a NMI
3867 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3868 GUEST_INTR_STATE_NMI);
3870 case INTR_TYPE_SOFT_EXCEPTION:
3871 vmx->vcpu.arch.event_exit_inst_len =
3872 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3874 case INTR_TYPE_HARD_EXCEPTION:
3875 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3876 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3877 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3879 kvm_queue_exception(&vmx->vcpu, vector);
3881 case INTR_TYPE_SOFT_INTR:
3882 vmx->vcpu.arch.event_exit_inst_len =
3883 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3885 case INTR_TYPE_EXT_INTR:
3886 kvm_queue_interrupt(&vmx->vcpu, vector,
3887 type == INTR_TYPE_SOFT_INTR);
3895 * Failure to inject an interrupt should give us the information
3896 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3897 * when fetching the interrupt redirection bitmap in the real-mode
3898 * tss, this doesn't happen. So we do it ourselves.
3900 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3902 vmx->rmode.irq.pending = 0;
3903 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3905 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3906 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3907 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3908 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3911 vmx->idt_vectoring_info =
3912 VECTORING_INFO_VALID_MASK
3913 | INTR_TYPE_EXT_INTR
3914 | vmx->rmode.irq.vector;
3917 #ifdef CONFIG_X86_64
3925 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3927 struct vcpu_vmx *vmx = to_vmx(vcpu);
3929 /* Record the guest's net vcpu time for enforced NMI injections. */
3930 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3931 vmx->entry_time = ktime_get();
3933 /* Don't enter VMX if guest state is invalid, let the exit handler
3934 start emulation until we arrive back to a valid state */
3935 if (vmx->emulation_required && emulate_invalid_guest_state)
3938 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3939 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3940 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3941 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3943 /* When single-stepping over STI and MOV SS, we must clear the
3944 * corresponding interruptibility bits in the guest state. Otherwise
3945 * vmentry fails as it then expects bit 14 (BS) in pending debug
3946 * exceptions being set, but that's not correct for the guest debugging
3948 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3949 vmx_set_interrupt_shadow(vcpu, 0);
3952 /* Store host registers */
3953 "push %%"R"dx; push %%"R"bp;"
3955 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3957 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3958 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3960 /* Reload cr2 if changed */
3961 "mov %c[cr2](%0), %%"R"ax \n\t"
3962 "mov %%cr2, %%"R"dx \n\t"
3963 "cmp %%"R"ax, %%"R"dx \n\t"
3965 "mov %%"R"ax, %%cr2 \n\t"
3967 /* Check if vmlaunch of vmresume is needed */
3968 "cmpl $0, %c[launched](%0) \n\t"
3969 /* Load guest registers. Don't clobber flags. */
3970 "mov %c[rax](%0), %%"R"ax \n\t"
3971 "mov %c[rbx](%0), %%"R"bx \n\t"
3972 "mov %c[rdx](%0), %%"R"dx \n\t"
3973 "mov %c[rsi](%0), %%"R"si \n\t"
3974 "mov %c[rdi](%0), %%"R"di \n\t"
3975 "mov %c[rbp](%0), %%"R"bp \n\t"
3976 #ifdef CONFIG_X86_64
3977 "mov %c[r8](%0), %%r8 \n\t"
3978 "mov %c[r9](%0), %%r9 \n\t"
3979 "mov %c[r10](%0), %%r10 \n\t"
3980 "mov %c[r11](%0), %%r11 \n\t"
3981 "mov %c[r12](%0), %%r12 \n\t"
3982 "mov %c[r13](%0), %%r13 \n\t"
3983 "mov %c[r14](%0), %%r14 \n\t"
3984 "mov %c[r15](%0), %%r15 \n\t"
3986 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3988 /* Enter guest mode */
3989 "jne .Llaunched \n\t"
3990 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3991 "jmp .Lkvm_vmx_return \n\t"
3992 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3993 ".Lkvm_vmx_return: "
3994 /* Save guest registers, load host registers, keep flags */
3995 "xchg %0, (%%"R"sp) \n\t"
3996 "mov %%"R"ax, %c[rax](%0) \n\t"
3997 "mov %%"R"bx, %c[rbx](%0) \n\t"
3998 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3999 "mov %%"R"dx, %c[rdx](%0) \n\t"
4000 "mov %%"R"si, %c[rsi](%0) \n\t"
4001 "mov %%"R"di, %c[rdi](%0) \n\t"
4002 "mov %%"R"bp, %c[rbp](%0) \n\t"
4003 #ifdef CONFIG_X86_64
4004 "mov %%r8, %c[r8](%0) \n\t"
4005 "mov %%r9, %c[r9](%0) \n\t"
4006 "mov %%r10, %c[r10](%0) \n\t"
4007 "mov %%r11, %c[r11](%0) \n\t"
4008 "mov %%r12, %c[r12](%0) \n\t"
4009 "mov %%r13, %c[r13](%0) \n\t"
4010 "mov %%r14, %c[r14](%0) \n\t"
4011 "mov %%r15, %c[r15](%0) \n\t"
4013 "mov %%cr2, %%"R"ax \n\t"
4014 "mov %%"R"ax, %c[cr2](%0) \n\t"
4016 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
4017 "setbe %c[fail](%0) \n\t"
4018 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4019 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4020 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4021 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4022 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4023 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4024 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4025 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4026 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4027 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4028 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4029 #ifdef CONFIG_X86_64
4030 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4031 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4032 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4033 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4034 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4035 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4036 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4037 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4039 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4041 , R"bx", R"di", R"si"
4042 #ifdef CONFIG_X86_64
4043 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4047 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4048 | (1 << VCPU_EXREG_PDPTR));
4049 vcpu->arch.regs_dirty = 0;
4051 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4052 if (vmx->rmode.irq.pending)
4053 fixup_rmode_irq(vmx);
4055 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4058 vmx_complete_interrupts(vmx);
4064 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4066 struct vcpu_vmx *vmx = to_vmx(vcpu);
4070 free_vmcs(vmx->vmcs);
4075 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4077 struct vcpu_vmx *vmx = to_vmx(vcpu);
4080 vmx_free_vmcs(vcpu);
4081 kfree(vmx->guest_msrs);
4082 kvm_vcpu_uninit(vcpu);
4083 kmem_cache_free(kvm_vcpu_cache, vmx);
4086 static inline void vmcs_init(struct vmcs *vmcs)
4088 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4091 kvm_cpu_vmxon(phys_addr);
4099 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4102 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4106 return ERR_PTR(-ENOMEM);
4110 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4114 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4115 if (!vmx->guest_msrs) {
4120 vmx->vmcs = alloc_vmcs();
4124 vmcs_init(vmx->vmcs);
4127 vmx_vcpu_load(&vmx->vcpu, cpu);
4128 err = vmx_vcpu_setup(vmx);
4129 vmx_vcpu_put(&vmx->vcpu);
4133 if (vm_need_virtualize_apic_accesses(kvm))
4134 if (alloc_apic_access_page(kvm) != 0)
4138 if (!kvm->arch.ept_identity_map_addr)
4139 kvm->arch.ept_identity_map_addr =
4140 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4141 if (alloc_identity_pagetable(kvm) != 0)
4148 free_vmcs(vmx->vmcs);
4150 kfree(vmx->guest_msrs);
4152 kvm_vcpu_uninit(&vmx->vcpu);
4155 kmem_cache_free(kvm_vcpu_cache, vmx);
4156 return ERR_PTR(err);
4159 static void __init vmx_check_processor_compat(void *rtn)
4161 struct vmcs_config vmcs_conf;
4164 if (setup_vmcs_config(&vmcs_conf) < 0)
4166 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4167 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4168 smp_processor_id());
4173 static int get_ept_level(void)
4175 return VMX_EPT_DEFAULT_GAW + 1;
4178 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4182 /* For VT-d and EPT combination
4183 * 1. MMIO: always map as UC
4185 * a. VT-d without snooping control feature: can't guarantee the
4186 * result, try to trust guest.
4187 * b. VT-d with snooping control feature: snooping control feature of
4188 * VT-d engine can guarantee the cache correctness. Just set it
4189 * to WB to keep consistent with host. So the same as item 3.
4190 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4191 * consistent with host MTRR
4194 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4195 else if (vcpu->kvm->arch.iommu_domain &&
4196 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4197 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4198 VMX_EPT_MT_EPTE_SHIFT;
4200 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4206 #define _ER(x) { EXIT_REASON_##x, #x }
4208 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4210 _ER(EXTERNAL_INTERRUPT),
4212 _ER(PENDING_INTERRUPT),
4232 _ER(IO_INSTRUCTION),
4235 _ER(MWAIT_INSTRUCTION),
4236 _ER(MONITOR_INSTRUCTION),
4237 _ER(PAUSE_INSTRUCTION),
4238 _ER(MCE_DURING_VMENTRY),
4239 _ER(TPR_BELOW_THRESHOLD),
4249 static int vmx_get_lpage_level(void)
4251 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4252 return PT_DIRECTORY_LEVEL;
4254 /* For shadow and EPT supported 1GB page */
4255 return PT_PDPE_LEVEL;
4258 static inline u32 bit(int bitno)
4260 return 1 << (bitno & 31);
4263 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4265 struct kvm_cpuid_entry2 *best;
4266 struct vcpu_vmx *vmx = to_vmx(vcpu);
4269 vmx->rdtscp_enabled = false;
4270 if (vmx_rdtscp_supported()) {
4271 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4272 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4273 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4274 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4275 vmx->rdtscp_enabled = true;
4277 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4278 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4285 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4289 static struct kvm_x86_ops vmx_x86_ops = {
4290 .cpu_has_kvm_support = cpu_has_kvm_support,
4291 .disabled_by_bios = vmx_disabled_by_bios,
4292 .hardware_setup = hardware_setup,
4293 .hardware_unsetup = hardware_unsetup,
4294 .check_processor_compatibility = vmx_check_processor_compat,
4295 .hardware_enable = hardware_enable,
4296 .hardware_disable = hardware_disable,
4297 .cpu_has_accelerated_tpr = report_flexpriority,
4299 .vcpu_create = vmx_create_vcpu,
4300 .vcpu_free = vmx_free_vcpu,
4301 .vcpu_reset = vmx_vcpu_reset,
4303 .prepare_guest_switch = vmx_save_host_state,
4304 .vcpu_load = vmx_vcpu_load,
4305 .vcpu_put = vmx_vcpu_put,
4307 .set_guest_debug = set_guest_debug,
4308 .get_msr = vmx_get_msr,
4309 .set_msr = vmx_set_msr,
4310 .get_segment_base = vmx_get_segment_base,
4311 .get_segment = vmx_get_segment,
4312 .set_segment = vmx_set_segment,
4313 .get_cpl = vmx_get_cpl,
4314 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4315 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4316 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4317 .set_cr0 = vmx_set_cr0,
4318 .set_cr3 = vmx_set_cr3,
4319 .set_cr4 = vmx_set_cr4,
4320 .set_efer = vmx_set_efer,
4321 .get_idt = vmx_get_idt,
4322 .set_idt = vmx_set_idt,
4323 .get_gdt = vmx_get_gdt,
4324 .set_gdt = vmx_set_gdt,
4325 .set_dr7 = vmx_set_dr7,
4326 .cache_reg = vmx_cache_reg,
4327 .get_rflags = vmx_get_rflags,
4328 .set_rflags = vmx_set_rflags,
4329 .fpu_activate = vmx_fpu_activate,
4330 .fpu_deactivate = vmx_fpu_deactivate,
4332 .tlb_flush = vmx_flush_tlb,
4334 .run = vmx_vcpu_run,
4335 .handle_exit = vmx_handle_exit,
4336 .skip_emulated_instruction = skip_emulated_instruction,
4337 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4338 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4339 .patch_hypercall = vmx_patch_hypercall,
4340 .set_irq = vmx_inject_irq,
4341 .set_nmi = vmx_inject_nmi,
4342 .queue_exception = vmx_queue_exception,
4343 .interrupt_allowed = vmx_interrupt_allowed,
4344 .nmi_allowed = vmx_nmi_allowed,
4345 .get_nmi_mask = vmx_get_nmi_mask,
4346 .set_nmi_mask = vmx_set_nmi_mask,
4347 .enable_nmi_window = enable_nmi_window,
4348 .enable_irq_window = enable_irq_window,
4349 .update_cr8_intercept = update_cr8_intercept,
4351 .set_tss_addr = vmx_set_tss_addr,
4352 .get_tdp_level = get_ept_level,
4353 .get_mt_mask = vmx_get_mt_mask,
4355 .exit_reasons_str = vmx_exit_reasons_str,
4356 .get_lpage_level = vmx_get_lpage_level,
4358 .cpuid_update = vmx_cpuid_update,
4360 .rdtscp_supported = vmx_rdtscp_supported,
4362 .set_supported_cpuid = vmx_set_supported_cpuid,
4364 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4367 static int __init vmx_init(void)
4371 rdmsrl_safe(MSR_EFER, &host_efer);
4373 for (i = 0; i < NR_VMX_MSR; ++i)
4374 kvm_define_shared_msr(i, vmx_msr_index[i]);
4376 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4377 if (!vmx_io_bitmap_a)
4380 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4381 if (!vmx_io_bitmap_b) {
4386 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4387 if (!vmx_msr_bitmap_legacy) {
4392 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4393 if (!vmx_msr_bitmap_longmode) {
4399 * Allow direct access to the PC debug port (it is often used for I/O
4400 * delays, but the vmexits simply slow things down).
4402 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4403 clear_bit(0x80, vmx_io_bitmap_a);
4405 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4407 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4408 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4410 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4412 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4413 __alignof__(struct vcpu_vmx), THIS_MODULE);
4417 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4418 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4419 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4420 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4421 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4422 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4425 bypass_guest_pf = 0;
4426 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4427 VMX_EPT_WRITABLE_MASK);
4428 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4429 VMX_EPT_EXECUTABLE_MASK);
4434 if (bypass_guest_pf)
4435 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4440 free_page((unsigned long)vmx_msr_bitmap_longmode);
4442 free_page((unsigned long)vmx_msr_bitmap_legacy);
4444 free_page((unsigned long)vmx_io_bitmap_b);
4446 free_page((unsigned long)vmx_io_bitmap_a);
4450 static void __exit vmx_exit(void)
4452 free_page((unsigned long)vmx_msr_bitmap_legacy);
4453 free_page((unsigned long)vmx_msr_bitmap_longmode);
4454 free_page((unsigned long)vmx_io_bitmap_b);
4455 free_page((unsigned long)vmx_io_bitmap_a);
4460 module_init(vmx_init)
4461 module_exit(vmx_exit)