arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_ept(void)
1243 {
1244         return vmcs_config.cpu_based_2nd_exec_ctrl &
1245                 SECONDARY_EXEC_ENABLE_EPT;
1246 }
1247
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1249 {
1250         return vmcs_config.cpu_based_2nd_exec_ctrl &
1251                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252 }
1253
1254 static inline bool cpu_has_vmx_ple(void)
1255 {
1256         return vmcs_config.cpu_based_2nd_exec_ctrl &
1257                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258 }
1259
1260 static inline bool cpu_has_vmx_basic_inout(void)
1261 {
1262         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263 }
1264
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1266 {
1267         return flexpriority_enabled && lapic_in_kernel(vcpu);
1268 }
1269
1270 static inline bool cpu_has_vmx_vpid(void)
1271 {
1272         return vmcs_config.cpu_based_2nd_exec_ctrl &
1273                 SECONDARY_EXEC_ENABLE_VPID;
1274 }
1275
1276 static inline bool cpu_has_vmx_rdtscp(void)
1277 {
1278         return vmcs_config.cpu_based_2nd_exec_ctrl &
1279                 SECONDARY_EXEC_RDTSCP;
1280 }
1281
1282 static inline bool cpu_has_vmx_invpcid(void)
1283 {
1284         return vmcs_config.cpu_based_2nd_exec_ctrl &
1285                 SECONDARY_EXEC_ENABLE_INVPCID;
1286 }
1287
1288 static inline bool cpu_has_virtual_nmis(void)
1289 {
1290         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1291 }
1292
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl &
1296                 SECONDARY_EXEC_WBINVD_EXITING;
1297 }
1298
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 {
1301         u64 vmx_msr;
1302         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303         /* check if the cpu supports writing r/o exit information fields */
1304         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1305                 return false;
1306
1307         return vmcs_config.cpu_based_2nd_exec_ctrl &
1308                 SECONDARY_EXEC_SHADOW_VMCS;
1309 }
1310
1311 static inline bool cpu_has_vmx_pml(void)
1312 {
1313         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1314 }
1315
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl &
1319                 SECONDARY_EXEC_TSC_SCALING;
1320 }
1321
1322 static inline bool report_flexpriority(void)
1323 {
1324         return flexpriority_enabled;
1325 }
1326
1327 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328 {
1329         return vmcs12->cpu_based_vm_exec_control & bit;
1330 }
1331
1332 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return (vmcs12->cpu_based_vm_exec_control &
1335                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336                 (vmcs12->secondary_vm_exec_control & bit);
1337 }
1338
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1340 {
1341         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342 }
1343
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control &
1347                 PIN_BASED_VMX_PREEMPTION_TIMER;
1348 }
1349
1350 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351 {
1352         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353 }
1354
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358                 vmx_xsaves_supported();
1359 }
1360
1361 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1362 {
1363         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1364 }
1365
1366 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1369 }
1370
1371 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1374 }
1375
1376 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1379 }
1380
1381 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1382 {
1383         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1384 }
1385
1386 static inline bool is_nmi(u32 intr_info)
1387 {
1388         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1389                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1390 }
1391
1392 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1393                               u32 exit_intr_info,
1394                               unsigned long exit_qualification);
1395 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1396                         struct vmcs12 *vmcs12,
1397                         u32 reason, unsigned long qualification);
1398
1399 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1400 {
1401         int i;
1402
1403         for (i = 0; i < vmx->nmsrs; ++i)
1404                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1405                         return i;
1406         return -1;
1407 }
1408
1409 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1410 {
1411     struct {
1412         u64 vpid : 16;
1413         u64 rsvd : 48;
1414         u64 gva;
1415     } operand = { vpid, 0, gva };
1416
1417     asm volatile (__ex(ASM_VMX_INVVPID)
1418                   /* CF==1 or ZF==1 --> rc = -1 */
1419                   "; ja 1f ; ud2 ; 1:"
1420                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1421 }
1422
1423 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1424 {
1425         struct {
1426                 u64 eptp, gpa;
1427         } operand = {eptp, gpa};
1428
1429         asm volatile (__ex(ASM_VMX_INVEPT)
1430                         /* CF==1 or ZF==1 --> rc = -1 */
1431                         "; ja 1f ; ud2 ; 1:\n"
1432                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1433 }
1434
1435 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1436 {
1437         int i;
1438
1439         i = __find_msr_index(vmx, msr);
1440         if (i >= 0)
1441                 return &vmx->guest_msrs[i];
1442         return NULL;
1443 }
1444
1445 static void vmcs_clear(struct vmcs *vmcs)
1446 {
1447         u64 phys_addr = __pa(vmcs);
1448         u8 error;
1449
1450         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1451                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1452                       : "cc", "memory");
1453         if (error)
1454                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1455                        vmcs, phys_addr);
1456 }
1457
1458 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1459 {
1460         vmcs_clear(loaded_vmcs->vmcs);
1461         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1462                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1463         loaded_vmcs->cpu = -1;
1464         loaded_vmcs->launched = 0;
1465 }
1466
1467 static void vmcs_load(struct vmcs *vmcs)
1468 {
1469         u64 phys_addr = __pa(vmcs);
1470         u8 error;
1471
1472         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1473                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1474                         : "cc", "memory");
1475         if (error)
1476                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1477                        vmcs, phys_addr);
1478 }
1479
1480 #ifdef CONFIG_KEXEC_CORE
1481 /*
1482  * This bitmap is used to indicate whether the vmclear
1483  * operation is enabled on all cpus. All disabled by
1484  * default.
1485  */
1486 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1487
1488 static inline void crash_enable_local_vmclear(int cpu)
1489 {
1490         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1491 }
1492
1493 static inline void crash_disable_local_vmclear(int cpu)
1494 {
1495         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline int crash_local_vmclear_enabled(int cpu)
1499 {
1500         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static void crash_vmclear_local_loaded_vmcss(void)
1504 {
1505         int cpu = raw_smp_processor_id();
1506         struct loaded_vmcs *v;
1507
1508         if (!crash_local_vmclear_enabled(cpu))
1509                 return;
1510
1511         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1512                             loaded_vmcss_on_cpu_link)
1513                 vmcs_clear(v->vmcs);
1514 }
1515 #else
1516 static inline void crash_enable_local_vmclear(int cpu) { }
1517 static inline void crash_disable_local_vmclear(int cpu) { }
1518 #endif /* CONFIG_KEXEC_CORE */
1519
1520 static void __loaded_vmcs_clear(void *arg)
1521 {
1522         struct loaded_vmcs *loaded_vmcs = arg;
1523         int cpu = raw_smp_processor_id();
1524
1525         if (loaded_vmcs->cpu != cpu)
1526                 return; /* vcpu migration can race with cpu offline */
1527         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1528                 per_cpu(current_vmcs, cpu) = NULL;
1529         crash_disable_local_vmclear(cpu);
1530         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1531
1532         /*
1533          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534          * is before setting loaded_vmcs->vcpu to -1 which is done in
1535          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536          * then adds the vmcs into percpu list before it is deleted.
1537          */
1538         smp_wmb();
1539
1540         loaded_vmcs_init(loaded_vmcs);
1541         crash_enable_local_vmclear(cpu);
1542 }
1543
1544 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1545 {
1546         int cpu = loaded_vmcs->cpu;
1547
1548         if (cpu != -1)
1549                 smp_call_function_single(cpu,
1550                          __loaded_vmcs_clear, loaded_vmcs, 1);
1551 }
1552
1553 static inline void vpid_sync_vcpu_single(int vpid)
1554 {
1555         if (vpid == 0)
1556                 return;
1557
1558         if (cpu_has_vmx_invvpid_single())
1559                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1560 }
1561
1562 static inline void vpid_sync_vcpu_global(void)
1563 {
1564         if (cpu_has_vmx_invvpid_global())
1565                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1566 }
1567
1568 static inline void vpid_sync_context(int vpid)
1569 {
1570         if (cpu_has_vmx_invvpid_single())
1571                 vpid_sync_vcpu_single(vpid);
1572         else
1573                 vpid_sync_vcpu_global();
1574 }
1575
1576 static inline void ept_sync_global(void)
1577 {
1578         if (cpu_has_vmx_invept_global())
1579                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1580 }
1581
1582 static inline void ept_sync_context(u64 eptp)
1583 {
1584         if (enable_ept) {
1585                 if (cpu_has_vmx_invept_context())
1586                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1587                 else
1588                         ept_sync_global();
1589         }
1590 }
1591
1592 static __always_inline void vmcs_check16(unsigned long field)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595                          "16-bit accessor invalid for 64-bit field");
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597                          "16-bit accessor invalid for 64-bit high field");
1598         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599                          "16-bit accessor invalid for 32-bit high field");
1600         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601                          "16-bit accessor invalid for natural width field");
1602 }
1603
1604 static __always_inline void vmcs_check32(unsigned long field)
1605 {
1606         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607                          "32-bit accessor invalid for 16-bit field");
1608         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609                          "32-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check64(unsigned long field)
1613 {
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615                          "64-bit accessor invalid for 16-bit field");
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617                          "64-bit accessor invalid for 64-bit high field");
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619                          "64-bit accessor invalid for 32-bit field");
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621                          "64-bit accessor invalid for natural width field");
1622 }
1623
1624 static __always_inline void vmcs_checkl(unsigned long field)
1625 {
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627                          "Natural width accessor invalid for 16-bit field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629                          "Natural width accessor invalid for 64-bit field");
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631                          "Natural width accessor invalid for 64-bit high field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633                          "Natural width accessor invalid for 32-bit field");
1634 }
1635
1636 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1637 {
1638         unsigned long value;
1639
1640         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641                       : "=a"(value) : "d"(field) : "cc");
1642         return value;
1643 }
1644
1645 static __always_inline u16 vmcs_read16(unsigned long field)
1646 {
1647         vmcs_check16(field);
1648         return __vmcs_readl(field);
1649 }
1650
1651 static __always_inline u32 vmcs_read32(unsigned long field)
1652 {
1653         vmcs_check32(field);
1654         return __vmcs_readl(field);
1655 }
1656
1657 static __always_inline u64 vmcs_read64(unsigned long field)
1658 {
1659         vmcs_check64(field);
1660 #ifdef CONFIG_X86_64
1661         return __vmcs_readl(field);
1662 #else
1663         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1664 #endif
1665 }
1666
1667 static __always_inline unsigned long vmcs_readl(unsigned long field)
1668 {
1669         vmcs_checkl(field);
1670         return __vmcs_readl(field);
1671 }
1672
1673 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1674 {
1675         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1677         dump_stack();
1678 }
1679
1680 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1681 {
1682         u8 error;
1683
1684         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1685                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1686         if (unlikely(error))
1687                 vmwrite_error(field, value);
1688 }
1689
1690 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1691 {
1692         vmcs_check16(field);
1693         __vmcs_writel(field, value);
1694 }
1695
1696 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1697 {
1698         vmcs_check32(field);
1699         __vmcs_writel(field, value);
1700 }
1701
1702 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1703 {
1704         vmcs_check64(field);
1705         __vmcs_writel(field, value);
1706 #ifndef CONFIG_X86_64
1707         asm volatile ("");
1708         __vmcs_writel(field+1, value >> 32);
1709 #endif
1710 }
1711
1712 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1713 {
1714         vmcs_checkl(field);
1715         __vmcs_writel(field, value);
1716 }
1717
1718 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1719 {
1720         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721                          "vmcs_clear_bits does not support 64-bit fields");
1722         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1723 }
1724
1725 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1726 {
1727         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728                          "vmcs_set_bits does not support 64-bit fields");
1729         __vmcs_writel(field, __vmcs_readl(field) | mask);
1730 }
1731
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1733 {
1734         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1735 }
1736
1737 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1738 {
1739         vmcs_write32(VM_ENTRY_CONTROLS, val);
1740         vmx->vm_entry_controls_shadow = val;
1741 }
1742
1743 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1744 {
1745         if (vmx->vm_entry_controls_shadow != val)
1746                 vm_entry_controls_init(vmx, val);
1747 }
1748
1749 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1750 {
1751         return vmx->vm_entry_controls_shadow;
1752 }
1753
1754
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1756 {
1757         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1758 }
1759
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1763 }
1764
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1766 {
1767         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1768 }
1769
1770 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1771 {
1772         vmcs_write32(VM_EXIT_CONTROLS, val);
1773         vmx->vm_exit_controls_shadow = val;
1774 }
1775
1776 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1777 {
1778         if (vmx->vm_exit_controls_shadow != val)
1779                 vm_exit_controls_init(vmx, val);
1780 }
1781
1782 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1783 {
1784         return vmx->vm_exit_controls_shadow;
1785 }
1786
1787
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1789 {
1790         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1791 }
1792
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1796 }
1797
1798 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1799 {
1800         vmx->segment_cache.bitmask = 0;
1801 }
1802
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1804                                        unsigned field)
1805 {
1806         bool ret;
1807         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1808
1809         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811                 vmx->segment_cache.bitmask = 0;
1812         }
1813         ret = vmx->segment_cache.bitmask & mask;
1814         vmx->segment_cache.bitmask |= mask;
1815         return ret;
1816 }
1817
1818 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1819 {
1820         u16 *p = &vmx->segment_cache.seg[seg].selector;
1821
1822         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1824         return *p;
1825 }
1826
1827 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         ulong *p = &vmx->segment_cache.seg[seg].base;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1833         return *p;
1834 }
1835
1836 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         u32 *p = &vmx->segment_cache.seg[seg].limit;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].ar;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1851         return *p;
1852 }
1853
1854 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1855 {
1856         u32 eb;
1857
1858         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1859              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1860         if ((vcpu->guest_debug &
1861              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863                 eb |= 1u << BP_VECTOR;
1864         if (to_vmx(vcpu)->rmode.vm86_active)
1865                 eb = ~0;
1866         if (enable_ept)
1867                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1868
1869         /* When we are running a nested L2 guest and L1 specified for it a
1870          * certain exception bitmap, we must trap the same exceptions and pass
1871          * them to L1. When running L2, we will only handle the exceptions
1872          * specified above if L1 did not want them.
1873          */
1874         if (is_guest_mode(vcpu))
1875                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1876
1877         vmcs_write32(EXCEPTION_BITMAP, eb);
1878 }
1879
1880 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1881                 unsigned long entry, unsigned long exit)
1882 {
1883         vm_entry_controls_clearbit(vmx, entry);
1884         vm_exit_controls_clearbit(vmx, exit);
1885 }
1886
1887 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1888 {
1889         unsigned i;
1890         struct msr_autoload *m = &vmx->msr_autoload;
1891
1892         switch (msr) {
1893         case MSR_EFER:
1894                 if (cpu_has_load_ia32_efer) {
1895                         clear_atomic_switch_msr_special(vmx,
1896                                         VM_ENTRY_LOAD_IA32_EFER,
1897                                         VM_EXIT_LOAD_IA32_EFER);
1898                         return;
1899                 }
1900                 break;
1901         case MSR_CORE_PERF_GLOBAL_CTRL:
1902                 if (cpu_has_load_perf_global_ctrl) {
1903                         clear_atomic_switch_msr_special(vmx,
1904                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1905                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1906                         return;
1907                 }
1908                 break;
1909         }
1910
1911         for (i = 0; i < m->nr; ++i)
1912                 if (m->guest[i].index == msr)
1913                         break;
1914
1915         if (i == m->nr)
1916                 return;
1917         --m->nr;
1918         m->guest[i] = m->guest[m->nr];
1919         m->host[i] = m->host[m->nr];
1920         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1921         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1922 }
1923
1924 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1925                 unsigned long entry, unsigned long exit,
1926                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1927                 u64 guest_val, u64 host_val)
1928 {
1929         vmcs_write64(guest_val_vmcs, guest_val);
1930         vmcs_write64(host_val_vmcs, host_val);
1931         vm_entry_controls_setbit(vmx, entry);
1932         vm_exit_controls_setbit(vmx, exit);
1933 }
1934
1935 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1936                                   u64 guest_val, u64 host_val)
1937 {
1938         unsigned i;
1939         struct msr_autoload *m = &vmx->msr_autoload;
1940
1941         switch (msr) {
1942         case MSR_EFER:
1943                 if (cpu_has_load_ia32_efer) {
1944                         add_atomic_switch_msr_special(vmx,
1945                                         VM_ENTRY_LOAD_IA32_EFER,
1946                                         VM_EXIT_LOAD_IA32_EFER,
1947                                         GUEST_IA32_EFER,
1948                                         HOST_IA32_EFER,
1949                                         guest_val, host_val);
1950                         return;
1951                 }
1952                 break;
1953         case MSR_CORE_PERF_GLOBAL_CTRL:
1954                 if (cpu_has_load_perf_global_ctrl) {
1955                         add_atomic_switch_msr_special(vmx,
1956                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1957                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1958                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1959                                         HOST_IA32_PERF_GLOBAL_CTRL,
1960                                         guest_val, host_val);
1961                         return;
1962                 }
1963                 break;
1964         case MSR_IA32_PEBS_ENABLE:
1965                 /* PEBS needs a quiescent period after being disabled (to write
1966                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1967                  * provide that period, so a CPU could write host's record into
1968                  * guest's memory.
1969                  */
1970                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1971         }
1972
1973         for (i = 0; i < m->nr; ++i)
1974                 if (m->guest[i].index == msr)
1975                         break;
1976
1977         if (i == NR_AUTOLOAD_MSRS) {
1978                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1979                                 "Can't add msr %x\n", msr);
1980                 return;
1981         } else if (i == m->nr) {
1982                 ++m->nr;
1983                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1984                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1985         }
1986
1987         m->guest[i].index = msr;
1988         m->guest[i].value = guest_val;
1989         m->host[i].index = msr;
1990         m->host[i].value = host_val;
1991 }
1992
1993 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1994 {
1995         u64 guest_efer = vmx->vcpu.arch.efer;
1996         u64 ignore_bits = 0;
1997
1998         if (!enable_ept) {
1999                 /*
2000                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2001                  * host CPUID is more efficient than testing guest CPUID
2002                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2003                  */
2004                 if (boot_cpu_has(X86_FEATURE_SMEP))
2005                         guest_efer |= EFER_NX;
2006                 else if (!(guest_efer & EFER_NX))
2007                         ignore_bits |= EFER_NX;
2008         }
2009
2010         /*
2011          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2012          */
2013         ignore_bits |= EFER_SCE;
2014 #ifdef CONFIG_X86_64
2015         ignore_bits |= EFER_LMA | EFER_LME;
2016         /* SCE is meaningful only in long mode on Intel */
2017         if (guest_efer & EFER_LMA)
2018                 ignore_bits &= ~(u64)EFER_SCE;
2019 #endif
2020
2021         clear_atomic_switch_msr(vmx, MSR_EFER);
2022
2023         /*
2024          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2025          * On CPUs that support "load IA32_EFER", always switch EFER
2026          * atomically, since it's faster than switching it manually.
2027          */
2028         if (cpu_has_load_ia32_efer ||
2029             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2030                 if (!(guest_efer & EFER_LMA))
2031                         guest_efer &= ~EFER_LME;
2032                 if (guest_efer != host_efer)
2033                         add_atomic_switch_msr(vmx, MSR_EFER,
2034                                               guest_efer, host_efer);
2035                 return false;
2036         } else {
2037                 guest_efer &= ~ignore_bits;
2038                 guest_efer |= host_efer & ignore_bits;
2039
2040                 vmx->guest_msrs[efer_offset].data = guest_efer;
2041                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2042
2043                 return true;
2044         }
2045 }
2046
2047 #ifdef CONFIG_X86_32
2048 /*
2049  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2050  * VMCS rather than the segment table.  KVM uses this helper to figure
2051  * out the current bases to poke them into the VMCS before entry.
2052  */
2053 static unsigned long segment_base(u16 selector)
2054 {
2055         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2056         struct desc_struct *table;
2057         unsigned long v;
2058
2059         if (!(selector & ~SEGMENT_RPL_MASK))
2060                 return 0;
2061
2062         table = (struct desc_struct *)gdt->address;
2063
2064         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2065                 u16 ldt_selector = kvm_read_ldt();
2066
2067                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2068                         return 0;
2069
2070                 table = (struct desc_struct *)segment_base(ldt_selector);
2071         }
2072         v = get_desc_base(&table[selector >> 3]);
2073         return v;
2074 }
2075 #endif
2076
2077 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2078 {
2079         struct vcpu_vmx *vmx = to_vmx(vcpu);
2080         int i;
2081
2082         if (vmx->host_state.loaded)
2083                 return;
2084
2085         vmx->host_state.loaded = 1;
2086         /*
2087          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2088          * allow segment selectors with cpl > 0 or ti == 1.
2089          */
2090         vmx->host_state.ldt_sel = kvm_read_ldt();
2091         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2092         savesegment(fs, vmx->host_state.fs_sel);
2093         if (!(vmx->host_state.fs_sel & 7)) {
2094                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2095                 vmx->host_state.fs_reload_needed = 0;
2096         } else {
2097                 vmcs_write16(HOST_FS_SELECTOR, 0);
2098                 vmx->host_state.fs_reload_needed = 1;
2099         }
2100         savesegment(gs, vmx->host_state.gs_sel);
2101         if (!(vmx->host_state.gs_sel & 7))
2102                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2103         else {
2104                 vmcs_write16(HOST_GS_SELECTOR, 0);
2105                 vmx->host_state.gs_ldt_reload_needed = 1;
2106         }
2107
2108 #ifdef CONFIG_X86_64
2109         savesegment(ds, vmx->host_state.ds_sel);
2110         savesegment(es, vmx->host_state.es_sel);
2111 #endif
2112
2113 #ifdef CONFIG_X86_64
2114         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2115         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2116 #else
2117         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2118         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2119 #endif
2120
2121 #ifdef CONFIG_X86_64
2122         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2123         if (is_long_mode(&vmx->vcpu))
2124                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2125 #endif
2126         if (boot_cpu_has(X86_FEATURE_MPX))
2127                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2128         for (i = 0; i < vmx->save_nmsrs; ++i)
2129                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2130                                    vmx->guest_msrs[i].data,
2131                                    vmx->guest_msrs[i].mask);
2132 }
2133
2134 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2135 {
2136         if (!vmx->host_state.loaded)
2137                 return;
2138
2139         ++vmx->vcpu.stat.host_state_reload;
2140         vmx->host_state.loaded = 0;
2141 #ifdef CONFIG_X86_64
2142         if (is_long_mode(&vmx->vcpu))
2143                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2144 #endif
2145         if (vmx->host_state.gs_ldt_reload_needed) {
2146                 kvm_load_ldt(vmx->host_state.ldt_sel);
2147 #ifdef CONFIG_X86_64
2148                 load_gs_index(vmx->host_state.gs_sel);
2149 #else
2150                 loadsegment(gs, vmx->host_state.gs_sel);
2151 #endif
2152         }
2153         if (vmx->host_state.fs_reload_needed)
2154                 loadsegment(fs, vmx->host_state.fs_sel);
2155 #ifdef CONFIG_X86_64
2156         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2157                 loadsegment(ds, vmx->host_state.ds_sel);
2158                 loadsegment(es, vmx->host_state.es_sel);
2159         }
2160 #endif
2161         invalidate_tss_limit();
2162 #ifdef CONFIG_X86_64
2163         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2164 #endif
2165         if (vmx->host_state.msr_host_bndcfgs)
2166                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2167         load_gdt(this_cpu_ptr(&host_gdt));
2168 }
2169
2170 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2171 {
2172         preempt_disable();
2173         __vmx_load_host_state(vmx);
2174         preempt_enable();
2175 }
2176
2177 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2178 {
2179         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2180         struct pi_desc old, new;
2181         unsigned int dest;
2182
2183         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2184                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2185                 !kvm_vcpu_apicv_active(vcpu))
2186                 return;
2187
2188         do {
2189                 old.control = new.control = pi_desc->control;
2190
2191                 /*
2192                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2193                  * are two possible cases:
2194                  * 1. After running 'pre_block', context switch
2195                  *    happened. For this case, 'sn' was set in
2196                  *    vmx_vcpu_put(), so we need to clear it here.
2197                  * 2. After running 'pre_block', we were blocked,
2198                  *    and woken up by some other guy. For this case,
2199                  *    we don't need to do anything, 'pi_post_block'
2200                  *    will do everything for us. However, we cannot
2201                  *    check whether it is case #1 or case #2 here
2202                  *    (maybe, not needed), so we also clear sn here,
2203                  *    I think it is not a big deal.
2204                  */
2205                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2206                         if (vcpu->cpu != cpu) {
2207                                 dest = cpu_physical_id(cpu);
2208
2209                                 if (x2apic_enabled())
2210                                         new.ndst = dest;
2211                                 else
2212                                         new.ndst = (dest << 8) & 0xFF00;
2213                         }
2214
2215                         /* set 'NV' to 'notification vector' */
2216                         new.nv = POSTED_INTR_VECTOR;
2217                 }
2218
2219                 /* Allow posting non-urgent interrupts */
2220                 new.sn = 0;
2221         } while (cmpxchg(&pi_desc->control, old.control,
2222                         new.control) != old.control);
2223 }
2224
2225 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2226 {
2227         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2228         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2229 }
2230
2231 /*
2232  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2233  * vcpu mutex is already taken.
2234  */
2235 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2236 {
2237         struct vcpu_vmx *vmx = to_vmx(vcpu);
2238         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2239         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2240
2241         if (!vmm_exclusive)
2242                 kvm_cpu_vmxon(phys_addr);
2243         else if (!already_loaded)
2244                 loaded_vmcs_clear(vmx->loaded_vmcs);
2245
2246         if (!already_loaded) {
2247                 local_irq_disable();
2248                 crash_disable_local_vmclear(cpu);
2249
2250                 /*
2251                  * Read loaded_vmcs->cpu should be before fetching
2252                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2253                  * See the comments in __loaded_vmcs_clear().
2254                  */
2255                 smp_rmb();
2256
2257                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2258                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2259                 crash_enable_local_vmclear(cpu);
2260                 local_irq_enable();
2261         }
2262
2263         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2264                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2265                 vmcs_load(vmx->loaded_vmcs->vmcs);
2266         }
2267
2268         if (!already_loaded) {
2269                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2270                 unsigned long sysenter_esp;
2271
2272                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2273
2274                 /*
2275                  * Linux uses per-cpu TSS and GDT, so set these when switching
2276                  * processors.  See 22.2.4.
2277                  */
2278                 vmcs_writel(HOST_TR_BASE,
2279                             (unsigned long)this_cpu_ptr(&cpu_tss));
2280                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2281
2282                 /*
2283                  * VM exits change the host TR limit to 0x67 after a VM
2284                  * exit.  This is okay, since 0x67 covers everything except
2285                  * the IO bitmap and have have code to handle the IO bitmap
2286                  * being lost after a VM exit.
2287                  */
2288                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2289
2290                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2291                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2292
2293                 vmx->loaded_vmcs->cpu = cpu;
2294         }
2295
2296         /* Setup TSC multiplier */
2297         if (kvm_has_tsc_control &&
2298             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2299                 decache_tsc_multiplier(vmx);
2300
2301         vmx_vcpu_pi_load(vcpu, cpu);
2302         vmx->host_pkru = read_pkru();
2303 }
2304
2305 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2306 {
2307         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2308
2309         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2310                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2311                 !kvm_vcpu_apicv_active(vcpu))
2312                 return;
2313
2314         /* Set SN when the vCPU is preempted */
2315         if (vcpu->preempted)
2316                 pi_set_sn(pi_desc);
2317 }
2318
2319 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2320 {
2321         vmx_vcpu_pi_put(vcpu);
2322
2323         __vmx_load_host_state(to_vmx(vcpu));
2324         if (!vmm_exclusive) {
2325                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2326                 vcpu->cpu = -1;
2327                 kvm_cpu_vmxoff();
2328         }
2329 }
2330
2331 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2332
2333 /*
2334  * Return the cr0 value that a nested guest would read. This is a combination
2335  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2336  * its hypervisor (cr0_read_shadow).
2337  */
2338 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2339 {
2340         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2341                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2342 }
2343 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2344 {
2345         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2346                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2347 }
2348
2349 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2350 {
2351         unsigned long rflags, save_rflags;
2352
2353         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2354                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2355                 rflags = vmcs_readl(GUEST_RFLAGS);
2356                 if (to_vmx(vcpu)->rmode.vm86_active) {
2357                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2358                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2359                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2360                 }
2361                 to_vmx(vcpu)->rflags = rflags;
2362         }
2363         return to_vmx(vcpu)->rflags;
2364 }
2365
2366 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2367 {
2368         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2369         to_vmx(vcpu)->rflags = rflags;
2370         if (to_vmx(vcpu)->rmode.vm86_active) {
2371                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2372                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2373         }
2374         vmcs_writel(GUEST_RFLAGS, rflags);
2375 }
2376
2377 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2378 {
2379         return to_vmx(vcpu)->guest_pkru;
2380 }
2381
2382 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2383 {
2384         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2385         int ret = 0;
2386
2387         if (interruptibility & GUEST_INTR_STATE_STI)
2388                 ret |= KVM_X86_SHADOW_INT_STI;
2389         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2390                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2391
2392         return ret;
2393 }
2394
2395 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2396 {
2397         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2398         u32 interruptibility = interruptibility_old;
2399
2400         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2401
2402         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2403                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2404         else if (mask & KVM_X86_SHADOW_INT_STI)
2405                 interruptibility |= GUEST_INTR_STATE_STI;
2406
2407         if ((interruptibility != interruptibility_old))
2408                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2409 }
2410
2411 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2412 {
2413         unsigned long rip;
2414
2415         rip = kvm_rip_read(vcpu);
2416         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2417         kvm_rip_write(vcpu, rip);
2418
2419         /* skipping an emulated instruction also counts */
2420         vmx_set_interrupt_shadow(vcpu, 0);
2421 }
2422
2423 /*
2424  * KVM wants to inject page-faults which it got to the guest. This function
2425  * checks whether in a nested guest, we need to inject them to L1 or L2.
2426  */
2427 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2428 {
2429         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2430
2431         if (!(vmcs12->exception_bitmap & (1u << nr)))
2432                 return 0;
2433
2434         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2435                           vmcs_read32(VM_EXIT_INTR_INFO),
2436                           vmcs_readl(EXIT_QUALIFICATION));
2437         return 1;
2438 }
2439
2440 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2441                                 bool has_error_code, u32 error_code,
2442                                 bool reinject)
2443 {
2444         struct vcpu_vmx *vmx = to_vmx(vcpu);
2445         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2446
2447         if (!reinject && is_guest_mode(vcpu) &&
2448             nested_vmx_check_exception(vcpu, nr))
2449                 return;
2450
2451         if (has_error_code) {
2452                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2453                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2454         }
2455
2456         if (vmx->rmode.vm86_active) {
2457                 int inc_eip = 0;
2458                 if (kvm_exception_is_soft(nr))
2459                         inc_eip = vcpu->arch.event_exit_inst_len;
2460                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2461                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2462                 return;
2463         }
2464
2465         if (kvm_exception_is_soft(nr)) {
2466                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2467                              vmx->vcpu.arch.event_exit_inst_len);
2468                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2469         } else
2470                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2471
2472         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2473 }
2474
2475 static bool vmx_rdtscp_supported(void)
2476 {
2477         return cpu_has_vmx_rdtscp();
2478 }
2479
2480 static bool vmx_invpcid_supported(void)
2481 {
2482         return cpu_has_vmx_invpcid() && enable_ept;
2483 }
2484
2485 /*
2486  * Swap MSR entry in host/guest MSR entry array.
2487  */
2488 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2489 {
2490         struct shared_msr_entry tmp;
2491
2492         tmp = vmx->guest_msrs[to];
2493         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2494         vmx->guest_msrs[from] = tmp;
2495 }
2496
2497 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2498 {
2499         unsigned long *msr_bitmap;
2500
2501         if (is_guest_mode(vcpu))
2502                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2503         else if (cpu_has_secondary_exec_ctrls() &&
2504                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2505                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2506                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2507                         if (is_long_mode(vcpu))
2508                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2509                         else
2510                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2511                 } else {
2512                         if (is_long_mode(vcpu))
2513                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2514                         else
2515                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2516                 }
2517         } else {
2518                 if (is_long_mode(vcpu))
2519                         msr_bitmap = vmx_msr_bitmap_longmode;
2520                 else
2521                         msr_bitmap = vmx_msr_bitmap_legacy;
2522         }
2523
2524         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2525 }
2526
2527 /*
2528  * Set up the vmcs to automatically save and restore system
2529  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2530  * mode, as fiddling with msrs is very expensive.
2531  */
2532 static void setup_msrs(struct vcpu_vmx *vmx)
2533 {
2534         int save_nmsrs, index;
2535
2536         save_nmsrs = 0;
2537 #ifdef CONFIG_X86_64
2538         if (is_long_mode(&vmx->vcpu)) {
2539                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2540                 if (index >= 0)
2541                         move_msr_up(vmx, index, save_nmsrs++);
2542                 index = __find_msr_index(vmx, MSR_LSTAR);
2543                 if (index >= 0)
2544                         move_msr_up(vmx, index, save_nmsrs++);
2545                 index = __find_msr_index(vmx, MSR_CSTAR);
2546                 if (index >= 0)
2547                         move_msr_up(vmx, index, save_nmsrs++);
2548                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2549                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2550                         move_msr_up(vmx, index, save_nmsrs++);
2551                 /*
2552                  * MSR_STAR is only needed on long mode guests, and only
2553                  * if efer.sce is enabled.
2554                  */
2555                 index = __find_msr_index(vmx, MSR_STAR);
2556                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2557                         move_msr_up(vmx, index, save_nmsrs++);
2558         }
2559 #endif
2560         index = __find_msr_index(vmx, MSR_EFER);
2561         if (index >= 0 && update_transition_efer(vmx, index))
2562                 move_msr_up(vmx, index, save_nmsrs++);
2563
2564         vmx->save_nmsrs = save_nmsrs;
2565
2566         if (cpu_has_vmx_msr_bitmap())
2567                 vmx_set_msr_bitmap(&vmx->vcpu);
2568 }
2569
2570 /*
2571  * reads and returns guest's timestamp counter "register"
2572  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2573  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2574  */
2575 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2576 {
2577         u64 host_tsc, tsc_offset;
2578
2579         host_tsc = rdtsc();
2580         tsc_offset = vmcs_read64(TSC_OFFSET);
2581         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2582 }
2583
2584 /*
2585  * writes 'offset' into guest's timestamp counter offset register
2586  */
2587 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2588 {
2589         if (is_guest_mode(vcpu)) {
2590                 /*
2591                  * We're here if L1 chose not to trap WRMSR to TSC. According
2592                  * to the spec, this should set L1's TSC; The offset that L1
2593                  * set for L2 remains unchanged, and still needs to be added
2594                  * to the newly set TSC to get L2's TSC.
2595                  */
2596                 struct vmcs12 *vmcs12;
2597                 /* recalculate vmcs02.TSC_OFFSET: */
2598                 vmcs12 = get_vmcs12(vcpu);
2599                 vmcs_write64(TSC_OFFSET, offset +
2600                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2601                          vmcs12->tsc_offset : 0));
2602         } else {
2603                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2604                                            vmcs_read64(TSC_OFFSET), offset);
2605                 vmcs_write64(TSC_OFFSET, offset);
2606         }
2607 }
2608
2609 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2610 {
2611         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2612         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2613 }
2614
2615 /*
2616  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2617  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2618  * all guests if the "nested" module option is off, and can also be disabled
2619  * for a single guest by disabling its VMX cpuid bit.
2620  */
2621 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2622 {
2623         return nested && guest_cpuid_has_vmx(vcpu);
2624 }
2625
2626 /*
2627  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2628  * returned for the various VMX controls MSRs when nested VMX is enabled.
2629  * The same values should also be used to verify that vmcs12 control fields are
2630  * valid during nested entry from L1 to L2.
2631  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2632  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2633  * bit in the high half is on if the corresponding bit in the control field
2634  * may be on. See also vmx_control_verify().
2635  */
2636 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2637 {
2638         /*
2639          * Note that as a general rule, the high half of the MSRs (bits in
2640          * the control fields which may be 1) should be initialized by the
2641          * intersection of the underlying hardware's MSR (i.e., features which
2642          * can be supported) and the list of features we want to expose -
2643          * because they are known to be properly supported in our code.
2644          * Also, usually, the low half of the MSRs (bits which must be 1) can
2645          * be set to 0, meaning that L1 may turn off any of these bits. The
2646          * reason is that if one of these bits is necessary, it will appear
2647          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2648          * fields of vmcs01 and vmcs02, will turn these bits off - and
2649          * nested_vmx_exit_handled() will not pass related exits to L1.
2650          * These rules have exceptions below.
2651          */
2652
2653         /* pin-based controls */
2654         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2655                 vmx->nested.nested_vmx_pinbased_ctls_low,
2656                 vmx->nested.nested_vmx_pinbased_ctls_high);
2657         vmx->nested.nested_vmx_pinbased_ctls_low |=
2658                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2659         vmx->nested.nested_vmx_pinbased_ctls_high &=
2660                 PIN_BASED_EXT_INTR_MASK |
2661                 PIN_BASED_NMI_EXITING |
2662                 PIN_BASED_VIRTUAL_NMIS;
2663         vmx->nested.nested_vmx_pinbased_ctls_high |=
2664                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2665                 PIN_BASED_VMX_PREEMPTION_TIMER;
2666         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2667                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2668                         PIN_BASED_POSTED_INTR;
2669
2670         /* exit controls */
2671         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2672                 vmx->nested.nested_vmx_exit_ctls_low,
2673                 vmx->nested.nested_vmx_exit_ctls_high);
2674         vmx->nested.nested_vmx_exit_ctls_low =
2675                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2676
2677         vmx->nested.nested_vmx_exit_ctls_high &=
2678 #ifdef CONFIG_X86_64
2679                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2680 #endif
2681                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2682         vmx->nested.nested_vmx_exit_ctls_high |=
2683                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2684                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2685                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2686
2687         if (kvm_mpx_supported())
2688                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2689
2690         /* We support free control of debug control saving. */
2691         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2692
2693         /* entry controls */
2694         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2695                 vmx->nested.nested_vmx_entry_ctls_low,
2696                 vmx->nested.nested_vmx_entry_ctls_high);
2697         vmx->nested.nested_vmx_entry_ctls_low =
2698                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2699         vmx->nested.nested_vmx_entry_ctls_high &=
2700 #ifdef CONFIG_X86_64
2701                 VM_ENTRY_IA32E_MODE |
2702 #endif
2703                 VM_ENTRY_LOAD_IA32_PAT;
2704         vmx->nested.nested_vmx_entry_ctls_high |=
2705                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2706         if (kvm_mpx_supported())
2707                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2708
2709         /* We support free control of debug control loading. */
2710         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2711
2712         /* cpu-based controls */
2713         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2714                 vmx->nested.nested_vmx_procbased_ctls_low,
2715                 vmx->nested.nested_vmx_procbased_ctls_high);
2716         vmx->nested.nested_vmx_procbased_ctls_low =
2717                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2718         vmx->nested.nested_vmx_procbased_ctls_high &=
2719                 CPU_BASED_VIRTUAL_INTR_PENDING |
2720                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2721                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2722                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2723                 CPU_BASED_CR3_STORE_EXITING |
2724 #ifdef CONFIG_X86_64
2725                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2726 #endif
2727                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2728                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2729                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2730                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2731                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2732         /*
2733          * We can allow some features even when not supported by the
2734          * hardware. For example, L1 can specify an MSR bitmap - and we
2735          * can use it to avoid exits to L1 - even when L0 runs L2
2736          * without MSR bitmaps.
2737          */
2738         vmx->nested.nested_vmx_procbased_ctls_high |=
2739                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2740                 CPU_BASED_USE_MSR_BITMAPS;
2741
2742         /* We support free control of CR3 access interception. */
2743         vmx->nested.nested_vmx_procbased_ctls_low &=
2744                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2745
2746         /* secondary cpu-based controls */
2747         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2748                 vmx->nested.nested_vmx_secondary_ctls_low,
2749                 vmx->nested.nested_vmx_secondary_ctls_high);
2750         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2751         vmx->nested.nested_vmx_secondary_ctls_high &=
2752                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2753                 SECONDARY_EXEC_RDTSCP |
2754                 SECONDARY_EXEC_DESC |
2755                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2756                 SECONDARY_EXEC_ENABLE_VPID |
2757                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2758                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2759                 SECONDARY_EXEC_WBINVD_EXITING |
2760                 SECONDARY_EXEC_XSAVES;
2761
2762         if (enable_ept) {
2763                 /* nested EPT: emulate EPT also to L1 */
2764                 vmx->nested.nested_vmx_secondary_ctls_high |=
2765                         SECONDARY_EXEC_ENABLE_EPT;
2766                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2767                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2768                          VMX_EPT_INVEPT_BIT;
2769                 if (cpu_has_vmx_ept_execute_only())
2770                         vmx->nested.nested_vmx_ept_caps |=
2771                                 VMX_EPT_EXECUTE_ONLY_BIT;
2772                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2773                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2774                         VMX_EPT_EXTENT_CONTEXT_BIT;
2775         } else
2776                 vmx->nested.nested_vmx_ept_caps = 0;
2777
2778         /*
2779          * Old versions of KVM use the single-context version without
2780          * checking for support, so declare that it is supported even
2781          * though it is treated as global context.  The alternative is
2782          * not failing the single-context invvpid, and it is worse.
2783          */
2784         if (enable_vpid)
2785                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2786                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2787         else
2788                 vmx->nested.nested_vmx_vpid_caps = 0;
2789
2790         if (enable_unrestricted_guest)
2791                 vmx->nested.nested_vmx_secondary_ctls_high |=
2792                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2793
2794         /* miscellaneous data */
2795         rdmsr(MSR_IA32_VMX_MISC,
2796                 vmx->nested.nested_vmx_misc_low,
2797                 vmx->nested.nested_vmx_misc_high);
2798         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2799         vmx->nested.nested_vmx_misc_low |=
2800                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2801                 VMX_MISC_ACTIVITY_HLT;
2802         vmx->nested.nested_vmx_misc_high = 0;
2803
2804         /*
2805          * This MSR reports some information about VMX support. We
2806          * should return information about the VMX we emulate for the
2807          * guest, and the VMCS structure we give it - not about the
2808          * VMX support of the underlying hardware.
2809          */
2810         vmx->nested.nested_vmx_basic =
2811                 VMCS12_REVISION |
2812                 VMX_BASIC_TRUE_CTLS |
2813                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2814                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2815
2816         if (cpu_has_vmx_basic_inout())
2817                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2818
2819         /*
2820          * These MSRs specify bits which the guest must keep fixed on
2821          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2822          * We picked the standard core2 setting.
2823          */
2824 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2825 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2826         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2827         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2828
2829         /* These MSRs specify bits which the guest must keep fixed off. */
2830         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2831         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2832
2833         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2834         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2835 }
2836
2837 /*
2838  * if fixed0[i] == 1: val[i] must be 1
2839  * if fixed1[i] == 0: val[i] must be 0
2840  */
2841 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2842 {
2843         return ((val & fixed1) | fixed0) == val;
2844 }
2845
2846 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2847 {
2848         return fixed_bits_valid(control, low, high);
2849 }
2850
2851 static inline u64 vmx_control_msr(u32 low, u32 high)
2852 {
2853         return low | ((u64)high << 32);
2854 }
2855
2856 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2857 {
2858         superset &= mask;
2859         subset &= mask;
2860
2861         return (superset | subset) == superset;
2862 }
2863
2864 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2865 {
2866         const u64 feature_and_reserved =
2867                 /* feature (except bit 48; see below) */
2868                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2869                 /* reserved */
2870                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2871         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2872
2873         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2874                 return -EINVAL;
2875
2876         /*
2877          * KVM does not emulate a version of VMX that constrains physical
2878          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2879          */
2880         if (data & BIT_ULL(48))
2881                 return -EINVAL;
2882
2883         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2884             vmx_basic_vmcs_revision_id(data))
2885                 return -EINVAL;
2886
2887         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2888                 return -EINVAL;
2889
2890         vmx->nested.nested_vmx_basic = data;
2891         return 0;
2892 }
2893
2894 static int
2895 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2896 {
2897         u64 supported;
2898         u32 *lowp, *highp;
2899
2900         switch (msr_index) {
2901         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2902                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2903                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2904                 break;
2905         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2906                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2907                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2908                 break;
2909         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2910                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2911                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2912                 break;
2913         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2914                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2915                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2916                 break;
2917         case MSR_IA32_VMX_PROCBASED_CTLS2:
2918                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2919                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2920                 break;
2921         default:
2922                 BUG();
2923         }
2924
2925         supported = vmx_control_msr(*lowp, *highp);
2926
2927         /* Check must-be-1 bits are still 1. */
2928         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2929                 return -EINVAL;
2930
2931         /* Check must-be-0 bits are still 0. */
2932         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2933                 return -EINVAL;
2934
2935         *lowp = data;
2936         *highp = data >> 32;
2937         return 0;
2938 }
2939
2940 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2941 {
2942         const u64 feature_and_reserved_bits =
2943                 /* feature */
2944                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2945                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2946                 /* reserved */
2947                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2948         u64 vmx_misc;
2949
2950         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2951                                    vmx->nested.nested_vmx_misc_high);
2952
2953         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2954                 return -EINVAL;
2955
2956         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2957              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2958             vmx_misc_preemption_timer_rate(data) !=
2959             vmx_misc_preemption_timer_rate(vmx_misc))
2960                 return -EINVAL;
2961
2962         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2963                 return -EINVAL;
2964
2965         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2966                 return -EINVAL;
2967
2968         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2969                 return -EINVAL;
2970
2971         vmx->nested.nested_vmx_misc_low = data;
2972         vmx->nested.nested_vmx_misc_high = data >> 32;
2973         return 0;
2974 }
2975
2976 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2977 {
2978         u64 vmx_ept_vpid_cap;
2979
2980         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2981                                            vmx->nested.nested_vmx_vpid_caps);
2982
2983         /* Every bit is either reserved or a feature bit. */
2984         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2985                 return -EINVAL;
2986
2987         vmx->nested.nested_vmx_ept_caps = data;
2988         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2989         return 0;
2990 }
2991
2992 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2993 {
2994         u64 *msr;
2995
2996         switch (msr_index) {
2997         case MSR_IA32_VMX_CR0_FIXED0:
2998                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
2999                 break;
3000         case MSR_IA32_VMX_CR4_FIXED0:
3001                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3002                 break;
3003         default:
3004                 BUG();
3005         }
3006
3007         /*
3008          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3009          * must be 1 in the restored value.
3010          */
3011         if (!is_bitwise_subset(data, *msr, -1ULL))
3012                 return -EINVAL;
3013
3014         *msr = data;
3015         return 0;
3016 }
3017
3018 /*
3019  * Called when userspace is restoring VMX MSRs.
3020  *
3021  * Returns 0 on success, non-0 otherwise.
3022  */
3023 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3024 {
3025         struct vcpu_vmx *vmx = to_vmx(vcpu);
3026
3027         switch (msr_index) {
3028         case MSR_IA32_VMX_BASIC:
3029                 return vmx_restore_vmx_basic(vmx, data);
3030         case MSR_IA32_VMX_PINBASED_CTLS:
3031         case MSR_IA32_VMX_PROCBASED_CTLS:
3032         case MSR_IA32_VMX_EXIT_CTLS:
3033         case MSR_IA32_VMX_ENTRY_CTLS:
3034                 /*
3035                  * The "non-true" VMX capability MSRs are generated from the
3036                  * "true" MSRs, so we do not support restoring them directly.
3037                  *
3038                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3039                  * should restore the "true" MSRs with the must-be-1 bits
3040                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3041                  * DEFAULT SETTINGS".
3042                  */
3043                 return -EINVAL;
3044         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3045         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3046         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3047         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3048         case MSR_IA32_VMX_PROCBASED_CTLS2:
3049                 return vmx_restore_control_msr(vmx, msr_index, data);
3050         case MSR_IA32_VMX_MISC:
3051                 return vmx_restore_vmx_misc(vmx, data);
3052         case MSR_IA32_VMX_CR0_FIXED0:
3053         case MSR_IA32_VMX_CR4_FIXED0:
3054                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3055         case MSR_IA32_VMX_CR0_FIXED1:
3056         case MSR_IA32_VMX_CR4_FIXED1:
3057                 /*
3058                  * These MSRs are generated based on the vCPU's CPUID, so we
3059                  * do not support restoring them directly.
3060                  */
3061                 return -EINVAL;
3062         case MSR_IA32_VMX_EPT_VPID_CAP:
3063                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3064         case MSR_IA32_VMX_VMCS_ENUM:
3065                 vmx->nested.nested_vmx_vmcs_enum = data;
3066                 return 0;
3067         default:
3068                 /*
3069                  * The rest of the VMX capability MSRs do not support restore.
3070                  */
3071                 return -EINVAL;
3072         }
3073 }
3074
3075 /* Returns 0 on success, non-0 otherwise. */
3076 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3077 {
3078         struct vcpu_vmx *vmx = to_vmx(vcpu);
3079
3080         switch (msr_index) {
3081         case MSR_IA32_VMX_BASIC:
3082                 *pdata = vmx->nested.nested_vmx_basic;
3083                 break;
3084         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3085         case MSR_IA32_VMX_PINBASED_CTLS:
3086                 *pdata = vmx_control_msr(
3087                         vmx->nested.nested_vmx_pinbased_ctls_low,
3088                         vmx->nested.nested_vmx_pinbased_ctls_high);
3089                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3090                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3091                 break;
3092         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3093         case MSR_IA32_VMX_PROCBASED_CTLS:
3094                 *pdata = vmx_control_msr(
3095                         vmx->nested.nested_vmx_procbased_ctls_low,
3096                         vmx->nested.nested_vmx_procbased_ctls_high);
3097                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3098                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3099                 break;
3100         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3101         case MSR_IA32_VMX_EXIT_CTLS:
3102                 *pdata = vmx_control_msr(
3103                         vmx->nested.nested_vmx_exit_ctls_low,
3104                         vmx->nested.nested_vmx_exit_ctls_high);
3105                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3106                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3107                 break;
3108         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3109         case MSR_IA32_VMX_ENTRY_CTLS:
3110                 *pdata = vmx_control_msr(
3111                         vmx->nested.nested_vmx_entry_ctls_low,
3112                         vmx->nested.nested_vmx_entry_ctls_high);
3113                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3114                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3115                 break;
3116         case MSR_IA32_VMX_MISC:
3117                 *pdata = vmx_control_msr(
3118                         vmx->nested.nested_vmx_misc_low,
3119                         vmx->nested.nested_vmx_misc_high);
3120                 break;
3121         case MSR_IA32_VMX_CR0_FIXED0:
3122                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3123                 break;
3124         case MSR_IA32_VMX_CR0_FIXED1:
3125                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3126                 break;
3127         case MSR_IA32_VMX_CR4_FIXED0:
3128                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3129                 break;
3130         case MSR_IA32_VMX_CR4_FIXED1:
3131                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3132                 break;
3133         case MSR_IA32_VMX_VMCS_ENUM:
3134                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3135                 break;
3136         case MSR_IA32_VMX_PROCBASED_CTLS2:
3137                 *pdata = vmx_control_msr(
3138                         vmx->nested.nested_vmx_secondary_ctls_low,
3139                         vmx->nested.nested_vmx_secondary_ctls_high);
3140                 break;
3141         case MSR_IA32_VMX_EPT_VPID_CAP:
3142                 *pdata = vmx->nested.nested_vmx_ept_caps |
3143                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3144                 break;
3145         default:
3146                 return 1;
3147         }
3148
3149         return 0;
3150 }
3151
3152 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3153                                                  uint64_t val)
3154 {
3155         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3156
3157         return !(val & ~valid_bits);
3158 }
3159
3160 /*
3161  * Reads an msr value (of 'msr_index') into 'pdata'.
3162  * Returns 0 on success, non-0 otherwise.
3163  * Assumes vcpu_load() was already called.
3164  */
3165 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3166 {
3167         struct shared_msr_entry *msr;
3168
3169         switch (msr_info->index) {
3170 #ifdef CONFIG_X86_64
3171         case MSR_FS_BASE:
3172                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3173                 break;
3174         case MSR_GS_BASE:
3175                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3176                 break;
3177         case MSR_KERNEL_GS_BASE:
3178                 vmx_load_host_state(to_vmx(vcpu));
3179                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3180                 break;
3181 #endif
3182         case MSR_EFER:
3183                 return kvm_get_msr_common(vcpu, msr_info);
3184         case MSR_IA32_TSC:
3185                 msr_info->data = guest_read_tsc(vcpu);
3186                 break;
3187         case MSR_IA32_SYSENTER_CS:
3188                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3189                 break;
3190         case MSR_IA32_SYSENTER_EIP:
3191                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3192                 break;
3193         case MSR_IA32_SYSENTER_ESP:
3194                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3195                 break;
3196         case MSR_IA32_BNDCFGS:
3197                 if (!kvm_mpx_supported())
3198                         return 1;
3199                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3200                 break;
3201         case MSR_IA32_MCG_EXT_CTL:
3202                 if (!msr_info->host_initiated &&
3203                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3204                       FEATURE_CONTROL_LMCE))
3205                         return 1;
3206                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3207                 break;
3208         case MSR_IA32_FEATURE_CONTROL:
3209                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3210                 break;
3211         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3212                 if (!nested_vmx_allowed(vcpu))
3213                         return 1;
3214                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3215         case MSR_IA32_XSS:
3216                 if (!vmx_xsaves_supported())
3217                         return 1;
3218                 msr_info->data = vcpu->arch.ia32_xss;
3219                 break;
3220         case MSR_TSC_AUX:
3221                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3222                         return 1;
3223                 /* Otherwise falls through */
3224         default:
3225                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3226                 if (msr) {
3227                         msr_info->data = msr->data;
3228                         break;
3229                 }
3230                 return kvm_get_msr_common(vcpu, msr_info);
3231         }
3232
3233         return 0;
3234 }
3235
3236 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3237
3238 /*
3239  * Writes msr value into into the appropriate "register".
3240  * Returns 0 on success, non-0 otherwise.
3241  * Assumes vcpu_load() was already called.
3242  */
3243 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3244 {
3245         struct vcpu_vmx *vmx = to_vmx(vcpu);
3246         struct shared_msr_entry *msr;
3247         int ret = 0;
3248         u32 msr_index = msr_info->index;
3249         u64 data = msr_info->data;
3250
3251         switch (msr_index) {
3252         case MSR_EFER:
3253                 ret = kvm_set_msr_common(vcpu, msr_info);
3254                 break;
3255 #ifdef CONFIG_X86_64
3256         case MSR_FS_BASE:
3257                 vmx_segment_cache_clear(vmx);
3258                 vmcs_writel(GUEST_FS_BASE, data);
3259                 break;
3260         case MSR_GS_BASE:
3261                 vmx_segment_cache_clear(vmx);
3262                 vmcs_writel(GUEST_GS_BASE, data);
3263                 break;
3264         case MSR_KERNEL_GS_BASE:
3265                 vmx_load_host_state(vmx);
3266                 vmx->msr_guest_kernel_gs_base = data;
3267                 break;
3268 #endif
3269         case MSR_IA32_SYSENTER_CS:
3270                 vmcs_write32(GUEST_SYSENTER_CS, data);
3271                 break;
3272         case MSR_IA32_SYSENTER_EIP:
3273                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3274                 break;
3275         case MSR_IA32_SYSENTER_ESP:
3276                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3277                 break;
3278         case MSR_IA32_BNDCFGS:
3279                 if (!kvm_mpx_supported())
3280                         return 1;
3281                 vmcs_write64(GUEST_BNDCFGS, data);
3282                 break;
3283         case MSR_IA32_TSC:
3284                 kvm_write_tsc(vcpu, msr_info);
3285                 break;
3286         case MSR_IA32_CR_PAT:
3287                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3288                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3289                                 return 1;
3290                         vmcs_write64(GUEST_IA32_PAT, data);
3291                         vcpu->arch.pat = data;
3292                         break;
3293                 }
3294                 ret = kvm_set_msr_common(vcpu, msr_info);
3295                 break;
3296         case MSR_IA32_TSC_ADJUST:
3297                 ret = kvm_set_msr_common(vcpu, msr_info);
3298                 break;
3299         case MSR_IA32_MCG_EXT_CTL:
3300                 if ((!msr_info->host_initiated &&
3301                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3302                        FEATURE_CONTROL_LMCE)) ||
3303                     (data & ~MCG_EXT_CTL_LMCE_EN))
3304                         return 1;
3305                 vcpu->arch.mcg_ext_ctl = data;
3306                 break;
3307         case MSR_IA32_FEATURE_CONTROL:
3308                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3309                     (to_vmx(vcpu)->msr_ia32_feature_control &
3310                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3311                         return 1;
3312                 vmx->msr_ia32_feature_control = data;
3313                 if (msr_info->host_initiated && data == 0)
3314                         vmx_leave_nested(vcpu);
3315                 break;
3316         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3317                 if (!msr_info->host_initiated)
3318                         return 1; /* they are read-only */
3319                 if (!nested_vmx_allowed(vcpu))
3320                         return 1;
3321                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3322         case MSR_IA32_XSS:
3323                 if (!vmx_xsaves_supported())
3324                         return 1;
3325                 /*
3326                  * The only supported bit as of Skylake is bit 8, but
3327                  * it is not supported on KVM.
3328                  */
3329                 if (data != 0)
3330                         return 1;
3331                 vcpu->arch.ia32_xss = data;
3332                 if (vcpu->arch.ia32_xss != host_xss)
3333                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3334                                 vcpu->arch.ia32_xss, host_xss);
3335                 else
3336                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3337                 break;
3338         case MSR_TSC_AUX:
3339                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3340                         return 1;
3341                 /* Check reserved bit, higher 32 bits should be zero */
3342                 if ((data >> 32) != 0)
3343                         return 1;
3344                 /* Otherwise falls through */
3345         default:
3346                 msr = find_msr_entry(vmx, msr_index);
3347                 if (msr) {
3348                         u64 old_msr_data = msr->data;
3349                         msr->data = data;
3350                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3351                                 preempt_disable();
3352                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3353                                                          msr->mask);
3354                                 preempt_enable();
3355                                 if (ret)
3356                                         msr->data = old_msr_data;
3357                         }
3358                         break;
3359                 }
3360                 ret = kvm_set_msr_common(vcpu, msr_info);
3361         }
3362
3363         return ret;
3364 }
3365
3366 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3367 {
3368         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3369         switch (reg) {
3370         case VCPU_REGS_RSP:
3371                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3372                 break;
3373         case VCPU_REGS_RIP:
3374                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3375                 break;
3376         case VCPU_EXREG_PDPTR:
3377                 if (enable_ept)
3378                         ept_save_pdptrs(vcpu);
3379                 break;
3380         default:
3381                 break;
3382         }
3383 }
3384
3385 static __init int cpu_has_kvm_support(void)
3386 {
3387         return cpu_has_vmx();
3388 }
3389
3390 static __init int vmx_disabled_by_bios(void)
3391 {
3392         u64 msr;
3393
3394         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3395         if (msr & FEATURE_CONTROL_LOCKED) {
3396                 /* launched w/ TXT and VMX disabled */
3397                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3398                         && tboot_enabled())
3399                         return 1;
3400                 /* launched w/o TXT and VMX only enabled w/ TXT */
3401                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3402                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3403                         && !tboot_enabled()) {
3404                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3405                                 "activate TXT before enabling KVM\n");
3406                         return 1;
3407                 }
3408                 /* launched w/o TXT and VMX disabled */
3409                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3410                         && !tboot_enabled())
3411                         return 1;
3412         }
3413
3414         return 0;
3415 }
3416
3417 static void kvm_cpu_vmxon(u64 addr)
3418 {
3419         intel_pt_handle_vmx(1);
3420
3421         asm volatile (ASM_VMX_VMXON_RAX
3422                         : : "a"(&addr), "m"(addr)
3423                         : "memory", "cc");
3424 }
3425
3426 static int hardware_enable(void)
3427 {
3428         int cpu = raw_smp_processor_id();
3429         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3430         u64 old, test_bits;
3431
3432         if (cr4_read_shadow() & X86_CR4_VMXE)
3433                 return -EBUSY;
3434
3435         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3436         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3437         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3438
3439         /*
3440          * Now we can enable the vmclear operation in kdump
3441          * since the loaded_vmcss_on_cpu list on this cpu
3442          * has been initialized.
3443          *
3444          * Though the cpu is not in VMX operation now, there
3445          * is no problem to enable the vmclear operation
3446          * for the loaded_vmcss_on_cpu list is empty!
3447          */
3448         crash_enable_local_vmclear(cpu);
3449
3450         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3451
3452         test_bits = FEATURE_CONTROL_LOCKED;
3453         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3454         if (tboot_enabled())
3455                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3456
3457         if ((old & test_bits) != test_bits) {
3458                 /* enable and lock */
3459                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3460         }
3461         cr4_set_bits(X86_CR4_VMXE);
3462
3463         if (vmm_exclusive) {
3464                 kvm_cpu_vmxon(phys_addr);
3465                 ept_sync_global();
3466         }
3467
3468         native_store_gdt(this_cpu_ptr(&host_gdt));
3469
3470         return 0;
3471 }
3472
3473 static void vmclear_local_loaded_vmcss(void)
3474 {
3475         int cpu = raw_smp_processor_id();
3476         struct loaded_vmcs *v, *n;
3477
3478         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3479                                  loaded_vmcss_on_cpu_link)
3480                 __loaded_vmcs_clear(v);
3481 }
3482
3483
3484 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3485  * tricks.
3486  */
3487 static void kvm_cpu_vmxoff(void)
3488 {
3489         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3490
3491         intel_pt_handle_vmx(0);
3492 }
3493
3494 static void hardware_disable(void)
3495 {
3496         if (vmm_exclusive) {
3497                 vmclear_local_loaded_vmcss();
3498                 kvm_cpu_vmxoff();
3499         }
3500         cr4_clear_bits(X86_CR4_VMXE);
3501 }
3502
3503 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3504                                       u32 msr, u32 *result)
3505 {
3506         u32 vmx_msr_low, vmx_msr_high;
3507         u32 ctl = ctl_min | ctl_opt;
3508
3509         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3510
3511         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3512         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3513
3514         /* Ensure minimum (required) set of control bits are supported. */
3515         if (ctl_min & ~ctl)
3516                 return -EIO;
3517
3518         *result = ctl;
3519         return 0;
3520 }
3521
3522 static __init bool allow_1_setting(u32 msr, u32 ctl)
3523 {
3524         u32 vmx_msr_low, vmx_msr_high;
3525
3526         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3527         return vmx_msr_high & ctl;
3528 }
3529
3530 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3531 {
3532         u32 vmx_msr_low, vmx_msr_high;
3533         u32 min, opt, min2, opt2;
3534         u32 _pin_based_exec_control = 0;
3535         u32 _cpu_based_exec_control = 0;
3536         u32 _cpu_based_2nd_exec_control = 0;
3537         u32 _vmexit_control = 0;
3538         u32 _vmentry_control = 0;
3539
3540         min = CPU_BASED_HLT_EXITING |
3541 #ifdef CONFIG_X86_64
3542               CPU_BASED_CR8_LOAD_EXITING |
3543               CPU_BASED_CR8_STORE_EXITING |
3544 #endif
3545               CPU_BASED_CR3_LOAD_EXITING |
3546               CPU_BASED_CR3_STORE_EXITING |
3547               CPU_BASED_USE_IO_BITMAPS |
3548               CPU_BASED_MOV_DR_EXITING |
3549               CPU_BASED_USE_TSC_OFFSETING |
3550               CPU_BASED_MWAIT_EXITING |
3551               CPU_BASED_MONITOR_EXITING |
3552               CPU_BASED_INVLPG_EXITING |
3553               CPU_BASED_RDPMC_EXITING;
3554
3555         opt = CPU_BASED_TPR_SHADOW |
3556               CPU_BASED_USE_MSR_BITMAPS |
3557               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3558         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3559                                 &_cpu_based_exec_control) < 0)
3560                 return -EIO;
3561 #ifdef CONFIG_X86_64
3562         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3563                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3564                                            ~CPU_BASED_CR8_STORE_EXITING;
3565 #endif
3566         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3567                 min2 = 0;
3568                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3569                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3570                         SECONDARY_EXEC_WBINVD_EXITING |
3571                         SECONDARY_EXEC_ENABLE_VPID |
3572                         SECONDARY_EXEC_ENABLE_EPT |
3573                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3574                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3575                         SECONDARY_EXEC_RDTSCP |
3576                         SECONDARY_EXEC_ENABLE_INVPCID |
3577                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3578                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3579                         SECONDARY_EXEC_SHADOW_VMCS |
3580                         SECONDARY_EXEC_XSAVES |
3581                         SECONDARY_EXEC_ENABLE_PML |
3582                         SECONDARY_EXEC_TSC_SCALING;
3583                 if (adjust_vmx_controls(min2, opt2,
3584                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3585                                         &_cpu_based_2nd_exec_control) < 0)
3586                         return -EIO;
3587         }
3588 #ifndef CONFIG_X86_64
3589         if (!(_cpu_based_2nd_exec_control &
3590                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3591                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3592 #endif
3593
3594         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3595                 _cpu_based_2nd_exec_control &= ~(
3596                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3597                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3598                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3599
3600         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3601                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3602                    enabled */
3603                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3604                                              CPU_BASED_CR3_STORE_EXITING |
3605                                              CPU_BASED_INVLPG_EXITING);
3606                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3607                       vmx_capability.ept, vmx_capability.vpid);
3608         }
3609
3610         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3611 #ifdef CONFIG_X86_64
3612         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3613 #endif
3614         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3615                 VM_EXIT_CLEAR_BNDCFGS;
3616         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3617                                 &_vmexit_control) < 0)
3618                 return -EIO;
3619
3620         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3621         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3622                  PIN_BASED_VMX_PREEMPTION_TIMER;
3623         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3624                                 &_pin_based_exec_control) < 0)
3625                 return -EIO;
3626
3627         if (cpu_has_broken_vmx_preemption_timer())
3628                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3629         if (!(_cpu_based_2nd_exec_control &
3630                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3631                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3632
3633         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3634         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3635         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3636                                 &_vmentry_control) < 0)
3637                 return -EIO;
3638
3639         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3640
3641         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3642         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3643                 return -EIO;
3644
3645 #ifdef CONFIG_X86_64
3646         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3647         if (vmx_msr_high & (1u<<16))
3648                 return -EIO;
3649 #endif
3650
3651         /* Require Write-Back (WB) memory type for VMCS accesses. */
3652         if (((vmx_msr_high >> 18) & 15) != 6)
3653                 return -EIO;
3654
3655         vmcs_conf->size = vmx_msr_high & 0x1fff;
3656         vmcs_conf->order = get_order(vmcs_conf->size);
3657         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3658         vmcs_conf->revision_id = vmx_msr_low;
3659
3660         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3661         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3662         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3663         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3664         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3665
3666         cpu_has_load_ia32_efer =
3667                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3668                                 VM_ENTRY_LOAD_IA32_EFER)
3669                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3670                                    VM_EXIT_LOAD_IA32_EFER);
3671
3672         cpu_has_load_perf_global_ctrl =
3673                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3674                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3675                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3676                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3677
3678         /*
3679          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3680          * but due to errata below it can't be used. Workaround is to use
3681          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3682          *
3683          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3684          *
3685          * AAK155             (model 26)
3686          * AAP115             (model 30)
3687          * AAT100             (model 37)
3688          * BC86,AAY89,BD102   (model 44)
3689          * BA97               (model 46)
3690          *
3691          */
3692         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3693                 switch (boot_cpu_data.x86_model) {
3694                 case 26:
3695                 case 30:
3696                 case 37:
3697                 case 44:
3698                 case 46:
3699                         cpu_has_load_perf_global_ctrl = false;
3700                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3701                                         "does not work properly. Using workaround\n");
3702                         break;
3703                 default:
3704                         break;
3705                 }
3706         }
3707
3708         if (boot_cpu_has(X86_FEATURE_XSAVES))
3709                 rdmsrl(MSR_IA32_XSS, host_xss);
3710
3711         return 0;
3712 }
3713
3714 static struct vmcs *alloc_vmcs_cpu(int cpu)
3715 {
3716         int node = cpu_to_node(cpu);
3717         struct page *pages;
3718         struct vmcs *vmcs;
3719
3720         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3721         if (!pages)
3722                 return NULL;
3723         vmcs = page_address(pages);
3724         memset(vmcs, 0, vmcs_config.size);
3725         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3726         return vmcs;
3727 }
3728
3729 static struct vmcs *alloc_vmcs(void)
3730 {
3731         return alloc_vmcs_cpu(raw_smp_processor_id());
3732 }
3733
3734 static void free_vmcs(struct vmcs *vmcs)
3735 {
3736         free_pages((unsigned long)vmcs, vmcs_config.order);
3737 }
3738
3739 /*
3740  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3741  */
3742 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3743 {
3744         if (!loaded_vmcs->vmcs)
3745                 return;
3746         loaded_vmcs_clear(loaded_vmcs);
3747         free_vmcs(loaded_vmcs->vmcs);
3748         loaded_vmcs->vmcs = NULL;
3749         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3750 }
3751
3752 static void free_kvm_area(void)
3753 {
3754         int cpu;
3755
3756         for_each_possible_cpu(cpu) {
3757                 free_vmcs(per_cpu(vmxarea, cpu));
3758                 per_cpu(vmxarea, cpu) = NULL;
3759         }
3760 }
3761
3762 static void init_vmcs_shadow_fields(void)
3763 {
3764         int i, j;
3765
3766         /* No checks for read only fields yet */
3767
3768         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3769                 switch (shadow_read_write_fields[i]) {
3770                 case GUEST_BNDCFGS:
3771                         if (!kvm_mpx_supported())
3772                                 continue;
3773                         break;
3774                 default:
3775                         break;
3776                 }
3777
3778                 if (j < i)
3779                         shadow_read_write_fields[j] =
3780                                 shadow_read_write_fields[i];
3781                 j++;
3782         }
3783         max_shadow_read_write_fields = j;
3784
3785         /* shadowed fields guest access without vmexit */
3786         for (i = 0; i < max_shadow_read_write_fields; i++) {
3787                 clear_bit(shadow_read_write_fields[i],
3788                           vmx_vmwrite_bitmap);
3789                 clear_bit(shadow_read_write_fields[i],
3790                           vmx_vmread_bitmap);
3791         }
3792         for (i = 0; i < max_shadow_read_only_fields; i++)
3793                 clear_bit(shadow_read_only_fields[i],
3794                           vmx_vmread_bitmap);
3795 }
3796
3797 static __init int alloc_kvm_area(void)
3798 {
3799         int cpu;
3800
3801         for_each_possible_cpu(cpu) {
3802                 struct vmcs *vmcs;
3803
3804                 vmcs = alloc_vmcs_cpu(cpu);
3805                 if (!vmcs) {
3806                         free_kvm_area();
3807                         return -ENOMEM;
3808                 }
3809
3810                 per_cpu(vmxarea, cpu) = vmcs;
3811         }
3812         return 0;
3813 }
3814
3815 static bool emulation_required(struct kvm_vcpu *vcpu)
3816 {
3817         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3818 }
3819
3820 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3821                 struct kvm_segment *save)
3822 {
3823         if (!emulate_invalid_guest_state) {
3824                 /*
3825                  * CS and SS RPL should be equal during guest entry according
3826                  * to VMX spec, but in reality it is not always so. Since vcpu
3827                  * is in the middle of the transition from real mode to
3828                  * protected mode it is safe to assume that RPL 0 is a good
3829                  * default value.
3830                  */
3831                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3832                         save->selector &= ~SEGMENT_RPL_MASK;
3833                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3834                 save->s = 1;
3835         }
3836         vmx_set_segment(vcpu, save, seg);
3837 }
3838
3839 static void enter_pmode(struct kvm_vcpu *vcpu)
3840 {
3841         unsigned long flags;
3842         struct vcpu_vmx *vmx = to_vmx(vcpu);
3843
3844         /*
3845          * Update real mode segment cache. It may be not up-to-date if sement
3846          * register was written while vcpu was in a guest mode.
3847          */
3848         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3849         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3850         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3851         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3852         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3853         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3854
3855         vmx->rmode.vm86_active = 0;
3856
3857         vmx_segment_cache_clear(vmx);
3858
3859         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3860
3861         flags = vmcs_readl(GUEST_RFLAGS);
3862         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3863         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3864         vmcs_writel(GUEST_RFLAGS, flags);
3865
3866         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3867                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3868
3869         update_exception_bitmap(vcpu);
3870
3871         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3872         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3873         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3874         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3875         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3876         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3877 }
3878
3879 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3880 {
3881         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3882         struct kvm_segment var = *save;
3883
3884         var.dpl = 0x3;
3885         if (seg == VCPU_SREG_CS)
3886                 var.type = 0x3;
3887
3888         if (!emulate_invalid_guest_state) {
3889                 var.selector = var.base >> 4;
3890                 var.base = var.base & 0xffff0;
3891                 var.limit = 0xffff;
3892                 var.g = 0;
3893                 var.db = 0;
3894                 var.present = 1;
3895                 var.s = 1;
3896                 var.l = 0;
3897                 var.unusable = 0;
3898                 var.type = 0x3;
3899                 var.avl = 0;
3900                 if (save->base & 0xf)
3901                         printk_once(KERN_WARNING "kvm: segment base is not "
3902                                         "paragraph aligned when entering "
3903                                         "protected mode (seg=%d)", seg);
3904         }
3905
3906         vmcs_write16(sf->selector, var.selector);
3907         vmcs_writel(sf->base, var.base);
3908         vmcs_write32(sf->limit, var.limit);
3909         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3910 }
3911
3912 static void enter_rmode(struct kvm_vcpu *vcpu)
3913 {
3914         unsigned long flags;
3915         struct vcpu_vmx *vmx = to_vmx(vcpu);
3916
3917         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3918         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3919         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3920         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3921         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3922         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3923         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3924
3925         vmx->rmode.vm86_active = 1;
3926
3927         /*
3928          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3929          * vcpu. Warn the user that an update is overdue.
3930          */
3931         if (!vcpu->kvm->arch.tss_addr)
3932                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3933                              "called before entering vcpu\n");
3934
3935         vmx_segment_cache_clear(vmx);
3936
3937         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3938         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3939         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3940
3941         flags = vmcs_readl(GUEST_RFLAGS);
3942         vmx->rmode.save_rflags = flags;
3943
3944         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3945
3946         vmcs_writel(GUEST_RFLAGS, flags);
3947         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3948         update_exception_bitmap(vcpu);
3949
3950         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3951         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3952         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3953         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3954         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3955         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3956
3957         kvm_mmu_reset_context(vcpu);
3958 }
3959
3960 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3961 {
3962         struct vcpu_vmx *vmx = to_vmx(vcpu);
3963         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3964
3965         if (!msr)
3966                 return;
3967
3968         /*
3969          * Force kernel_gs_base reloading before EFER changes, as control
3970          * of this msr depends on is_long_mode().
3971          */
3972         vmx_load_host_state(to_vmx(vcpu));
3973         vcpu->arch.efer = efer;
3974         if (efer & EFER_LMA) {
3975                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3976                 msr->data = efer;
3977         } else {
3978                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3979
3980                 msr->data = efer & ~EFER_LME;
3981         }
3982         setup_msrs(vmx);
3983 }
3984
3985 #ifdef CONFIG_X86_64
3986
3987 static void enter_lmode(struct kvm_vcpu *vcpu)
3988 {
3989         u32 guest_tr_ar;
3990
3991         vmx_segment_cache_clear(to_vmx(vcpu));
3992
3993         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3994         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3995                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3996                                      __func__);
3997                 vmcs_write32(GUEST_TR_AR_BYTES,
3998                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3999                              | VMX_AR_TYPE_BUSY_64_TSS);
4000         }
4001         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4002 }
4003
4004 static void exit_lmode(struct kvm_vcpu *vcpu)
4005 {
4006         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4007         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4008 }
4009
4010 #endif
4011
4012 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4013 {
4014         vpid_sync_context(vpid);
4015         if (enable_ept) {
4016                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4017                         return;
4018                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4019         }
4020 }
4021
4022 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4023 {
4024         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4025 }
4026
4027 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4028 {
4029         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4030
4031         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4032         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4033 }
4034
4035 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4036 {
4037         if (enable_ept && is_paging(vcpu))
4038                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4039         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4040 }
4041
4042 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4043 {
4044         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4045
4046         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4047         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4048 }
4049
4050 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4051 {
4052         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4053
4054         if (!test_bit(VCPU_EXREG_PDPTR,
4055                       (unsigned long *)&vcpu->arch.regs_dirty))
4056                 return;
4057
4058         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4059                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4060                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4061                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4062                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4063         }
4064 }
4065
4066 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4067 {
4068         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4069
4070         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4071                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4072                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4073                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4074                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4075         }
4076
4077         __set_bit(VCPU_EXREG_PDPTR,
4078                   (unsigned long *)&vcpu->arch.regs_avail);
4079         __set_bit(VCPU_EXREG_PDPTR,
4080                   (unsigned long *)&vcpu->arch.regs_dirty);
4081 }
4082
4083 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4084 {
4085         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4086         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4087         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4088
4089         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4090                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4091             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4092                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4093
4094         return fixed_bits_valid(val, fixed0, fixed1);
4095 }
4096
4097 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4098 {
4099         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4100         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4101
4102         return fixed_bits_valid(val, fixed0, fixed1);
4103 }
4104
4105 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4106 {
4107         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4108         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4109
4110         return fixed_bits_valid(val, fixed0, fixed1);
4111 }
4112
4113 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4114 #define nested_guest_cr4_valid  nested_cr4_valid
4115 #define nested_host_cr4_valid   nested_cr4_valid
4116
4117 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4118
4119 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4120                                         unsigned long cr0,
4121                                         struct kvm_vcpu *vcpu)
4122 {
4123         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4124                 vmx_decache_cr3(vcpu);
4125         if (!(cr0 & X86_CR0_PG)) {
4126                 /* From paging/starting to nonpaging */
4127                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4128                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4129                              (CPU_BASED_CR3_LOAD_EXITING |
4130                               CPU_BASED_CR3_STORE_EXITING));
4131                 vcpu->arch.cr0 = cr0;
4132                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4133         } else if (!is_paging(vcpu)) {
4134                 /* From nonpaging to paging */
4135                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4136                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4137                              ~(CPU_BASED_CR3_LOAD_EXITING |
4138                                CPU_BASED_CR3_STORE_EXITING));
4139                 vcpu->arch.cr0 = cr0;
4140                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4141         }
4142
4143         if (!(cr0 & X86_CR0_WP))
4144                 *hw_cr0 &= ~X86_CR0_WP;
4145 }
4146
4147 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4148 {
4149         struct vcpu_vmx *vmx = to_vmx(vcpu);
4150         unsigned long hw_cr0;
4151
4152         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4153         if (enable_unrestricted_guest)
4154                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4155         else {
4156                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4157
4158                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4159                         enter_pmode(vcpu);
4160
4161                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4162                         enter_rmode(vcpu);
4163         }
4164
4165 #ifdef CONFIG_X86_64
4166         if (vcpu->arch.efer & EFER_LME) {
4167                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4168                         enter_lmode(vcpu);
4169                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4170                         exit_lmode(vcpu);
4171         }
4172 #endif
4173
4174         if (enable_ept)
4175                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4176
4177         vmcs_writel(CR0_READ_SHADOW, cr0);
4178         vmcs_writel(GUEST_CR0, hw_cr0);
4179         vcpu->arch.cr0 = cr0;
4180
4181         /* depends on vcpu->arch.cr0 to be set to a new value */
4182         vmx->emulation_required = emulation_required(vcpu);
4183 }
4184
4185 static u64 construct_eptp(unsigned long root_hpa)
4186 {
4187         u64 eptp;
4188
4189         /* TODO write the value reading from MSR */
4190         eptp = VMX_EPT_DEFAULT_MT |
4191                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4192         if (enable_ept_ad_bits)
4193                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4194         eptp |= (root_hpa & PAGE_MASK);
4195
4196         return eptp;
4197 }
4198
4199 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4200 {
4201         unsigned long guest_cr3;
4202         u64 eptp;
4203
4204         guest_cr3 = cr3;
4205         if (enable_ept) {
4206                 eptp = construct_eptp(cr3);
4207                 vmcs_write64(EPT_POINTER, eptp);
4208                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4209                         guest_cr3 = kvm_read_cr3(vcpu);
4210                 else
4211                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4212                 ept_load_pdptrs(vcpu);
4213         }
4214
4215         vmx_flush_tlb(vcpu);
4216         vmcs_writel(GUEST_CR3, guest_cr3);
4217 }
4218
4219 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4220 {
4221         /*
4222          * Pass through host's Machine Check Enable value to hw_cr4, which
4223          * is in force while we are in guest mode.  Do not let guests control
4224          * this bit, even if host CR4.MCE == 0.
4225          */
4226         unsigned long hw_cr4 =
4227                 (cr4_read_shadow() & X86_CR4_MCE) |
4228                 (cr4 & ~X86_CR4_MCE) |
4229                 (to_vmx(vcpu)->rmode.vm86_active ?
4230                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4231
4232         if (cr4 & X86_CR4_VMXE) {
4233                 /*
4234                  * To use VMXON (and later other VMX instructions), a guest
4235                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4236                  * So basically the check on whether to allow nested VMX
4237                  * is here.
4238                  */
4239                 if (!nested_vmx_allowed(vcpu))
4240                         return 1;
4241         }
4242
4243         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4244                 return 1;
4245
4246         vcpu->arch.cr4 = cr4;
4247         if (enable_ept) {
4248                 if (!is_paging(vcpu)) {
4249                         hw_cr4 &= ~X86_CR4_PAE;
4250                         hw_cr4 |= X86_CR4_PSE;
4251                 } else if (!(cr4 & X86_CR4_PAE)) {
4252                         hw_cr4 &= ~X86_CR4_PAE;
4253                 }
4254         }
4255
4256         if (!enable_unrestricted_guest && !is_paging(vcpu))
4257                 /*
4258                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4259                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4260                  * to be manually disabled when guest switches to non-paging
4261                  * mode.
4262                  *
4263                  * If !enable_unrestricted_guest, the CPU is always running
4264                  * with CR0.PG=1 and CR4 needs to be modified.
4265                  * If enable_unrestricted_guest, the CPU automatically
4266                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4267                  */
4268                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4269
4270         vmcs_writel(CR4_READ_SHADOW, cr4);
4271         vmcs_writel(GUEST_CR4, hw_cr4);
4272         return 0;
4273 }
4274
4275 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4276                             struct kvm_segment *var, int seg)
4277 {
4278         struct vcpu_vmx *vmx = to_vmx(vcpu);
4279         u32 ar;
4280
4281         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4282                 *var = vmx->rmode.segs[seg];
4283                 if (seg == VCPU_SREG_TR
4284                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4285                         return;
4286                 var->base = vmx_read_guest_seg_base(vmx, seg);
4287                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4288                 return;
4289         }
4290         var->base = vmx_read_guest_seg_base(vmx, seg);
4291         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4292         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4293         ar = vmx_read_guest_seg_ar(vmx, seg);
4294         var->unusable = (ar >> 16) & 1;
4295         var->type = ar & 15;
4296         var->s = (ar >> 4) & 1;
4297         var->dpl = (ar >> 5) & 3;
4298         /*
4299          * Some userspaces do not preserve unusable property. Since usable
4300          * segment has to be present according to VMX spec we can use present
4301          * property to amend userspace bug by making unusable segment always
4302          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4303          * segment as unusable.
4304          */
4305         var->present = !var->unusable;
4306         var->avl = (ar >> 12) & 1;
4307         var->l = (ar >> 13) & 1;
4308         var->db = (ar >> 14) & 1;
4309         var->g = (ar >> 15) & 1;
4310 }
4311
4312 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4313 {
4314         struct kvm_segment s;
4315
4316         if (to_vmx(vcpu)->rmode.vm86_active) {
4317                 vmx_get_segment(vcpu, &s, seg);
4318                 return s.base;
4319         }
4320         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4321 }
4322
4323 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4324 {
4325         struct vcpu_vmx *vmx = to_vmx(vcpu);
4326
4327         if (unlikely(vmx->rmode.vm86_active))
4328                 return 0;
4329         else {
4330                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4331                 return VMX_AR_DPL(ar);
4332         }
4333 }
4334
4335 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4336 {
4337         u32 ar;
4338
4339         if (var->unusable || !var->present)
4340                 ar = 1 << 16;
4341         else {
4342                 ar = var->type & 15;
4343                 ar |= (var->s & 1) << 4;
4344                 ar |= (var->dpl & 3) << 5;
4345                 ar |= (var->present & 1) << 7;
4346                 ar |= (var->avl & 1) << 12;
4347                 ar |= (var->l & 1) << 13;
4348                 ar |= (var->db & 1) << 14;
4349                 ar |= (var->g & 1) << 15;
4350         }
4351
4352         return ar;
4353 }
4354
4355 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4356                             struct kvm_segment *var, int seg)
4357 {
4358         struct vcpu_vmx *vmx = to_vmx(vcpu);
4359         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4360
4361         vmx_segment_cache_clear(vmx);
4362
4363         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4364                 vmx->rmode.segs[seg] = *var;
4365                 if (seg == VCPU_SREG_TR)
4366                         vmcs_write16(sf->selector, var->selector);
4367                 else if (var->s)
4368                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4369                 goto out;
4370         }
4371
4372         vmcs_writel(sf->base, var->base);
4373         vmcs_write32(sf->limit, var->limit);
4374         vmcs_write16(sf->selector, var->selector);
4375
4376         /*
4377          *   Fix the "Accessed" bit in AR field of segment registers for older
4378          * qemu binaries.
4379          *   IA32 arch specifies that at the time of processor reset the
4380          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4381          * is setting it to 0 in the userland code. This causes invalid guest
4382          * state vmexit when "unrestricted guest" mode is turned on.
4383          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4384          * tree. Newer qemu binaries with that qemu fix would not need this
4385          * kvm hack.
4386          */
4387         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4388                 var->type |= 0x1; /* Accessed */
4389
4390         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4391
4392 out:
4393         vmx->emulation_required = emulation_required(vcpu);
4394 }
4395
4396 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4397 {
4398         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4399
4400         *db = (ar >> 14) & 1;
4401         *l = (ar >> 13) & 1;
4402 }
4403
4404 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4405 {
4406         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4407         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4408 }
4409
4410 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4411 {
4412         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4413         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4414 }
4415
4416 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4417 {
4418         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4419         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4420 }
4421
4422 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4423 {
4424         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4425         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4426 }
4427
4428 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4429 {
4430         struct kvm_segment var;
4431         u32 ar;
4432
4433         vmx_get_segment(vcpu, &var, seg);
4434         var.dpl = 0x3;
4435         if (seg == VCPU_SREG_CS)
4436                 var.type = 0x3;
4437         ar = vmx_segment_access_rights(&var);
4438
4439         if (var.base != (var.selector << 4))
4440                 return false;
4441         if (var.limit != 0xffff)
4442                 return false;
4443         if (ar != 0xf3)
4444                 return false;
4445
4446         return true;
4447 }
4448
4449 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4450 {
4451         struct kvm_segment cs;
4452         unsigned int cs_rpl;
4453
4454         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4455         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4456
4457         if (cs.unusable)
4458                 return false;
4459         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4460                 return false;
4461         if (!cs.s)
4462                 return false;
4463         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4464                 if (cs.dpl > cs_rpl)
4465                         return false;
4466         } else {
4467                 if (cs.dpl != cs_rpl)
4468                         return false;
4469         }
4470         if (!cs.present)
4471                 return false;
4472
4473         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4474         return true;
4475 }
4476
4477 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4478 {
4479         struct kvm_segment ss;
4480         unsigned int ss_rpl;
4481
4482         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4483         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4484
4485         if (ss.unusable)
4486                 return true;
4487         if (ss.type != 3 && ss.type != 7)
4488                 return false;
4489         if (!ss.s)
4490                 return false;
4491         if (ss.dpl != ss_rpl) /* DPL != RPL */
4492                 return false;
4493         if (!ss.present)
4494                 return false;
4495
4496         return true;
4497 }
4498
4499 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4500 {
4501         struct kvm_segment var;
4502         unsigned int rpl;
4503
4504         vmx_get_segment(vcpu, &var, seg);
4505         rpl = var.selector & SEGMENT_RPL_MASK;
4506
4507         if (var.unusable)
4508                 return true;
4509         if (!var.s)
4510                 return false;
4511         if (!var.present)
4512                 return false;
4513         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4514                 if (var.dpl < rpl) /* DPL < RPL */
4515                         return false;
4516         }
4517
4518         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4519          * rights flags
4520          */
4521         return true;
4522 }
4523
4524 static bool tr_valid(struct kvm_vcpu *vcpu)
4525 {
4526         struct kvm_segment tr;
4527
4528         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4529
4530         if (tr.unusable)
4531                 return false;
4532         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4533                 return false;
4534         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4535                 return false;
4536         if (!tr.present)
4537                 return false;
4538
4539         return true;
4540 }
4541
4542 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4543 {
4544         struct kvm_segment ldtr;
4545
4546         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4547
4548         if (ldtr.unusable)
4549                 return true;
4550         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4551                 return false;
4552         if (ldtr.type != 2)
4553                 return false;
4554         if (!ldtr.present)
4555                 return false;
4556
4557         return true;
4558 }
4559
4560 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4561 {
4562         struct kvm_segment cs, ss;
4563
4564         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4565         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4566
4567         return ((cs.selector & SEGMENT_RPL_MASK) ==
4568                  (ss.selector & SEGMENT_RPL_MASK));
4569 }
4570
4571 /*
4572  * Check if guest state is valid. Returns true if valid, false if
4573  * not.
4574  * We assume that registers are always usable
4575  */
4576 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4577 {
4578         if (enable_unrestricted_guest)
4579                 return true;
4580
4581         /* real mode guest state checks */
4582         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4583                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4584                         return false;
4585                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4586                         return false;
4587                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4588                         return false;
4589                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4590                         return false;
4591                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4592                         return false;
4593                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4594                         return false;
4595         } else {
4596         /* protected mode guest state checks */
4597                 if (!cs_ss_rpl_check(vcpu))
4598                         return false;
4599                 if (!code_segment_valid(vcpu))
4600                         return false;
4601                 if (!stack_segment_valid(vcpu))
4602                         return false;
4603                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4604                         return false;
4605                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4606                         return false;
4607                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4608                         return false;
4609                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4610                         return false;
4611                 if (!tr_valid(vcpu))
4612                         return false;
4613                 if (!ldtr_valid(vcpu))
4614                         return false;
4615         }
4616         /* TODO:
4617          * - Add checks on RIP
4618          * - Add checks on RFLAGS
4619          */
4620
4621         return true;
4622 }
4623
4624 static int init_rmode_tss(struct kvm *kvm)
4625 {
4626         gfn_t fn;
4627         u16 data = 0;
4628         int idx, r;
4629
4630         idx = srcu_read_lock(&kvm->srcu);
4631         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4632         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4633         if (r < 0)
4634                 goto out;
4635         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4636         r = kvm_write_guest_page(kvm, fn++, &data,
4637                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4638         if (r < 0)
4639                 goto out;
4640         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4641         if (r < 0)
4642                 goto out;
4643         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4644         if (r < 0)
4645                 goto out;
4646         data = ~0;
4647         r = kvm_write_guest_page(kvm, fn, &data,
4648                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4649                                  sizeof(u8));
4650 out:
4651         srcu_read_unlock(&kvm->srcu, idx);
4652         return r;
4653 }
4654
4655 static int init_rmode_identity_map(struct kvm *kvm)
4656 {
4657         int i, idx, r = 0;
4658         kvm_pfn_t identity_map_pfn;
4659         u32 tmp;
4660
4661         if (!enable_ept)
4662                 return 0;
4663
4664         /* Protect kvm->arch.ept_identity_pagetable_done. */
4665         mutex_lock(&kvm->slots_lock);
4666
4667         if (likely(kvm->arch.ept_identity_pagetable_done))
4668                 goto out2;
4669
4670         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4671
4672         r = alloc_identity_pagetable(kvm);
4673         if (r < 0)
4674                 goto out2;
4675
4676         idx = srcu_read_lock(&kvm->srcu);
4677         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4678         if (r < 0)
4679                 goto out;
4680         /* Set up identity-mapping pagetable for EPT in real mode */
4681         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4682                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4683                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4684                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4685                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4686                 if (r < 0)
4687                         goto out;
4688         }
4689         kvm->arch.ept_identity_pagetable_done = true;
4690
4691 out:
4692         srcu_read_unlock(&kvm->srcu, idx);
4693
4694 out2:
4695         mutex_unlock(&kvm->slots_lock);
4696         return r;
4697 }
4698
4699 static void seg_setup(int seg)
4700 {
4701         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4702         unsigned int ar;
4703
4704         vmcs_write16(sf->selector, 0);
4705         vmcs_writel(sf->base, 0);
4706         vmcs_write32(sf->limit, 0xffff);
4707         ar = 0x93;
4708         if (seg == VCPU_SREG_CS)
4709                 ar |= 0x08; /* code segment */
4710
4711         vmcs_write32(sf->ar_bytes, ar);
4712 }
4713
4714 static int alloc_apic_access_page(struct kvm *kvm)
4715 {
4716         struct page *page;
4717         int r = 0;
4718
4719         mutex_lock(&kvm->slots_lock);
4720         if (kvm->arch.apic_access_page_done)
4721                 goto out;
4722         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4723                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4724         if (r)
4725                 goto out;
4726
4727         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4728         if (is_error_page(page)) {
4729                 r = -EFAULT;
4730                 goto out;
4731         }
4732
4733         /*
4734          * Do not pin the page in memory, so that memory hot-unplug
4735          * is able to migrate it.
4736          */
4737         put_page(page);
4738         kvm->arch.apic_access_page_done = true;
4739 out:
4740         mutex_unlock(&kvm->slots_lock);
4741         return r;
4742 }
4743
4744 static int alloc_identity_pagetable(struct kvm *kvm)
4745 {
4746         /* Called with kvm->slots_lock held. */
4747
4748         int r = 0;
4749
4750         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4751
4752         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4753                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4754
4755         return r;
4756 }
4757
4758 static int allocate_vpid(void)
4759 {
4760         int vpid;
4761
4762         if (!enable_vpid)
4763                 return 0;
4764         spin_lock(&vmx_vpid_lock);
4765         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4766         if (vpid < VMX_NR_VPIDS)
4767                 __set_bit(vpid, vmx_vpid_bitmap);
4768         else
4769                 vpid = 0;
4770         spin_unlock(&vmx_vpid_lock);
4771         return vpid;
4772 }
4773
4774 static void free_vpid(int vpid)
4775 {
4776         if (!enable_vpid || vpid == 0)
4777                 return;
4778         spin_lock(&vmx_vpid_lock);
4779         __clear_bit(vpid, vmx_vpid_bitmap);
4780         spin_unlock(&vmx_vpid_lock);
4781 }
4782
4783 #define MSR_TYPE_R      1
4784 #define MSR_TYPE_W      2
4785 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4786                                                 u32 msr, int type)
4787 {
4788         int f = sizeof(unsigned long);
4789
4790         if (!cpu_has_vmx_msr_bitmap())
4791                 return;
4792
4793         /*
4794          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4795          * have the write-low and read-high bitmap offsets the wrong way round.
4796          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4797          */
4798         if (msr <= 0x1fff) {
4799                 if (type & MSR_TYPE_R)
4800                         /* read-low */
4801                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4802
4803                 if (type & MSR_TYPE_W)
4804                         /* write-low */
4805                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4806
4807         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4808                 msr &= 0x1fff;
4809                 if (type & MSR_TYPE_R)
4810                         /* read-high */
4811                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4812
4813                 if (type & MSR_TYPE_W)
4814                         /* write-high */
4815                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4816
4817         }
4818 }
4819
4820 /*
4821  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4822  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4823  */
4824 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4825                                                unsigned long *msr_bitmap_nested,
4826                                                u32 msr, int type)
4827 {
4828         int f = sizeof(unsigned long);
4829
4830         if (!cpu_has_vmx_msr_bitmap()) {
4831                 WARN_ON(1);
4832                 return;
4833         }
4834
4835         /*
4836          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4837          * have the write-low and read-high bitmap offsets the wrong way round.
4838          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4839          */
4840         if (msr <= 0x1fff) {
4841                 if (type & MSR_TYPE_R &&
4842                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4843                         /* read-low */
4844                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4845
4846                 if (type & MSR_TYPE_W &&
4847                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4848                         /* write-low */
4849                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4850
4851         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4852                 msr &= 0x1fff;
4853                 if (type & MSR_TYPE_R &&
4854                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4855                         /* read-high */
4856                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4857
4858                 if (type & MSR_TYPE_W &&
4859                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4860                         /* write-high */
4861                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4862
4863         }
4864 }
4865
4866 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4867 {
4868         if (!longmode_only)
4869                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4870                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4871         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4872                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4873 }
4874
4875 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4876 {
4877         if (apicv_active) {
4878                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4879                                 msr, type);
4880                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4881                                 msr, type);
4882         } else {
4883                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4884                                 msr, type);
4885                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4886                                 msr, type);
4887         }
4888 }
4889
4890 static bool vmx_get_enable_apicv(void)
4891 {
4892         return enable_apicv;
4893 }
4894
4895 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4896 {
4897         struct vcpu_vmx *vmx = to_vmx(vcpu);
4898         int max_irr;
4899         void *vapic_page;
4900         u16 status;
4901
4902         if (vmx->nested.pi_desc &&
4903             vmx->nested.pi_pending) {
4904                 vmx->nested.pi_pending = false;
4905                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4906                         return;
4907
4908                 max_irr = find_last_bit(
4909                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4910
4911                 if (max_irr == 256)
4912                         return;
4913
4914                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4915                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4916                 kunmap(vmx->nested.virtual_apic_page);
4917
4918                 status = vmcs_read16(GUEST_INTR_STATUS);
4919                 if ((u8)max_irr > ((u8)status & 0xff)) {
4920                         status &= ~0xff;
4921                         status |= (u8)max_irr;
4922                         vmcs_write16(GUEST_INTR_STATUS, status);
4923                 }
4924         }
4925 }
4926
4927 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4928 {
4929 #ifdef CONFIG_SMP
4930         if (vcpu->mode == IN_GUEST_MODE) {
4931                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4932
4933                 /*
4934                  * Currently, we don't support urgent interrupt,
4935                  * all interrupts are recognized as non-urgent
4936                  * interrupt, so we cannot post interrupts when
4937                  * 'SN' is set.
4938                  *
4939                  * If the vcpu is in guest mode, it means it is
4940                  * running instead of being scheduled out and
4941                  * waiting in the run queue, and that's the only
4942                  * case when 'SN' is set currently, warning if
4943                  * 'SN' is set.
4944                  */
4945                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4946
4947                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4948                                 POSTED_INTR_VECTOR);
4949                 return true;
4950         }
4951 #endif
4952         return false;
4953 }
4954
4955 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4956                                                 int vector)
4957 {
4958         struct vcpu_vmx *vmx = to_vmx(vcpu);
4959
4960         if (is_guest_mode(vcpu) &&
4961             vector == vmx->nested.posted_intr_nv) {
4962                 /* the PIR and ON have been set by L1. */
4963                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4964                 /*
4965                  * If a posted intr is not recognized by hardware,
4966                  * we will accomplish it in the next vmentry.
4967                  */
4968                 vmx->nested.pi_pending = true;
4969                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4970                 return 0;
4971         }
4972         return -1;
4973 }
4974 /*
4975  * Send interrupt to vcpu via posted interrupt way.
4976  * 1. If target vcpu is running(non-root mode), send posted interrupt
4977  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4978  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4979  * interrupt from PIR in next vmentry.
4980  */
4981 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4982 {
4983         struct vcpu_vmx *vmx = to_vmx(vcpu);
4984         int r;
4985
4986         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4987         if (!r)
4988                 return;
4989
4990         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4991                 return;
4992
4993         /* If a previous notification has sent the IPI, nothing to do.  */
4994         if (pi_test_and_set_on(&vmx->pi_desc))
4995                 return;
4996
4997         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
4998                 kvm_vcpu_kick(vcpu);
4999 }
5000
5001 /*
5002  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5003  * will not change in the lifetime of the guest.
5004  * Note that host-state that does change is set elsewhere. E.g., host-state
5005  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5006  */
5007 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5008 {
5009         u32 low32, high32;
5010         unsigned long tmpl;
5011         struct desc_ptr dt;
5012         unsigned long cr0, cr4;
5013
5014         cr0 = read_cr0();
5015         WARN_ON(cr0 & X86_CR0_TS);
5016         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5017         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5018
5019         /* Save the most likely value for this task's CR4 in the VMCS. */
5020         cr4 = cr4_read_shadow();
5021         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5022         vmx->host_state.vmcs_host_cr4 = cr4;
5023
5024         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5025 #ifdef CONFIG_X86_64
5026         /*
5027          * Load null selectors, so we can avoid reloading them in
5028          * __vmx_load_host_state(), in case userspace uses the null selectors
5029          * too (the expected case).
5030          */
5031         vmcs_write16(HOST_DS_SELECTOR, 0);
5032         vmcs_write16(HOST_ES_SELECTOR, 0);
5033 #else
5034         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5035         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5036 #endif
5037         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5038         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5039
5040         native_store_idt(&dt);
5041         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5042         vmx->host_idt_base = dt.address;
5043
5044         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5045
5046         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5047         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5048         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5049         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5050
5051         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5052                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5053                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5054         }
5055 }
5056
5057 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5058 {
5059         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5060         if (enable_ept)
5061                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5062         if (is_guest_mode(&vmx->vcpu))
5063                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5064                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5065         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5066 }
5067
5068 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5069 {
5070         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5071
5072         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5073                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5074         /* Enable the preemption timer dynamically */
5075         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5076         return pin_based_exec_ctrl;
5077 }
5078
5079 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5080 {
5081         struct vcpu_vmx *vmx = to_vmx(vcpu);
5082
5083         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5084         if (cpu_has_secondary_exec_ctrls()) {
5085                 if (kvm_vcpu_apicv_active(vcpu))
5086                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5087                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5088                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5089                 else
5090                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5091                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5092                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5093         }
5094
5095         if (cpu_has_vmx_msr_bitmap())
5096                 vmx_set_msr_bitmap(vcpu);
5097 }
5098
5099 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5100 {
5101         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5102
5103         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5104                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5105
5106         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5107                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5108 #ifdef CONFIG_X86_64
5109                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5110                                 CPU_BASED_CR8_LOAD_EXITING;
5111 #endif
5112         }
5113         if (!enable_ept)
5114                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5115                                 CPU_BASED_CR3_LOAD_EXITING  |
5116                                 CPU_BASED_INVLPG_EXITING;
5117         return exec_control;
5118 }
5119
5120 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5121 {
5122         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5123         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5124                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5125         if (vmx->vpid == 0)
5126                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5127         if (!enable_ept) {
5128                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5129                 enable_unrestricted_guest = 0;
5130                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5131                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5132         }
5133         if (!enable_unrestricted_guest)
5134                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5135         if (!ple_gap)
5136                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5137         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5138                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5139                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5140         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5141         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5142            (handle_vmptrld).
5143            We can NOT enable shadow_vmcs here because we don't have yet
5144            a current VMCS12
5145         */
5146         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5147
5148         if (!enable_pml)
5149                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5150
5151         return exec_control;
5152 }
5153
5154 static void ept_set_mmio_spte_mask(void)
5155 {
5156         /*
5157          * EPT Misconfigurations can be generated if the value of bits 2:0
5158          * of an EPT paging-structure entry is 110b (write/execute).
5159          */
5160         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5161 }
5162
5163 #define VMX_XSS_EXIT_BITMAP 0
5164 /*
5165  * Sets up the vmcs for emulated real mode.
5166  */
5167 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5168 {
5169 #ifdef CONFIG_X86_64
5170         unsigned long a;
5171 #endif
5172         int i;
5173
5174         /* I/O */
5175         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5176         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5177
5178         if (enable_shadow_vmcs) {
5179                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5180                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5181         }
5182         if (cpu_has_vmx_msr_bitmap())
5183                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5184
5185         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5186
5187         /* Control */
5188         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5189         vmx->hv_deadline_tsc = -1;
5190
5191         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5192
5193         if (cpu_has_secondary_exec_ctrls()) {
5194                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5195                                 vmx_secondary_exec_control(vmx));
5196         }
5197
5198         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5199                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5200                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5201                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5202                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5203
5204                 vmcs_write16(GUEST_INTR_STATUS, 0);
5205
5206                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5207                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5208         }
5209
5210         if (ple_gap) {
5211                 vmcs_write32(PLE_GAP, ple_gap);
5212                 vmx->ple_window = ple_window;
5213                 vmx->ple_window_dirty = true;
5214         }
5215
5216         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5217         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5218         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5219
5220         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5221         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5222         vmx_set_constant_host_state(vmx);
5223 #ifdef CONFIG_X86_64
5224         rdmsrl(MSR_FS_BASE, a);
5225         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5226         rdmsrl(MSR_GS_BASE, a);
5227         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5228 #else
5229         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5230         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5231 #endif
5232
5233         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5234         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5235         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5236         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5237         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5238
5239         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5240                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5241
5242         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5243                 u32 index = vmx_msr_index[i];
5244                 u32 data_low, data_high;
5245                 int j = vmx->nmsrs;
5246
5247                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5248                         continue;
5249                 if (wrmsr_safe(index, data_low, data_high) < 0)
5250                         continue;
5251                 vmx->guest_msrs[j].index = i;
5252                 vmx->guest_msrs[j].data = 0;
5253                 vmx->guest_msrs[j].mask = -1ull;
5254                 ++vmx->nmsrs;
5255         }
5256
5257
5258         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5259
5260         /* 22.2.1, 20.8.1 */
5261         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5262
5263         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5264         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5265
5266         set_cr4_guest_host_mask(vmx);
5267
5268         if (vmx_xsaves_supported())
5269                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5270
5271         if (enable_pml) {
5272                 ASSERT(vmx->pml_pg);
5273                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5274                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5275         }
5276
5277         return 0;
5278 }
5279
5280 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5281 {
5282         struct vcpu_vmx *vmx = to_vmx(vcpu);
5283         struct msr_data apic_base_msr;
5284         u64 cr0;
5285
5286         vmx->rmode.vm86_active = 0;
5287
5288         vmx->soft_vnmi_blocked = 0;
5289
5290         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5291         kvm_set_cr8(vcpu, 0);
5292
5293         if (!init_event) {
5294                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5295                                      MSR_IA32_APICBASE_ENABLE;
5296                 if (kvm_vcpu_is_reset_bsp(vcpu))
5297                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5298                 apic_base_msr.host_initiated = true;
5299                 kvm_set_apic_base(vcpu, &apic_base_msr);
5300         }
5301
5302         vmx_segment_cache_clear(vmx);
5303
5304         seg_setup(VCPU_SREG_CS);
5305         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5306         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5307
5308         seg_setup(VCPU_SREG_DS);
5309         seg_setup(VCPU_SREG_ES);
5310         seg_setup(VCPU_SREG_FS);
5311         seg_setup(VCPU_SREG_GS);
5312         seg_setup(VCPU_SREG_SS);
5313
5314         vmcs_write16(GUEST_TR_SELECTOR, 0);
5315         vmcs_writel(GUEST_TR_BASE, 0);
5316         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5317         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5318
5319         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5320         vmcs_writel(GUEST_LDTR_BASE, 0);
5321         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5322         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5323
5324         if (!init_event) {
5325                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5326                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5327                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5328                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5329         }
5330
5331         vmcs_writel(GUEST_RFLAGS, 0x02);
5332         kvm_rip_write(vcpu, 0xfff0);
5333
5334         vmcs_writel(GUEST_GDTR_BASE, 0);
5335         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5336
5337         vmcs_writel(GUEST_IDTR_BASE, 0);
5338         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5339
5340         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5341         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5342         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5343
5344         setup_msrs(vmx);
5345
5346         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5347
5348         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5349                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5350                 if (cpu_need_tpr_shadow(vcpu))
5351                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5352                                      __pa(vcpu->arch.apic->regs));
5353                 vmcs_write32(TPR_THRESHOLD, 0);
5354         }
5355
5356         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5357
5358         if (kvm_vcpu_apicv_active(vcpu))
5359                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5360
5361         if (vmx->vpid != 0)
5362                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5363
5364         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5365         vmx->vcpu.arch.cr0 = cr0;
5366         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5367         vmx_set_cr4(vcpu, 0);
5368         vmx_set_efer(vcpu, 0);
5369
5370         update_exception_bitmap(vcpu);
5371
5372         vpid_sync_context(vmx->vpid);
5373 }
5374
5375 /*
5376  * In nested virtualization, check if L1 asked to exit on external interrupts.
5377  * For most existing hypervisors, this will always return true.
5378  */
5379 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5380 {
5381         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5382                 PIN_BASED_EXT_INTR_MASK;
5383 }
5384
5385 /*
5386  * In nested virtualization, check if L1 has set
5387  * VM_EXIT_ACK_INTR_ON_EXIT
5388  */
5389 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5390 {
5391         return get_vmcs12(vcpu)->vm_exit_controls &
5392                 VM_EXIT_ACK_INTR_ON_EXIT;
5393 }
5394
5395 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5396 {
5397         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5398                 PIN_BASED_NMI_EXITING;
5399 }
5400
5401 static void enable_irq_window(struct kvm_vcpu *vcpu)
5402 {
5403         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5404                       CPU_BASED_VIRTUAL_INTR_PENDING);
5405 }
5406
5407 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5408 {
5409         if (!cpu_has_virtual_nmis() ||
5410             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5411                 enable_irq_window(vcpu);
5412                 return;
5413         }
5414
5415         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5416                       CPU_BASED_VIRTUAL_NMI_PENDING);
5417 }
5418
5419 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5420 {
5421         struct vcpu_vmx *vmx = to_vmx(vcpu);
5422         uint32_t intr;
5423         int irq = vcpu->arch.interrupt.nr;
5424
5425         trace_kvm_inj_virq(irq);
5426
5427         ++vcpu->stat.irq_injections;
5428         if (vmx->rmode.vm86_active) {
5429                 int inc_eip = 0;
5430                 if (vcpu->arch.interrupt.soft)
5431                         inc_eip = vcpu->arch.event_exit_inst_len;
5432                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5433                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5434                 return;
5435         }
5436         intr = irq | INTR_INFO_VALID_MASK;
5437         if (vcpu->arch.interrupt.soft) {
5438                 intr |= INTR_TYPE_SOFT_INTR;
5439                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5440                              vmx->vcpu.arch.event_exit_inst_len);
5441         } else
5442                 intr |= INTR_TYPE_EXT_INTR;
5443         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5444 }
5445
5446 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5447 {
5448         struct vcpu_vmx *vmx = to_vmx(vcpu);
5449
5450         if (!is_guest_mode(vcpu)) {
5451                 if (!cpu_has_virtual_nmis()) {
5452                         /*
5453                          * Tracking the NMI-blocked state in software is built upon
5454                          * finding the next open IRQ window. This, in turn, depends on
5455                          * well-behaving guests: They have to keep IRQs disabled at
5456                          * least as long as the NMI handler runs. Otherwise we may
5457                          * cause NMI nesting, maybe breaking the guest. But as this is
5458                          * highly unlikely, we can live with the residual risk.
5459                          */
5460                         vmx->soft_vnmi_blocked = 1;
5461                         vmx->vnmi_blocked_time = 0;
5462                 }
5463
5464                 ++vcpu->stat.nmi_injections;
5465                 vmx->nmi_known_unmasked = false;
5466         }
5467
5468         if (vmx->rmode.vm86_active) {
5469                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5470                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5471                 return;
5472         }
5473
5474         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5475                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5476 }
5477
5478 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5479 {
5480         if (!cpu_has_virtual_nmis())
5481                 return to_vmx(vcpu)->soft_vnmi_blocked;
5482         if (to_vmx(vcpu)->nmi_known_unmasked)
5483                 return false;
5484         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5485 }
5486
5487 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5488 {
5489         struct vcpu_vmx *vmx = to_vmx(vcpu);
5490
5491         if (!cpu_has_virtual_nmis()) {
5492                 if (vmx->soft_vnmi_blocked != masked) {
5493                         vmx->soft_vnmi_blocked = masked;
5494                         vmx->vnmi_blocked_time = 0;
5495                 }
5496         } else {
5497                 vmx->nmi_known_unmasked = !masked;
5498                 if (masked)
5499                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5500                                       GUEST_INTR_STATE_NMI);
5501                 else
5502                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5503                                         GUEST_INTR_STATE_NMI);
5504         }
5505 }
5506
5507 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5508 {
5509         if (to_vmx(vcpu)->nested.nested_run_pending)
5510                 return 0;
5511
5512         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5513                 return 0;
5514
5515         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5516                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5517                    | GUEST_INTR_STATE_NMI));
5518 }
5519
5520 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5521 {
5522         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5523                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5524                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5525                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5526 }
5527
5528 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5529 {
5530         int ret;
5531
5532         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5533                                     PAGE_SIZE * 3);
5534         if (ret)
5535                 return ret;
5536         kvm->arch.tss_addr = addr;
5537         return init_rmode_tss(kvm);
5538 }
5539
5540 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5541 {
5542         switch (vec) {
5543         case BP_VECTOR:
5544                 /*
5545                  * Update instruction length as we may reinject the exception
5546                  * from user space while in guest debugging mode.
5547                  */
5548                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5549                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5550                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5551                         return false;
5552                 /* fall through */
5553         case DB_VECTOR:
5554                 if (vcpu->guest_debug &
5555                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5556                         return false;
5557                 /* fall through */
5558         case DE_VECTOR:
5559         case OF_VECTOR:
5560         case BR_VECTOR:
5561         case UD_VECTOR:
5562         case DF_VECTOR:
5563         case SS_VECTOR:
5564         case GP_VECTOR:
5565         case MF_VECTOR:
5566                 return true;
5567         break;
5568         }
5569         return false;
5570 }
5571
5572 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5573                                   int vec, u32 err_code)
5574 {
5575         /*
5576          * Instruction with address size override prefix opcode 0x67
5577          * Cause the #SS fault with 0 error code in VM86 mode.
5578          */
5579         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5580                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5581                         if (vcpu->arch.halt_request) {
5582                                 vcpu->arch.halt_request = 0;
5583                                 return kvm_vcpu_halt(vcpu);
5584                         }
5585                         return 1;
5586                 }
5587                 return 0;
5588         }
5589
5590         /*
5591          * Forward all other exceptions that are valid in real mode.
5592          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5593          *        the required debugging infrastructure rework.
5594          */
5595         kvm_queue_exception(vcpu, vec);
5596         return 1;
5597 }
5598
5599 /*
5600  * Trigger machine check on the host. We assume all the MSRs are already set up
5601  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5602  * We pass a fake environment to the machine check handler because we want
5603  * the guest to be always treated like user space, no matter what context
5604  * it used internally.
5605  */
5606 static void kvm_machine_check(void)
5607 {
5608 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5609         struct pt_regs regs = {
5610                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5611                 .flags = X86_EFLAGS_IF,
5612         };
5613
5614         do_machine_check(&regs, 0);
5615 #endif
5616 }
5617
5618 static int handle_machine_check(struct kvm_vcpu *vcpu)
5619 {
5620         /* already handled by vcpu_run */
5621         return 1;
5622 }
5623
5624 static int handle_exception(struct kvm_vcpu *vcpu)
5625 {
5626         struct vcpu_vmx *vmx = to_vmx(vcpu);
5627         struct kvm_run *kvm_run = vcpu->run;
5628         u32 intr_info, ex_no, error_code;
5629         unsigned long cr2, rip, dr6;
5630         u32 vect_info;
5631         enum emulation_result er;
5632
5633         vect_info = vmx->idt_vectoring_info;
5634         intr_info = vmx->exit_intr_info;
5635
5636         if (is_machine_check(intr_info))
5637                 return handle_machine_check(vcpu);
5638
5639         if (is_nmi(intr_info))
5640                 return 1;  /* already handled by vmx_vcpu_run() */
5641
5642         if (is_invalid_opcode(intr_info)) {
5643                 if (is_guest_mode(vcpu)) {
5644                         kvm_queue_exception(vcpu, UD_VECTOR);
5645                         return 1;
5646                 }
5647                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5648                 if (er != EMULATE_DONE)
5649                         kvm_queue_exception(vcpu, UD_VECTOR);
5650                 return 1;
5651         }
5652
5653         error_code = 0;
5654         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5655                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5656
5657         /*
5658          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5659          * MMIO, it is better to report an internal error.
5660          * See the comments in vmx_handle_exit.
5661          */
5662         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5663             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5664                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5665                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5666                 vcpu->run->internal.ndata = 3;
5667                 vcpu->run->internal.data[0] = vect_info;
5668                 vcpu->run->internal.data[1] = intr_info;
5669                 vcpu->run->internal.data[2] = error_code;
5670                 return 0;
5671         }
5672
5673         if (is_page_fault(intr_info)) {
5674                 /* EPT won't cause page fault directly */
5675                 BUG_ON(enable_ept);
5676                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5677                 trace_kvm_page_fault(cr2, error_code);
5678
5679                 if (kvm_event_needs_reinjection(vcpu))
5680                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5681                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5682         }
5683
5684         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5685
5686         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5687                 return handle_rmode_exception(vcpu, ex_no, error_code);
5688
5689         switch (ex_no) {
5690         case AC_VECTOR:
5691                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5692                 return 1;
5693         case DB_VECTOR:
5694                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5695                 if (!(vcpu->guest_debug &
5696                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5697                         vcpu->arch.dr6 &= ~15;
5698                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5699                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5700                                 skip_emulated_instruction(vcpu);
5701
5702                         kvm_queue_exception(vcpu, DB_VECTOR);
5703                         return 1;
5704                 }
5705                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5706                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5707                 /* fall through */
5708         case BP_VECTOR:
5709                 /*
5710                  * Update instruction length as we may reinject #BP from
5711                  * user space while in guest debugging mode. Reading it for
5712                  * #DB as well causes no harm, it is not used in that case.
5713                  */
5714                 vmx->vcpu.arch.event_exit_inst_len =
5715                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5716                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5717                 rip = kvm_rip_read(vcpu);
5718                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5719                 kvm_run->debug.arch.exception = ex_no;
5720                 break;
5721         default:
5722                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5723                 kvm_run->ex.exception = ex_no;
5724                 kvm_run->ex.error_code = error_code;
5725                 break;
5726         }
5727         return 0;
5728 }
5729
5730 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5731 {
5732         ++vcpu->stat.irq_exits;
5733         return 1;
5734 }
5735
5736 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5737 {
5738         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5739         return 0;
5740 }
5741
5742 static int handle_io(struct kvm_vcpu *vcpu)
5743 {
5744         unsigned long exit_qualification;
5745         int size, in, string, ret;
5746         unsigned port;
5747
5748         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5749         string = (exit_qualification & 16) != 0;
5750         in = (exit_qualification & 8) != 0;
5751
5752         ++vcpu->stat.io_exits;
5753
5754         if (string || in)
5755                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5756
5757         port = exit_qualification >> 16;
5758         size = (exit_qualification & 7) + 1;
5759
5760         ret = kvm_skip_emulated_instruction(vcpu);
5761
5762         /*
5763          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5764          * KVM_EXIT_DEBUG here.
5765          */
5766         return kvm_fast_pio_out(vcpu, size, port) && ret;
5767 }
5768
5769 static void
5770 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5771 {
5772         /*
5773          * Patch in the VMCALL instruction:
5774          */
5775         hypercall[0] = 0x0f;
5776         hypercall[1] = 0x01;
5777         hypercall[2] = 0xc1;
5778 }
5779
5780 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5781 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5782 {
5783         if (is_guest_mode(vcpu)) {
5784                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5785                 unsigned long orig_val = val;
5786
5787                 /*
5788                  * We get here when L2 changed cr0 in a way that did not change
5789                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5790                  * but did change L0 shadowed bits. So we first calculate the
5791                  * effective cr0 value that L1 would like to write into the
5792                  * hardware. It consists of the L2-owned bits from the new
5793                  * value combined with the L1-owned bits from L1's guest_cr0.
5794                  */
5795                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5796                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5797
5798                 if (!nested_guest_cr0_valid(vcpu, val))
5799                         return 1;
5800
5801                 if (kvm_set_cr0(vcpu, val))
5802                         return 1;
5803                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5804                 return 0;
5805         } else {
5806                 if (to_vmx(vcpu)->nested.vmxon &&
5807                     !nested_host_cr0_valid(vcpu, val))
5808                         return 1;
5809
5810                 return kvm_set_cr0(vcpu, val);
5811         }
5812 }
5813
5814 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5815 {
5816         if (is_guest_mode(vcpu)) {
5817                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5818                 unsigned long orig_val = val;
5819
5820                 /* analogously to handle_set_cr0 */
5821                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5822                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5823                 if (kvm_set_cr4(vcpu, val))
5824                         return 1;
5825                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5826                 return 0;
5827         } else
5828                 return kvm_set_cr4(vcpu, val);
5829 }
5830
5831 static int handle_cr(struct kvm_vcpu *vcpu)
5832 {
5833         unsigned long exit_qualification, val;
5834         int cr;
5835         int reg;
5836         int err;
5837         int ret;
5838
5839         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5840         cr = exit_qualification & 15;
5841         reg = (exit_qualification >> 8) & 15;
5842         switch ((exit_qualification >> 4) & 3) {
5843         case 0: /* mov to cr */
5844                 val = kvm_register_readl(vcpu, reg);
5845                 trace_kvm_cr_write(cr, val);
5846                 switch (cr) {
5847                 case 0:
5848                         err = handle_set_cr0(vcpu, val);
5849                         return kvm_complete_insn_gp(vcpu, err);
5850                 case 3:
5851                         err = kvm_set_cr3(vcpu, val);
5852                         return kvm_complete_insn_gp(vcpu, err);
5853                 case 4:
5854                         err = handle_set_cr4(vcpu, val);
5855                         return kvm_complete_insn_gp(vcpu, err);
5856                 case 8: {
5857                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5858                                 u8 cr8 = (u8)val;
5859                                 err = kvm_set_cr8(vcpu, cr8);
5860                                 ret = kvm_complete_insn_gp(vcpu, err);
5861                                 if (lapic_in_kernel(vcpu))
5862                                         return ret;
5863                                 if (cr8_prev <= cr8)
5864                                         return ret;
5865                                 /*
5866                                  * TODO: we might be squashing a
5867                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5868                                  * KVM_EXIT_DEBUG here.
5869                                  */
5870                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5871                                 return 0;
5872                         }
5873                 }
5874                 break;
5875         case 2: /* clts */
5876                 WARN_ONCE(1, "Guest should always own CR0.TS");
5877                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5878                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5879                 return kvm_skip_emulated_instruction(vcpu);
5880         case 1: /*mov from cr*/
5881                 switch (cr) {
5882                 case 3:
5883                         val = kvm_read_cr3(vcpu);
5884                         kvm_register_write(vcpu, reg, val);
5885                         trace_kvm_cr_read(cr, val);
5886                         return kvm_skip_emulated_instruction(vcpu);
5887                 case 8:
5888                         val = kvm_get_cr8(vcpu);
5889                         kvm_register_write(vcpu, reg, val);
5890                         trace_kvm_cr_read(cr, val);
5891                         return kvm_skip_emulated_instruction(vcpu);
5892                 }
5893                 break;
5894         case 3: /* lmsw */
5895                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5896                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5897                 kvm_lmsw(vcpu, val);
5898
5899                 return kvm_skip_emulated_instruction(vcpu);
5900         default:
5901                 break;
5902         }
5903         vcpu->run->exit_reason = 0;
5904         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5905                (int)(exit_qualification >> 4) & 3, cr);
5906         return 0;
5907 }
5908
5909 static int handle_dr(struct kvm_vcpu *vcpu)
5910 {
5911         unsigned long exit_qualification;
5912         int dr, dr7, reg;
5913
5914         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5915         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5916
5917         /* First, if DR does not exist, trigger UD */
5918         if (!kvm_require_dr(vcpu, dr))
5919                 return 1;
5920
5921         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5922         if (!kvm_require_cpl(vcpu, 0))
5923                 return 1;
5924         dr7 = vmcs_readl(GUEST_DR7);
5925         if (dr7 & DR7_GD) {
5926                 /*
5927                  * As the vm-exit takes precedence over the debug trap, we
5928                  * need to emulate the latter, either for the host or the
5929                  * guest debugging itself.
5930                  */
5931                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5932                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5933                         vcpu->run->debug.arch.dr7 = dr7;
5934                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5935                         vcpu->run->debug.arch.exception = DB_VECTOR;
5936                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5937                         return 0;
5938                 } else {
5939                         vcpu->arch.dr6 &= ~15;
5940                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5941                         kvm_queue_exception(vcpu, DB_VECTOR);
5942                         return 1;
5943                 }
5944         }
5945
5946         if (vcpu->guest_debug == 0) {
5947                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5948                                 CPU_BASED_MOV_DR_EXITING);
5949
5950                 /*
5951                  * No more DR vmexits; force a reload of the debug registers
5952                  * and reenter on this instruction.  The next vmexit will
5953                  * retrieve the full state of the debug registers.
5954                  */
5955                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5956                 return 1;
5957         }
5958
5959         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5960         if (exit_qualification & TYPE_MOV_FROM_DR) {
5961                 unsigned long val;
5962
5963                 if (kvm_get_dr(vcpu, dr, &val))
5964                         return 1;
5965                 kvm_register_write(vcpu, reg, val);
5966         } else
5967                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5968                         return 1;
5969
5970         return kvm_skip_emulated_instruction(vcpu);
5971 }
5972
5973 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5974 {
5975         return vcpu->arch.dr6;
5976 }
5977
5978 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5979 {
5980 }
5981
5982 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5983 {
5984         get_debugreg(vcpu->arch.db[0], 0);
5985         get_debugreg(vcpu->arch.db[1], 1);
5986         get_debugreg(vcpu->arch.db[2], 2);
5987         get_debugreg(vcpu->arch.db[3], 3);
5988         get_debugreg(vcpu->arch.dr6, 6);
5989         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5990
5991         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5992         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5993 }
5994
5995 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5996 {
5997         vmcs_writel(GUEST_DR7, val);
5998 }
5999
6000 static int handle_cpuid(struct kvm_vcpu *vcpu)
6001 {
6002         return kvm_emulate_cpuid(vcpu);
6003 }
6004
6005 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6006 {
6007         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6008         struct msr_data msr_info;
6009
6010         msr_info.index = ecx;
6011         msr_info.host_initiated = false;
6012         if (vmx_get_msr(vcpu, &msr_info)) {
6013                 trace_kvm_msr_read_ex(ecx);
6014                 kvm_inject_gp(vcpu, 0);
6015                 return 1;
6016         }
6017
6018         trace_kvm_msr_read(ecx, msr_info.data);
6019
6020         /* FIXME: handling of bits 32:63 of rax, rdx */
6021         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6022         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6023         return kvm_skip_emulated_instruction(vcpu);
6024 }
6025
6026 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6027 {
6028         struct msr_data msr;
6029         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6030         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6031                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6032
6033         msr.data = data;
6034         msr.index = ecx;
6035         msr.host_initiated = false;
6036         if (kvm_set_msr(vcpu, &msr) != 0) {
6037                 trace_kvm_msr_write_ex(ecx, data);
6038                 kvm_inject_gp(vcpu, 0);
6039                 return 1;
6040         }
6041
6042         trace_kvm_msr_write(ecx, data);
6043         return kvm_skip_emulated_instruction(vcpu);
6044 }
6045
6046 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6047 {
6048         kvm_apic_update_ppr(vcpu);
6049         return 1;
6050 }
6051
6052 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6053 {
6054         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6055                         CPU_BASED_VIRTUAL_INTR_PENDING);
6056
6057         kvm_make_request(KVM_REQ_EVENT, vcpu);
6058
6059         ++vcpu->stat.irq_window_exits;
6060         return 1;
6061 }
6062
6063 static int handle_halt(struct kvm_vcpu *vcpu)
6064 {
6065         return kvm_emulate_halt(vcpu);
6066 }
6067
6068 static int handle_vmcall(struct kvm_vcpu *vcpu)
6069 {
6070         return kvm_emulate_hypercall(vcpu);
6071 }
6072
6073 static int handle_invd(struct kvm_vcpu *vcpu)
6074 {
6075         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6076 }
6077
6078 static int handle_invlpg(struct kvm_vcpu *vcpu)
6079 {
6080         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6081
6082         kvm_mmu_invlpg(vcpu, exit_qualification);
6083         return kvm_skip_emulated_instruction(vcpu);
6084 }
6085
6086 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6087 {
6088         int err;
6089
6090         err = kvm_rdpmc(vcpu);
6091         return kvm_complete_insn_gp(vcpu, err);
6092 }
6093
6094 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6095 {
6096         return kvm_emulate_wbinvd(vcpu);
6097 }
6098
6099 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6100 {
6101         u64 new_bv = kvm_read_edx_eax(vcpu);
6102         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6103
6104         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6105                 return kvm_skip_emulated_instruction(vcpu);
6106         return 1;
6107 }
6108
6109 static int handle_xsaves(struct kvm_vcpu *vcpu)
6110 {
6111         kvm_skip_emulated_instruction(vcpu);
6112         WARN(1, "this should never happen\n");
6113         return 1;
6114 }
6115
6116 static int handle_xrstors(struct kvm_vcpu *vcpu)
6117 {
6118         kvm_skip_emulated_instruction(vcpu);
6119         WARN(1, "this should never happen\n");
6120         return 1;
6121 }
6122
6123 static int handle_apic_access(struct kvm_vcpu *vcpu)
6124 {
6125         if (likely(fasteoi)) {
6126                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6127                 int access_type, offset;
6128
6129                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6130                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6131                 /*
6132                  * Sane guest uses MOV to write EOI, with written value
6133                  * not cared. So make a short-circuit here by avoiding
6134                  * heavy instruction emulation.
6135                  */
6136                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6137                     (offset == APIC_EOI)) {
6138                         kvm_lapic_set_eoi(vcpu);
6139                         return kvm_skip_emulated_instruction(vcpu);
6140                 }
6141         }
6142         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6143 }
6144
6145 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6146 {
6147         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6148         int vector = exit_qualification & 0xff;
6149
6150         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6151         kvm_apic_set_eoi_accelerated(vcpu, vector);
6152         return 1;
6153 }
6154
6155 static int handle_apic_write(struct kvm_vcpu *vcpu)
6156 {
6157         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6158         u32 offset = exit_qualification & 0xfff;
6159
6160         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6161         kvm_apic_write_nodecode(vcpu, offset);
6162         return 1;
6163 }
6164
6165 static int handle_task_switch(struct kvm_vcpu *vcpu)
6166 {
6167         struct vcpu_vmx *vmx = to_vmx(vcpu);
6168         unsigned long exit_qualification;
6169         bool has_error_code = false;
6170         u32 error_code = 0;
6171         u16 tss_selector;
6172         int reason, type, idt_v, idt_index;
6173
6174         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6175         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6176         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6177
6178         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6179
6180         reason = (u32)exit_qualification >> 30;
6181         if (reason == TASK_SWITCH_GATE && idt_v) {
6182                 switch (type) {
6183                 case INTR_TYPE_NMI_INTR:
6184                         vcpu->arch.nmi_injected = false;
6185                         vmx_set_nmi_mask(vcpu, true);
6186                         break;
6187                 case INTR_TYPE_EXT_INTR:
6188                 case INTR_TYPE_SOFT_INTR:
6189                         kvm_clear_interrupt_queue(vcpu);
6190                         break;
6191                 case INTR_TYPE_HARD_EXCEPTION:
6192                         if (vmx->idt_vectoring_info &
6193                             VECTORING_INFO_DELIVER_CODE_MASK) {
6194                                 has_error_code = true;
6195                                 error_code =
6196                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6197                         }
6198                         /* fall through */
6199                 case INTR_TYPE_SOFT_EXCEPTION:
6200                         kvm_clear_exception_queue(vcpu);
6201                         break;
6202                 default:
6203                         break;
6204                 }
6205         }
6206         tss_selector = exit_qualification;
6207
6208         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6209                        type != INTR_TYPE_EXT_INTR &&
6210                        type != INTR_TYPE_NMI_INTR))
6211                 skip_emulated_instruction(vcpu);
6212
6213         if (kvm_task_switch(vcpu, tss_selector,
6214                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6215                             has_error_code, error_code) == EMULATE_FAIL) {
6216                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6217                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6218                 vcpu->run->internal.ndata = 0;
6219                 return 0;
6220         }
6221
6222         /*
6223          * TODO: What about debug traps on tss switch?
6224          *       Are we supposed to inject them and update dr6?
6225          */
6226
6227         return 1;
6228 }
6229
6230 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6231 {
6232         unsigned long exit_qualification;
6233         gpa_t gpa;
6234         u32 error_code;
6235         int gla_validity;
6236
6237         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6238
6239         gla_validity = (exit_qualification >> 7) & 0x3;
6240         if (gla_validity == 0x2) {
6241                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6242                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6243                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6244                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6245                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6246                         (long unsigned int)exit_qualification);
6247                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6248                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6249                 return 0;
6250         }
6251
6252         /*
6253          * EPT violation happened while executing iret from NMI,
6254          * "blocked by NMI" bit has to be set before next VM entry.
6255          * There are errata that may cause this bit to not be set:
6256          * AAK134, BY25.
6257          */
6258         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6259                         cpu_has_virtual_nmis() &&
6260                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6261                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6262
6263         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6264         trace_kvm_page_fault(gpa, exit_qualification);
6265
6266         /* Is it a read fault? */
6267         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6268                      ? PFERR_USER_MASK : 0;
6269         /* Is it a write fault? */
6270         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6271                       ? PFERR_WRITE_MASK : 0;
6272         /* Is it a fetch fault? */
6273         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6274                       ? PFERR_FETCH_MASK : 0;
6275         /* ept page table entry is present? */
6276         error_code |= (exit_qualification &
6277                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6278                         EPT_VIOLATION_EXECUTABLE))
6279                       ? PFERR_PRESENT_MASK : 0;
6280
6281         vcpu->arch.gpa_available = true;
6282         vcpu->arch.exit_qualification = exit_qualification;
6283
6284         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6285 }
6286
6287 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6288 {
6289         int ret;
6290         gpa_t gpa;
6291
6292         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6293         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6294                 trace_kvm_fast_mmio(gpa);
6295                 return kvm_skip_emulated_instruction(vcpu);
6296         }
6297
6298         ret = handle_mmio_page_fault(vcpu, gpa, true);
6299         vcpu->arch.gpa_available = true;
6300         if (likely(ret == RET_MMIO_PF_EMULATE))
6301                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6302                                               EMULATE_DONE;
6303
6304         if (unlikely(ret == RET_MMIO_PF_INVALID))
6305                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6306
6307         if (unlikely(ret == RET_MMIO_PF_RETRY))
6308                 return 1;
6309
6310         /* It is the real ept misconfig */
6311         WARN_ON(1);
6312
6313         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6314         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6315
6316         return 0;
6317 }
6318
6319 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6320 {
6321         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6322                         CPU_BASED_VIRTUAL_NMI_PENDING);
6323         ++vcpu->stat.nmi_window_exits;
6324         kvm_make_request(KVM_REQ_EVENT, vcpu);
6325
6326         return 1;
6327 }
6328
6329 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6330 {
6331         struct vcpu_vmx *vmx = to_vmx(vcpu);
6332         enum emulation_result err = EMULATE_DONE;
6333         int ret = 1;
6334         u32 cpu_exec_ctrl;
6335         bool intr_window_requested;
6336         unsigned count = 130;
6337
6338         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6339         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6340
6341         while (vmx->emulation_required && count-- != 0) {
6342                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6343                         return handle_interrupt_window(&vmx->vcpu);
6344
6345                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6346                         return 1;
6347
6348                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6349
6350                 if (err == EMULATE_USER_EXIT) {
6351                         ++vcpu->stat.mmio_exits;
6352                         ret = 0;
6353                         goto out;
6354                 }
6355
6356                 if (err != EMULATE_DONE) {
6357                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6358                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6359                         vcpu->run->internal.ndata = 0;
6360                         return 0;
6361                 }
6362
6363                 if (vcpu->arch.halt_request) {
6364                         vcpu->arch.halt_request = 0;
6365                         ret = kvm_vcpu_halt(vcpu);
6366                         goto out;
6367                 }
6368
6369                 if (signal_pending(current))
6370                         goto out;
6371                 if (need_resched())
6372                         schedule();
6373         }
6374
6375 out:
6376         return ret;
6377 }
6378
6379 static int __grow_ple_window(int val)
6380 {
6381         if (ple_window_grow < 1)
6382                 return ple_window;
6383
6384         val = min(val, ple_window_actual_max);
6385
6386         if (ple_window_grow < ple_window)
6387                 val *= ple_window_grow;
6388         else
6389                 val += ple_window_grow;
6390
6391         return val;
6392 }
6393
6394 static int __shrink_ple_window(int val, int modifier, int minimum)
6395 {
6396         if (modifier < 1)
6397                 return ple_window;
6398
6399         if (modifier < ple_window)
6400                 val /= modifier;
6401         else
6402                 val -= modifier;
6403
6404         return max(val, minimum);
6405 }
6406
6407 static void grow_ple_window(struct kvm_vcpu *vcpu)
6408 {
6409         struct vcpu_vmx *vmx = to_vmx(vcpu);
6410         int old = vmx->ple_window;
6411
6412         vmx->ple_window = __grow_ple_window(old);
6413
6414         if (vmx->ple_window != old)
6415                 vmx->ple_window_dirty = true;
6416
6417         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6418 }
6419
6420 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6421 {
6422         struct vcpu_vmx *vmx = to_vmx(vcpu);
6423         int old = vmx->ple_window;
6424
6425         vmx->ple_window = __shrink_ple_window(old,
6426                                               ple_window_shrink, ple_window);
6427
6428         if (vmx->ple_window != old)
6429                 vmx->ple_window_dirty = true;
6430
6431         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6432 }
6433
6434 /*
6435  * ple_window_actual_max is computed to be one grow_ple_window() below
6436  * ple_window_max. (See __grow_ple_window for the reason.)
6437  * This prevents overflows, because ple_window_max is int.
6438  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6439  * this process.
6440  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6441  */
6442 static void update_ple_window_actual_max(void)
6443 {
6444         ple_window_actual_max =
6445                         __shrink_ple_window(max(ple_window_max, ple_window),
6446                                             ple_window_grow, INT_MIN);
6447 }
6448
6449 /*
6450  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6451  */
6452 static void wakeup_handler(void)
6453 {
6454         struct kvm_vcpu *vcpu;
6455         int cpu = smp_processor_id();
6456
6457         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6458         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6459                         blocked_vcpu_list) {
6460                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6461
6462                 if (pi_test_on(pi_desc) == 1)
6463                         kvm_vcpu_kick(vcpu);
6464         }
6465         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6466 }
6467
6468 void vmx_enable_tdp(void)
6469 {
6470         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6471                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6472                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6473                 0ull, VMX_EPT_EXECUTABLE_MASK,
6474                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6475                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6476
6477         ept_set_mmio_spte_mask();
6478         kvm_enable_tdp();
6479 }
6480
6481 static __init int hardware_setup(void)
6482 {
6483         int r = -ENOMEM, i, msr;
6484
6485         rdmsrl_safe(MSR_EFER, &host_efer);
6486
6487         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6488                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6489
6490         for (i = 0; i < VMX_BITMAP_NR; i++) {
6491                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6492                 if (!vmx_bitmap[i])
6493                         goto out;
6494         }
6495
6496         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6497         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6498         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6499
6500         /*
6501          * Allow direct access to the PC debug port (it is often used for I/O
6502          * delays, but the vmexits simply slow things down).
6503          */
6504         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6505         clear_bit(0x80, vmx_io_bitmap_a);
6506
6507         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6508
6509         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6510         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6511
6512         if (setup_vmcs_config(&vmcs_config) < 0) {
6513                 r = -EIO;
6514                 goto out;
6515         }
6516
6517         if (boot_cpu_has(X86_FEATURE_NX))
6518                 kvm_enable_efer_bits(EFER_NX);
6519
6520         if (!cpu_has_vmx_vpid())
6521                 enable_vpid = 0;
6522         if (!cpu_has_vmx_shadow_vmcs())
6523                 enable_shadow_vmcs = 0;
6524         if (enable_shadow_vmcs)
6525                 init_vmcs_shadow_fields();
6526
6527         if (!cpu_has_vmx_ept() ||
6528             !cpu_has_vmx_ept_4levels()) {
6529                 enable_ept = 0;
6530                 enable_unrestricted_guest = 0;
6531                 enable_ept_ad_bits = 0;
6532         }
6533
6534         if (!cpu_has_vmx_ept_ad_bits())
6535                 enable_ept_ad_bits = 0;
6536
6537         if (!cpu_has_vmx_unrestricted_guest())
6538                 enable_unrestricted_guest = 0;
6539
6540         if (!cpu_has_vmx_flexpriority())
6541                 flexpriority_enabled = 0;
6542
6543         /*
6544          * set_apic_access_page_addr() is used to reload apic access
6545          * page upon invalidation.  No need to do anything if not
6546          * using the APIC_ACCESS_ADDR VMCS field.
6547          */
6548         if (!flexpriority_enabled)
6549                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6550
6551         if (!cpu_has_vmx_tpr_shadow())
6552                 kvm_x86_ops->update_cr8_intercept = NULL;
6553
6554         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6555                 kvm_disable_largepages();
6556
6557         if (!cpu_has_vmx_ple())
6558                 ple_gap = 0;
6559
6560         if (!cpu_has_vmx_apicv()) {
6561                 enable_apicv = 0;
6562                 kvm_x86_ops->sync_pir_to_irr = NULL;
6563         }
6564
6565         if (cpu_has_vmx_tsc_scaling()) {
6566                 kvm_has_tsc_control = true;
6567                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6568                 kvm_tsc_scaling_ratio_frac_bits = 48;
6569         }
6570
6571         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6572         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6573         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6574         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6575         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6576         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6577         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6578
6579         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6580                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6581         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6582                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6583         memcpy(vmx_msr_bitmap_legacy_x2apic,
6584                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6585         memcpy(vmx_msr_bitmap_longmode_x2apic,
6586                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6587
6588         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6589
6590         for (msr = 0x800; msr <= 0x8ff; msr++) {
6591                 if (msr == 0x839 /* TMCCT */)
6592                         continue;
6593                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6594         }
6595
6596         /*
6597          * TPR reads and writes can be virtualized even if virtual interrupt
6598          * delivery is not in use.
6599          */
6600         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6601         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6602
6603         /* EOI */
6604         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6605         /* SELF-IPI */
6606         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6607
6608         if (enable_ept)
6609                 vmx_enable_tdp();
6610         else
6611                 kvm_disable_tdp();
6612
6613         update_ple_window_actual_max();
6614
6615         /*
6616          * Only enable PML when hardware supports PML feature, and both EPT
6617          * and EPT A/D bit features are enabled -- PML depends on them to work.
6618          */
6619         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6620                 enable_pml = 0;
6621
6622         if (!enable_pml) {
6623                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6624                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6625                 kvm_x86_ops->flush_log_dirty = NULL;
6626                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6627         }
6628
6629         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6630                 u64 vmx_msr;
6631
6632                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6633                 cpu_preemption_timer_multi =
6634                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6635         } else {
6636                 kvm_x86_ops->set_hv_timer = NULL;
6637                 kvm_x86_ops->cancel_hv_timer = NULL;
6638         }
6639
6640         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6641
6642         kvm_mce_cap_supported |= MCG_LMCE_P;
6643
6644         return alloc_kvm_area();
6645
6646 out:
6647         for (i = 0; i < VMX_BITMAP_NR; i++)
6648                 free_page((unsigned long)vmx_bitmap[i]);
6649
6650     return r;
6651 }
6652
6653 static __exit void hardware_unsetup(void)
6654 {
6655         int i;
6656
6657         for (i = 0; i < VMX_BITMAP_NR; i++)
6658                 free_page((unsigned long)vmx_bitmap[i]);
6659
6660         free_kvm_area();
6661 }
6662
6663 /*
6664  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6665  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6666  */
6667 static int handle_pause(struct kvm_vcpu *vcpu)
6668 {
6669         if (ple_gap)
6670                 grow_ple_window(vcpu);
6671
6672         kvm_vcpu_on_spin(vcpu);
6673         return kvm_skip_emulated_instruction(vcpu);
6674 }
6675
6676 static int handle_nop(struct kvm_vcpu *vcpu)
6677 {
6678         return kvm_skip_emulated_instruction(vcpu);
6679 }
6680
6681 static int handle_mwait(struct kvm_vcpu *vcpu)
6682 {
6683         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6684         return handle_nop(vcpu);
6685 }
6686
6687 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6688 {
6689         return 1;
6690 }
6691
6692 static int handle_monitor(struct kvm_vcpu *vcpu)
6693 {
6694         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6695         return handle_nop(vcpu);
6696 }
6697
6698 /*
6699  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6700  * We could reuse a single VMCS for all the L2 guests, but we also want the
6701  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6702  * allows keeping them loaded on the processor, and in the future will allow
6703  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6704  * every entry if they never change.
6705  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6706  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6707  *
6708  * The following functions allocate and free a vmcs02 in this pool.
6709  */
6710
6711 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6712 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6713 {
6714         struct vmcs02_list *item;
6715         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6716                 if (item->vmptr == vmx->nested.current_vmptr) {
6717                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6718                         return &item->vmcs02;
6719                 }
6720
6721         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6722                 /* Recycle the least recently used VMCS. */
6723                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6724                                        struct vmcs02_list, list);
6725                 item->vmptr = vmx->nested.current_vmptr;
6726                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6727                 return &item->vmcs02;
6728         }
6729
6730         /* Create a new VMCS */
6731         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6732         if (!item)
6733                 return NULL;
6734         item->vmcs02.vmcs = alloc_vmcs();
6735         item->vmcs02.shadow_vmcs = NULL;
6736         if (!item->vmcs02.vmcs) {
6737                 kfree(item);
6738                 return NULL;
6739         }
6740         loaded_vmcs_init(&item->vmcs02);
6741         item->vmptr = vmx->nested.current_vmptr;
6742         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6743         vmx->nested.vmcs02_num++;
6744         return &item->vmcs02;
6745 }
6746
6747 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6748 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6749 {
6750         struct vmcs02_list *item;
6751         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6752                 if (item->vmptr == vmptr) {
6753                         free_loaded_vmcs(&item->vmcs02);
6754                         list_del(&item->list);
6755                         kfree(item);
6756                         vmx->nested.vmcs02_num--;
6757                         return;
6758                 }
6759 }
6760
6761 /*
6762  * Free all VMCSs saved for this vcpu, except the one pointed by
6763  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6764  * must be &vmx->vmcs01.
6765  */
6766 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6767 {
6768         struct vmcs02_list *item, *n;
6769
6770         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6771         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6772                 /*
6773                  * Something will leak if the above WARN triggers.  Better than
6774                  * a use-after-free.
6775                  */
6776                 if (vmx->loaded_vmcs == &item->vmcs02)
6777                         continue;
6778
6779                 free_loaded_vmcs(&item->vmcs02);
6780                 list_del(&item->list);
6781                 kfree(item);
6782                 vmx->nested.vmcs02_num--;
6783         }
6784 }
6785
6786 /*
6787  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6788  * set the success or error code of an emulated VMX instruction, as specified
6789  * by Vol 2B, VMX Instruction Reference, "Conventions".
6790  */
6791 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6792 {
6793         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6794                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6795                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6796 }
6797
6798 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6799 {
6800         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6801                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6802                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6803                         | X86_EFLAGS_CF);
6804 }
6805
6806 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6807                                         u32 vm_instruction_error)
6808 {
6809         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6810                 /*
6811                  * failValid writes the error number to the current VMCS, which
6812                  * can't be done there isn't a current VMCS.
6813                  */
6814                 nested_vmx_failInvalid(vcpu);
6815                 return;
6816         }
6817         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6818                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6819                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6820                         | X86_EFLAGS_ZF);
6821         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6822         /*
6823          * We don't need to force a shadow sync because
6824          * VM_INSTRUCTION_ERROR is not shadowed
6825          */
6826 }
6827
6828 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6829 {
6830         /* TODO: not to reset guest simply here. */
6831         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6832         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6833 }
6834
6835 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6836 {
6837         struct vcpu_vmx *vmx =
6838                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6839
6840         vmx->nested.preemption_timer_expired = true;
6841         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6842         kvm_vcpu_kick(&vmx->vcpu);
6843
6844         return HRTIMER_NORESTART;
6845 }
6846
6847 /*
6848  * Decode the memory-address operand of a vmx instruction, as recorded on an
6849  * exit caused by such an instruction (run by a guest hypervisor).
6850  * On success, returns 0. When the operand is invalid, returns 1 and throws
6851  * #UD or #GP.
6852  */
6853 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6854                                  unsigned long exit_qualification,
6855                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6856 {
6857         gva_t off;
6858         bool exn;
6859         struct kvm_segment s;
6860
6861         /*
6862          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6863          * Execution", on an exit, vmx_instruction_info holds most of the
6864          * addressing components of the operand. Only the displacement part
6865          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6866          * For how an actual address is calculated from all these components,
6867          * refer to Vol. 1, "Operand Addressing".
6868          */
6869         int  scaling = vmx_instruction_info & 3;
6870         int  addr_size = (vmx_instruction_info >> 7) & 7;
6871         bool is_reg = vmx_instruction_info & (1u << 10);
6872         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6873         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6874         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6875         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6876         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6877
6878         if (is_reg) {
6879                 kvm_queue_exception(vcpu, UD_VECTOR);
6880                 return 1;
6881         }
6882
6883         /* Addr = segment_base + offset */
6884         /* offset = base + [index * scale] + displacement */
6885         off = exit_qualification; /* holds the displacement */
6886         if (base_is_valid)
6887                 off += kvm_register_read(vcpu, base_reg);
6888         if (index_is_valid)
6889                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6890         vmx_get_segment(vcpu, &s, seg_reg);
6891         *ret = s.base + off;
6892
6893         if (addr_size == 1) /* 32 bit */
6894                 *ret &= 0xffffffff;
6895
6896         /* Checks for #GP/#SS exceptions. */
6897         exn = false;
6898         if (is_long_mode(vcpu)) {
6899                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6900                  * non-canonical form. This is the only check on the memory
6901                  * destination for long mode!
6902                  */
6903                 exn = is_noncanonical_address(*ret);
6904         } else if (is_protmode(vcpu)) {
6905                 /* Protected mode: apply checks for segment validity in the
6906                  * following order:
6907                  * - segment type check (#GP(0) may be thrown)
6908                  * - usability check (#GP(0)/#SS(0))
6909                  * - limit check (#GP(0)/#SS(0))
6910                  */
6911                 if (wr)
6912                         /* #GP(0) if the destination operand is located in a
6913                          * read-only data segment or any code segment.
6914                          */
6915                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6916                 else
6917                         /* #GP(0) if the source operand is located in an
6918                          * execute-only code segment
6919                          */
6920                         exn = ((s.type & 0xa) == 8);
6921                 if (exn) {
6922                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6923                         return 1;
6924                 }
6925                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6926                  */
6927                 exn = (s.unusable != 0);
6928                 /* Protected mode: #GP(0)/#SS(0) if the memory
6929                  * operand is outside the segment limit.
6930                  */
6931                 exn = exn || (off + sizeof(u64) > s.limit);
6932         }
6933         if (exn) {
6934                 kvm_queue_exception_e(vcpu,
6935                                       seg_reg == VCPU_SREG_SS ?
6936                                                 SS_VECTOR : GP_VECTOR,
6937                                       0);
6938                 return 1;
6939         }
6940
6941         return 0;
6942 }
6943
6944 /*
6945  * This function performs the various checks including
6946  * - if it's 4KB aligned
6947  * - No bits beyond the physical address width are set
6948  * - Returns 0 on success or else 1
6949  * (Intel SDM Section 30.3)
6950  */
6951 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6952                                   gpa_t *vmpointer)
6953 {
6954         gva_t gva;
6955         gpa_t vmptr;
6956         struct x86_exception e;
6957         struct page *page;
6958         struct vcpu_vmx *vmx = to_vmx(vcpu);
6959         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6960
6961         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6962                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6963                 return 1;
6964
6965         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6966                                 sizeof(vmptr), &e)) {
6967                 kvm_inject_page_fault(vcpu, &e);
6968                 return 1;
6969         }
6970
6971         switch (exit_reason) {
6972         case EXIT_REASON_VMON:
6973                 /*
6974                  * SDM 3: 24.11.5
6975                  * The first 4 bytes of VMXON region contain the supported
6976                  * VMCS revision identifier
6977                  *
6978                  * Note - IA32_VMX_BASIC[48] will never be 1
6979                  * for the nested case;
6980                  * which replaces physical address width with 32
6981                  *
6982                  */
6983                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6984                         nested_vmx_failInvalid(vcpu);
6985                         return kvm_skip_emulated_instruction(vcpu);
6986                 }
6987
6988                 page = nested_get_page(vcpu, vmptr);
6989                 if (page == NULL) {
6990                         nested_vmx_failInvalid(vcpu);
6991                         return kvm_skip_emulated_instruction(vcpu);
6992                 }
6993                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6994                         kunmap(page);
6995                         nested_release_page_clean(page);
6996                         nested_vmx_failInvalid(vcpu);
6997                         return kvm_skip_emulated_instruction(vcpu);
6998                 }
6999                 kunmap(page);
7000                 nested_release_page_clean(page);
7001                 vmx->nested.vmxon_ptr = vmptr;
7002                 break;
7003         case EXIT_REASON_VMCLEAR:
7004                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7005                         nested_vmx_failValid(vcpu,
7006                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7007                         return kvm_skip_emulated_instruction(vcpu);
7008                 }
7009
7010                 if (vmptr == vmx->nested.vmxon_ptr) {
7011                         nested_vmx_failValid(vcpu,
7012                                              VMXERR_VMCLEAR_VMXON_POINTER);
7013                         return kvm_skip_emulated_instruction(vcpu);
7014                 }
7015                 break;
7016         case EXIT_REASON_VMPTRLD:
7017                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7018                         nested_vmx_failValid(vcpu,
7019                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7020                         return kvm_skip_emulated_instruction(vcpu);
7021                 }
7022
7023                 if (vmptr == vmx->nested.vmxon_ptr) {
7024                         nested_vmx_failValid(vcpu,
7025                                              VMXERR_VMPTRLD_VMXON_POINTER);
7026                         return kvm_skip_emulated_instruction(vcpu);
7027                 }
7028                 break;
7029         default:
7030                 return 1; /* shouldn't happen */
7031         }
7032
7033         if (vmpointer)
7034                 *vmpointer = vmptr;
7035         return 0;
7036 }
7037
7038 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7039 {
7040         struct vcpu_vmx *vmx = to_vmx(vcpu);
7041         struct vmcs *shadow_vmcs;
7042
7043         if (cpu_has_vmx_msr_bitmap()) {
7044                 vmx->nested.msr_bitmap =
7045                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7046                 if (!vmx->nested.msr_bitmap)
7047                         goto out_msr_bitmap;
7048         }
7049
7050         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7051         if (!vmx->nested.cached_vmcs12)
7052                 goto out_cached_vmcs12;
7053
7054         if (enable_shadow_vmcs) {
7055                 shadow_vmcs = alloc_vmcs();
7056                 if (!shadow_vmcs)
7057                         goto out_shadow_vmcs;
7058                 /* mark vmcs as shadow */
7059                 shadow_vmcs->revision_id |= (1u << 31);
7060                 /* init shadow vmcs */
7061                 vmcs_clear(shadow_vmcs);
7062                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7063         }
7064
7065         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7066         vmx->nested.vmcs02_num = 0;
7067
7068         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7069                      HRTIMER_MODE_REL_PINNED);
7070         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7071
7072         vmx->nested.vmxon = true;
7073         return 0;
7074
7075 out_shadow_vmcs:
7076         kfree(vmx->nested.cached_vmcs12);
7077
7078 out_cached_vmcs12:
7079         free_page((unsigned long)vmx->nested.msr_bitmap);
7080
7081 out_msr_bitmap:
7082         return -ENOMEM;
7083 }
7084
7085 /*
7086  * Emulate the VMXON instruction.
7087  * Currently, we just remember that VMX is active, and do not save or even
7088  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7089  * do not currently need to store anything in that guest-allocated memory
7090  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7091  * argument is different from the VMXON pointer (which the spec says they do).
7092  */
7093 static int handle_vmon(struct kvm_vcpu *vcpu)
7094 {
7095         int ret;
7096         struct kvm_segment cs;
7097         struct vcpu_vmx *vmx = to_vmx(vcpu);
7098         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7099                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7100
7101         /* The Intel VMX Instruction Reference lists a bunch of bits that
7102          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7103          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7104          * Otherwise, we should fail with #UD. We test these now:
7105          */
7106         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7107             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7108             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7109                 kvm_queue_exception(vcpu, UD_VECTOR);
7110                 return 1;
7111         }
7112
7113         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7114         if (is_long_mode(vcpu) && !cs.l) {
7115                 kvm_queue_exception(vcpu, UD_VECTOR);
7116                 return 1;
7117         }
7118
7119         if (vmx_get_cpl(vcpu)) {
7120                 kvm_inject_gp(vcpu, 0);
7121                 return 1;
7122         }
7123
7124         if (vmx->nested.vmxon) {
7125                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7126                 return kvm_skip_emulated_instruction(vcpu);
7127         }
7128
7129         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7130                         != VMXON_NEEDED_FEATURES) {
7131                 kvm_inject_gp(vcpu, 0);
7132                 return 1;
7133         }
7134
7135         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7136                 return 1;
7137
7138         ret = enter_vmx_operation(vcpu);
7139         if (ret)
7140                 return ret;
7141
7142         nested_vmx_succeed(vcpu);
7143         return kvm_skip_emulated_instruction(vcpu);
7144 }
7145
7146 /*
7147  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7148  * for running VMX instructions (except VMXON, whose prerequisites are
7149  * slightly different). It also specifies what exception to inject otherwise.
7150  */
7151 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7152 {
7153         struct kvm_segment cs;
7154         struct vcpu_vmx *vmx = to_vmx(vcpu);
7155
7156         if (!vmx->nested.vmxon) {
7157                 kvm_queue_exception(vcpu, UD_VECTOR);
7158                 return 0;
7159         }
7160
7161         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7162         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7163             (is_long_mode(vcpu) && !cs.l)) {
7164                 kvm_queue_exception(vcpu, UD_VECTOR);
7165                 return 0;
7166         }
7167
7168         if (vmx_get_cpl(vcpu)) {
7169                 kvm_inject_gp(vcpu, 0);
7170                 return 0;
7171         }
7172
7173         return 1;
7174 }
7175
7176 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7177 {
7178         if (vmx->nested.current_vmptr == -1ull)
7179                 return;
7180
7181         /* current_vmptr and current_vmcs12 are always set/reset together */
7182         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7183                 return;
7184
7185         if (enable_shadow_vmcs) {
7186                 /* copy to memory all shadowed fields in case
7187                    they were modified */
7188                 copy_shadow_to_vmcs12(vmx);
7189                 vmx->nested.sync_shadow_vmcs = false;
7190                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7191                                 SECONDARY_EXEC_SHADOW_VMCS);
7192                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7193         }
7194         vmx->nested.posted_intr_nv = -1;
7195
7196         /* Flush VMCS12 to guest memory */
7197         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7198                VMCS12_SIZE);
7199
7200         kunmap(vmx->nested.current_vmcs12_page);
7201         nested_release_page(vmx->nested.current_vmcs12_page);
7202         vmx->nested.current_vmptr = -1ull;
7203         vmx->nested.current_vmcs12 = NULL;
7204 }
7205
7206 /*
7207  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7208  * just stops using VMX.
7209  */
7210 static void free_nested(struct vcpu_vmx *vmx)
7211 {
7212         if (!vmx->nested.vmxon)
7213                 return;
7214
7215         vmx->nested.vmxon = false;
7216         free_vpid(vmx->nested.vpid02);
7217         nested_release_vmcs12(vmx);
7218         if (vmx->nested.msr_bitmap) {
7219                 free_page((unsigned long)vmx->nested.msr_bitmap);
7220                 vmx->nested.msr_bitmap = NULL;
7221         }
7222         if (enable_shadow_vmcs) {
7223                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7224                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7225                 vmx->vmcs01.shadow_vmcs = NULL;
7226         }
7227         kfree(vmx->nested.cached_vmcs12);
7228         /* Unpin physical memory we referred to in current vmcs02 */
7229         if (vmx->nested.apic_access_page) {
7230                 nested_release_page(vmx->nested.apic_access_page);
7231                 vmx->nested.apic_access_page = NULL;
7232         }
7233         if (vmx->nested.virtual_apic_page) {
7234                 nested_release_page(vmx->nested.virtual_apic_page);
7235                 vmx->nested.virtual_apic_page = NULL;
7236         }
7237         if (vmx->nested.pi_desc_page) {
7238                 kunmap(vmx->nested.pi_desc_page);
7239                 nested_release_page(vmx->nested.pi_desc_page);
7240                 vmx->nested.pi_desc_page = NULL;
7241                 vmx->nested.pi_desc = NULL;
7242         }
7243
7244         nested_free_all_saved_vmcss(vmx);
7245 }
7246
7247 /* Emulate the VMXOFF instruction */
7248 static int handle_vmoff(struct kvm_vcpu *vcpu)
7249 {
7250         if (!nested_vmx_check_permission(vcpu))
7251                 return 1;
7252         free_nested(to_vmx(vcpu));
7253         nested_vmx_succeed(vcpu);
7254         return kvm_skip_emulated_instruction(vcpu);
7255 }
7256
7257 /* Emulate the VMCLEAR instruction */
7258 static int handle_vmclear(struct kvm_vcpu *vcpu)
7259 {
7260         struct vcpu_vmx *vmx = to_vmx(vcpu);
7261         gpa_t vmptr;
7262         struct vmcs12 *vmcs12;
7263         struct page *page;
7264
7265         if (!nested_vmx_check_permission(vcpu))
7266                 return 1;
7267
7268         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7269                 return 1;
7270
7271         if (vmptr == vmx->nested.current_vmptr)
7272                 nested_release_vmcs12(vmx);
7273
7274         page = nested_get_page(vcpu, vmptr);
7275         if (page == NULL) {
7276                 /*
7277                  * For accurate processor emulation, VMCLEAR beyond available
7278                  * physical memory should do nothing at all. However, it is
7279                  * possible that a nested vmx bug, not a guest hypervisor bug,
7280                  * resulted in this case, so let's shut down before doing any
7281                  * more damage:
7282                  */
7283                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7284                 return 1;
7285         }
7286         vmcs12 = kmap(page);
7287         vmcs12->launch_state = 0;
7288         kunmap(page);
7289         nested_release_page(page);
7290
7291         nested_free_vmcs02(vmx, vmptr);
7292
7293         nested_vmx_succeed(vcpu);
7294         return kvm_skip_emulated_instruction(vcpu);
7295 }
7296
7297 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7298
7299 /* Emulate the VMLAUNCH instruction */
7300 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7301 {
7302         return nested_vmx_run(vcpu, true);
7303 }
7304
7305 /* Emulate the VMRESUME instruction */
7306 static int handle_vmresume(struct kvm_vcpu *vcpu)
7307 {
7308
7309         return nested_vmx_run(vcpu, false);
7310 }
7311
7312 enum vmcs_field_type {
7313         VMCS_FIELD_TYPE_U16 = 0,
7314         VMCS_FIELD_TYPE_U64 = 1,
7315         VMCS_FIELD_TYPE_U32 = 2,
7316         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7317 };
7318
7319 static inline int vmcs_field_type(unsigned long field)
7320 {
7321         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7322                 return VMCS_FIELD_TYPE_U32;
7323         return (field >> 13) & 0x3 ;
7324 }
7325
7326 static inline int vmcs_field_readonly(unsigned long field)
7327 {
7328         return (((field >> 10) & 0x3) == 1);
7329 }
7330
7331 /*
7332  * Read a vmcs12 field. Since these can have varying lengths and we return
7333  * one type, we chose the biggest type (u64) and zero-extend the return value
7334  * to that size. Note that the caller, handle_vmread, might need to use only
7335  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7336  * 64-bit fields are to be returned).
7337  */
7338 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7339                                   unsigned long field, u64 *ret)
7340 {
7341         short offset = vmcs_field_to_offset(field);
7342         char *p;
7343
7344         if (offset < 0)
7345                 return offset;
7346
7347         p = ((char *)(get_vmcs12(vcpu))) + offset;
7348
7349         switch (vmcs_field_type(field)) {
7350         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7351                 *ret = *((natural_width *)p);
7352                 return 0;
7353         case VMCS_FIELD_TYPE_U16:
7354                 *ret = *((u16 *)p);
7355                 return 0;
7356         case VMCS_FIELD_TYPE_U32:
7357                 *ret = *((u32 *)p);
7358                 return 0;
7359         case VMCS_FIELD_TYPE_U64:
7360                 *ret = *((u64 *)p);
7361                 return 0;
7362         default:
7363                 WARN_ON(1);
7364                 return -ENOENT;
7365         }
7366 }
7367
7368
7369 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7370                                    unsigned long field, u64 field_value){
7371         short offset = vmcs_field_to_offset(field);
7372         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7373         if (offset < 0)
7374                 return offset;
7375
7376         switch (vmcs_field_type(field)) {
7377         case VMCS_FIELD_TYPE_U16:
7378                 *(u16 *)p = field_value;
7379                 return 0;
7380         case VMCS_FIELD_TYPE_U32:
7381                 *(u32 *)p = field_value;
7382                 return 0;
7383         case VMCS_FIELD_TYPE_U64:
7384                 *(u64 *)p = field_value;
7385                 return 0;
7386         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7387                 *(natural_width *)p = field_value;
7388                 return 0;
7389         default:
7390                 WARN_ON(1);
7391                 return -ENOENT;
7392         }
7393
7394 }
7395
7396 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7397 {
7398         int i;
7399         unsigned long field;
7400         u64 field_value;
7401         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7402         const unsigned long *fields = shadow_read_write_fields;
7403         const int num_fields = max_shadow_read_write_fields;
7404
7405         preempt_disable();
7406
7407         vmcs_load(shadow_vmcs);
7408
7409         for (i = 0; i < num_fields; i++) {
7410                 field = fields[i];
7411                 switch (vmcs_field_type(field)) {
7412                 case VMCS_FIELD_TYPE_U16:
7413                         field_value = vmcs_read16(field);
7414                         break;
7415                 case VMCS_FIELD_TYPE_U32:
7416                         field_value = vmcs_read32(field);
7417                         break;
7418                 case VMCS_FIELD_TYPE_U64:
7419                         field_value = vmcs_read64(field);
7420                         break;
7421                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7422                         field_value = vmcs_readl(field);
7423                         break;
7424                 default:
7425                         WARN_ON(1);
7426                         continue;
7427                 }
7428                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7429         }
7430
7431         vmcs_clear(shadow_vmcs);
7432         vmcs_load(vmx->loaded_vmcs->vmcs);
7433
7434         preempt_enable();
7435 }
7436
7437 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7438 {
7439         const unsigned long *fields[] = {
7440                 shadow_read_write_fields,
7441                 shadow_read_only_fields
7442         };
7443         const int max_fields[] = {
7444                 max_shadow_read_write_fields,
7445                 max_shadow_read_only_fields
7446         };
7447         int i, q;
7448         unsigned long field;
7449         u64 field_value = 0;
7450         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7451
7452         vmcs_load(shadow_vmcs);
7453
7454         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7455                 for (i = 0; i < max_fields[q]; i++) {
7456                         field = fields[q][i];
7457                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7458
7459                         switch (vmcs_field_type(field)) {
7460                         case VMCS_FIELD_TYPE_U16:
7461                                 vmcs_write16(field, (u16)field_value);
7462                                 break;
7463                         case VMCS_FIELD_TYPE_U32:
7464                                 vmcs_write32(field, (u32)field_value);
7465                                 break;
7466                         case VMCS_FIELD_TYPE_U64:
7467                                 vmcs_write64(field, (u64)field_value);
7468                                 break;
7469                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7470                                 vmcs_writel(field, (long)field_value);
7471                                 break;
7472                         default:
7473                                 WARN_ON(1);
7474                                 break;
7475                         }
7476                 }
7477         }
7478
7479         vmcs_clear(shadow_vmcs);
7480         vmcs_load(vmx->loaded_vmcs->vmcs);
7481 }
7482
7483 /*
7484  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7485  * used before) all generate the same failure when it is missing.
7486  */
7487 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7488 {
7489         struct vcpu_vmx *vmx = to_vmx(vcpu);
7490         if (vmx->nested.current_vmptr == -1ull) {
7491                 nested_vmx_failInvalid(vcpu);
7492                 return 0;
7493         }
7494         return 1;
7495 }
7496
7497 static int handle_vmread(struct kvm_vcpu *vcpu)
7498 {
7499         unsigned long field;
7500         u64 field_value;
7501         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7502         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7503         gva_t gva = 0;
7504
7505         if (!nested_vmx_check_permission(vcpu))
7506                 return 1;
7507
7508         if (!nested_vmx_check_vmcs12(vcpu))
7509                 return kvm_skip_emulated_instruction(vcpu);
7510
7511         /* Decode instruction info and find the field to read */
7512         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7513         /* Read the field, zero-extended to a u64 field_value */
7514         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7515                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7516                 return kvm_skip_emulated_instruction(vcpu);
7517         }
7518         /*
7519          * Now copy part of this value to register or memory, as requested.
7520          * Note that the number of bits actually copied is 32 or 64 depending
7521          * on the guest's mode (32 or 64 bit), not on the given field's length.
7522          */
7523         if (vmx_instruction_info & (1u << 10)) {
7524                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7525                         field_value);
7526         } else {
7527                 if (get_vmx_mem_address(vcpu, exit_qualification,
7528                                 vmx_instruction_info, true, &gva))
7529                         return 1;
7530                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7531                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7532                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7533         }
7534
7535         nested_vmx_succeed(vcpu);
7536         return kvm_skip_emulated_instruction(vcpu);
7537 }
7538
7539
7540 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7541 {
7542         unsigned long field;
7543         gva_t gva;
7544         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7545         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7546         /* The value to write might be 32 or 64 bits, depending on L1's long
7547          * mode, and eventually we need to write that into a field of several
7548          * possible lengths. The code below first zero-extends the value to 64
7549          * bit (field_value), and then copies only the appropriate number of
7550          * bits into the vmcs12 field.
7551          */
7552         u64 field_value = 0;
7553         struct x86_exception e;
7554
7555         if (!nested_vmx_check_permission(vcpu))
7556                 return 1;
7557
7558         if (!nested_vmx_check_vmcs12(vcpu))
7559                 return kvm_skip_emulated_instruction(vcpu);
7560
7561         if (vmx_instruction_info & (1u << 10))
7562                 field_value = kvm_register_readl(vcpu,
7563                         (((vmx_instruction_info) >> 3) & 0xf));
7564         else {
7565                 if (get_vmx_mem_address(vcpu, exit_qualification,
7566                                 vmx_instruction_info, false, &gva))
7567                         return 1;
7568                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7569                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7570                         kvm_inject_page_fault(vcpu, &e);
7571                         return 1;
7572                 }
7573         }
7574
7575
7576         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7577         if (vmcs_field_readonly(field)) {
7578                 nested_vmx_failValid(vcpu,
7579                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7580                 return kvm_skip_emulated_instruction(vcpu);
7581         }
7582
7583         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7584                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7585                 return kvm_skip_emulated_instruction(vcpu);
7586         }
7587
7588         nested_vmx_succeed(vcpu);
7589         return kvm_skip_emulated_instruction(vcpu);
7590 }
7591
7592 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7593 {
7594         vmx->nested.current_vmptr = vmptr;
7595         if (enable_shadow_vmcs) {
7596                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7597                               SECONDARY_EXEC_SHADOW_VMCS);
7598                 vmcs_write64(VMCS_LINK_POINTER,
7599                              __pa(vmx->vmcs01.shadow_vmcs));
7600                 vmx->nested.sync_shadow_vmcs = true;
7601         }
7602 }
7603
7604 /* Emulate the VMPTRLD instruction */
7605 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7606 {
7607         struct vcpu_vmx *vmx = to_vmx(vcpu);
7608         gpa_t vmptr;
7609
7610         if (!nested_vmx_check_permission(vcpu))
7611                 return 1;
7612
7613         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7614                 return 1;
7615
7616         if (vmx->nested.current_vmptr != vmptr) {
7617                 struct vmcs12 *new_vmcs12;
7618                 struct page *page;
7619                 page = nested_get_page(vcpu, vmptr);
7620                 if (page == NULL) {
7621                         nested_vmx_failInvalid(vcpu);
7622                         return kvm_skip_emulated_instruction(vcpu);
7623                 }
7624                 new_vmcs12 = kmap(page);
7625                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7626                         kunmap(page);
7627                         nested_release_page_clean(page);
7628                         nested_vmx_failValid(vcpu,
7629                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7630                         return kvm_skip_emulated_instruction(vcpu);
7631                 }
7632
7633                 nested_release_vmcs12(vmx);
7634                 vmx->nested.current_vmcs12 = new_vmcs12;
7635                 vmx->nested.current_vmcs12_page = page;
7636                 /*
7637                  * Load VMCS12 from guest memory since it is not already
7638                  * cached.
7639                  */
7640                 memcpy(vmx->nested.cached_vmcs12,
7641                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7642                 set_current_vmptr(vmx, vmptr);
7643         }
7644
7645         nested_vmx_succeed(vcpu);
7646         return kvm_skip_emulated_instruction(vcpu);
7647 }
7648
7649 /* Emulate the VMPTRST instruction */
7650 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7651 {
7652         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7653         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7654         gva_t vmcs_gva;
7655         struct x86_exception e;
7656
7657         if (!nested_vmx_check_permission(vcpu))
7658                 return 1;
7659
7660         if (get_vmx_mem_address(vcpu, exit_qualification,
7661                         vmx_instruction_info, true, &vmcs_gva))
7662                 return 1;
7663         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7664         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7665                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7666                                  sizeof(u64), &e)) {
7667                 kvm_inject_page_fault(vcpu, &e);
7668                 return 1;
7669         }
7670         nested_vmx_succeed(vcpu);
7671         return kvm_skip_emulated_instruction(vcpu);
7672 }
7673
7674 /* Emulate the INVEPT instruction */
7675 static int handle_invept(struct kvm_vcpu *vcpu)
7676 {
7677         struct vcpu_vmx *vmx = to_vmx(vcpu);
7678         u32 vmx_instruction_info, types;
7679         unsigned long type;
7680         gva_t gva;
7681         struct x86_exception e;
7682         struct {
7683                 u64 eptp, gpa;
7684         } operand;
7685
7686         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7687               SECONDARY_EXEC_ENABLE_EPT) ||
7688             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7689                 kvm_queue_exception(vcpu, UD_VECTOR);
7690                 return 1;
7691         }
7692
7693         if (!nested_vmx_check_permission(vcpu))
7694                 return 1;
7695
7696         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7697                 kvm_queue_exception(vcpu, UD_VECTOR);
7698                 return 1;
7699         }
7700
7701         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7702         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7703
7704         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7705
7706         if (type >= 32 || !(types & (1 << type))) {
7707                 nested_vmx_failValid(vcpu,
7708                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7709                 return kvm_skip_emulated_instruction(vcpu);
7710         }
7711
7712         /* According to the Intel VMX instruction reference, the memory
7713          * operand is read even if it isn't needed (e.g., for type==global)
7714          */
7715         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7716                         vmx_instruction_info, false, &gva))
7717                 return 1;
7718         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7719                                 sizeof(operand), &e)) {
7720                 kvm_inject_page_fault(vcpu, &e);
7721                 return 1;
7722         }
7723
7724         switch (type) {
7725         case VMX_EPT_EXTENT_GLOBAL:
7726         /*
7727          * TODO: track mappings and invalidate
7728          * single context requests appropriately
7729          */
7730         case VMX_EPT_EXTENT_CONTEXT:
7731                 kvm_mmu_sync_roots(vcpu);
7732                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7733                 nested_vmx_succeed(vcpu);
7734                 break;
7735         default:
7736                 BUG_ON(1);
7737                 break;
7738         }
7739
7740         return kvm_skip_emulated_instruction(vcpu);
7741 }
7742
7743 static int handle_invvpid(struct kvm_vcpu *vcpu)
7744 {
7745         struct vcpu_vmx *vmx = to_vmx(vcpu);
7746         u32 vmx_instruction_info;
7747         unsigned long type, types;
7748         gva_t gva;
7749         struct x86_exception e;
7750         int vpid;
7751
7752         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7753               SECONDARY_EXEC_ENABLE_VPID) ||
7754                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7755                 kvm_queue_exception(vcpu, UD_VECTOR);
7756                 return 1;
7757         }
7758
7759         if (!nested_vmx_check_permission(vcpu))
7760                 return 1;
7761
7762         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7763         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7764
7765         types = (vmx->nested.nested_vmx_vpid_caps &
7766                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7767
7768         if (type >= 32 || !(types & (1 << type))) {
7769                 nested_vmx_failValid(vcpu,
7770                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7771                 return kvm_skip_emulated_instruction(vcpu);
7772         }
7773
7774         /* according to the intel vmx instruction reference, the memory
7775          * operand is read even if it isn't needed (e.g., for type==global)
7776          */
7777         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7778                         vmx_instruction_info, false, &gva))
7779                 return 1;
7780         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7781                                 sizeof(u32), &e)) {
7782                 kvm_inject_page_fault(vcpu, &e);
7783                 return 1;
7784         }
7785
7786         switch (type) {
7787         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7788         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7789         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7790                 if (!vpid) {
7791                         nested_vmx_failValid(vcpu,
7792                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7793                         return kvm_skip_emulated_instruction(vcpu);
7794                 }
7795                 break;
7796         case VMX_VPID_EXTENT_ALL_CONTEXT:
7797                 break;
7798         default:
7799                 WARN_ON_ONCE(1);
7800                 return kvm_skip_emulated_instruction(vcpu);
7801         }
7802
7803         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7804         nested_vmx_succeed(vcpu);
7805
7806         return kvm_skip_emulated_instruction(vcpu);
7807 }
7808
7809 static int handle_pml_full(struct kvm_vcpu *vcpu)
7810 {
7811         unsigned long exit_qualification;
7812
7813         trace_kvm_pml_full(vcpu->vcpu_id);
7814
7815         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7816
7817         /*
7818          * PML buffer FULL happened while executing iret from NMI,
7819          * "blocked by NMI" bit has to be set before next VM entry.
7820          */
7821         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7822                         cpu_has_virtual_nmis() &&
7823                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7824                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7825                                 GUEST_INTR_STATE_NMI);
7826
7827         /*
7828          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7829          * here.., and there's no userspace involvement needed for PML.
7830          */
7831         return 1;
7832 }
7833
7834 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7835 {
7836         kvm_lapic_expired_hv_timer(vcpu);
7837         return 1;
7838 }
7839
7840 /*
7841  * The exit handlers return 1 if the exit was handled fully and guest execution
7842  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7843  * to be done to userspace and return 0.
7844  */
7845 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7846         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7847         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7848         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7849         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7850         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7851         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7852         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7853         [EXIT_REASON_CPUID]                   = handle_cpuid,
7854         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7855         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7856         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7857         [EXIT_REASON_HLT]                     = handle_halt,
7858         [EXIT_REASON_INVD]                    = handle_invd,
7859         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7860         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7861         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7862         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7863         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7864         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7865         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7866         [EXIT_REASON_VMREAD]                  = handle_vmread,
7867         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7868         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7869         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7870         [EXIT_REASON_VMON]                    = handle_vmon,
7871         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7872         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7873         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7874         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7875         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7876         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7877         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7878         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7879         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7880         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7881         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7882         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7883         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7884         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7885         [EXIT_REASON_INVEPT]                  = handle_invept,
7886         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7887         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7888         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7889         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7890         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7891 };
7892
7893 static const int kvm_vmx_max_exit_handlers =
7894         ARRAY_SIZE(kvm_vmx_exit_handlers);
7895
7896 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7897                                        struct vmcs12 *vmcs12)
7898 {
7899         unsigned long exit_qualification;
7900         gpa_t bitmap, last_bitmap;
7901         unsigned int port;
7902         int size;
7903         u8 b;
7904
7905         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7906                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7907
7908         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7909
7910         port = exit_qualification >> 16;
7911         size = (exit_qualification & 7) + 1;
7912
7913         last_bitmap = (gpa_t)-1;
7914         b = -1;
7915
7916         while (size > 0) {
7917                 if (port < 0x8000)
7918                         bitmap = vmcs12->io_bitmap_a;
7919                 else if (port < 0x10000)
7920                         bitmap = vmcs12->io_bitmap_b;
7921                 else
7922                         return true;
7923                 bitmap += (port & 0x7fff) / 8;
7924
7925                 if (last_bitmap != bitmap)
7926                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7927                                 return true;
7928                 if (b & (1 << (port & 7)))
7929                         return true;
7930
7931                 port++;
7932                 size--;
7933                 last_bitmap = bitmap;
7934         }
7935
7936         return false;
7937 }
7938
7939 /*
7940  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7941  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7942  * disinterest in the current event (read or write a specific MSR) by using an
7943  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7944  */
7945 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7946         struct vmcs12 *vmcs12, u32 exit_reason)
7947 {
7948         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7949         gpa_t bitmap;
7950
7951         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7952                 return true;
7953
7954         /*
7955          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7956          * for the four combinations of read/write and low/high MSR numbers.
7957          * First we need to figure out which of the four to use:
7958          */
7959         bitmap = vmcs12->msr_bitmap;
7960         if (exit_reason == EXIT_REASON_MSR_WRITE)
7961                 bitmap += 2048;
7962         if (msr_index >= 0xc0000000) {
7963                 msr_index -= 0xc0000000;
7964                 bitmap += 1024;
7965         }
7966
7967         /* Then read the msr_index'th bit from this bitmap: */
7968         if (msr_index < 1024*8) {
7969                 unsigned char b;
7970                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7971                         return true;
7972                 return 1 & (b >> (msr_index & 7));
7973         } else
7974                 return true; /* let L1 handle the wrong parameter */
7975 }
7976
7977 /*
7978  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7979  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7980  * intercept (via guest_host_mask etc.) the current event.
7981  */
7982 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7983         struct vmcs12 *vmcs12)
7984 {
7985         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7986         int cr = exit_qualification & 15;
7987         int reg = (exit_qualification >> 8) & 15;
7988         unsigned long val = kvm_register_readl(vcpu, reg);
7989
7990         switch ((exit_qualification >> 4) & 3) {
7991         case 0: /* mov to cr */
7992                 switch (cr) {
7993                 case 0:
7994                         if (vmcs12->cr0_guest_host_mask &
7995                             (val ^ vmcs12->cr0_read_shadow))
7996                                 return true;
7997                         break;
7998                 case 3:
7999                         if ((vmcs12->cr3_target_count >= 1 &&
8000                                         vmcs12->cr3_target_value0 == val) ||
8001                                 (vmcs12->cr3_target_count >= 2 &&
8002                                         vmcs12->cr3_target_value1 == val) ||
8003                                 (vmcs12->cr3_target_count >= 3 &&
8004                                         vmcs12->cr3_target_value2 == val) ||
8005                                 (vmcs12->cr3_target_count >= 4 &&
8006                                         vmcs12->cr3_target_value3 == val))
8007                                 return false;
8008                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8009                                 return true;
8010                         break;
8011                 case 4:
8012                         if (vmcs12->cr4_guest_host_mask &
8013                             (vmcs12->cr4_read_shadow ^ val))
8014                                 return true;
8015                         break;
8016                 case 8:
8017                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8018                                 return true;
8019                         break;
8020                 }
8021                 break;
8022         case 2: /* clts */
8023                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8024                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8025                         return true;
8026                 break;
8027         case 1: /* mov from cr */
8028                 switch (cr) {
8029                 case 3:
8030                         if (vmcs12->cpu_based_vm_exec_control &
8031                             CPU_BASED_CR3_STORE_EXITING)
8032                                 return true;
8033                         break;
8034                 case 8:
8035                         if (vmcs12->cpu_based_vm_exec_control &
8036                             CPU_BASED_CR8_STORE_EXITING)
8037                                 return true;
8038                         break;
8039                 }
8040                 break;
8041         case 3: /* lmsw */
8042                 /*
8043                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8044                  * cr0. Other attempted changes are ignored, with no exit.
8045                  */
8046                 if (vmcs12->cr0_guest_host_mask & 0xe &
8047                     (val ^ vmcs12->cr0_read_shadow))
8048                         return true;
8049                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8050                     !(vmcs12->cr0_read_shadow & 0x1) &&
8051                     (val & 0x1))
8052                         return true;
8053                 break;
8054         }
8055         return false;
8056 }
8057
8058 /*
8059  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8060  * should handle it ourselves in L0 (and then continue L2). Only call this
8061  * when in is_guest_mode (L2).
8062  */
8063 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8064 {
8065         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8066         struct vcpu_vmx *vmx = to_vmx(vcpu);
8067         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8068         u32 exit_reason = vmx->exit_reason;
8069
8070         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8071                                 vmcs_readl(EXIT_QUALIFICATION),
8072                                 vmx->idt_vectoring_info,
8073                                 intr_info,
8074                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8075                                 KVM_ISA_VMX);
8076
8077         if (vmx->nested.nested_run_pending)
8078                 return false;
8079
8080         if (unlikely(vmx->fail)) {
8081                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8082                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8083                 return true;
8084         }
8085
8086         switch (exit_reason) {
8087         case EXIT_REASON_EXCEPTION_NMI:
8088                 if (is_nmi(intr_info))
8089                         return false;
8090                 else if (is_page_fault(intr_info))
8091                         return enable_ept;
8092                 else if (is_no_device(intr_info) &&
8093                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8094                         return false;
8095                 else if (is_debug(intr_info) &&
8096                          vcpu->guest_debug &
8097                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8098                         return false;
8099                 else if (is_breakpoint(intr_info) &&
8100                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8101                         return false;
8102                 return vmcs12->exception_bitmap &
8103                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8104         case EXIT_REASON_EXTERNAL_INTERRUPT:
8105                 return false;
8106         case EXIT_REASON_TRIPLE_FAULT:
8107                 return true;
8108         case EXIT_REASON_PENDING_INTERRUPT:
8109                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8110         case EXIT_REASON_NMI_WINDOW:
8111                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8112         case EXIT_REASON_TASK_SWITCH:
8113                 return true;
8114         case EXIT_REASON_CPUID:
8115                 return true;
8116         case EXIT_REASON_HLT:
8117                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8118         case EXIT_REASON_INVD:
8119                 return true;
8120         case EXIT_REASON_INVLPG:
8121                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8122         case EXIT_REASON_RDPMC:
8123                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8124         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8125                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8126         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8127         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8128         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8129         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8130         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8131         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8132                 /*
8133                  * VMX instructions trap unconditionally. This allows L1 to
8134                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8135                  */
8136                 return true;
8137         case EXIT_REASON_CR_ACCESS:
8138                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8139         case EXIT_REASON_DR_ACCESS:
8140                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8141         case EXIT_REASON_IO_INSTRUCTION:
8142                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8143         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8144                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8145         case EXIT_REASON_MSR_READ:
8146         case EXIT_REASON_MSR_WRITE:
8147                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8148         case EXIT_REASON_INVALID_STATE:
8149                 return true;
8150         case EXIT_REASON_MWAIT_INSTRUCTION:
8151                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8152         case EXIT_REASON_MONITOR_TRAP_FLAG:
8153                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8154         case EXIT_REASON_MONITOR_INSTRUCTION:
8155                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8156         case EXIT_REASON_PAUSE_INSTRUCTION:
8157                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8158                         nested_cpu_has2(vmcs12,
8159                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8160         case EXIT_REASON_MCE_DURING_VMENTRY:
8161                 return false;
8162         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8163                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8164         case EXIT_REASON_APIC_ACCESS:
8165                 return nested_cpu_has2(vmcs12,
8166                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8167         case EXIT_REASON_APIC_WRITE:
8168         case EXIT_REASON_EOI_INDUCED:
8169                 /* apic_write and eoi_induced should exit unconditionally. */
8170                 return true;
8171         case EXIT_REASON_EPT_VIOLATION:
8172                 /*
8173                  * L0 always deals with the EPT violation. If nested EPT is
8174                  * used, and the nested mmu code discovers that the address is
8175                  * missing in the guest EPT table (EPT12), the EPT violation
8176                  * will be injected with nested_ept_inject_page_fault()
8177                  */
8178                 return false;
8179         case EXIT_REASON_EPT_MISCONFIG:
8180                 /*
8181                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8182                  * table (shadow on EPT) or a merged EPT table that L0 built
8183                  * (EPT on EPT). So any problems with the structure of the
8184                  * table is L0's fault.
8185                  */
8186                 return false;
8187         case EXIT_REASON_WBINVD:
8188                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8189         case EXIT_REASON_XSETBV:
8190                 return true;
8191         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8192                 /*
8193                  * This should never happen, since it is not possible to
8194                  * set XSS to a non-zero value---neither in L1 nor in L2.
8195                  * If if it were, XSS would have to be checked against
8196                  * the XSS exit bitmap in vmcs12.
8197                  */
8198                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8199         case EXIT_REASON_PREEMPTION_TIMER:
8200                 return false;
8201         default:
8202                 return true;
8203         }
8204 }
8205
8206 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8207 {
8208         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8209         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8210 }
8211
8212 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8213 {
8214         if (vmx->pml_pg) {
8215                 __free_page(vmx->pml_pg);
8216                 vmx->pml_pg = NULL;
8217         }
8218 }
8219
8220 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8221 {
8222         struct vcpu_vmx *vmx = to_vmx(vcpu);
8223         u64 *pml_buf;
8224         u16 pml_idx;
8225
8226         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8227
8228         /* Do nothing if PML buffer is empty */
8229         if (pml_idx == (PML_ENTITY_NUM - 1))
8230                 return;
8231
8232         /* PML index always points to next available PML buffer entity */
8233         if (pml_idx >= PML_ENTITY_NUM)
8234                 pml_idx = 0;
8235         else
8236                 pml_idx++;
8237
8238         pml_buf = page_address(vmx->pml_pg);
8239         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8240                 u64 gpa;
8241
8242                 gpa = pml_buf[pml_idx];
8243                 WARN_ON(gpa & (PAGE_SIZE - 1));
8244                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8245         }
8246
8247         /* reset PML index */
8248         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8249 }
8250
8251 /*
8252  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8253  * Called before reporting dirty_bitmap to userspace.
8254  */
8255 static void kvm_flush_pml_buffers(struct kvm *kvm)
8256 {
8257         int i;
8258         struct kvm_vcpu *vcpu;
8259         /*
8260          * We only need to kick vcpu out of guest mode here, as PML buffer
8261          * is flushed at beginning of all VMEXITs, and it's obvious that only
8262          * vcpus running in guest are possible to have unflushed GPAs in PML
8263          * buffer.
8264          */
8265         kvm_for_each_vcpu(i, vcpu, kvm)
8266                 kvm_vcpu_kick(vcpu);
8267 }
8268
8269 static void vmx_dump_sel(char *name, uint32_t sel)
8270 {
8271         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8272                name, vmcs_read16(sel),
8273                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8274                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8275                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8276 }
8277
8278 static void vmx_dump_dtsel(char *name, uint32_t limit)
8279 {
8280         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8281                name, vmcs_read32(limit),
8282                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8283 }
8284
8285 static void dump_vmcs(void)
8286 {
8287         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8288         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8289         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8290         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8291         u32 secondary_exec_control = 0;
8292         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8293         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8294         int i, n;
8295
8296         if (cpu_has_secondary_exec_ctrls())
8297                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8298
8299         pr_err("*** Guest State ***\n");
8300         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8301                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8302                vmcs_readl(CR0_GUEST_HOST_MASK));
8303         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8304                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8305         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8306         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8307             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8308         {
8309                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8310                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8311                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8312                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8313         }
8314         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8315                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8316         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8317                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8318         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8319                vmcs_readl(GUEST_SYSENTER_ESP),
8320                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8321         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8322         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8323         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8324         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8325         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8326         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8327         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8328         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8329         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8330         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8331         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8332             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8333                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8334                        efer, vmcs_read64(GUEST_IA32_PAT));
8335         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8336                vmcs_read64(GUEST_IA32_DEBUGCTL),
8337                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8338         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8339                 pr_err("PerfGlobCtl = 0x%016llx\n",
8340                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8341         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8342                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8343         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8344                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8345                vmcs_read32(GUEST_ACTIVITY_STATE));
8346         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8347                 pr_err("InterruptStatus = %04x\n",
8348                        vmcs_read16(GUEST_INTR_STATUS));
8349
8350         pr_err("*** Host State ***\n");
8351         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8352                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8353         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8354                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8355                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8356                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8357                vmcs_read16(HOST_TR_SELECTOR));
8358         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8359                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8360                vmcs_readl(HOST_TR_BASE));
8361         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8362                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8363         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8364                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8365                vmcs_readl(HOST_CR4));
8366         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8367                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8368                vmcs_read32(HOST_IA32_SYSENTER_CS),
8369                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8370         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8371                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8372                        vmcs_read64(HOST_IA32_EFER),
8373                        vmcs_read64(HOST_IA32_PAT));
8374         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8375                 pr_err("PerfGlobCtl = 0x%016llx\n",
8376                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8377
8378         pr_err("*** Control State ***\n");
8379         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8380                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8381         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8382         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8383                vmcs_read32(EXCEPTION_BITMAP),
8384                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8385                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8386         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8387                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8388                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8389                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8390         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8391                vmcs_read32(VM_EXIT_INTR_INFO),
8392                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8393                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8394         pr_err("        reason=%08x qualification=%016lx\n",
8395                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8396         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8397                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8398                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8399         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8400         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8401                 pr_err("TSC Multiplier = 0x%016llx\n",
8402                        vmcs_read64(TSC_MULTIPLIER));
8403         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8404                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8405         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8406                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8407         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8408                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8409         n = vmcs_read32(CR3_TARGET_COUNT);
8410         for (i = 0; i + 1 < n; i += 4)
8411                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8412                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8413                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8414         if (i < n)
8415                 pr_err("CR3 target%u=%016lx\n",
8416                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8417         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8418                 pr_err("PLE Gap=%08x Window=%08x\n",
8419                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8420         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8421                 pr_err("Virtual processor ID = 0x%04x\n",
8422                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8423 }
8424
8425 /*
8426  * The guest has exited.  See if we can fix it or if we need userspace
8427  * assistance.
8428  */
8429 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8430 {
8431         struct vcpu_vmx *vmx = to_vmx(vcpu);
8432         u32 exit_reason = vmx->exit_reason;
8433         u32 vectoring_info = vmx->idt_vectoring_info;
8434
8435         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8436         vcpu->arch.gpa_available = false;
8437
8438         /*
8439          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8440          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8441          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8442          * mode as if vcpus is in root mode, the PML buffer must has been
8443          * flushed already.
8444          */
8445         if (enable_pml)
8446                 vmx_flush_pml_buffer(vcpu);
8447
8448         /* If guest state is invalid, start emulating */
8449         if (vmx->emulation_required)
8450                 return handle_invalid_guest_state(vcpu);
8451
8452         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8453                 nested_vmx_vmexit(vcpu, exit_reason,
8454                                   vmcs_read32(VM_EXIT_INTR_INFO),
8455                                   vmcs_readl(EXIT_QUALIFICATION));
8456                 return 1;
8457         }
8458
8459         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8460                 dump_vmcs();
8461                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8462                 vcpu->run->fail_entry.hardware_entry_failure_reason
8463                         = exit_reason;
8464                 return 0;
8465         }
8466
8467         if (unlikely(vmx->fail)) {
8468                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8469                 vcpu->run->fail_entry.hardware_entry_failure_reason
8470                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8471                 return 0;
8472         }
8473
8474         /*
8475          * Note:
8476          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8477          * delivery event since it indicates guest is accessing MMIO.
8478          * The vm-exit can be triggered again after return to guest that
8479          * will cause infinite loop.
8480          */
8481         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8482                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8483                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8484                         exit_reason != EXIT_REASON_PML_FULL &&
8485                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8486                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8487                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8488                 vcpu->run->internal.ndata = 2;
8489                 vcpu->run->internal.data[0] = vectoring_info;
8490                 vcpu->run->internal.data[1] = exit_reason;
8491                 return 0;
8492         }
8493
8494         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8495             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8496                                         get_vmcs12(vcpu))))) {
8497                 if (vmx_interrupt_allowed(vcpu)) {
8498                         vmx->soft_vnmi_blocked = 0;
8499                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8500                            vcpu->arch.nmi_pending) {
8501                         /*
8502                          * This CPU don't support us in finding the end of an
8503                          * NMI-blocked window if the guest runs with IRQs
8504                          * disabled. So we pull the trigger after 1 s of
8505                          * futile waiting, but inform the user about this.
8506                          */
8507                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8508                                "state on VCPU %d after 1 s timeout\n",
8509                                __func__, vcpu->vcpu_id);
8510                         vmx->soft_vnmi_blocked = 0;
8511                 }
8512         }
8513
8514         if (exit_reason < kvm_vmx_max_exit_handlers
8515             && kvm_vmx_exit_handlers[exit_reason])
8516                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8517         else {
8518                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8519                 kvm_queue_exception(vcpu, UD_VECTOR);
8520                 return 1;
8521         }
8522 }
8523
8524 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8525 {
8526         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8527
8528         if (is_guest_mode(vcpu) &&
8529                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8530                 return;
8531
8532         if (irr == -1 || tpr < irr) {
8533                 vmcs_write32(TPR_THRESHOLD, 0);
8534                 return;
8535         }
8536
8537         vmcs_write32(TPR_THRESHOLD, irr);
8538 }
8539
8540 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8541 {
8542         u32 sec_exec_control;
8543
8544         /* Postpone execution until vmcs01 is the current VMCS. */
8545         if (is_guest_mode(vcpu)) {
8546                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8547                 return;
8548         }
8549
8550         if (!cpu_has_vmx_virtualize_x2apic_mode())
8551                 return;
8552
8553         if (!cpu_need_tpr_shadow(vcpu))
8554                 return;
8555
8556         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8557
8558         if (set) {
8559                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8560                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8561         } else {
8562                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8563                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8564         }
8565         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8566
8567         vmx_set_msr_bitmap(vcpu);
8568 }
8569
8570 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8571 {
8572         struct vcpu_vmx *vmx = to_vmx(vcpu);
8573
8574         /*
8575          * Currently we do not handle the nested case where L2 has an
8576          * APIC access page of its own; that page is still pinned.
8577          * Hence, we skip the case where the VCPU is in guest mode _and_
8578          * L1 prepared an APIC access page for L2.
8579          *
8580          * For the case where L1 and L2 share the same APIC access page
8581          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8582          * in the vmcs12), this function will only update either the vmcs01
8583          * or the vmcs02.  If the former, the vmcs02 will be updated by
8584          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8585          * the next L2->L1 exit.
8586          */
8587         if (!is_guest_mode(vcpu) ||
8588             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8589                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8590                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8591 }
8592
8593 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8594 {
8595         u16 status;
8596         u8 old;
8597
8598         if (max_isr == -1)
8599                 max_isr = 0;
8600
8601         status = vmcs_read16(GUEST_INTR_STATUS);
8602         old = status >> 8;
8603         if (max_isr != old) {
8604                 status &= 0xff;
8605                 status |= max_isr << 8;
8606                 vmcs_write16(GUEST_INTR_STATUS, status);
8607         }
8608 }
8609
8610 static void vmx_set_rvi(int vector)
8611 {
8612         u16 status;
8613         u8 old;
8614
8615         if (vector == -1)
8616                 vector = 0;
8617
8618         status = vmcs_read16(GUEST_INTR_STATUS);
8619         old = (u8)status & 0xff;
8620         if ((u8)vector != old) {
8621                 status &= ~0xff;
8622                 status |= (u8)vector;
8623                 vmcs_write16(GUEST_INTR_STATUS, status);
8624         }
8625 }
8626
8627 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8628 {
8629         if (!is_guest_mode(vcpu)) {
8630                 vmx_set_rvi(max_irr);
8631                 return;
8632         }
8633
8634         if (max_irr == -1)
8635                 return;
8636
8637         /*
8638          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8639          * handles it.
8640          */
8641         if (nested_exit_on_intr(vcpu))
8642                 return;
8643
8644         /*
8645          * Else, fall back to pre-APICv interrupt injection since L2
8646          * is run without virtual interrupt delivery.
8647          */
8648         if (!kvm_event_needs_reinjection(vcpu) &&
8649             vmx_interrupt_allowed(vcpu)) {
8650                 kvm_queue_interrupt(vcpu, max_irr, false);
8651                 vmx_inject_irq(vcpu);
8652         }
8653 }
8654
8655 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8656 {
8657         struct vcpu_vmx *vmx = to_vmx(vcpu);
8658         int max_irr;
8659
8660         WARN_ON(!vcpu->arch.apicv_active);
8661         if (pi_test_on(&vmx->pi_desc)) {
8662                 pi_clear_on(&vmx->pi_desc);
8663                 /*
8664                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8665                  * But on x86 this is just a compiler barrier anyway.
8666                  */
8667                 smp_mb__after_atomic();
8668                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8669         } else {
8670                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8671         }
8672         vmx_hwapic_irr_update(vcpu, max_irr);
8673         return max_irr;
8674 }
8675
8676 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8677 {
8678         if (!kvm_vcpu_apicv_active(vcpu))
8679                 return;
8680
8681         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8682         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8683         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8684         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8685 }
8686
8687 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8688 {
8689         struct vcpu_vmx *vmx = to_vmx(vcpu);
8690
8691         pi_clear_on(&vmx->pi_desc);
8692         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8693 }
8694
8695 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8696 {
8697         u32 exit_intr_info;
8698
8699         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8700               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8701                 return;
8702
8703         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8704         exit_intr_info = vmx->exit_intr_info;
8705
8706         /* Handle machine checks before interrupts are enabled */
8707         if (is_machine_check(exit_intr_info))
8708                 kvm_machine_check();
8709
8710         /* We need to handle NMIs before interrupts are enabled */
8711         if (is_nmi(exit_intr_info)) {
8712                 kvm_before_handle_nmi(&vmx->vcpu);
8713                 asm("int $2");
8714                 kvm_after_handle_nmi(&vmx->vcpu);
8715         }
8716 }
8717
8718 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8719 {
8720         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8721         register void *__sp asm(_ASM_SP);
8722
8723         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8724                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8725                 unsigned int vector;
8726                 unsigned long entry;
8727                 gate_desc *desc;
8728                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8729 #ifdef CONFIG_X86_64
8730                 unsigned long tmp;
8731 #endif
8732
8733                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8734                 desc = (gate_desc *)vmx->host_idt_base + vector;
8735                 entry = gate_offset(*desc);
8736                 asm volatile(
8737 #ifdef CONFIG_X86_64
8738                         "mov %%" _ASM_SP ", %[sp]\n\t"
8739                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8740                         "push $%c[ss]\n\t"
8741                         "push %[sp]\n\t"
8742 #endif
8743                         "pushf\n\t"
8744                         __ASM_SIZE(push) " $%c[cs]\n\t"
8745                         "call *%[entry]\n\t"
8746                         :
8747 #ifdef CONFIG_X86_64
8748                         [sp]"=&r"(tmp),
8749 #endif
8750                         "+r"(__sp)
8751                         :
8752                         [entry]"r"(entry),
8753                         [ss]"i"(__KERNEL_DS),
8754                         [cs]"i"(__KERNEL_CS)
8755                         );
8756         }
8757 }
8758
8759 static bool vmx_has_high_real_mode_segbase(void)
8760 {
8761         return enable_unrestricted_guest || emulate_invalid_guest_state;
8762 }
8763
8764 static bool vmx_mpx_supported(void)
8765 {
8766         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8767                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8768 }
8769
8770 static bool vmx_xsaves_supported(void)
8771 {
8772         return vmcs_config.cpu_based_2nd_exec_ctrl &
8773                 SECONDARY_EXEC_XSAVES;
8774 }
8775
8776 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8777 {
8778         u32 exit_intr_info;
8779         bool unblock_nmi;
8780         u8 vector;
8781         bool idtv_info_valid;
8782
8783         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8784
8785         if (cpu_has_virtual_nmis()) {
8786                 if (vmx->nmi_known_unmasked)
8787                         return;
8788                 /*
8789                  * Can't use vmx->exit_intr_info since we're not sure what
8790                  * the exit reason is.
8791                  */
8792                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8793                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8794                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8795                 /*
8796                  * SDM 3: 27.7.1.2 (September 2008)
8797                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8798                  * a guest IRET fault.
8799                  * SDM 3: 23.2.2 (September 2008)
8800                  * Bit 12 is undefined in any of the following cases:
8801                  *  If the VM exit sets the valid bit in the IDT-vectoring
8802                  *   information field.
8803                  *  If the VM exit is due to a double fault.
8804                  */
8805                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8806                     vector != DF_VECTOR && !idtv_info_valid)
8807                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8808                                       GUEST_INTR_STATE_NMI);
8809                 else
8810                         vmx->nmi_known_unmasked =
8811                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8812                                   & GUEST_INTR_STATE_NMI);
8813         } else if (unlikely(vmx->soft_vnmi_blocked))
8814                 vmx->vnmi_blocked_time +=
8815                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8816 }
8817
8818 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8819                                       u32 idt_vectoring_info,
8820                                       int instr_len_field,
8821                                       int error_code_field)
8822 {
8823         u8 vector;
8824         int type;
8825         bool idtv_info_valid;
8826
8827         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8828
8829         vcpu->arch.nmi_injected = false;
8830         kvm_clear_exception_queue(vcpu);
8831         kvm_clear_interrupt_queue(vcpu);
8832
8833         if (!idtv_info_valid)
8834                 return;
8835
8836         kvm_make_request(KVM_REQ_EVENT, vcpu);
8837
8838         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8839         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8840
8841         switch (type) {
8842         case INTR_TYPE_NMI_INTR:
8843                 vcpu->arch.nmi_injected = true;
8844                 /*
8845                  * SDM 3: 27.7.1.2 (September 2008)
8846                  * Clear bit "block by NMI" before VM entry if a NMI
8847                  * delivery faulted.
8848                  */
8849                 vmx_set_nmi_mask(vcpu, false);
8850                 break;
8851         case INTR_TYPE_SOFT_EXCEPTION:
8852                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8853                 /* fall through */
8854         case INTR_TYPE_HARD_EXCEPTION:
8855                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8856                         u32 err = vmcs_read32(error_code_field);
8857                         kvm_requeue_exception_e(vcpu, vector, err);
8858                 } else
8859                         kvm_requeue_exception(vcpu, vector);
8860                 break;
8861         case INTR_TYPE_SOFT_INTR:
8862                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8863                 /* fall through */
8864         case INTR_TYPE_EXT_INTR:
8865                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8866                 break;
8867         default:
8868                 break;
8869         }
8870 }
8871
8872 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8873 {
8874         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8875                                   VM_EXIT_INSTRUCTION_LEN,
8876                                   IDT_VECTORING_ERROR_CODE);
8877 }
8878
8879 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8880 {
8881         __vmx_complete_interrupts(vcpu,
8882                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8883                                   VM_ENTRY_INSTRUCTION_LEN,
8884                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8885
8886         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8887 }
8888
8889 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8890 {
8891         int i, nr_msrs;
8892         struct perf_guest_switch_msr *msrs;
8893
8894         msrs = perf_guest_get_msrs(&nr_msrs);
8895
8896         if (!msrs)
8897                 return;
8898
8899         for (i = 0; i < nr_msrs; i++)
8900                 if (msrs[i].host == msrs[i].guest)
8901                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8902                 else
8903                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8904                                         msrs[i].host);
8905 }
8906
8907 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8908 {
8909         struct vcpu_vmx *vmx = to_vmx(vcpu);
8910         u64 tscl;
8911         u32 delta_tsc;
8912
8913         if (vmx->hv_deadline_tsc == -1)
8914                 return;
8915
8916         tscl = rdtsc();
8917         if (vmx->hv_deadline_tsc > tscl)
8918                 /* sure to be 32 bit only because checked on set_hv_timer */
8919                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8920                         cpu_preemption_timer_multi);
8921         else
8922                 delta_tsc = 0;
8923
8924         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8925 }
8926
8927 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8928 {
8929         struct vcpu_vmx *vmx = to_vmx(vcpu);
8930         unsigned long debugctlmsr, cr4;
8931
8932         /* Record the guest's net vcpu time for enforced NMI injections. */
8933         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8934                 vmx->entry_time = ktime_get();
8935
8936         /* Don't enter VMX if guest state is invalid, let the exit handler
8937            start emulation until we arrive back to a valid state */
8938         if (vmx->emulation_required)
8939                 return;
8940
8941         if (vmx->ple_window_dirty) {
8942                 vmx->ple_window_dirty = false;
8943                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8944         }
8945
8946         if (vmx->nested.sync_shadow_vmcs) {
8947                 copy_vmcs12_to_shadow(vmx);
8948                 vmx->nested.sync_shadow_vmcs = false;
8949         }
8950
8951         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8952                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8953         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8954                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8955
8956         cr4 = cr4_read_shadow();
8957         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8958                 vmcs_writel(HOST_CR4, cr4);
8959                 vmx->host_state.vmcs_host_cr4 = cr4;
8960         }
8961
8962         /* When single-stepping over STI and MOV SS, we must clear the
8963          * corresponding interruptibility bits in the guest state. Otherwise
8964          * vmentry fails as it then expects bit 14 (BS) in pending debug
8965          * exceptions being set, but that's not correct for the guest debugging
8966          * case. */
8967         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8968                 vmx_set_interrupt_shadow(vcpu, 0);
8969
8970         if (vmx->guest_pkru_valid)
8971                 __write_pkru(vmx->guest_pkru);
8972
8973         atomic_switch_perf_msrs(vmx);
8974         debugctlmsr = get_debugctlmsr();
8975
8976         vmx_arm_hv_timer(vcpu);
8977
8978         vmx->__launched = vmx->loaded_vmcs->launched;
8979         asm(
8980                 /* Store host registers */
8981                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8982                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8983                 "push %%" _ASM_CX " \n\t"
8984                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8985                 "je 1f \n\t"
8986                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8987                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8988                 "1: \n\t"
8989                 /* Reload cr2 if changed */
8990                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8991                 "mov %%cr2, %%" _ASM_DX " \n\t"
8992                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8993                 "je 2f \n\t"
8994                 "mov %%" _ASM_AX", %%cr2 \n\t"
8995                 "2: \n\t"
8996                 /* Check if vmlaunch of vmresume is needed */
8997                 "cmpl $0, %c[launched](%0) \n\t"
8998                 /* Load guest registers.  Don't clobber flags. */
8999                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9000                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9001                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9002                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9003                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9004                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9005 #ifdef CONFIG_X86_64
9006                 "mov %c[r8](%0),  %%r8  \n\t"
9007                 "mov %c[r9](%0),  %%r9  \n\t"
9008                 "mov %c[r10](%0), %%r10 \n\t"
9009                 "mov %c[r11](%0), %%r11 \n\t"
9010                 "mov %c[r12](%0), %%r12 \n\t"
9011                 "mov %c[r13](%0), %%r13 \n\t"
9012                 "mov %c[r14](%0), %%r14 \n\t"
9013                 "mov %c[r15](%0), %%r15 \n\t"
9014 #endif
9015                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9016
9017                 /* Enter guest mode */
9018                 "jne 1f \n\t"
9019                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9020                 "jmp 2f \n\t"
9021                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9022                 "2: "
9023                 /* Save guest registers, load host registers, keep flags */
9024                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9025                 "pop %0 \n\t"
9026                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9027                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9028                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9029                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9030                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9031                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9032                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9033 #ifdef CONFIG_X86_64
9034                 "mov %%r8,  %c[r8](%0) \n\t"
9035                 "mov %%r9,  %c[r9](%0) \n\t"
9036                 "mov %%r10, %c[r10](%0) \n\t"
9037                 "mov %%r11, %c[r11](%0) \n\t"
9038                 "mov %%r12, %c[r12](%0) \n\t"
9039                 "mov %%r13, %c[r13](%0) \n\t"
9040                 "mov %%r14, %c[r14](%0) \n\t"
9041                 "mov %%r15, %c[r15](%0) \n\t"
9042 #endif
9043                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9044                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9045
9046                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9047                 "setbe %c[fail](%0) \n\t"
9048                 ".pushsection .rodata \n\t"
9049                 ".global vmx_return \n\t"
9050                 "vmx_return: " _ASM_PTR " 2b \n\t"
9051                 ".popsection"
9052               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9053                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9054                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9055                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9056                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9057                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9058                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9059                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9060                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9061                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9062                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9063 #ifdef CONFIG_X86_64
9064                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9065                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9066                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9067                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9068                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9069                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9070                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9071                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9072 #endif
9073                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9074                 [wordsize]"i"(sizeof(ulong))
9075               : "cc", "memory"
9076 #ifdef CONFIG_X86_64
9077                 , "rax", "rbx", "rdi", "rsi"
9078                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9079 #else
9080                 , "eax", "ebx", "edi", "esi"
9081 #endif
9082               );
9083
9084         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9085         if (debugctlmsr)
9086                 update_debugctlmsr(debugctlmsr);
9087
9088 #ifndef CONFIG_X86_64
9089         /*
9090          * The sysexit path does not restore ds/es, so we must set them to
9091          * a reasonable value ourselves.
9092          *
9093          * We can't defer this to vmx_load_host_state() since that function
9094          * may be executed in interrupt context, which saves and restore segments
9095          * around it, nullifying its effect.
9096          */
9097         loadsegment(ds, __USER_DS);
9098         loadsegment(es, __USER_DS);
9099 #endif
9100
9101         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9102                                   | (1 << VCPU_EXREG_RFLAGS)
9103                                   | (1 << VCPU_EXREG_PDPTR)
9104                                   | (1 << VCPU_EXREG_SEGMENTS)
9105                                   | (1 << VCPU_EXREG_CR3));
9106         vcpu->arch.regs_dirty = 0;
9107
9108         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9109
9110         vmx->loaded_vmcs->launched = 1;
9111
9112         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9113
9114         /*
9115          * eager fpu is enabled if PKEY is supported and CR4 is switched
9116          * back on host, so it is safe to read guest PKRU from current
9117          * XSAVE.
9118          */
9119         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9120                 vmx->guest_pkru = __read_pkru();
9121                 if (vmx->guest_pkru != vmx->host_pkru) {
9122                         vmx->guest_pkru_valid = true;
9123                         __write_pkru(vmx->host_pkru);
9124                 } else
9125                         vmx->guest_pkru_valid = false;
9126         }
9127
9128         /*
9129          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9130          * we did not inject a still-pending event to L1 now because of
9131          * nested_run_pending, we need to re-enable this bit.
9132          */
9133         if (vmx->nested.nested_run_pending)
9134                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9135
9136         vmx->nested.nested_run_pending = 0;
9137
9138         vmx_complete_atomic_exit(vmx);
9139         vmx_recover_nmi_blocking(vmx);
9140         vmx_complete_interrupts(vmx);
9141 }
9142
9143 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9144 {
9145         struct vcpu_vmx *vmx = to_vmx(vcpu);
9146         int cpu;
9147
9148         if (vmx->loaded_vmcs == &vmx->vmcs01)
9149                 return;
9150
9151         cpu = get_cpu();
9152         vmx->loaded_vmcs = &vmx->vmcs01;
9153         vmx_vcpu_put(vcpu);
9154         vmx_vcpu_load(vcpu, cpu);
9155         vcpu->cpu = cpu;
9156         put_cpu();
9157 }
9158
9159 /*
9160  * Ensure that the current vmcs of the logical processor is the
9161  * vmcs01 of the vcpu before calling free_nested().
9162  */
9163 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9164 {
9165        struct vcpu_vmx *vmx = to_vmx(vcpu);
9166        int r;
9167
9168        r = vcpu_load(vcpu);
9169        BUG_ON(r);
9170        vmx_load_vmcs01(vcpu);
9171        free_nested(vmx);
9172        vcpu_put(vcpu);
9173 }
9174
9175 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9176 {
9177         struct vcpu_vmx *vmx = to_vmx(vcpu);
9178
9179         if (enable_pml)
9180                 vmx_destroy_pml_buffer(vmx);
9181         free_vpid(vmx->vpid);
9182         leave_guest_mode(vcpu);
9183         vmx_free_vcpu_nested(vcpu);
9184         free_loaded_vmcs(vmx->loaded_vmcs);
9185         kfree(vmx->guest_msrs);
9186         kvm_vcpu_uninit(vcpu);
9187         kmem_cache_free(kvm_vcpu_cache, vmx);
9188 }
9189
9190 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9191 {
9192         int err;
9193         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9194         int cpu;
9195
9196         if (!vmx)
9197                 return ERR_PTR(-ENOMEM);
9198
9199         vmx->vpid = allocate_vpid();
9200
9201         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9202         if (err)
9203                 goto free_vcpu;
9204
9205         err = -ENOMEM;
9206
9207         /*
9208          * If PML is turned on, failure on enabling PML just results in failure
9209          * of creating the vcpu, therefore we can simplify PML logic (by
9210          * avoiding dealing with cases, such as enabling PML partially on vcpus
9211          * for the guest, etc.
9212          */
9213         if (enable_pml) {
9214                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9215                 if (!vmx->pml_pg)
9216                         goto uninit_vcpu;
9217         }
9218
9219         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9220         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9221                      > PAGE_SIZE);
9222
9223         if (!vmx->guest_msrs)
9224                 goto free_pml;
9225
9226         vmx->loaded_vmcs = &vmx->vmcs01;
9227         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9228         vmx->loaded_vmcs->shadow_vmcs = NULL;
9229         if (!vmx->loaded_vmcs->vmcs)
9230                 goto free_msrs;
9231         if (!vmm_exclusive)
9232                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9233         loaded_vmcs_init(vmx->loaded_vmcs);
9234         if (!vmm_exclusive)
9235                 kvm_cpu_vmxoff();
9236
9237         cpu = get_cpu();
9238         vmx_vcpu_load(&vmx->vcpu, cpu);
9239         vmx->vcpu.cpu = cpu;
9240         err = vmx_vcpu_setup(vmx);
9241         vmx_vcpu_put(&vmx->vcpu);
9242         put_cpu();
9243         if (err)
9244                 goto free_vmcs;
9245         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9246                 err = alloc_apic_access_page(kvm);
9247                 if (err)
9248                         goto free_vmcs;
9249         }
9250
9251         if (enable_ept) {
9252                 if (!kvm->arch.ept_identity_map_addr)
9253                         kvm->arch.ept_identity_map_addr =
9254                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9255                 err = init_rmode_identity_map(kvm);
9256                 if (err)
9257                         goto free_vmcs;
9258         }
9259
9260         if (nested) {
9261                 nested_vmx_setup_ctls_msrs(vmx);
9262                 vmx->nested.vpid02 = allocate_vpid();
9263         }
9264
9265         vmx->nested.posted_intr_nv = -1;
9266         vmx->nested.current_vmptr = -1ull;
9267         vmx->nested.current_vmcs12 = NULL;
9268
9269         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9270
9271         return &vmx->vcpu;
9272
9273 free_vmcs:
9274         free_vpid(vmx->nested.vpid02);
9275         free_loaded_vmcs(vmx->loaded_vmcs);
9276 free_msrs:
9277         kfree(vmx->guest_msrs);
9278 free_pml:
9279         vmx_destroy_pml_buffer(vmx);
9280 uninit_vcpu:
9281         kvm_vcpu_uninit(&vmx->vcpu);
9282 free_vcpu:
9283         free_vpid(vmx->vpid);
9284         kmem_cache_free(kvm_vcpu_cache, vmx);
9285         return ERR_PTR(err);
9286 }
9287
9288 static void __init vmx_check_processor_compat(void *rtn)
9289 {
9290         struct vmcs_config vmcs_conf;
9291
9292         *(int *)rtn = 0;
9293         if (setup_vmcs_config(&vmcs_conf) < 0)
9294                 *(int *)rtn = -EIO;
9295         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9296                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9297                                 smp_processor_id());
9298                 *(int *)rtn = -EIO;
9299         }
9300 }
9301
9302 static int get_ept_level(void)
9303 {
9304         return VMX_EPT_DEFAULT_GAW + 1;
9305 }
9306
9307 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9308 {
9309         u8 cache;
9310         u64 ipat = 0;
9311
9312         /* For VT-d and EPT combination
9313          * 1. MMIO: always map as UC
9314          * 2. EPT with VT-d:
9315          *   a. VT-d without snooping control feature: can't guarantee the
9316          *      result, try to trust guest.
9317          *   b. VT-d with snooping control feature: snooping control feature of
9318          *      VT-d engine can guarantee the cache correctness. Just set it
9319          *      to WB to keep consistent with host. So the same as item 3.
9320          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9321          *    consistent with host MTRR
9322          */
9323         if (is_mmio) {
9324                 cache = MTRR_TYPE_UNCACHABLE;
9325                 goto exit;
9326         }
9327
9328         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9329                 ipat = VMX_EPT_IPAT_BIT;
9330                 cache = MTRR_TYPE_WRBACK;
9331                 goto exit;
9332         }
9333
9334         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9335                 ipat = VMX_EPT_IPAT_BIT;
9336                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9337                         cache = MTRR_TYPE_WRBACK;
9338                 else
9339                         cache = MTRR_TYPE_UNCACHABLE;
9340                 goto exit;
9341         }
9342
9343         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9344
9345 exit:
9346         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9347 }
9348
9349 static int vmx_get_lpage_level(void)
9350 {
9351         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9352                 return PT_DIRECTORY_LEVEL;
9353         else
9354                 /* For shadow and EPT supported 1GB page */
9355                 return PT_PDPE_LEVEL;
9356 }
9357
9358 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9359 {
9360         /*
9361          * These bits in the secondary execution controls field
9362          * are dynamic, the others are mostly based on the hypervisor
9363          * architecture and the guest's CPUID.  Do not touch the
9364          * dynamic bits.
9365          */
9366         u32 mask =
9367                 SECONDARY_EXEC_SHADOW_VMCS |
9368                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9369                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9370
9371         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9372
9373         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9374                      (new_ctl & ~mask) | (cur_ctl & mask));
9375 }
9376
9377 /*
9378  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9379  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9380  */
9381 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9382 {
9383         struct vcpu_vmx *vmx = to_vmx(vcpu);
9384         struct kvm_cpuid_entry2 *entry;
9385
9386         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9387         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9388
9389 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9390         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9391                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9392 } while (0)
9393
9394         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9395         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9396         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9397         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9398         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9399         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9400         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9401         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9402         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9403         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9404         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9405         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9406         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9407         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9408         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9409
9410         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9411         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9412         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9413         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9414         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9415         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9416         cr4_fixed1_update(bit(11),            ecx, bit(2));
9417
9418 #undef cr4_fixed1_update
9419 }
9420
9421 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9422 {
9423         struct kvm_cpuid_entry2 *best;
9424         struct vcpu_vmx *vmx = to_vmx(vcpu);
9425         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9426
9427         if (vmx_rdtscp_supported()) {
9428                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9429                 if (!rdtscp_enabled)
9430                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9431
9432                 if (nested) {
9433                         if (rdtscp_enabled)
9434                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9435                                         SECONDARY_EXEC_RDTSCP;
9436                         else
9437                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9438                                         ~SECONDARY_EXEC_RDTSCP;
9439                 }
9440         }
9441
9442         /* Exposing INVPCID only when PCID is exposed */
9443         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9444         if (vmx_invpcid_supported() &&
9445             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9446             !guest_cpuid_has_pcid(vcpu))) {
9447                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9448
9449                 if (best)
9450                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9451         }
9452
9453         if (cpu_has_secondary_exec_ctrls())
9454                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9455
9456         if (nested_vmx_allowed(vcpu))
9457                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9458                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9459         else
9460                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9461                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9462
9463         if (nested_vmx_allowed(vcpu))
9464                 nested_vmx_cr_fixed1_bits_update(vcpu);
9465 }
9466
9467 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9468 {
9469         if (func == 1 && nested)
9470                 entry->ecx |= bit(X86_FEATURE_VMX);
9471 }
9472
9473 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9474                 struct x86_exception *fault)
9475 {
9476         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9477         u32 exit_reason;
9478
9479         if (fault->error_code & PFERR_RSVD_MASK)
9480                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9481         else
9482                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9483         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9484         vmcs12->guest_physical_address = fault->address;
9485 }
9486
9487 /* Callbacks for nested_ept_init_mmu_context: */
9488
9489 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9490 {
9491         /* return the page table to be shadowed - in our case, EPT12 */
9492         return get_vmcs12(vcpu)->ept_pointer;
9493 }
9494
9495 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9496 {
9497         WARN_ON(mmu_is_nested(vcpu));
9498         kvm_init_shadow_ept_mmu(vcpu,
9499                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9500                         VMX_EPT_EXECUTE_ONLY_BIT);
9501         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9502         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9503         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9504
9505         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9506 }
9507
9508 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9509 {
9510         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9511 }
9512
9513 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9514                                             u16 error_code)
9515 {
9516         bool inequality, bit;
9517
9518         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9519         inequality =
9520                 (error_code & vmcs12->page_fault_error_code_mask) !=
9521                  vmcs12->page_fault_error_code_match;
9522         return inequality ^ bit;
9523 }
9524
9525 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9526                 struct x86_exception *fault)
9527 {
9528         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9529
9530         WARN_ON(!is_guest_mode(vcpu));
9531
9532         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9533                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9534                                   vmcs_read32(VM_EXIT_INTR_INFO),
9535                                   vmcs_readl(EXIT_QUALIFICATION));
9536         else
9537                 kvm_inject_page_fault(vcpu, fault);
9538 }
9539
9540 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9541                                                struct vmcs12 *vmcs12);
9542
9543 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9544                                         struct vmcs12 *vmcs12)
9545 {
9546         struct vcpu_vmx *vmx = to_vmx(vcpu);
9547         u64 hpa;
9548
9549         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9550                 /*
9551                  * Translate L1 physical address to host physical
9552                  * address for vmcs02. Keep the page pinned, so this
9553                  * physical address remains valid. We keep a reference
9554                  * to it so we can release it later.
9555                  */
9556                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9557                         nested_release_page(vmx->nested.apic_access_page);
9558                 vmx->nested.apic_access_page =
9559                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9560                 /*
9561                  * If translation failed, no matter: This feature asks
9562                  * to exit when accessing the given address, and if it
9563                  * can never be accessed, this feature won't do
9564                  * anything anyway.
9565                  */
9566                 if (vmx->nested.apic_access_page) {
9567                         hpa = page_to_phys(vmx->nested.apic_access_page);
9568                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9569                 } else {
9570                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9571                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9572                 }
9573         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9574                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9575                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9576                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9577                 kvm_vcpu_reload_apic_access_page(vcpu);
9578         }
9579
9580         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9581                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9582                         nested_release_page(vmx->nested.virtual_apic_page);
9583                 vmx->nested.virtual_apic_page =
9584                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9585
9586                 /*
9587                  * If translation failed, VM entry will fail because
9588                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9589                  * Failing the vm entry is _not_ what the processor
9590                  * does but it's basically the only possibility we
9591                  * have.  We could still enter the guest if CR8 load
9592                  * exits are enabled, CR8 store exits are enabled, and
9593                  * virtualize APIC access is disabled; in this case
9594                  * the processor would never use the TPR shadow and we
9595                  * could simply clear the bit from the execution
9596                  * control.  But such a configuration is useless, so
9597                  * let's keep the code simple.
9598                  */
9599                 if (vmx->nested.virtual_apic_page) {
9600                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9601                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9602                 }
9603         }
9604
9605         if (nested_cpu_has_posted_intr(vmcs12)) {
9606                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9607                         kunmap(vmx->nested.pi_desc_page);
9608                         nested_release_page(vmx->nested.pi_desc_page);
9609                 }
9610                 vmx->nested.pi_desc_page =
9611                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9612                 vmx->nested.pi_desc =
9613                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9614                 if (!vmx->nested.pi_desc) {
9615                         nested_release_page_clean(vmx->nested.pi_desc_page);
9616                         return;
9617                 }
9618                 vmx->nested.pi_desc =
9619                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9620                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9621                         (PAGE_SIZE - 1)));
9622                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9623                         page_to_phys(vmx->nested.pi_desc_page) +
9624                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9625                         (PAGE_SIZE - 1)));
9626         }
9627         if (cpu_has_vmx_msr_bitmap() &&
9628             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9629             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9630                 ;
9631         else
9632                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9633                                 CPU_BASED_USE_MSR_BITMAPS);
9634 }
9635
9636 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9637 {
9638         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9639         struct vcpu_vmx *vmx = to_vmx(vcpu);
9640
9641         if (vcpu->arch.virtual_tsc_khz == 0)
9642                 return;
9643
9644         /* Make sure short timeouts reliably trigger an immediate vmexit.
9645          * hrtimer_start does not guarantee this. */
9646         if (preemption_timeout <= 1) {
9647                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9648                 return;
9649         }
9650
9651         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9652         preemption_timeout *= 1000000;
9653         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9654         hrtimer_start(&vmx->nested.preemption_timer,
9655                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9656 }
9657
9658 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9659                                                 struct vmcs12 *vmcs12)
9660 {
9661         int maxphyaddr;
9662         u64 addr;
9663
9664         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9665                 return 0;
9666
9667         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9668                 WARN_ON(1);
9669                 return -EINVAL;
9670         }
9671         maxphyaddr = cpuid_maxphyaddr(vcpu);
9672
9673         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9674            ((addr + PAGE_SIZE) >> maxphyaddr))
9675                 return -EINVAL;
9676
9677         return 0;
9678 }
9679
9680 /*
9681  * Merge L0's and L1's MSR bitmap, return false to indicate that
9682  * we do not use the hardware.
9683  */
9684 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9685                                                struct vmcs12 *vmcs12)
9686 {
9687         int msr;
9688         struct page *page;
9689         unsigned long *msr_bitmap_l1;
9690         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9691
9692         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9693         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9694                 return false;
9695
9696         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9697         if (!page) {
9698                 WARN_ON(1);
9699                 return false;
9700         }
9701         msr_bitmap_l1 = (unsigned long *)kmap(page);
9702
9703         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9704
9705         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9706                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9707                         for (msr = 0x800; msr <= 0x8ff; msr++)
9708                                 nested_vmx_disable_intercept_for_msr(
9709                                         msr_bitmap_l1, msr_bitmap_l0,
9710                                         msr, MSR_TYPE_R);
9711
9712                 nested_vmx_disable_intercept_for_msr(
9713                                 msr_bitmap_l1, msr_bitmap_l0,
9714                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9715                                 MSR_TYPE_R | MSR_TYPE_W);
9716
9717                 if (nested_cpu_has_vid(vmcs12)) {
9718                         nested_vmx_disable_intercept_for_msr(
9719                                 msr_bitmap_l1, msr_bitmap_l0,
9720                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9721                                 MSR_TYPE_W);
9722                         nested_vmx_disable_intercept_for_msr(
9723                                 msr_bitmap_l1, msr_bitmap_l0,
9724                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9725                                 MSR_TYPE_W);
9726                 }
9727         }
9728         kunmap(page);
9729         nested_release_page_clean(page);
9730
9731         return true;
9732 }
9733
9734 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9735                                            struct vmcs12 *vmcs12)
9736 {
9737         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9738             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9739             !nested_cpu_has_vid(vmcs12) &&
9740             !nested_cpu_has_posted_intr(vmcs12))
9741                 return 0;
9742
9743         /*
9744          * If virtualize x2apic mode is enabled,
9745          * virtualize apic access must be disabled.
9746          */
9747         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9748             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9749                 return -EINVAL;
9750
9751         /*
9752          * If virtual interrupt delivery is enabled,
9753          * we must exit on external interrupts.
9754          */
9755         if (nested_cpu_has_vid(vmcs12) &&
9756            !nested_exit_on_intr(vcpu))
9757                 return -EINVAL;
9758
9759         /*
9760          * bits 15:8 should be zero in posted_intr_nv,
9761          * the descriptor address has been already checked
9762          * in nested_get_vmcs12_pages.
9763          */
9764         if (nested_cpu_has_posted_intr(vmcs12) &&
9765            (!nested_cpu_has_vid(vmcs12) ||
9766             !nested_exit_intr_ack_set(vcpu) ||
9767             vmcs12->posted_intr_nv & 0xff00))
9768                 return -EINVAL;
9769
9770         /* tpr shadow is needed by all apicv features. */
9771         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9772                 return -EINVAL;
9773
9774         return 0;
9775 }
9776
9777 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9778                                        unsigned long count_field,
9779                                        unsigned long addr_field)
9780 {
9781         int maxphyaddr;
9782         u64 count, addr;
9783
9784         if (vmcs12_read_any(vcpu, count_field, &count) ||
9785             vmcs12_read_any(vcpu, addr_field, &addr)) {
9786                 WARN_ON(1);
9787                 return -EINVAL;
9788         }
9789         if (count == 0)
9790                 return 0;
9791         maxphyaddr = cpuid_maxphyaddr(vcpu);
9792         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9793             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9794                 pr_debug_ratelimited(
9795                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9796                         addr_field, maxphyaddr, count, addr);
9797                 return -EINVAL;
9798         }
9799         return 0;
9800 }
9801
9802 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9803                                                 struct vmcs12 *vmcs12)
9804 {
9805         if (vmcs12->vm_exit_msr_load_count == 0 &&
9806             vmcs12->vm_exit_msr_store_count == 0 &&
9807             vmcs12->vm_entry_msr_load_count == 0)
9808                 return 0; /* Fast path */
9809         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9810                                         VM_EXIT_MSR_LOAD_ADDR) ||
9811             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9812                                         VM_EXIT_MSR_STORE_ADDR) ||
9813             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9814                                         VM_ENTRY_MSR_LOAD_ADDR))
9815                 return -EINVAL;
9816         return 0;
9817 }
9818
9819 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9820                                        struct vmx_msr_entry *e)
9821 {
9822         /* x2APIC MSR accesses are not allowed */
9823         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9824                 return -EINVAL;
9825         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9826             e->index == MSR_IA32_UCODE_REV)
9827                 return -EINVAL;
9828         if (e->reserved != 0)
9829                 return -EINVAL;
9830         return 0;
9831 }
9832
9833 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9834                                      struct vmx_msr_entry *e)
9835 {
9836         if (e->index == MSR_FS_BASE ||
9837             e->index == MSR_GS_BASE ||
9838             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9839             nested_vmx_msr_check_common(vcpu, e))
9840                 return -EINVAL;
9841         return 0;
9842 }
9843
9844 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9845                                       struct vmx_msr_entry *e)
9846 {
9847         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9848             nested_vmx_msr_check_common(vcpu, e))
9849                 return -EINVAL;
9850         return 0;
9851 }
9852
9853 /*
9854  * Load guest's/host's msr at nested entry/exit.
9855  * return 0 for success, entry index for failure.
9856  */
9857 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9858 {
9859         u32 i;
9860         struct vmx_msr_entry e;
9861         struct msr_data msr;
9862
9863         msr.host_initiated = false;
9864         for (i = 0; i < count; i++) {
9865                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9866                                         &e, sizeof(e))) {
9867                         pr_debug_ratelimited(
9868                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9869                                 __func__, i, gpa + i * sizeof(e));
9870                         goto fail;
9871                 }
9872                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9873                         pr_debug_ratelimited(
9874                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9875                                 __func__, i, e.index, e.reserved);
9876                         goto fail;
9877                 }
9878                 msr.index = e.index;
9879                 msr.data = e.value;
9880                 if (kvm_set_msr(vcpu, &msr)) {
9881                         pr_debug_ratelimited(
9882                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9883                                 __func__, i, e.index, e.value);
9884                         goto fail;
9885                 }
9886         }
9887         return 0;
9888 fail:
9889         return i + 1;
9890 }
9891
9892 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9893 {
9894         u32 i;
9895         struct vmx_msr_entry e;
9896
9897         for (i = 0; i < count; i++) {
9898                 struct msr_data msr_info;
9899                 if (kvm_vcpu_read_guest(vcpu,
9900                                         gpa + i * sizeof(e),
9901                                         &e, 2 * sizeof(u32))) {
9902                         pr_debug_ratelimited(
9903                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9904                                 __func__, i, gpa + i * sizeof(e));
9905                         return -EINVAL;
9906                 }
9907                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9908                         pr_debug_ratelimited(
9909                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9910                                 __func__, i, e.index, e.reserved);
9911                         return -EINVAL;
9912                 }
9913                 msr_info.host_initiated = false;
9914                 msr_info.index = e.index;
9915                 if (kvm_get_msr(vcpu, &msr_info)) {
9916                         pr_debug_ratelimited(
9917                                 "%s cannot read MSR (%u, 0x%x)\n",
9918                                 __func__, i, e.index);
9919                         return -EINVAL;
9920                 }
9921                 if (kvm_vcpu_write_guest(vcpu,
9922                                          gpa + i * sizeof(e) +
9923                                              offsetof(struct vmx_msr_entry, value),
9924                                          &msr_info.data, sizeof(msr_info.data))) {
9925                         pr_debug_ratelimited(
9926                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9927                                 __func__, i, e.index, msr_info.data);
9928                         return -EINVAL;
9929                 }
9930         }
9931         return 0;
9932 }
9933
9934 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9935 {
9936         unsigned long invalid_mask;
9937
9938         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9939         return (val & invalid_mask) == 0;
9940 }
9941
9942 /*
9943  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9944  * emulating VM entry into a guest with EPT enabled.
9945  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9946  * is assigned to entry_failure_code on failure.
9947  */
9948 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9949                                u32 *entry_failure_code)
9950 {
9951         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9952                 if (!nested_cr3_valid(vcpu, cr3)) {
9953                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9954                         return 1;
9955                 }
9956
9957                 /*
9958                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9959                  * must not be dereferenced.
9960                  */
9961                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9962                     !nested_ept) {
9963                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9964                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9965                                 return 1;
9966                         }
9967                 }
9968
9969                 vcpu->arch.cr3 = cr3;
9970                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9971         }
9972
9973         kvm_mmu_reset_context(vcpu);
9974         return 0;
9975 }
9976
9977 /*
9978  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9979  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9980  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9981  * guest in a way that will both be appropriate to L1's requests, and our
9982  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9983  * function also has additional necessary side-effects, like setting various
9984  * vcpu->arch fields.
9985  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9986  * is assigned to entry_failure_code on failure.
9987  */
9988 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9989                           bool from_vmentry, u32 *entry_failure_code)
9990 {
9991         struct vcpu_vmx *vmx = to_vmx(vcpu);
9992         u32 exec_control;
9993         bool nested_ept_enabled = false;
9994
9995         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9996         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9997         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9998         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9999         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10000         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10001         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10002         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10003         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10004         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10005         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10006         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10007         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10008         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10009         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10010         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10011         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10012         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10013         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10014         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10015         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10016         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10017         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10018         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10019         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10020         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10021         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10022         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10023         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10024         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10025         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10026         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10027         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10028         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10029         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10030         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10031
10032         if (from_vmentry &&
10033             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10034                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10035                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10036         } else {
10037                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10038                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10039         }
10040         if (from_vmentry) {
10041                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10042                              vmcs12->vm_entry_intr_info_field);
10043                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10044                              vmcs12->vm_entry_exception_error_code);
10045                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10046                              vmcs12->vm_entry_instruction_len);
10047                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10048                              vmcs12->guest_interruptibility_info);
10049         } else {
10050                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10051         }
10052         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10053         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10054         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10055                 vmcs12->guest_pending_dbg_exceptions);
10056         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10057         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10058
10059         if (nested_cpu_has_xsaves(vmcs12))
10060                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10061         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10062
10063         exec_control = vmcs12->pin_based_vm_exec_control;
10064
10065         /* Preemption timer setting is only taken from vmcs01.  */
10066         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10067         exec_control |= vmcs_config.pin_based_exec_ctrl;
10068         if (vmx->hv_deadline_tsc == -1)
10069                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10070
10071         /* Posted interrupts setting is only taken from vmcs12.  */
10072         if (nested_cpu_has_posted_intr(vmcs12)) {
10073                 /*
10074                  * Note that we use L0's vector here and in
10075                  * vmx_deliver_nested_posted_interrupt.
10076                  */
10077                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10078                 vmx->nested.pi_pending = false;
10079                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10080         } else {
10081                 exec_control &= ~PIN_BASED_POSTED_INTR;
10082         }
10083
10084         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10085
10086         vmx->nested.preemption_timer_expired = false;
10087         if (nested_cpu_has_preemption_timer(vmcs12))
10088                 vmx_start_preemption_timer(vcpu);
10089
10090         /*
10091          * Whether page-faults are trapped is determined by a combination of
10092          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10093          * If enable_ept, L0 doesn't care about page faults and we should
10094          * set all of these to L1's desires. However, if !enable_ept, L0 does
10095          * care about (at least some) page faults, and because it is not easy
10096          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10097          * to exit on each and every L2 page fault. This is done by setting
10098          * MASK=MATCH=0 and (see below) EB.PF=1.
10099          * Note that below we don't need special code to set EB.PF beyond the
10100          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10101          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10102          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10103          *
10104          * A problem with this approach (when !enable_ept) is that L1 may be
10105          * injected with more page faults than it asked for. This could have
10106          * caused problems, but in practice existing hypervisors don't care.
10107          * To fix this, we will need to emulate the PFEC checking (on the L1
10108          * page tables), using walk_addr(), when injecting PFs to L1.
10109          */
10110         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10111                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10112         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10113                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10114
10115         if (cpu_has_secondary_exec_ctrls()) {
10116                 exec_control = vmx_secondary_exec_control(vmx);
10117
10118                 /* Take the following fields only from vmcs12 */
10119                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10120                                   SECONDARY_EXEC_RDTSCP |
10121                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10122                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10123                 if (nested_cpu_has(vmcs12,
10124                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10125                         exec_control |= vmcs12->secondary_vm_exec_control;
10126
10127                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10128                         vmcs_write64(EOI_EXIT_BITMAP0,
10129                                 vmcs12->eoi_exit_bitmap0);
10130                         vmcs_write64(EOI_EXIT_BITMAP1,
10131                                 vmcs12->eoi_exit_bitmap1);
10132                         vmcs_write64(EOI_EXIT_BITMAP2,
10133                                 vmcs12->eoi_exit_bitmap2);
10134                         vmcs_write64(EOI_EXIT_BITMAP3,
10135                                 vmcs12->eoi_exit_bitmap3);
10136                         vmcs_write16(GUEST_INTR_STATUS,
10137                                 vmcs12->guest_intr_status);
10138                 }
10139
10140                 nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0;
10141
10142                 /*
10143                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10144                  * nested_get_vmcs12_pages will either fix it up or
10145                  * remove the VM execution control.
10146                  */
10147                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10148                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10149
10150                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10151         }
10152
10153
10154         /*
10155          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10156          * Some constant fields are set here by vmx_set_constant_host_state().
10157          * Other fields are different per CPU, and will be set later when
10158          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10159          */
10160         vmx_set_constant_host_state(vmx);
10161
10162         /*
10163          * Set the MSR load/store lists to match L0's settings.
10164          */
10165         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10166         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10167         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10168         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10169         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10170
10171         /*
10172          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10173          * entry, but only if the current (host) sp changed from the value
10174          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10175          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10176          * here we just force the write to happen on entry.
10177          */
10178         vmx->host_rsp = 0;
10179
10180         exec_control = vmx_exec_control(vmx); /* L0's desires */
10181         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10182         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10183         exec_control &= ~CPU_BASED_TPR_SHADOW;
10184         exec_control |= vmcs12->cpu_based_vm_exec_control;
10185
10186         /*
10187          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10188          * nested_get_vmcs12_pages can't fix it up, the illegal value
10189          * will result in a VM entry failure.
10190          */
10191         if (exec_control & CPU_BASED_TPR_SHADOW) {
10192                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10193                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10194         }
10195
10196         /*
10197          * Merging of IO bitmap not currently supported.
10198          * Rather, exit every time.
10199          */
10200         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10201         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10202
10203         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10204
10205         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10206          * bitwise-or of what L1 wants to trap for L2, and what we want to
10207          * trap. Note that CR0.TS also needs updating - we do this later.
10208          */
10209         update_exception_bitmap(vcpu);
10210         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10211         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10212
10213         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10214          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10215          * bits are further modified by vmx_set_efer() below.
10216          */
10217         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10218
10219         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10220          * emulated by vmx_set_efer(), below.
10221          */
10222         vm_entry_controls_init(vmx,
10223                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10224                         ~VM_ENTRY_IA32E_MODE) |
10225                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10226
10227         if (from_vmentry &&
10228             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10229                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10230                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10231         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10232                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10233         }
10234
10235         set_cr4_guest_host_mask(vmx);
10236
10237         if (from_vmentry &&
10238             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10239                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10240
10241         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10242                 vmcs_write64(TSC_OFFSET,
10243                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10244         else
10245                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10246         if (kvm_has_tsc_control)
10247                 decache_tsc_multiplier(vmx);
10248
10249         if (enable_vpid) {
10250                 /*
10251                  * There is no direct mapping between vpid02 and vpid12, the
10252                  * vpid02 is per-vCPU for L0 and reused while the value of
10253                  * vpid12 is changed w/ one invvpid during nested vmentry.
10254                  * The vpid12 is allocated by L1 for L2, so it will not
10255                  * influence global bitmap(for vpid01 and vpid02 allocation)
10256                  * even if spawn a lot of nested vCPUs.
10257                  */
10258                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10259                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10260                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10261                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10262                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10263                         }
10264                 } else {
10265                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10266                         vmx_flush_tlb(vcpu);
10267                 }
10268
10269         }
10270
10271         if (nested_cpu_has_ept(vmcs12)) {
10272                 kvm_mmu_unload(vcpu);
10273                 nested_ept_init_mmu_context(vcpu);
10274         }
10275
10276         /*
10277          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10278          * bits which we consider mandatory enabled.
10279          * The CR0_READ_SHADOW is what L2 should have expected to read given
10280          * the specifications by L1; It's not enough to take
10281          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10282          * have more bits than L1 expected.
10283          */
10284         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10285         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10286
10287         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10288         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10289
10290         if (from_vmentry &&
10291             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10292                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10293         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10294                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10295         else
10296                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10297         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10298         vmx_set_efer(vcpu, vcpu->arch.efer);
10299
10300         /* Shadow page tables on either EPT or shadow page tables. */
10301         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled,
10302                                 entry_failure_code))
10303                 return 1;
10304
10305         kvm_mmu_reset_context(vcpu);
10306
10307         if (!enable_ept)
10308                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10309
10310         /*
10311          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10312          */
10313         if (enable_ept) {
10314                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10315                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10316                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10317                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10318         }
10319
10320         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10321         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10322         return 0;
10323 }
10324
10325 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10326 {
10327         struct vcpu_vmx *vmx = to_vmx(vcpu);
10328
10329         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10330             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10331                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10332
10333         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10334                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10335
10336         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10337                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10338
10339         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10340                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10341
10342         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10343                                 vmx->nested.nested_vmx_procbased_ctls_low,
10344                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10345             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10346                                 vmx->nested.nested_vmx_secondary_ctls_low,
10347                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10348             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10349                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10350                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10351             !vmx_control_verify(vmcs12->vm_exit_controls,
10352                                 vmx->nested.nested_vmx_exit_ctls_low,
10353                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10354             !vmx_control_verify(vmcs12->vm_entry_controls,
10355                                 vmx->nested.nested_vmx_entry_ctls_low,
10356                                 vmx->nested.nested_vmx_entry_ctls_high))
10357                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10358
10359         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10360             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10361             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10362                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10363
10364         return 0;
10365 }
10366
10367 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10368                                   u32 *exit_qual)
10369 {
10370         bool ia32e;
10371
10372         *exit_qual = ENTRY_FAIL_DEFAULT;
10373
10374         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10375             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10376                 return 1;
10377
10378         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10379             vmcs12->vmcs_link_pointer != -1ull) {
10380                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10381                 return 1;
10382         }
10383
10384         /*
10385          * If the load IA32_EFER VM-entry control is 1, the following checks
10386          * are performed on the field for the IA32_EFER MSR:
10387          * - Bits reserved in the IA32_EFER MSR must be 0.
10388          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10389          *   the IA-32e mode guest VM-exit control. It must also be identical
10390          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10391          *   CR0.PG) is 1.
10392          */
10393         if (to_vmx(vcpu)->nested.nested_run_pending &&
10394             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10395                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10396                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10397                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10398                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10399                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10400                         return 1;
10401         }
10402
10403         /*
10404          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10405          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10406          * the values of the LMA and LME bits in the field must each be that of
10407          * the host address-space size VM-exit control.
10408          */
10409         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10410                 ia32e = (vmcs12->vm_exit_controls &
10411                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10412                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10413                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10414                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10415                         return 1;
10416         }
10417
10418         return 0;
10419 }
10420
10421 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10422 {
10423         struct vcpu_vmx *vmx = to_vmx(vcpu);
10424         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10425         struct loaded_vmcs *vmcs02;
10426         int cpu;
10427         u32 msr_entry_idx;
10428         u32 exit_qual;
10429
10430         vmcs02 = nested_get_current_vmcs02(vmx);
10431         if (!vmcs02)
10432                 return -ENOMEM;
10433
10434         enter_guest_mode(vcpu);
10435
10436         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10437                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10438
10439         cpu = get_cpu();
10440         vmx->loaded_vmcs = vmcs02;
10441         vmx_vcpu_put(vcpu);
10442         vmx_vcpu_load(vcpu, cpu);
10443         vcpu->cpu = cpu;
10444         put_cpu();
10445
10446         vmx_segment_cache_clear(vmx);
10447
10448         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10449                 leave_guest_mode(vcpu);
10450                 vmx_load_vmcs01(vcpu);
10451                 nested_vmx_entry_failure(vcpu, vmcs12,
10452                                          EXIT_REASON_INVALID_STATE, exit_qual);
10453                 return 1;
10454         }
10455
10456         nested_get_vmcs12_pages(vcpu, vmcs12);
10457
10458         msr_entry_idx = nested_vmx_load_msr(vcpu,
10459                                             vmcs12->vm_entry_msr_load_addr,
10460                                             vmcs12->vm_entry_msr_load_count);
10461         if (msr_entry_idx) {
10462                 leave_guest_mode(vcpu);
10463                 vmx_load_vmcs01(vcpu);
10464                 nested_vmx_entry_failure(vcpu, vmcs12,
10465                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10466                 return 1;
10467         }
10468
10469         vmcs12->launch_state = 1;
10470
10471         /*
10472          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10473          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10474          * returned as far as L1 is concerned. It will only return (and set
10475          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10476          */
10477         return 0;
10478 }
10479
10480 /*
10481  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10482  * for running an L2 nested guest.
10483  */
10484 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10485 {
10486         struct vmcs12 *vmcs12;
10487         struct vcpu_vmx *vmx = to_vmx(vcpu);
10488         u32 exit_qual;
10489         int ret;
10490
10491         if (!nested_vmx_check_permission(vcpu))
10492                 return 1;
10493
10494         if (!nested_vmx_check_vmcs12(vcpu))
10495                 goto out;
10496
10497         vmcs12 = get_vmcs12(vcpu);
10498
10499         if (enable_shadow_vmcs)
10500                 copy_shadow_to_vmcs12(vmx);
10501
10502         /*
10503          * The nested entry process starts with enforcing various prerequisites
10504          * on vmcs12 as required by the Intel SDM, and act appropriately when
10505          * they fail: As the SDM explains, some conditions should cause the
10506          * instruction to fail, while others will cause the instruction to seem
10507          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10508          * To speed up the normal (success) code path, we should avoid checking
10509          * for misconfigurations which will anyway be caught by the processor
10510          * when using the merged vmcs02.
10511          */
10512         if (vmcs12->launch_state == launch) {
10513                 nested_vmx_failValid(vcpu,
10514                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10515                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10516                 goto out;
10517         }
10518
10519         ret = check_vmentry_prereqs(vcpu, vmcs12);
10520         if (ret) {
10521                 nested_vmx_failValid(vcpu, ret);
10522                 goto out;
10523         }
10524
10525         /*
10526          * After this point, the trap flag no longer triggers a singlestep trap
10527          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10528          * This is not 100% correct; for performance reasons, we delegate most
10529          * of the checks on host state to the processor.  If those fail,
10530          * the singlestep trap is missed.
10531          */
10532         skip_emulated_instruction(vcpu);
10533
10534         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10535         if (ret) {
10536                 nested_vmx_entry_failure(vcpu, vmcs12,
10537                                          EXIT_REASON_INVALID_STATE, exit_qual);
10538                 return 1;
10539         }
10540
10541         /*
10542          * We're finally done with prerequisite checking, and can start with
10543          * the nested entry.
10544          */
10545
10546         ret = enter_vmx_non_root_mode(vcpu, true);
10547         if (ret)
10548                 return ret;
10549
10550         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10551                 return kvm_vcpu_halt(vcpu);
10552
10553         vmx->nested.nested_run_pending = 1;
10554
10555         return 1;
10556
10557 out:
10558         return kvm_skip_emulated_instruction(vcpu);
10559 }
10560
10561 /*
10562  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10563  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10564  * This function returns the new value we should put in vmcs12.guest_cr0.
10565  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10566  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10567  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10568  *     didn't trap the bit, because if L1 did, so would L0).
10569  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10570  *     been modified by L2, and L1 knows it. So just leave the old value of
10571  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10572  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10573  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10574  *     changed these bits, and therefore they need to be updated, but L0
10575  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10576  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10577  */
10578 static inline unsigned long
10579 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10580 {
10581         return
10582         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10583         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10584         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10585                         vcpu->arch.cr0_guest_owned_bits));
10586 }
10587
10588 static inline unsigned long
10589 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10590 {
10591         return
10592         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10593         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10594         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10595                         vcpu->arch.cr4_guest_owned_bits));
10596 }
10597
10598 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10599                                        struct vmcs12 *vmcs12)
10600 {
10601         u32 idt_vectoring;
10602         unsigned int nr;
10603
10604         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10605                 nr = vcpu->arch.exception.nr;
10606                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10607
10608                 if (kvm_exception_is_soft(nr)) {
10609                         vmcs12->vm_exit_instruction_len =
10610                                 vcpu->arch.event_exit_inst_len;
10611                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10612                 } else
10613                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10614
10615                 if (vcpu->arch.exception.has_error_code) {
10616                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10617                         vmcs12->idt_vectoring_error_code =
10618                                 vcpu->arch.exception.error_code;
10619                 }
10620
10621                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10622         } else if (vcpu->arch.nmi_injected) {
10623                 vmcs12->idt_vectoring_info_field =
10624                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10625         } else if (vcpu->arch.interrupt.pending) {
10626                 nr = vcpu->arch.interrupt.nr;
10627                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10628
10629                 if (vcpu->arch.interrupt.soft) {
10630                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10631                         vmcs12->vm_entry_instruction_len =
10632                                 vcpu->arch.event_exit_inst_len;
10633                 } else
10634                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10635
10636                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10637         }
10638 }
10639
10640 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10641 {
10642         struct vcpu_vmx *vmx = to_vmx(vcpu);
10643
10644         if (vcpu->arch.exception.pending ||
10645                 vcpu->arch.nmi_injected ||
10646                 vcpu->arch.interrupt.pending)
10647                 return -EBUSY;
10648
10649         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10650             vmx->nested.preemption_timer_expired) {
10651                 if (vmx->nested.nested_run_pending)
10652                         return -EBUSY;
10653                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10654                 return 0;
10655         }
10656
10657         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10658                 if (vmx->nested.nested_run_pending)
10659                         return -EBUSY;
10660                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10661                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10662                                   INTR_INFO_VALID_MASK, 0);
10663                 /*
10664                  * The NMI-triggered VM exit counts as injection:
10665                  * clear this one and block further NMIs.
10666                  */
10667                 vcpu->arch.nmi_pending = 0;
10668                 vmx_set_nmi_mask(vcpu, true);
10669                 return 0;
10670         }
10671
10672         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10673             nested_exit_on_intr(vcpu)) {
10674                 if (vmx->nested.nested_run_pending)
10675                         return -EBUSY;
10676                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10677                 return 0;
10678         }
10679
10680         vmx_complete_nested_posted_interrupt(vcpu);
10681         return 0;
10682 }
10683
10684 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10685 {
10686         ktime_t remaining =
10687                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10688         u64 value;
10689
10690         if (ktime_to_ns(remaining) <= 0)
10691                 return 0;
10692
10693         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10694         do_div(value, 1000000);
10695         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10696 }
10697
10698 /*
10699  * Update the guest state fields of vmcs12 to reflect changes that
10700  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10701  * VM-entry controls is also updated, since this is really a guest
10702  * state bit.)
10703  */
10704 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10705 {
10706         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10707         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10708
10709         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10710         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10711         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10712
10713         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10714         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10715         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10716         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10717         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10718         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10719         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10720         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10721         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10722         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10723         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10724         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10725         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10726         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10727         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10728         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10729         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10730         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10731         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10732         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10733         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10734         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10735         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10736         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10737         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10738         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10739         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10740         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10741         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10742         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10743         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10744         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10745         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10746         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10747         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10748         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10749
10750         vmcs12->guest_interruptibility_info =
10751                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10752         vmcs12->guest_pending_dbg_exceptions =
10753                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10754         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10755                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10756         else
10757                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10758
10759         if (nested_cpu_has_preemption_timer(vmcs12)) {
10760                 if (vmcs12->vm_exit_controls &
10761                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10762                         vmcs12->vmx_preemption_timer_value =
10763                                 vmx_get_preemption_timer_value(vcpu);
10764                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10765         }
10766
10767         /*
10768          * In some cases (usually, nested EPT), L2 is allowed to change its
10769          * own CR3 without exiting. If it has changed it, we must keep it.
10770          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10771          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10772          *
10773          * Additionally, restore L2's PDPTR to vmcs12.
10774          */
10775         if (enable_ept) {
10776                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10777                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10778                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10779                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10780                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10781         }
10782
10783         if (nested_cpu_has_ept(vmcs12))
10784                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10785
10786         if (nested_cpu_has_vid(vmcs12))
10787                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10788
10789         vmcs12->vm_entry_controls =
10790                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10791                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10792
10793         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10794                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10795                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10796         }
10797
10798         /* TODO: These cannot have changed unless we have MSR bitmaps and
10799          * the relevant bit asks not to trap the change */
10800         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10801                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10802         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10803                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10804         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10805         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10806         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10807         if (kvm_mpx_supported())
10808                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10809         if (nested_cpu_has_xsaves(vmcs12))
10810                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10811 }
10812
10813 /*
10814  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10815  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10816  * and this function updates it to reflect the changes to the guest state while
10817  * L2 was running (and perhaps made some exits which were handled directly by L0
10818  * without going back to L1), and to reflect the exit reason.
10819  * Note that we do not have to copy here all VMCS fields, just those that
10820  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10821  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10822  * which already writes to vmcs12 directly.
10823  */
10824 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10825                            u32 exit_reason, u32 exit_intr_info,
10826                            unsigned long exit_qualification)
10827 {
10828         /* update guest state fields: */
10829         sync_vmcs12(vcpu, vmcs12);
10830
10831         /* update exit information fields: */
10832
10833         vmcs12->vm_exit_reason = exit_reason;
10834         vmcs12->exit_qualification = exit_qualification;
10835
10836         vmcs12->vm_exit_intr_info = exit_intr_info;
10837         if ((vmcs12->vm_exit_intr_info &
10838              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10839             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10840                 vmcs12->vm_exit_intr_error_code =
10841                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10842         vmcs12->idt_vectoring_info_field = 0;
10843         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10844         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10845
10846         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10847                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10848                  * instead of reading the real value. */
10849                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10850
10851                 /*
10852                  * Transfer the event that L0 or L1 may wanted to inject into
10853                  * L2 to IDT_VECTORING_INFO_FIELD.
10854                  */
10855                 vmcs12_save_pending_event(vcpu, vmcs12);
10856         }
10857
10858         /*
10859          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10860          * preserved above and would only end up incorrectly in L1.
10861          */
10862         vcpu->arch.nmi_injected = false;
10863         kvm_clear_exception_queue(vcpu);
10864         kvm_clear_interrupt_queue(vcpu);
10865 }
10866
10867 /*
10868  * A part of what we need to when the nested L2 guest exits and we want to
10869  * run its L1 parent, is to reset L1's guest state to the host state specified
10870  * in vmcs12.
10871  * This function is to be called not only on normal nested exit, but also on
10872  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10873  * Failures During or After Loading Guest State").
10874  * This function should be called when the active VMCS is L1's (vmcs01).
10875  */
10876 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10877                                    struct vmcs12 *vmcs12)
10878 {
10879         struct kvm_segment seg;
10880         u32 entry_failure_code;
10881
10882         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10883                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10884         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10885                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10886         else
10887                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10888         vmx_set_efer(vcpu, vcpu->arch.efer);
10889
10890         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10891         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10892         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10893         /*
10894          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10895          * actually changed, because vmx_set_cr0 refers to efer set above.
10896          *
10897          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10898          * (KVM doesn't change it);
10899          */
10900         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10901         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10902
10903         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10904         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10905         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10906
10907         nested_ept_uninit_mmu_context(vcpu);
10908
10909         /*
10910          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10911          * couldn't have changed.
10912          */
10913         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10914                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10915
10916         if (!enable_ept)
10917                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10918
10919         if (enable_vpid) {
10920                 /*
10921                  * Trivially support vpid by letting L2s share their parent
10922                  * L1's vpid. TODO: move to a more elaborate solution, giving
10923                  * each L2 its own vpid and exposing the vpid feature to L1.
10924                  */
10925                 vmx_flush_tlb(vcpu);
10926         }
10927
10928
10929         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10930         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10931         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10932         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10933         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10934
10935         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10936         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10937                 vmcs_write64(GUEST_BNDCFGS, 0);
10938
10939         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10940                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10941                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10942         }
10943         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10944                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10945                         vmcs12->host_ia32_perf_global_ctrl);
10946
10947         /* Set L1 segment info according to Intel SDM
10948             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10949         seg = (struct kvm_segment) {
10950                 .base = 0,
10951                 .limit = 0xFFFFFFFF,
10952                 .selector = vmcs12->host_cs_selector,
10953                 .type = 11,
10954                 .present = 1,
10955                 .s = 1,
10956                 .g = 1
10957         };
10958         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10959                 seg.l = 1;
10960         else
10961                 seg.db = 1;
10962         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10963         seg = (struct kvm_segment) {
10964                 .base = 0,
10965                 .limit = 0xFFFFFFFF,
10966                 .type = 3,
10967                 .present = 1,
10968                 .s = 1,
10969                 .db = 1,
10970                 .g = 1
10971         };
10972         seg.selector = vmcs12->host_ds_selector;
10973         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10974         seg.selector = vmcs12->host_es_selector;
10975         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10976         seg.selector = vmcs12->host_ss_selector;
10977         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10978         seg.selector = vmcs12->host_fs_selector;
10979         seg.base = vmcs12->host_fs_base;
10980         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10981         seg.selector = vmcs12->host_gs_selector;
10982         seg.base = vmcs12->host_gs_base;
10983         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10984         seg = (struct kvm_segment) {
10985                 .base = vmcs12->host_tr_base,
10986                 .limit = 0x67,
10987                 .selector = vmcs12->host_tr_selector,
10988                 .type = 11,
10989                 .present = 1
10990         };
10991         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10992
10993         kvm_set_dr(vcpu, 7, 0x400);
10994         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10995
10996         if (cpu_has_vmx_msr_bitmap())
10997                 vmx_set_msr_bitmap(vcpu);
10998
10999         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11000                                 vmcs12->vm_exit_msr_load_count))
11001                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11002 }
11003
11004 /*
11005  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11006  * and modify vmcs12 to make it see what it would expect to see there if
11007  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11008  */
11009 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11010                               u32 exit_intr_info,
11011                               unsigned long exit_qualification)
11012 {
11013         struct vcpu_vmx *vmx = to_vmx(vcpu);
11014         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11015         u32 vm_inst_error = 0;
11016
11017         /* trying to cancel vmlaunch/vmresume is a bug */
11018         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11019
11020         leave_guest_mode(vcpu);
11021         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11022                        exit_qualification);
11023
11024         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11025                                  vmcs12->vm_exit_msr_store_count))
11026                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11027
11028         if (unlikely(vmx->fail))
11029                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11030
11031         vmx_load_vmcs01(vcpu);
11032
11033         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11034             && nested_exit_intr_ack_set(vcpu)) {
11035                 int irq = kvm_cpu_get_interrupt(vcpu);
11036                 WARN_ON(irq < 0);
11037                 vmcs12->vm_exit_intr_info = irq |
11038                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11039         }
11040
11041         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11042                                        vmcs12->exit_qualification,
11043                                        vmcs12->idt_vectoring_info_field,
11044                                        vmcs12->vm_exit_intr_info,
11045                                        vmcs12->vm_exit_intr_error_code,
11046                                        KVM_ISA_VMX);
11047
11048         vm_entry_controls_reset_shadow(vmx);
11049         vm_exit_controls_reset_shadow(vmx);
11050         vmx_segment_cache_clear(vmx);
11051
11052         /* if no vmcs02 cache requested, remove the one we used */
11053         if (VMCS02_POOL_SIZE == 0)
11054                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11055
11056         load_vmcs12_host_state(vcpu, vmcs12);
11057
11058         /* Update any VMCS fields that might have changed while L2 ran */
11059         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11060         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11061         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11062         if (vmx->hv_deadline_tsc == -1)
11063                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11064                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11065         else
11066                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11067                               PIN_BASED_VMX_PREEMPTION_TIMER);
11068         if (kvm_has_tsc_control)
11069                 decache_tsc_multiplier(vmx);
11070
11071         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11072                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11073                 vmx_set_virtual_x2apic_mode(vcpu,
11074                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11075         }
11076
11077         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11078         vmx->host_rsp = 0;
11079
11080         /* Unpin physical memory we referred to in vmcs02 */
11081         if (vmx->nested.apic_access_page) {
11082                 nested_release_page(vmx->nested.apic_access_page);
11083                 vmx->nested.apic_access_page = NULL;
11084         }
11085         if (vmx->nested.virtual_apic_page) {
11086                 nested_release_page(vmx->nested.virtual_apic_page);
11087                 vmx->nested.virtual_apic_page = NULL;
11088         }
11089         if (vmx->nested.pi_desc_page) {
11090                 kunmap(vmx->nested.pi_desc_page);
11091                 nested_release_page(vmx->nested.pi_desc_page);
11092                 vmx->nested.pi_desc_page = NULL;
11093                 vmx->nested.pi_desc = NULL;
11094         }
11095
11096         /*
11097          * We are now running in L2, mmu_notifier will force to reload the
11098          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11099          */
11100         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11101
11102         /*
11103          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11104          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11105          * success or failure flag accordingly.
11106          */
11107         if (unlikely(vmx->fail)) {
11108                 vmx->fail = 0;
11109                 nested_vmx_failValid(vcpu, vm_inst_error);
11110         } else
11111                 nested_vmx_succeed(vcpu);
11112         if (enable_shadow_vmcs)
11113                 vmx->nested.sync_shadow_vmcs = true;
11114
11115         /* in case we halted in L2 */
11116         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11117 }
11118
11119 /*
11120  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11121  */
11122 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11123 {
11124         if (is_guest_mode(vcpu))
11125                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11126         free_nested(to_vmx(vcpu));
11127 }
11128
11129 /*
11130  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11131  * 23.7 "VM-entry failures during or after loading guest state" (this also
11132  * lists the acceptable exit-reason and exit-qualification parameters).
11133  * It should only be called before L2 actually succeeded to run, and when
11134  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11135  */
11136 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11137                         struct vmcs12 *vmcs12,
11138                         u32 reason, unsigned long qualification)
11139 {
11140         load_vmcs12_host_state(vcpu, vmcs12);
11141         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11142         vmcs12->exit_qualification = qualification;
11143         nested_vmx_succeed(vcpu);
11144         if (enable_shadow_vmcs)
11145                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11146 }
11147
11148 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11149                                struct x86_instruction_info *info,
11150                                enum x86_intercept_stage stage)
11151 {
11152         return X86EMUL_CONTINUE;
11153 }
11154
11155 #ifdef CONFIG_X86_64
11156 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11157 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11158                                   u64 divisor, u64 *result)
11159 {
11160         u64 low = a << shift, high = a >> (64 - shift);
11161
11162         /* To avoid the overflow on divq */
11163         if (high >= divisor)
11164                 return 1;
11165
11166         /* Low hold the result, high hold rem which is discarded */
11167         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11168             "rm" (divisor), "0" (low), "1" (high));
11169         *result = low;
11170
11171         return 0;
11172 }
11173
11174 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11175 {
11176         struct vcpu_vmx *vmx = to_vmx(vcpu);
11177         u64 tscl = rdtsc();
11178         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11179         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11180
11181         /* Convert to host delta tsc if tsc scaling is enabled */
11182         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11183                         u64_shl_div_u64(delta_tsc,
11184                                 kvm_tsc_scaling_ratio_frac_bits,
11185                                 vcpu->arch.tsc_scaling_ratio,
11186                                 &delta_tsc))
11187                 return -ERANGE;
11188
11189         /*
11190          * If the delta tsc can't fit in the 32 bit after the multi shift,
11191          * we can't use the preemption timer.
11192          * It's possible that it fits on later vmentries, but checking
11193          * on every vmentry is costly so we just use an hrtimer.
11194          */
11195         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11196                 return -ERANGE;
11197
11198         vmx->hv_deadline_tsc = tscl + delta_tsc;
11199         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11200                         PIN_BASED_VMX_PREEMPTION_TIMER);
11201         return 0;
11202 }
11203
11204 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11205 {
11206         struct vcpu_vmx *vmx = to_vmx(vcpu);
11207         vmx->hv_deadline_tsc = -1;
11208         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11209                         PIN_BASED_VMX_PREEMPTION_TIMER);
11210 }
11211 #endif
11212
11213 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11214 {
11215         if (ple_gap)
11216                 shrink_ple_window(vcpu);
11217 }
11218
11219 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11220                                      struct kvm_memory_slot *slot)
11221 {
11222         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11223         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11224 }
11225
11226 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11227                                        struct kvm_memory_slot *slot)
11228 {
11229         kvm_mmu_slot_set_dirty(kvm, slot);
11230 }
11231
11232 static void vmx_flush_log_dirty(struct kvm *kvm)
11233 {
11234         kvm_flush_pml_buffers(kvm);
11235 }
11236
11237 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11238                                            struct kvm_memory_slot *memslot,
11239                                            gfn_t offset, unsigned long mask)
11240 {
11241         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11242 }
11243
11244 /*
11245  * This routine does the following things for vCPU which is going
11246  * to be blocked if VT-d PI is enabled.
11247  * - Store the vCPU to the wakeup list, so when interrupts happen
11248  *   we can find the right vCPU to wake up.
11249  * - Change the Posted-interrupt descriptor as below:
11250  *      'NDST' <-- vcpu->pre_pcpu
11251  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11252  * - If 'ON' is set during this process, which means at least one
11253  *   interrupt is posted for this vCPU, we cannot block it, in
11254  *   this case, return 1, otherwise, return 0.
11255  *
11256  */
11257 static int pi_pre_block(struct kvm_vcpu *vcpu)
11258 {
11259         unsigned long flags;
11260         unsigned int dest;
11261         struct pi_desc old, new;
11262         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11263
11264         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11265                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11266                 !kvm_vcpu_apicv_active(vcpu))
11267                 return 0;
11268
11269         vcpu->pre_pcpu = vcpu->cpu;
11270         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11271                           vcpu->pre_pcpu), flags);
11272         list_add_tail(&vcpu->blocked_vcpu_list,
11273                       &per_cpu(blocked_vcpu_on_cpu,
11274                       vcpu->pre_pcpu));
11275         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11276                                vcpu->pre_pcpu), flags);
11277
11278         do {
11279                 old.control = new.control = pi_desc->control;
11280
11281                 /*
11282                  * We should not block the vCPU if
11283                  * an interrupt is posted for it.
11284                  */
11285                 if (pi_test_on(pi_desc) == 1) {
11286                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11287                                           vcpu->pre_pcpu), flags);
11288                         list_del(&vcpu->blocked_vcpu_list);
11289                         spin_unlock_irqrestore(
11290                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11291                                         vcpu->pre_pcpu), flags);
11292                         vcpu->pre_pcpu = -1;
11293
11294                         return 1;
11295                 }
11296
11297                 WARN((pi_desc->sn == 1),
11298                      "Warning: SN field of posted-interrupts "
11299                      "is set before blocking\n");
11300
11301                 /*
11302                  * Since vCPU can be preempted during this process,
11303                  * vcpu->cpu could be different with pre_pcpu, we
11304                  * need to set pre_pcpu as the destination of wakeup
11305                  * notification event, then we can find the right vCPU
11306                  * to wakeup in wakeup handler if interrupts happen
11307                  * when the vCPU is in blocked state.
11308                  */
11309                 dest = cpu_physical_id(vcpu->pre_pcpu);
11310
11311                 if (x2apic_enabled())
11312                         new.ndst = dest;
11313                 else
11314                         new.ndst = (dest << 8) & 0xFF00;
11315
11316                 /* set 'NV' to 'wakeup vector' */
11317                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11318         } while (cmpxchg(&pi_desc->control, old.control,
11319                         new.control) != old.control);
11320
11321         return 0;
11322 }
11323
11324 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11325 {
11326         if (pi_pre_block(vcpu))
11327                 return 1;
11328
11329         if (kvm_lapic_hv_timer_in_use(vcpu))
11330                 kvm_lapic_switch_to_sw_timer(vcpu);
11331
11332         return 0;
11333 }
11334
11335 static void pi_post_block(struct kvm_vcpu *vcpu)
11336 {
11337         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11338         struct pi_desc old, new;
11339         unsigned int dest;
11340         unsigned long flags;
11341
11342         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11343                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11344                 !kvm_vcpu_apicv_active(vcpu))
11345                 return;
11346
11347         do {
11348                 old.control = new.control = pi_desc->control;
11349
11350                 dest = cpu_physical_id(vcpu->cpu);
11351
11352                 if (x2apic_enabled())
11353                         new.ndst = dest;
11354                 else
11355                         new.ndst = (dest << 8) & 0xFF00;
11356
11357                 /* Allow posting non-urgent interrupts */
11358                 new.sn = 0;
11359
11360                 /* set 'NV' to 'notification vector' */
11361                 new.nv = POSTED_INTR_VECTOR;
11362         } while (cmpxchg(&pi_desc->control, old.control,
11363                         new.control) != old.control);
11364
11365         if(vcpu->pre_pcpu != -1) {
11366                 spin_lock_irqsave(
11367                         &per_cpu(blocked_vcpu_on_cpu_lock,
11368                         vcpu->pre_pcpu), flags);
11369                 list_del(&vcpu->blocked_vcpu_list);
11370                 spin_unlock_irqrestore(
11371                         &per_cpu(blocked_vcpu_on_cpu_lock,
11372                         vcpu->pre_pcpu), flags);
11373                 vcpu->pre_pcpu = -1;
11374         }
11375 }
11376
11377 static void vmx_post_block(struct kvm_vcpu *vcpu)
11378 {
11379         if (kvm_x86_ops->set_hv_timer)
11380                 kvm_lapic_switch_to_hv_timer(vcpu);
11381
11382         pi_post_block(vcpu);
11383 }
11384
11385 /*
11386  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11387  *
11388  * @kvm: kvm
11389  * @host_irq: host irq of the interrupt
11390  * @guest_irq: gsi of the interrupt
11391  * @set: set or unset PI
11392  * returns 0 on success, < 0 on failure
11393  */
11394 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11395                               uint32_t guest_irq, bool set)
11396 {
11397         struct kvm_kernel_irq_routing_entry *e;
11398         struct kvm_irq_routing_table *irq_rt;
11399         struct kvm_lapic_irq irq;
11400         struct kvm_vcpu *vcpu;
11401         struct vcpu_data vcpu_info;
11402         int idx, ret = -EINVAL;
11403
11404         if (!kvm_arch_has_assigned_device(kvm) ||
11405                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11406                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11407                 return 0;
11408
11409         idx = srcu_read_lock(&kvm->irq_srcu);
11410         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11411         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11412
11413         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11414                 if (e->type != KVM_IRQ_ROUTING_MSI)
11415                         continue;
11416                 /*
11417                  * VT-d PI cannot support posting multicast/broadcast
11418                  * interrupts to a vCPU, we still use interrupt remapping
11419                  * for these kind of interrupts.
11420                  *
11421                  * For lowest-priority interrupts, we only support
11422                  * those with single CPU as the destination, e.g. user
11423                  * configures the interrupts via /proc/irq or uses
11424                  * irqbalance to make the interrupts single-CPU.
11425                  *
11426                  * We will support full lowest-priority interrupt later.
11427                  */
11428
11429                 kvm_set_msi_irq(kvm, e, &irq);
11430                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11431                         /*
11432                          * Make sure the IRTE is in remapped mode if
11433                          * we don't handle it in posted mode.
11434                          */
11435                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11436                         if (ret < 0) {
11437                                 printk(KERN_INFO
11438                                    "failed to back to remapped mode, irq: %u\n",
11439                                    host_irq);
11440                                 goto out;
11441                         }
11442
11443                         continue;
11444                 }
11445
11446                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11447                 vcpu_info.vector = irq.vector;
11448
11449                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11450                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11451
11452                 if (set)
11453                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11454                 else {
11455                         /* suppress notification event before unposting */
11456                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11457                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11458                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11459                 }
11460
11461                 if (ret < 0) {
11462                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11463                                         __func__);
11464                         goto out;
11465                 }
11466         }
11467
11468         ret = 0;
11469 out:
11470         srcu_read_unlock(&kvm->irq_srcu, idx);
11471         return ret;
11472 }
11473
11474 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11475 {
11476         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11477                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11478                         FEATURE_CONTROL_LMCE;
11479         else
11480                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11481                         ~FEATURE_CONTROL_LMCE;
11482 }
11483
11484 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11485         .cpu_has_kvm_support = cpu_has_kvm_support,
11486         .disabled_by_bios = vmx_disabled_by_bios,
11487         .hardware_setup = hardware_setup,
11488         .hardware_unsetup = hardware_unsetup,
11489         .check_processor_compatibility = vmx_check_processor_compat,
11490         .hardware_enable = hardware_enable,
11491         .hardware_disable = hardware_disable,
11492         .cpu_has_accelerated_tpr = report_flexpriority,
11493         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11494
11495         .vcpu_create = vmx_create_vcpu,
11496         .vcpu_free = vmx_free_vcpu,
11497         .vcpu_reset = vmx_vcpu_reset,
11498
11499         .prepare_guest_switch = vmx_save_host_state,
11500         .vcpu_load = vmx_vcpu_load,
11501         .vcpu_put = vmx_vcpu_put,
11502
11503         .update_bp_intercept = update_exception_bitmap,
11504         .get_msr = vmx_get_msr,
11505         .set_msr = vmx_set_msr,
11506         .get_segment_base = vmx_get_segment_base,
11507         .get_segment = vmx_get_segment,
11508         .set_segment = vmx_set_segment,
11509         .get_cpl = vmx_get_cpl,
11510         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11511         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11512         .decache_cr3 = vmx_decache_cr3,
11513         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11514         .set_cr0 = vmx_set_cr0,
11515         .set_cr3 = vmx_set_cr3,
11516         .set_cr4 = vmx_set_cr4,
11517         .set_efer = vmx_set_efer,
11518         .get_idt = vmx_get_idt,
11519         .set_idt = vmx_set_idt,
11520         .get_gdt = vmx_get_gdt,
11521         .set_gdt = vmx_set_gdt,
11522         .get_dr6 = vmx_get_dr6,
11523         .set_dr6 = vmx_set_dr6,
11524         .set_dr7 = vmx_set_dr7,
11525         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11526         .cache_reg = vmx_cache_reg,
11527         .get_rflags = vmx_get_rflags,
11528         .set_rflags = vmx_set_rflags,
11529
11530         .get_pkru = vmx_get_pkru,
11531
11532         .tlb_flush = vmx_flush_tlb,
11533
11534         .run = vmx_vcpu_run,
11535         .handle_exit = vmx_handle_exit,
11536         .skip_emulated_instruction = skip_emulated_instruction,
11537         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11538         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11539         .patch_hypercall = vmx_patch_hypercall,
11540         .set_irq = vmx_inject_irq,
11541         .set_nmi = vmx_inject_nmi,
11542         .queue_exception = vmx_queue_exception,
11543         .cancel_injection = vmx_cancel_injection,
11544         .interrupt_allowed = vmx_interrupt_allowed,
11545         .nmi_allowed = vmx_nmi_allowed,
11546         .get_nmi_mask = vmx_get_nmi_mask,
11547         .set_nmi_mask = vmx_set_nmi_mask,
11548         .enable_nmi_window = enable_nmi_window,
11549         .enable_irq_window = enable_irq_window,
11550         .update_cr8_intercept = update_cr8_intercept,
11551         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11552         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11553         .get_enable_apicv = vmx_get_enable_apicv,
11554         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11555         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11556         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11557         .hwapic_irr_update = vmx_hwapic_irr_update,
11558         .hwapic_isr_update = vmx_hwapic_isr_update,
11559         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11560         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11561
11562         .set_tss_addr = vmx_set_tss_addr,
11563         .get_tdp_level = get_ept_level,
11564         .get_mt_mask = vmx_get_mt_mask,
11565
11566         .get_exit_info = vmx_get_exit_info,
11567
11568         .get_lpage_level = vmx_get_lpage_level,
11569
11570         .cpuid_update = vmx_cpuid_update,
11571
11572         .rdtscp_supported = vmx_rdtscp_supported,
11573         .invpcid_supported = vmx_invpcid_supported,
11574
11575         .set_supported_cpuid = vmx_set_supported_cpuid,
11576
11577         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11578
11579         .write_tsc_offset = vmx_write_tsc_offset,
11580
11581         .set_tdp_cr3 = vmx_set_cr3,
11582
11583         .check_intercept = vmx_check_intercept,
11584         .handle_external_intr = vmx_handle_external_intr,
11585         .mpx_supported = vmx_mpx_supported,
11586         .xsaves_supported = vmx_xsaves_supported,
11587
11588         .check_nested_events = vmx_check_nested_events,
11589
11590         .sched_in = vmx_sched_in,
11591
11592         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11593         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11594         .flush_log_dirty = vmx_flush_log_dirty,
11595         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11596
11597         .pre_block = vmx_pre_block,
11598         .post_block = vmx_post_block,
11599
11600         .pmu_ops = &intel_pmu_ops,
11601
11602         .update_pi_irte = vmx_update_pi_irte,
11603
11604 #ifdef CONFIG_X86_64
11605         .set_hv_timer = vmx_set_hv_timer,
11606         .cancel_hv_timer = vmx_cancel_hv_timer,
11607 #endif
11608
11609         .setup_mce = vmx_setup_mce,
11610 };
11611
11612 static int __init vmx_init(void)
11613 {
11614         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11615                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11616         if (r)
11617                 return r;
11618
11619 #ifdef CONFIG_KEXEC_CORE
11620         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11621                            crash_vmclear_local_loaded_vmcss);
11622 #endif
11623
11624         return 0;
11625 }
11626
11627 static void __exit vmx_exit(void)
11628 {
11629 #ifdef CONFIG_KEXEC_CORE
11630         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11631         synchronize_rcu();
11632 #endif
11633
11634         kvm_exit();
11635 }
11636
11637 module_init(vmx_init)
11638 module_exit(vmx_exit)