arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_ept(void)
1243 {
1244         return vmcs_config.cpu_based_2nd_exec_ctrl &
1245                 SECONDARY_EXEC_ENABLE_EPT;
1246 }
1247
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1249 {
1250         return vmcs_config.cpu_based_2nd_exec_ctrl &
1251                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252 }
1253
1254 static inline bool cpu_has_vmx_ple(void)
1255 {
1256         return vmcs_config.cpu_based_2nd_exec_ctrl &
1257                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258 }
1259
1260 static inline bool cpu_has_vmx_basic_inout(void)
1261 {
1262         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263 }
1264
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1266 {
1267         return flexpriority_enabled && lapic_in_kernel(vcpu);
1268 }
1269
1270 static inline bool cpu_has_vmx_vpid(void)
1271 {
1272         return vmcs_config.cpu_based_2nd_exec_ctrl &
1273                 SECONDARY_EXEC_ENABLE_VPID;
1274 }
1275
1276 static inline bool cpu_has_vmx_rdtscp(void)
1277 {
1278         return vmcs_config.cpu_based_2nd_exec_ctrl &
1279                 SECONDARY_EXEC_RDTSCP;
1280 }
1281
1282 static inline bool cpu_has_vmx_invpcid(void)
1283 {
1284         return vmcs_config.cpu_based_2nd_exec_ctrl &
1285                 SECONDARY_EXEC_ENABLE_INVPCID;
1286 }
1287
1288 static inline bool cpu_has_virtual_nmis(void)
1289 {
1290         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1291 }
1292
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl &
1296                 SECONDARY_EXEC_WBINVD_EXITING;
1297 }
1298
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 {
1301         u64 vmx_msr;
1302         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303         /* check if the cpu supports writing r/o exit information fields */
1304         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1305                 return false;
1306
1307         return vmcs_config.cpu_based_2nd_exec_ctrl &
1308                 SECONDARY_EXEC_SHADOW_VMCS;
1309 }
1310
1311 static inline bool cpu_has_vmx_pml(void)
1312 {
1313         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1314 }
1315
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl &
1319                 SECONDARY_EXEC_TSC_SCALING;
1320 }
1321
1322 static inline bool report_flexpriority(void)
1323 {
1324         return flexpriority_enabled;
1325 }
1326
1327 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328 {
1329         return vmcs12->cpu_based_vm_exec_control & bit;
1330 }
1331
1332 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return (vmcs12->cpu_based_vm_exec_control &
1335                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336                 (vmcs12->secondary_vm_exec_control & bit);
1337 }
1338
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1340 {
1341         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342 }
1343
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control &
1347                 PIN_BASED_VMX_PREEMPTION_TIMER;
1348 }
1349
1350 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351 {
1352         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353 }
1354
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358                 vmx_xsaves_supported();
1359 }
1360
1361 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1362 {
1363         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1364 }
1365
1366 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1369 }
1370
1371 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1374 }
1375
1376 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1379 }
1380
1381 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1382 {
1383         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1384 }
1385
1386 static inline bool is_nmi(u32 intr_info)
1387 {
1388         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1389                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1390 }
1391
1392 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1393                               u32 exit_intr_info,
1394                               unsigned long exit_qualification);
1395 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1396                         struct vmcs12 *vmcs12,
1397                         u32 reason, unsigned long qualification);
1398
1399 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1400 {
1401         int i;
1402
1403         for (i = 0; i < vmx->nmsrs; ++i)
1404                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1405                         return i;
1406         return -1;
1407 }
1408
1409 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1410 {
1411     struct {
1412         u64 vpid : 16;
1413         u64 rsvd : 48;
1414         u64 gva;
1415     } operand = { vpid, 0, gva };
1416
1417     asm volatile (__ex(ASM_VMX_INVVPID)
1418                   /* CF==1 or ZF==1 --> rc = -1 */
1419                   "; ja 1f ; ud2 ; 1:"
1420                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1421 }
1422
1423 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1424 {
1425         struct {
1426                 u64 eptp, gpa;
1427         } operand = {eptp, gpa};
1428
1429         asm volatile (__ex(ASM_VMX_INVEPT)
1430                         /* CF==1 or ZF==1 --> rc = -1 */
1431                         "; ja 1f ; ud2 ; 1:\n"
1432                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1433 }
1434
1435 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1436 {
1437         int i;
1438
1439         i = __find_msr_index(vmx, msr);
1440         if (i >= 0)
1441                 return &vmx->guest_msrs[i];
1442         return NULL;
1443 }
1444
1445 static void vmcs_clear(struct vmcs *vmcs)
1446 {
1447         u64 phys_addr = __pa(vmcs);
1448         u8 error;
1449
1450         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1451                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1452                       : "cc", "memory");
1453         if (error)
1454                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1455                        vmcs, phys_addr);
1456 }
1457
1458 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1459 {
1460         vmcs_clear(loaded_vmcs->vmcs);
1461         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1462                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1463         loaded_vmcs->cpu = -1;
1464         loaded_vmcs->launched = 0;
1465 }
1466
1467 static void vmcs_load(struct vmcs *vmcs)
1468 {
1469         u64 phys_addr = __pa(vmcs);
1470         u8 error;
1471
1472         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1473                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1474                         : "cc", "memory");
1475         if (error)
1476                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1477                        vmcs, phys_addr);
1478 }
1479
1480 #ifdef CONFIG_KEXEC_CORE
1481 /*
1482  * This bitmap is used to indicate whether the vmclear
1483  * operation is enabled on all cpus. All disabled by
1484  * default.
1485  */
1486 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1487
1488 static inline void crash_enable_local_vmclear(int cpu)
1489 {
1490         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1491 }
1492
1493 static inline void crash_disable_local_vmclear(int cpu)
1494 {
1495         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline int crash_local_vmclear_enabled(int cpu)
1499 {
1500         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static void crash_vmclear_local_loaded_vmcss(void)
1504 {
1505         int cpu = raw_smp_processor_id();
1506         struct loaded_vmcs *v;
1507
1508         if (!crash_local_vmclear_enabled(cpu))
1509                 return;
1510
1511         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1512                             loaded_vmcss_on_cpu_link)
1513                 vmcs_clear(v->vmcs);
1514 }
1515 #else
1516 static inline void crash_enable_local_vmclear(int cpu) { }
1517 static inline void crash_disable_local_vmclear(int cpu) { }
1518 #endif /* CONFIG_KEXEC_CORE */
1519
1520 static void __loaded_vmcs_clear(void *arg)
1521 {
1522         struct loaded_vmcs *loaded_vmcs = arg;
1523         int cpu = raw_smp_processor_id();
1524
1525         if (loaded_vmcs->cpu != cpu)
1526                 return; /* vcpu migration can race with cpu offline */
1527         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1528                 per_cpu(current_vmcs, cpu) = NULL;
1529         crash_disable_local_vmclear(cpu);
1530         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1531
1532         /*
1533          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534          * is before setting loaded_vmcs->vcpu to -1 which is done in
1535          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536          * then adds the vmcs into percpu list before it is deleted.
1537          */
1538         smp_wmb();
1539
1540         loaded_vmcs_init(loaded_vmcs);
1541         crash_enable_local_vmclear(cpu);
1542 }
1543
1544 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1545 {
1546         int cpu = loaded_vmcs->cpu;
1547
1548         if (cpu != -1)
1549                 smp_call_function_single(cpu,
1550                          __loaded_vmcs_clear, loaded_vmcs, 1);
1551 }
1552
1553 static inline void vpid_sync_vcpu_single(int vpid)
1554 {
1555         if (vpid == 0)
1556                 return;
1557
1558         if (cpu_has_vmx_invvpid_single())
1559                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1560 }
1561
1562 static inline void vpid_sync_vcpu_global(void)
1563 {
1564         if (cpu_has_vmx_invvpid_global())
1565                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1566 }
1567
1568 static inline void vpid_sync_context(int vpid)
1569 {
1570         if (cpu_has_vmx_invvpid_single())
1571                 vpid_sync_vcpu_single(vpid);
1572         else
1573                 vpid_sync_vcpu_global();
1574 }
1575
1576 static inline void ept_sync_global(void)
1577 {
1578         if (cpu_has_vmx_invept_global())
1579                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1580 }
1581
1582 static inline void ept_sync_context(u64 eptp)
1583 {
1584         if (enable_ept) {
1585                 if (cpu_has_vmx_invept_context())
1586                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1587                 else
1588                         ept_sync_global();
1589         }
1590 }
1591
1592 static __always_inline void vmcs_check16(unsigned long field)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595                          "16-bit accessor invalid for 64-bit field");
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597                          "16-bit accessor invalid for 64-bit high field");
1598         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599                          "16-bit accessor invalid for 32-bit high field");
1600         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601                          "16-bit accessor invalid for natural width field");
1602 }
1603
1604 static __always_inline void vmcs_check32(unsigned long field)
1605 {
1606         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607                          "32-bit accessor invalid for 16-bit field");
1608         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609                          "32-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check64(unsigned long field)
1613 {
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615                          "64-bit accessor invalid for 16-bit field");
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617                          "64-bit accessor invalid for 64-bit high field");
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619                          "64-bit accessor invalid for 32-bit field");
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621                          "64-bit accessor invalid for natural width field");
1622 }
1623
1624 static __always_inline void vmcs_checkl(unsigned long field)
1625 {
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627                          "Natural width accessor invalid for 16-bit field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629                          "Natural width accessor invalid for 64-bit field");
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631                          "Natural width accessor invalid for 64-bit high field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633                          "Natural width accessor invalid for 32-bit field");
1634 }
1635
1636 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1637 {
1638         unsigned long value;
1639
1640         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641                       : "=a"(value) : "d"(field) : "cc");
1642         return value;
1643 }
1644
1645 static __always_inline u16 vmcs_read16(unsigned long field)
1646 {
1647         vmcs_check16(field);
1648         return __vmcs_readl(field);
1649 }
1650
1651 static __always_inline u32 vmcs_read32(unsigned long field)
1652 {
1653         vmcs_check32(field);
1654         return __vmcs_readl(field);
1655 }
1656
1657 static __always_inline u64 vmcs_read64(unsigned long field)
1658 {
1659         vmcs_check64(field);
1660 #ifdef CONFIG_X86_64
1661         return __vmcs_readl(field);
1662 #else
1663         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1664 #endif
1665 }
1666
1667 static __always_inline unsigned long vmcs_readl(unsigned long field)
1668 {
1669         vmcs_checkl(field);
1670         return __vmcs_readl(field);
1671 }
1672
1673 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1674 {
1675         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1677         dump_stack();
1678 }
1679
1680 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1681 {
1682         u8 error;
1683
1684         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1685                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1686         if (unlikely(error))
1687                 vmwrite_error(field, value);
1688 }
1689
1690 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1691 {
1692         vmcs_check16(field);
1693         __vmcs_writel(field, value);
1694 }
1695
1696 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1697 {
1698         vmcs_check32(field);
1699         __vmcs_writel(field, value);
1700 }
1701
1702 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1703 {
1704         vmcs_check64(field);
1705         __vmcs_writel(field, value);
1706 #ifndef CONFIG_X86_64
1707         asm volatile ("");
1708         __vmcs_writel(field+1, value >> 32);
1709 #endif
1710 }
1711
1712 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1713 {
1714         vmcs_checkl(field);
1715         __vmcs_writel(field, value);
1716 }
1717
1718 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1719 {
1720         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721                          "vmcs_clear_bits does not support 64-bit fields");
1722         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1723 }
1724
1725 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1726 {
1727         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728                          "vmcs_set_bits does not support 64-bit fields");
1729         __vmcs_writel(field, __vmcs_readl(field) | mask);
1730 }
1731
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1733 {
1734         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1735 }
1736
1737 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1738 {
1739         vmcs_write32(VM_ENTRY_CONTROLS, val);
1740         vmx->vm_entry_controls_shadow = val;
1741 }
1742
1743 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1744 {
1745         if (vmx->vm_entry_controls_shadow != val)
1746                 vm_entry_controls_init(vmx, val);
1747 }
1748
1749 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1750 {
1751         return vmx->vm_entry_controls_shadow;
1752 }
1753
1754
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1756 {
1757         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1758 }
1759
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1763 }
1764
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1766 {
1767         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1768 }
1769
1770 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1771 {
1772         vmcs_write32(VM_EXIT_CONTROLS, val);
1773         vmx->vm_exit_controls_shadow = val;
1774 }
1775
1776 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1777 {
1778         if (vmx->vm_exit_controls_shadow != val)
1779                 vm_exit_controls_init(vmx, val);
1780 }
1781
1782 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1783 {
1784         return vmx->vm_exit_controls_shadow;
1785 }
1786
1787
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1789 {
1790         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1791 }
1792
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1796 }
1797
1798 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1799 {
1800         vmx->segment_cache.bitmask = 0;
1801 }
1802
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1804                                        unsigned field)
1805 {
1806         bool ret;
1807         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1808
1809         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811                 vmx->segment_cache.bitmask = 0;
1812         }
1813         ret = vmx->segment_cache.bitmask & mask;
1814         vmx->segment_cache.bitmask |= mask;
1815         return ret;
1816 }
1817
1818 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1819 {
1820         u16 *p = &vmx->segment_cache.seg[seg].selector;
1821
1822         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1824         return *p;
1825 }
1826
1827 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         ulong *p = &vmx->segment_cache.seg[seg].base;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1833         return *p;
1834 }
1835
1836 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         u32 *p = &vmx->segment_cache.seg[seg].limit;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].ar;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1851         return *p;
1852 }
1853
1854 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1855 {
1856         u32 eb;
1857
1858         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1859              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1860         if ((vcpu->guest_debug &
1861              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863                 eb |= 1u << BP_VECTOR;
1864         if (to_vmx(vcpu)->rmode.vm86_active)
1865                 eb = ~0;
1866         if (enable_ept)
1867                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1868
1869         /* When we are running a nested L2 guest and L1 specified for it a
1870          * certain exception bitmap, we must trap the same exceptions and pass
1871          * them to L1. When running L2, we will only handle the exceptions
1872          * specified above if L1 did not want them.
1873          */
1874         if (is_guest_mode(vcpu))
1875                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1876
1877         vmcs_write32(EXCEPTION_BITMAP, eb);
1878 }
1879
1880 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1881                 unsigned long entry, unsigned long exit)
1882 {
1883         vm_entry_controls_clearbit(vmx, entry);
1884         vm_exit_controls_clearbit(vmx, exit);
1885 }
1886
1887 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1888 {
1889         unsigned i;
1890         struct msr_autoload *m = &vmx->msr_autoload;
1891
1892         switch (msr) {
1893         case MSR_EFER:
1894                 if (cpu_has_load_ia32_efer) {
1895                         clear_atomic_switch_msr_special(vmx,
1896                                         VM_ENTRY_LOAD_IA32_EFER,
1897                                         VM_EXIT_LOAD_IA32_EFER);
1898                         return;
1899                 }
1900                 break;
1901         case MSR_CORE_PERF_GLOBAL_CTRL:
1902                 if (cpu_has_load_perf_global_ctrl) {
1903                         clear_atomic_switch_msr_special(vmx,
1904                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1905                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1906                         return;
1907                 }
1908                 break;
1909         }
1910
1911         for (i = 0; i < m->nr; ++i)
1912                 if (m->guest[i].index == msr)
1913                         break;
1914
1915         if (i == m->nr)
1916                 return;
1917         --m->nr;
1918         m->guest[i] = m->guest[m->nr];
1919         m->host[i] = m->host[m->nr];
1920         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1921         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1922 }
1923
1924 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1925                 unsigned long entry, unsigned long exit,
1926                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1927                 u64 guest_val, u64 host_val)
1928 {
1929         vmcs_write64(guest_val_vmcs, guest_val);
1930         vmcs_write64(host_val_vmcs, host_val);
1931         vm_entry_controls_setbit(vmx, entry);
1932         vm_exit_controls_setbit(vmx, exit);
1933 }
1934
1935 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1936                                   u64 guest_val, u64 host_val)
1937 {
1938         unsigned i;
1939         struct msr_autoload *m = &vmx->msr_autoload;
1940
1941         switch (msr) {
1942         case MSR_EFER:
1943                 if (cpu_has_load_ia32_efer) {
1944                         add_atomic_switch_msr_special(vmx,
1945                                         VM_ENTRY_LOAD_IA32_EFER,
1946                                         VM_EXIT_LOAD_IA32_EFER,
1947                                         GUEST_IA32_EFER,
1948                                         HOST_IA32_EFER,
1949                                         guest_val, host_val);
1950                         return;
1951                 }
1952                 break;
1953         case MSR_CORE_PERF_GLOBAL_CTRL:
1954                 if (cpu_has_load_perf_global_ctrl) {
1955                         add_atomic_switch_msr_special(vmx,
1956                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1957                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1958                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1959                                         HOST_IA32_PERF_GLOBAL_CTRL,
1960                                         guest_val, host_val);
1961                         return;
1962                 }
1963                 break;
1964         case MSR_IA32_PEBS_ENABLE:
1965                 /* PEBS needs a quiescent period after being disabled (to write
1966                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1967                  * provide that period, so a CPU could write host's record into
1968                  * guest's memory.
1969                  */
1970                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1971         }
1972
1973         for (i = 0; i < m->nr; ++i)
1974                 if (m->guest[i].index == msr)
1975                         break;
1976
1977         if (i == NR_AUTOLOAD_MSRS) {
1978                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1979                                 "Can't add msr %x\n", msr);
1980                 return;
1981         } else if (i == m->nr) {
1982                 ++m->nr;
1983                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1984                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1985         }
1986
1987         m->guest[i].index = msr;
1988         m->guest[i].value = guest_val;
1989         m->host[i].index = msr;
1990         m->host[i].value = host_val;
1991 }
1992
1993 static void reload_tss(void)
1994 {
1995         /*
1996          * VT restores TR but not its size.  Useless.
1997          */
1998         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1999         struct desc_struct *descs;
2000
2001         descs = (void *)gdt->address;
2002         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
2003         load_TR_desc();
2004 }
2005
2006 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2007 {
2008         u64 guest_efer = vmx->vcpu.arch.efer;
2009         u64 ignore_bits = 0;
2010
2011         if (!enable_ept) {
2012                 /*
2013                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2014                  * host CPUID is more efficient than testing guest CPUID
2015                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2016                  */
2017                 if (boot_cpu_has(X86_FEATURE_SMEP))
2018                         guest_efer |= EFER_NX;
2019                 else if (!(guest_efer & EFER_NX))
2020                         ignore_bits |= EFER_NX;
2021         }
2022
2023         /*
2024          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2025          */
2026         ignore_bits |= EFER_SCE;
2027 #ifdef CONFIG_X86_64
2028         ignore_bits |= EFER_LMA | EFER_LME;
2029         /* SCE is meaningful only in long mode on Intel */
2030         if (guest_efer & EFER_LMA)
2031                 ignore_bits &= ~(u64)EFER_SCE;
2032 #endif
2033
2034         clear_atomic_switch_msr(vmx, MSR_EFER);
2035
2036         /*
2037          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2038          * On CPUs that support "load IA32_EFER", always switch EFER
2039          * atomically, since it's faster than switching it manually.
2040          */
2041         if (cpu_has_load_ia32_efer ||
2042             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2043                 if (!(guest_efer & EFER_LMA))
2044                         guest_efer &= ~EFER_LME;
2045                 if (guest_efer != host_efer)
2046                         add_atomic_switch_msr(vmx, MSR_EFER,
2047                                               guest_efer, host_efer);
2048                 return false;
2049         } else {
2050                 guest_efer &= ~ignore_bits;
2051                 guest_efer |= host_efer & ignore_bits;
2052
2053                 vmx->guest_msrs[efer_offset].data = guest_efer;
2054                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2055
2056                 return true;
2057         }
2058 }
2059
2060 #ifdef CONFIG_X86_32
2061 /*
2062  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2063  * VMCS rather than the segment table.  KVM uses this helper to figure
2064  * out the current bases to poke them into the VMCS before entry.
2065  */
2066 static unsigned long segment_base(u16 selector)
2067 {
2068         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2069         struct desc_struct *d;
2070         struct desc_struct *table;
2071         unsigned long v;
2072
2073         if (!(selector & ~SEGMENT_RPL_MASK))
2074                 return 0;
2075
2076         table = (struct desc_struct *)gdt->address;
2077
2078         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2079                 u16 ldt_selector = kvm_read_ldt();
2080
2081                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2082                         return 0;
2083
2084                 table = (struct desc_struct *)segment_base(ldt_selector);
2085         }
2086         v = get_desc_base(&table[selector >> 3]);
2087         return v;
2088 }
2089 #endif
2090
2091 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2092 {
2093         struct vcpu_vmx *vmx = to_vmx(vcpu);
2094         int i;
2095
2096         if (vmx->host_state.loaded)
2097                 return;
2098
2099         vmx->host_state.loaded = 1;
2100         /*
2101          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2102          * allow segment selectors with cpl > 0 or ti == 1.
2103          */
2104         vmx->host_state.ldt_sel = kvm_read_ldt();
2105         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2106         savesegment(fs, vmx->host_state.fs_sel);
2107         if (!(vmx->host_state.fs_sel & 7)) {
2108                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2109                 vmx->host_state.fs_reload_needed = 0;
2110         } else {
2111                 vmcs_write16(HOST_FS_SELECTOR, 0);
2112                 vmx->host_state.fs_reload_needed = 1;
2113         }
2114         savesegment(gs, vmx->host_state.gs_sel);
2115         if (!(vmx->host_state.gs_sel & 7))
2116                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2117         else {
2118                 vmcs_write16(HOST_GS_SELECTOR, 0);
2119                 vmx->host_state.gs_ldt_reload_needed = 1;
2120         }
2121
2122 #ifdef CONFIG_X86_64
2123         savesegment(ds, vmx->host_state.ds_sel);
2124         savesegment(es, vmx->host_state.es_sel);
2125 #endif
2126
2127 #ifdef CONFIG_X86_64
2128         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2129         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2130 #else
2131         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2132         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2133 #endif
2134
2135 #ifdef CONFIG_X86_64
2136         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2137         if (is_long_mode(&vmx->vcpu))
2138                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2139 #endif
2140         if (boot_cpu_has(X86_FEATURE_MPX))
2141                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2142         for (i = 0; i < vmx->save_nmsrs; ++i)
2143                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2144                                    vmx->guest_msrs[i].data,
2145                                    vmx->guest_msrs[i].mask);
2146 }
2147
2148 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2149 {
2150         if (!vmx->host_state.loaded)
2151                 return;
2152
2153         ++vmx->vcpu.stat.host_state_reload;
2154         vmx->host_state.loaded = 0;
2155 #ifdef CONFIG_X86_64
2156         if (is_long_mode(&vmx->vcpu))
2157                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2158 #endif
2159         if (vmx->host_state.gs_ldt_reload_needed) {
2160                 kvm_load_ldt(vmx->host_state.ldt_sel);
2161 #ifdef CONFIG_X86_64
2162                 load_gs_index(vmx->host_state.gs_sel);
2163 #else
2164                 loadsegment(gs, vmx->host_state.gs_sel);
2165 #endif
2166         }
2167         if (vmx->host_state.fs_reload_needed)
2168                 loadsegment(fs, vmx->host_state.fs_sel);
2169 #ifdef CONFIG_X86_64
2170         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2171                 loadsegment(ds, vmx->host_state.ds_sel);
2172                 loadsegment(es, vmx->host_state.es_sel);
2173         }
2174 #endif
2175         reload_tss();
2176 #ifdef CONFIG_X86_64
2177         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2178 #endif
2179         if (vmx->host_state.msr_host_bndcfgs)
2180                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2181         load_gdt(this_cpu_ptr(&host_gdt));
2182 }
2183
2184 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2185 {
2186         preempt_disable();
2187         __vmx_load_host_state(vmx);
2188         preempt_enable();
2189 }
2190
2191 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2192 {
2193         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2194         struct pi_desc old, new;
2195         unsigned int dest;
2196
2197         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2198                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2199                 !kvm_vcpu_apicv_active(vcpu))
2200                 return;
2201
2202         do {
2203                 old.control = new.control = pi_desc->control;
2204
2205                 /*
2206                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2207                  * are two possible cases:
2208                  * 1. After running 'pre_block', context switch
2209                  *    happened. For this case, 'sn' was set in
2210                  *    vmx_vcpu_put(), so we need to clear it here.
2211                  * 2. After running 'pre_block', we were blocked,
2212                  *    and woken up by some other guy. For this case,
2213                  *    we don't need to do anything, 'pi_post_block'
2214                  *    will do everything for us. However, we cannot
2215                  *    check whether it is case #1 or case #2 here
2216                  *    (maybe, not needed), so we also clear sn here,
2217                  *    I think it is not a big deal.
2218                  */
2219                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2220                         if (vcpu->cpu != cpu) {
2221                                 dest = cpu_physical_id(cpu);
2222
2223                                 if (x2apic_enabled())
2224                                         new.ndst = dest;
2225                                 else
2226                                         new.ndst = (dest << 8) & 0xFF00;
2227                         }
2228
2229                         /* set 'NV' to 'notification vector' */
2230                         new.nv = POSTED_INTR_VECTOR;
2231                 }
2232
2233                 /* Allow posting non-urgent interrupts */
2234                 new.sn = 0;
2235         } while (cmpxchg(&pi_desc->control, old.control,
2236                         new.control) != old.control);
2237 }
2238
2239 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2240 {
2241         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2242         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2243 }
2244
2245 /*
2246  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2247  * vcpu mutex is already taken.
2248  */
2249 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2250 {
2251         struct vcpu_vmx *vmx = to_vmx(vcpu);
2252         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2253         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2254
2255         if (!vmm_exclusive)
2256                 kvm_cpu_vmxon(phys_addr);
2257         else if (!already_loaded)
2258                 loaded_vmcs_clear(vmx->loaded_vmcs);
2259
2260         if (!already_loaded) {
2261                 local_irq_disable();
2262                 crash_disable_local_vmclear(cpu);
2263
2264                 /*
2265                  * Read loaded_vmcs->cpu should be before fetching
2266                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2267                  * See the comments in __loaded_vmcs_clear().
2268                  */
2269                 smp_rmb();
2270
2271                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2272                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2273                 crash_enable_local_vmclear(cpu);
2274                 local_irq_enable();
2275         }
2276
2277         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2278                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2279                 vmcs_load(vmx->loaded_vmcs->vmcs);
2280         }
2281
2282         if (!already_loaded) {
2283                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2284                 unsigned long sysenter_esp;
2285
2286                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2287
2288                 /*
2289                  * Linux uses per-cpu TSS and GDT, so set these when switching
2290                  * processors.  See 22.2.4.
2291                  */
2292                 vmcs_writel(HOST_TR_BASE,
2293                             (unsigned long)this_cpu_ptr(&cpu_tss));
2294                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2295
2296                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2297                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2298
2299                 vmx->loaded_vmcs->cpu = cpu;
2300         }
2301
2302         /* Setup TSC multiplier */
2303         if (kvm_has_tsc_control &&
2304             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2305                 decache_tsc_multiplier(vmx);
2306
2307         vmx_vcpu_pi_load(vcpu, cpu);
2308         vmx->host_pkru = read_pkru();
2309 }
2310
2311 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2312 {
2313         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2314
2315         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2316                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2317                 !kvm_vcpu_apicv_active(vcpu))
2318                 return;
2319
2320         /* Set SN when the vCPU is preempted */
2321         if (vcpu->preempted)
2322                 pi_set_sn(pi_desc);
2323 }
2324
2325 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2326 {
2327         vmx_vcpu_pi_put(vcpu);
2328
2329         __vmx_load_host_state(to_vmx(vcpu));
2330         if (!vmm_exclusive) {
2331                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2332                 vcpu->cpu = -1;
2333                 kvm_cpu_vmxoff();
2334         }
2335 }
2336
2337 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2338
2339 /*
2340  * Return the cr0 value that a nested guest would read. This is a combination
2341  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2342  * its hypervisor (cr0_read_shadow).
2343  */
2344 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2345 {
2346         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2347                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2348 }
2349 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2350 {
2351         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2352                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2353 }
2354
2355 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2356 {
2357         unsigned long rflags, save_rflags;
2358
2359         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2360                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2361                 rflags = vmcs_readl(GUEST_RFLAGS);
2362                 if (to_vmx(vcpu)->rmode.vm86_active) {
2363                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2364                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2365                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2366                 }
2367                 to_vmx(vcpu)->rflags = rflags;
2368         }
2369         return to_vmx(vcpu)->rflags;
2370 }
2371
2372 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2373 {
2374         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2375         to_vmx(vcpu)->rflags = rflags;
2376         if (to_vmx(vcpu)->rmode.vm86_active) {
2377                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2378                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2379         }
2380         vmcs_writel(GUEST_RFLAGS, rflags);
2381 }
2382
2383 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2384 {
2385         return to_vmx(vcpu)->guest_pkru;
2386 }
2387
2388 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2389 {
2390         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2391         int ret = 0;
2392
2393         if (interruptibility & GUEST_INTR_STATE_STI)
2394                 ret |= KVM_X86_SHADOW_INT_STI;
2395         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2396                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2397
2398         return ret;
2399 }
2400
2401 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2402 {
2403         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2404         u32 interruptibility = interruptibility_old;
2405
2406         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2407
2408         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2409                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2410         else if (mask & KVM_X86_SHADOW_INT_STI)
2411                 interruptibility |= GUEST_INTR_STATE_STI;
2412
2413         if ((interruptibility != interruptibility_old))
2414                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2415 }
2416
2417 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2418 {
2419         unsigned long rip;
2420
2421         rip = kvm_rip_read(vcpu);
2422         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2423         kvm_rip_write(vcpu, rip);
2424
2425         /* skipping an emulated instruction also counts */
2426         vmx_set_interrupt_shadow(vcpu, 0);
2427 }
2428
2429 /*
2430  * KVM wants to inject page-faults which it got to the guest. This function
2431  * checks whether in a nested guest, we need to inject them to L1 or L2.
2432  */
2433 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2434 {
2435         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2436
2437         if (!(vmcs12->exception_bitmap & (1u << nr)))
2438                 return 0;
2439
2440         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2441                           vmcs_read32(VM_EXIT_INTR_INFO),
2442                           vmcs_readl(EXIT_QUALIFICATION));
2443         return 1;
2444 }
2445
2446 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2447                                 bool has_error_code, u32 error_code,
2448                                 bool reinject)
2449 {
2450         struct vcpu_vmx *vmx = to_vmx(vcpu);
2451         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2452
2453         if (!reinject && is_guest_mode(vcpu) &&
2454             nested_vmx_check_exception(vcpu, nr))
2455                 return;
2456
2457         if (has_error_code) {
2458                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2459                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2460         }
2461
2462         if (vmx->rmode.vm86_active) {
2463                 int inc_eip = 0;
2464                 if (kvm_exception_is_soft(nr))
2465                         inc_eip = vcpu->arch.event_exit_inst_len;
2466                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2467                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2468                 return;
2469         }
2470
2471         if (kvm_exception_is_soft(nr)) {
2472                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2473                              vmx->vcpu.arch.event_exit_inst_len);
2474                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2475         } else
2476                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2477
2478         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2479 }
2480
2481 static bool vmx_rdtscp_supported(void)
2482 {
2483         return cpu_has_vmx_rdtscp();
2484 }
2485
2486 static bool vmx_invpcid_supported(void)
2487 {
2488         return cpu_has_vmx_invpcid() && enable_ept;
2489 }
2490
2491 /*
2492  * Swap MSR entry in host/guest MSR entry array.
2493  */
2494 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2495 {
2496         struct shared_msr_entry tmp;
2497
2498         tmp = vmx->guest_msrs[to];
2499         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2500         vmx->guest_msrs[from] = tmp;
2501 }
2502
2503 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2504 {
2505         unsigned long *msr_bitmap;
2506
2507         if (is_guest_mode(vcpu))
2508                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2509         else if (cpu_has_secondary_exec_ctrls() &&
2510                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2511                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2512                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2513                         if (is_long_mode(vcpu))
2514                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2515                         else
2516                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2517                 } else {
2518                         if (is_long_mode(vcpu))
2519                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2520                         else
2521                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2522                 }
2523         } else {
2524                 if (is_long_mode(vcpu))
2525                         msr_bitmap = vmx_msr_bitmap_longmode;
2526                 else
2527                         msr_bitmap = vmx_msr_bitmap_legacy;
2528         }
2529
2530         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2531 }
2532
2533 /*
2534  * Set up the vmcs to automatically save and restore system
2535  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2536  * mode, as fiddling with msrs is very expensive.
2537  */
2538 static void setup_msrs(struct vcpu_vmx *vmx)
2539 {
2540         int save_nmsrs, index;
2541
2542         save_nmsrs = 0;
2543 #ifdef CONFIG_X86_64
2544         if (is_long_mode(&vmx->vcpu)) {
2545                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2546                 if (index >= 0)
2547                         move_msr_up(vmx, index, save_nmsrs++);
2548                 index = __find_msr_index(vmx, MSR_LSTAR);
2549                 if (index >= 0)
2550                         move_msr_up(vmx, index, save_nmsrs++);
2551                 index = __find_msr_index(vmx, MSR_CSTAR);
2552                 if (index >= 0)
2553                         move_msr_up(vmx, index, save_nmsrs++);
2554                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2555                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2556                         move_msr_up(vmx, index, save_nmsrs++);
2557                 /*
2558                  * MSR_STAR is only needed on long mode guests, and only
2559                  * if efer.sce is enabled.
2560                  */
2561                 index = __find_msr_index(vmx, MSR_STAR);
2562                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2563                         move_msr_up(vmx, index, save_nmsrs++);
2564         }
2565 #endif
2566         index = __find_msr_index(vmx, MSR_EFER);
2567         if (index >= 0 && update_transition_efer(vmx, index))
2568                 move_msr_up(vmx, index, save_nmsrs++);
2569
2570         vmx->save_nmsrs = save_nmsrs;
2571
2572         if (cpu_has_vmx_msr_bitmap())
2573                 vmx_set_msr_bitmap(&vmx->vcpu);
2574 }
2575
2576 /*
2577  * reads and returns guest's timestamp counter "register"
2578  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2579  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2580  */
2581 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2582 {
2583         u64 host_tsc, tsc_offset;
2584
2585         host_tsc = rdtsc();
2586         tsc_offset = vmcs_read64(TSC_OFFSET);
2587         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2588 }
2589
2590 /*
2591  * writes 'offset' into guest's timestamp counter offset register
2592  */
2593 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2594 {
2595         if (is_guest_mode(vcpu)) {
2596                 /*
2597                  * We're here if L1 chose not to trap WRMSR to TSC. According
2598                  * to the spec, this should set L1's TSC; The offset that L1
2599                  * set for L2 remains unchanged, and still needs to be added
2600                  * to the newly set TSC to get L2's TSC.
2601                  */
2602                 struct vmcs12 *vmcs12;
2603                 /* recalculate vmcs02.TSC_OFFSET: */
2604                 vmcs12 = get_vmcs12(vcpu);
2605                 vmcs_write64(TSC_OFFSET, offset +
2606                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2607                          vmcs12->tsc_offset : 0));
2608         } else {
2609                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2610                                            vmcs_read64(TSC_OFFSET), offset);
2611                 vmcs_write64(TSC_OFFSET, offset);
2612         }
2613 }
2614
2615 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2616 {
2617         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2618         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2619 }
2620
2621 /*
2622  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2623  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2624  * all guests if the "nested" module option is off, and can also be disabled
2625  * for a single guest by disabling its VMX cpuid bit.
2626  */
2627 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2628 {
2629         return nested && guest_cpuid_has_vmx(vcpu);
2630 }
2631
2632 /*
2633  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2634  * returned for the various VMX controls MSRs when nested VMX is enabled.
2635  * The same values should also be used to verify that vmcs12 control fields are
2636  * valid during nested entry from L1 to L2.
2637  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2638  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2639  * bit in the high half is on if the corresponding bit in the control field
2640  * may be on. See also vmx_control_verify().
2641  */
2642 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2643 {
2644         /*
2645          * Note that as a general rule, the high half of the MSRs (bits in
2646          * the control fields which may be 1) should be initialized by the
2647          * intersection of the underlying hardware's MSR (i.e., features which
2648          * can be supported) and the list of features we want to expose -
2649          * because they are known to be properly supported in our code.
2650          * Also, usually, the low half of the MSRs (bits which must be 1) can
2651          * be set to 0, meaning that L1 may turn off any of these bits. The
2652          * reason is that if one of these bits is necessary, it will appear
2653          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2654          * fields of vmcs01 and vmcs02, will turn these bits off - and
2655          * nested_vmx_exit_handled() will not pass related exits to L1.
2656          * These rules have exceptions below.
2657          */
2658
2659         /* pin-based controls */
2660         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2661                 vmx->nested.nested_vmx_pinbased_ctls_low,
2662                 vmx->nested.nested_vmx_pinbased_ctls_high);
2663         vmx->nested.nested_vmx_pinbased_ctls_low |=
2664                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2665         vmx->nested.nested_vmx_pinbased_ctls_high &=
2666                 PIN_BASED_EXT_INTR_MASK |
2667                 PIN_BASED_NMI_EXITING |
2668                 PIN_BASED_VIRTUAL_NMIS;
2669         vmx->nested.nested_vmx_pinbased_ctls_high |=
2670                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2671                 PIN_BASED_VMX_PREEMPTION_TIMER;
2672         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2673                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2674                         PIN_BASED_POSTED_INTR;
2675
2676         /* exit controls */
2677         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2678                 vmx->nested.nested_vmx_exit_ctls_low,
2679                 vmx->nested.nested_vmx_exit_ctls_high);
2680         vmx->nested.nested_vmx_exit_ctls_low =
2681                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2682
2683         vmx->nested.nested_vmx_exit_ctls_high &=
2684 #ifdef CONFIG_X86_64
2685                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2686 #endif
2687                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2688         vmx->nested.nested_vmx_exit_ctls_high |=
2689                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2690                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2691                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2692
2693         if (kvm_mpx_supported())
2694                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2695
2696         /* We support free control of debug control saving. */
2697         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2698
2699         /* entry controls */
2700         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2701                 vmx->nested.nested_vmx_entry_ctls_low,
2702                 vmx->nested.nested_vmx_entry_ctls_high);
2703         vmx->nested.nested_vmx_entry_ctls_low =
2704                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2705         vmx->nested.nested_vmx_entry_ctls_high &=
2706 #ifdef CONFIG_X86_64
2707                 VM_ENTRY_IA32E_MODE |
2708 #endif
2709                 VM_ENTRY_LOAD_IA32_PAT;
2710         vmx->nested.nested_vmx_entry_ctls_high |=
2711                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2712         if (kvm_mpx_supported())
2713                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2714
2715         /* We support free control of debug control loading. */
2716         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2717
2718         /* cpu-based controls */
2719         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2720                 vmx->nested.nested_vmx_procbased_ctls_low,
2721                 vmx->nested.nested_vmx_procbased_ctls_high);
2722         vmx->nested.nested_vmx_procbased_ctls_low =
2723                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2724         vmx->nested.nested_vmx_procbased_ctls_high &=
2725                 CPU_BASED_VIRTUAL_INTR_PENDING |
2726                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2727                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2728                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2729                 CPU_BASED_CR3_STORE_EXITING |
2730 #ifdef CONFIG_X86_64
2731                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2732 #endif
2733                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2734                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2735                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2736                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2737                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2738         /*
2739          * We can allow some features even when not supported by the
2740          * hardware. For example, L1 can specify an MSR bitmap - and we
2741          * can use it to avoid exits to L1 - even when L0 runs L2
2742          * without MSR bitmaps.
2743          */
2744         vmx->nested.nested_vmx_procbased_ctls_high |=
2745                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2746                 CPU_BASED_USE_MSR_BITMAPS;
2747
2748         /* We support free control of CR3 access interception. */
2749         vmx->nested.nested_vmx_procbased_ctls_low &=
2750                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2751
2752         /* secondary cpu-based controls */
2753         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2754                 vmx->nested.nested_vmx_secondary_ctls_low,
2755                 vmx->nested.nested_vmx_secondary_ctls_high);
2756         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2757         vmx->nested.nested_vmx_secondary_ctls_high &=
2758                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2759                 SECONDARY_EXEC_RDTSCP |
2760                 SECONDARY_EXEC_DESC |
2761                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2762                 SECONDARY_EXEC_ENABLE_VPID |
2763                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2764                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2765                 SECONDARY_EXEC_WBINVD_EXITING |
2766                 SECONDARY_EXEC_XSAVES;
2767
2768         if (enable_ept) {
2769                 /* nested EPT: emulate EPT also to L1 */
2770                 vmx->nested.nested_vmx_secondary_ctls_high |=
2771                         SECONDARY_EXEC_ENABLE_EPT;
2772                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2773                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2774                          VMX_EPT_INVEPT_BIT;
2775                 if (cpu_has_vmx_ept_execute_only())
2776                         vmx->nested.nested_vmx_ept_caps |=
2777                                 VMX_EPT_EXECUTE_ONLY_BIT;
2778                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2779                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2780                         VMX_EPT_EXTENT_CONTEXT_BIT;
2781         } else
2782                 vmx->nested.nested_vmx_ept_caps = 0;
2783
2784         /*
2785          * Old versions of KVM use the single-context version without
2786          * checking for support, so declare that it is supported even
2787          * though it is treated as global context.  The alternative is
2788          * not failing the single-context invvpid, and it is worse.
2789          */
2790         if (enable_vpid)
2791                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2792                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2793         else
2794                 vmx->nested.nested_vmx_vpid_caps = 0;
2795
2796         if (enable_unrestricted_guest)
2797                 vmx->nested.nested_vmx_secondary_ctls_high |=
2798                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2799
2800         /* miscellaneous data */
2801         rdmsr(MSR_IA32_VMX_MISC,
2802                 vmx->nested.nested_vmx_misc_low,
2803                 vmx->nested.nested_vmx_misc_high);
2804         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2805         vmx->nested.nested_vmx_misc_low |=
2806                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2807                 VMX_MISC_ACTIVITY_HLT;
2808         vmx->nested.nested_vmx_misc_high = 0;
2809
2810         /*
2811          * This MSR reports some information about VMX support. We
2812          * should return information about the VMX we emulate for the
2813          * guest, and the VMCS structure we give it - not about the
2814          * VMX support of the underlying hardware.
2815          */
2816         vmx->nested.nested_vmx_basic =
2817                 VMCS12_REVISION |
2818                 VMX_BASIC_TRUE_CTLS |
2819                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2820                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2821
2822         if (cpu_has_vmx_basic_inout())
2823                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2824
2825         /*
2826          * These MSRs specify bits which the guest must keep fixed on
2827          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2828          * We picked the standard core2 setting.
2829          */
2830 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2831 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2832         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2833         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2834
2835         /* These MSRs specify bits which the guest must keep fixed off. */
2836         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2837         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2838
2839         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2840         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2841 }
2842
2843 /*
2844  * if fixed0[i] == 1: val[i] must be 1
2845  * if fixed1[i] == 0: val[i] must be 0
2846  */
2847 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2848 {
2849         return ((val & fixed1) | fixed0) == val;
2850 }
2851
2852 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2853 {
2854         return fixed_bits_valid(control, low, high);
2855 }
2856
2857 static inline u64 vmx_control_msr(u32 low, u32 high)
2858 {
2859         return low | ((u64)high << 32);
2860 }
2861
2862 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2863 {
2864         superset &= mask;
2865         subset &= mask;
2866
2867         return (superset | subset) == superset;
2868 }
2869
2870 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2871 {
2872         const u64 feature_and_reserved =
2873                 /* feature (except bit 48; see below) */
2874                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2875                 /* reserved */
2876                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2877         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2878
2879         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2880                 return -EINVAL;
2881
2882         /*
2883          * KVM does not emulate a version of VMX that constrains physical
2884          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2885          */
2886         if (data & BIT_ULL(48))
2887                 return -EINVAL;
2888
2889         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2890             vmx_basic_vmcs_revision_id(data))
2891                 return -EINVAL;
2892
2893         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2894                 return -EINVAL;
2895
2896         vmx->nested.nested_vmx_basic = data;
2897         return 0;
2898 }
2899
2900 static int
2901 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2902 {
2903         u64 supported;
2904         u32 *lowp, *highp;
2905
2906         switch (msr_index) {
2907         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2908                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2909                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2910                 break;
2911         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2912                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2913                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2914                 break;
2915         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2916                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2917                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2918                 break;
2919         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2920                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2921                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2922                 break;
2923         case MSR_IA32_VMX_PROCBASED_CTLS2:
2924                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2925                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2926                 break;
2927         default:
2928                 BUG();
2929         }
2930
2931         supported = vmx_control_msr(*lowp, *highp);
2932
2933         /* Check must-be-1 bits are still 1. */
2934         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2935                 return -EINVAL;
2936
2937         /* Check must-be-0 bits are still 0. */
2938         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2939                 return -EINVAL;
2940
2941         *lowp = data;
2942         *highp = data >> 32;
2943         return 0;
2944 }
2945
2946 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2947 {
2948         const u64 feature_and_reserved_bits =
2949                 /* feature */
2950                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2951                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2952                 /* reserved */
2953                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2954         u64 vmx_misc;
2955
2956         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2957                                    vmx->nested.nested_vmx_misc_high);
2958
2959         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2960                 return -EINVAL;
2961
2962         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2963              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2964             vmx_misc_preemption_timer_rate(data) !=
2965             vmx_misc_preemption_timer_rate(vmx_misc))
2966                 return -EINVAL;
2967
2968         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2969                 return -EINVAL;
2970
2971         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2972                 return -EINVAL;
2973
2974         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2975                 return -EINVAL;
2976
2977         vmx->nested.nested_vmx_misc_low = data;
2978         vmx->nested.nested_vmx_misc_high = data >> 32;
2979         return 0;
2980 }
2981
2982 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2983 {
2984         u64 vmx_ept_vpid_cap;
2985
2986         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2987                                            vmx->nested.nested_vmx_vpid_caps);
2988
2989         /* Every bit is either reserved or a feature bit. */
2990         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2991                 return -EINVAL;
2992
2993         vmx->nested.nested_vmx_ept_caps = data;
2994         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2995         return 0;
2996 }
2997
2998 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2999 {
3000         u64 *msr;
3001
3002         switch (msr_index) {
3003         case MSR_IA32_VMX_CR0_FIXED0:
3004                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3005                 break;
3006         case MSR_IA32_VMX_CR4_FIXED0:
3007                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3008                 break;
3009         default:
3010                 BUG();
3011         }
3012
3013         /*
3014          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3015          * must be 1 in the restored value.
3016          */
3017         if (!is_bitwise_subset(data, *msr, -1ULL))
3018                 return -EINVAL;
3019
3020         *msr = data;
3021         return 0;
3022 }
3023
3024 /*
3025  * Called when userspace is restoring VMX MSRs.
3026  *
3027  * Returns 0 on success, non-0 otherwise.
3028  */
3029 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3030 {
3031         struct vcpu_vmx *vmx = to_vmx(vcpu);
3032
3033         switch (msr_index) {
3034         case MSR_IA32_VMX_BASIC:
3035                 return vmx_restore_vmx_basic(vmx, data);
3036         case MSR_IA32_VMX_PINBASED_CTLS:
3037         case MSR_IA32_VMX_PROCBASED_CTLS:
3038         case MSR_IA32_VMX_EXIT_CTLS:
3039         case MSR_IA32_VMX_ENTRY_CTLS:
3040                 /*
3041                  * The "non-true" VMX capability MSRs are generated from the
3042                  * "true" MSRs, so we do not support restoring them directly.
3043                  *
3044                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3045                  * should restore the "true" MSRs with the must-be-1 bits
3046                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3047                  * DEFAULT SETTINGS".
3048                  */
3049                 return -EINVAL;
3050         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3051         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3052         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3053         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3054         case MSR_IA32_VMX_PROCBASED_CTLS2:
3055                 return vmx_restore_control_msr(vmx, msr_index, data);
3056         case MSR_IA32_VMX_MISC:
3057                 return vmx_restore_vmx_misc(vmx, data);
3058         case MSR_IA32_VMX_CR0_FIXED0:
3059         case MSR_IA32_VMX_CR4_FIXED0:
3060                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3061         case MSR_IA32_VMX_CR0_FIXED1:
3062         case MSR_IA32_VMX_CR4_FIXED1:
3063                 /*
3064                  * These MSRs are generated based on the vCPU's CPUID, so we
3065                  * do not support restoring them directly.
3066                  */
3067                 return -EINVAL;
3068         case MSR_IA32_VMX_EPT_VPID_CAP:
3069                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3070         case MSR_IA32_VMX_VMCS_ENUM:
3071                 vmx->nested.nested_vmx_vmcs_enum = data;
3072                 return 0;
3073         default:
3074                 /*
3075                  * The rest of the VMX capability MSRs do not support restore.
3076                  */
3077                 return -EINVAL;
3078         }
3079 }
3080
3081 /* Returns 0 on success, non-0 otherwise. */
3082 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3083 {
3084         struct vcpu_vmx *vmx = to_vmx(vcpu);
3085
3086         switch (msr_index) {
3087         case MSR_IA32_VMX_BASIC:
3088                 *pdata = vmx->nested.nested_vmx_basic;
3089                 break;
3090         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3091         case MSR_IA32_VMX_PINBASED_CTLS:
3092                 *pdata = vmx_control_msr(
3093                         vmx->nested.nested_vmx_pinbased_ctls_low,
3094                         vmx->nested.nested_vmx_pinbased_ctls_high);
3095                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3096                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3097                 break;
3098         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3099         case MSR_IA32_VMX_PROCBASED_CTLS:
3100                 *pdata = vmx_control_msr(
3101                         vmx->nested.nested_vmx_procbased_ctls_low,
3102                         vmx->nested.nested_vmx_procbased_ctls_high);
3103                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3104                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3105                 break;
3106         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3107         case MSR_IA32_VMX_EXIT_CTLS:
3108                 *pdata = vmx_control_msr(
3109                         vmx->nested.nested_vmx_exit_ctls_low,
3110                         vmx->nested.nested_vmx_exit_ctls_high);
3111                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3112                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3113                 break;
3114         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3115         case MSR_IA32_VMX_ENTRY_CTLS:
3116                 *pdata = vmx_control_msr(
3117                         vmx->nested.nested_vmx_entry_ctls_low,
3118                         vmx->nested.nested_vmx_entry_ctls_high);
3119                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3120                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3121                 break;
3122         case MSR_IA32_VMX_MISC:
3123                 *pdata = vmx_control_msr(
3124                         vmx->nested.nested_vmx_misc_low,
3125                         vmx->nested.nested_vmx_misc_high);
3126                 break;
3127         case MSR_IA32_VMX_CR0_FIXED0:
3128                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3129                 break;
3130         case MSR_IA32_VMX_CR0_FIXED1:
3131                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3132                 break;
3133         case MSR_IA32_VMX_CR4_FIXED0:
3134                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3135                 break;
3136         case MSR_IA32_VMX_CR4_FIXED1:
3137                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3138                 break;
3139         case MSR_IA32_VMX_VMCS_ENUM:
3140                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3141                 break;
3142         case MSR_IA32_VMX_PROCBASED_CTLS2:
3143                 *pdata = vmx_control_msr(
3144                         vmx->nested.nested_vmx_secondary_ctls_low,
3145                         vmx->nested.nested_vmx_secondary_ctls_high);
3146                 break;
3147         case MSR_IA32_VMX_EPT_VPID_CAP:
3148                 *pdata = vmx->nested.nested_vmx_ept_caps |
3149                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3150                 break;
3151         default:
3152                 return 1;
3153         }
3154
3155         return 0;
3156 }
3157
3158 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3159                                                  uint64_t val)
3160 {
3161         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3162
3163         return !(val & ~valid_bits);
3164 }
3165
3166 /*
3167  * Reads an msr value (of 'msr_index') into 'pdata'.
3168  * Returns 0 on success, non-0 otherwise.
3169  * Assumes vcpu_load() was already called.
3170  */
3171 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3172 {
3173         struct shared_msr_entry *msr;
3174
3175         switch (msr_info->index) {
3176 #ifdef CONFIG_X86_64
3177         case MSR_FS_BASE:
3178                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3179                 break;
3180         case MSR_GS_BASE:
3181                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3182                 break;
3183         case MSR_KERNEL_GS_BASE:
3184                 vmx_load_host_state(to_vmx(vcpu));
3185                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3186                 break;
3187 #endif
3188         case MSR_EFER:
3189                 return kvm_get_msr_common(vcpu, msr_info);
3190         case MSR_IA32_TSC:
3191                 msr_info->data = guest_read_tsc(vcpu);
3192                 break;
3193         case MSR_IA32_SYSENTER_CS:
3194                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3195                 break;
3196         case MSR_IA32_SYSENTER_EIP:
3197                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3198                 break;
3199         case MSR_IA32_SYSENTER_ESP:
3200                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3201                 break;
3202         case MSR_IA32_BNDCFGS:
3203                 if (!kvm_mpx_supported())
3204                         return 1;
3205                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3206                 break;
3207         case MSR_IA32_MCG_EXT_CTL:
3208                 if (!msr_info->host_initiated &&
3209                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3210                       FEATURE_CONTROL_LMCE))
3211                         return 1;
3212                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3213                 break;
3214         case MSR_IA32_FEATURE_CONTROL:
3215                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3216                 break;
3217         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3218                 if (!nested_vmx_allowed(vcpu))
3219                         return 1;
3220                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3221         case MSR_IA32_XSS:
3222                 if (!vmx_xsaves_supported())
3223                         return 1;
3224                 msr_info->data = vcpu->arch.ia32_xss;
3225                 break;
3226         case MSR_TSC_AUX:
3227                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3228                         return 1;
3229                 /* Otherwise falls through */
3230         default:
3231                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3232                 if (msr) {
3233                         msr_info->data = msr->data;
3234                         break;
3235                 }
3236                 return kvm_get_msr_common(vcpu, msr_info);
3237         }
3238
3239         return 0;
3240 }
3241
3242 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3243
3244 /*
3245  * Writes msr value into into the appropriate "register".
3246  * Returns 0 on success, non-0 otherwise.
3247  * Assumes vcpu_load() was already called.
3248  */
3249 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3250 {
3251         struct vcpu_vmx *vmx = to_vmx(vcpu);
3252         struct shared_msr_entry *msr;
3253         int ret = 0;
3254         u32 msr_index = msr_info->index;
3255         u64 data = msr_info->data;
3256
3257         switch (msr_index) {
3258         case MSR_EFER:
3259                 ret = kvm_set_msr_common(vcpu, msr_info);
3260                 break;
3261 #ifdef CONFIG_X86_64
3262         case MSR_FS_BASE:
3263                 vmx_segment_cache_clear(vmx);
3264                 vmcs_writel(GUEST_FS_BASE, data);
3265                 break;
3266         case MSR_GS_BASE:
3267                 vmx_segment_cache_clear(vmx);
3268                 vmcs_writel(GUEST_GS_BASE, data);
3269                 break;
3270         case MSR_KERNEL_GS_BASE:
3271                 vmx_load_host_state(vmx);
3272                 vmx->msr_guest_kernel_gs_base = data;
3273                 break;
3274 #endif
3275         case MSR_IA32_SYSENTER_CS:
3276                 vmcs_write32(GUEST_SYSENTER_CS, data);
3277                 break;
3278         case MSR_IA32_SYSENTER_EIP:
3279                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3280                 break;
3281         case MSR_IA32_SYSENTER_ESP:
3282                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3283                 break;
3284         case MSR_IA32_BNDCFGS:
3285                 if (!kvm_mpx_supported())
3286                         return 1;
3287                 vmcs_write64(GUEST_BNDCFGS, data);
3288                 break;
3289         case MSR_IA32_TSC:
3290                 kvm_write_tsc(vcpu, msr_info);
3291                 break;
3292         case MSR_IA32_CR_PAT:
3293                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3294                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3295                                 return 1;
3296                         vmcs_write64(GUEST_IA32_PAT, data);
3297                         vcpu->arch.pat = data;
3298                         break;
3299                 }
3300                 ret = kvm_set_msr_common(vcpu, msr_info);
3301                 break;
3302         case MSR_IA32_TSC_ADJUST:
3303                 ret = kvm_set_msr_common(vcpu, msr_info);
3304                 break;
3305         case MSR_IA32_MCG_EXT_CTL:
3306                 if ((!msr_info->host_initiated &&
3307                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3308                        FEATURE_CONTROL_LMCE)) ||
3309                     (data & ~MCG_EXT_CTL_LMCE_EN))
3310                         return 1;
3311                 vcpu->arch.mcg_ext_ctl = data;
3312                 break;
3313         case MSR_IA32_FEATURE_CONTROL:
3314                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3315                     (to_vmx(vcpu)->msr_ia32_feature_control &
3316                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3317                         return 1;
3318                 vmx->msr_ia32_feature_control = data;
3319                 if (msr_info->host_initiated && data == 0)
3320                         vmx_leave_nested(vcpu);
3321                 break;
3322         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3323                 if (!msr_info->host_initiated)
3324                         return 1; /* they are read-only */
3325                 if (!nested_vmx_allowed(vcpu))
3326                         return 1;
3327                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3328         case MSR_IA32_XSS:
3329                 if (!vmx_xsaves_supported())
3330                         return 1;
3331                 /*
3332                  * The only supported bit as of Skylake is bit 8, but
3333                  * it is not supported on KVM.
3334                  */
3335                 if (data != 0)
3336                         return 1;
3337                 vcpu->arch.ia32_xss = data;
3338                 if (vcpu->arch.ia32_xss != host_xss)
3339                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3340                                 vcpu->arch.ia32_xss, host_xss);
3341                 else
3342                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3343                 break;
3344         case MSR_TSC_AUX:
3345                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3346                         return 1;
3347                 /* Check reserved bit, higher 32 bits should be zero */
3348                 if ((data >> 32) != 0)
3349                         return 1;
3350                 /* Otherwise falls through */
3351         default:
3352                 msr = find_msr_entry(vmx, msr_index);
3353                 if (msr) {
3354                         u64 old_msr_data = msr->data;
3355                         msr->data = data;
3356                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3357                                 preempt_disable();
3358                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3359                                                          msr->mask);
3360                                 preempt_enable();
3361                                 if (ret)
3362                                         msr->data = old_msr_data;
3363                         }
3364                         break;
3365                 }
3366                 ret = kvm_set_msr_common(vcpu, msr_info);
3367         }
3368
3369         return ret;
3370 }
3371
3372 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3373 {
3374         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3375         switch (reg) {
3376         case VCPU_REGS_RSP:
3377                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3378                 break;
3379         case VCPU_REGS_RIP:
3380                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3381                 break;
3382         case VCPU_EXREG_PDPTR:
3383                 if (enable_ept)
3384                         ept_save_pdptrs(vcpu);
3385                 break;
3386         default:
3387                 break;
3388         }
3389 }
3390
3391 static __init int cpu_has_kvm_support(void)
3392 {
3393         return cpu_has_vmx();
3394 }
3395
3396 static __init int vmx_disabled_by_bios(void)
3397 {
3398         u64 msr;
3399
3400         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3401         if (msr & FEATURE_CONTROL_LOCKED) {
3402                 /* launched w/ TXT and VMX disabled */
3403                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3404                         && tboot_enabled())
3405                         return 1;
3406                 /* launched w/o TXT and VMX only enabled w/ TXT */
3407                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3408                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3409                         && !tboot_enabled()) {
3410                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3411                                 "activate TXT before enabling KVM\n");
3412                         return 1;
3413                 }
3414                 /* launched w/o TXT and VMX disabled */
3415                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3416                         && !tboot_enabled())
3417                         return 1;
3418         }
3419
3420         return 0;
3421 }
3422
3423 static void kvm_cpu_vmxon(u64 addr)
3424 {
3425         intel_pt_handle_vmx(1);
3426
3427         asm volatile (ASM_VMX_VMXON_RAX
3428                         : : "a"(&addr), "m"(addr)
3429                         : "memory", "cc");
3430 }
3431
3432 static int hardware_enable(void)
3433 {
3434         int cpu = raw_smp_processor_id();
3435         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3436         u64 old, test_bits;
3437
3438         if (cr4_read_shadow() & X86_CR4_VMXE)
3439                 return -EBUSY;
3440
3441         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3442         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3443         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3444
3445         /*
3446          * Now we can enable the vmclear operation in kdump
3447          * since the loaded_vmcss_on_cpu list on this cpu
3448          * has been initialized.
3449          *
3450          * Though the cpu is not in VMX operation now, there
3451          * is no problem to enable the vmclear operation
3452          * for the loaded_vmcss_on_cpu list is empty!
3453          */
3454         crash_enable_local_vmclear(cpu);
3455
3456         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3457
3458         test_bits = FEATURE_CONTROL_LOCKED;
3459         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3460         if (tboot_enabled())
3461                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3462
3463         if ((old & test_bits) != test_bits) {
3464                 /* enable and lock */
3465                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3466         }
3467         cr4_set_bits(X86_CR4_VMXE);
3468
3469         if (vmm_exclusive) {
3470                 kvm_cpu_vmxon(phys_addr);
3471                 ept_sync_global();
3472         }
3473
3474         native_store_gdt(this_cpu_ptr(&host_gdt));
3475
3476         return 0;
3477 }
3478
3479 static void vmclear_local_loaded_vmcss(void)
3480 {
3481         int cpu = raw_smp_processor_id();
3482         struct loaded_vmcs *v, *n;
3483
3484         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3485                                  loaded_vmcss_on_cpu_link)
3486                 __loaded_vmcs_clear(v);
3487 }
3488
3489
3490 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3491  * tricks.
3492  */
3493 static void kvm_cpu_vmxoff(void)
3494 {
3495         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3496
3497         intel_pt_handle_vmx(0);
3498 }
3499
3500 static void hardware_disable(void)
3501 {
3502         if (vmm_exclusive) {
3503                 vmclear_local_loaded_vmcss();
3504                 kvm_cpu_vmxoff();
3505         }
3506         cr4_clear_bits(X86_CR4_VMXE);
3507 }
3508
3509 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3510                                       u32 msr, u32 *result)
3511 {
3512         u32 vmx_msr_low, vmx_msr_high;
3513         u32 ctl = ctl_min | ctl_opt;
3514
3515         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3516
3517         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3518         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3519
3520         /* Ensure minimum (required) set of control bits are supported. */
3521         if (ctl_min & ~ctl)
3522                 return -EIO;
3523
3524         *result = ctl;
3525         return 0;
3526 }
3527
3528 static __init bool allow_1_setting(u32 msr, u32 ctl)
3529 {
3530         u32 vmx_msr_low, vmx_msr_high;
3531
3532         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3533         return vmx_msr_high & ctl;
3534 }
3535
3536 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3537 {
3538         u32 vmx_msr_low, vmx_msr_high;
3539         u32 min, opt, min2, opt2;
3540         u32 _pin_based_exec_control = 0;
3541         u32 _cpu_based_exec_control = 0;
3542         u32 _cpu_based_2nd_exec_control = 0;
3543         u32 _vmexit_control = 0;
3544         u32 _vmentry_control = 0;
3545
3546         min = CPU_BASED_HLT_EXITING |
3547 #ifdef CONFIG_X86_64
3548               CPU_BASED_CR8_LOAD_EXITING |
3549               CPU_BASED_CR8_STORE_EXITING |
3550 #endif
3551               CPU_BASED_CR3_LOAD_EXITING |
3552               CPU_BASED_CR3_STORE_EXITING |
3553               CPU_BASED_USE_IO_BITMAPS |
3554               CPU_BASED_MOV_DR_EXITING |
3555               CPU_BASED_USE_TSC_OFFSETING |
3556               CPU_BASED_MWAIT_EXITING |
3557               CPU_BASED_MONITOR_EXITING |
3558               CPU_BASED_INVLPG_EXITING |
3559               CPU_BASED_RDPMC_EXITING;
3560
3561         opt = CPU_BASED_TPR_SHADOW |
3562               CPU_BASED_USE_MSR_BITMAPS |
3563               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3564         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3565                                 &_cpu_based_exec_control) < 0)
3566                 return -EIO;
3567 #ifdef CONFIG_X86_64
3568         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3569                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3570                                            ~CPU_BASED_CR8_STORE_EXITING;
3571 #endif
3572         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3573                 min2 = 0;
3574                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3575                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3576                         SECONDARY_EXEC_WBINVD_EXITING |
3577                         SECONDARY_EXEC_ENABLE_VPID |
3578                         SECONDARY_EXEC_ENABLE_EPT |
3579                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3580                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3581                         SECONDARY_EXEC_RDTSCP |
3582                         SECONDARY_EXEC_ENABLE_INVPCID |
3583                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3584                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3585                         SECONDARY_EXEC_SHADOW_VMCS |
3586                         SECONDARY_EXEC_XSAVES |
3587                         SECONDARY_EXEC_ENABLE_PML |
3588                         SECONDARY_EXEC_TSC_SCALING;
3589                 if (adjust_vmx_controls(min2, opt2,
3590                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3591                                         &_cpu_based_2nd_exec_control) < 0)
3592                         return -EIO;
3593         }
3594 #ifndef CONFIG_X86_64
3595         if (!(_cpu_based_2nd_exec_control &
3596                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3597                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3598 #endif
3599
3600         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3601                 _cpu_based_2nd_exec_control &= ~(
3602                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3603                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3604                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3605
3606         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3607                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3608                    enabled */
3609                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3610                                              CPU_BASED_CR3_STORE_EXITING |
3611                                              CPU_BASED_INVLPG_EXITING);
3612                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3613                       vmx_capability.ept, vmx_capability.vpid);
3614         }
3615
3616         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3617 #ifdef CONFIG_X86_64
3618         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3619 #endif
3620         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3621                 VM_EXIT_CLEAR_BNDCFGS;
3622         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3623                                 &_vmexit_control) < 0)
3624                 return -EIO;
3625
3626         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3627         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3628                  PIN_BASED_VMX_PREEMPTION_TIMER;
3629         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3630                                 &_pin_based_exec_control) < 0)
3631                 return -EIO;
3632
3633         if (cpu_has_broken_vmx_preemption_timer())
3634                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3635         if (!(_cpu_based_2nd_exec_control &
3636                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3637                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3638
3639         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3640         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3641         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3642                                 &_vmentry_control) < 0)
3643                 return -EIO;
3644
3645         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3646
3647         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3648         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3649                 return -EIO;
3650
3651 #ifdef CONFIG_X86_64
3652         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3653         if (vmx_msr_high & (1u<<16))
3654                 return -EIO;
3655 #endif
3656
3657         /* Require Write-Back (WB) memory type for VMCS accesses. */
3658         if (((vmx_msr_high >> 18) & 15) != 6)
3659                 return -EIO;
3660
3661         vmcs_conf->size = vmx_msr_high & 0x1fff;
3662         vmcs_conf->order = get_order(vmcs_conf->size);
3663         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3664         vmcs_conf->revision_id = vmx_msr_low;
3665
3666         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3667         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3668         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3669         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3670         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3671
3672         cpu_has_load_ia32_efer =
3673                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3674                                 VM_ENTRY_LOAD_IA32_EFER)
3675                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3676                                    VM_EXIT_LOAD_IA32_EFER);
3677
3678         cpu_has_load_perf_global_ctrl =
3679                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3680                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3681                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3682                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3683
3684         /*
3685          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3686          * but due to errata below it can't be used. Workaround is to use
3687          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3688          *
3689          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3690          *
3691          * AAK155             (model 26)
3692          * AAP115             (model 30)
3693          * AAT100             (model 37)
3694          * BC86,AAY89,BD102   (model 44)
3695          * BA97               (model 46)
3696          *
3697          */
3698         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3699                 switch (boot_cpu_data.x86_model) {
3700                 case 26:
3701                 case 30:
3702                 case 37:
3703                 case 44:
3704                 case 46:
3705                         cpu_has_load_perf_global_ctrl = false;
3706                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3707                                         "does not work properly. Using workaround\n");
3708                         break;
3709                 default:
3710                         break;
3711                 }
3712         }
3713
3714         if (boot_cpu_has(X86_FEATURE_XSAVES))
3715                 rdmsrl(MSR_IA32_XSS, host_xss);
3716
3717         return 0;
3718 }
3719
3720 static struct vmcs *alloc_vmcs_cpu(int cpu)
3721 {
3722         int node = cpu_to_node(cpu);
3723         struct page *pages;
3724         struct vmcs *vmcs;
3725
3726         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3727         if (!pages)
3728                 return NULL;
3729         vmcs = page_address(pages);
3730         memset(vmcs, 0, vmcs_config.size);
3731         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3732         return vmcs;
3733 }
3734
3735 static struct vmcs *alloc_vmcs(void)
3736 {
3737         return alloc_vmcs_cpu(raw_smp_processor_id());
3738 }
3739
3740 static void free_vmcs(struct vmcs *vmcs)
3741 {
3742         free_pages((unsigned long)vmcs, vmcs_config.order);
3743 }
3744
3745 /*
3746  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3747  */
3748 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3749 {
3750         if (!loaded_vmcs->vmcs)
3751                 return;
3752         loaded_vmcs_clear(loaded_vmcs);
3753         free_vmcs(loaded_vmcs->vmcs);
3754         loaded_vmcs->vmcs = NULL;
3755         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3756 }
3757
3758 static void free_kvm_area(void)
3759 {
3760         int cpu;
3761
3762         for_each_possible_cpu(cpu) {
3763                 free_vmcs(per_cpu(vmxarea, cpu));
3764                 per_cpu(vmxarea, cpu) = NULL;
3765         }
3766 }
3767
3768 static void init_vmcs_shadow_fields(void)
3769 {
3770         int i, j;
3771
3772         /* No checks for read only fields yet */
3773
3774         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3775                 switch (shadow_read_write_fields[i]) {
3776                 case GUEST_BNDCFGS:
3777                         if (!kvm_mpx_supported())
3778                                 continue;
3779                         break;
3780                 default:
3781                         break;
3782                 }
3783
3784                 if (j < i)
3785                         shadow_read_write_fields[j] =
3786                                 shadow_read_write_fields[i];
3787                 j++;
3788         }
3789         max_shadow_read_write_fields = j;
3790
3791         /* shadowed fields guest access without vmexit */
3792         for (i = 0; i < max_shadow_read_write_fields; i++) {
3793                 clear_bit(shadow_read_write_fields[i],
3794                           vmx_vmwrite_bitmap);
3795                 clear_bit(shadow_read_write_fields[i],
3796                           vmx_vmread_bitmap);
3797         }
3798         for (i = 0; i < max_shadow_read_only_fields; i++)
3799                 clear_bit(shadow_read_only_fields[i],
3800                           vmx_vmread_bitmap);
3801 }
3802
3803 static __init int alloc_kvm_area(void)
3804 {
3805         int cpu;
3806
3807         for_each_possible_cpu(cpu) {
3808                 struct vmcs *vmcs;
3809
3810                 vmcs = alloc_vmcs_cpu(cpu);
3811                 if (!vmcs) {
3812                         free_kvm_area();
3813                         return -ENOMEM;
3814                 }
3815
3816                 per_cpu(vmxarea, cpu) = vmcs;
3817         }
3818         return 0;
3819 }
3820
3821 static bool emulation_required(struct kvm_vcpu *vcpu)
3822 {
3823         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3824 }
3825
3826 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3827                 struct kvm_segment *save)
3828 {
3829         if (!emulate_invalid_guest_state) {
3830                 /*
3831                  * CS and SS RPL should be equal during guest entry according
3832                  * to VMX spec, but in reality it is not always so. Since vcpu
3833                  * is in the middle of the transition from real mode to
3834                  * protected mode it is safe to assume that RPL 0 is a good
3835                  * default value.
3836                  */
3837                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3838                         save->selector &= ~SEGMENT_RPL_MASK;
3839                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3840                 save->s = 1;
3841         }
3842         vmx_set_segment(vcpu, save, seg);
3843 }
3844
3845 static void enter_pmode(struct kvm_vcpu *vcpu)
3846 {
3847         unsigned long flags;
3848         struct vcpu_vmx *vmx = to_vmx(vcpu);
3849
3850         /*
3851          * Update real mode segment cache. It may be not up-to-date if sement
3852          * register was written while vcpu was in a guest mode.
3853          */
3854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3855         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3856         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3857         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3858         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3859         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3860
3861         vmx->rmode.vm86_active = 0;
3862
3863         vmx_segment_cache_clear(vmx);
3864
3865         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3866
3867         flags = vmcs_readl(GUEST_RFLAGS);
3868         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3869         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3870         vmcs_writel(GUEST_RFLAGS, flags);
3871
3872         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3873                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3874
3875         update_exception_bitmap(vcpu);
3876
3877         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3878         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3879         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3880         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3881         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3882         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3883 }
3884
3885 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3886 {
3887         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3888         struct kvm_segment var = *save;
3889
3890         var.dpl = 0x3;
3891         if (seg == VCPU_SREG_CS)
3892                 var.type = 0x3;
3893
3894         if (!emulate_invalid_guest_state) {
3895                 var.selector = var.base >> 4;
3896                 var.base = var.base & 0xffff0;
3897                 var.limit = 0xffff;
3898                 var.g = 0;
3899                 var.db = 0;
3900                 var.present = 1;
3901                 var.s = 1;
3902                 var.l = 0;
3903                 var.unusable = 0;
3904                 var.type = 0x3;
3905                 var.avl = 0;
3906                 if (save->base & 0xf)
3907                         printk_once(KERN_WARNING "kvm: segment base is not "
3908                                         "paragraph aligned when entering "
3909                                         "protected mode (seg=%d)", seg);
3910         }
3911
3912         vmcs_write16(sf->selector, var.selector);
3913         vmcs_write32(sf->base, var.base);
3914         vmcs_write32(sf->limit, var.limit);
3915         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3916 }
3917
3918 static void enter_rmode(struct kvm_vcpu *vcpu)
3919 {
3920         unsigned long flags;
3921         struct vcpu_vmx *vmx = to_vmx(vcpu);
3922
3923         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3924         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3925         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3926         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3927         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3928         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3929         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3930
3931         vmx->rmode.vm86_active = 1;
3932
3933         /*
3934          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3935          * vcpu. Warn the user that an update is overdue.
3936          */
3937         if (!vcpu->kvm->arch.tss_addr)
3938                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3939                              "called before entering vcpu\n");
3940
3941         vmx_segment_cache_clear(vmx);
3942
3943         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3944         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3945         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3946
3947         flags = vmcs_readl(GUEST_RFLAGS);
3948         vmx->rmode.save_rflags = flags;
3949
3950         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3951
3952         vmcs_writel(GUEST_RFLAGS, flags);
3953         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3954         update_exception_bitmap(vcpu);
3955
3956         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3957         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3958         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3959         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3960         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3961         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3962
3963         kvm_mmu_reset_context(vcpu);
3964 }
3965
3966 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3967 {
3968         struct vcpu_vmx *vmx = to_vmx(vcpu);
3969         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3970
3971         if (!msr)
3972                 return;
3973
3974         /*
3975          * Force kernel_gs_base reloading before EFER changes, as control
3976          * of this msr depends on is_long_mode().
3977          */
3978         vmx_load_host_state(to_vmx(vcpu));
3979         vcpu->arch.efer = efer;
3980         if (efer & EFER_LMA) {
3981                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3982                 msr->data = efer;
3983         } else {
3984                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3985
3986                 msr->data = efer & ~EFER_LME;
3987         }
3988         setup_msrs(vmx);
3989 }
3990
3991 #ifdef CONFIG_X86_64
3992
3993 static void enter_lmode(struct kvm_vcpu *vcpu)
3994 {
3995         u32 guest_tr_ar;
3996
3997         vmx_segment_cache_clear(to_vmx(vcpu));
3998
3999         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4000         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4001                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4002                                      __func__);
4003                 vmcs_write32(GUEST_TR_AR_BYTES,
4004                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4005                              | VMX_AR_TYPE_BUSY_64_TSS);
4006         }
4007         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4008 }
4009
4010 static void exit_lmode(struct kvm_vcpu *vcpu)
4011 {
4012         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4013         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4014 }
4015
4016 #endif
4017
4018 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4019 {
4020         vpid_sync_context(vpid);
4021         if (enable_ept) {
4022                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4023                         return;
4024                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4025         }
4026 }
4027
4028 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4029 {
4030         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4031 }
4032
4033 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4034 {
4035         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4036
4037         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4038         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4039 }
4040
4041 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4042 {
4043         if (enable_ept && is_paging(vcpu))
4044                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4045         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4046 }
4047
4048 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4049 {
4050         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4051
4052         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4053         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4054 }
4055
4056 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4057 {
4058         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4059
4060         if (!test_bit(VCPU_EXREG_PDPTR,
4061                       (unsigned long *)&vcpu->arch.regs_dirty))
4062                 return;
4063
4064         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4065                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4066                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4067                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4068                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4069         }
4070 }
4071
4072 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4073 {
4074         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4075
4076         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4077                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4078                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4079                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4080                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4081         }
4082
4083         __set_bit(VCPU_EXREG_PDPTR,
4084                   (unsigned long *)&vcpu->arch.regs_avail);
4085         __set_bit(VCPU_EXREG_PDPTR,
4086                   (unsigned long *)&vcpu->arch.regs_dirty);
4087 }
4088
4089 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4090 {
4091         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4092         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4093         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4094
4095         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4096                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4097             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4098                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4099
4100         return fixed_bits_valid(val, fixed0, fixed1);
4101 }
4102
4103 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4104 {
4105         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4106         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4107
4108         return fixed_bits_valid(val, fixed0, fixed1);
4109 }
4110
4111 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4112 {
4113         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4114         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4115
4116         return fixed_bits_valid(val, fixed0, fixed1);
4117 }
4118
4119 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4120 #define nested_guest_cr4_valid  nested_cr4_valid
4121 #define nested_host_cr4_valid   nested_cr4_valid
4122
4123 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4124
4125 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4126                                         unsigned long cr0,
4127                                         struct kvm_vcpu *vcpu)
4128 {
4129         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4130                 vmx_decache_cr3(vcpu);
4131         if (!(cr0 & X86_CR0_PG)) {
4132                 /* From paging/starting to nonpaging */
4133                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4134                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4135                              (CPU_BASED_CR3_LOAD_EXITING |
4136                               CPU_BASED_CR3_STORE_EXITING));
4137                 vcpu->arch.cr0 = cr0;
4138                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4139         } else if (!is_paging(vcpu)) {
4140                 /* From nonpaging to paging */
4141                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4142                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4143                              ~(CPU_BASED_CR3_LOAD_EXITING |
4144                                CPU_BASED_CR3_STORE_EXITING));
4145                 vcpu->arch.cr0 = cr0;
4146                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4147         }
4148
4149         if (!(cr0 & X86_CR0_WP))
4150                 *hw_cr0 &= ~X86_CR0_WP;
4151 }
4152
4153 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4154 {
4155         struct vcpu_vmx *vmx = to_vmx(vcpu);
4156         unsigned long hw_cr0;
4157
4158         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4159         if (enable_unrestricted_guest)
4160                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4161         else {
4162                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4163
4164                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4165                         enter_pmode(vcpu);
4166
4167                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4168                         enter_rmode(vcpu);
4169         }
4170
4171 #ifdef CONFIG_X86_64
4172         if (vcpu->arch.efer & EFER_LME) {
4173                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4174                         enter_lmode(vcpu);
4175                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4176                         exit_lmode(vcpu);
4177         }
4178 #endif
4179
4180         if (enable_ept)
4181                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4182
4183         vmcs_writel(CR0_READ_SHADOW, cr0);
4184         vmcs_writel(GUEST_CR0, hw_cr0);
4185         vcpu->arch.cr0 = cr0;
4186
4187         /* depends on vcpu->arch.cr0 to be set to a new value */
4188         vmx->emulation_required = emulation_required(vcpu);
4189 }
4190
4191 static u64 construct_eptp(unsigned long root_hpa)
4192 {
4193         u64 eptp;
4194
4195         /* TODO write the value reading from MSR */
4196         eptp = VMX_EPT_DEFAULT_MT |
4197                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4198         if (enable_ept_ad_bits)
4199                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4200         eptp |= (root_hpa & PAGE_MASK);
4201
4202         return eptp;
4203 }
4204
4205 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4206 {
4207         unsigned long guest_cr3;
4208         u64 eptp;
4209
4210         guest_cr3 = cr3;
4211         if (enable_ept) {
4212                 eptp = construct_eptp(cr3);
4213                 vmcs_write64(EPT_POINTER, eptp);
4214                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4215                         guest_cr3 = kvm_read_cr3(vcpu);
4216                 else
4217                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4218                 ept_load_pdptrs(vcpu);
4219         }
4220
4221         vmx_flush_tlb(vcpu);
4222         vmcs_writel(GUEST_CR3, guest_cr3);
4223 }
4224
4225 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4226 {
4227         /*
4228          * Pass through host's Machine Check Enable value to hw_cr4, which
4229          * is in force while we are in guest mode.  Do not let guests control
4230          * this bit, even if host CR4.MCE == 0.
4231          */
4232         unsigned long hw_cr4 =
4233                 (cr4_read_shadow() & X86_CR4_MCE) |
4234                 (cr4 & ~X86_CR4_MCE) |
4235                 (to_vmx(vcpu)->rmode.vm86_active ?
4236                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4237
4238         if (cr4 & X86_CR4_VMXE) {
4239                 /*
4240                  * To use VMXON (and later other VMX instructions), a guest
4241                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4242                  * So basically the check on whether to allow nested VMX
4243                  * is here.
4244                  */
4245                 if (!nested_vmx_allowed(vcpu))
4246                         return 1;
4247         }
4248
4249         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4250                 return 1;
4251
4252         vcpu->arch.cr4 = cr4;
4253         if (enable_ept) {
4254                 if (!is_paging(vcpu)) {
4255                         hw_cr4 &= ~X86_CR4_PAE;
4256                         hw_cr4 |= X86_CR4_PSE;
4257                 } else if (!(cr4 & X86_CR4_PAE)) {
4258                         hw_cr4 &= ~X86_CR4_PAE;
4259                 }
4260         }
4261
4262         if (!enable_unrestricted_guest && !is_paging(vcpu))
4263                 /*
4264                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4265                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4266                  * to be manually disabled when guest switches to non-paging
4267                  * mode.
4268                  *
4269                  * If !enable_unrestricted_guest, the CPU is always running
4270                  * with CR0.PG=1 and CR4 needs to be modified.
4271                  * If enable_unrestricted_guest, the CPU automatically
4272                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4273                  */
4274                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4275
4276         vmcs_writel(CR4_READ_SHADOW, cr4);
4277         vmcs_writel(GUEST_CR4, hw_cr4);
4278         return 0;
4279 }
4280
4281 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4282                             struct kvm_segment *var, int seg)
4283 {
4284         struct vcpu_vmx *vmx = to_vmx(vcpu);
4285         u32 ar;
4286
4287         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4288                 *var = vmx->rmode.segs[seg];
4289                 if (seg == VCPU_SREG_TR
4290                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4291                         return;
4292                 var->base = vmx_read_guest_seg_base(vmx, seg);
4293                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4294                 return;
4295         }
4296         var->base = vmx_read_guest_seg_base(vmx, seg);
4297         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4298         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4299         ar = vmx_read_guest_seg_ar(vmx, seg);
4300         var->unusable = (ar >> 16) & 1;
4301         var->type = ar & 15;
4302         var->s = (ar >> 4) & 1;
4303         var->dpl = (ar >> 5) & 3;
4304         /*
4305          * Some userspaces do not preserve unusable property. Since usable
4306          * segment has to be present according to VMX spec we can use present
4307          * property to amend userspace bug by making unusable segment always
4308          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4309          * segment as unusable.
4310          */
4311         var->present = !var->unusable;
4312         var->avl = (ar >> 12) & 1;
4313         var->l = (ar >> 13) & 1;
4314         var->db = (ar >> 14) & 1;
4315         var->g = (ar >> 15) & 1;
4316 }
4317
4318 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4319 {
4320         struct kvm_segment s;
4321
4322         if (to_vmx(vcpu)->rmode.vm86_active) {
4323                 vmx_get_segment(vcpu, &s, seg);
4324                 return s.base;
4325         }
4326         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4327 }
4328
4329 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4330 {
4331         struct vcpu_vmx *vmx = to_vmx(vcpu);
4332
4333         if (unlikely(vmx->rmode.vm86_active))
4334                 return 0;
4335         else {
4336                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4337                 return VMX_AR_DPL(ar);
4338         }
4339 }
4340
4341 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4342 {
4343         u32 ar;
4344
4345         if (var->unusable || !var->present)
4346                 ar = 1 << 16;
4347         else {
4348                 ar = var->type & 15;
4349                 ar |= (var->s & 1) << 4;
4350                 ar |= (var->dpl & 3) << 5;
4351                 ar |= (var->present & 1) << 7;
4352                 ar |= (var->avl & 1) << 12;
4353                 ar |= (var->l & 1) << 13;
4354                 ar |= (var->db & 1) << 14;
4355                 ar |= (var->g & 1) << 15;
4356         }
4357
4358         return ar;
4359 }
4360
4361 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4362                             struct kvm_segment *var, int seg)
4363 {
4364         struct vcpu_vmx *vmx = to_vmx(vcpu);
4365         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4366
4367         vmx_segment_cache_clear(vmx);
4368
4369         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4370                 vmx->rmode.segs[seg] = *var;
4371                 if (seg == VCPU_SREG_TR)
4372                         vmcs_write16(sf->selector, var->selector);
4373                 else if (var->s)
4374                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4375                 goto out;
4376         }
4377
4378         vmcs_writel(sf->base, var->base);
4379         vmcs_write32(sf->limit, var->limit);
4380         vmcs_write16(sf->selector, var->selector);
4381
4382         /*
4383          *   Fix the "Accessed" bit in AR field of segment registers for older
4384          * qemu binaries.
4385          *   IA32 arch specifies that at the time of processor reset the
4386          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4387          * is setting it to 0 in the userland code. This causes invalid guest
4388          * state vmexit when "unrestricted guest" mode is turned on.
4389          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4390          * tree. Newer qemu binaries with that qemu fix would not need this
4391          * kvm hack.
4392          */
4393         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4394                 var->type |= 0x1; /* Accessed */
4395
4396         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4397
4398 out:
4399         vmx->emulation_required = emulation_required(vcpu);
4400 }
4401
4402 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4403 {
4404         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4405
4406         *db = (ar >> 14) & 1;
4407         *l = (ar >> 13) & 1;
4408 }
4409
4410 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4411 {
4412         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4413         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4414 }
4415
4416 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4417 {
4418         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4419         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4420 }
4421
4422 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4423 {
4424         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4425         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4426 }
4427
4428 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4429 {
4430         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4431         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4432 }
4433
4434 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4435 {
4436         struct kvm_segment var;
4437         u32 ar;
4438
4439         vmx_get_segment(vcpu, &var, seg);
4440         var.dpl = 0x3;
4441         if (seg == VCPU_SREG_CS)
4442                 var.type = 0x3;
4443         ar = vmx_segment_access_rights(&var);
4444
4445         if (var.base != (var.selector << 4))
4446                 return false;
4447         if (var.limit != 0xffff)
4448                 return false;
4449         if (ar != 0xf3)
4450                 return false;
4451
4452         return true;
4453 }
4454
4455 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4456 {
4457         struct kvm_segment cs;
4458         unsigned int cs_rpl;
4459
4460         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4461         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4462
4463         if (cs.unusable)
4464                 return false;
4465         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4466                 return false;
4467         if (!cs.s)
4468                 return false;
4469         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4470                 if (cs.dpl > cs_rpl)
4471                         return false;
4472         } else {
4473                 if (cs.dpl != cs_rpl)
4474                         return false;
4475         }
4476         if (!cs.present)
4477                 return false;
4478
4479         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4480         return true;
4481 }
4482
4483 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4484 {
4485         struct kvm_segment ss;
4486         unsigned int ss_rpl;
4487
4488         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4489         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4490
4491         if (ss.unusable)
4492                 return true;
4493         if (ss.type != 3 && ss.type != 7)
4494                 return false;
4495         if (!ss.s)
4496                 return false;
4497         if (ss.dpl != ss_rpl) /* DPL != RPL */
4498                 return false;
4499         if (!ss.present)
4500                 return false;
4501
4502         return true;
4503 }
4504
4505 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4506 {
4507         struct kvm_segment var;
4508         unsigned int rpl;
4509
4510         vmx_get_segment(vcpu, &var, seg);
4511         rpl = var.selector & SEGMENT_RPL_MASK;
4512
4513         if (var.unusable)
4514                 return true;
4515         if (!var.s)
4516                 return false;
4517         if (!var.present)
4518                 return false;
4519         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4520                 if (var.dpl < rpl) /* DPL < RPL */
4521                         return false;
4522         }
4523
4524         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4525          * rights flags
4526          */
4527         return true;
4528 }
4529
4530 static bool tr_valid(struct kvm_vcpu *vcpu)
4531 {
4532         struct kvm_segment tr;
4533
4534         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4535
4536         if (tr.unusable)
4537                 return false;
4538         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4539                 return false;
4540         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4541                 return false;
4542         if (!tr.present)
4543                 return false;
4544
4545         return true;
4546 }
4547
4548 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4549 {
4550         struct kvm_segment ldtr;
4551
4552         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4553
4554         if (ldtr.unusable)
4555                 return true;
4556         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4557                 return false;
4558         if (ldtr.type != 2)
4559                 return false;
4560         if (!ldtr.present)
4561                 return false;
4562
4563         return true;
4564 }
4565
4566 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4567 {
4568         struct kvm_segment cs, ss;
4569
4570         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4571         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4572
4573         return ((cs.selector & SEGMENT_RPL_MASK) ==
4574                  (ss.selector & SEGMENT_RPL_MASK));
4575 }
4576
4577 /*
4578  * Check if guest state is valid. Returns true if valid, false if
4579  * not.
4580  * We assume that registers are always usable
4581  */
4582 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4583 {
4584         if (enable_unrestricted_guest)
4585                 return true;
4586
4587         /* real mode guest state checks */
4588         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4589                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4590                         return false;
4591                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4592                         return false;
4593                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4594                         return false;
4595                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4596                         return false;
4597                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4598                         return false;
4599                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4600                         return false;
4601         } else {
4602         /* protected mode guest state checks */
4603                 if (!cs_ss_rpl_check(vcpu))
4604                         return false;
4605                 if (!code_segment_valid(vcpu))
4606                         return false;
4607                 if (!stack_segment_valid(vcpu))
4608                         return false;
4609                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4610                         return false;
4611                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4612                         return false;
4613                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4614                         return false;
4615                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4616                         return false;
4617                 if (!tr_valid(vcpu))
4618                         return false;
4619                 if (!ldtr_valid(vcpu))
4620                         return false;
4621         }
4622         /* TODO:
4623          * - Add checks on RIP
4624          * - Add checks on RFLAGS
4625          */
4626
4627         return true;
4628 }
4629
4630 static int init_rmode_tss(struct kvm *kvm)
4631 {
4632         gfn_t fn;
4633         u16 data = 0;
4634         int idx, r;
4635
4636         idx = srcu_read_lock(&kvm->srcu);
4637         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4638         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4639         if (r < 0)
4640                 goto out;
4641         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4642         r = kvm_write_guest_page(kvm, fn++, &data,
4643                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4644         if (r < 0)
4645                 goto out;
4646         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4647         if (r < 0)
4648                 goto out;
4649         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4650         if (r < 0)
4651                 goto out;
4652         data = ~0;
4653         r = kvm_write_guest_page(kvm, fn, &data,
4654                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4655                                  sizeof(u8));
4656 out:
4657         srcu_read_unlock(&kvm->srcu, idx);
4658         return r;
4659 }
4660
4661 static int init_rmode_identity_map(struct kvm *kvm)
4662 {
4663         int i, idx, r = 0;
4664         kvm_pfn_t identity_map_pfn;
4665         u32 tmp;
4666
4667         if (!enable_ept)
4668                 return 0;
4669
4670         /* Protect kvm->arch.ept_identity_pagetable_done. */
4671         mutex_lock(&kvm->slots_lock);
4672
4673         if (likely(kvm->arch.ept_identity_pagetable_done))
4674                 goto out2;
4675
4676         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4677
4678         r = alloc_identity_pagetable(kvm);
4679         if (r < 0)
4680                 goto out2;
4681
4682         idx = srcu_read_lock(&kvm->srcu);
4683         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4684         if (r < 0)
4685                 goto out;
4686         /* Set up identity-mapping pagetable for EPT in real mode */
4687         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4688                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4689                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4690                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4691                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4692                 if (r < 0)
4693                         goto out;
4694         }
4695         kvm->arch.ept_identity_pagetable_done = true;
4696
4697 out:
4698         srcu_read_unlock(&kvm->srcu, idx);
4699
4700 out2:
4701         mutex_unlock(&kvm->slots_lock);
4702         return r;
4703 }
4704
4705 static void seg_setup(int seg)
4706 {
4707         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4708         unsigned int ar;
4709
4710         vmcs_write16(sf->selector, 0);
4711         vmcs_writel(sf->base, 0);
4712         vmcs_write32(sf->limit, 0xffff);
4713         ar = 0x93;
4714         if (seg == VCPU_SREG_CS)
4715                 ar |= 0x08; /* code segment */
4716
4717         vmcs_write32(sf->ar_bytes, ar);
4718 }
4719
4720 static int alloc_apic_access_page(struct kvm *kvm)
4721 {
4722         struct page *page;
4723         int r = 0;
4724
4725         mutex_lock(&kvm->slots_lock);
4726         if (kvm->arch.apic_access_page_done)
4727                 goto out;
4728         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4729                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4730         if (r)
4731                 goto out;
4732
4733         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4734         if (is_error_page(page)) {
4735                 r = -EFAULT;
4736                 goto out;
4737         }
4738
4739         /*
4740          * Do not pin the page in memory, so that memory hot-unplug
4741          * is able to migrate it.
4742          */
4743         put_page(page);
4744         kvm->arch.apic_access_page_done = true;
4745 out:
4746         mutex_unlock(&kvm->slots_lock);
4747         return r;
4748 }
4749
4750 static int alloc_identity_pagetable(struct kvm *kvm)
4751 {
4752         /* Called with kvm->slots_lock held. */
4753
4754         int r = 0;
4755
4756         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4757
4758         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4759                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4760
4761         return r;
4762 }
4763
4764 static int allocate_vpid(void)
4765 {
4766         int vpid;
4767
4768         if (!enable_vpid)
4769                 return 0;
4770         spin_lock(&vmx_vpid_lock);
4771         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4772         if (vpid < VMX_NR_VPIDS)
4773                 __set_bit(vpid, vmx_vpid_bitmap);
4774         else
4775                 vpid = 0;
4776         spin_unlock(&vmx_vpid_lock);
4777         return vpid;
4778 }
4779
4780 static void free_vpid(int vpid)
4781 {
4782         if (!enable_vpid || vpid == 0)
4783                 return;
4784         spin_lock(&vmx_vpid_lock);
4785         __clear_bit(vpid, vmx_vpid_bitmap);
4786         spin_unlock(&vmx_vpid_lock);
4787 }
4788
4789 #define MSR_TYPE_R      1
4790 #define MSR_TYPE_W      2
4791 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4792                                                 u32 msr, int type)
4793 {
4794         int f = sizeof(unsigned long);
4795
4796         if (!cpu_has_vmx_msr_bitmap())
4797                 return;
4798
4799         /*
4800          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4801          * have the write-low and read-high bitmap offsets the wrong way round.
4802          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4803          */
4804         if (msr <= 0x1fff) {
4805                 if (type & MSR_TYPE_R)
4806                         /* read-low */
4807                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4808
4809                 if (type & MSR_TYPE_W)
4810                         /* write-low */
4811                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4812
4813         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4814                 msr &= 0x1fff;
4815                 if (type & MSR_TYPE_R)
4816                         /* read-high */
4817                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4818
4819                 if (type & MSR_TYPE_W)
4820                         /* write-high */
4821                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4822
4823         }
4824 }
4825
4826 /*
4827  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4828  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4829  */
4830 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4831                                                unsigned long *msr_bitmap_nested,
4832                                                u32 msr, int type)
4833 {
4834         int f = sizeof(unsigned long);
4835
4836         if (!cpu_has_vmx_msr_bitmap()) {
4837                 WARN_ON(1);
4838                 return;
4839         }
4840
4841         /*
4842          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4843          * have the write-low and read-high bitmap offsets the wrong way round.
4844          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4845          */
4846         if (msr <= 0x1fff) {
4847                 if (type & MSR_TYPE_R &&
4848                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4849                         /* read-low */
4850                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4851
4852                 if (type & MSR_TYPE_W &&
4853                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4854                         /* write-low */
4855                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4856
4857         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4858                 msr &= 0x1fff;
4859                 if (type & MSR_TYPE_R &&
4860                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4861                         /* read-high */
4862                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4863
4864                 if (type & MSR_TYPE_W &&
4865                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4866                         /* write-high */
4867                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4868
4869         }
4870 }
4871
4872 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4873 {
4874         if (!longmode_only)
4875                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4876                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4877         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4878                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4879 }
4880
4881 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4882 {
4883         if (apicv_active) {
4884                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4885                                 msr, type);
4886                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4887                                 msr, type);
4888         } else {
4889                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4890                                 msr, type);
4891                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4892                                 msr, type);
4893         }
4894 }
4895
4896 static bool vmx_get_enable_apicv(void)
4897 {
4898         return enable_apicv;
4899 }
4900
4901 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4902 {
4903         struct vcpu_vmx *vmx = to_vmx(vcpu);
4904         int max_irr;
4905         void *vapic_page;
4906         u16 status;
4907
4908         if (vmx->nested.pi_desc &&
4909             vmx->nested.pi_pending) {
4910                 vmx->nested.pi_pending = false;
4911                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4912                         return;
4913
4914                 max_irr = find_last_bit(
4915                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4916
4917                 if (max_irr == 256)
4918                         return;
4919
4920                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4921                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4922                 kunmap(vmx->nested.virtual_apic_page);
4923
4924                 status = vmcs_read16(GUEST_INTR_STATUS);
4925                 if ((u8)max_irr > ((u8)status & 0xff)) {
4926                         status &= ~0xff;
4927                         status |= (u8)max_irr;
4928                         vmcs_write16(GUEST_INTR_STATUS, status);
4929                 }
4930         }
4931 }
4932
4933 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4934 {
4935 #ifdef CONFIG_SMP
4936         if (vcpu->mode == IN_GUEST_MODE) {
4937                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4938
4939                 /*
4940                  * Currently, we don't support urgent interrupt,
4941                  * all interrupts are recognized as non-urgent
4942                  * interrupt, so we cannot post interrupts when
4943                  * 'SN' is set.
4944                  *
4945                  * If the vcpu is in guest mode, it means it is
4946                  * running instead of being scheduled out and
4947                  * waiting in the run queue, and that's the only
4948                  * case when 'SN' is set currently, warning if
4949                  * 'SN' is set.
4950                  */
4951                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4952
4953                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4954                                 POSTED_INTR_VECTOR);
4955                 return true;
4956         }
4957 #endif
4958         return false;
4959 }
4960
4961 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4962                                                 int vector)
4963 {
4964         struct vcpu_vmx *vmx = to_vmx(vcpu);
4965
4966         if (is_guest_mode(vcpu) &&
4967             vector == vmx->nested.posted_intr_nv) {
4968                 /* the PIR and ON have been set by L1. */
4969                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4970                 /*
4971                  * If a posted intr is not recognized by hardware,
4972                  * we will accomplish it in the next vmentry.
4973                  */
4974                 vmx->nested.pi_pending = true;
4975                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4976                 return 0;
4977         }
4978         return -1;
4979 }
4980 /*
4981  * Send interrupt to vcpu via posted interrupt way.
4982  * 1. If target vcpu is running(non-root mode), send posted interrupt
4983  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4984  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4985  * interrupt from PIR in next vmentry.
4986  */
4987 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4988 {
4989         struct vcpu_vmx *vmx = to_vmx(vcpu);
4990         int r;
4991
4992         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4993         if (!r)
4994                 return;
4995
4996         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4997                 return;
4998
4999         /* If a previous notification has sent the IPI, nothing to do.  */
5000         if (pi_test_and_set_on(&vmx->pi_desc))
5001                 return;
5002
5003         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5004                 kvm_vcpu_kick(vcpu);
5005 }
5006
5007 /*
5008  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5009  * will not change in the lifetime of the guest.
5010  * Note that host-state that does change is set elsewhere. E.g., host-state
5011  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5012  */
5013 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5014 {
5015         u32 low32, high32;
5016         unsigned long tmpl;
5017         struct desc_ptr dt;
5018         unsigned long cr0, cr4;
5019
5020         cr0 = read_cr0();
5021         WARN_ON(cr0 & X86_CR0_TS);
5022         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5023         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5024
5025         /* Save the most likely value for this task's CR4 in the VMCS. */
5026         cr4 = cr4_read_shadow();
5027         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5028         vmx->host_state.vmcs_host_cr4 = cr4;
5029
5030         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5031 #ifdef CONFIG_X86_64
5032         /*
5033          * Load null selectors, so we can avoid reloading them in
5034          * __vmx_load_host_state(), in case userspace uses the null selectors
5035          * too (the expected case).
5036          */
5037         vmcs_write16(HOST_DS_SELECTOR, 0);
5038         vmcs_write16(HOST_ES_SELECTOR, 0);
5039 #else
5040         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5041         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5042 #endif
5043         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5044         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5045
5046         native_store_idt(&dt);
5047         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5048         vmx->host_idt_base = dt.address;
5049
5050         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5051
5052         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5053         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5054         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5055         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5056
5057         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5058                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5059                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5060         }
5061 }
5062
5063 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5064 {
5065         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5066         if (enable_ept)
5067                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5068         if (is_guest_mode(&vmx->vcpu))
5069                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5070                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5071         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5072 }
5073
5074 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5075 {
5076         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5077
5078         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5079                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5080         /* Enable the preemption timer dynamically */
5081         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5082         return pin_based_exec_ctrl;
5083 }
5084
5085 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5086 {
5087         struct vcpu_vmx *vmx = to_vmx(vcpu);
5088
5089         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5090         if (cpu_has_secondary_exec_ctrls()) {
5091                 if (kvm_vcpu_apicv_active(vcpu))
5092                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5093                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5094                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5095                 else
5096                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5097                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5098                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5099         }
5100
5101         if (cpu_has_vmx_msr_bitmap())
5102                 vmx_set_msr_bitmap(vcpu);
5103 }
5104
5105 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5106 {
5107         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5108
5109         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5110                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5111
5112         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5113                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5114 #ifdef CONFIG_X86_64
5115                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5116                                 CPU_BASED_CR8_LOAD_EXITING;
5117 #endif
5118         }
5119         if (!enable_ept)
5120                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5121                                 CPU_BASED_CR3_LOAD_EXITING  |
5122                                 CPU_BASED_INVLPG_EXITING;
5123         return exec_control;
5124 }
5125
5126 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5127 {
5128         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5129         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5130                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5131         if (vmx->vpid == 0)
5132                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5133         if (!enable_ept) {
5134                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5135                 enable_unrestricted_guest = 0;
5136                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5137                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5138         }
5139         if (!enable_unrestricted_guest)
5140                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5141         if (!ple_gap)
5142                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5143         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5144                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5145                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5146         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5147         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5148            (handle_vmptrld).
5149            We can NOT enable shadow_vmcs here because we don't have yet
5150            a current VMCS12
5151         */
5152         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5153
5154         if (!enable_pml)
5155                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5156
5157         return exec_control;
5158 }
5159
5160 static void ept_set_mmio_spte_mask(void)
5161 {
5162         /*
5163          * EPT Misconfigurations can be generated if the value of bits 2:0
5164          * of an EPT paging-structure entry is 110b (write/execute).
5165          */
5166         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5167 }
5168
5169 #define VMX_XSS_EXIT_BITMAP 0
5170 /*
5171  * Sets up the vmcs for emulated real mode.
5172  */
5173 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5174 {
5175 #ifdef CONFIG_X86_64
5176         unsigned long a;
5177 #endif
5178         int i;
5179
5180         /* I/O */
5181         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5182         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5183
5184         if (enable_shadow_vmcs) {
5185                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5186                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5187         }
5188         if (cpu_has_vmx_msr_bitmap())
5189                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5190
5191         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5192
5193         /* Control */
5194         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5195         vmx->hv_deadline_tsc = -1;
5196
5197         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5198
5199         if (cpu_has_secondary_exec_ctrls()) {
5200                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5201                                 vmx_secondary_exec_control(vmx));
5202         }
5203
5204         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5205                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5206                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5207                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5208                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5209
5210                 vmcs_write16(GUEST_INTR_STATUS, 0);
5211
5212                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5213                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5214         }
5215
5216         if (ple_gap) {
5217                 vmcs_write32(PLE_GAP, ple_gap);
5218                 vmx->ple_window = ple_window;
5219                 vmx->ple_window_dirty = true;
5220         }
5221
5222         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5223         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5224         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5225
5226         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5227         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5228         vmx_set_constant_host_state(vmx);
5229 #ifdef CONFIG_X86_64
5230         rdmsrl(MSR_FS_BASE, a);
5231         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5232         rdmsrl(MSR_GS_BASE, a);
5233         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5234 #else
5235         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5236         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5237 #endif
5238
5239         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5240         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5241         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5242         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5243         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5244
5245         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5246                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5247
5248         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5249                 u32 index = vmx_msr_index[i];
5250                 u32 data_low, data_high;
5251                 int j = vmx->nmsrs;
5252
5253                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5254                         continue;
5255                 if (wrmsr_safe(index, data_low, data_high) < 0)
5256                         continue;
5257                 vmx->guest_msrs[j].index = i;
5258                 vmx->guest_msrs[j].data = 0;
5259                 vmx->guest_msrs[j].mask = -1ull;
5260                 ++vmx->nmsrs;
5261         }
5262
5263
5264         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5265
5266         /* 22.2.1, 20.8.1 */
5267         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5268
5269         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5270         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5271
5272         set_cr4_guest_host_mask(vmx);
5273
5274         if (vmx_xsaves_supported())
5275                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5276
5277         if (enable_pml) {
5278                 ASSERT(vmx->pml_pg);
5279                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5280                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5281         }
5282
5283         return 0;
5284 }
5285
5286 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5287 {
5288         struct vcpu_vmx *vmx = to_vmx(vcpu);
5289         struct msr_data apic_base_msr;
5290         u64 cr0;
5291
5292         vmx->rmode.vm86_active = 0;
5293
5294         vmx->soft_vnmi_blocked = 0;
5295
5296         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5297         kvm_set_cr8(vcpu, 0);
5298
5299         if (!init_event) {
5300                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5301                                      MSR_IA32_APICBASE_ENABLE;
5302                 if (kvm_vcpu_is_reset_bsp(vcpu))
5303                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5304                 apic_base_msr.host_initiated = true;
5305                 kvm_set_apic_base(vcpu, &apic_base_msr);
5306         }
5307
5308         vmx_segment_cache_clear(vmx);
5309
5310         seg_setup(VCPU_SREG_CS);
5311         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5312         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5313
5314         seg_setup(VCPU_SREG_DS);
5315         seg_setup(VCPU_SREG_ES);
5316         seg_setup(VCPU_SREG_FS);
5317         seg_setup(VCPU_SREG_GS);
5318         seg_setup(VCPU_SREG_SS);
5319
5320         vmcs_write16(GUEST_TR_SELECTOR, 0);
5321         vmcs_writel(GUEST_TR_BASE, 0);
5322         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5323         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5324
5325         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5326         vmcs_writel(GUEST_LDTR_BASE, 0);
5327         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5328         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5329
5330         if (!init_event) {
5331                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5332                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5333                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5334                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5335         }
5336
5337         vmcs_writel(GUEST_RFLAGS, 0x02);
5338         kvm_rip_write(vcpu, 0xfff0);
5339
5340         vmcs_writel(GUEST_GDTR_BASE, 0);
5341         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5342
5343         vmcs_writel(GUEST_IDTR_BASE, 0);
5344         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5345
5346         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5347         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5348         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5349
5350         setup_msrs(vmx);
5351
5352         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5353
5354         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5355                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5356                 if (cpu_need_tpr_shadow(vcpu))
5357                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5358                                      __pa(vcpu->arch.apic->regs));
5359                 vmcs_write32(TPR_THRESHOLD, 0);
5360         }
5361
5362         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5363
5364         if (kvm_vcpu_apicv_active(vcpu))
5365                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5366
5367         if (vmx->vpid != 0)
5368                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5369
5370         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5371         vmx->vcpu.arch.cr0 = cr0;
5372         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5373         vmx_set_cr4(vcpu, 0);
5374         vmx_set_efer(vcpu, 0);
5375
5376         update_exception_bitmap(vcpu);
5377
5378         vpid_sync_context(vmx->vpid);
5379 }
5380
5381 /*
5382  * In nested virtualization, check if L1 asked to exit on external interrupts.
5383  * For most existing hypervisors, this will always return true.
5384  */
5385 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5386 {
5387         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5388                 PIN_BASED_EXT_INTR_MASK;
5389 }
5390
5391 /*
5392  * In nested virtualization, check if L1 has set
5393  * VM_EXIT_ACK_INTR_ON_EXIT
5394  */
5395 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5396 {
5397         return get_vmcs12(vcpu)->vm_exit_controls &
5398                 VM_EXIT_ACK_INTR_ON_EXIT;
5399 }
5400
5401 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5402 {
5403         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5404                 PIN_BASED_NMI_EXITING;
5405 }
5406
5407 static void enable_irq_window(struct kvm_vcpu *vcpu)
5408 {
5409         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5410                       CPU_BASED_VIRTUAL_INTR_PENDING);
5411 }
5412
5413 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5414 {
5415         if (!cpu_has_virtual_nmis() ||
5416             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5417                 enable_irq_window(vcpu);
5418                 return;
5419         }
5420
5421         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5422                       CPU_BASED_VIRTUAL_NMI_PENDING);
5423 }
5424
5425 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5426 {
5427         struct vcpu_vmx *vmx = to_vmx(vcpu);
5428         uint32_t intr;
5429         int irq = vcpu->arch.interrupt.nr;
5430
5431         trace_kvm_inj_virq(irq);
5432
5433         ++vcpu->stat.irq_injections;
5434         if (vmx->rmode.vm86_active) {
5435                 int inc_eip = 0;
5436                 if (vcpu->arch.interrupt.soft)
5437                         inc_eip = vcpu->arch.event_exit_inst_len;
5438                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5439                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5440                 return;
5441         }
5442         intr = irq | INTR_INFO_VALID_MASK;
5443         if (vcpu->arch.interrupt.soft) {
5444                 intr |= INTR_TYPE_SOFT_INTR;
5445                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5446                              vmx->vcpu.arch.event_exit_inst_len);
5447         } else
5448                 intr |= INTR_TYPE_EXT_INTR;
5449         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5450 }
5451
5452 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5453 {
5454         struct vcpu_vmx *vmx = to_vmx(vcpu);
5455
5456         if (!is_guest_mode(vcpu)) {
5457                 if (!cpu_has_virtual_nmis()) {
5458                         /*
5459                          * Tracking the NMI-blocked state in software is built upon
5460                          * finding the next open IRQ window. This, in turn, depends on
5461                          * well-behaving guests: They have to keep IRQs disabled at
5462                          * least as long as the NMI handler runs. Otherwise we may
5463                          * cause NMI nesting, maybe breaking the guest. But as this is
5464                          * highly unlikely, we can live with the residual risk.
5465                          */
5466                         vmx->soft_vnmi_blocked = 1;
5467                         vmx->vnmi_blocked_time = 0;
5468                 }
5469
5470                 ++vcpu->stat.nmi_injections;
5471                 vmx->nmi_known_unmasked = false;
5472         }
5473
5474         if (vmx->rmode.vm86_active) {
5475                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5476                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5477                 return;
5478         }
5479
5480         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5481                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5482 }
5483
5484 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5485 {
5486         if (!cpu_has_virtual_nmis())
5487                 return to_vmx(vcpu)->soft_vnmi_blocked;
5488         if (to_vmx(vcpu)->nmi_known_unmasked)
5489                 return false;
5490         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5491 }
5492
5493 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5494 {
5495         struct vcpu_vmx *vmx = to_vmx(vcpu);
5496
5497         if (!cpu_has_virtual_nmis()) {
5498                 if (vmx->soft_vnmi_blocked != masked) {
5499                         vmx->soft_vnmi_blocked = masked;
5500                         vmx->vnmi_blocked_time = 0;
5501                 }
5502         } else {
5503                 vmx->nmi_known_unmasked = !masked;
5504                 if (masked)
5505                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5506                                       GUEST_INTR_STATE_NMI);
5507                 else
5508                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5509                                         GUEST_INTR_STATE_NMI);
5510         }
5511 }
5512
5513 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5514 {
5515         if (to_vmx(vcpu)->nested.nested_run_pending)
5516                 return 0;
5517
5518         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5519                 return 0;
5520
5521         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5522                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5523                    | GUEST_INTR_STATE_NMI));
5524 }
5525
5526 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5527 {
5528         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5529                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5530                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5531                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5532 }
5533
5534 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5535 {
5536         int ret;
5537
5538         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5539                                     PAGE_SIZE * 3);
5540         if (ret)
5541                 return ret;
5542         kvm->arch.tss_addr = addr;
5543         return init_rmode_tss(kvm);
5544 }
5545
5546 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5547 {
5548         switch (vec) {
5549         case BP_VECTOR:
5550                 /*
5551                  * Update instruction length as we may reinject the exception
5552                  * from user space while in guest debugging mode.
5553                  */
5554                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5555                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5556                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5557                         return false;
5558                 /* fall through */
5559         case DB_VECTOR:
5560                 if (vcpu->guest_debug &
5561                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5562                         return false;
5563                 /* fall through */
5564         case DE_VECTOR:
5565         case OF_VECTOR:
5566         case BR_VECTOR:
5567         case UD_VECTOR:
5568         case DF_VECTOR:
5569         case SS_VECTOR:
5570         case GP_VECTOR:
5571         case MF_VECTOR:
5572                 return true;
5573         break;
5574         }
5575         return false;
5576 }
5577
5578 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5579                                   int vec, u32 err_code)
5580 {
5581         /*
5582          * Instruction with address size override prefix opcode 0x67
5583          * Cause the #SS fault with 0 error code in VM86 mode.
5584          */
5585         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5586                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5587                         if (vcpu->arch.halt_request) {
5588                                 vcpu->arch.halt_request = 0;
5589                                 return kvm_vcpu_halt(vcpu);
5590                         }
5591                         return 1;
5592                 }
5593                 return 0;
5594         }
5595
5596         /*
5597          * Forward all other exceptions that are valid in real mode.
5598          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5599          *        the required debugging infrastructure rework.
5600          */
5601         kvm_queue_exception(vcpu, vec);
5602         return 1;
5603 }
5604
5605 /*
5606  * Trigger machine check on the host. We assume all the MSRs are already set up
5607  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5608  * We pass a fake environment to the machine check handler because we want
5609  * the guest to be always treated like user space, no matter what context
5610  * it used internally.
5611  */
5612 static void kvm_machine_check(void)
5613 {
5614 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5615         struct pt_regs regs = {
5616                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5617                 .flags = X86_EFLAGS_IF,
5618         };
5619
5620         do_machine_check(&regs, 0);
5621 #endif
5622 }
5623
5624 static int handle_machine_check(struct kvm_vcpu *vcpu)
5625 {
5626         /* already handled by vcpu_run */
5627         return 1;
5628 }
5629
5630 static int handle_exception(struct kvm_vcpu *vcpu)
5631 {
5632         struct vcpu_vmx *vmx = to_vmx(vcpu);
5633         struct kvm_run *kvm_run = vcpu->run;
5634         u32 intr_info, ex_no, error_code;
5635         unsigned long cr2, rip, dr6;
5636         u32 vect_info;
5637         enum emulation_result er;
5638
5639         vect_info = vmx->idt_vectoring_info;
5640         intr_info = vmx->exit_intr_info;
5641
5642         if (is_machine_check(intr_info))
5643                 return handle_machine_check(vcpu);
5644
5645         if (is_nmi(intr_info))
5646                 return 1;  /* already handled by vmx_vcpu_run() */
5647
5648         if (is_invalid_opcode(intr_info)) {
5649                 if (is_guest_mode(vcpu)) {
5650                         kvm_queue_exception(vcpu, UD_VECTOR);
5651                         return 1;
5652                 }
5653                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5654                 if (er != EMULATE_DONE)
5655                         kvm_queue_exception(vcpu, UD_VECTOR);
5656                 return 1;
5657         }
5658
5659         error_code = 0;
5660         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5661                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5662
5663         /*
5664          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5665          * MMIO, it is better to report an internal error.
5666          * See the comments in vmx_handle_exit.
5667          */
5668         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5669             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5670                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5671                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5672                 vcpu->run->internal.ndata = 3;
5673                 vcpu->run->internal.data[0] = vect_info;
5674                 vcpu->run->internal.data[1] = intr_info;
5675                 vcpu->run->internal.data[2] = error_code;
5676                 return 0;
5677         }
5678
5679         if (is_page_fault(intr_info)) {
5680                 /* EPT won't cause page fault directly */
5681                 BUG_ON(enable_ept);
5682                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5683                 trace_kvm_page_fault(cr2, error_code);
5684
5685                 if (kvm_event_needs_reinjection(vcpu))
5686                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5687                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5688         }
5689
5690         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5691
5692         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5693                 return handle_rmode_exception(vcpu, ex_no, error_code);
5694
5695         switch (ex_no) {
5696         case AC_VECTOR:
5697                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5698                 return 1;
5699         case DB_VECTOR:
5700                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5701                 if (!(vcpu->guest_debug &
5702                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5703                         vcpu->arch.dr6 &= ~15;
5704                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5705                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5706                                 skip_emulated_instruction(vcpu);
5707
5708                         kvm_queue_exception(vcpu, DB_VECTOR);
5709                         return 1;
5710                 }
5711                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5712                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5713                 /* fall through */
5714         case BP_VECTOR:
5715                 /*
5716                  * Update instruction length as we may reinject #BP from
5717                  * user space while in guest debugging mode. Reading it for
5718                  * #DB as well causes no harm, it is not used in that case.
5719                  */
5720                 vmx->vcpu.arch.event_exit_inst_len =
5721                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5722                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5723                 rip = kvm_rip_read(vcpu);
5724                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5725                 kvm_run->debug.arch.exception = ex_no;
5726                 break;
5727         default:
5728                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5729                 kvm_run->ex.exception = ex_no;
5730                 kvm_run->ex.error_code = error_code;
5731                 break;
5732         }
5733         return 0;
5734 }
5735
5736 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5737 {
5738         ++vcpu->stat.irq_exits;
5739         return 1;
5740 }
5741
5742 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5743 {
5744         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5745         return 0;
5746 }
5747
5748 static int handle_io(struct kvm_vcpu *vcpu)
5749 {
5750         unsigned long exit_qualification;
5751         int size, in, string, ret;
5752         unsigned port;
5753
5754         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5755         string = (exit_qualification & 16) != 0;
5756         in = (exit_qualification & 8) != 0;
5757
5758         ++vcpu->stat.io_exits;
5759
5760         if (string || in)
5761                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5762
5763         port = exit_qualification >> 16;
5764         size = (exit_qualification & 7) + 1;
5765
5766         ret = kvm_skip_emulated_instruction(vcpu);
5767
5768         /*
5769          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5770          * KVM_EXIT_DEBUG here.
5771          */
5772         return kvm_fast_pio_out(vcpu, size, port) && ret;
5773 }
5774
5775 static void
5776 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5777 {
5778         /*
5779          * Patch in the VMCALL instruction:
5780          */
5781         hypercall[0] = 0x0f;
5782         hypercall[1] = 0x01;
5783         hypercall[2] = 0xc1;
5784 }
5785
5786 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5787 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5788 {
5789         if (is_guest_mode(vcpu)) {
5790                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5791                 unsigned long orig_val = val;
5792
5793                 /*
5794                  * We get here when L2 changed cr0 in a way that did not change
5795                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5796                  * but did change L0 shadowed bits. So we first calculate the
5797                  * effective cr0 value that L1 would like to write into the
5798                  * hardware. It consists of the L2-owned bits from the new
5799                  * value combined with the L1-owned bits from L1's guest_cr0.
5800                  */
5801                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5802                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5803
5804                 if (!nested_guest_cr0_valid(vcpu, val))
5805                         return 1;
5806
5807                 if (kvm_set_cr0(vcpu, val))
5808                         return 1;
5809                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5810                 return 0;
5811         } else {
5812                 if (to_vmx(vcpu)->nested.vmxon &&
5813                     !nested_host_cr0_valid(vcpu, val))
5814                         return 1;
5815
5816                 return kvm_set_cr0(vcpu, val);
5817         }
5818 }
5819
5820 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5821 {
5822         if (is_guest_mode(vcpu)) {
5823                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5824                 unsigned long orig_val = val;
5825
5826                 /* analogously to handle_set_cr0 */
5827                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5828                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5829                 if (kvm_set_cr4(vcpu, val))
5830                         return 1;
5831                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5832                 return 0;
5833         } else
5834                 return kvm_set_cr4(vcpu, val);
5835 }
5836
5837 static int handle_cr(struct kvm_vcpu *vcpu)
5838 {
5839         unsigned long exit_qualification, val;
5840         int cr;
5841         int reg;
5842         int err;
5843         int ret;
5844
5845         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5846         cr = exit_qualification & 15;
5847         reg = (exit_qualification >> 8) & 15;
5848         switch ((exit_qualification >> 4) & 3) {
5849         case 0: /* mov to cr */
5850                 val = kvm_register_readl(vcpu, reg);
5851                 trace_kvm_cr_write(cr, val);
5852                 switch (cr) {
5853                 case 0:
5854                         err = handle_set_cr0(vcpu, val);
5855                         return kvm_complete_insn_gp(vcpu, err);
5856                 case 3:
5857                         err = kvm_set_cr3(vcpu, val);
5858                         return kvm_complete_insn_gp(vcpu, err);
5859                 case 4:
5860                         err = handle_set_cr4(vcpu, val);
5861                         return kvm_complete_insn_gp(vcpu, err);
5862                 case 8: {
5863                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5864                                 u8 cr8 = (u8)val;
5865                                 err = kvm_set_cr8(vcpu, cr8);
5866                                 ret = kvm_complete_insn_gp(vcpu, err);
5867                                 if (lapic_in_kernel(vcpu))
5868                                         return ret;
5869                                 if (cr8_prev <= cr8)
5870                                         return ret;
5871                                 /*
5872                                  * TODO: we might be squashing a
5873                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5874                                  * KVM_EXIT_DEBUG here.
5875                                  */
5876                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5877                                 return 0;
5878                         }
5879                 }
5880                 break;
5881         case 2: /* clts */
5882                 WARN_ONCE(1, "Guest should always own CR0.TS");
5883                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5884                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5885                 return kvm_skip_emulated_instruction(vcpu);
5886         case 1: /*mov from cr*/
5887                 switch (cr) {
5888                 case 3:
5889                         val = kvm_read_cr3(vcpu);
5890                         kvm_register_write(vcpu, reg, val);
5891                         trace_kvm_cr_read(cr, val);
5892                         return kvm_skip_emulated_instruction(vcpu);
5893                 case 8:
5894                         val = kvm_get_cr8(vcpu);
5895                         kvm_register_write(vcpu, reg, val);
5896                         trace_kvm_cr_read(cr, val);
5897                         return kvm_skip_emulated_instruction(vcpu);
5898                 }
5899                 break;
5900         case 3: /* lmsw */
5901                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5902                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5903                 kvm_lmsw(vcpu, val);
5904
5905                 return kvm_skip_emulated_instruction(vcpu);
5906         default:
5907                 break;
5908         }
5909         vcpu->run->exit_reason = 0;
5910         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5911                (int)(exit_qualification >> 4) & 3, cr);
5912         return 0;
5913 }
5914
5915 static int handle_dr(struct kvm_vcpu *vcpu)
5916 {
5917         unsigned long exit_qualification;
5918         int dr, dr7, reg;
5919
5920         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5921         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5922
5923         /* First, if DR does not exist, trigger UD */
5924         if (!kvm_require_dr(vcpu, dr))
5925                 return 1;
5926
5927         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5928         if (!kvm_require_cpl(vcpu, 0))
5929                 return 1;
5930         dr7 = vmcs_readl(GUEST_DR7);
5931         if (dr7 & DR7_GD) {
5932                 /*
5933                  * As the vm-exit takes precedence over the debug trap, we
5934                  * need to emulate the latter, either for the host or the
5935                  * guest debugging itself.
5936                  */
5937                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5938                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5939                         vcpu->run->debug.arch.dr7 = dr7;
5940                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5941                         vcpu->run->debug.arch.exception = DB_VECTOR;
5942                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5943                         return 0;
5944                 } else {
5945                         vcpu->arch.dr6 &= ~15;
5946                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5947                         kvm_queue_exception(vcpu, DB_VECTOR);
5948                         return 1;
5949                 }
5950         }
5951
5952         if (vcpu->guest_debug == 0) {
5953                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5954                                 CPU_BASED_MOV_DR_EXITING);
5955
5956                 /*
5957                  * No more DR vmexits; force a reload of the debug registers
5958                  * and reenter on this instruction.  The next vmexit will
5959                  * retrieve the full state of the debug registers.
5960                  */
5961                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5962                 return 1;
5963         }
5964
5965         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5966         if (exit_qualification & TYPE_MOV_FROM_DR) {
5967                 unsigned long val;
5968
5969                 if (kvm_get_dr(vcpu, dr, &val))
5970                         return 1;
5971                 kvm_register_write(vcpu, reg, val);
5972         } else
5973                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5974                         return 1;
5975
5976         return kvm_skip_emulated_instruction(vcpu);
5977 }
5978
5979 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5980 {
5981         return vcpu->arch.dr6;
5982 }
5983
5984 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5985 {
5986 }
5987
5988 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5989 {
5990         get_debugreg(vcpu->arch.db[0], 0);
5991         get_debugreg(vcpu->arch.db[1], 1);
5992         get_debugreg(vcpu->arch.db[2], 2);
5993         get_debugreg(vcpu->arch.db[3], 3);
5994         get_debugreg(vcpu->arch.dr6, 6);
5995         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5996
5997         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5998         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5999 }
6000
6001 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6002 {
6003         vmcs_writel(GUEST_DR7, val);
6004 }
6005
6006 static int handle_cpuid(struct kvm_vcpu *vcpu)
6007 {
6008         return kvm_emulate_cpuid(vcpu);
6009 }
6010
6011 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6012 {
6013         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6014         struct msr_data msr_info;
6015
6016         msr_info.index = ecx;
6017         msr_info.host_initiated = false;
6018         if (vmx_get_msr(vcpu, &msr_info)) {
6019                 trace_kvm_msr_read_ex(ecx);
6020                 kvm_inject_gp(vcpu, 0);
6021                 return 1;
6022         }
6023
6024         trace_kvm_msr_read(ecx, msr_info.data);
6025
6026         /* FIXME: handling of bits 32:63 of rax, rdx */
6027         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6028         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6029         return kvm_skip_emulated_instruction(vcpu);
6030 }
6031
6032 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6033 {
6034         struct msr_data msr;
6035         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6036         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6037                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6038
6039         msr.data = data;
6040         msr.index = ecx;
6041         msr.host_initiated = false;
6042         if (kvm_set_msr(vcpu, &msr) != 0) {
6043                 trace_kvm_msr_write_ex(ecx, data);
6044                 kvm_inject_gp(vcpu, 0);
6045                 return 1;
6046         }
6047
6048         trace_kvm_msr_write(ecx, data);
6049         return kvm_skip_emulated_instruction(vcpu);
6050 }
6051
6052 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6053 {
6054         kvm_apic_update_ppr(vcpu);
6055         return 1;
6056 }
6057
6058 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6059 {
6060         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6061                         CPU_BASED_VIRTUAL_INTR_PENDING);
6062
6063         kvm_make_request(KVM_REQ_EVENT, vcpu);
6064
6065         ++vcpu->stat.irq_window_exits;
6066         return 1;
6067 }
6068
6069 static int handle_halt(struct kvm_vcpu *vcpu)
6070 {
6071         return kvm_emulate_halt(vcpu);
6072 }
6073
6074 static int handle_vmcall(struct kvm_vcpu *vcpu)
6075 {
6076         return kvm_emulate_hypercall(vcpu);
6077 }
6078
6079 static int handle_invd(struct kvm_vcpu *vcpu)
6080 {
6081         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6082 }
6083
6084 static int handle_invlpg(struct kvm_vcpu *vcpu)
6085 {
6086         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6087
6088         kvm_mmu_invlpg(vcpu, exit_qualification);
6089         return kvm_skip_emulated_instruction(vcpu);
6090 }
6091
6092 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6093 {
6094         int err;
6095
6096         err = kvm_rdpmc(vcpu);
6097         return kvm_complete_insn_gp(vcpu, err);
6098 }
6099
6100 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6101 {
6102         return kvm_emulate_wbinvd(vcpu);
6103 }
6104
6105 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6106 {
6107         u64 new_bv = kvm_read_edx_eax(vcpu);
6108         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6109
6110         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6111                 return kvm_skip_emulated_instruction(vcpu);
6112         return 1;
6113 }
6114
6115 static int handle_xsaves(struct kvm_vcpu *vcpu)
6116 {
6117         kvm_skip_emulated_instruction(vcpu);
6118         WARN(1, "this should never happen\n");
6119         return 1;
6120 }
6121
6122 static int handle_xrstors(struct kvm_vcpu *vcpu)
6123 {
6124         kvm_skip_emulated_instruction(vcpu);
6125         WARN(1, "this should never happen\n");
6126         return 1;
6127 }
6128
6129 static int handle_apic_access(struct kvm_vcpu *vcpu)
6130 {
6131         if (likely(fasteoi)) {
6132                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6133                 int access_type, offset;
6134
6135                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6136                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6137                 /*
6138                  * Sane guest uses MOV to write EOI, with written value
6139                  * not cared. So make a short-circuit here by avoiding
6140                  * heavy instruction emulation.
6141                  */
6142                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6143                     (offset == APIC_EOI)) {
6144                         kvm_lapic_set_eoi(vcpu);
6145                         return kvm_skip_emulated_instruction(vcpu);
6146                 }
6147         }
6148         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6149 }
6150
6151 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6152 {
6153         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6154         int vector = exit_qualification & 0xff;
6155
6156         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6157         kvm_apic_set_eoi_accelerated(vcpu, vector);
6158         return 1;
6159 }
6160
6161 static int handle_apic_write(struct kvm_vcpu *vcpu)
6162 {
6163         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6164         u32 offset = exit_qualification & 0xfff;
6165
6166         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6167         kvm_apic_write_nodecode(vcpu, offset);
6168         return 1;
6169 }
6170
6171 static int handle_task_switch(struct kvm_vcpu *vcpu)
6172 {
6173         struct vcpu_vmx *vmx = to_vmx(vcpu);
6174         unsigned long exit_qualification;
6175         bool has_error_code = false;
6176         u32 error_code = 0;
6177         u16 tss_selector;
6178         int reason, type, idt_v, idt_index;
6179
6180         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6181         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6182         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6183
6184         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6185
6186         reason = (u32)exit_qualification >> 30;
6187         if (reason == TASK_SWITCH_GATE && idt_v) {
6188                 switch (type) {
6189                 case INTR_TYPE_NMI_INTR:
6190                         vcpu->arch.nmi_injected = false;
6191                         vmx_set_nmi_mask(vcpu, true);
6192                         break;
6193                 case INTR_TYPE_EXT_INTR:
6194                 case INTR_TYPE_SOFT_INTR:
6195                         kvm_clear_interrupt_queue(vcpu);
6196                         break;
6197                 case INTR_TYPE_HARD_EXCEPTION:
6198                         if (vmx->idt_vectoring_info &
6199                             VECTORING_INFO_DELIVER_CODE_MASK) {
6200                                 has_error_code = true;
6201                                 error_code =
6202                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6203                         }
6204                         /* fall through */
6205                 case INTR_TYPE_SOFT_EXCEPTION:
6206                         kvm_clear_exception_queue(vcpu);
6207                         break;
6208                 default:
6209                         break;
6210                 }
6211         }
6212         tss_selector = exit_qualification;
6213
6214         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6215                        type != INTR_TYPE_EXT_INTR &&
6216                        type != INTR_TYPE_NMI_INTR))
6217                 skip_emulated_instruction(vcpu);
6218
6219         if (kvm_task_switch(vcpu, tss_selector,
6220                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6221                             has_error_code, error_code) == EMULATE_FAIL) {
6222                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6223                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6224                 vcpu->run->internal.ndata = 0;
6225                 return 0;
6226         }
6227
6228         /*
6229          * TODO: What about debug traps on tss switch?
6230          *       Are we supposed to inject them and update dr6?
6231          */
6232
6233         return 1;
6234 }
6235
6236 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6237 {
6238         unsigned long exit_qualification;
6239         gpa_t gpa;
6240         u32 error_code;
6241         int gla_validity;
6242
6243         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6244
6245         gla_validity = (exit_qualification >> 7) & 0x3;
6246         if (gla_validity == 0x2) {
6247                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6248                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6249                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6250                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6251                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6252                         (long unsigned int)exit_qualification);
6253                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6254                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6255                 return 0;
6256         }
6257
6258         /*
6259          * EPT violation happened while executing iret from NMI,
6260          * "blocked by NMI" bit has to be set before next VM entry.
6261          * There are errata that may cause this bit to not be set:
6262          * AAK134, BY25.
6263          */
6264         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6265                         cpu_has_virtual_nmis() &&
6266                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6267                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6268
6269         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6270         trace_kvm_page_fault(gpa, exit_qualification);
6271
6272         /* Is it a read fault? */
6273         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6274                      ? PFERR_USER_MASK : 0;
6275         /* Is it a write fault? */
6276         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6277                       ? PFERR_WRITE_MASK : 0;
6278         /* Is it a fetch fault? */
6279         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6280                       ? PFERR_FETCH_MASK : 0;
6281         /* ept page table entry is present? */
6282         error_code |= (exit_qualification &
6283                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6284                         EPT_VIOLATION_EXECUTABLE))
6285                       ? PFERR_PRESENT_MASK : 0;
6286
6287         vcpu->arch.gpa_available = true;
6288         vcpu->arch.exit_qualification = exit_qualification;
6289
6290         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6291 }
6292
6293 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6294 {
6295         int ret;
6296         gpa_t gpa;
6297
6298         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6299         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6300                 trace_kvm_fast_mmio(gpa);
6301                 return kvm_skip_emulated_instruction(vcpu);
6302         }
6303
6304         ret = handle_mmio_page_fault(vcpu, gpa, true);
6305         vcpu->arch.gpa_available = true;
6306         if (likely(ret == RET_MMIO_PF_EMULATE))
6307                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6308                                               EMULATE_DONE;
6309
6310         if (unlikely(ret == RET_MMIO_PF_INVALID))
6311                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6312
6313         if (unlikely(ret == RET_MMIO_PF_RETRY))
6314                 return 1;
6315
6316         /* It is the real ept misconfig */
6317         WARN_ON(1);
6318
6319         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6320         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6321
6322         return 0;
6323 }
6324
6325 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6326 {
6327         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6328                         CPU_BASED_VIRTUAL_NMI_PENDING);
6329         ++vcpu->stat.nmi_window_exits;
6330         kvm_make_request(KVM_REQ_EVENT, vcpu);
6331
6332         return 1;
6333 }
6334
6335 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6336 {
6337         struct vcpu_vmx *vmx = to_vmx(vcpu);
6338         enum emulation_result err = EMULATE_DONE;
6339         int ret = 1;
6340         u32 cpu_exec_ctrl;
6341         bool intr_window_requested;
6342         unsigned count = 130;
6343
6344         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6345         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6346
6347         while (vmx->emulation_required && count-- != 0) {
6348                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6349                         return handle_interrupt_window(&vmx->vcpu);
6350
6351                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6352                         return 1;
6353
6354                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6355
6356                 if (err == EMULATE_USER_EXIT) {
6357                         ++vcpu->stat.mmio_exits;
6358                         ret = 0;
6359                         goto out;
6360                 }
6361
6362                 if (err != EMULATE_DONE) {
6363                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6364                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6365                         vcpu->run->internal.ndata = 0;
6366                         return 0;
6367                 }
6368
6369                 if (vcpu->arch.halt_request) {
6370                         vcpu->arch.halt_request = 0;
6371                         ret = kvm_vcpu_halt(vcpu);
6372                         goto out;
6373                 }
6374
6375                 if (signal_pending(current))
6376                         goto out;
6377                 if (need_resched())
6378                         schedule();
6379         }
6380
6381 out:
6382         return ret;
6383 }
6384
6385 static int __grow_ple_window(int val)
6386 {
6387         if (ple_window_grow < 1)
6388                 return ple_window;
6389
6390         val = min(val, ple_window_actual_max);
6391
6392         if (ple_window_grow < ple_window)
6393                 val *= ple_window_grow;
6394         else
6395                 val += ple_window_grow;
6396
6397         return val;
6398 }
6399
6400 static int __shrink_ple_window(int val, int modifier, int minimum)
6401 {
6402         if (modifier < 1)
6403                 return ple_window;
6404
6405         if (modifier < ple_window)
6406                 val /= modifier;
6407         else
6408                 val -= modifier;
6409
6410         return max(val, minimum);
6411 }
6412
6413 static void grow_ple_window(struct kvm_vcpu *vcpu)
6414 {
6415         struct vcpu_vmx *vmx = to_vmx(vcpu);
6416         int old = vmx->ple_window;
6417
6418         vmx->ple_window = __grow_ple_window(old);
6419
6420         if (vmx->ple_window != old)
6421                 vmx->ple_window_dirty = true;
6422
6423         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6424 }
6425
6426 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6427 {
6428         struct vcpu_vmx *vmx = to_vmx(vcpu);
6429         int old = vmx->ple_window;
6430
6431         vmx->ple_window = __shrink_ple_window(old,
6432                                               ple_window_shrink, ple_window);
6433
6434         if (vmx->ple_window != old)
6435                 vmx->ple_window_dirty = true;
6436
6437         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6438 }
6439
6440 /*
6441  * ple_window_actual_max is computed to be one grow_ple_window() below
6442  * ple_window_max. (See __grow_ple_window for the reason.)
6443  * This prevents overflows, because ple_window_max is int.
6444  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6445  * this process.
6446  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6447  */
6448 static void update_ple_window_actual_max(void)
6449 {
6450         ple_window_actual_max =
6451                         __shrink_ple_window(max(ple_window_max, ple_window),
6452                                             ple_window_grow, INT_MIN);
6453 }
6454
6455 /*
6456  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6457  */
6458 static void wakeup_handler(void)
6459 {
6460         struct kvm_vcpu *vcpu;
6461         int cpu = smp_processor_id();
6462
6463         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6464         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6465                         blocked_vcpu_list) {
6466                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6467
6468                 if (pi_test_on(pi_desc) == 1)
6469                         kvm_vcpu_kick(vcpu);
6470         }
6471         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6472 }
6473
6474 void vmx_enable_tdp(void)
6475 {
6476         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6477                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6478                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6479                 0ull, VMX_EPT_EXECUTABLE_MASK,
6480                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6481                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6482
6483         ept_set_mmio_spte_mask();
6484         kvm_enable_tdp();
6485 }
6486
6487 static __init int hardware_setup(void)
6488 {
6489         int r = -ENOMEM, i, msr;
6490
6491         rdmsrl_safe(MSR_EFER, &host_efer);
6492
6493         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6494                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6495
6496         for (i = 0; i < VMX_BITMAP_NR; i++) {
6497                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6498                 if (!vmx_bitmap[i])
6499                         goto out;
6500         }
6501
6502         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6503         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6504         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6505
6506         /*
6507          * Allow direct access to the PC debug port (it is often used for I/O
6508          * delays, but the vmexits simply slow things down).
6509          */
6510         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6511         clear_bit(0x80, vmx_io_bitmap_a);
6512
6513         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6514
6515         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6516         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6517
6518         if (setup_vmcs_config(&vmcs_config) < 0) {
6519                 r = -EIO;
6520                 goto out;
6521         }
6522
6523         if (boot_cpu_has(X86_FEATURE_NX))
6524                 kvm_enable_efer_bits(EFER_NX);
6525
6526         if (!cpu_has_vmx_vpid())
6527                 enable_vpid = 0;
6528         if (!cpu_has_vmx_shadow_vmcs())
6529                 enable_shadow_vmcs = 0;
6530         if (enable_shadow_vmcs)
6531                 init_vmcs_shadow_fields();
6532
6533         if (!cpu_has_vmx_ept() ||
6534             !cpu_has_vmx_ept_4levels()) {
6535                 enable_ept = 0;
6536                 enable_unrestricted_guest = 0;
6537                 enable_ept_ad_bits = 0;
6538         }
6539
6540         if (!cpu_has_vmx_ept_ad_bits())
6541                 enable_ept_ad_bits = 0;
6542
6543         if (!cpu_has_vmx_unrestricted_guest())
6544                 enable_unrestricted_guest = 0;
6545
6546         if (!cpu_has_vmx_flexpriority())
6547                 flexpriority_enabled = 0;
6548
6549         /*
6550          * set_apic_access_page_addr() is used to reload apic access
6551          * page upon invalidation.  No need to do anything if not
6552          * using the APIC_ACCESS_ADDR VMCS field.
6553          */
6554         if (!flexpriority_enabled)
6555                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6556
6557         if (!cpu_has_vmx_tpr_shadow())
6558                 kvm_x86_ops->update_cr8_intercept = NULL;
6559
6560         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6561                 kvm_disable_largepages();
6562
6563         if (!cpu_has_vmx_ple())
6564                 ple_gap = 0;
6565
6566         if (!cpu_has_vmx_apicv()) {
6567                 enable_apicv = 0;
6568                 kvm_x86_ops->sync_pir_to_irr = NULL;
6569         }
6570
6571         if (cpu_has_vmx_tsc_scaling()) {
6572                 kvm_has_tsc_control = true;
6573                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6574                 kvm_tsc_scaling_ratio_frac_bits = 48;
6575         }
6576
6577         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6578         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6579         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6580         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6581         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6582         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6583         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6584
6585         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6586                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6587         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6588                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6589         memcpy(vmx_msr_bitmap_legacy_x2apic,
6590                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6591         memcpy(vmx_msr_bitmap_longmode_x2apic,
6592                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6593
6594         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6595
6596         for (msr = 0x800; msr <= 0x8ff; msr++) {
6597                 if (msr == 0x839 /* TMCCT */)
6598                         continue;
6599                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6600         }
6601
6602         /*
6603          * TPR reads and writes can be virtualized even if virtual interrupt
6604          * delivery is not in use.
6605          */
6606         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6607         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6608
6609         /* EOI */
6610         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6611         /* SELF-IPI */
6612         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6613
6614         if (enable_ept)
6615                 vmx_enable_tdp();
6616         else
6617                 kvm_disable_tdp();
6618
6619         update_ple_window_actual_max();
6620
6621         /*
6622          * Only enable PML when hardware supports PML feature, and both EPT
6623          * and EPT A/D bit features are enabled -- PML depends on them to work.
6624          */
6625         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6626                 enable_pml = 0;
6627
6628         if (!enable_pml) {
6629                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6630                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6631                 kvm_x86_ops->flush_log_dirty = NULL;
6632                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6633         }
6634
6635         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6636                 u64 vmx_msr;
6637
6638                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6639                 cpu_preemption_timer_multi =
6640                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6641         } else {
6642                 kvm_x86_ops->set_hv_timer = NULL;
6643                 kvm_x86_ops->cancel_hv_timer = NULL;
6644         }
6645
6646         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6647
6648         kvm_mce_cap_supported |= MCG_LMCE_P;
6649
6650         return alloc_kvm_area();
6651
6652 out:
6653         for (i = 0; i < VMX_BITMAP_NR; i++)
6654                 free_page((unsigned long)vmx_bitmap[i]);
6655
6656     return r;
6657 }
6658
6659 static __exit void hardware_unsetup(void)
6660 {
6661         int i;
6662
6663         for (i = 0; i < VMX_BITMAP_NR; i++)
6664                 free_page((unsigned long)vmx_bitmap[i]);
6665
6666         free_kvm_area();
6667 }
6668
6669 /*
6670  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6671  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6672  */
6673 static int handle_pause(struct kvm_vcpu *vcpu)
6674 {
6675         if (ple_gap)
6676                 grow_ple_window(vcpu);
6677
6678         kvm_vcpu_on_spin(vcpu);
6679         return kvm_skip_emulated_instruction(vcpu);
6680 }
6681
6682 static int handle_nop(struct kvm_vcpu *vcpu)
6683 {
6684         return kvm_skip_emulated_instruction(vcpu);
6685 }
6686
6687 static int handle_mwait(struct kvm_vcpu *vcpu)
6688 {
6689         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6690         return handle_nop(vcpu);
6691 }
6692
6693 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6694 {
6695         return 1;
6696 }
6697
6698 static int handle_monitor(struct kvm_vcpu *vcpu)
6699 {
6700         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6701         return handle_nop(vcpu);
6702 }
6703
6704 /*
6705  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6706  * We could reuse a single VMCS for all the L2 guests, but we also want the
6707  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6708  * allows keeping them loaded on the processor, and in the future will allow
6709  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6710  * every entry if they never change.
6711  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6712  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6713  *
6714  * The following functions allocate and free a vmcs02 in this pool.
6715  */
6716
6717 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6718 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6719 {
6720         struct vmcs02_list *item;
6721         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6722                 if (item->vmptr == vmx->nested.current_vmptr) {
6723                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6724                         return &item->vmcs02;
6725                 }
6726
6727         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6728                 /* Recycle the least recently used VMCS. */
6729                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6730                                        struct vmcs02_list, list);
6731                 item->vmptr = vmx->nested.current_vmptr;
6732                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6733                 return &item->vmcs02;
6734         }
6735
6736         /* Create a new VMCS */
6737         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6738         if (!item)
6739                 return NULL;
6740         item->vmcs02.vmcs = alloc_vmcs();
6741         item->vmcs02.shadow_vmcs = NULL;
6742         if (!item->vmcs02.vmcs) {
6743                 kfree(item);
6744                 return NULL;
6745         }
6746         loaded_vmcs_init(&item->vmcs02);
6747         item->vmptr = vmx->nested.current_vmptr;
6748         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6749         vmx->nested.vmcs02_num++;
6750         return &item->vmcs02;
6751 }
6752
6753 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6754 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6755 {
6756         struct vmcs02_list *item;
6757         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6758                 if (item->vmptr == vmptr) {
6759                         free_loaded_vmcs(&item->vmcs02);
6760                         list_del(&item->list);
6761                         kfree(item);
6762                         vmx->nested.vmcs02_num--;
6763                         return;
6764                 }
6765 }
6766
6767 /*
6768  * Free all VMCSs saved for this vcpu, except the one pointed by
6769  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6770  * must be &vmx->vmcs01.
6771  */
6772 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6773 {
6774         struct vmcs02_list *item, *n;
6775
6776         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6777         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6778                 /*
6779                  * Something will leak if the above WARN triggers.  Better than
6780                  * a use-after-free.
6781                  */
6782                 if (vmx->loaded_vmcs == &item->vmcs02)
6783                         continue;
6784
6785                 free_loaded_vmcs(&item->vmcs02);
6786                 list_del(&item->list);
6787                 kfree(item);
6788                 vmx->nested.vmcs02_num--;
6789         }
6790 }
6791
6792 /*
6793  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6794  * set the success or error code of an emulated VMX instruction, as specified
6795  * by Vol 2B, VMX Instruction Reference, "Conventions".
6796  */
6797 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6798 {
6799         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6800                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6801                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6802 }
6803
6804 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6805 {
6806         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6807                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6808                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6809                         | X86_EFLAGS_CF);
6810 }
6811
6812 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6813                                         u32 vm_instruction_error)
6814 {
6815         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6816                 /*
6817                  * failValid writes the error number to the current VMCS, which
6818                  * can't be done there isn't a current VMCS.
6819                  */
6820                 nested_vmx_failInvalid(vcpu);
6821                 return;
6822         }
6823         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6824                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6825                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6826                         | X86_EFLAGS_ZF);
6827         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6828         /*
6829          * We don't need to force a shadow sync because
6830          * VM_INSTRUCTION_ERROR is not shadowed
6831          */
6832 }
6833
6834 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6835 {
6836         /* TODO: not to reset guest simply here. */
6837         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6838         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6839 }
6840
6841 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6842 {
6843         struct vcpu_vmx *vmx =
6844                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6845
6846         vmx->nested.preemption_timer_expired = true;
6847         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6848         kvm_vcpu_kick(&vmx->vcpu);
6849
6850         return HRTIMER_NORESTART;
6851 }
6852
6853 /*
6854  * Decode the memory-address operand of a vmx instruction, as recorded on an
6855  * exit caused by such an instruction (run by a guest hypervisor).
6856  * On success, returns 0. When the operand is invalid, returns 1 and throws
6857  * #UD or #GP.
6858  */
6859 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6860                                  unsigned long exit_qualification,
6861                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6862 {
6863         gva_t off;
6864         bool exn;
6865         struct kvm_segment s;
6866
6867         /*
6868          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6869          * Execution", on an exit, vmx_instruction_info holds most of the
6870          * addressing components of the operand. Only the displacement part
6871          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6872          * For how an actual address is calculated from all these components,
6873          * refer to Vol. 1, "Operand Addressing".
6874          */
6875         int  scaling = vmx_instruction_info & 3;
6876         int  addr_size = (vmx_instruction_info >> 7) & 7;
6877         bool is_reg = vmx_instruction_info & (1u << 10);
6878         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6879         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6880         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6881         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6882         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6883
6884         if (is_reg) {
6885                 kvm_queue_exception(vcpu, UD_VECTOR);
6886                 return 1;
6887         }
6888
6889         /* Addr = segment_base + offset */
6890         /* offset = base + [index * scale] + displacement */
6891         off = exit_qualification; /* holds the displacement */
6892         if (base_is_valid)
6893                 off += kvm_register_read(vcpu, base_reg);
6894         if (index_is_valid)
6895                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6896         vmx_get_segment(vcpu, &s, seg_reg);
6897         *ret = s.base + off;
6898
6899         if (addr_size == 1) /* 32 bit */
6900                 *ret &= 0xffffffff;
6901
6902         /* Checks for #GP/#SS exceptions. */
6903         exn = false;
6904         if (is_long_mode(vcpu)) {
6905                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6906                  * non-canonical form. This is the only check on the memory
6907                  * destination for long mode!
6908                  */
6909                 exn = is_noncanonical_address(*ret);
6910         } else if (is_protmode(vcpu)) {
6911                 /* Protected mode: apply checks for segment validity in the
6912                  * following order:
6913                  * - segment type check (#GP(0) may be thrown)
6914                  * - usability check (#GP(0)/#SS(0))
6915                  * - limit check (#GP(0)/#SS(0))
6916                  */
6917                 if (wr)
6918                         /* #GP(0) if the destination operand is located in a
6919                          * read-only data segment or any code segment.
6920                          */
6921                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6922                 else
6923                         /* #GP(0) if the source operand is located in an
6924                          * execute-only code segment
6925                          */
6926                         exn = ((s.type & 0xa) == 8);
6927                 if (exn) {
6928                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6929                         return 1;
6930                 }
6931                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6932                  */
6933                 exn = (s.unusable != 0);
6934                 /* Protected mode: #GP(0)/#SS(0) if the memory
6935                  * operand is outside the segment limit.
6936                  */
6937                 exn = exn || (off + sizeof(u64) > s.limit);
6938         }
6939         if (exn) {
6940                 kvm_queue_exception_e(vcpu,
6941                                       seg_reg == VCPU_SREG_SS ?
6942                                                 SS_VECTOR : GP_VECTOR,
6943                                       0);
6944                 return 1;
6945         }
6946
6947         return 0;
6948 }
6949
6950 /*
6951  * This function performs the various checks including
6952  * - if it's 4KB aligned
6953  * - No bits beyond the physical address width are set
6954  * - Returns 0 on success or else 1
6955  * (Intel SDM Section 30.3)
6956  */
6957 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6958                                   gpa_t *vmpointer)
6959 {
6960         gva_t gva;
6961         gpa_t vmptr;
6962         struct x86_exception e;
6963         struct page *page;
6964         struct vcpu_vmx *vmx = to_vmx(vcpu);
6965         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6966
6967         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6968                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6969                 return 1;
6970
6971         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6972                                 sizeof(vmptr), &e)) {
6973                 kvm_inject_page_fault(vcpu, &e);
6974                 return 1;
6975         }
6976
6977         switch (exit_reason) {
6978         case EXIT_REASON_VMON:
6979                 /*
6980                  * SDM 3: 24.11.5
6981                  * The first 4 bytes of VMXON region contain the supported
6982                  * VMCS revision identifier
6983                  *
6984                  * Note - IA32_VMX_BASIC[48] will never be 1
6985                  * for the nested case;
6986                  * which replaces physical address width with 32
6987                  *
6988                  */
6989                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6990                         nested_vmx_failInvalid(vcpu);
6991                         return kvm_skip_emulated_instruction(vcpu);
6992                 }
6993
6994                 page = nested_get_page(vcpu, vmptr);
6995                 if (page == NULL) {
6996                         nested_vmx_failInvalid(vcpu);
6997                         return kvm_skip_emulated_instruction(vcpu);
6998                 }
6999                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7000                         kunmap(page);
7001                         nested_release_page_clean(page);
7002                         nested_vmx_failInvalid(vcpu);
7003                         return kvm_skip_emulated_instruction(vcpu);
7004                 }
7005                 kunmap(page);
7006                 nested_release_page_clean(page);
7007                 vmx->nested.vmxon_ptr = vmptr;
7008                 break;
7009         case EXIT_REASON_VMCLEAR:
7010                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7011                         nested_vmx_failValid(vcpu,
7012                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7013                         return kvm_skip_emulated_instruction(vcpu);
7014                 }
7015
7016                 if (vmptr == vmx->nested.vmxon_ptr) {
7017                         nested_vmx_failValid(vcpu,
7018                                              VMXERR_VMCLEAR_VMXON_POINTER);
7019                         return kvm_skip_emulated_instruction(vcpu);
7020                 }
7021                 break;
7022         case EXIT_REASON_VMPTRLD:
7023                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7024                         nested_vmx_failValid(vcpu,
7025                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7026                         return kvm_skip_emulated_instruction(vcpu);
7027                 }
7028
7029                 if (vmptr == vmx->nested.vmxon_ptr) {
7030                         nested_vmx_failValid(vcpu,
7031                                              VMXERR_VMPTRLD_VMXON_POINTER);
7032                         return kvm_skip_emulated_instruction(vcpu);
7033                 }
7034                 break;
7035         default:
7036                 return 1; /* shouldn't happen */
7037         }
7038
7039         if (vmpointer)
7040                 *vmpointer = vmptr;
7041         return 0;
7042 }
7043
7044 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7045 {
7046         struct vcpu_vmx *vmx = to_vmx(vcpu);
7047         struct vmcs *shadow_vmcs;
7048
7049         if (cpu_has_vmx_msr_bitmap()) {
7050                 vmx->nested.msr_bitmap =
7051                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7052                 if (!vmx->nested.msr_bitmap)
7053                         goto out_msr_bitmap;
7054         }
7055
7056         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7057         if (!vmx->nested.cached_vmcs12)
7058                 goto out_cached_vmcs12;
7059
7060         if (enable_shadow_vmcs) {
7061                 shadow_vmcs = alloc_vmcs();
7062                 if (!shadow_vmcs)
7063                         goto out_shadow_vmcs;
7064                 /* mark vmcs as shadow */
7065                 shadow_vmcs->revision_id |= (1u << 31);
7066                 /* init shadow vmcs */
7067                 vmcs_clear(shadow_vmcs);
7068                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7069         }
7070
7071         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7072         vmx->nested.vmcs02_num = 0;
7073
7074         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7075                      HRTIMER_MODE_REL_PINNED);
7076         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7077
7078         vmx->nested.vmxon = true;
7079         return 0;
7080
7081 out_shadow_vmcs:
7082         kfree(vmx->nested.cached_vmcs12);
7083
7084 out_cached_vmcs12:
7085         free_page((unsigned long)vmx->nested.msr_bitmap);
7086
7087 out_msr_bitmap:
7088         return -ENOMEM;
7089 }
7090
7091 /*
7092  * Emulate the VMXON instruction.
7093  * Currently, we just remember that VMX is active, and do not save or even
7094  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7095  * do not currently need to store anything in that guest-allocated memory
7096  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7097  * argument is different from the VMXON pointer (which the spec says they do).
7098  */
7099 static int handle_vmon(struct kvm_vcpu *vcpu)
7100 {
7101         int ret;
7102         struct kvm_segment cs;
7103         struct vcpu_vmx *vmx = to_vmx(vcpu);
7104         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7105                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7106
7107         /* The Intel VMX Instruction Reference lists a bunch of bits that
7108          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7109          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7110          * Otherwise, we should fail with #UD. We test these now:
7111          */
7112         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7113             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7114             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7115                 kvm_queue_exception(vcpu, UD_VECTOR);
7116                 return 1;
7117         }
7118
7119         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7120         if (is_long_mode(vcpu) && !cs.l) {
7121                 kvm_queue_exception(vcpu, UD_VECTOR);
7122                 return 1;
7123         }
7124
7125         if (vmx_get_cpl(vcpu)) {
7126                 kvm_inject_gp(vcpu, 0);
7127                 return 1;
7128         }
7129
7130         if (vmx->nested.vmxon) {
7131                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7132                 return kvm_skip_emulated_instruction(vcpu);
7133         }
7134
7135         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7136                         != VMXON_NEEDED_FEATURES) {
7137                 kvm_inject_gp(vcpu, 0);
7138                 return 1;
7139         }
7140
7141         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7142                 return 1;
7143
7144         ret = enter_vmx_operation(vcpu);
7145         if (ret)
7146                 return ret;
7147
7148         nested_vmx_succeed(vcpu);
7149         return kvm_skip_emulated_instruction(vcpu);
7150 }
7151
7152 /*
7153  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7154  * for running VMX instructions (except VMXON, whose prerequisites are
7155  * slightly different). It also specifies what exception to inject otherwise.
7156  */
7157 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7158 {
7159         struct kvm_segment cs;
7160         struct vcpu_vmx *vmx = to_vmx(vcpu);
7161
7162         if (!vmx->nested.vmxon) {
7163                 kvm_queue_exception(vcpu, UD_VECTOR);
7164                 return 0;
7165         }
7166
7167         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7168         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7169             (is_long_mode(vcpu) && !cs.l)) {
7170                 kvm_queue_exception(vcpu, UD_VECTOR);
7171                 return 0;
7172         }
7173
7174         if (vmx_get_cpl(vcpu)) {
7175                 kvm_inject_gp(vcpu, 0);
7176                 return 0;
7177         }
7178
7179         return 1;
7180 }
7181
7182 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7183 {
7184         if (vmx->nested.current_vmptr == -1ull)
7185                 return;
7186
7187         /* current_vmptr and current_vmcs12 are always set/reset together */
7188         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7189                 return;
7190
7191         if (enable_shadow_vmcs) {
7192                 /* copy to memory all shadowed fields in case
7193                    they were modified */
7194                 copy_shadow_to_vmcs12(vmx);
7195                 vmx->nested.sync_shadow_vmcs = false;
7196                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7197                                 SECONDARY_EXEC_SHADOW_VMCS);
7198                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7199         }
7200         vmx->nested.posted_intr_nv = -1;
7201
7202         /* Flush VMCS12 to guest memory */
7203         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7204                VMCS12_SIZE);
7205
7206         kunmap(vmx->nested.current_vmcs12_page);
7207         nested_release_page(vmx->nested.current_vmcs12_page);
7208         vmx->nested.current_vmptr = -1ull;
7209         vmx->nested.current_vmcs12 = NULL;
7210 }
7211
7212 /*
7213  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7214  * just stops using VMX.
7215  */
7216 static void free_nested(struct vcpu_vmx *vmx)
7217 {
7218         if (!vmx->nested.vmxon)
7219                 return;
7220
7221         vmx->nested.vmxon = false;
7222         free_vpid(vmx->nested.vpid02);
7223         nested_release_vmcs12(vmx);
7224         if (vmx->nested.msr_bitmap) {
7225                 free_page((unsigned long)vmx->nested.msr_bitmap);
7226                 vmx->nested.msr_bitmap = NULL;
7227         }
7228         if (enable_shadow_vmcs) {
7229                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7230                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7231                 vmx->vmcs01.shadow_vmcs = NULL;
7232         }
7233         kfree(vmx->nested.cached_vmcs12);
7234         /* Unpin physical memory we referred to in current vmcs02 */
7235         if (vmx->nested.apic_access_page) {
7236                 nested_release_page(vmx->nested.apic_access_page);
7237                 vmx->nested.apic_access_page = NULL;
7238         }
7239         if (vmx->nested.virtual_apic_page) {
7240                 nested_release_page(vmx->nested.virtual_apic_page);
7241                 vmx->nested.virtual_apic_page = NULL;
7242         }
7243         if (vmx->nested.pi_desc_page) {
7244                 kunmap(vmx->nested.pi_desc_page);
7245                 nested_release_page(vmx->nested.pi_desc_page);
7246                 vmx->nested.pi_desc_page = NULL;
7247                 vmx->nested.pi_desc = NULL;
7248         }
7249
7250         nested_free_all_saved_vmcss(vmx);
7251 }
7252
7253 /* Emulate the VMXOFF instruction */
7254 static int handle_vmoff(struct kvm_vcpu *vcpu)
7255 {
7256         if (!nested_vmx_check_permission(vcpu))
7257                 return 1;
7258         free_nested(to_vmx(vcpu));
7259         nested_vmx_succeed(vcpu);
7260         return kvm_skip_emulated_instruction(vcpu);
7261 }
7262
7263 /* Emulate the VMCLEAR instruction */
7264 static int handle_vmclear(struct kvm_vcpu *vcpu)
7265 {
7266         struct vcpu_vmx *vmx = to_vmx(vcpu);
7267         gpa_t vmptr;
7268         struct vmcs12 *vmcs12;
7269         struct page *page;
7270
7271         if (!nested_vmx_check_permission(vcpu))
7272                 return 1;
7273
7274         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7275                 return 1;
7276
7277         if (vmptr == vmx->nested.current_vmptr)
7278                 nested_release_vmcs12(vmx);
7279
7280         page = nested_get_page(vcpu, vmptr);
7281         if (page == NULL) {
7282                 /*
7283                  * For accurate processor emulation, VMCLEAR beyond available
7284                  * physical memory should do nothing at all. However, it is
7285                  * possible that a nested vmx bug, not a guest hypervisor bug,
7286                  * resulted in this case, so let's shut down before doing any
7287                  * more damage:
7288                  */
7289                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7290                 return 1;
7291         }
7292         vmcs12 = kmap(page);
7293         vmcs12->launch_state = 0;
7294         kunmap(page);
7295         nested_release_page(page);
7296
7297         nested_free_vmcs02(vmx, vmptr);
7298
7299         nested_vmx_succeed(vcpu);
7300         return kvm_skip_emulated_instruction(vcpu);
7301 }
7302
7303 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7304
7305 /* Emulate the VMLAUNCH instruction */
7306 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7307 {
7308         return nested_vmx_run(vcpu, true);
7309 }
7310
7311 /* Emulate the VMRESUME instruction */
7312 static int handle_vmresume(struct kvm_vcpu *vcpu)
7313 {
7314
7315         return nested_vmx_run(vcpu, false);
7316 }
7317
7318 enum vmcs_field_type {
7319         VMCS_FIELD_TYPE_U16 = 0,
7320         VMCS_FIELD_TYPE_U64 = 1,
7321         VMCS_FIELD_TYPE_U32 = 2,
7322         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7323 };
7324
7325 static inline int vmcs_field_type(unsigned long field)
7326 {
7327         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7328                 return VMCS_FIELD_TYPE_U32;
7329         return (field >> 13) & 0x3 ;
7330 }
7331
7332 static inline int vmcs_field_readonly(unsigned long field)
7333 {
7334         return (((field >> 10) & 0x3) == 1);
7335 }
7336
7337 /*
7338  * Read a vmcs12 field. Since these can have varying lengths and we return
7339  * one type, we chose the biggest type (u64) and zero-extend the return value
7340  * to that size. Note that the caller, handle_vmread, might need to use only
7341  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7342  * 64-bit fields are to be returned).
7343  */
7344 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7345                                   unsigned long field, u64 *ret)
7346 {
7347         short offset = vmcs_field_to_offset(field);
7348         char *p;
7349
7350         if (offset < 0)
7351                 return offset;
7352
7353         p = ((char *)(get_vmcs12(vcpu))) + offset;
7354
7355         switch (vmcs_field_type(field)) {
7356         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7357                 *ret = *((natural_width *)p);
7358                 return 0;
7359         case VMCS_FIELD_TYPE_U16:
7360                 *ret = *((u16 *)p);
7361                 return 0;
7362         case VMCS_FIELD_TYPE_U32:
7363                 *ret = *((u32 *)p);
7364                 return 0;
7365         case VMCS_FIELD_TYPE_U64:
7366                 *ret = *((u64 *)p);
7367                 return 0;
7368         default:
7369                 WARN_ON(1);
7370                 return -ENOENT;
7371         }
7372 }
7373
7374
7375 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7376                                    unsigned long field, u64 field_value){
7377         short offset = vmcs_field_to_offset(field);
7378         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7379         if (offset < 0)
7380                 return offset;
7381
7382         switch (vmcs_field_type(field)) {
7383         case VMCS_FIELD_TYPE_U16:
7384                 *(u16 *)p = field_value;
7385                 return 0;
7386         case VMCS_FIELD_TYPE_U32:
7387                 *(u32 *)p = field_value;
7388                 return 0;
7389         case VMCS_FIELD_TYPE_U64:
7390                 *(u64 *)p = field_value;
7391                 return 0;
7392         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7393                 *(natural_width *)p = field_value;
7394                 return 0;
7395         default:
7396                 WARN_ON(1);
7397                 return -ENOENT;
7398         }
7399
7400 }
7401
7402 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7403 {
7404         int i;
7405         unsigned long field;
7406         u64 field_value;
7407         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7408         const unsigned long *fields = shadow_read_write_fields;
7409         const int num_fields = max_shadow_read_write_fields;
7410
7411         preempt_disable();
7412
7413         vmcs_load(shadow_vmcs);
7414
7415         for (i = 0; i < num_fields; i++) {
7416                 field = fields[i];
7417                 switch (vmcs_field_type(field)) {
7418                 case VMCS_FIELD_TYPE_U16:
7419                         field_value = vmcs_read16(field);
7420                         break;
7421                 case VMCS_FIELD_TYPE_U32:
7422                         field_value = vmcs_read32(field);
7423                         break;
7424                 case VMCS_FIELD_TYPE_U64:
7425                         field_value = vmcs_read64(field);
7426                         break;
7427                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7428                         field_value = vmcs_readl(field);
7429                         break;
7430                 default:
7431                         WARN_ON(1);
7432                         continue;
7433                 }
7434                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7435         }
7436
7437         vmcs_clear(shadow_vmcs);
7438         vmcs_load(vmx->loaded_vmcs->vmcs);
7439
7440         preempt_enable();
7441 }
7442
7443 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7444 {
7445         const unsigned long *fields[] = {
7446                 shadow_read_write_fields,
7447                 shadow_read_only_fields
7448         };
7449         const int max_fields[] = {
7450                 max_shadow_read_write_fields,
7451                 max_shadow_read_only_fields
7452         };
7453         int i, q;
7454         unsigned long field;
7455         u64 field_value = 0;
7456         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7457
7458         vmcs_load(shadow_vmcs);
7459
7460         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7461                 for (i = 0; i < max_fields[q]; i++) {
7462                         field = fields[q][i];
7463                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7464
7465                         switch (vmcs_field_type(field)) {
7466                         case VMCS_FIELD_TYPE_U16:
7467                                 vmcs_write16(field, (u16)field_value);
7468                                 break;
7469                         case VMCS_FIELD_TYPE_U32:
7470                                 vmcs_write32(field, (u32)field_value);
7471                                 break;
7472                         case VMCS_FIELD_TYPE_U64:
7473                                 vmcs_write64(field, (u64)field_value);
7474                                 break;
7475                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7476                                 vmcs_writel(field, (long)field_value);
7477                                 break;
7478                         default:
7479                                 WARN_ON(1);
7480                                 break;
7481                         }
7482                 }
7483         }
7484
7485         vmcs_clear(shadow_vmcs);
7486         vmcs_load(vmx->loaded_vmcs->vmcs);
7487 }
7488
7489 /*
7490  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7491  * used before) all generate the same failure when it is missing.
7492  */
7493 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7494 {
7495         struct vcpu_vmx *vmx = to_vmx(vcpu);
7496         if (vmx->nested.current_vmptr == -1ull) {
7497                 nested_vmx_failInvalid(vcpu);
7498                 return 0;
7499         }
7500         return 1;
7501 }
7502
7503 static int handle_vmread(struct kvm_vcpu *vcpu)
7504 {
7505         unsigned long field;
7506         u64 field_value;
7507         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7508         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7509         gva_t gva = 0;
7510
7511         if (!nested_vmx_check_permission(vcpu))
7512                 return 1;
7513
7514         if (!nested_vmx_check_vmcs12(vcpu))
7515                 return kvm_skip_emulated_instruction(vcpu);
7516
7517         /* Decode instruction info and find the field to read */
7518         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7519         /* Read the field, zero-extended to a u64 field_value */
7520         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7521                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7522                 return kvm_skip_emulated_instruction(vcpu);
7523         }
7524         /*
7525          * Now copy part of this value to register or memory, as requested.
7526          * Note that the number of bits actually copied is 32 or 64 depending
7527          * on the guest's mode (32 or 64 bit), not on the given field's length.
7528          */
7529         if (vmx_instruction_info & (1u << 10)) {
7530                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7531                         field_value);
7532         } else {
7533                 if (get_vmx_mem_address(vcpu, exit_qualification,
7534                                 vmx_instruction_info, true, &gva))
7535                         return 1;
7536                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7537                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7538                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7539         }
7540
7541         nested_vmx_succeed(vcpu);
7542         return kvm_skip_emulated_instruction(vcpu);
7543 }
7544
7545
7546 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7547 {
7548         unsigned long field;
7549         gva_t gva;
7550         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7551         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7552         /* The value to write might be 32 or 64 bits, depending on L1's long
7553          * mode, and eventually we need to write that into a field of several
7554          * possible lengths. The code below first zero-extends the value to 64
7555          * bit (field_value), and then copies only the appropriate number of
7556          * bits into the vmcs12 field.
7557          */
7558         u64 field_value = 0;
7559         struct x86_exception e;
7560
7561         if (!nested_vmx_check_permission(vcpu))
7562                 return 1;
7563
7564         if (!nested_vmx_check_vmcs12(vcpu))
7565                 return kvm_skip_emulated_instruction(vcpu);
7566
7567         if (vmx_instruction_info & (1u << 10))
7568                 field_value = kvm_register_readl(vcpu,
7569                         (((vmx_instruction_info) >> 3) & 0xf));
7570         else {
7571                 if (get_vmx_mem_address(vcpu, exit_qualification,
7572                                 vmx_instruction_info, false, &gva))
7573                         return 1;
7574                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7575                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7576                         kvm_inject_page_fault(vcpu, &e);
7577                         return 1;
7578                 }
7579         }
7580
7581
7582         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7583         if (vmcs_field_readonly(field)) {
7584                 nested_vmx_failValid(vcpu,
7585                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7586                 return kvm_skip_emulated_instruction(vcpu);
7587         }
7588
7589         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7590                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7591                 return kvm_skip_emulated_instruction(vcpu);
7592         }
7593
7594         nested_vmx_succeed(vcpu);
7595         return kvm_skip_emulated_instruction(vcpu);
7596 }
7597
7598 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7599 {
7600         vmx->nested.current_vmptr = vmptr;
7601         if (enable_shadow_vmcs) {
7602                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7603                               SECONDARY_EXEC_SHADOW_VMCS);
7604                 vmcs_write64(VMCS_LINK_POINTER,
7605                              __pa(vmx->vmcs01.shadow_vmcs));
7606                 vmx->nested.sync_shadow_vmcs = true;
7607         }
7608 }
7609
7610 /* Emulate the VMPTRLD instruction */
7611 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7612 {
7613         struct vcpu_vmx *vmx = to_vmx(vcpu);
7614         gpa_t vmptr;
7615
7616         if (!nested_vmx_check_permission(vcpu))
7617                 return 1;
7618
7619         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7620                 return 1;
7621
7622         if (vmx->nested.current_vmptr != vmptr) {
7623                 struct vmcs12 *new_vmcs12;
7624                 struct page *page;
7625                 page = nested_get_page(vcpu, vmptr);
7626                 if (page == NULL) {
7627                         nested_vmx_failInvalid(vcpu);
7628                         return kvm_skip_emulated_instruction(vcpu);
7629                 }
7630                 new_vmcs12 = kmap(page);
7631                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7632                         kunmap(page);
7633                         nested_release_page_clean(page);
7634                         nested_vmx_failValid(vcpu,
7635                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7636                         return kvm_skip_emulated_instruction(vcpu);
7637                 }
7638
7639                 nested_release_vmcs12(vmx);
7640                 vmx->nested.current_vmcs12 = new_vmcs12;
7641                 vmx->nested.current_vmcs12_page = page;
7642                 /*
7643                  * Load VMCS12 from guest memory since it is not already
7644                  * cached.
7645                  */
7646                 memcpy(vmx->nested.cached_vmcs12,
7647                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7648                 set_current_vmptr(vmx, vmptr);
7649         }
7650
7651         nested_vmx_succeed(vcpu);
7652         return kvm_skip_emulated_instruction(vcpu);
7653 }
7654
7655 /* Emulate the VMPTRST instruction */
7656 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7657 {
7658         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7659         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7660         gva_t vmcs_gva;
7661         struct x86_exception e;
7662
7663         if (!nested_vmx_check_permission(vcpu))
7664                 return 1;
7665
7666         if (get_vmx_mem_address(vcpu, exit_qualification,
7667                         vmx_instruction_info, true, &vmcs_gva))
7668                 return 1;
7669         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7670         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7671                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7672                                  sizeof(u64), &e)) {
7673                 kvm_inject_page_fault(vcpu, &e);
7674                 return 1;
7675         }
7676         nested_vmx_succeed(vcpu);
7677         return kvm_skip_emulated_instruction(vcpu);
7678 }
7679
7680 /* Emulate the INVEPT instruction */
7681 static int handle_invept(struct kvm_vcpu *vcpu)
7682 {
7683         struct vcpu_vmx *vmx = to_vmx(vcpu);
7684         u32 vmx_instruction_info, types;
7685         unsigned long type;
7686         gva_t gva;
7687         struct x86_exception e;
7688         struct {
7689                 u64 eptp, gpa;
7690         } operand;
7691
7692         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7693               SECONDARY_EXEC_ENABLE_EPT) ||
7694             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7695                 kvm_queue_exception(vcpu, UD_VECTOR);
7696                 return 1;
7697         }
7698
7699         if (!nested_vmx_check_permission(vcpu))
7700                 return 1;
7701
7702         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7703                 kvm_queue_exception(vcpu, UD_VECTOR);
7704                 return 1;
7705         }
7706
7707         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7708         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7709
7710         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7711
7712         if (type >= 32 || !(types & (1 << type))) {
7713                 nested_vmx_failValid(vcpu,
7714                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7715                 return kvm_skip_emulated_instruction(vcpu);
7716         }
7717
7718         /* According to the Intel VMX instruction reference, the memory
7719          * operand is read even if it isn't needed (e.g., for type==global)
7720          */
7721         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7722                         vmx_instruction_info, false, &gva))
7723                 return 1;
7724         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7725                                 sizeof(operand), &e)) {
7726                 kvm_inject_page_fault(vcpu, &e);
7727                 return 1;
7728         }
7729
7730         switch (type) {
7731         case VMX_EPT_EXTENT_GLOBAL:
7732         /*
7733          * TODO: track mappings and invalidate
7734          * single context requests appropriately
7735          */
7736         case VMX_EPT_EXTENT_CONTEXT:
7737                 kvm_mmu_sync_roots(vcpu);
7738                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7739                 nested_vmx_succeed(vcpu);
7740                 break;
7741         default:
7742                 BUG_ON(1);
7743                 break;
7744         }
7745
7746         return kvm_skip_emulated_instruction(vcpu);
7747 }
7748
7749 static int handle_invvpid(struct kvm_vcpu *vcpu)
7750 {
7751         struct vcpu_vmx *vmx = to_vmx(vcpu);
7752         u32 vmx_instruction_info;
7753         unsigned long type, types;
7754         gva_t gva;
7755         struct x86_exception e;
7756         int vpid;
7757
7758         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7759               SECONDARY_EXEC_ENABLE_VPID) ||
7760                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7761                 kvm_queue_exception(vcpu, UD_VECTOR);
7762                 return 1;
7763         }
7764
7765         if (!nested_vmx_check_permission(vcpu))
7766                 return 1;
7767
7768         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7769         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7770
7771         types = (vmx->nested.nested_vmx_vpid_caps &
7772                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7773
7774         if (type >= 32 || !(types & (1 << type))) {
7775                 nested_vmx_failValid(vcpu,
7776                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7777                 return kvm_skip_emulated_instruction(vcpu);
7778         }
7779
7780         /* according to the intel vmx instruction reference, the memory
7781          * operand is read even if it isn't needed (e.g., for type==global)
7782          */
7783         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7784                         vmx_instruction_info, false, &gva))
7785                 return 1;
7786         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7787                                 sizeof(u32), &e)) {
7788                 kvm_inject_page_fault(vcpu, &e);
7789                 return 1;
7790         }
7791
7792         switch (type) {
7793         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7794         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7795         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7796                 if (!vpid) {
7797                         nested_vmx_failValid(vcpu,
7798                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7799                         return kvm_skip_emulated_instruction(vcpu);
7800                 }
7801                 break;
7802         case VMX_VPID_EXTENT_ALL_CONTEXT:
7803                 break;
7804         default:
7805                 WARN_ON_ONCE(1);
7806                 return kvm_skip_emulated_instruction(vcpu);
7807         }
7808
7809         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7810         nested_vmx_succeed(vcpu);
7811
7812         return kvm_skip_emulated_instruction(vcpu);
7813 }
7814
7815 static int handle_pml_full(struct kvm_vcpu *vcpu)
7816 {
7817         unsigned long exit_qualification;
7818
7819         trace_kvm_pml_full(vcpu->vcpu_id);
7820
7821         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7822
7823         /*
7824          * PML buffer FULL happened while executing iret from NMI,
7825          * "blocked by NMI" bit has to be set before next VM entry.
7826          */
7827         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7828                         cpu_has_virtual_nmis() &&
7829                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7830                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7831                                 GUEST_INTR_STATE_NMI);
7832
7833         /*
7834          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7835          * here.., and there's no userspace involvement needed for PML.
7836          */
7837         return 1;
7838 }
7839
7840 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7841 {
7842         kvm_lapic_expired_hv_timer(vcpu);
7843         return 1;
7844 }
7845
7846 /*
7847  * The exit handlers return 1 if the exit was handled fully and guest execution
7848  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7849  * to be done to userspace and return 0.
7850  */
7851 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7852         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7853         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7854         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7855         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7856         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7857         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7858         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7859         [EXIT_REASON_CPUID]                   = handle_cpuid,
7860         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7861         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7862         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7863         [EXIT_REASON_HLT]                     = handle_halt,
7864         [EXIT_REASON_INVD]                    = handle_invd,
7865         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7866         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7867         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7868         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7869         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7870         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7871         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7872         [EXIT_REASON_VMREAD]                  = handle_vmread,
7873         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7874         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7875         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7876         [EXIT_REASON_VMON]                    = handle_vmon,
7877         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7878         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7879         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7880         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7881         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7882         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7883         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7884         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7885         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7886         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7887         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7888         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7889         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7890         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7891         [EXIT_REASON_INVEPT]                  = handle_invept,
7892         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7893         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7894         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7895         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7896         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7897 };
7898
7899 static const int kvm_vmx_max_exit_handlers =
7900         ARRAY_SIZE(kvm_vmx_exit_handlers);
7901
7902 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7903                                        struct vmcs12 *vmcs12)
7904 {
7905         unsigned long exit_qualification;
7906         gpa_t bitmap, last_bitmap;
7907         unsigned int port;
7908         int size;
7909         u8 b;
7910
7911         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7912                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7913
7914         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7915
7916         port = exit_qualification >> 16;
7917         size = (exit_qualification & 7) + 1;
7918
7919         last_bitmap = (gpa_t)-1;
7920         b = -1;
7921
7922         while (size > 0) {
7923                 if (port < 0x8000)
7924                         bitmap = vmcs12->io_bitmap_a;
7925                 else if (port < 0x10000)
7926                         bitmap = vmcs12->io_bitmap_b;
7927                 else
7928                         return true;
7929                 bitmap += (port & 0x7fff) / 8;
7930
7931                 if (last_bitmap != bitmap)
7932                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7933                                 return true;
7934                 if (b & (1 << (port & 7)))
7935                         return true;
7936
7937                 port++;
7938                 size--;
7939                 last_bitmap = bitmap;
7940         }
7941
7942         return false;
7943 }
7944
7945 /*
7946  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7947  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7948  * disinterest in the current event (read or write a specific MSR) by using an
7949  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7950  */
7951 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7952         struct vmcs12 *vmcs12, u32 exit_reason)
7953 {
7954         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7955         gpa_t bitmap;
7956
7957         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7958                 return true;
7959
7960         /*
7961          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7962          * for the four combinations of read/write and low/high MSR numbers.
7963          * First we need to figure out which of the four to use:
7964          */
7965         bitmap = vmcs12->msr_bitmap;
7966         if (exit_reason == EXIT_REASON_MSR_WRITE)
7967                 bitmap += 2048;
7968         if (msr_index >= 0xc0000000) {
7969                 msr_index -= 0xc0000000;
7970                 bitmap += 1024;
7971         }
7972
7973         /* Then read the msr_index'th bit from this bitmap: */
7974         if (msr_index < 1024*8) {
7975                 unsigned char b;
7976                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7977                         return true;
7978                 return 1 & (b >> (msr_index & 7));
7979         } else
7980                 return true; /* let L1 handle the wrong parameter */
7981 }
7982
7983 /*
7984  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7985  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7986  * intercept (via guest_host_mask etc.) the current event.
7987  */
7988 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7989         struct vmcs12 *vmcs12)
7990 {
7991         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7992         int cr = exit_qualification & 15;
7993         int reg = (exit_qualification >> 8) & 15;
7994         unsigned long val = kvm_register_readl(vcpu, reg);
7995
7996         switch ((exit_qualification >> 4) & 3) {
7997         case 0: /* mov to cr */
7998                 switch (cr) {
7999                 case 0:
8000                         if (vmcs12->cr0_guest_host_mask &
8001                             (val ^ vmcs12->cr0_read_shadow))
8002                                 return true;
8003                         break;
8004                 case 3:
8005                         if ((vmcs12->cr3_target_count >= 1 &&
8006                                         vmcs12->cr3_target_value0 == val) ||
8007                                 (vmcs12->cr3_target_count >= 2 &&
8008                                         vmcs12->cr3_target_value1 == val) ||
8009                                 (vmcs12->cr3_target_count >= 3 &&
8010                                         vmcs12->cr3_target_value2 == val) ||
8011                                 (vmcs12->cr3_target_count >= 4 &&
8012                                         vmcs12->cr3_target_value3 == val))
8013                                 return false;
8014                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8015                                 return true;
8016                         break;
8017                 case 4:
8018                         if (vmcs12->cr4_guest_host_mask &
8019                             (vmcs12->cr4_read_shadow ^ val))
8020                                 return true;
8021                         break;
8022                 case 8:
8023                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8024                                 return true;
8025                         break;
8026                 }
8027                 break;
8028         case 2: /* clts */
8029                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8030                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8031                         return true;
8032                 break;
8033         case 1: /* mov from cr */
8034                 switch (cr) {
8035                 case 3:
8036                         if (vmcs12->cpu_based_vm_exec_control &
8037                             CPU_BASED_CR3_STORE_EXITING)
8038                                 return true;
8039                         break;
8040                 case 8:
8041                         if (vmcs12->cpu_based_vm_exec_control &
8042                             CPU_BASED_CR8_STORE_EXITING)
8043                                 return true;
8044                         break;
8045                 }
8046                 break;
8047         case 3: /* lmsw */
8048                 /*
8049                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8050                  * cr0. Other attempted changes are ignored, with no exit.
8051                  */
8052                 if (vmcs12->cr0_guest_host_mask & 0xe &
8053                     (val ^ vmcs12->cr0_read_shadow))
8054                         return true;
8055                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8056                     !(vmcs12->cr0_read_shadow & 0x1) &&
8057                     (val & 0x1))
8058                         return true;
8059                 break;
8060         }
8061         return false;
8062 }
8063
8064 /*
8065  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8066  * should handle it ourselves in L0 (and then continue L2). Only call this
8067  * when in is_guest_mode (L2).
8068  */
8069 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8070 {
8071         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8072         struct vcpu_vmx *vmx = to_vmx(vcpu);
8073         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8074         u32 exit_reason = vmx->exit_reason;
8075
8076         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8077                                 vmcs_readl(EXIT_QUALIFICATION),
8078                                 vmx->idt_vectoring_info,
8079                                 intr_info,
8080                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8081                                 KVM_ISA_VMX);
8082
8083         if (vmx->nested.nested_run_pending)
8084                 return false;
8085
8086         if (unlikely(vmx->fail)) {
8087                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8088                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8089                 return true;
8090         }
8091
8092         switch (exit_reason) {
8093         case EXIT_REASON_EXCEPTION_NMI:
8094                 if (is_nmi(intr_info))
8095                         return false;
8096                 else if (is_page_fault(intr_info))
8097                         return enable_ept;
8098                 else if (is_no_device(intr_info) &&
8099                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8100                         return false;
8101                 else if (is_debug(intr_info) &&
8102                          vcpu->guest_debug &
8103                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8104                         return false;
8105                 else if (is_breakpoint(intr_info) &&
8106                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8107                         return false;
8108                 return vmcs12->exception_bitmap &
8109                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8110         case EXIT_REASON_EXTERNAL_INTERRUPT:
8111                 return false;
8112         case EXIT_REASON_TRIPLE_FAULT:
8113                 return true;
8114         case EXIT_REASON_PENDING_INTERRUPT:
8115                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8116         case EXIT_REASON_NMI_WINDOW:
8117                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8118         case EXIT_REASON_TASK_SWITCH:
8119                 return true;
8120         case EXIT_REASON_CPUID:
8121                 return true;
8122         case EXIT_REASON_HLT:
8123                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8124         case EXIT_REASON_INVD:
8125                 return true;
8126         case EXIT_REASON_INVLPG:
8127                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8128         case EXIT_REASON_RDPMC:
8129                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8130         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8131                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8132         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8133         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8134         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8135         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8136         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8137         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8138                 /*
8139                  * VMX instructions trap unconditionally. This allows L1 to
8140                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8141                  */
8142                 return true;
8143         case EXIT_REASON_CR_ACCESS:
8144                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8145         case EXIT_REASON_DR_ACCESS:
8146                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8147         case EXIT_REASON_IO_INSTRUCTION:
8148                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8149         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8150                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8151         case EXIT_REASON_MSR_READ:
8152         case EXIT_REASON_MSR_WRITE:
8153                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8154         case EXIT_REASON_INVALID_STATE:
8155                 return true;
8156         case EXIT_REASON_MWAIT_INSTRUCTION:
8157                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8158         case EXIT_REASON_MONITOR_TRAP_FLAG:
8159                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8160         case EXIT_REASON_MONITOR_INSTRUCTION:
8161                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8162         case EXIT_REASON_PAUSE_INSTRUCTION:
8163                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8164                         nested_cpu_has2(vmcs12,
8165                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8166         case EXIT_REASON_MCE_DURING_VMENTRY:
8167                 return false;
8168         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8169                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8170         case EXIT_REASON_APIC_ACCESS:
8171                 return nested_cpu_has2(vmcs12,
8172                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8173         case EXIT_REASON_APIC_WRITE:
8174         case EXIT_REASON_EOI_INDUCED:
8175                 /* apic_write and eoi_induced should exit unconditionally. */
8176                 return true;
8177         case EXIT_REASON_EPT_VIOLATION:
8178                 /*
8179                  * L0 always deals with the EPT violation. If nested EPT is
8180                  * used, and the nested mmu code discovers that the address is
8181                  * missing in the guest EPT table (EPT12), the EPT violation
8182                  * will be injected with nested_ept_inject_page_fault()
8183                  */
8184                 return false;
8185         case EXIT_REASON_EPT_MISCONFIG:
8186                 /*
8187                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8188                  * table (shadow on EPT) or a merged EPT table that L0 built
8189                  * (EPT on EPT). So any problems with the structure of the
8190                  * table is L0's fault.
8191                  */
8192                 return false;
8193         case EXIT_REASON_WBINVD:
8194                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8195         case EXIT_REASON_XSETBV:
8196                 return true;
8197         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8198                 /*
8199                  * This should never happen, since it is not possible to
8200                  * set XSS to a non-zero value---neither in L1 nor in L2.
8201                  * If if it were, XSS would have to be checked against
8202                  * the XSS exit bitmap in vmcs12.
8203                  */
8204                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8205         case EXIT_REASON_PREEMPTION_TIMER:
8206                 return false;
8207         default:
8208                 return true;
8209         }
8210 }
8211
8212 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8213 {
8214         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8215         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8216 }
8217
8218 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8219 {
8220         if (vmx->pml_pg) {
8221                 __free_page(vmx->pml_pg);
8222                 vmx->pml_pg = NULL;
8223         }
8224 }
8225
8226 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8227 {
8228         struct vcpu_vmx *vmx = to_vmx(vcpu);
8229         u64 *pml_buf;
8230         u16 pml_idx;
8231
8232         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8233
8234         /* Do nothing if PML buffer is empty */
8235         if (pml_idx == (PML_ENTITY_NUM - 1))
8236                 return;
8237
8238         /* PML index always points to next available PML buffer entity */
8239         if (pml_idx >= PML_ENTITY_NUM)
8240                 pml_idx = 0;
8241         else
8242                 pml_idx++;
8243
8244         pml_buf = page_address(vmx->pml_pg);
8245         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8246                 u64 gpa;
8247
8248                 gpa = pml_buf[pml_idx];
8249                 WARN_ON(gpa & (PAGE_SIZE - 1));
8250                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8251         }
8252
8253         /* reset PML index */
8254         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8255 }
8256
8257 /*
8258  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8259  * Called before reporting dirty_bitmap to userspace.
8260  */
8261 static void kvm_flush_pml_buffers(struct kvm *kvm)
8262 {
8263         int i;
8264         struct kvm_vcpu *vcpu;
8265         /*
8266          * We only need to kick vcpu out of guest mode here, as PML buffer
8267          * is flushed at beginning of all VMEXITs, and it's obvious that only
8268          * vcpus running in guest are possible to have unflushed GPAs in PML
8269          * buffer.
8270          */
8271         kvm_for_each_vcpu(i, vcpu, kvm)
8272                 kvm_vcpu_kick(vcpu);
8273 }
8274
8275 static void vmx_dump_sel(char *name, uint32_t sel)
8276 {
8277         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8278                name, vmcs_read32(sel),
8279                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8280                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8281                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8282 }
8283
8284 static void vmx_dump_dtsel(char *name, uint32_t limit)
8285 {
8286         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8287                name, vmcs_read32(limit),
8288                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8289 }
8290
8291 static void dump_vmcs(void)
8292 {
8293         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8294         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8295         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8296         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8297         u32 secondary_exec_control = 0;
8298         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8299         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8300         int i, n;
8301
8302         if (cpu_has_secondary_exec_ctrls())
8303                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8304
8305         pr_err("*** Guest State ***\n");
8306         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8307                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8308                vmcs_readl(CR0_GUEST_HOST_MASK));
8309         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8310                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8311         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8312         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8313             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8314         {
8315                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8316                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8317                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8318                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8319         }
8320         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8321                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8322         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8323                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8324         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8325                vmcs_readl(GUEST_SYSENTER_ESP),
8326                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8327         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8328         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8329         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8330         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8331         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8332         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8333         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8334         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8335         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8336         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8337         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8338             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8339                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8340                        efer, vmcs_read64(GUEST_IA32_PAT));
8341         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8342                vmcs_read64(GUEST_IA32_DEBUGCTL),
8343                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8344         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8345                 pr_err("PerfGlobCtl = 0x%016llx\n",
8346                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8347         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8348                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8349         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8350                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8351                vmcs_read32(GUEST_ACTIVITY_STATE));
8352         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8353                 pr_err("InterruptStatus = %04x\n",
8354                        vmcs_read16(GUEST_INTR_STATUS));
8355
8356         pr_err("*** Host State ***\n");
8357         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8358                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8359         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8360                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8361                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8362                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8363                vmcs_read16(HOST_TR_SELECTOR));
8364         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8365                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8366                vmcs_readl(HOST_TR_BASE));
8367         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8368                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8369         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8370                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8371                vmcs_readl(HOST_CR4));
8372         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8373                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8374                vmcs_read32(HOST_IA32_SYSENTER_CS),
8375                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8376         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8377                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8378                        vmcs_read64(HOST_IA32_EFER),
8379                        vmcs_read64(HOST_IA32_PAT));
8380         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8381                 pr_err("PerfGlobCtl = 0x%016llx\n",
8382                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8383
8384         pr_err("*** Control State ***\n");
8385         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8386                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8387         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8388         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8389                vmcs_read32(EXCEPTION_BITMAP),
8390                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8391                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8392         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8393                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8394                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8395                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8396         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8397                vmcs_read32(VM_EXIT_INTR_INFO),
8398                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8399                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8400         pr_err("        reason=%08x qualification=%016lx\n",
8401                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8402         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8403                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8404                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8405         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8406         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8407                 pr_err("TSC Multiplier = 0x%016llx\n",
8408                        vmcs_read64(TSC_MULTIPLIER));
8409         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8410                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8411         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8412                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8413         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8414                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8415         n = vmcs_read32(CR3_TARGET_COUNT);
8416         for (i = 0; i + 1 < n; i += 4)
8417                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8418                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8419                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8420         if (i < n)
8421                 pr_err("CR3 target%u=%016lx\n",
8422                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8423         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8424                 pr_err("PLE Gap=%08x Window=%08x\n",
8425                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8426         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8427                 pr_err("Virtual processor ID = 0x%04x\n",
8428                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8429 }
8430
8431 /*
8432  * The guest has exited.  See if we can fix it or if we need userspace
8433  * assistance.
8434  */
8435 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8436 {
8437         struct vcpu_vmx *vmx = to_vmx(vcpu);
8438         u32 exit_reason = vmx->exit_reason;
8439         u32 vectoring_info = vmx->idt_vectoring_info;
8440
8441         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8442         vcpu->arch.gpa_available = false;
8443
8444         /*
8445          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8446          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8447          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8448          * mode as if vcpus is in root mode, the PML buffer must has been
8449          * flushed already.
8450          */
8451         if (enable_pml)
8452                 vmx_flush_pml_buffer(vcpu);
8453
8454         /* If guest state is invalid, start emulating */
8455         if (vmx->emulation_required)
8456                 return handle_invalid_guest_state(vcpu);
8457
8458         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8459                 nested_vmx_vmexit(vcpu, exit_reason,
8460                                   vmcs_read32(VM_EXIT_INTR_INFO),
8461                                   vmcs_readl(EXIT_QUALIFICATION));
8462                 return 1;
8463         }
8464
8465         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8466                 dump_vmcs();
8467                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8468                 vcpu->run->fail_entry.hardware_entry_failure_reason
8469                         = exit_reason;
8470                 return 0;
8471         }
8472
8473         if (unlikely(vmx->fail)) {
8474                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8475                 vcpu->run->fail_entry.hardware_entry_failure_reason
8476                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8477                 return 0;
8478         }
8479
8480         /*
8481          * Note:
8482          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8483          * delivery event since it indicates guest is accessing MMIO.
8484          * The vm-exit can be triggered again after return to guest that
8485          * will cause infinite loop.
8486          */
8487         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8488                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8489                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8490                         exit_reason != EXIT_REASON_PML_FULL &&
8491                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8492                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8493                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8494                 vcpu->run->internal.ndata = 2;
8495                 vcpu->run->internal.data[0] = vectoring_info;
8496                 vcpu->run->internal.data[1] = exit_reason;
8497                 return 0;
8498         }
8499
8500         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8501             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8502                                         get_vmcs12(vcpu))))) {
8503                 if (vmx_interrupt_allowed(vcpu)) {
8504                         vmx->soft_vnmi_blocked = 0;
8505                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8506                            vcpu->arch.nmi_pending) {
8507                         /*
8508                          * This CPU don't support us in finding the end of an
8509                          * NMI-blocked window if the guest runs with IRQs
8510                          * disabled. So we pull the trigger after 1 s of
8511                          * futile waiting, but inform the user about this.
8512                          */
8513                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8514                                "state on VCPU %d after 1 s timeout\n",
8515                                __func__, vcpu->vcpu_id);
8516                         vmx->soft_vnmi_blocked = 0;
8517                 }
8518         }
8519
8520         if (exit_reason < kvm_vmx_max_exit_handlers
8521             && kvm_vmx_exit_handlers[exit_reason])
8522                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8523         else {
8524                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8525                 kvm_queue_exception(vcpu, UD_VECTOR);
8526                 return 1;
8527         }
8528 }
8529
8530 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8531 {
8532         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8533
8534         if (is_guest_mode(vcpu) &&
8535                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8536                 return;
8537
8538         if (irr == -1 || tpr < irr) {
8539                 vmcs_write32(TPR_THRESHOLD, 0);
8540                 return;
8541         }
8542
8543         vmcs_write32(TPR_THRESHOLD, irr);
8544 }
8545
8546 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8547 {
8548         u32 sec_exec_control;
8549
8550         /* Postpone execution until vmcs01 is the current VMCS. */
8551         if (is_guest_mode(vcpu)) {
8552                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8553                 return;
8554         }
8555
8556         if (!cpu_has_vmx_virtualize_x2apic_mode())
8557                 return;
8558
8559         if (!cpu_need_tpr_shadow(vcpu))
8560                 return;
8561
8562         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8563
8564         if (set) {
8565                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8566                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8567         } else {
8568                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8569                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8570         }
8571         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8572
8573         vmx_set_msr_bitmap(vcpu);
8574 }
8575
8576 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8577 {
8578         struct vcpu_vmx *vmx = to_vmx(vcpu);
8579
8580         /*
8581          * Currently we do not handle the nested case where L2 has an
8582          * APIC access page of its own; that page is still pinned.
8583          * Hence, we skip the case where the VCPU is in guest mode _and_
8584          * L1 prepared an APIC access page for L2.
8585          *
8586          * For the case where L1 and L2 share the same APIC access page
8587          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8588          * in the vmcs12), this function will only update either the vmcs01
8589          * or the vmcs02.  If the former, the vmcs02 will be updated by
8590          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8591          * the next L2->L1 exit.
8592          */
8593         if (!is_guest_mode(vcpu) ||
8594             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8595                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8596                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8597 }
8598
8599 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8600 {
8601         u16 status;
8602         u8 old;
8603
8604         if (max_isr == -1)
8605                 max_isr = 0;
8606
8607         status = vmcs_read16(GUEST_INTR_STATUS);
8608         old = status >> 8;
8609         if (max_isr != old) {
8610                 status &= 0xff;
8611                 status |= max_isr << 8;
8612                 vmcs_write16(GUEST_INTR_STATUS, status);
8613         }
8614 }
8615
8616 static void vmx_set_rvi(int vector)
8617 {
8618         u16 status;
8619         u8 old;
8620
8621         if (vector == -1)
8622                 vector = 0;
8623
8624         status = vmcs_read16(GUEST_INTR_STATUS);
8625         old = (u8)status & 0xff;
8626         if ((u8)vector != old) {
8627                 status &= ~0xff;
8628                 status |= (u8)vector;
8629                 vmcs_write16(GUEST_INTR_STATUS, status);
8630         }
8631 }
8632
8633 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8634 {
8635         if (!is_guest_mode(vcpu)) {
8636                 vmx_set_rvi(max_irr);
8637                 return;
8638         }
8639
8640         if (max_irr == -1)
8641                 return;
8642
8643         /*
8644          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8645          * handles it.
8646          */
8647         if (nested_exit_on_intr(vcpu))
8648                 return;
8649
8650         /*
8651          * Else, fall back to pre-APICv interrupt injection since L2
8652          * is run without virtual interrupt delivery.
8653          */
8654         if (!kvm_event_needs_reinjection(vcpu) &&
8655             vmx_interrupt_allowed(vcpu)) {
8656                 kvm_queue_interrupt(vcpu, max_irr, false);
8657                 vmx_inject_irq(vcpu);
8658         }
8659 }
8660
8661 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8662 {
8663         struct vcpu_vmx *vmx = to_vmx(vcpu);
8664         int max_irr;
8665
8666         WARN_ON(!vcpu->arch.apicv_active);
8667         if (pi_test_on(&vmx->pi_desc)) {
8668                 pi_clear_on(&vmx->pi_desc);
8669                 /*
8670                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8671                  * But on x86 this is just a compiler barrier anyway.
8672                  */
8673                 smp_mb__after_atomic();
8674                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8675         } else {
8676                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8677         }
8678         vmx_hwapic_irr_update(vcpu, max_irr);
8679         return max_irr;
8680 }
8681
8682 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8683 {
8684         if (!kvm_vcpu_apicv_active(vcpu))
8685                 return;
8686
8687         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8688         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8689         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8690         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8691 }
8692
8693 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8694 {
8695         struct vcpu_vmx *vmx = to_vmx(vcpu);
8696
8697         pi_clear_on(&vmx->pi_desc);
8698         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8699 }
8700
8701 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8702 {
8703         u32 exit_intr_info;
8704
8705         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8706               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8707                 return;
8708
8709         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8710         exit_intr_info = vmx->exit_intr_info;
8711
8712         /* Handle machine checks before interrupts are enabled */
8713         if (is_machine_check(exit_intr_info))
8714                 kvm_machine_check();
8715
8716         /* We need to handle NMIs before interrupts are enabled */
8717         if (is_nmi(exit_intr_info)) {
8718                 kvm_before_handle_nmi(&vmx->vcpu);
8719                 asm("int $2");
8720                 kvm_after_handle_nmi(&vmx->vcpu);
8721         }
8722 }
8723
8724 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8725 {
8726         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8727         register void *__sp asm(_ASM_SP);
8728
8729         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8730                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8731                 unsigned int vector;
8732                 unsigned long entry;
8733                 gate_desc *desc;
8734                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8735 #ifdef CONFIG_X86_64
8736                 unsigned long tmp;
8737 #endif
8738
8739                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8740                 desc = (gate_desc *)vmx->host_idt_base + vector;
8741                 entry = gate_offset(*desc);
8742                 asm volatile(
8743 #ifdef CONFIG_X86_64
8744                         "mov %%" _ASM_SP ", %[sp]\n\t"
8745                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8746                         "push $%c[ss]\n\t"
8747                         "push %[sp]\n\t"
8748 #endif
8749                         "pushf\n\t"
8750                         __ASM_SIZE(push) " $%c[cs]\n\t"
8751                         "call *%[entry]\n\t"
8752                         :
8753 #ifdef CONFIG_X86_64
8754                         [sp]"=&r"(tmp),
8755 #endif
8756                         "+r"(__sp)
8757                         :
8758                         [entry]"r"(entry),
8759                         [ss]"i"(__KERNEL_DS),
8760                         [cs]"i"(__KERNEL_CS)
8761                         );
8762         }
8763 }
8764
8765 static bool vmx_has_high_real_mode_segbase(void)
8766 {
8767         return enable_unrestricted_guest || emulate_invalid_guest_state;
8768 }
8769
8770 static bool vmx_mpx_supported(void)
8771 {
8772         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8773                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8774 }
8775
8776 static bool vmx_xsaves_supported(void)
8777 {
8778         return vmcs_config.cpu_based_2nd_exec_ctrl &
8779                 SECONDARY_EXEC_XSAVES;
8780 }
8781
8782 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8783 {
8784         u32 exit_intr_info;
8785         bool unblock_nmi;
8786         u8 vector;
8787         bool idtv_info_valid;
8788
8789         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8790
8791         if (cpu_has_virtual_nmis()) {
8792                 if (vmx->nmi_known_unmasked)
8793                         return;
8794                 /*
8795                  * Can't use vmx->exit_intr_info since we're not sure what
8796                  * the exit reason is.
8797                  */
8798                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8799                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8800                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8801                 /*
8802                  * SDM 3: 27.7.1.2 (September 2008)
8803                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8804                  * a guest IRET fault.
8805                  * SDM 3: 23.2.2 (September 2008)
8806                  * Bit 12 is undefined in any of the following cases:
8807                  *  If the VM exit sets the valid bit in the IDT-vectoring
8808                  *   information field.
8809                  *  If the VM exit is due to a double fault.
8810                  */
8811                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8812                     vector != DF_VECTOR && !idtv_info_valid)
8813                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8814                                       GUEST_INTR_STATE_NMI);
8815                 else
8816                         vmx->nmi_known_unmasked =
8817                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8818                                   & GUEST_INTR_STATE_NMI);
8819         } else if (unlikely(vmx->soft_vnmi_blocked))
8820                 vmx->vnmi_blocked_time +=
8821                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8822 }
8823
8824 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8825                                       u32 idt_vectoring_info,
8826                                       int instr_len_field,
8827                                       int error_code_field)
8828 {
8829         u8 vector;
8830         int type;
8831         bool idtv_info_valid;
8832
8833         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8834
8835         vcpu->arch.nmi_injected = false;
8836         kvm_clear_exception_queue(vcpu);
8837         kvm_clear_interrupt_queue(vcpu);
8838
8839         if (!idtv_info_valid)
8840                 return;
8841
8842         kvm_make_request(KVM_REQ_EVENT, vcpu);
8843
8844         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8845         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8846
8847         switch (type) {
8848         case INTR_TYPE_NMI_INTR:
8849                 vcpu->arch.nmi_injected = true;
8850                 /*
8851                  * SDM 3: 27.7.1.2 (September 2008)
8852                  * Clear bit "block by NMI" before VM entry if a NMI
8853                  * delivery faulted.
8854                  */
8855                 vmx_set_nmi_mask(vcpu, false);
8856                 break;
8857         case INTR_TYPE_SOFT_EXCEPTION:
8858                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8859                 /* fall through */
8860         case INTR_TYPE_HARD_EXCEPTION:
8861                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8862                         u32 err = vmcs_read32(error_code_field);
8863                         kvm_requeue_exception_e(vcpu, vector, err);
8864                 } else
8865                         kvm_requeue_exception(vcpu, vector);
8866                 break;
8867         case INTR_TYPE_SOFT_INTR:
8868                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8869                 /* fall through */
8870         case INTR_TYPE_EXT_INTR:
8871                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8872                 break;
8873         default:
8874                 break;
8875         }
8876 }
8877
8878 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8879 {
8880         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8881                                   VM_EXIT_INSTRUCTION_LEN,
8882                                   IDT_VECTORING_ERROR_CODE);
8883 }
8884
8885 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8886 {
8887         __vmx_complete_interrupts(vcpu,
8888                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8889                                   VM_ENTRY_INSTRUCTION_LEN,
8890                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8891
8892         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8893 }
8894
8895 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8896 {
8897         int i, nr_msrs;
8898         struct perf_guest_switch_msr *msrs;
8899
8900         msrs = perf_guest_get_msrs(&nr_msrs);
8901
8902         if (!msrs)
8903                 return;
8904
8905         for (i = 0; i < nr_msrs; i++)
8906                 if (msrs[i].host == msrs[i].guest)
8907                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8908                 else
8909                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8910                                         msrs[i].host);
8911 }
8912
8913 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8914 {
8915         struct vcpu_vmx *vmx = to_vmx(vcpu);
8916         u64 tscl;
8917         u32 delta_tsc;
8918
8919         if (vmx->hv_deadline_tsc == -1)
8920                 return;
8921
8922         tscl = rdtsc();
8923         if (vmx->hv_deadline_tsc > tscl)
8924                 /* sure to be 32 bit only because checked on set_hv_timer */
8925                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8926                         cpu_preemption_timer_multi);
8927         else
8928                 delta_tsc = 0;
8929
8930         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8931 }
8932
8933 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8934 {
8935         struct vcpu_vmx *vmx = to_vmx(vcpu);
8936         unsigned long debugctlmsr, cr4;
8937
8938         /* Record the guest's net vcpu time for enforced NMI injections. */
8939         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8940                 vmx->entry_time = ktime_get();
8941
8942         /* Don't enter VMX if guest state is invalid, let the exit handler
8943            start emulation until we arrive back to a valid state */
8944         if (vmx->emulation_required)
8945                 return;
8946
8947         if (vmx->ple_window_dirty) {
8948                 vmx->ple_window_dirty = false;
8949                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8950         }
8951
8952         if (vmx->nested.sync_shadow_vmcs) {
8953                 copy_vmcs12_to_shadow(vmx);
8954                 vmx->nested.sync_shadow_vmcs = false;
8955         }
8956
8957         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8958                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8959         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8960                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8961
8962         cr4 = cr4_read_shadow();
8963         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8964                 vmcs_writel(HOST_CR4, cr4);
8965                 vmx->host_state.vmcs_host_cr4 = cr4;
8966         }
8967
8968         /* When single-stepping over STI and MOV SS, we must clear the
8969          * corresponding interruptibility bits in the guest state. Otherwise
8970          * vmentry fails as it then expects bit 14 (BS) in pending debug
8971          * exceptions being set, but that's not correct for the guest debugging
8972          * case. */
8973         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8974                 vmx_set_interrupt_shadow(vcpu, 0);
8975
8976         if (vmx->guest_pkru_valid)
8977                 __write_pkru(vmx->guest_pkru);
8978
8979         atomic_switch_perf_msrs(vmx);
8980         debugctlmsr = get_debugctlmsr();
8981
8982         vmx_arm_hv_timer(vcpu);
8983
8984         vmx->__launched = vmx->loaded_vmcs->launched;
8985         asm(
8986                 /* Store host registers */
8987                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8988                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8989                 "push %%" _ASM_CX " \n\t"
8990                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8991                 "je 1f \n\t"
8992                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8993                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8994                 "1: \n\t"
8995                 /* Reload cr2 if changed */
8996                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8997                 "mov %%cr2, %%" _ASM_DX " \n\t"
8998                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8999                 "je 2f \n\t"
9000                 "mov %%" _ASM_AX", %%cr2 \n\t"
9001                 "2: \n\t"
9002                 /* Check if vmlaunch of vmresume is needed */
9003                 "cmpl $0, %c[launched](%0) \n\t"
9004                 /* Load guest registers.  Don't clobber flags. */
9005                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9006                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9007                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9008                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9009                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9010                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9011 #ifdef CONFIG_X86_64
9012                 "mov %c[r8](%0),  %%r8  \n\t"
9013                 "mov %c[r9](%0),  %%r9  \n\t"
9014                 "mov %c[r10](%0), %%r10 \n\t"
9015                 "mov %c[r11](%0), %%r11 \n\t"
9016                 "mov %c[r12](%0), %%r12 \n\t"
9017                 "mov %c[r13](%0), %%r13 \n\t"
9018                 "mov %c[r14](%0), %%r14 \n\t"
9019                 "mov %c[r15](%0), %%r15 \n\t"
9020 #endif
9021                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9022
9023                 /* Enter guest mode */
9024                 "jne 1f \n\t"
9025                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9026                 "jmp 2f \n\t"
9027                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9028                 "2: "
9029                 /* Save guest registers, load host registers, keep flags */
9030                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9031                 "pop %0 \n\t"
9032                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9033                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9034                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9035                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9036                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9037                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9038                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9039 #ifdef CONFIG_X86_64
9040                 "mov %%r8,  %c[r8](%0) \n\t"
9041                 "mov %%r9,  %c[r9](%0) \n\t"
9042                 "mov %%r10, %c[r10](%0) \n\t"
9043                 "mov %%r11, %c[r11](%0) \n\t"
9044                 "mov %%r12, %c[r12](%0) \n\t"
9045                 "mov %%r13, %c[r13](%0) \n\t"
9046                 "mov %%r14, %c[r14](%0) \n\t"
9047                 "mov %%r15, %c[r15](%0) \n\t"
9048 #endif
9049                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9050                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9051
9052                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9053                 "setbe %c[fail](%0) \n\t"
9054                 ".pushsection .rodata \n\t"
9055                 ".global vmx_return \n\t"
9056                 "vmx_return: " _ASM_PTR " 2b \n\t"
9057                 ".popsection"
9058               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9059                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9060                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9061                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9062                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9063                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9064                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9065                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9066                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9067                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9068                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9069 #ifdef CONFIG_X86_64
9070                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9071                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9072                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9073                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9074                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9075                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9076                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9077                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9078 #endif
9079                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9080                 [wordsize]"i"(sizeof(ulong))
9081               : "cc", "memory"
9082 #ifdef CONFIG_X86_64
9083                 , "rax", "rbx", "rdi", "rsi"
9084                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9085 #else
9086                 , "eax", "ebx", "edi", "esi"
9087 #endif
9088               );
9089
9090         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9091         if (debugctlmsr)
9092                 update_debugctlmsr(debugctlmsr);
9093
9094 #ifndef CONFIG_X86_64
9095         /*
9096          * The sysexit path does not restore ds/es, so we must set them to
9097          * a reasonable value ourselves.
9098          *
9099          * We can't defer this to vmx_load_host_state() since that function
9100          * may be executed in interrupt context, which saves and restore segments
9101          * around it, nullifying its effect.
9102          */
9103         loadsegment(ds, __USER_DS);
9104         loadsegment(es, __USER_DS);
9105 #endif
9106
9107         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9108                                   | (1 << VCPU_EXREG_RFLAGS)
9109                                   | (1 << VCPU_EXREG_PDPTR)
9110                                   | (1 << VCPU_EXREG_SEGMENTS)
9111                                   | (1 << VCPU_EXREG_CR3));
9112         vcpu->arch.regs_dirty = 0;
9113
9114         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9115
9116         vmx->loaded_vmcs->launched = 1;
9117
9118         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9119
9120         /*
9121          * eager fpu is enabled if PKEY is supported and CR4 is switched
9122          * back on host, so it is safe to read guest PKRU from current
9123          * XSAVE.
9124          */
9125         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9126                 vmx->guest_pkru = __read_pkru();
9127                 if (vmx->guest_pkru != vmx->host_pkru) {
9128                         vmx->guest_pkru_valid = true;
9129                         __write_pkru(vmx->host_pkru);
9130                 } else
9131                         vmx->guest_pkru_valid = false;
9132         }
9133
9134         /*
9135          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9136          * we did not inject a still-pending event to L1 now because of
9137          * nested_run_pending, we need to re-enable this bit.
9138          */
9139         if (vmx->nested.nested_run_pending)
9140                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9141
9142         vmx->nested.nested_run_pending = 0;
9143
9144         vmx_complete_atomic_exit(vmx);
9145         vmx_recover_nmi_blocking(vmx);
9146         vmx_complete_interrupts(vmx);
9147 }
9148
9149 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9150 {
9151         struct vcpu_vmx *vmx = to_vmx(vcpu);
9152         int cpu;
9153
9154         if (vmx->loaded_vmcs == &vmx->vmcs01)
9155                 return;
9156
9157         cpu = get_cpu();
9158         vmx->loaded_vmcs = &vmx->vmcs01;
9159         vmx_vcpu_put(vcpu);
9160         vmx_vcpu_load(vcpu, cpu);
9161         vcpu->cpu = cpu;
9162         put_cpu();
9163 }
9164
9165 /*
9166  * Ensure that the current vmcs of the logical processor is the
9167  * vmcs01 of the vcpu before calling free_nested().
9168  */
9169 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9170 {
9171        struct vcpu_vmx *vmx = to_vmx(vcpu);
9172        int r;
9173
9174        r = vcpu_load(vcpu);
9175        BUG_ON(r);
9176        vmx_load_vmcs01(vcpu);
9177        free_nested(vmx);
9178        vcpu_put(vcpu);
9179 }
9180
9181 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9182 {
9183         struct vcpu_vmx *vmx = to_vmx(vcpu);
9184
9185         if (enable_pml)
9186                 vmx_destroy_pml_buffer(vmx);
9187         free_vpid(vmx->vpid);
9188         leave_guest_mode(vcpu);
9189         vmx_free_vcpu_nested(vcpu);
9190         free_loaded_vmcs(vmx->loaded_vmcs);
9191         kfree(vmx->guest_msrs);
9192         kvm_vcpu_uninit(vcpu);
9193         kmem_cache_free(kvm_vcpu_cache, vmx);
9194 }
9195
9196 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9197 {
9198         int err;
9199         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9200         int cpu;
9201
9202         if (!vmx)
9203                 return ERR_PTR(-ENOMEM);
9204
9205         vmx->vpid = allocate_vpid();
9206
9207         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9208         if (err)
9209                 goto free_vcpu;
9210
9211         err = -ENOMEM;
9212
9213         /*
9214          * If PML is turned on, failure on enabling PML just results in failure
9215          * of creating the vcpu, therefore we can simplify PML logic (by
9216          * avoiding dealing with cases, such as enabling PML partially on vcpus
9217          * for the guest, etc.
9218          */
9219         if (enable_pml) {
9220                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9221                 if (!vmx->pml_pg)
9222                         goto uninit_vcpu;
9223         }
9224
9225         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9226         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9227                      > PAGE_SIZE);
9228
9229         if (!vmx->guest_msrs)
9230                 goto free_pml;
9231
9232         vmx->loaded_vmcs = &vmx->vmcs01;
9233         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9234         vmx->loaded_vmcs->shadow_vmcs = NULL;
9235         if (!vmx->loaded_vmcs->vmcs)
9236                 goto free_msrs;
9237         if (!vmm_exclusive)
9238                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9239         loaded_vmcs_init(vmx->loaded_vmcs);
9240         if (!vmm_exclusive)
9241                 kvm_cpu_vmxoff();
9242
9243         cpu = get_cpu();
9244         vmx_vcpu_load(&vmx->vcpu, cpu);
9245         vmx->vcpu.cpu = cpu;
9246         err = vmx_vcpu_setup(vmx);
9247         vmx_vcpu_put(&vmx->vcpu);
9248         put_cpu();
9249         if (err)
9250                 goto free_vmcs;
9251         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9252                 err = alloc_apic_access_page(kvm);
9253                 if (err)
9254                         goto free_vmcs;
9255         }
9256
9257         if (enable_ept) {
9258                 if (!kvm->arch.ept_identity_map_addr)
9259                         kvm->arch.ept_identity_map_addr =
9260                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9261                 err = init_rmode_identity_map(kvm);
9262                 if (err)
9263                         goto free_vmcs;
9264         }
9265
9266         if (nested) {
9267                 nested_vmx_setup_ctls_msrs(vmx);
9268                 vmx->nested.vpid02 = allocate_vpid();
9269         }
9270
9271         vmx->nested.posted_intr_nv = -1;
9272         vmx->nested.current_vmptr = -1ull;
9273         vmx->nested.current_vmcs12 = NULL;
9274
9275         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9276
9277         return &vmx->vcpu;
9278
9279 free_vmcs:
9280         free_vpid(vmx->nested.vpid02);
9281         free_loaded_vmcs(vmx->loaded_vmcs);
9282 free_msrs:
9283         kfree(vmx->guest_msrs);
9284 free_pml:
9285         vmx_destroy_pml_buffer(vmx);
9286 uninit_vcpu:
9287         kvm_vcpu_uninit(&vmx->vcpu);
9288 free_vcpu:
9289         free_vpid(vmx->vpid);
9290         kmem_cache_free(kvm_vcpu_cache, vmx);
9291         return ERR_PTR(err);
9292 }
9293
9294 static void __init vmx_check_processor_compat(void *rtn)
9295 {
9296         struct vmcs_config vmcs_conf;
9297
9298         *(int *)rtn = 0;
9299         if (setup_vmcs_config(&vmcs_conf) < 0)
9300                 *(int *)rtn = -EIO;
9301         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9302                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9303                                 smp_processor_id());
9304                 *(int *)rtn = -EIO;
9305         }
9306 }
9307
9308 static int get_ept_level(void)
9309 {
9310         return VMX_EPT_DEFAULT_GAW + 1;
9311 }
9312
9313 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9314 {
9315         u8 cache;
9316         u64 ipat = 0;
9317
9318         /* For VT-d and EPT combination
9319          * 1. MMIO: always map as UC
9320          * 2. EPT with VT-d:
9321          *   a. VT-d without snooping control feature: can't guarantee the
9322          *      result, try to trust guest.
9323          *   b. VT-d with snooping control feature: snooping control feature of
9324          *      VT-d engine can guarantee the cache correctness. Just set it
9325          *      to WB to keep consistent with host. So the same as item 3.
9326          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9327          *    consistent with host MTRR
9328          */
9329         if (is_mmio) {
9330                 cache = MTRR_TYPE_UNCACHABLE;
9331                 goto exit;
9332         }
9333
9334         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9335                 ipat = VMX_EPT_IPAT_BIT;
9336                 cache = MTRR_TYPE_WRBACK;
9337                 goto exit;
9338         }
9339
9340         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9341                 ipat = VMX_EPT_IPAT_BIT;
9342                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9343                         cache = MTRR_TYPE_WRBACK;
9344                 else
9345                         cache = MTRR_TYPE_UNCACHABLE;
9346                 goto exit;
9347         }
9348
9349         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9350
9351 exit:
9352         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9353 }
9354
9355 static int vmx_get_lpage_level(void)
9356 {
9357         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9358                 return PT_DIRECTORY_LEVEL;
9359         else
9360                 /* For shadow and EPT supported 1GB page */
9361                 return PT_PDPE_LEVEL;
9362 }
9363
9364 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9365 {
9366         /*
9367          * These bits in the secondary execution controls field
9368          * are dynamic, the others are mostly based on the hypervisor
9369          * architecture and the guest's CPUID.  Do not touch the
9370          * dynamic bits.
9371          */
9372         u32 mask =
9373                 SECONDARY_EXEC_SHADOW_VMCS |
9374                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9375                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9376
9377         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9378
9379         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9380                      (new_ctl & ~mask) | (cur_ctl & mask));
9381 }
9382
9383 /*
9384  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9385  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9386  */
9387 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9388 {
9389         struct vcpu_vmx *vmx = to_vmx(vcpu);
9390         struct kvm_cpuid_entry2 *entry;
9391
9392         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9393         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9394
9395 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9396         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9397                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9398 } while (0)
9399
9400         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9401         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9402         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9403         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9404         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9405         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9406         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9407         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9408         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9409         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9410         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9411         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9412         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9413         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9414         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9415
9416         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9417         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9418         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9419         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9420         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9421         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9422         cr4_fixed1_update(bit(11),            ecx, bit(2));
9423
9424 #undef cr4_fixed1_update
9425 }
9426
9427 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9428 {
9429         struct kvm_cpuid_entry2 *best;
9430         struct vcpu_vmx *vmx = to_vmx(vcpu);
9431         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9432
9433         if (vmx_rdtscp_supported()) {
9434                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9435                 if (!rdtscp_enabled)
9436                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9437
9438                 if (nested) {
9439                         if (rdtscp_enabled)
9440                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9441                                         SECONDARY_EXEC_RDTSCP;
9442                         else
9443                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9444                                         ~SECONDARY_EXEC_RDTSCP;
9445                 }
9446         }
9447
9448         /* Exposing INVPCID only when PCID is exposed */
9449         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9450         if (vmx_invpcid_supported() &&
9451             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9452             !guest_cpuid_has_pcid(vcpu))) {
9453                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9454
9455                 if (best)
9456                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9457         }
9458
9459         if (cpu_has_secondary_exec_ctrls())
9460                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9461
9462         if (nested_vmx_allowed(vcpu))
9463                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9464                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9465         else
9466                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9467                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9468
9469         if (nested_vmx_allowed(vcpu))
9470                 nested_vmx_cr_fixed1_bits_update(vcpu);
9471 }
9472
9473 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9474 {
9475         if (func == 1 && nested)
9476                 entry->ecx |= bit(X86_FEATURE_VMX);
9477 }
9478
9479 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9480                 struct x86_exception *fault)
9481 {
9482         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9483         u32 exit_reason;
9484
9485         if (fault->error_code & PFERR_RSVD_MASK)
9486                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9487         else
9488                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9489         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9490         vmcs12->guest_physical_address = fault->address;
9491 }
9492
9493 /* Callbacks for nested_ept_init_mmu_context: */
9494
9495 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9496 {
9497         /* return the page table to be shadowed - in our case, EPT12 */
9498         return get_vmcs12(vcpu)->ept_pointer;
9499 }
9500
9501 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9502 {
9503         WARN_ON(mmu_is_nested(vcpu));
9504         kvm_init_shadow_ept_mmu(vcpu,
9505                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9506                         VMX_EPT_EXECUTE_ONLY_BIT);
9507         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9508         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9509         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9510
9511         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9512 }
9513
9514 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9515 {
9516         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9517 }
9518
9519 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9520                                             u16 error_code)
9521 {
9522         bool inequality, bit;
9523
9524         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9525         inequality =
9526                 (error_code & vmcs12->page_fault_error_code_mask) !=
9527                  vmcs12->page_fault_error_code_match;
9528         return inequality ^ bit;
9529 }
9530
9531 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9532                 struct x86_exception *fault)
9533 {
9534         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9535
9536         WARN_ON(!is_guest_mode(vcpu));
9537
9538         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9539                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9540                                   vmcs_read32(VM_EXIT_INTR_INFO),
9541                                   vmcs_readl(EXIT_QUALIFICATION));
9542         else
9543                 kvm_inject_page_fault(vcpu, fault);
9544 }
9545
9546 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9547                                                struct vmcs12 *vmcs12);
9548
9549 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9550                                         struct vmcs12 *vmcs12)
9551 {
9552         struct vcpu_vmx *vmx = to_vmx(vcpu);
9553         u64 hpa;
9554
9555         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9556                 /*
9557                  * Translate L1 physical address to host physical
9558                  * address for vmcs02. Keep the page pinned, so this
9559                  * physical address remains valid. We keep a reference
9560                  * to it so we can release it later.
9561                  */
9562                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9563                         nested_release_page(vmx->nested.apic_access_page);
9564                 vmx->nested.apic_access_page =
9565                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9566                 /*
9567                  * If translation failed, no matter: This feature asks
9568                  * to exit when accessing the given address, and if it
9569                  * can never be accessed, this feature won't do
9570                  * anything anyway.
9571                  */
9572                 if (vmx->nested.apic_access_page) {
9573                         hpa = page_to_phys(vmx->nested.apic_access_page);
9574                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9575                 } else {
9576                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9577                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9578                 }
9579         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9580                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9581                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9582                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9583                 kvm_vcpu_reload_apic_access_page(vcpu);
9584         }
9585
9586         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9587                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9588                         nested_release_page(vmx->nested.virtual_apic_page);
9589                 vmx->nested.virtual_apic_page =
9590                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9591
9592                 /*
9593                  * If translation failed, VM entry will fail because
9594                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9595                  * Failing the vm entry is _not_ what the processor
9596                  * does but it's basically the only possibility we
9597                  * have.  We could still enter the guest if CR8 load
9598                  * exits are enabled, CR8 store exits are enabled, and
9599                  * virtualize APIC access is disabled; in this case
9600                  * the processor would never use the TPR shadow and we
9601                  * could simply clear the bit from the execution
9602                  * control.  But such a configuration is useless, so
9603                  * let's keep the code simple.
9604                  */
9605                 if (vmx->nested.virtual_apic_page) {
9606                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9607                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9608                 }
9609         }
9610
9611         if (nested_cpu_has_posted_intr(vmcs12)) {
9612                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9613                         kunmap(vmx->nested.pi_desc_page);
9614                         nested_release_page(vmx->nested.pi_desc_page);
9615                 }
9616                 vmx->nested.pi_desc_page =
9617                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9618                 vmx->nested.pi_desc =
9619                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9620                 if (!vmx->nested.pi_desc) {
9621                         nested_release_page_clean(vmx->nested.pi_desc_page);
9622                         return;
9623                 }
9624                 vmx->nested.pi_desc =
9625                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9626                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9627                         (PAGE_SIZE - 1)));
9628                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9629                         page_to_phys(vmx->nested.pi_desc_page) +
9630                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9631                         (PAGE_SIZE - 1)));
9632         }
9633         if (cpu_has_vmx_msr_bitmap() &&
9634             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9635             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9636                 ;
9637         else
9638                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9639                                 CPU_BASED_USE_MSR_BITMAPS);
9640 }
9641
9642 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9643 {
9644         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9645         struct vcpu_vmx *vmx = to_vmx(vcpu);
9646
9647         if (vcpu->arch.virtual_tsc_khz == 0)
9648                 return;
9649
9650         /* Make sure short timeouts reliably trigger an immediate vmexit.
9651          * hrtimer_start does not guarantee this. */
9652         if (preemption_timeout <= 1) {
9653                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9654                 return;
9655         }
9656
9657         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9658         preemption_timeout *= 1000000;
9659         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9660         hrtimer_start(&vmx->nested.preemption_timer,
9661                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9662 }
9663
9664 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9665                                                 struct vmcs12 *vmcs12)
9666 {
9667         int maxphyaddr;
9668         u64 addr;
9669
9670         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9671                 return 0;
9672
9673         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9674                 WARN_ON(1);
9675                 return -EINVAL;
9676         }
9677         maxphyaddr = cpuid_maxphyaddr(vcpu);
9678
9679         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9680            ((addr + PAGE_SIZE) >> maxphyaddr))
9681                 return -EINVAL;
9682
9683         return 0;
9684 }
9685
9686 /*
9687  * Merge L0's and L1's MSR bitmap, return false to indicate that
9688  * we do not use the hardware.
9689  */
9690 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9691                                                struct vmcs12 *vmcs12)
9692 {
9693         int msr;
9694         struct page *page;
9695         unsigned long *msr_bitmap_l1;
9696         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9697
9698         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9699         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9700                 return false;
9701
9702         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9703         if (!page) {
9704                 WARN_ON(1);
9705                 return false;
9706         }
9707         msr_bitmap_l1 = (unsigned long *)kmap(page);
9708
9709         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9710
9711         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9712                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9713                         for (msr = 0x800; msr <= 0x8ff; msr++)
9714                                 nested_vmx_disable_intercept_for_msr(
9715                                         msr_bitmap_l1, msr_bitmap_l0,
9716                                         msr, MSR_TYPE_R);
9717
9718                 nested_vmx_disable_intercept_for_msr(
9719                                 msr_bitmap_l1, msr_bitmap_l0,
9720                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9721                                 MSR_TYPE_R | MSR_TYPE_W);
9722
9723                 if (nested_cpu_has_vid(vmcs12)) {
9724                         nested_vmx_disable_intercept_for_msr(
9725                                 msr_bitmap_l1, msr_bitmap_l0,
9726                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9727                                 MSR_TYPE_W);
9728                         nested_vmx_disable_intercept_for_msr(
9729                                 msr_bitmap_l1, msr_bitmap_l0,
9730                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9731                                 MSR_TYPE_W);
9732                 }
9733         }
9734         kunmap(page);
9735         nested_release_page_clean(page);
9736
9737         return true;
9738 }
9739
9740 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9741                                            struct vmcs12 *vmcs12)
9742 {
9743         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9744             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9745             !nested_cpu_has_vid(vmcs12) &&
9746             !nested_cpu_has_posted_intr(vmcs12))
9747                 return 0;
9748
9749         /*
9750          * If virtualize x2apic mode is enabled,
9751          * virtualize apic access must be disabled.
9752          */
9753         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9754             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9755                 return -EINVAL;
9756
9757         /*
9758          * If virtual interrupt delivery is enabled,
9759          * we must exit on external interrupts.
9760          */
9761         if (nested_cpu_has_vid(vmcs12) &&
9762            !nested_exit_on_intr(vcpu))
9763                 return -EINVAL;
9764
9765         /*
9766          * bits 15:8 should be zero in posted_intr_nv,
9767          * the descriptor address has been already checked
9768          * in nested_get_vmcs12_pages.
9769          */
9770         if (nested_cpu_has_posted_intr(vmcs12) &&
9771            (!nested_cpu_has_vid(vmcs12) ||
9772             !nested_exit_intr_ack_set(vcpu) ||
9773             vmcs12->posted_intr_nv & 0xff00))
9774                 return -EINVAL;
9775
9776         /* tpr shadow is needed by all apicv features. */
9777         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9778                 return -EINVAL;
9779
9780         return 0;
9781 }
9782
9783 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9784                                        unsigned long count_field,
9785                                        unsigned long addr_field)
9786 {
9787         int maxphyaddr;
9788         u64 count, addr;
9789
9790         if (vmcs12_read_any(vcpu, count_field, &count) ||
9791             vmcs12_read_any(vcpu, addr_field, &addr)) {
9792                 WARN_ON(1);
9793                 return -EINVAL;
9794         }
9795         if (count == 0)
9796                 return 0;
9797         maxphyaddr = cpuid_maxphyaddr(vcpu);
9798         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9799             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9800                 pr_debug_ratelimited(
9801                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9802                         addr_field, maxphyaddr, count, addr);
9803                 return -EINVAL;
9804         }
9805         return 0;
9806 }
9807
9808 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9809                                                 struct vmcs12 *vmcs12)
9810 {
9811         if (vmcs12->vm_exit_msr_load_count == 0 &&
9812             vmcs12->vm_exit_msr_store_count == 0 &&
9813             vmcs12->vm_entry_msr_load_count == 0)
9814                 return 0; /* Fast path */
9815         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9816                                         VM_EXIT_MSR_LOAD_ADDR) ||
9817             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9818                                         VM_EXIT_MSR_STORE_ADDR) ||
9819             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9820                                         VM_ENTRY_MSR_LOAD_ADDR))
9821                 return -EINVAL;
9822         return 0;
9823 }
9824
9825 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9826                                        struct vmx_msr_entry *e)
9827 {
9828         /* x2APIC MSR accesses are not allowed */
9829         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9830                 return -EINVAL;
9831         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9832             e->index == MSR_IA32_UCODE_REV)
9833                 return -EINVAL;
9834         if (e->reserved != 0)
9835                 return -EINVAL;
9836         return 0;
9837 }
9838
9839 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9840                                      struct vmx_msr_entry *e)
9841 {
9842         if (e->index == MSR_FS_BASE ||
9843             e->index == MSR_GS_BASE ||
9844             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9845             nested_vmx_msr_check_common(vcpu, e))
9846                 return -EINVAL;
9847         return 0;
9848 }
9849
9850 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9851                                       struct vmx_msr_entry *e)
9852 {
9853         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9854             nested_vmx_msr_check_common(vcpu, e))
9855                 return -EINVAL;
9856         return 0;
9857 }
9858
9859 /*
9860  * Load guest's/host's msr at nested entry/exit.
9861  * return 0 for success, entry index for failure.
9862  */
9863 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9864 {
9865         u32 i;
9866         struct vmx_msr_entry e;
9867         struct msr_data msr;
9868
9869         msr.host_initiated = false;
9870         for (i = 0; i < count; i++) {
9871                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9872                                         &e, sizeof(e))) {
9873                         pr_debug_ratelimited(
9874                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9875                                 __func__, i, gpa + i * sizeof(e));
9876                         goto fail;
9877                 }
9878                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9879                         pr_debug_ratelimited(
9880                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9881                                 __func__, i, e.index, e.reserved);
9882                         goto fail;
9883                 }
9884                 msr.index = e.index;
9885                 msr.data = e.value;
9886                 if (kvm_set_msr(vcpu, &msr)) {
9887                         pr_debug_ratelimited(
9888                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9889                                 __func__, i, e.index, e.value);
9890                         goto fail;
9891                 }
9892         }
9893         return 0;
9894 fail:
9895         return i + 1;
9896 }
9897
9898 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9899 {
9900         u32 i;
9901         struct vmx_msr_entry e;
9902
9903         for (i = 0; i < count; i++) {
9904                 struct msr_data msr_info;
9905                 if (kvm_vcpu_read_guest(vcpu,
9906                                         gpa + i * sizeof(e),
9907                                         &e, 2 * sizeof(u32))) {
9908                         pr_debug_ratelimited(
9909                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9910                                 __func__, i, gpa + i * sizeof(e));
9911                         return -EINVAL;
9912                 }
9913                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9914                         pr_debug_ratelimited(
9915                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9916                                 __func__, i, e.index, e.reserved);
9917                         return -EINVAL;
9918                 }
9919                 msr_info.host_initiated = false;
9920                 msr_info.index = e.index;
9921                 if (kvm_get_msr(vcpu, &msr_info)) {
9922                         pr_debug_ratelimited(
9923                                 "%s cannot read MSR (%u, 0x%x)\n",
9924                                 __func__, i, e.index);
9925                         return -EINVAL;
9926                 }
9927                 if (kvm_vcpu_write_guest(vcpu,
9928                                          gpa + i * sizeof(e) +
9929                                              offsetof(struct vmx_msr_entry, value),
9930                                          &msr_info.data, sizeof(msr_info.data))) {
9931                         pr_debug_ratelimited(
9932                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9933                                 __func__, i, e.index, msr_info.data);
9934                         return -EINVAL;
9935                 }
9936         }
9937         return 0;
9938 }
9939
9940 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9941 {
9942         unsigned long invalid_mask;
9943
9944         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9945         return (val & invalid_mask) == 0;
9946 }
9947
9948 /*
9949  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9950  * emulating VM entry into a guest with EPT enabled.
9951  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9952  * is assigned to entry_failure_code on failure.
9953  */
9954 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9955                                u32 *entry_failure_code)
9956 {
9957         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9958                 if (!nested_cr3_valid(vcpu, cr3)) {
9959                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9960                         return 1;
9961                 }
9962
9963                 /*
9964                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9965                  * must not be dereferenced.
9966                  */
9967                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9968                     !nested_ept) {
9969                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9970                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9971                                 return 1;
9972                         }
9973                 }
9974
9975                 vcpu->arch.cr3 = cr3;
9976                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9977         }
9978
9979         kvm_mmu_reset_context(vcpu);
9980         return 0;
9981 }
9982
9983 /*
9984  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9985  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9986  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9987  * guest in a way that will both be appropriate to L1's requests, and our
9988  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9989  * function also has additional necessary side-effects, like setting various
9990  * vcpu->arch fields.
9991  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9992  * is assigned to entry_failure_code on failure.
9993  */
9994 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9995                           bool from_vmentry, u32 *entry_failure_code)
9996 {
9997         struct vcpu_vmx *vmx = to_vmx(vcpu);
9998         u32 exec_control;
9999         bool nested_ept_enabled = false;
10000
10001         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10002         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10003         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10004         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10005         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10006         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10007         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10008         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10009         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10010         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10011         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10012         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10013         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10014         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10015         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10016         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10017         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10018         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10019         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10020         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10021         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10022         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10023         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10024         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10025         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10026         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10027         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10028         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10029         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10030         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10031         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10032         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10033         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10034         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10035         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10036         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10037
10038         if (from_vmentry &&
10039             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10040                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10041                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10042         } else {
10043                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10044                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10045         }
10046         if (from_vmentry) {
10047                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10048                              vmcs12->vm_entry_intr_info_field);
10049                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10050                              vmcs12->vm_entry_exception_error_code);
10051                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10052                              vmcs12->vm_entry_instruction_len);
10053                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10054                              vmcs12->guest_interruptibility_info);
10055         } else {
10056                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10057         }
10058         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10059         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10060         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10061                 vmcs12->guest_pending_dbg_exceptions);
10062         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10063         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10064
10065         if (nested_cpu_has_xsaves(vmcs12))
10066                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10067         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10068
10069         exec_control = vmcs12->pin_based_vm_exec_control;
10070
10071         /* Preemption timer setting is only taken from vmcs01.  */
10072         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10073         exec_control |= vmcs_config.pin_based_exec_ctrl;
10074         if (vmx->hv_deadline_tsc == -1)
10075                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10076
10077         /* Posted interrupts setting is only taken from vmcs12.  */
10078         if (nested_cpu_has_posted_intr(vmcs12)) {
10079                 /*
10080                  * Note that we use L0's vector here and in
10081                  * vmx_deliver_nested_posted_interrupt.
10082                  */
10083                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10084                 vmx->nested.pi_pending = false;
10085                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10086         } else {
10087                 exec_control &= ~PIN_BASED_POSTED_INTR;
10088         }
10089
10090         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10091
10092         vmx->nested.preemption_timer_expired = false;
10093         if (nested_cpu_has_preemption_timer(vmcs12))
10094                 vmx_start_preemption_timer(vcpu);
10095
10096         /*
10097          * Whether page-faults are trapped is determined by a combination of
10098          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10099          * If enable_ept, L0 doesn't care about page faults and we should
10100          * set all of these to L1's desires. However, if !enable_ept, L0 does
10101          * care about (at least some) page faults, and because it is not easy
10102          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10103          * to exit on each and every L2 page fault. This is done by setting
10104          * MASK=MATCH=0 and (see below) EB.PF=1.
10105          * Note that below we don't need special code to set EB.PF beyond the
10106          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10107          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10108          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10109          *
10110          * A problem with this approach (when !enable_ept) is that L1 may be
10111          * injected with more page faults than it asked for. This could have
10112          * caused problems, but in practice existing hypervisors don't care.
10113          * To fix this, we will need to emulate the PFEC checking (on the L1
10114          * page tables), using walk_addr(), when injecting PFs to L1.
10115          */
10116         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10117                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10118         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10119                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10120
10121         if (cpu_has_secondary_exec_ctrls()) {
10122                 exec_control = vmx_secondary_exec_control(vmx);
10123
10124                 /* Take the following fields only from vmcs12 */
10125                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10126                                   SECONDARY_EXEC_RDTSCP |
10127                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10128                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10129                 if (nested_cpu_has(vmcs12,
10130                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10131                         exec_control |= vmcs12->secondary_vm_exec_control;
10132
10133                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10134                         vmcs_write64(EOI_EXIT_BITMAP0,
10135                                 vmcs12->eoi_exit_bitmap0);
10136                         vmcs_write64(EOI_EXIT_BITMAP1,
10137                                 vmcs12->eoi_exit_bitmap1);
10138                         vmcs_write64(EOI_EXIT_BITMAP2,
10139                                 vmcs12->eoi_exit_bitmap2);
10140                         vmcs_write64(EOI_EXIT_BITMAP3,
10141                                 vmcs12->eoi_exit_bitmap3);
10142                         vmcs_write16(GUEST_INTR_STATUS,
10143                                 vmcs12->guest_intr_status);
10144                 }
10145
10146                 nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0;
10147
10148                 /*
10149                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10150                  * nested_get_vmcs12_pages will either fix it up or
10151                  * remove the VM execution control.
10152                  */
10153                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10154                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10155
10156                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10157         }
10158
10159
10160         /*
10161          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10162          * Some constant fields are set here by vmx_set_constant_host_state().
10163          * Other fields are different per CPU, and will be set later when
10164          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10165          */
10166         vmx_set_constant_host_state(vmx);
10167
10168         /*
10169          * Set the MSR load/store lists to match L0's settings.
10170          */
10171         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10172         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10173         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10174         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10175         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10176
10177         /*
10178          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10179          * entry, but only if the current (host) sp changed from the value
10180          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10181          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10182          * here we just force the write to happen on entry.
10183          */
10184         vmx->host_rsp = 0;
10185
10186         exec_control = vmx_exec_control(vmx); /* L0's desires */
10187         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10188         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10189         exec_control &= ~CPU_BASED_TPR_SHADOW;
10190         exec_control |= vmcs12->cpu_based_vm_exec_control;
10191
10192         /*
10193          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10194          * nested_get_vmcs12_pages can't fix it up, the illegal value
10195          * will result in a VM entry failure.
10196          */
10197         if (exec_control & CPU_BASED_TPR_SHADOW) {
10198                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10199                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10200         }
10201
10202         /*
10203          * Merging of IO bitmap not currently supported.
10204          * Rather, exit every time.
10205          */
10206         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10207         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10208
10209         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10210
10211         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10212          * bitwise-or of what L1 wants to trap for L2, and what we want to
10213          * trap. Note that CR0.TS also needs updating - we do this later.
10214          */
10215         update_exception_bitmap(vcpu);
10216         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10217         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10218
10219         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10220          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10221          * bits are further modified by vmx_set_efer() below.
10222          */
10223         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10224
10225         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10226          * emulated by vmx_set_efer(), below.
10227          */
10228         vm_entry_controls_init(vmx,
10229                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10230                         ~VM_ENTRY_IA32E_MODE) |
10231                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10232
10233         if (from_vmentry &&
10234             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10235                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10236                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10237         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10238                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10239         }
10240
10241         set_cr4_guest_host_mask(vmx);
10242
10243         if (from_vmentry &&
10244             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10245                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10246
10247         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10248                 vmcs_write64(TSC_OFFSET,
10249                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10250         else
10251                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10252         if (kvm_has_tsc_control)
10253                 decache_tsc_multiplier(vmx);
10254
10255         if (enable_vpid) {
10256                 /*
10257                  * There is no direct mapping between vpid02 and vpid12, the
10258                  * vpid02 is per-vCPU for L0 and reused while the value of
10259                  * vpid12 is changed w/ one invvpid during nested vmentry.
10260                  * The vpid12 is allocated by L1 for L2, so it will not
10261                  * influence global bitmap(for vpid01 and vpid02 allocation)
10262                  * even if spawn a lot of nested vCPUs.
10263                  */
10264                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10265                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10266                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10267                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10268                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10269                         }
10270                 } else {
10271                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10272                         vmx_flush_tlb(vcpu);
10273                 }
10274
10275         }
10276
10277         if (nested_cpu_has_ept(vmcs12)) {
10278                 kvm_mmu_unload(vcpu);
10279                 nested_ept_init_mmu_context(vcpu);
10280         }
10281
10282         /*
10283          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10284          * bits which we consider mandatory enabled.
10285          * The CR0_READ_SHADOW is what L2 should have expected to read given
10286          * the specifications by L1; It's not enough to take
10287          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10288          * have more bits than L1 expected.
10289          */
10290         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10291         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10292
10293         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10294         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10295
10296         if (from_vmentry &&
10297             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10298                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10299         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10300                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10301         else
10302                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10303         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10304         vmx_set_efer(vcpu, vcpu->arch.efer);
10305
10306         /* Shadow page tables on either EPT or shadow page tables. */
10307         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled,
10308                                 entry_failure_code))
10309                 return 1;
10310
10311         kvm_mmu_reset_context(vcpu);
10312
10313         if (!enable_ept)
10314                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10315
10316         /*
10317          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10318          */
10319         if (enable_ept) {
10320                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10321                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10322                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10323                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10324         }
10325
10326         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10327         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10328         return 0;
10329 }
10330
10331 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10332 {
10333         struct vcpu_vmx *vmx = to_vmx(vcpu);
10334
10335         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10336             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10337                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10338
10339         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10340                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10341
10342         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10343                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10344
10345         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10346                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10347
10348         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10349                                 vmx->nested.nested_vmx_procbased_ctls_low,
10350                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10351             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10352                                 vmx->nested.nested_vmx_secondary_ctls_low,
10353                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10354             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10355                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10356                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10357             !vmx_control_verify(vmcs12->vm_exit_controls,
10358                                 vmx->nested.nested_vmx_exit_ctls_low,
10359                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10360             !vmx_control_verify(vmcs12->vm_entry_controls,
10361                                 vmx->nested.nested_vmx_entry_ctls_low,
10362                                 vmx->nested.nested_vmx_entry_ctls_high))
10363                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10364
10365         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10366             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10367             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10368                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10369
10370         return 0;
10371 }
10372
10373 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10374                                   u32 *exit_qual)
10375 {
10376         bool ia32e;
10377
10378         *exit_qual = ENTRY_FAIL_DEFAULT;
10379
10380         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10381             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10382                 return 1;
10383
10384         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10385             vmcs12->vmcs_link_pointer != -1ull) {
10386                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10387                 return 1;
10388         }
10389
10390         /*
10391          * If the load IA32_EFER VM-entry control is 1, the following checks
10392          * are performed on the field for the IA32_EFER MSR:
10393          * - Bits reserved in the IA32_EFER MSR must be 0.
10394          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10395          *   the IA-32e mode guest VM-exit control. It must also be identical
10396          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10397          *   CR0.PG) is 1.
10398          */
10399         if (to_vmx(vcpu)->nested.nested_run_pending &&
10400             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10401                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10402                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10403                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10404                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10405                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10406                         return 1;
10407         }
10408
10409         /*
10410          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10411          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10412          * the values of the LMA and LME bits in the field must each be that of
10413          * the host address-space size VM-exit control.
10414          */
10415         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10416                 ia32e = (vmcs12->vm_exit_controls &
10417                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10418                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10419                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10420                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10421                         return 1;
10422         }
10423
10424         return 0;
10425 }
10426
10427 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10428 {
10429         struct vcpu_vmx *vmx = to_vmx(vcpu);
10430         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10431         struct loaded_vmcs *vmcs02;
10432         int cpu;
10433         u32 msr_entry_idx;
10434         u32 exit_qual;
10435
10436         vmcs02 = nested_get_current_vmcs02(vmx);
10437         if (!vmcs02)
10438                 return -ENOMEM;
10439
10440         enter_guest_mode(vcpu);
10441
10442         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10443                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10444
10445         cpu = get_cpu();
10446         vmx->loaded_vmcs = vmcs02;
10447         vmx_vcpu_put(vcpu);
10448         vmx_vcpu_load(vcpu, cpu);
10449         vcpu->cpu = cpu;
10450         put_cpu();
10451
10452         vmx_segment_cache_clear(vmx);
10453
10454         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10455                 leave_guest_mode(vcpu);
10456                 vmx_load_vmcs01(vcpu);
10457                 nested_vmx_entry_failure(vcpu, vmcs12,
10458                                          EXIT_REASON_INVALID_STATE, exit_qual);
10459                 return 1;
10460         }
10461
10462         nested_get_vmcs12_pages(vcpu, vmcs12);
10463
10464         msr_entry_idx = nested_vmx_load_msr(vcpu,
10465                                             vmcs12->vm_entry_msr_load_addr,
10466                                             vmcs12->vm_entry_msr_load_count);
10467         if (msr_entry_idx) {
10468                 leave_guest_mode(vcpu);
10469                 vmx_load_vmcs01(vcpu);
10470                 nested_vmx_entry_failure(vcpu, vmcs12,
10471                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10472                 return 1;
10473         }
10474
10475         vmcs12->launch_state = 1;
10476
10477         /*
10478          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10479          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10480          * returned as far as L1 is concerned. It will only return (and set
10481          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10482          */
10483         return 0;
10484 }
10485
10486 /*
10487  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10488  * for running an L2 nested guest.
10489  */
10490 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10491 {
10492         struct vmcs12 *vmcs12;
10493         struct vcpu_vmx *vmx = to_vmx(vcpu);
10494         u32 exit_qual;
10495         int ret;
10496
10497         if (!nested_vmx_check_permission(vcpu))
10498                 return 1;
10499
10500         if (!nested_vmx_check_vmcs12(vcpu))
10501                 goto out;
10502
10503         vmcs12 = get_vmcs12(vcpu);
10504
10505         if (enable_shadow_vmcs)
10506                 copy_shadow_to_vmcs12(vmx);
10507
10508         /*
10509          * The nested entry process starts with enforcing various prerequisites
10510          * on vmcs12 as required by the Intel SDM, and act appropriately when
10511          * they fail: As the SDM explains, some conditions should cause the
10512          * instruction to fail, while others will cause the instruction to seem
10513          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10514          * To speed up the normal (success) code path, we should avoid checking
10515          * for misconfigurations which will anyway be caught by the processor
10516          * when using the merged vmcs02.
10517          */
10518         if (vmcs12->launch_state == launch) {
10519                 nested_vmx_failValid(vcpu,
10520                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10521                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10522                 goto out;
10523         }
10524
10525         ret = check_vmentry_prereqs(vcpu, vmcs12);
10526         if (ret) {
10527                 nested_vmx_failValid(vcpu, ret);
10528                 goto out;
10529         }
10530
10531         /*
10532          * After this point, the trap flag no longer triggers a singlestep trap
10533          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10534          * This is not 100% correct; for performance reasons, we delegate most
10535          * of the checks on host state to the processor.  If those fail,
10536          * the singlestep trap is missed.
10537          */
10538         skip_emulated_instruction(vcpu);
10539
10540         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10541         if (ret) {
10542                 nested_vmx_entry_failure(vcpu, vmcs12,
10543                                          EXIT_REASON_INVALID_STATE, exit_qual);
10544                 return 1;
10545         }
10546
10547         /*
10548          * We're finally done with prerequisite checking, and can start with
10549          * the nested entry.
10550          */
10551
10552         ret = enter_vmx_non_root_mode(vcpu, true);
10553         if (ret)
10554                 return ret;
10555
10556         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10557                 return kvm_vcpu_halt(vcpu);
10558
10559         vmx->nested.nested_run_pending = 1;
10560
10561         return 1;
10562
10563 out:
10564         return kvm_skip_emulated_instruction(vcpu);
10565 }
10566
10567 /*
10568  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10569  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10570  * This function returns the new value we should put in vmcs12.guest_cr0.
10571  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10572  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10573  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10574  *     didn't trap the bit, because if L1 did, so would L0).
10575  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10576  *     been modified by L2, and L1 knows it. So just leave the old value of
10577  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10578  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10579  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10580  *     changed these bits, and therefore they need to be updated, but L0
10581  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10582  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10583  */
10584 static inline unsigned long
10585 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10586 {
10587         return
10588         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10589         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10590         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10591                         vcpu->arch.cr0_guest_owned_bits));
10592 }
10593
10594 static inline unsigned long
10595 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10596 {
10597         return
10598         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10599         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10600         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10601                         vcpu->arch.cr4_guest_owned_bits));
10602 }
10603
10604 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10605                                        struct vmcs12 *vmcs12)
10606 {
10607         u32 idt_vectoring;
10608         unsigned int nr;
10609
10610         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10611                 nr = vcpu->arch.exception.nr;
10612                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10613
10614                 if (kvm_exception_is_soft(nr)) {
10615                         vmcs12->vm_exit_instruction_len =
10616                                 vcpu->arch.event_exit_inst_len;
10617                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10618                 } else
10619                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10620
10621                 if (vcpu->arch.exception.has_error_code) {
10622                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10623                         vmcs12->idt_vectoring_error_code =
10624                                 vcpu->arch.exception.error_code;
10625                 }
10626
10627                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10628         } else if (vcpu->arch.nmi_injected) {
10629                 vmcs12->idt_vectoring_info_field =
10630                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10631         } else if (vcpu->arch.interrupt.pending) {
10632                 nr = vcpu->arch.interrupt.nr;
10633                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10634
10635                 if (vcpu->arch.interrupt.soft) {
10636                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10637                         vmcs12->vm_entry_instruction_len =
10638                                 vcpu->arch.event_exit_inst_len;
10639                 } else
10640                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10641
10642                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10643         }
10644 }
10645
10646 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10647 {
10648         struct vcpu_vmx *vmx = to_vmx(vcpu);
10649
10650         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10651             vmx->nested.preemption_timer_expired) {
10652                 if (vmx->nested.nested_run_pending)
10653                         return -EBUSY;
10654                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10655                 return 0;
10656         }
10657
10658         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10659                 if (vmx->nested.nested_run_pending ||
10660                     vcpu->arch.interrupt.pending)
10661                         return -EBUSY;
10662                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10663                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10664                                   INTR_INFO_VALID_MASK, 0);
10665                 /*
10666                  * The NMI-triggered VM exit counts as injection:
10667                  * clear this one and block further NMIs.
10668                  */
10669                 vcpu->arch.nmi_pending = 0;
10670                 vmx_set_nmi_mask(vcpu, true);
10671                 return 0;
10672         }
10673
10674         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10675             nested_exit_on_intr(vcpu)) {
10676                 if (vmx->nested.nested_run_pending)
10677                         return -EBUSY;
10678                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10679                 return 0;
10680         }
10681
10682         vmx_complete_nested_posted_interrupt(vcpu);
10683         return 0;
10684 }
10685
10686 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10687 {
10688         ktime_t remaining =
10689                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10690         u64 value;
10691
10692         if (ktime_to_ns(remaining) <= 0)
10693                 return 0;
10694
10695         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10696         do_div(value, 1000000);
10697         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10698 }
10699
10700 /*
10701  * Update the guest state fields of vmcs12 to reflect changes that
10702  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10703  * VM-entry controls is also updated, since this is really a guest
10704  * state bit.)
10705  */
10706 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10707 {
10708         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10709         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10710
10711         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10712         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10713         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10714
10715         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10716         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10717         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10718         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10719         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10720         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10721         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10722         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10723         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10724         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10725         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10726         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10727         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10728         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10729         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10730         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10731         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10732         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10733         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10734         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10735         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10736         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10737         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10738         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10739         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10740         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10741         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10742         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10743         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10744         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10745         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10746         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10747         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10748         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10749         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10750         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10751
10752         vmcs12->guest_interruptibility_info =
10753                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10754         vmcs12->guest_pending_dbg_exceptions =
10755                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10756         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10757                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10758         else
10759                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10760
10761         if (nested_cpu_has_preemption_timer(vmcs12)) {
10762                 if (vmcs12->vm_exit_controls &
10763                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10764                         vmcs12->vmx_preemption_timer_value =
10765                                 vmx_get_preemption_timer_value(vcpu);
10766                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10767         }
10768
10769         /*
10770          * In some cases (usually, nested EPT), L2 is allowed to change its
10771          * own CR3 without exiting. If it has changed it, we must keep it.
10772          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10773          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10774          *
10775          * Additionally, restore L2's PDPTR to vmcs12.
10776          */
10777         if (enable_ept) {
10778                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10779                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10780                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10781                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10782                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10783         }
10784
10785         if (nested_cpu_has_ept(vmcs12))
10786                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10787
10788         if (nested_cpu_has_vid(vmcs12))
10789                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10790
10791         vmcs12->vm_entry_controls =
10792                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10793                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10794
10795         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10796                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10797                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10798         }
10799
10800         /* TODO: These cannot have changed unless we have MSR bitmaps and
10801          * the relevant bit asks not to trap the change */
10802         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10803                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10804         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10805                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10806         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10807         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10808         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10809         if (kvm_mpx_supported())
10810                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10811         if (nested_cpu_has_xsaves(vmcs12))
10812                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10813 }
10814
10815 /*
10816  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10817  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10818  * and this function updates it to reflect the changes to the guest state while
10819  * L2 was running (and perhaps made some exits which were handled directly by L0
10820  * without going back to L1), and to reflect the exit reason.
10821  * Note that we do not have to copy here all VMCS fields, just those that
10822  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10823  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10824  * which already writes to vmcs12 directly.
10825  */
10826 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10827                            u32 exit_reason, u32 exit_intr_info,
10828                            unsigned long exit_qualification)
10829 {
10830         /* update guest state fields: */
10831         sync_vmcs12(vcpu, vmcs12);
10832
10833         /* update exit information fields: */
10834
10835         vmcs12->vm_exit_reason = exit_reason;
10836         vmcs12->exit_qualification = exit_qualification;
10837
10838         vmcs12->vm_exit_intr_info = exit_intr_info;
10839         if ((vmcs12->vm_exit_intr_info &
10840              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10841             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10842                 vmcs12->vm_exit_intr_error_code =
10843                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10844         vmcs12->idt_vectoring_info_field = 0;
10845         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10846         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10847
10848         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10849                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10850                  * instead of reading the real value. */
10851                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10852
10853                 /*
10854                  * Transfer the event that L0 or L1 may wanted to inject into
10855                  * L2 to IDT_VECTORING_INFO_FIELD.
10856                  */
10857                 vmcs12_save_pending_event(vcpu, vmcs12);
10858         }
10859
10860         /*
10861          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10862          * preserved above and would only end up incorrectly in L1.
10863          */
10864         vcpu->arch.nmi_injected = false;
10865         kvm_clear_exception_queue(vcpu);
10866         kvm_clear_interrupt_queue(vcpu);
10867 }
10868
10869 /*
10870  * A part of what we need to when the nested L2 guest exits and we want to
10871  * run its L1 parent, is to reset L1's guest state to the host state specified
10872  * in vmcs12.
10873  * This function is to be called not only on normal nested exit, but also on
10874  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10875  * Failures During or After Loading Guest State").
10876  * This function should be called when the active VMCS is L1's (vmcs01).
10877  */
10878 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10879                                    struct vmcs12 *vmcs12)
10880 {
10881         struct kvm_segment seg;
10882         u32 entry_failure_code;
10883
10884         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10885                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10886         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10887                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10888         else
10889                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10890         vmx_set_efer(vcpu, vcpu->arch.efer);
10891
10892         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10893         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10894         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10895         /*
10896          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10897          * actually changed, because vmx_set_cr0 refers to efer set above.
10898          *
10899          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10900          * (KVM doesn't change it);
10901          */
10902         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10903         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10904
10905         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10906         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10907         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10908
10909         nested_ept_uninit_mmu_context(vcpu);
10910
10911         /*
10912          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10913          * couldn't have changed.
10914          */
10915         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10916                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10917
10918         if (!enable_ept)
10919                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10920
10921         if (enable_vpid) {
10922                 /*
10923                  * Trivially support vpid by letting L2s share their parent
10924                  * L1's vpid. TODO: move to a more elaborate solution, giving
10925                  * each L2 its own vpid and exposing the vpid feature to L1.
10926                  */
10927                 vmx_flush_tlb(vcpu);
10928         }
10929
10930
10931         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10932         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10933         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10934         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10935         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10936
10937         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10938         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10939                 vmcs_write64(GUEST_BNDCFGS, 0);
10940
10941         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10942                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10943                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10944         }
10945         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10946                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10947                         vmcs12->host_ia32_perf_global_ctrl);
10948
10949         /* Set L1 segment info according to Intel SDM
10950             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10951         seg = (struct kvm_segment) {
10952                 .base = 0,
10953                 .limit = 0xFFFFFFFF,
10954                 .selector = vmcs12->host_cs_selector,
10955                 .type = 11,
10956                 .present = 1,
10957                 .s = 1,
10958                 .g = 1
10959         };
10960         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10961                 seg.l = 1;
10962         else
10963                 seg.db = 1;
10964         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10965         seg = (struct kvm_segment) {
10966                 .base = 0,
10967                 .limit = 0xFFFFFFFF,
10968                 .type = 3,
10969                 .present = 1,
10970                 .s = 1,
10971                 .db = 1,
10972                 .g = 1
10973         };
10974         seg.selector = vmcs12->host_ds_selector;
10975         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10976         seg.selector = vmcs12->host_es_selector;
10977         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10978         seg.selector = vmcs12->host_ss_selector;
10979         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10980         seg.selector = vmcs12->host_fs_selector;
10981         seg.base = vmcs12->host_fs_base;
10982         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10983         seg.selector = vmcs12->host_gs_selector;
10984         seg.base = vmcs12->host_gs_base;
10985         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10986         seg = (struct kvm_segment) {
10987                 .base = vmcs12->host_tr_base,
10988                 .limit = 0x67,
10989                 .selector = vmcs12->host_tr_selector,
10990                 .type = 11,
10991                 .present = 1
10992         };
10993         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10994
10995         kvm_set_dr(vcpu, 7, 0x400);
10996         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10997
10998         if (cpu_has_vmx_msr_bitmap())
10999                 vmx_set_msr_bitmap(vcpu);
11000
11001         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11002                                 vmcs12->vm_exit_msr_load_count))
11003                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11004 }
11005
11006 /*
11007  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11008  * and modify vmcs12 to make it see what it would expect to see there if
11009  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11010  */
11011 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11012                               u32 exit_intr_info,
11013                               unsigned long exit_qualification)
11014 {
11015         struct vcpu_vmx *vmx = to_vmx(vcpu);
11016         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11017         u32 vm_inst_error = 0;
11018
11019         /* trying to cancel vmlaunch/vmresume is a bug */
11020         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11021
11022         leave_guest_mode(vcpu);
11023         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11024                        exit_qualification);
11025
11026         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11027                                  vmcs12->vm_exit_msr_store_count))
11028                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11029
11030         if (unlikely(vmx->fail))
11031                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11032
11033         vmx_load_vmcs01(vcpu);
11034
11035         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11036             && nested_exit_intr_ack_set(vcpu)) {
11037                 int irq = kvm_cpu_get_interrupt(vcpu);
11038                 WARN_ON(irq < 0);
11039                 vmcs12->vm_exit_intr_info = irq |
11040                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11041         }
11042
11043         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11044                                        vmcs12->exit_qualification,
11045                                        vmcs12->idt_vectoring_info_field,
11046                                        vmcs12->vm_exit_intr_info,
11047                                        vmcs12->vm_exit_intr_error_code,
11048                                        KVM_ISA_VMX);
11049
11050         vm_entry_controls_reset_shadow(vmx);
11051         vm_exit_controls_reset_shadow(vmx);
11052         vmx_segment_cache_clear(vmx);
11053
11054         /* if no vmcs02 cache requested, remove the one we used */
11055         if (VMCS02_POOL_SIZE == 0)
11056                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11057
11058         load_vmcs12_host_state(vcpu, vmcs12);
11059
11060         /* Update any VMCS fields that might have changed while L2 ran */
11061         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11062         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11063         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11064         if (vmx->hv_deadline_tsc == -1)
11065                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11066                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11067         else
11068                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11069                               PIN_BASED_VMX_PREEMPTION_TIMER);
11070         if (kvm_has_tsc_control)
11071                 decache_tsc_multiplier(vmx);
11072
11073         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11074                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11075                 vmx_set_virtual_x2apic_mode(vcpu,
11076                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11077         }
11078
11079         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11080         vmx->host_rsp = 0;
11081
11082         /* Unpin physical memory we referred to in vmcs02 */
11083         if (vmx->nested.apic_access_page) {
11084                 nested_release_page(vmx->nested.apic_access_page);
11085                 vmx->nested.apic_access_page = NULL;
11086         }
11087         if (vmx->nested.virtual_apic_page) {
11088                 nested_release_page(vmx->nested.virtual_apic_page);
11089                 vmx->nested.virtual_apic_page = NULL;
11090         }
11091         if (vmx->nested.pi_desc_page) {
11092                 kunmap(vmx->nested.pi_desc_page);
11093                 nested_release_page(vmx->nested.pi_desc_page);
11094                 vmx->nested.pi_desc_page = NULL;
11095                 vmx->nested.pi_desc = NULL;
11096         }
11097
11098         /*
11099          * We are now running in L2, mmu_notifier will force to reload the
11100          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11101          */
11102         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11103
11104         /*
11105          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11106          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11107          * success or failure flag accordingly.
11108          */
11109         if (unlikely(vmx->fail)) {
11110                 vmx->fail = 0;
11111                 nested_vmx_failValid(vcpu, vm_inst_error);
11112         } else
11113                 nested_vmx_succeed(vcpu);
11114         if (enable_shadow_vmcs)
11115                 vmx->nested.sync_shadow_vmcs = true;
11116
11117         /* in case we halted in L2 */
11118         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11119 }
11120
11121 /*
11122  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11123  */
11124 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11125 {
11126         if (is_guest_mode(vcpu))
11127                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11128         free_nested(to_vmx(vcpu));
11129 }
11130
11131 /*
11132  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11133  * 23.7 "VM-entry failures during or after loading guest state" (this also
11134  * lists the acceptable exit-reason and exit-qualification parameters).
11135  * It should only be called before L2 actually succeeded to run, and when
11136  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11137  */
11138 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11139                         struct vmcs12 *vmcs12,
11140                         u32 reason, unsigned long qualification)
11141 {
11142         load_vmcs12_host_state(vcpu, vmcs12);
11143         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11144         vmcs12->exit_qualification = qualification;
11145         nested_vmx_succeed(vcpu);
11146         if (enable_shadow_vmcs)
11147                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11148 }
11149
11150 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11151                                struct x86_instruction_info *info,
11152                                enum x86_intercept_stage stage)
11153 {
11154         return X86EMUL_CONTINUE;
11155 }
11156
11157 #ifdef CONFIG_X86_64
11158 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11159 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11160                                   u64 divisor, u64 *result)
11161 {
11162         u64 low = a << shift, high = a >> (64 - shift);
11163
11164         /* To avoid the overflow on divq */
11165         if (high >= divisor)
11166                 return 1;
11167
11168         /* Low hold the result, high hold rem which is discarded */
11169         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11170             "rm" (divisor), "0" (low), "1" (high));
11171         *result = low;
11172
11173         return 0;
11174 }
11175
11176 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11177 {
11178         struct vcpu_vmx *vmx = to_vmx(vcpu);
11179         u64 tscl = rdtsc();
11180         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11181         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11182
11183         /* Convert to host delta tsc if tsc scaling is enabled */
11184         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11185                         u64_shl_div_u64(delta_tsc,
11186                                 kvm_tsc_scaling_ratio_frac_bits,
11187                                 vcpu->arch.tsc_scaling_ratio,
11188                                 &delta_tsc))
11189                 return -ERANGE;
11190
11191         /*
11192          * If the delta tsc can't fit in the 32 bit after the multi shift,
11193          * we can't use the preemption timer.
11194          * It's possible that it fits on later vmentries, but checking
11195          * on every vmentry is costly so we just use an hrtimer.
11196          */
11197         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11198                 return -ERANGE;
11199
11200         vmx->hv_deadline_tsc = tscl + delta_tsc;
11201         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11202                         PIN_BASED_VMX_PREEMPTION_TIMER);
11203         return 0;
11204 }
11205
11206 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11207 {
11208         struct vcpu_vmx *vmx = to_vmx(vcpu);
11209         vmx->hv_deadline_tsc = -1;
11210         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11211                         PIN_BASED_VMX_PREEMPTION_TIMER);
11212 }
11213 #endif
11214
11215 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11216 {
11217         if (ple_gap)
11218                 shrink_ple_window(vcpu);
11219 }
11220
11221 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11222                                      struct kvm_memory_slot *slot)
11223 {
11224         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11225         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11226 }
11227
11228 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11229                                        struct kvm_memory_slot *slot)
11230 {
11231         kvm_mmu_slot_set_dirty(kvm, slot);
11232 }
11233
11234 static void vmx_flush_log_dirty(struct kvm *kvm)
11235 {
11236         kvm_flush_pml_buffers(kvm);
11237 }
11238
11239 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11240                                            struct kvm_memory_slot *memslot,
11241                                            gfn_t offset, unsigned long mask)
11242 {
11243         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11244 }
11245
11246 /*
11247  * This routine does the following things for vCPU which is going
11248  * to be blocked if VT-d PI is enabled.
11249  * - Store the vCPU to the wakeup list, so when interrupts happen
11250  *   we can find the right vCPU to wake up.
11251  * - Change the Posted-interrupt descriptor as below:
11252  *      'NDST' <-- vcpu->pre_pcpu
11253  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11254  * - If 'ON' is set during this process, which means at least one
11255  *   interrupt is posted for this vCPU, we cannot block it, in
11256  *   this case, return 1, otherwise, return 0.
11257  *
11258  */
11259 static int pi_pre_block(struct kvm_vcpu *vcpu)
11260 {
11261         unsigned long flags;
11262         unsigned int dest;
11263         struct pi_desc old, new;
11264         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11265
11266         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11267                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11268                 !kvm_vcpu_apicv_active(vcpu))
11269                 return 0;
11270
11271         vcpu->pre_pcpu = vcpu->cpu;
11272         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11273                           vcpu->pre_pcpu), flags);
11274         list_add_tail(&vcpu->blocked_vcpu_list,
11275                       &per_cpu(blocked_vcpu_on_cpu,
11276                       vcpu->pre_pcpu));
11277         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11278                                vcpu->pre_pcpu), flags);
11279
11280         do {
11281                 old.control = new.control = pi_desc->control;
11282
11283                 /*
11284                  * We should not block the vCPU if
11285                  * an interrupt is posted for it.
11286                  */
11287                 if (pi_test_on(pi_desc) == 1) {
11288                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11289                                           vcpu->pre_pcpu), flags);
11290                         list_del(&vcpu->blocked_vcpu_list);
11291                         spin_unlock_irqrestore(
11292                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11293                                         vcpu->pre_pcpu), flags);
11294                         vcpu->pre_pcpu = -1;
11295
11296                         return 1;
11297                 }
11298
11299                 WARN((pi_desc->sn == 1),
11300                      "Warning: SN field of posted-interrupts "
11301                      "is set before blocking\n");
11302
11303                 /*
11304                  * Since vCPU can be preempted during this process,
11305                  * vcpu->cpu could be different with pre_pcpu, we
11306                  * need to set pre_pcpu as the destination of wakeup
11307                  * notification event, then we can find the right vCPU
11308                  * to wakeup in wakeup handler if interrupts happen
11309                  * when the vCPU is in blocked state.
11310                  */
11311                 dest = cpu_physical_id(vcpu->pre_pcpu);
11312
11313                 if (x2apic_enabled())
11314                         new.ndst = dest;
11315                 else
11316                         new.ndst = (dest << 8) & 0xFF00;
11317
11318                 /* set 'NV' to 'wakeup vector' */
11319                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11320         } while (cmpxchg(&pi_desc->control, old.control,
11321                         new.control) != old.control);
11322
11323         return 0;
11324 }
11325
11326 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11327 {
11328         if (pi_pre_block(vcpu))
11329                 return 1;
11330
11331         if (kvm_lapic_hv_timer_in_use(vcpu))
11332                 kvm_lapic_switch_to_sw_timer(vcpu);
11333
11334         return 0;
11335 }
11336
11337 static void pi_post_block(struct kvm_vcpu *vcpu)
11338 {
11339         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11340         struct pi_desc old, new;
11341         unsigned int dest;
11342         unsigned long flags;
11343
11344         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11345                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11346                 !kvm_vcpu_apicv_active(vcpu))
11347                 return;
11348
11349         do {
11350                 old.control = new.control = pi_desc->control;
11351
11352                 dest = cpu_physical_id(vcpu->cpu);
11353
11354                 if (x2apic_enabled())
11355                         new.ndst = dest;
11356                 else
11357                         new.ndst = (dest << 8) & 0xFF00;
11358
11359                 /* Allow posting non-urgent interrupts */
11360                 new.sn = 0;
11361
11362                 /* set 'NV' to 'notification vector' */
11363                 new.nv = POSTED_INTR_VECTOR;
11364         } while (cmpxchg(&pi_desc->control, old.control,
11365                         new.control) != old.control);
11366
11367         if(vcpu->pre_pcpu != -1) {
11368                 spin_lock_irqsave(
11369                         &per_cpu(blocked_vcpu_on_cpu_lock,
11370                         vcpu->pre_pcpu), flags);
11371                 list_del(&vcpu->blocked_vcpu_list);
11372                 spin_unlock_irqrestore(
11373                         &per_cpu(blocked_vcpu_on_cpu_lock,
11374                         vcpu->pre_pcpu), flags);
11375                 vcpu->pre_pcpu = -1;
11376         }
11377 }
11378
11379 static void vmx_post_block(struct kvm_vcpu *vcpu)
11380 {
11381         if (kvm_x86_ops->set_hv_timer)
11382                 kvm_lapic_switch_to_hv_timer(vcpu);
11383
11384         pi_post_block(vcpu);
11385 }
11386
11387 /*
11388  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11389  *
11390  * @kvm: kvm
11391  * @host_irq: host irq of the interrupt
11392  * @guest_irq: gsi of the interrupt
11393  * @set: set or unset PI
11394  * returns 0 on success, < 0 on failure
11395  */
11396 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11397                               uint32_t guest_irq, bool set)
11398 {
11399         struct kvm_kernel_irq_routing_entry *e;
11400         struct kvm_irq_routing_table *irq_rt;
11401         struct kvm_lapic_irq irq;
11402         struct kvm_vcpu *vcpu;
11403         struct vcpu_data vcpu_info;
11404         int idx, ret = -EINVAL;
11405
11406         if (!kvm_arch_has_assigned_device(kvm) ||
11407                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11408                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11409                 return 0;
11410
11411         idx = srcu_read_lock(&kvm->irq_srcu);
11412         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11413         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11414
11415         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11416                 if (e->type != KVM_IRQ_ROUTING_MSI)
11417                         continue;
11418                 /*
11419                  * VT-d PI cannot support posting multicast/broadcast
11420                  * interrupts to a vCPU, we still use interrupt remapping
11421                  * for these kind of interrupts.
11422                  *
11423                  * For lowest-priority interrupts, we only support
11424                  * those with single CPU as the destination, e.g. user
11425                  * configures the interrupts via /proc/irq or uses
11426                  * irqbalance to make the interrupts single-CPU.
11427                  *
11428                  * We will support full lowest-priority interrupt later.
11429                  */
11430
11431                 kvm_set_msi_irq(kvm, e, &irq);
11432                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11433                         /*
11434                          * Make sure the IRTE is in remapped mode if
11435                          * we don't handle it in posted mode.
11436                          */
11437                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11438                         if (ret < 0) {
11439                                 printk(KERN_INFO
11440                                    "failed to back to remapped mode, irq: %u\n",
11441                                    host_irq);
11442                                 goto out;
11443                         }
11444
11445                         continue;
11446                 }
11447
11448                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11449                 vcpu_info.vector = irq.vector;
11450
11451                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11452                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11453
11454                 if (set)
11455                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11456                 else {
11457                         /* suppress notification event before unposting */
11458                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11459                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11460                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11461                 }
11462
11463                 if (ret < 0) {
11464                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11465                                         __func__);
11466                         goto out;
11467                 }
11468         }
11469
11470         ret = 0;
11471 out:
11472         srcu_read_unlock(&kvm->irq_srcu, idx);
11473         return ret;
11474 }
11475
11476 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11477 {
11478         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11479                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11480                         FEATURE_CONTROL_LMCE;
11481         else
11482                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11483                         ~FEATURE_CONTROL_LMCE;
11484 }
11485
11486 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11487         .cpu_has_kvm_support = cpu_has_kvm_support,
11488         .disabled_by_bios = vmx_disabled_by_bios,
11489         .hardware_setup = hardware_setup,
11490         .hardware_unsetup = hardware_unsetup,
11491         .check_processor_compatibility = vmx_check_processor_compat,
11492         .hardware_enable = hardware_enable,
11493         .hardware_disable = hardware_disable,
11494         .cpu_has_accelerated_tpr = report_flexpriority,
11495         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11496
11497         .vcpu_create = vmx_create_vcpu,
11498         .vcpu_free = vmx_free_vcpu,
11499         .vcpu_reset = vmx_vcpu_reset,
11500
11501         .prepare_guest_switch = vmx_save_host_state,
11502         .vcpu_load = vmx_vcpu_load,
11503         .vcpu_put = vmx_vcpu_put,
11504
11505         .update_bp_intercept = update_exception_bitmap,
11506         .get_msr = vmx_get_msr,
11507         .set_msr = vmx_set_msr,
11508         .get_segment_base = vmx_get_segment_base,
11509         .get_segment = vmx_get_segment,
11510         .set_segment = vmx_set_segment,
11511         .get_cpl = vmx_get_cpl,
11512         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11513         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11514         .decache_cr3 = vmx_decache_cr3,
11515         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11516         .set_cr0 = vmx_set_cr0,
11517         .set_cr3 = vmx_set_cr3,
11518         .set_cr4 = vmx_set_cr4,
11519         .set_efer = vmx_set_efer,
11520         .get_idt = vmx_get_idt,
11521         .set_idt = vmx_set_idt,
11522         .get_gdt = vmx_get_gdt,
11523         .set_gdt = vmx_set_gdt,
11524         .get_dr6 = vmx_get_dr6,
11525         .set_dr6 = vmx_set_dr6,
11526         .set_dr7 = vmx_set_dr7,
11527         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11528         .cache_reg = vmx_cache_reg,
11529         .get_rflags = vmx_get_rflags,
11530         .set_rflags = vmx_set_rflags,
11531
11532         .get_pkru = vmx_get_pkru,
11533
11534         .tlb_flush = vmx_flush_tlb,
11535
11536         .run = vmx_vcpu_run,
11537         .handle_exit = vmx_handle_exit,
11538         .skip_emulated_instruction = skip_emulated_instruction,
11539         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11540         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11541         .patch_hypercall = vmx_patch_hypercall,
11542         .set_irq = vmx_inject_irq,
11543         .set_nmi = vmx_inject_nmi,
11544         .queue_exception = vmx_queue_exception,
11545         .cancel_injection = vmx_cancel_injection,
11546         .interrupt_allowed = vmx_interrupt_allowed,
11547         .nmi_allowed = vmx_nmi_allowed,
11548         .get_nmi_mask = vmx_get_nmi_mask,
11549         .set_nmi_mask = vmx_set_nmi_mask,
11550         .enable_nmi_window = enable_nmi_window,
11551         .enable_irq_window = enable_irq_window,
11552         .update_cr8_intercept = update_cr8_intercept,
11553         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11554         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11555         .get_enable_apicv = vmx_get_enable_apicv,
11556         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11557         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11558         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11559         .hwapic_irr_update = vmx_hwapic_irr_update,
11560         .hwapic_isr_update = vmx_hwapic_isr_update,
11561         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11562         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11563
11564         .set_tss_addr = vmx_set_tss_addr,
11565         .get_tdp_level = get_ept_level,
11566         .get_mt_mask = vmx_get_mt_mask,
11567
11568         .get_exit_info = vmx_get_exit_info,
11569
11570         .get_lpage_level = vmx_get_lpage_level,
11571
11572         .cpuid_update = vmx_cpuid_update,
11573
11574         .rdtscp_supported = vmx_rdtscp_supported,
11575         .invpcid_supported = vmx_invpcid_supported,
11576
11577         .set_supported_cpuid = vmx_set_supported_cpuid,
11578
11579         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11580
11581         .write_tsc_offset = vmx_write_tsc_offset,
11582
11583         .set_tdp_cr3 = vmx_set_cr3,
11584
11585         .check_intercept = vmx_check_intercept,
11586         .handle_external_intr = vmx_handle_external_intr,
11587         .mpx_supported = vmx_mpx_supported,
11588         .xsaves_supported = vmx_xsaves_supported,
11589
11590         .check_nested_events = vmx_check_nested_events,
11591
11592         .sched_in = vmx_sched_in,
11593
11594         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11595         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11596         .flush_log_dirty = vmx_flush_log_dirty,
11597         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11598
11599         .pre_block = vmx_pre_block,
11600         .post_block = vmx_post_block,
11601
11602         .pmu_ops = &intel_pmu_ops,
11603
11604         .update_pi_irte = vmx_update_pi_irte,
11605
11606 #ifdef CONFIG_X86_64
11607         .set_hv_timer = vmx_set_hv_timer,
11608         .cancel_hv_timer = vmx_cancel_hv_timer,
11609 #endif
11610
11611         .setup_mce = vmx_setup_mce,
11612 };
11613
11614 static int __init vmx_init(void)
11615 {
11616         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11617                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11618         if (r)
11619                 return r;
11620
11621 #ifdef CONFIG_KEXEC_CORE
11622         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11623                            crash_vmclear_local_loaded_vmcss);
11624 #endif
11625
11626         return 0;
11627 }
11628
11629 static void __exit vmx_exit(void)
11630 {
11631 #ifdef CONFIG_KEXEC_CORE
11632         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11633         synchronize_rcu();
11634 #endif
11635
11636         kvm_exit();
11637 }
11638
11639 module_init(vmx_init)
11640 module_exit(vmx_exit)