2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64 static bool __read_mostly enable_vpid = 1;
65 module_param_named(vpid, enable_vpid, bool, 0444);
67 static bool __read_mostly flexpriority_enabled = 1;
68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
70 static bool __read_mostly enable_ept = 1;
71 module_param_named(ept, enable_ept, bool, S_IRUGO);
73 static bool __read_mostly enable_unrestricted_guest = 1;
74 module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
77 static bool __read_mostly enable_ept_ad_bits = 1;
78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80 static bool __read_mostly emulate_invalid_guest_state = true;
81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
83 static bool __read_mostly vmm_exclusive = 1;
84 module_param(vmm_exclusive, bool, S_IRUGO);
86 static bool __read_mostly fasteoi = 1;
87 module_param(fasteoi, bool, S_IRUGO);
89 static bool __read_mostly enable_apicv = 1;
90 module_param(enable_apicv, bool, S_IRUGO);
92 static bool __read_mostly enable_shadow_vmcs = 1;
93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested = 0;
100 module_param(nested, bool, S_IRUGO);
102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
121 * According to test, this time is usually smaller than 128 cycles.
122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
128 #define KVM_VMX_DEFAULT_PLE_GAP 128
129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131 module_param(ple_gap, int, S_IRUGO);
133 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134 module_param(ple_window, int, S_IRUGO);
136 extern const ulong vmx_return;
138 #define NR_AUTOLOAD_MSRS 8
139 #define VMCS02_POOL_SIZE 1
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
156 struct list_head loaded_vmcss_on_cpu_link;
159 struct shared_msr_entry {
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
178 typedef u64 natural_width;
179 struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
204 u64 guest_ia32_perf_global_ctrl;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
293 u32 guest_ldtr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
334 #define VMCS12_REVISION 0x11e57ed0
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
341 #define VMCS12_SIZE 0x1000
343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
345 struct list_head list;
347 struct loaded_vmcs vmcs02;
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
355 /* Has the level1 guest done vmxon? */
358 /* The guest-physical address of the current VMCS L1 keeps for L2 */
360 /* The host-usable pointer to the above */
361 struct page *current_vmcs12_page;
362 struct vmcs12 *current_vmcs12;
363 struct vmcs *current_shadow_vmcs;
365 * Indicates if the shadow vmcs must be updated with the
366 * data hold by vmcs12
368 bool sync_shadow_vmcs;
370 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
371 struct list_head vmcs02_pool;
373 u64 vmcs01_tsc_offset;
374 /* L2 must run next, and mustn't decide to exit to L1. */
375 bool nested_run_pending;
377 * Guest pages referred to in vmcs02 with host-physical pointers, so
378 * we must keep them pinned while L2 runs.
380 struct page *apic_access_page;
381 u64 msr_ia32_feature_control;
383 struct hrtimer preemption_timer;
384 bool preemption_timer_expired;
387 #define POSTED_INTR_ON 0
388 /* Posted-Interrupt Descriptor */
390 u32 pir[8]; /* Posted interrupt requested */
391 u32 control; /* bit 0 of control is outstanding notification bit */
395 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
397 return test_and_set_bit(POSTED_INTR_ON,
398 (unsigned long *)&pi_desc->control);
401 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
403 return test_and_clear_bit(POSTED_INTR_ON,
404 (unsigned long *)&pi_desc->control);
407 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
409 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
413 struct kvm_vcpu vcpu;
414 unsigned long host_rsp;
417 bool nmi_known_unmasked;
419 u32 idt_vectoring_info;
421 struct shared_msr_entry *guest_msrs;
424 unsigned long host_idt_base;
426 u64 msr_host_kernel_gs_base;
427 u64 msr_guest_kernel_gs_base;
429 u32 vm_entry_controls_shadow;
430 u32 vm_exit_controls_shadow;
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
436 struct loaded_vmcs vmcs01;
437 struct loaded_vmcs *loaded_vmcs;
438 bool __launched; /* temporary, used in vmx_vcpu_run */
439 struct msr_autoload {
441 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
442 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
446 u16 fs_sel, gs_sel, ldt_sel;
450 int gs_ldt_reload_needed;
451 int fs_reload_needed;
452 u64 msr_host_bndcfgs;
457 struct kvm_segment segs[8];
460 u32 bitmask; /* 4 bits per segment (1 bit per field) */
461 struct kvm_save_segment {
469 bool emulation_required;
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked;
474 s64 vnmi_blocked_time;
479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc;
482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested;
486 enum segment_cache_field {
495 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
497 return container_of(vcpu, struct vcpu_vmx, vcpu);
500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
506 static unsigned long shadow_read_only_fields[] = {
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
521 VM_EXIT_INSTRUCTION_LEN,
522 IDT_VECTORING_INFO_FIELD,
523 IDT_VECTORING_ERROR_CODE,
524 VM_EXIT_INTR_ERROR_CODE,
526 GUEST_LINEAR_ADDRESS,
527 GUEST_PHYSICAL_ADDRESS
529 static int max_shadow_read_only_fields =
530 ARRAY_SIZE(shadow_read_only_fields);
532 static unsigned long shadow_read_write_fields[] = {
538 GUEST_INTERRUPTIBILITY_INFO,
551 CPU_BASED_VM_EXEC_CONTROL,
552 VM_ENTRY_EXCEPTION_ERROR_CODE,
553 VM_ENTRY_INTR_INFO_FIELD,
554 VM_ENTRY_INSTRUCTION_LEN,
555 VM_ENTRY_EXCEPTION_ERROR_CODE,
561 static int max_shadow_read_write_fields =
562 ARRAY_SIZE(shadow_read_write_fields);
564 static const unsigned short vmcs_field_to_offset_table[] = {
565 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
566 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
567 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
568 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
569 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
570 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
571 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
572 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
573 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
574 FIELD(HOST_ES_SELECTOR, host_es_selector),
575 FIELD(HOST_CS_SELECTOR, host_cs_selector),
576 FIELD(HOST_SS_SELECTOR, host_ss_selector),
577 FIELD(HOST_DS_SELECTOR, host_ds_selector),
578 FIELD(HOST_FS_SELECTOR, host_fs_selector),
579 FIELD(HOST_GS_SELECTOR, host_gs_selector),
580 FIELD(HOST_TR_SELECTOR, host_tr_selector),
581 FIELD64(IO_BITMAP_A, io_bitmap_a),
582 FIELD64(IO_BITMAP_B, io_bitmap_b),
583 FIELD64(MSR_BITMAP, msr_bitmap),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
587 FIELD64(TSC_OFFSET, tsc_offset),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
589 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
590 FIELD64(EPT_POINTER, ept_pointer),
591 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
592 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
593 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
594 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
595 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
597 FIELD64(GUEST_PDPTR0, guest_pdptr0),
598 FIELD64(GUEST_PDPTR1, guest_pdptr1),
599 FIELD64(GUEST_PDPTR2, guest_pdptr2),
600 FIELD64(GUEST_PDPTR3, guest_pdptr3),
601 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
602 FIELD64(HOST_IA32_PAT, host_ia32_pat),
603 FIELD64(HOST_IA32_EFER, host_ia32_efer),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
607 FIELD(EXCEPTION_BITMAP, exception_bitmap),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
610 FIELD(CR3_TARGET_COUNT, cr3_target_count),
611 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
612 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
614 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
619 FIELD(TPR_THRESHOLD, tpr_threshold),
620 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
621 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
622 FIELD(VM_EXIT_REASON, vm_exit_reason),
623 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
624 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
625 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
626 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
627 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
628 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
629 FIELD(GUEST_ES_LIMIT, guest_es_limit),
630 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
631 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
632 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
633 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
634 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
635 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
636 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
637 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
638 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
639 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
640 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
641 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
642 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
643 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
644 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
645 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
646 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
648 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
649 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
650 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
651 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
652 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
653 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
654 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
655 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
656 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
657 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
658 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
659 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
660 FIELD(EXIT_QUALIFICATION, exit_qualification),
661 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
662 FIELD(GUEST_CR0, guest_cr0),
663 FIELD(GUEST_CR3, guest_cr3),
664 FIELD(GUEST_CR4, guest_cr4),
665 FIELD(GUEST_ES_BASE, guest_es_base),
666 FIELD(GUEST_CS_BASE, guest_cs_base),
667 FIELD(GUEST_SS_BASE, guest_ss_base),
668 FIELD(GUEST_DS_BASE, guest_ds_base),
669 FIELD(GUEST_FS_BASE, guest_fs_base),
670 FIELD(GUEST_GS_BASE, guest_gs_base),
671 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
672 FIELD(GUEST_TR_BASE, guest_tr_base),
673 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
674 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
675 FIELD(GUEST_DR7, guest_dr7),
676 FIELD(GUEST_RSP, guest_rsp),
677 FIELD(GUEST_RIP, guest_rip),
678 FIELD(GUEST_RFLAGS, guest_rflags),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
680 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
681 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
682 FIELD(HOST_CR0, host_cr0),
683 FIELD(HOST_CR3, host_cr3),
684 FIELD(HOST_CR4, host_cr4),
685 FIELD(HOST_FS_BASE, host_fs_base),
686 FIELD(HOST_GS_BASE, host_gs_base),
687 FIELD(HOST_TR_BASE, host_tr_base),
688 FIELD(HOST_GDTR_BASE, host_gdtr_base),
689 FIELD(HOST_IDTR_BASE, host_idtr_base),
690 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
691 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
692 FIELD(HOST_RSP, host_rsp),
693 FIELD(HOST_RIP, host_rip),
695 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
697 static inline short vmcs_field_to_offset(unsigned long field)
699 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
701 return vmcs_field_to_offset_table[field];
704 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
706 return to_vmx(vcpu)->nested.current_vmcs12;
709 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
711 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
712 if (is_error_page(page))
718 static void nested_release_page(struct page *page)
720 kvm_release_page_dirty(page);
723 static void nested_release_page_clean(struct page *page)
725 kvm_release_page_clean(page);
728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
729 static u64 construct_eptp(unsigned long root_hpa);
730 static void kvm_cpu_vmxon(u64 addr);
731 static void kvm_cpu_vmxoff(void);
732 static bool vmx_mpx_supported(void);
733 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
734 static void vmx_set_segment(struct kvm_vcpu *vcpu,
735 struct kvm_segment *var, int seg);
736 static void vmx_get_segment(struct kvm_vcpu *vcpu,
737 struct kvm_segment *var, int seg);
738 static bool guest_state_valid(struct kvm_vcpu *vcpu);
739 static u32 vmx_segment_access_rights(struct kvm_segment *var);
740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
741 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
742 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
743 static bool vmx_mpx_supported(void);
745 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
746 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
748 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
749 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
751 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
752 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
754 static unsigned long *vmx_io_bitmap_a;
755 static unsigned long *vmx_io_bitmap_b;
756 static unsigned long *vmx_msr_bitmap_legacy;
757 static unsigned long *vmx_msr_bitmap_longmode;
758 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
759 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
760 static unsigned long *vmx_vmread_bitmap;
761 static unsigned long *vmx_vmwrite_bitmap;
763 static bool cpu_has_load_ia32_efer;
764 static bool cpu_has_load_perf_global_ctrl;
766 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
767 static DEFINE_SPINLOCK(vmx_vpid_lock);
769 static struct vmcs_config {
773 u32 pin_based_exec_ctrl;
774 u32 cpu_based_exec_ctrl;
775 u32 cpu_based_2nd_exec_ctrl;
780 static struct vmx_capability {
785 #define VMX_SEGMENT_FIELD(seg) \
786 [VCPU_SREG_##seg] = { \
787 .selector = GUEST_##seg##_SELECTOR, \
788 .base = GUEST_##seg##_BASE, \
789 .limit = GUEST_##seg##_LIMIT, \
790 .ar_bytes = GUEST_##seg##_AR_BYTES, \
793 static const struct kvm_vmx_segment_field {
798 } kvm_vmx_segment_fields[] = {
799 VMX_SEGMENT_FIELD(CS),
800 VMX_SEGMENT_FIELD(DS),
801 VMX_SEGMENT_FIELD(ES),
802 VMX_SEGMENT_FIELD(FS),
803 VMX_SEGMENT_FIELD(GS),
804 VMX_SEGMENT_FIELD(SS),
805 VMX_SEGMENT_FIELD(TR),
806 VMX_SEGMENT_FIELD(LDTR),
809 static u64 host_efer;
811 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
814 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
815 * away by decrementing the array size.
817 static const u32 vmx_msr_index[] = {
819 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
821 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
825 static inline bool is_page_fault(u32 intr_info)
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
828 INTR_INFO_VALID_MASK)) ==
829 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
832 static inline bool is_no_device(u32 intr_info)
834 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
835 INTR_INFO_VALID_MASK)) ==
836 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
839 static inline bool is_invalid_opcode(u32 intr_info)
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
843 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
846 static inline bool is_external_interrupt(u32 intr_info)
848 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
849 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
852 static inline bool is_machine_check(u32 intr_info)
854 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
855 INTR_INFO_VALID_MASK)) ==
856 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
859 static inline bool cpu_has_vmx_msr_bitmap(void)
861 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
864 static inline bool cpu_has_vmx_tpr_shadow(void)
866 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
869 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
871 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
874 static inline bool cpu_has_secondary_exec_ctrls(void)
876 return vmcs_config.cpu_based_exec_ctrl &
877 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
882 return vmcs_config.cpu_based_2nd_exec_ctrl &
883 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
888 return vmcs_config.cpu_based_2nd_exec_ctrl &
889 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
892 static inline bool cpu_has_vmx_apic_register_virt(void)
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_APIC_REGISTER_VIRT;
898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
900 return vmcs_config.cpu_based_2nd_exec_ctrl &
901 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
904 static inline bool cpu_has_vmx_posted_intr(void)
906 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
909 static inline bool cpu_has_vmx_apicv(void)
911 return cpu_has_vmx_apic_register_virt() &&
912 cpu_has_vmx_virtual_intr_delivery() &&
913 cpu_has_vmx_posted_intr();
916 static inline bool cpu_has_vmx_flexpriority(void)
918 return cpu_has_vmx_tpr_shadow() &&
919 cpu_has_vmx_virtualize_apic_accesses();
922 static inline bool cpu_has_vmx_ept_execute_only(void)
924 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
929 return vmx_capability.ept & VMX_EPTP_UC_BIT;
932 static inline bool cpu_has_vmx_eptp_writeback(void)
934 return vmx_capability.ept & VMX_EPTP_WB_BIT;
937 static inline bool cpu_has_vmx_ept_2m_page(void)
939 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
942 static inline bool cpu_has_vmx_ept_1g_page(void)
944 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
947 static inline bool cpu_has_vmx_ept_4levels(void)
949 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
952 static inline bool cpu_has_vmx_ept_ad_bits(void)
954 return vmx_capability.ept & VMX_EPT_AD_BIT;
957 static inline bool cpu_has_vmx_invept_context(void)
959 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
962 static inline bool cpu_has_vmx_invept_global(void)
964 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
967 static inline bool cpu_has_vmx_invvpid_single(void)
969 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
972 static inline bool cpu_has_vmx_invvpid_global(void)
974 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
977 static inline bool cpu_has_vmx_ept(void)
979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_ENABLE_EPT;
983 static inline bool cpu_has_vmx_unrestricted_guest(void)
985 return vmcs_config.cpu_based_2nd_exec_ctrl &
986 SECONDARY_EXEC_UNRESTRICTED_GUEST;
989 static inline bool cpu_has_vmx_ple(void)
991 return vmcs_config.cpu_based_2nd_exec_ctrl &
992 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
995 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
997 return flexpriority_enabled && irqchip_in_kernel(kvm);
1000 static inline bool cpu_has_vmx_vpid(void)
1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_ENABLE_VPID;
1006 static inline bool cpu_has_vmx_rdtscp(void)
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_RDTSCP;
1012 static inline bool cpu_has_vmx_invpcid(void)
1014 return vmcs_config.cpu_based_2nd_exec_ctrl &
1015 SECONDARY_EXEC_ENABLE_INVPCID;
1018 static inline bool cpu_has_virtual_nmis(void)
1020 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_WBINVD_EXITING;
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1032 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033 /* check if the cpu supports writing r/o exit information fields */
1034 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_SHADOW_VMCS;
1041 static inline bool report_flexpriority(void)
1043 return flexpriority_enabled;
1046 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1048 return vmcs12->cpu_based_vm_exec_control & bit;
1051 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1053 return (vmcs12->cpu_based_vm_exec_control &
1054 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055 (vmcs12->secondary_vm_exec_control & bit);
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1060 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1065 return vmcs12->pin_based_vm_exec_control &
1066 PIN_BASED_VMX_PREEMPTION_TIMER;
1069 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1071 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1074 static inline bool is_exception(u32 intr_info)
1076 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1080 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1082 unsigned long exit_qualification);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084 struct vmcs12 *vmcs12,
1085 u32 reason, unsigned long qualification);
1087 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1091 for (i = 0; i < vmx->nmsrs; ++i)
1092 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1097 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1103 } operand = { vpid, 0, gva };
1105 asm volatile (__ex(ASM_VMX_INVVPID)
1106 /* CF==1 or ZF==1 --> rc = -1 */
1107 "; ja 1f ; ud2 ; 1:"
1108 : : "a"(&operand), "c"(ext) : "cc", "memory");
1111 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1115 } operand = {eptp, gpa};
1117 asm volatile (__ex(ASM_VMX_INVEPT)
1118 /* CF==1 or ZF==1 --> rc = -1 */
1119 "; ja 1f ; ud2 ; 1:\n"
1120 : : "a" (&operand), "c" (ext) : "cc", "memory");
1123 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1127 i = __find_msr_index(vmx, msr);
1129 return &vmx->guest_msrs[i];
1133 static void vmcs_clear(struct vmcs *vmcs)
1135 u64 phys_addr = __pa(vmcs);
1138 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1139 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1142 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1146 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1148 vmcs_clear(loaded_vmcs->vmcs);
1149 loaded_vmcs->cpu = -1;
1150 loaded_vmcs->launched = 0;
1153 static void vmcs_load(struct vmcs *vmcs)
1155 u64 phys_addr = __pa(vmcs);
1158 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1159 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1162 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1168 * This bitmap is used to indicate whether the vmclear
1169 * operation is enabled on all cpus. All disabled by
1172 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1174 static inline void crash_enable_local_vmclear(int cpu)
1176 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1179 static inline void crash_disable_local_vmclear(int cpu)
1181 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1184 static inline int crash_local_vmclear_enabled(int cpu)
1186 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1189 static void crash_vmclear_local_loaded_vmcss(void)
1191 int cpu = raw_smp_processor_id();
1192 struct loaded_vmcs *v;
1194 if (!crash_local_vmclear_enabled(cpu))
1197 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198 loaded_vmcss_on_cpu_link)
1199 vmcs_clear(v->vmcs);
1202 static inline void crash_enable_local_vmclear(int cpu) { }
1203 static inline void crash_disable_local_vmclear(int cpu) { }
1204 #endif /* CONFIG_KEXEC */
1206 static void __loaded_vmcs_clear(void *arg)
1208 struct loaded_vmcs *loaded_vmcs = arg;
1209 int cpu = raw_smp_processor_id();
1211 if (loaded_vmcs->cpu != cpu)
1212 return; /* vcpu migration can race with cpu offline */
1213 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1214 per_cpu(current_vmcs, cpu) = NULL;
1215 crash_disable_local_vmclear(cpu);
1216 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1219 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220 * is before setting loaded_vmcs->vcpu to -1 which is done in
1221 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222 * then adds the vmcs into percpu list before it is deleted.
1226 loaded_vmcs_init(loaded_vmcs);
1227 crash_enable_local_vmclear(cpu);
1230 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1232 int cpu = loaded_vmcs->cpu;
1235 smp_call_function_single(cpu,
1236 __loaded_vmcs_clear, loaded_vmcs, 1);
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1244 if (cpu_has_vmx_invvpid_single())
1245 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1248 static inline void vpid_sync_vcpu_global(void)
1250 if (cpu_has_vmx_invvpid_global())
1251 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1254 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1256 if (cpu_has_vmx_invvpid_single())
1257 vpid_sync_vcpu_single(vmx);
1259 vpid_sync_vcpu_global();
1262 static inline void ept_sync_global(void)
1264 if (cpu_has_vmx_invept_global())
1265 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1268 static inline void ept_sync_context(u64 eptp)
1271 if (cpu_has_vmx_invept_context())
1272 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1278 static __always_inline unsigned long vmcs_readl(unsigned long field)
1280 unsigned long value;
1282 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283 : "=a"(value) : "d"(field) : "cc");
1287 static __always_inline u16 vmcs_read16(unsigned long field)
1289 return vmcs_readl(field);
1292 static __always_inline u32 vmcs_read32(unsigned long field)
1294 return vmcs_readl(field);
1297 static __always_inline u64 vmcs_read64(unsigned long field)
1299 #ifdef CONFIG_X86_64
1300 return vmcs_readl(field);
1302 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1306 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1308 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1313 static void vmcs_writel(unsigned long field, unsigned long value)
1317 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1318 : "=q"(error) : "a"(value), "d"(field) : "cc");
1319 if (unlikely(error))
1320 vmwrite_error(field, value);
1323 static void vmcs_write16(unsigned long field, u16 value)
1325 vmcs_writel(field, value);
1328 static void vmcs_write32(unsigned long field, u32 value)
1330 vmcs_writel(field, value);
1333 static void vmcs_write64(unsigned long field, u64 value)
1335 vmcs_writel(field, value);
1336 #ifndef CONFIG_X86_64
1338 vmcs_writel(field+1, value >> 32);
1342 static void vmcs_clear_bits(unsigned long field, u32 mask)
1344 vmcs_writel(field, vmcs_readl(field) & ~mask);
1347 static void vmcs_set_bits(unsigned long field, u32 mask)
1349 vmcs_writel(field, vmcs_readl(field) | mask);
1352 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1354 vmcs_write32(VM_ENTRY_CONTROLS, val);
1355 vmx->vm_entry_controls_shadow = val;
1358 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1360 if (vmx->vm_entry_controls_shadow != val)
1361 vm_entry_controls_init(vmx, val);
1364 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1366 return vmx->vm_entry_controls_shadow;
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1372 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1377 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1380 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1382 vmcs_write32(VM_EXIT_CONTROLS, val);
1383 vmx->vm_exit_controls_shadow = val;
1386 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1388 if (vmx->vm_exit_controls_shadow != val)
1389 vm_exit_controls_init(vmx, val);
1392 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1394 return vmx->vm_exit_controls_shadow;
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1400 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1405 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1408 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1410 vmx->segment_cache.bitmask = 0;
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1417 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1419 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421 vmx->segment_cache.bitmask = 0;
1423 ret = vmx->segment_cache.bitmask & mask;
1424 vmx->segment_cache.bitmask |= mask;
1428 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1430 u16 *p = &vmx->segment_cache.seg[seg].selector;
1432 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1437 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1439 ulong *p = &vmx->segment_cache.seg[seg].base;
1441 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1446 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1448 u32 *p = &vmx->segment_cache.seg[seg].limit;
1450 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1455 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1457 u32 *p = &vmx->segment_cache.seg[seg].ar;
1459 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1468 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470 if ((vcpu->guest_debug &
1471 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473 eb |= 1u << BP_VECTOR;
1474 if (to_vmx(vcpu)->rmode.vm86_active)
1477 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1478 if (vcpu->fpu_active)
1479 eb &= ~(1u << NM_VECTOR);
1481 /* When we are running a nested L2 guest and L1 specified for it a
1482 * certain exception bitmap, we must trap the same exceptions and pass
1483 * them to L1. When running L2, we will only handle the exceptions
1484 * specified above if L1 did not want them.
1486 if (is_guest_mode(vcpu))
1487 eb |= get_vmcs12(vcpu)->exception_bitmap;
1489 vmcs_write32(EXCEPTION_BITMAP, eb);
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493 unsigned long entry, unsigned long exit)
1495 vm_entry_controls_clearbit(vmx, entry);
1496 vm_exit_controls_clearbit(vmx, exit);
1499 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1502 struct msr_autoload *m = &vmx->msr_autoload;
1506 if (cpu_has_load_ia32_efer) {
1507 clear_atomic_switch_msr_special(vmx,
1508 VM_ENTRY_LOAD_IA32_EFER,
1509 VM_EXIT_LOAD_IA32_EFER);
1513 case MSR_CORE_PERF_GLOBAL_CTRL:
1514 if (cpu_has_load_perf_global_ctrl) {
1515 clear_atomic_switch_msr_special(vmx,
1516 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1523 for (i = 0; i < m->nr; ++i)
1524 if (m->guest[i].index == msr)
1530 m->guest[i] = m->guest[m->nr];
1531 m->host[i] = m->host[m->nr];
1532 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537 unsigned long entry, unsigned long exit,
1538 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539 u64 guest_val, u64 host_val)
1541 vmcs_write64(guest_val_vmcs, guest_val);
1542 vmcs_write64(host_val_vmcs, host_val);
1543 vm_entry_controls_setbit(vmx, entry);
1544 vm_exit_controls_setbit(vmx, exit);
1547 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548 u64 guest_val, u64 host_val)
1551 struct msr_autoload *m = &vmx->msr_autoload;
1555 if (cpu_has_load_ia32_efer) {
1556 add_atomic_switch_msr_special(vmx,
1557 VM_ENTRY_LOAD_IA32_EFER,
1558 VM_EXIT_LOAD_IA32_EFER,
1561 guest_val, host_val);
1565 case MSR_CORE_PERF_GLOBAL_CTRL:
1566 if (cpu_has_load_perf_global_ctrl) {
1567 add_atomic_switch_msr_special(vmx,
1568 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570 GUEST_IA32_PERF_GLOBAL_CTRL,
1571 HOST_IA32_PERF_GLOBAL_CTRL,
1572 guest_val, host_val);
1578 for (i = 0; i < m->nr; ++i)
1579 if (m->guest[i].index == msr)
1582 if (i == NR_AUTOLOAD_MSRS) {
1583 printk_once(KERN_WARNING "Not enough msr switch entries. "
1584 "Can't add msr %x\n", msr);
1586 } else if (i == m->nr) {
1588 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1592 m->guest[i].index = msr;
1593 m->guest[i].value = guest_val;
1594 m->host[i].index = msr;
1595 m->host[i].value = host_val;
1598 static void reload_tss(void)
1601 * VT restores TR but not its size. Useless.
1603 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1604 struct desc_struct *descs;
1606 descs = (void *)gdt->address;
1607 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1616 guest_efer = vmx->vcpu.arch.efer;
1619 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1622 ignore_bits = EFER_NX | EFER_SCE;
1623 #ifdef CONFIG_X86_64
1624 ignore_bits |= EFER_LMA | EFER_LME;
1625 /* SCE is meaningful only in long mode on Intel */
1626 if (guest_efer & EFER_LMA)
1627 ignore_bits &= ~(u64)EFER_SCE;
1629 guest_efer &= ~ignore_bits;
1630 guest_efer |= host_efer & ignore_bits;
1631 vmx->guest_msrs[efer_offset].data = guest_efer;
1632 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1634 clear_atomic_switch_msr(vmx, MSR_EFER);
1635 /* On ept, can't emulate nx, and must switch nx atomically */
1636 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637 guest_efer = vmx->vcpu.arch.efer;
1638 if (!(guest_efer & EFER_LMA))
1639 guest_efer &= ~EFER_LME;
1640 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1647 static unsigned long segment_base(u16 selector)
1649 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1650 struct desc_struct *d;
1651 unsigned long table_base;
1654 if (!(selector & ~3))
1657 table_base = gdt->address;
1659 if (selector & 4) { /* from ldt */
1660 u16 ldt_selector = kvm_read_ldt();
1662 if (!(ldt_selector & ~3))
1665 table_base = segment_base(ldt_selector);
1667 d = (struct desc_struct *)(table_base + (selector & ~7));
1668 v = get_desc_base(d);
1669 #ifdef CONFIG_X86_64
1670 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1676 static inline unsigned long kvm_read_tr_base(void)
1679 asm("str %0" : "=g"(tr));
1680 return segment_base(tr);
1683 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1685 struct vcpu_vmx *vmx = to_vmx(vcpu);
1688 if (vmx->host_state.loaded)
1691 vmx->host_state.loaded = 1;
1693 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1694 * allow segment selectors with cpl > 0 or ti == 1.
1696 vmx->host_state.ldt_sel = kvm_read_ldt();
1697 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1698 savesegment(fs, vmx->host_state.fs_sel);
1699 if (!(vmx->host_state.fs_sel & 7)) {
1700 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1701 vmx->host_state.fs_reload_needed = 0;
1703 vmcs_write16(HOST_FS_SELECTOR, 0);
1704 vmx->host_state.fs_reload_needed = 1;
1706 savesegment(gs, vmx->host_state.gs_sel);
1707 if (!(vmx->host_state.gs_sel & 7))
1708 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1710 vmcs_write16(HOST_GS_SELECTOR, 0);
1711 vmx->host_state.gs_ldt_reload_needed = 1;
1714 #ifdef CONFIG_X86_64
1715 savesegment(ds, vmx->host_state.ds_sel);
1716 savesegment(es, vmx->host_state.es_sel);
1719 #ifdef CONFIG_X86_64
1720 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1723 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1727 #ifdef CONFIG_X86_64
1728 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729 if (is_long_mode(&vmx->vcpu))
1730 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1732 if (boot_cpu_has(X86_FEATURE_MPX))
1733 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1734 for (i = 0; i < vmx->save_nmsrs; ++i)
1735 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1736 vmx->guest_msrs[i].data,
1737 vmx->guest_msrs[i].mask);
1740 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1742 if (!vmx->host_state.loaded)
1745 ++vmx->vcpu.stat.host_state_reload;
1746 vmx->host_state.loaded = 0;
1747 #ifdef CONFIG_X86_64
1748 if (is_long_mode(&vmx->vcpu))
1749 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1751 if (vmx->host_state.gs_ldt_reload_needed) {
1752 kvm_load_ldt(vmx->host_state.ldt_sel);
1753 #ifdef CONFIG_X86_64
1754 load_gs_index(vmx->host_state.gs_sel);
1756 loadsegment(gs, vmx->host_state.gs_sel);
1759 if (vmx->host_state.fs_reload_needed)
1760 loadsegment(fs, vmx->host_state.fs_sel);
1761 #ifdef CONFIG_X86_64
1762 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763 loadsegment(ds, vmx->host_state.ds_sel);
1764 loadsegment(es, vmx->host_state.es_sel);
1768 #ifdef CONFIG_X86_64
1769 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1771 if (vmx->host_state.msr_host_bndcfgs)
1772 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1774 * If the FPU is not active (through the host task or
1775 * the guest vcpu), then restore the cr0.TS bit.
1777 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1779 load_gdt(&__get_cpu_var(host_gdt));
1782 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1785 __vmx_load_host_state(vmx);
1790 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791 * vcpu mutex is already taken.
1793 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
1796 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1799 kvm_cpu_vmxon(phys_addr);
1800 else if (vmx->loaded_vmcs->cpu != cpu)
1801 loaded_vmcs_clear(vmx->loaded_vmcs);
1803 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805 vmcs_load(vmx->loaded_vmcs->vmcs);
1808 if (vmx->loaded_vmcs->cpu != cpu) {
1809 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1810 unsigned long sysenter_esp;
1812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1813 local_irq_disable();
1814 crash_disable_local_vmclear(cpu);
1817 * Read loaded_vmcs->cpu should be before fetching
1818 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819 * See the comments in __loaded_vmcs_clear().
1823 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824 &per_cpu(loaded_vmcss_on_cpu, cpu));
1825 crash_enable_local_vmclear(cpu);
1829 * Linux uses per-cpu TSS and GDT, so set these when switching
1832 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1833 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1835 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1837 vmx->loaded_vmcs->cpu = cpu;
1841 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1843 __vmx_load_host_state(to_vmx(vcpu));
1844 if (!vmm_exclusive) {
1845 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1851 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1855 if (vcpu->fpu_active)
1857 vcpu->fpu_active = 1;
1858 cr0 = vmcs_readl(GUEST_CR0);
1859 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861 vmcs_writel(GUEST_CR0, cr0);
1862 update_exception_bitmap(vcpu);
1863 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1864 if (is_guest_mode(vcpu))
1865 vcpu->arch.cr0_guest_owned_bits &=
1866 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1867 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1873 * Return the cr0 value that a nested guest would read. This is a combination
1874 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875 * its hypervisor (cr0_read_shadow).
1877 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1879 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1882 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1884 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1888 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1890 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891 * set this *before* calling this function.
1893 vmx_decache_cr0_guest_bits(vcpu);
1894 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1895 update_exception_bitmap(vcpu);
1896 vcpu->arch.cr0_guest_owned_bits = 0;
1897 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898 if (is_guest_mode(vcpu)) {
1900 * L1's specified read shadow might not contain the TS bit,
1901 * so now that we turned on shadowing of this bit, we need to
1902 * set this bit of the shadow. Like in nested_vmx_run we need
1903 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904 * up-to-date here because we just decached cr0.TS (and we'll
1905 * only update vmcs12->guest_cr0 on nested exit).
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909 (vcpu->arch.cr0 & X86_CR0_TS);
1910 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1912 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1917 unsigned long rflags, save_rflags;
1919 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921 rflags = vmcs_readl(GUEST_RFLAGS);
1922 if (to_vmx(vcpu)->rmode.vm86_active) {
1923 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1927 to_vmx(vcpu)->rflags = rflags;
1929 return to_vmx(vcpu)->rflags;
1932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1934 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935 to_vmx(vcpu)->rflags = rflags;
1936 if (to_vmx(vcpu)->rmode.vm86_active) {
1937 to_vmx(vcpu)->rmode.save_rflags = rflags;
1938 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1940 vmcs_writel(GUEST_RFLAGS, rflags);
1943 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1945 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1948 if (interruptibility & GUEST_INTR_STATE_STI)
1949 ret |= KVM_X86_SHADOW_INT_STI;
1950 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1951 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1958 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959 u32 interruptibility = interruptibility_old;
1961 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1963 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1964 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1965 else if (mask & KVM_X86_SHADOW_INT_STI)
1966 interruptibility |= GUEST_INTR_STATE_STI;
1968 if ((interruptibility != interruptibility_old))
1969 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1972 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1976 rip = kvm_rip_read(vcpu);
1977 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1978 kvm_rip_write(vcpu, rip);
1980 /* skipping an emulated instruction also counts */
1981 vmx_set_interrupt_shadow(vcpu, 0);
1985 * KVM wants to inject page-faults which it got to the guest. This function
1986 * checks whether in a nested guest, we need to inject them to L1 or L2.
1988 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1990 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1992 if (!(vmcs12->exception_bitmap & (1u << nr)))
1995 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996 vmcs_read32(VM_EXIT_INTR_INFO),
1997 vmcs_readl(EXIT_QUALIFICATION));
2001 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2002 bool has_error_code, u32 error_code,
2005 struct vcpu_vmx *vmx = to_vmx(vcpu);
2006 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2008 if (!reinject && is_guest_mode(vcpu) &&
2009 nested_vmx_check_exception(vcpu, nr))
2012 if (has_error_code) {
2013 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2014 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2017 if (vmx->rmode.vm86_active) {
2019 if (kvm_exception_is_soft(nr))
2020 inc_eip = vcpu->arch.event_exit_inst_len;
2021 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2026 if (kvm_exception_is_soft(nr)) {
2027 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028 vmx->vcpu.arch.event_exit_inst_len);
2029 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2031 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2036 static bool vmx_rdtscp_supported(void)
2038 return cpu_has_vmx_rdtscp();
2041 static bool vmx_invpcid_supported(void)
2043 return cpu_has_vmx_invpcid() && enable_ept;
2047 * Swap MSR entry in host/guest MSR entry array.
2049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2051 struct shared_msr_entry tmp;
2053 tmp = vmx->guest_msrs[to];
2054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055 vmx->guest_msrs[from] = tmp;
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2060 unsigned long *msr_bitmap;
2062 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063 if (is_long_mode(vcpu))
2064 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2066 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2068 if (is_long_mode(vcpu))
2069 msr_bitmap = vmx_msr_bitmap_longmode;
2071 msr_bitmap = vmx_msr_bitmap_legacy;
2074 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2078 * Set up the vmcs to automatically save and restore system
2079 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2080 * mode, as fiddling with msrs is very expensive.
2082 static void setup_msrs(struct vcpu_vmx *vmx)
2084 int save_nmsrs, index;
2087 #ifdef CONFIG_X86_64
2088 if (is_long_mode(&vmx->vcpu)) {
2089 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2091 move_msr_up(vmx, index, save_nmsrs++);
2092 index = __find_msr_index(vmx, MSR_LSTAR);
2094 move_msr_up(vmx, index, save_nmsrs++);
2095 index = __find_msr_index(vmx, MSR_CSTAR);
2097 move_msr_up(vmx, index, save_nmsrs++);
2098 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099 if (index >= 0 && vmx->rdtscp_enabled)
2100 move_msr_up(vmx, index, save_nmsrs++);
2102 * MSR_STAR is only needed on long mode guests, and only
2103 * if efer.sce is enabled.
2105 index = __find_msr_index(vmx, MSR_STAR);
2106 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2107 move_msr_up(vmx, index, save_nmsrs++);
2110 index = __find_msr_index(vmx, MSR_EFER);
2111 if (index >= 0 && update_transition_efer(vmx, index))
2112 move_msr_up(vmx, index, save_nmsrs++);
2114 vmx->save_nmsrs = save_nmsrs;
2116 if (cpu_has_vmx_msr_bitmap())
2117 vmx_set_msr_bitmap(&vmx->vcpu);
2121 * reads and returns guest's timestamp counter "register"
2122 * guest_tsc = host_tsc + tsc_offset -- 21.3
2124 static u64 guest_read_tsc(void)
2126 u64 host_tsc, tsc_offset;
2129 tsc_offset = vmcs_read64(TSC_OFFSET);
2130 return host_tsc + tsc_offset;
2134 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135 * counter, even if a nested guest (L2) is currently running.
2137 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2141 tsc_offset = is_guest_mode(vcpu) ?
2142 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143 vmcs_read64(TSC_OFFSET);
2144 return host_tsc + tsc_offset;
2148 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2149 * software catchup for faster rates on slower CPUs.
2151 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2156 if (user_tsc_khz > tsc_khz) {
2157 vcpu->arch.tsc_catchup = 1;
2158 vcpu->arch.tsc_always_catchup = 1;
2160 WARN(1, "user requested TSC rate below hardware speed\n");
2163 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2165 return vmcs_read64(TSC_OFFSET);
2169 * writes 'offset' into guest's timestamp counter offset register
2171 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2173 if (is_guest_mode(vcpu)) {
2175 * We're here if L1 chose not to trap WRMSR to TSC. According
2176 * to the spec, this should set L1's TSC; The offset that L1
2177 * set for L2 remains unchanged, and still needs to be added
2178 * to the newly set TSC to get L2's TSC.
2180 struct vmcs12 *vmcs12;
2181 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182 /* recalculate vmcs02.TSC_OFFSET: */
2183 vmcs12 = get_vmcs12(vcpu);
2184 vmcs_write64(TSC_OFFSET, offset +
2185 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186 vmcs12->tsc_offset : 0));
2188 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189 vmcs_read64(TSC_OFFSET), offset);
2190 vmcs_write64(TSC_OFFSET, offset);
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2196 u64 offset = vmcs_read64(TSC_OFFSET);
2198 vmcs_write64(TSC_OFFSET, offset + adjustment);
2199 if (is_guest_mode(vcpu)) {
2200 /* Even when running L2, the adjustment needs to apply to L1 */
2201 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2203 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204 offset + adjustment);
2207 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2209 return target_tsc - native_read_tsc();
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2214 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2219 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221 * all guests if the "nested" module option is off, and can also be disabled
2222 * for a single guest by disabling its VMX cpuid bit.
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2226 return nested && guest_cpuid_has_vmx(vcpu);
2230 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231 * returned for the various VMX controls MSRs when nested VMX is enabled.
2232 * The same values should also be used to verify that vmcs12 control fields are
2233 * valid during nested entry from L1 to L2.
2234 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236 * bit in the high half is on if the corresponding bit in the control field
2237 * may be on. See also vmx_control_verify().
2238 * TODO: allow these variables to be modified (downgraded) by module options
2241 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2246 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2247 static u32 nested_vmx_ept_caps;
2248 static __init void nested_vmx_setup_ctls_msrs(void)
2251 * Note that as a general rule, the high half of the MSRs (bits in
2252 * the control fields which may be 1) should be initialized by the
2253 * intersection of the underlying hardware's MSR (i.e., features which
2254 * can be supported) and the list of features we want to expose -
2255 * because they are known to be properly supported in our code.
2256 * Also, usually, the low half of the MSRs (bits which must be 1) can
2257 * be set to 0, meaning that L1 may turn off any of these bits. The
2258 * reason is that if one of these bits is necessary, it will appear
2259 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260 * fields of vmcs01 and vmcs02, will turn these bits off - and
2261 * nested_vmx_exit_handled() will not pass related exits to L1.
2262 * These rules have exceptions below.
2265 /* pin-based controls */
2266 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2269 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2272 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2274 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2276 PIN_BASED_VMX_PREEMPTION_TIMER;
2280 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2283 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2285 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2286 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2287 nested_vmx_exit_ctls_high &=
2288 #ifdef CONFIG_X86_64
2289 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2291 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2294 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2295 if (vmx_mpx_supported())
2296 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2298 /* entry controls */
2299 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2300 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2301 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2302 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2303 nested_vmx_entry_ctls_high &=
2304 #ifdef CONFIG_X86_64
2305 VM_ENTRY_IA32E_MODE |
2307 VM_ENTRY_LOAD_IA32_PAT;
2308 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2309 VM_ENTRY_LOAD_IA32_EFER);
2310 if (vmx_mpx_supported())
2311 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2313 /* cpu-based controls */
2314 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2315 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2316 nested_vmx_procbased_ctls_low = 0;
2317 nested_vmx_procbased_ctls_high &=
2318 CPU_BASED_VIRTUAL_INTR_PENDING |
2319 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2320 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2321 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2322 CPU_BASED_CR3_STORE_EXITING |
2323 #ifdef CONFIG_X86_64
2324 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2326 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2327 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2328 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2329 CPU_BASED_PAUSE_EXITING |
2330 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2332 * We can allow some features even when not supported by the
2333 * hardware. For example, L1 can specify an MSR bitmap - and we
2334 * can use it to avoid exits to L1 - even when L0 runs L2
2335 * without MSR bitmaps.
2337 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2339 /* secondary cpu-based controls */
2340 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2341 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2342 nested_vmx_secondary_ctls_low = 0;
2343 nested_vmx_secondary_ctls_high &=
2344 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2345 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2346 SECONDARY_EXEC_WBINVD_EXITING;
2349 /* nested EPT: emulate EPT also to L1 */
2350 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2351 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2352 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2354 nested_vmx_ept_caps &= vmx_capability.ept;
2356 * Since invept is completely emulated we support both global
2357 * and context invalidation independent of what host cpu
2360 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2361 VMX_EPT_EXTENT_CONTEXT_BIT;
2363 nested_vmx_ept_caps = 0;
2365 /* miscellaneous data */
2366 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2367 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2368 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2369 VMX_MISC_ACTIVITY_HLT;
2370 nested_vmx_misc_high = 0;
2373 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2376 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2378 return ((control & high) | low) == control;
2381 static inline u64 vmx_control_msr(u32 low, u32 high)
2383 return low | ((u64)high << 32);
2386 /* Returns 0 on success, non-0 otherwise. */
2387 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2389 switch (msr_index) {
2390 case MSR_IA32_VMX_BASIC:
2392 * This MSR reports some information about VMX support. We
2393 * should return information about the VMX we emulate for the
2394 * guest, and the VMCS structure we give it - not about the
2395 * VMX support of the underlying hardware.
2397 *pdata = VMCS12_REVISION |
2398 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2401 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402 case MSR_IA32_VMX_PINBASED_CTLS:
2403 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404 nested_vmx_pinbased_ctls_high);
2406 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407 case MSR_IA32_VMX_PROCBASED_CTLS:
2408 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409 nested_vmx_procbased_ctls_high);
2411 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412 case MSR_IA32_VMX_EXIT_CTLS:
2413 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414 nested_vmx_exit_ctls_high);
2416 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417 case MSR_IA32_VMX_ENTRY_CTLS:
2418 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419 nested_vmx_entry_ctls_high);
2421 case MSR_IA32_VMX_MISC:
2422 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423 nested_vmx_misc_high);
2426 * These MSRs specify bits which the guest must keep fixed (on or off)
2427 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428 * We picked the standard core2 setting.
2430 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2432 case MSR_IA32_VMX_CR0_FIXED0:
2433 *pdata = VMXON_CR0_ALWAYSON;
2435 case MSR_IA32_VMX_CR0_FIXED1:
2438 case MSR_IA32_VMX_CR4_FIXED0:
2439 *pdata = VMXON_CR4_ALWAYSON;
2441 case MSR_IA32_VMX_CR4_FIXED1:
2444 case MSR_IA32_VMX_VMCS_ENUM:
2447 case MSR_IA32_VMX_PROCBASED_CTLS2:
2448 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449 nested_vmx_secondary_ctls_high);
2451 case MSR_IA32_VMX_EPT_VPID_CAP:
2452 /* Currently, no nested vpid support */
2453 *pdata = nested_vmx_ept_caps;
2463 * Reads an msr value (of 'msr_index') into 'pdata'.
2464 * Returns 0 on success, non-0 otherwise.
2465 * Assumes vcpu_load() was already called.
2467 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2470 struct shared_msr_entry *msr;
2473 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2477 switch (msr_index) {
2478 #ifdef CONFIG_X86_64
2480 data = vmcs_readl(GUEST_FS_BASE);
2483 data = vmcs_readl(GUEST_GS_BASE);
2485 case MSR_KERNEL_GS_BASE:
2486 vmx_load_host_state(to_vmx(vcpu));
2487 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2491 return kvm_get_msr_common(vcpu, msr_index, pdata);
2493 data = guest_read_tsc();
2495 case MSR_IA32_SYSENTER_CS:
2496 data = vmcs_read32(GUEST_SYSENTER_CS);
2498 case MSR_IA32_SYSENTER_EIP:
2499 data = vmcs_readl(GUEST_SYSENTER_EIP);
2501 case MSR_IA32_SYSENTER_ESP:
2502 data = vmcs_readl(GUEST_SYSENTER_ESP);
2504 case MSR_IA32_BNDCFGS:
2505 if (!vmx_mpx_supported())
2507 data = vmcs_read64(GUEST_BNDCFGS);
2509 case MSR_IA32_FEATURE_CONTROL:
2510 if (!nested_vmx_allowed(vcpu))
2512 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2514 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515 if (!nested_vmx_allowed(vcpu))
2517 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2519 if (!to_vmx(vcpu)->rdtscp_enabled)
2521 /* Otherwise falls through */
2523 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2528 return kvm_get_msr_common(vcpu, msr_index, pdata);
2535 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2538 * Writes msr value into into the appropriate "register".
2539 * Returns 0 on success, non-0 otherwise.
2540 * Assumes vcpu_load() was already called.
2542 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2544 struct vcpu_vmx *vmx = to_vmx(vcpu);
2545 struct shared_msr_entry *msr;
2547 u32 msr_index = msr_info->index;
2548 u64 data = msr_info->data;
2550 switch (msr_index) {
2552 ret = kvm_set_msr_common(vcpu, msr_info);
2554 #ifdef CONFIG_X86_64
2556 vmx_segment_cache_clear(vmx);
2557 vmcs_writel(GUEST_FS_BASE, data);
2560 vmx_segment_cache_clear(vmx);
2561 vmcs_writel(GUEST_GS_BASE, data);
2563 case MSR_KERNEL_GS_BASE:
2564 vmx_load_host_state(vmx);
2565 vmx->msr_guest_kernel_gs_base = data;
2568 case MSR_IA32_SYSENTER_CS:
2569 vmcs_write32(GUEST_SYSENTER_CS, data);
2571 case MSR_IA32_SYSENTER_EIP:
2572 vmcs_writel(GUEST_SYSENTER_EIP, data);
2574 case MSR_IA32_SYSENTER_ESP:
2575 vmcs_writel(GUEST_SYSENTER_ESP, data);
2577 case MSR_IA32_BNDCFGS:
2578 if (!vmx_mpx_supported())
2580 vmcs_write64(GUEST_BNDCFGS, data);
2583 kvm_write_tsc(vcpu, msr_info);
2585 case MSR_IA32_CR_PAT:
2586 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587 vmcs_write64(GUEST_IA32_PAT, data);
2588 vcpu->arch.pat = data;
2591 ret = kvm_set_msr_common(vcpu, msr_info);
2593 case MSR_IA32_TSC_ADJUST:
2594 ret = kvm_set_msr_common(vcpu, msr_info);
2596 case MSR_IA32_FEATURE_CONTROL:
2597 if (!nested_vmx_allowed(vcpu) ||
2598 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2601 vmx->nested.msr_ia32_feature_control = data;
2602 if (msr_info->host_initiated && data == 0)
2603 vmx_leave_nested(vcpu);
2605 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606 return 1; /* they are read-only */
2608 if (!vmx->rdtscp_enabled)
2610 /* Check reserved bit, higher 32 bits should be zero */
2611 if ((data >> 32) != 0)
2613 /* Otherwise falls through */
2615 msr = find_msr_entry(vmx, msr_index);
2618 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2620 kvm_set_shared_msr(msr->index, msr->data,
2626 ret = kvm_set_msr_common(vcpu, msr_info);
2632 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2634 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2637 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2640 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2642 case VCPU_EXREG_PDPTR:
2644 ept_save_pdptrs(vcpu);
2651 static __init int cpu_has_kvm_support(void)
2653 return cpu_has_vmx();
2656 static __init int vmx_disabled_by_bios(void)
2660 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2661 if (msr & FEATURE_CONTROL_LOCKED) {
2662 /* launched w/ TXT and VMX disabled */
2663 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2666 /* launched w/o TXT and VMX only enabled w/ TXT */
2667 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2668 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2669 && !tboot_enabled()) {
2670 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2671 "activate TXT before enabling KVM\n");
2674 /* launched w/o TXT and VMX disabled */
2675 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676 && !tboot_enabled())
2683 static void kvm_cpu_vmxon(u64 addr)
2685 asm volatile (ASM_VMX_VMXON_RAX
2686 : : "a"(&addr), "m"(addr)
2690 static int hardware_enable(void *garbage)
2692 int cpu = raw_smp_processor_id();
2693 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2696 if (read_cr4() & X86_CR4_VMXE)
2699 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2702 * Now we can enable the vmclear operation in kdump
2703 * since the loaded_vmcss_on_cpu list on this cpu
2704 * has been initialized.
2706 * Though the cpu is not in VMX operation now, there
2707 * is no problem to enable the vmclear operation
2708 * for the loaded_vmcss_on_cpu list is empty!
2710 crash_enable_local_vmclear(cpu);
2712 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2714 test_bits = FEATURE_CONTROL_LOCKED;
2715 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716 if (tboot_enabled())
2717 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2719 if ((old & test_bits) != test_bits) {
2720 /* enable and lock */
2721 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2723 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2725 if (vmm_exclusive) {
2726 kvm_cpu_vmxon(phys_addr);
2730 native_store_gdt(&__get_cpu_var(host_gdt));
2735 static void vmclear_local_loaded_vmcss(void)
2737 int cpu = raw_smp_processor_id();
2738 struct loaded_vmcs *v, *n;
2740 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741 loaded_vmcss_on_cpu_link)
2742 __loaded_vmcs_clear(v);
2746 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2749 static void kvm_cpu_vmxoff(void)
2751 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2754 static void hardware_disable(void *garbage)
2756 if (vmm_exclusive) {
2757 vmclear_local_loaded_vmcss();
2760 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2763 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2764 u32 msr, u32 *result)
2766 u32 vmx_msr_low, vmx_msr_high;
2767 u32 ctl = ctl_min | ctl_opt;
2769 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2771 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2774 /* Ensure minimum (required) set of control bits are supported. */
2782 static __init bool allow_1_setting(u32 msr, u32 ctl)
2784 u32 vmx_msr_low, vmx_msr_high;
2786 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787 return vmx_msr_high & ctl;
2790 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2792 u32 vmx_msr_low, vmx_msr_high;
2793 u32 min, opt, min2, opt2;
2794 u32 _pin_based_exec_control = 0;
2795 u32 _cpu_based_exec_control = 0;
2796 u32 _cpu_based_2nd_exec_control = 0;
2797 u32 _vmexit_control = 0;
2798 u32 _vmentry_control = 0;
2800 min = CPU_BASED_HLT_EXITING |
2801 #ifdef CONFIG_X86_64
2802 CPU_BASED_CR8_LOAD_EXITING |
2803 CPU_BASED_CR8_STORE_EXITING |
2805 CPU_BASED_CR3_LOAD_EXITING |
2806 CPU_BASED_CR3_STORE_EXITING |
2807 CPU_BASED_USE_IO_BITMAPS |
2808 CPU_BASED_MOV_DR_EXITING |
2809 CPU_BASED_USE_TSC_OFFSETING |
2810 CPU_BASED_MWAIT_EXITING |
2811 CPU_BASED_MONITOR_EXITING |
2812 CPU_BASED_INVLPG_EXITING |
2813 CPU_BASED_RDPMC_EXITING;
2815 opt = CPU_BASED_TPR_SHADOW |
2816 CPU_BASED_USE_MSR_BITMAPS |
2817 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2818 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819 &_cpu_based_exec_control) < 0)
2821 #ifdef CONFIG_X86_64
2822 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824 ~CPU_BASED_CR8_STORE_EXITING;
2826 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2828 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2829 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2830 SECONDARY_EXEC_WBINVD_EXITING |
2831 SECONDARY_EXEC_ENABLE_VPID |
2832 SECONDARY_EXEC_ENABLE_EPT |
2833 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2834 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2835 SECONDARY_EXEC_RDTSCP |
2836 SECONDARY_EXEC_ENABLE_INVPCID |
2837 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2838 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839 SECONDARY_EXEC_SHADOW_VMCS;
2840 if (adjust_vmx_controls(min2, opt2,
2841 MSR_IA32_VMX_PROCBASED_CTLS2,
2842 &_cpu_based_2nd_exec_control) < 0)
2845 #ifndef CONFIG_X86_64
2846 if (!(_cpu_based_2nd_exec_control &
2847 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2851 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852 _cpu_based_2nd_exec_control &= ~(
2853 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2854 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2857 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2858 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2860 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861 CPU_BASED_CR3_STORE_EXITING |
2862 CPU_BASED_INVLPG_EXITING);
2863 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864 vmx_capability.ept, vmx_capability.vpid);
2867 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2868 #ifdef CONFIG_X86_64
2869 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2871 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2872 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2873 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874 &_vmexit_control) < 0)
2877 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880 &_pin_based_exec_control) < 0)
2883 if (!(_cpu_based_2nd_exec_control &
2884 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2888 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2889 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2890 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891 &_vmentry_control) < 0)
2894 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2896 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2900 #ifdef CONFIG_X86_64
2901 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902 if (vmx_msr_high & (1u<<16))
2906 /* Require Write-Back (WB) memory type for VMCS accesses. */
2907 if (((vmx_msr_high >> 18) & 15) != 6)
2910 vmcs_conf->size = vmx_msr_high & 0x1fff;
2911 vmcs_conf->order = get_order(vmcs_config.size);
2912 vmcs_conf->revision_id = vmx_msr_low;
2914 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2916 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2917 vmcs_conf->vmexit_ctrl = _vmexit_control;
2918 vmcs_conf->vmentry_ctrl = _vmentry_control;
2920 cpu_has_load_ia32_efer =
2921 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922 VM_ENTRY_LOAD_IA32_EFER)
2923 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924 VM_EXIT_LOAD_IA32_EFER);
2926 cpu_has_load_perf_global_ctrl =
2927 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2933 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934 * but due to arrata below it can't be used. Workaround is to use
2935 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2937 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2942 * BC86,AAY89,BD102 (model 44)
2946 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947 switch (boot_cpu_data.x86_model) {
2953 cpu_has_load_perf_global_ctrl = false;
2954 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955 "does not work properly. Using workaround\n");
2965 static struct vmcs *alloc_vmcs_cpu(int cpu)
2967 int node = cpu_to_node(cpu);
2971 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2974 vmcs = page_address(pages);
2975 memset(vmcs, 0, vmcs_config.size);
2976 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2980 static struct vmcs *alloc_vmcs(void)
2982 return alloc_vmcs_cpu(raw_smp_processor_id());
2985 static void free_vmcs(struct vmcs *vmcs)
2987 free_pages((unsigned long)vmcs, vmcs_config.order);
2991 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2993 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2995 if (!loaded_vmcs->vmcs)
2997 loaded_vmcs_clear(loaded_vmcs);
2998 free_vmcs(loaded_vmcs->vmcs);
2999 loaded_vmcs->vmcs = NULL;
3002 static void free_kvm_area(void)
3006 for_each_possible_cpu(cpu) {
3007 free_vmcs(per_cpu(vmxarea, cpu));
3008 per_cpu(vmxarea, cpu) = NULL;
3012 static void init_vmcs_shadow_fields(void)
3016 /* No checks for read only fields yet */
3018 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3019 switch (shadow_read_write_fields[i]) {
3021 if (!vmx_mpx_supported())
3029 shadow_read_write_fields[j] =
3030 shadow_read_write_fields[i];
3033 max_shadow_read_write_fields = j;
3035 /* shadowed fields guest access without vmexit */
3036 for (i = 0; i < max_shadow_read_write_fields; i++) {
3037 clear_bit(shadow_read_write_fields[i],
3038 vmx_vmwrite_bitmap);
3039 clear_bit(shadow_read_write_fields[i],
3042 for (i = 0; i < max_shadow_read_only_fields; i++)
3043 clear_bit(shadow_read_only_fields[i],
3047 static __init int alloc_kvm_area(void)
3051 for_each_possible_cpu(cpu) {
3054 vmcs = alloc_vmcs_cpu(cpu);
3060 per_cpu(vmxarea, cpu) = vmcs;
3065 static __init int hardware_setup(void)
3067 if (setup_vmcs_config(&vmcs_config) < 0)
3070 if (boot_cpu_has(X86_FEATURE_NX))
3071 kvm_enable_efer_bits(EFER_NX);
3073 if (!cpu_has_vmx_vpid())
3075 if (!cpu_has_vmx_shadow_vmcs())
3076 enable_shadow_vmcs = 0;
3077 if (enable_shadow_vmcs)
3078 init_vmcs_shadow_fields();
3080 if (!cpu_has_vmx_ept() ||
3081 !cpu_has_vmx_ept_4levels()) {
3083 enable_unrestricted_guest = 0;
3084 enable_ept_ad_bits = 0;
3087 if (!cpu_has_vmx_ept_ad_bits())
3088 enable_ept_ad_bits = 0;
3090 if (!cpu_has_vmx_unrestricted_guest())
3091 enable_unrestricted_guest = 0;
3093 if (!cpu_has_vmx_flexpriority())
3094 flexpriority_enabled = 0;
3096 if (!cpu_has_vmx_tpr_shadow())
3097 kvm_x86_ops->update_cr8_intercept = NULL;
3099 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3100 kvm_disable_largepages();
3102 if (!cpu_has_vmx_ple())
3105 if (!cpu_has_vmx_apicv())
3109 kvm_x86_ops->update_cr8_intercept = NULL;
3111 kvm_x86_ops->hwapic_irr_update = NULL;
3112 kvm_x86_ops->deliver_posted_interrupt = NULL;
3113 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3117 nested_vmx_setup_ctls_msrs();
3119 return alloc_kvm_area();
3122 static __exit void hardware_unsetup(void)
3127 static bool emulation_required(struct kvm_vcpu *vcpu)
3129 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3132 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3133 struct kvm_segment *save)
3135 if (!emulate_invalid_guest_state) {
3137 * CS and SS RPL should be equal during guest entry according
3138 * to VMX spec, but in reality it is not always so. Since vcpu
3139 * is in the middle of the transition from real mode to
3140 * protected mode it is safe to assume that RPL 0 is a good
3143 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3144 save->selector &= ~SELECTOR_RPL_MASK;
3145 save->dpl = save->selector & SELECTOR_RPL_MASK;
3148 vmx_set_segment(vcpu, save, seg);
3151 static void enter_pmode(struct kvm_vcpu *vcpu)
3153 unsigned long flags;
3154 struct vcpu_vmx *vmx = to_vmx(vcpu);
3157 * Update real mode segment cache. It may be not up-to-date if sement
3158 * register was written while vcpu was in a guest mode.
3160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3161 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3162 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3163 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3164 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3165 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3167 vmx->rmode.vm86_active = 0;
3169 vmx_segment_cache_clear(vmx);
3171 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3173 flags = vmcs_readl(GUEST_RFLAGS);
3174 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3175 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3176 vmcs_writel(GUEST_RFLAGS, flags);
3178 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3179 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3181 update_exception_bitmap(vcpu);
3183 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3184 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3185 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3186 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3187 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3188 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3190 /* CPL is always 0 when CPU enters protected mode */
3191 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3195 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3197 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3198 struct kvm_segment var = *save;
3201 if (seg == VCPU_SREG_CS)
3204 if (!emulate_invalid_guest_state) {
3205 var.selector = var.base >> 4;
3206 var.base = var.base & 0xffff0;
3216 if (save->base & 0xf)
3217 printk_once(KERN_WARNING "kvm: segment base is not "
3218 "paragraph aligned when entering "
3219 "protected mode (seg=%d)", seg);
3222 vmcs_write16(sf->selector, var.selector);
3223 vmcs_write32(sf->base, var.base);
3224 vmcs_write32(sf->limit, var.limit);
3225 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3228 static void enter_rmode(struct kvm_vcpu *vcpu)
3230 unsigned long flags;
3231 struct vcpu_vmx *vmx = to_vmx(vcpu);
3233 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3234 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3235 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3236 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3237 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3238 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3239 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3241 vmx->rmode.vm86_active = 1;
3244 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3245 * vcpu. Warn the user that an update is overdue.
3247 if (!vcpu->kvm->arch.tss_addr)
3248 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3249 "called before entering vcpu\n");
3251 vmx_segment_cache_clear(vmx);
3253 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3254 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3255 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3257 flags = vmcs_readl(GUEST_RFLAGS);
3258 vmx->rmode.save_rflags = flags;
3260 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3262 vmcs_writel(GUEST_RFLAGS, flags);
3263 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3264 update_exception_bitmap(vcpu);
3266 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3267 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3268 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3269 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3270 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3271 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3273 kvm_mmu_reset_context(vcpu);
3276 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3278 struct vcpu_vmx *vmx = to_vmx(vcpu);
3279 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3285 * Force kernel_gs_base reloading before EFER changes, as control
3286 * of this msr depends on is_long_mode().
3288 vmx_load_host_state(to_vmx(vcpu));
3289 vcpu->arch.efer = efer;
3290 if (efer & EFER_LMA) {
3291 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3294 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3296 msr->data = efer & ~EFER_LME;
3301 #ifdef CONFIG_X86_64
3303 static void enter_lmode(struct kvm_vcpu *vcpu)
3307 vmx_segment_cache_clear(to_vmx(vcpu));
3309 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3310 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3311 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3313 vmcs_write32(GUEST_TR_AR_BYTES,
3314 (guest_tr_ar & ~AR_TYPE_MASK)
3315 | AR_TYPE_BUSY_64_TSS);
3317 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3320 static void exit_lmode(struct kvm_vcpu *vcpu)
3322 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3323 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3328 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3330 vpid_sync_context(to_vmx(vcpu));
3332 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3334 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3338 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3340 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3342 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3343 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3346 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3348 if (enable_ept && is_paging(vcpu))
3349 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3350 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3353 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3355 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3357 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3358 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3361 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3363 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3365 if (!test_bit(VCPU_EXREG_PDPTR,
3366 (unsigned long *)&vcpu->arch.regs_dirty))
3369 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3370 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3371 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3372 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3373 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3377 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3379 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3381 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3382 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3383 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3384 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3385 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3388 __set_bit(VCPU_EXREG_PDPTR,
3389 (unsigned long *)&vcpu->arch.regs_avail);
3390 __set_bit(VCPU_EXREG_PDPTR,
3391 (unsigned long *)&vcpu->arch.regs_dirty);
3394 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3396 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3398 struct kvm_vcpu *vcpu)
3400 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3401 vmx_decache_cr3(vcpu);
3402 if (!(cr0 & X86_CR0_PG)) {
3403 /* From paging/starting to nonpaging */
3404 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3405 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3406 (CPU_BASED_CR3_LOAD_EXITING |
3407 CPU_BASED_CR3_STORE_EXITING));
3408 vcpu->arch.cr0 = cr0;
3409 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3410 } else if (!is_paging(vcpu)) {
3411 /* From nonpaging to paging */
3412 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3413 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3414 ~(CPU_BASED_CR3_LOAD_EXITING |
3415 CPU_BASED_CR3_STORE_EXITING));
3416 vcpu->arch.cr0 = cr0;
3417 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3420 if (!(cr0 & X86_CR0_WP))
3421 *hw_cr0 &= ~X86_CR0_WP;
3424 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3426 struct vcpu_vmx *vmx = to_vmx(vcpu);
3427 unsigned long hw_cr0;
3429 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3430 if (enable_unrestricted_guest)
3431 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3433 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3435 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3438 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3442 #ifdef CONFIG_X86_64
3443 if (vcpu->arch.efer & EFER_LME) {
3444 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3446 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3452 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3454 if (!vcpu->fpu_active)
3455 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3457 vmcs_writel(CR0_READ_SHADOW, cr0);
3458 vmcs_writel(GUEST_CR0, hw_cr0);
3459 vcpu->arch.cr0 = cr0;
3461 /* depends on vcpu->arch.cr0 to be set to a new value */
3462 vmx->emulation_required = emulation_required(vcpu);
3465 static u64 construct_eptp(unsigned long root_hpa)
3469 /* TODO write the value reading from MSR */
3470 eptp = VMX_EPT_DEFAULT_MT |
3471 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3472 if (enable_ept_ad_bits)
3473 eptp |= VMX_EPT_AD_ENABLE_BIT;
3474 eptp |= (root_hpa & PAGE_MASK);
3479 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3481 unsigned long guest_cr3;
3486 eptp = construct_eptp(cr3);
3487 vmcs_write64(EPT_POINTER, eptp);
3488 if (is_paging(vcpu) || is_guest_mode(vcpu))
3489 guest_cr3 = kvm_read_cr3(vcpu);
3491 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3492 ept_load_pdptrs(vcpu);
3495 vmx_flush_tlb(vcpu);
3496 vmcs_writel(GUEST_CR3, guest_cr3);
3499 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3501 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3502 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3504 if (cr4 & X86_CR4_VMXE) {
3506 * To use VMXON (and later other VMX instructions), a guest
3507 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3508 * So basically the check on whether to allow nested VMX
3511 if (!nested_vmx_allowed(vcpu))
3514 if (to_vmx(vcpu)->nested.vmxon &&
3515 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3518 vcpu->arch.cr4 = cr4;
3520 if (!is_paging(vcpu)) {
3521 hw_cr4 &= ~X86_CR4_PAE;
3522 hw_cr4 |= X86_CR4_PSE;
3524 * SMEP/SMAP is disabled if CPU is in non-paging mode
3525 * in hardware. However KVM always uses paging mode to
3526 * emulate guest non-paging mode with TDP.
3527 * To emulate this behavior, SMEP/SMAP needs to be
3528 * manually disabled when guest switches to non-paging
3531 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3532 } else if (!(cr4 & X86_CR4_PAE)) {
3533 hw_cr4 &= ~X86_CR4_PAE;
3537 vmcs_writel(CR4_READ_SHADOW, cr4);
3538 vmcs_writel(GUEST_CR4, hw_cr4);
3542 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3543 struct kvm_segment *var, int seg)
3545 struct vcpu_vmx *vmx = to_vmx(vcpu);
3548 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3549 *var = vmx->rmode.segs[seg];
3550 if (seg == VCPU_SREG_TR
3551 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3553 var->base = vmx_read_guest_seg_base(vmx, seg);
3554 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3557 var->base = vmx_read_guest_seg_base(vmx, seg);
3558 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3559 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3560 ar = vmx_read_guest_seg_ar(vmx, seg);
3561 var->unusable = (ar >> 16) & 1;
3562 var->type = ar & 15;
3563 var->s = (ar >> 4) & 1;
3564 var->dpl = (ar >> 5) & 3;
3566 * Some userspaces do not preserve unusable property. Since usable
3567 * segment has to be present according to VMX spec we can use present
3568 * property to amend userspace bug by making unusable segment always
3569 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3570 * segment as unusable.
3572 var->present = !var->unusable;
3573 var->avl = (ar >> 12) & 1;
3574 var->l = (ar >> 13) & 1;
3575 var->db = (ar >> 14) & 1;
3576 var->g = (ar >> 15) & 1;
3579 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3581 struct kvm_segment s;
3583 if (to_vmx(vcpu)->rmode.vm86_active) {
3584 vmx_get_segment(vcpu, &s, seg);
3587 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3590 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3592 struct vcpu_vmx *vmx = to_vmx(vcpu);
3594 if (!is_protmode(vcpu))
3597 if (!is_long_mode(vcpu)
3598 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3601 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3602 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3603 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3610 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3614 if (var->unusable || !var->present)
3617 ar = var->type & 15;
3618 ar |= (var->s & 1) << 4;
3619 ar |= (var->dpl & 3) << 5;
3620 ar |= (var->present & 1) << 7;
3621 ar |= (var->avl & 1) << 12;
3622 ar |= (var->l & 1) << 13;
3623 ar |= (var->db & 1) << 14;
3624 ar |= (var->g & 1) << 15;
3630 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3631 struct kvm_segment *var, int seg)
3633 struct vcpu_vmx *vmx = to_vmx(vcpu);
3634 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3636 vmx_segment_cache_clear(vmx);
3637 if (seg == VCPU_SREG_CS)
3638 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3640 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3641 vmx->rmode.segs[seg] = *var;
3642 if (seg == VCPU_SREG_TR)
3643 vmcs_write16(sf->selector, var->selector);
3645 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3649 vmcs_writel(sf->base, var->base);
3650 vmcs_write32(sf->limit, var->limit);
3651 vmcs_write16(sf->selector, var->selector);
3654 * Fix the "Accessed" bit in AR field of segment registers for older
3656 * IA32 arch specifies that at the time of processor reset the
3657 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3658 * is setting it to 0 in the userland code. This causes invalid guest
3659 * state vmexit when "unrestricted guest" mode is turned on.
3660 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3661 * tree. Newer qemu binaries with that qemu fix would not need this
3664 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3665 var->type |= 0x1; /* Accessed */
3667 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3670 vmx->emulation_required |= emulation_required(vcpu);
3673 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3675 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3677 *db = (ar >> 14) & 1;
3678 *l = (ar >> 13) & 1;
3681 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3683 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3684 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3687 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3689 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3690 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3693 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3695 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3696 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3699 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3701 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3702 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3705 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3707 struct kvm_segment var;
3710 vmx_get_segment(vcpu, &var, seg);
3712 if (seg == VCPU_SREG_CS)
3714 ar = vmx_segment_access_rights(&var);
3716 if (var.base != (var.selector << 4))
3718 if (var.limit != 0xffff)
3726 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3728 struct kvm_segment cs;
3729 unsigned int cs_rpl;
3731 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3732 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3736 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3740 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3741 if (cs.dpl > cs_rpl)
3744 if (cs.dpl != cs_rpl)
3750 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3754 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3756 struct kvm_segment ss;
3757 unsigned int ss_rpl;
3759 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3760 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3764 if (ss.type != 3 && ss.type != 7)
3768 if (ss.dpl != ss_rpl) /* DPL != RPL */
3776 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3778 struct kvm_segment var;
3781 vmx_get_segment(vcpu, &var, seg);
3782 rpl = var.selector & SELECTOR_RPL_MASK;
3790 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3791 if (var.dpl < rpl) /* DPL < RPL */
3795 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3801 static bool tr_valid(struct kvm_vcpu *vcpu)
3803 struct kvm_segment tr;
3805 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3809 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3811 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3819 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3821 struct kvm_segment ldtr;
3823 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3827 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3837 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3839 struct kvm_segment cs, ss;
3841 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3842 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3844 return ((cs.selector & SELECTOR_RPL_MASK) ==
3845 (ss.selector & SELECTOR_RPL_MASK));
3849 * Check if guest state is valid. Returns true if valid, false if
3851 * We assume that registers are always usable
3853 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3855 if (enable_unrestricted_guest)
3858 /* real mode guest state checks */
3859 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3860 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3862 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3864 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3866 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3868 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3870 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3873 /* protected mode guest state checks */
3874 if (!cs_ss_rpl_check(vcpu))
3876 if (!code_segment_valid(vcpu))
3878 if (!stack_segment_valid(vcpu))
3880 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3882 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3884 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3886 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3888 if (!tr_valid(vcpu))
3890 if (!ldtr_valid(vcpu))
3894 * - Add checks on RIP
3895 * - Add checks on RFLAGS
3901 static int init_rmode_tss(struct kvm *kvm)
3905 int r, idx, ret = 0;
3907 idx = srcu_read_lock(&kvm->srcu);
3908 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3909 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3912 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3913 r = kvm_write_guest_page(kvm, fn++, &data,
3914 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3917 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3920 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3924 r = kvm_write_guest_page(kvm, fn, &data,
3925 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3932 srcu_read_unlock(&kvm->srcu, idx);
3936 static int init_rmode_identity_map(struct kvm *kvm)
3939 pfn_t identity_map_pfn;
3944 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3945 printk(KERN_ERR "EPT: identity-mapping pagetable "
3946 "haven't been allocated!\n");
3949 if (likely(kvm->arch.ept_identity_pagetable_done))
3952 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3953 idx = srcu_read_lock(&kvm->srcu);
3954 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3957 /* Set up identity-mapping pagetable for EPT in real mode */
3958 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3959 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3960 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3961 r = kvm_write_guest_page(kvm, identity_map_pfn,
3962 &tmp, i * sizeof(tmp), sizeof(tmp));
3966 kvm->arch.ept_identity_pagetable_done = true;
3969 srcu_read_unlock(&kvm->srcu, idx);
3973 static void seg_setup(int seg)
3975 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3978 vmcs_write16(sf->selector, 0);
3979 vmcs_writel(sf->base, 0);
3980 vmcs_write32(sf->limit, 0xffff);
3982 if (seg == VCPU_SREG_CS)
3983 ar |= 0x08; /* code segment */
3985 vmcs_write32(sf->ar_bytes, ar);
3988 static int alloc_apic_access_page(struct kvm *kvm)
3991 struct kvm_userspace_memory_region kvm_userspace_mem;
3994 mutex_lock(&kvm->slots_lock);
3995 if (kvm->arch.apic_access_page)
3997 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3998 kvm_userspace_mem.flags = 0;
3999 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4000 kvm_userspace_mem.memory_size = PAGE_SIZE;
4001 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4005 page = gfn_to_page(kvm, 0xfee00);
4006 if (is_error_page(page)) {
4011 kvm->arch.apic_access_page = page;
4013 mutex_unlock(&kvm->slots_lock);
4017 static int alloc_identity_pagetable(struct kvm *kvm)
4020 struct kvm_userspace_memory_region kvm_userspace_mem;
4023 mutex_lock(&kvm->slots_lock);
4024 if (kvm->arch.ept_identity_pagetable)
4026 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4027 kvm_userspace_mem.flags = 0;
4028 kvm_userspace_mem.guest_phys_addr =
4029 kvm->arch.ept_identity_map_addr;
4030 kvm_userspace_mem.memory_size = PAGE_SIZE;
4031 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4035 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4036 if (is_error_page(page)) {
4041 kvm->arch.ept_identity_pagetable = page;
4043 mutex_unlock(&kvm->slots_lock);
4047 static void allocate_vpid(struct vcpu_vmx *vmx)
4054 spin_lock(&vmx_vpid_lock);
4055 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4056 if (vpid < VMX_NR_VPIDS) {
4058 __set_bit(vpid, vmx_vpid_bitmap);
4060 spin_unlock(&vmx_vpid_lock);
4063 static void free_vpid(struct vcpu_vmx *vmx)
4067 spin_lock(&vmx_vpid_lock);
4069 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4070 spin_unlock(&vmx_vpid_lock);
4073 #define MSR_TYPE_R 1
4074 #define MSR_TYPE_W 2
4075 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4078 int f = sizeof(unsigned long);
4080 if (!cpu_has_vmx_msr_bitmap())
4084 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4085 * have the write-low and read-high bitmap offsets the wrong way round.
4086 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4088 if (msr <= 0x1fff) {
4089 if (type & MSR_TYPE_R)
4091 __clear_bit(msr, msr_bitmap + 0x000 / f);
4093 if (type & MSR_TYPE_W)
4095 __clear_bit(msr, msr_bitmap + 0x800 / f);
4097 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4099 if (type & MSR_TYPE_R)
4101 __clear_bit(msr, msr_bitmap + 0x400 / f);
4103 if (type & MSR_TYPE_W)
4105 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4110 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4113 int f = sizeof(unsigned long);
4115 if (!cpu_has_vmx_msr_bitmap())
4119 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4120 * have the write-low and read-high bitmap offsets the wrong way round.
4121 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4123 if (msr <= 0x1fff) {
4124 if (type & MSR_TYPE_R)
4126 __set_bit(msr, msr_bitmap + 0x000 / f);
4128 if (type & MSR_TYPE_W)
4130 __set_bit(msr, msr_bitmap + 0x800 / f);
4132 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4134 if (type & MSR_TYPE_R)
4136 __set_bit(msr, msr_bitmap + 0x400 / f);
4138 if (type & MSR_TYPE_W)
4140 __set_bit(msr, msr_bitmap + 0xc00 / f);
4145 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4148 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4149 msr, MSR_TYPE_R | MSR_TYPE_W);
4150 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4151 msr, MSR_TYPE_R | MSR_TYPE_W);
4154 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4156 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4158 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4162 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4164 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4166 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4170 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4172 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4174 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4178 static int vmx_vm_has_apicv(struct kvm *kvm)
4180 return enable_apicv && irqchip_in_kernel(kvm);
4184 * Send interrupt to vcpu via posted interrupt way.
4185 * 1. If target vcpu is running(non-root mode), send posted interrupt
4186 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4187 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4188 * interrupt from PIR in next vmentry.
4190 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4192 struct vcpu_vmx *vmx = to_vmx(vcpu);
4195 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4198 r = pi_test_and_set_on(&vmx->pi_desc);
4199 kvm_make_request(KVM_REQ_EVENT, vcpu);
4201 if (!r && (vcpu->mode == IN_GUEST_MODE))
4202 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4203 POSTED_INTR_VECTOR);
4206 kvm_vcpu_kick(vcpu);
4209 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4211 struct vcpu_vmx *vmx = to_vmx(vcpu);
4213 if (!pi_test_and_clear_on(&vmx->pi_desc))
4216 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4219 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4225 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4226 * will not change in the lifetime of the guest.
4227 * Note that host-state that does change is set elsewhere. E.g., host-state
4228 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4230 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4236 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4237 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4238 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4240 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4241 #ifdef CONFIG_X86_64
4243 * Load null selectors, so we can avoid reloading them in
4244 * __vmx_load_host_state(), in case userspace uses the null selectors
4245 * too (the expected case).
4247 vmcs_write16(HOST_DS_SELECTOR, 0);
4248 vmcs_write16(HOST_ES_SELECTOR, 0);
4250 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4251 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4253 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4254 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4256 native_store_idt(&dt);
4257 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4258 vmx->host_idt_base = dt.address;
4260 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4262 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4263 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4264 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4265 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4267 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4268 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4269 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4273 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4275 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4277 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4278 if (is_guest_mode(&vmx->vcpu))
4279 vmx->vcpu.arch.cr4_guest_owned_bits &=
4280 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4281 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4284 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4286 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4288 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4289 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4290 return pin_based_exec_ctrl;
4293 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4295 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4297 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4298 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4300 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4301 exec_control &= ~CPU_BASED_TPR_SHADOW;
4302 #ifdef CONFIG_X86_64
4303 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4304 CPU_BASED_CR8_LOAD_EXITING;
4308 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4309 CPU_BASED_CR3_LOAD_EXITING |
4310 CPU_BASED_INVLPG_EXITING;
4311 return exec_control;
4314 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4316 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4317 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4318 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4320 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4322 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4323 enable_unrestricted_guest = 0;
4324 /* Enable INVPCID for non-ept guests may cause performance regression. */
4325 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4327 if (!enable_unrestricted_guest)
4328 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4330 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4331 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4332 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4333 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4334 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4335 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4337 We can NOT enable shadow_vmcs here because we don't have yet
4340 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4341 return exec_control;
4344 static void ept_set_mmio_spte_mask(void)
4347 * EPT Misconfigurations can be generated if the value of bits 2:0
4348 * of an EPT paging-structure entry is 110b (write/execute).
4349 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4352 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4356 * Sets up the vmcs for emulated real mode.
4358 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4360 #ifdef CONFIG_X86_64
4366 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4367 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4369 if (enable_shadow_vmcs) {
4370 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4371 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4373 if (cpu_has_vmx_msr_bitmap())
4374 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4376 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4379 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4381 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4383 if (cpu_has_secondary_exec_ctrls()) {
4384 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4385 vmx_secondary_exec_control(vmx));
4388 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4389 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4390 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4391 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4392 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4394 vmcs_write16(GUEST_INTR_STATUS, 0);
4396 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4397 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4401 vmcs_write32(PLE_GAP, ple_gap);
4402 vmcs_write32(PLE_WINDOW, ple_window);
4405 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4406 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4407 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4409 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4410 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4411 vmx_set_constant_host_state(vmx);
4412 #ifdef CONFIG_X86_64
4413 rdmsrl(MSR_FS_BASE, a);
4414 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4415 rdmsrl(MSR_GS_BASE, a);
4416 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4418 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4419 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4422 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4423 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4424 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4425 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4426 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4428 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4429 u32 msr_low, msr_high;
4431 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4432 host_pat = msr_low | ((u64) msr_high << 32);
4433 /* Write the default value follow host pat */
4434 vmcs_write64(GUEST_IA32_PAT, host_pat);
4435 /* Keep arch.pat sync with GUEST_IA32_PAT */
4436 vmx->vcpu.arch.pat = host_pat;
4439 for (i = 0; i < NR_VMX_MSR; ++i) {
4440 u32 index = vmx_msr_index[i];
4441 u32 data_low, data_high;
4444 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4446 if (wrmsr_safe(index, data_low, data_high) < 0)
4448 vmx->guest_msrs[j].index = i;
4449 vmx->guest_msrs[j].data = 0;
4450 vmx->guest_msrs[j].mask = -1ull;
4455 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4457 /* 22.2.1, 20.8.1 */
4458 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4460 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4461 set_cr4_guest_host_mask(vmx);
4466 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4468 struct vcpu_vmx *vmx = to_vmx(vcpu);
4469 struct msr_data apic_base_msr;
4471 vmx->rmode.vm86_active = 0;
4473 vmx->soft_vnmi_blocked = 0;
4475 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4476 kvm_set_cr8(&vmx->vcpu, 0);
4477 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4478 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4479 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4480 apic_base_msr.host_initiated = true;
4481 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4483 vmx_segment_cache_clear(vmx);
4485 seg_setup(VCPU_SREG_CS);
4486 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4487 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4489 seg_setup(VCPU_SREG_DS);
4490 seg_setup(VCPU_SREG_ES);
4491 seg_setup(VCPU_SREG_FS);
4492 seg_setup(VCPU_SREG_GS);
4493 seg_setup(VCPU_SREG_SS);
4495 vmcs_write16(GUEST_TR_SELECTOR, 0);
4496 vmcs_writel(GUEST_TR_BASE, 0);
4497 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4498 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4500 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4501 vmcs_writel(GUEST_LDTR_BASE, 0);
4502 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4503 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4505 vmcs_write32(GUEST_SYSENTER_CS, 0);
4506 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4507 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4509 vmcs_writel(GUEST_RFLAGS, 0x02);
4510 kvm_rip_write(vcpu, 0xfff0);
4512 vmcs_writel(GUEST_GDTR_BASE, 0);
4513 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4515 vmcs_writel(GUEST_IDTR_BASE, 0);
4516 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4518 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4519 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4520 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4522 /* Special registers */
4523 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4527 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4529 if (cpu_has_vmx_tpr_shadow()) {
4530 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4531 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4532 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4533 __pa(vmx->vcpu.arch.apic->regs));
4534 vmcs_write32(TPR_THRESHOLD, 0);
4537 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4538 vmcs_write64(APIC_ACCESS_ADDR,
4539 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4541 if (vmx_vm_has_apicv(vcpu->kvm))
4542 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4545 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4547 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4548 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4549 vmx_set_cr4(&vmx->vcpu, 0);
4550 vmx_set_efer(&vmx->vcpu, 0);
4551 vmx_fpu_activate(&vmx->vcpu);
4552 update_exception_bitmap(&vmx->vcpu);
4554 vpid_sync_context(vmx);
4558 * In nested virtualization, check if L1 asked to exit on external interrupts.
4559 * For most existing hypervisors, this will always return true.
4561 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4563 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4564 PIN_BASED_EXT_INTR_MASK;
4567 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4569 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4570 PIN_BASED_NMI_EXITING;
4573 static void enable_irq_window(struct kvm_vcpu *vcpu)
4575 u32 cpu_based_vm_exec_control;
4577 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4578 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4579 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4582 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4584 u32 cpu_based_vm_exec_control;
4586 if (!cpu_has_virtual_nmis() ||
4587 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4588 enable_irq_window(vcpu);
4592 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4593 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4594 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4597 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4599 struct vcpu_vmx *vmx = to_vmx(vcpu);
4601 int irq = vcpu->arch.interrupt.nr;
4603 trace_kvm_inj_virq(irq);
4605 ++vcpu->stat.irq_injections;
4606 if (vmx->rmode.vm86_active) {
4608 if (vcpu->arch.interrupt.soft)
4609 inc_eip = vcpu->arch.event_exit_inst_len;
4610 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4611 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4614 intr = irq | INTR_INFO_VALID_MASK;
4615 if (vcpu->arch.interrupt.soft) {
4616 intr |= INTR_TYPE_SOFT_INTR;
4617 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4618 vmx->vcpu.arch.event_exit_inst_len);
4620 intr |= INTR_TYPE_EXT_INTR;
4621 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4624 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4626 struct vcpu_vmx *vmx = to_vmx(vcpu);
4628 if (is_guest_mode(vcpu))
4631 if (!cpu_has_virtual_nmis()) {
4633 * Tracking the NMI-blocked state in software is built upon
4634 * finding the next open IRQ window. This, in turn, depends on
4635 * well-behaving guests: They have to keep IRQs disabled at
4636 * least as long as the NMI handler runs. Otherwise we may
4637 * cause NMI nesting, maybe breaking the guest. But as this is
4638 * highly unlikely, we can live with the residual risk.
4640 vmx->soft_vnmi_blocked = 1;
4641 vmx->vnmi_blocked_time = 0;
4644 ++vcpu->stat.nmi_injections;
4645 vmx->nmi_known_unmasked = false;
4646 if (vmx->rmode.vm86_active) {
4647 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4648 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4651 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4652 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4655 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4657 if (!cpu_has_virtual_nmis())
4658 return to_vmx(vcpu)->soft_vnmi_blocked;
4659 if (to_vmx(vcpu)->nmi_known_unmasked)
4661 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4664 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4666 struct vcpu_vmx *vmx = to_vmx(vcpu);
4668 if (!cpu_has_virtual_nmis()) {
4669 if (vmx->soft_vnmi_blocked != masked) {
4670 vmx->soft_vnmi_blocked = masked;
4671 vmx->vnmi_blocked_time = 0;
4674 vmx->nmi_known_unmasked = !masked;
4676 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4677 GUEST_INTR_STATE_NMI);
4679 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4680 GUEST_INTR_STATE_NMI);
4684 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4686 if (to_vmx(vcpu)->nested.nested_run_pending)
4689 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4692 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4693 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4694 | GUEST_INTR_STATE_NMI));
4697 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4699 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4700 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4701 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4702 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4705 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4708 struct kvm_userspace_memory_region tss_mem = {
4709 .slot = TSS_PRIVATE_MEMSLOT,
4710 .guest_phys_addr = addr,
4711 .memory_size = PAGE_SIZE * 3,
4715 ret = kvm_set_memory_region(kvm, &tss_mem);
4718 kvm->arch.tss_addr = addr;
4719 if (!init_rmode_tss(kvm))
4725 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4730 * Update instruction length as we may reinject the exception
4731 * from user space while in guest debugging mode.
4733 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4734 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4735 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4739 if (vcpu->guest_debug &
4740 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4757 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4758 int vec, u32 err_code)
4761 * Instruction with address size override prefix opcode 0x67
4762 * Cause the #SS fault with 0 error code in VM86 mode.
4764 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4765 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4766 if (vcpu->arch.halt_request) {
4767 vcpu->arch.halt_request = 0;
4768 return kvm_emulate_halt(vcpu);
4776 * Forward all other exceptions that are valid in real mode.
4777 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4778 * the required debugging infrastructure rework.
4780 kvm_queue_exception(vcpu, vec);
4785 * Trigger machine check on the host. We assume all the MSRs are already set up
4786 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4787 * We pass a fake environment to the machine check handler because we want
4788 * the guest to be always treated like user space, no matter what context
4789 * it used internally.
4791 static void kvm_machine_check(void)
4793 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4794 struct pt_regs regs = {
4795 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4796 .flags = X86_EFLAGS_IF,
4799 do_machine_check(®s, 0);
4803 static int handle_machine_check(struct kvm_vcpu *vcpu)
4805 /* already handled by vcpu_run */
4809 static int handle_exception(struct kvm_vcpu *vcpu)
4811 struct vcpu_vmx *vmx = to_vmx(vcpu);
4812 struct kvm_run *kvm_run = vcpu->run;
4813 u32 intr_info, ex_no, error_code;
4814 unsigned long cr2, rip, dr6;
4816 enum emulation_result er;
4818 vect_info = vmx->idt_vectoring_info;
4819 intr_info = vmx->exit_intr_info;
4821 if (is_machine_check(intr_info))
4822 return handle_machine_check(vcpu);
4824 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4825 return 1; /* already handled by vmx_vcpu_run() */
4827 if (is_no_device(intr_info)) {
4828 vmx_fpu_activate(vcpu);
4832 if (is_invalid_opcode(intr_info)) {
4833 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4834 if (er != EMULATE_DONE)
4835 kvm_queue_exception(vcpu, UD_VECTOR);
4840 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4841 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4844 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4845 * MMIO, it is better to report an internal error.
4846 * See the comments in vmx_handle_exit.
4848 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4849 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4850 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4851 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4852 vcpu->run->internal.ndata = 2;
4853 vcpu->run->internal.data[0] = vect_info;
4854 vcpu->run->internal.data[1] = intr_info;
4858 if (is_page_fault(intr_info)) {
4859 /* EPT won't cause page fault directly */
4861 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4862 trace_kvm_page_fault(cr2, error_code);
4864 if (kvm_event_needs_reinjection(vcpu))
4865 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4866 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4869 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4871 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4872 return handle_rmode_exception(vcpu, ex_no, error_code);
4876 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4877 if (!(vcpu->guest_debug &
4878 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4879 vcpu->arch.dr6 &= ~15;
4880 vcpu->arch.dr6 |= dr6;
4881 kvm_queue_exception(vcpu, DB_VECTOR);
4884 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4885 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4889 * Update instruction length as we may reinject #BP from
4890 * user space while in guest debugging mode. Reading it for
4891 * #DB as well causes no harm, it is not used in that case.
4893 vmx->vcpu.arch.event_exit_inst_len =
4894 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4895 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4896 rip = kvm_rip_read(vcpu);
4897 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4898 kvm_run->debug.arch.exception = ex_no;
4901 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4902 kvm_run->ex.exception = ex_no;
4903 kvm_run->ex.error_code = error_code;
4909 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4911 ++vcpu->stat.irq_exits;
4915 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4917 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4921 static int handle_io(struct kvm_vcpu *vcpu)
4923 unsigned long exit_qualification;
4924 int size, in, string;
4927 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4928 string = (exit_qualification & 16) != 0;
4929 in = (exit_qualification & 8) != 0;
4931 ++vcpu->stat.io_exits;
4934 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4936 port = exit_qualification >> 16;
4937 size = (exit_qualification & 7) + 1;
4938 skip_emulated_instruction(vcpu);
4940 return kvm_fast_pio_out(vcpu, size, port);
4944 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4947 * Patch in the VMCALL instruction:
4949 hypercall[0] = 0x0f;
4950 hypercall[1] = 0x01;
4951 hypercall[2] = 0xc1;
4954 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4956 unsigned long always_on = VMXON_CR0_ALWAYSON;
4958 if (nested_vmx_secondary_ctls_high &
4959 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4960 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4961 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4962 return (val & always_on) == always_on;
4965 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4966 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4968 if (is_guest_mode(vcpu)) {
4969 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4970 unsigned long orig_val = val;
4973 * We get here when L2 changed cr0 in a way that did not change
4974 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4975 * but did change L0 shadowed bits. So we first calculate the
4976 * effective cr0 value that L1 would like to write into the
4977 * hardware. It consists of the L2-owned bits from the new
4978 * value combined with the L1-owned bits from L1's guest_cr0.
4980 val = (val & ~vmcs12->cr0_guest_host_mask) |
4981 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4983 if (!nested_cr0_valid(vmcs12, val))
4986 if (kvm_set_cr0(vcpu, val))
4988 vmcs_writel(CR0_READ_SHADOW, orig_val);
4991 if (to_vmx(vcpu)->nested.vmxon &&
4992 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4994 return kvm_set_cr0(vcpu, val);
4998 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5000 if (is_guest_mode(vcpu)) {
5001 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5002 unsigned long orig_val = val;
5004 /* analogously to handle_set_cr0 */
5005 val = (val & ~vmcs12->cr4_guest_host_mask) |
5006 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5007 if (kvm_set_cr4(vcpu, val))
5009 vmcs_writel(CR4_READ_SHADOW, orig_val);
5012 return kvm_set_cr4(vcpu, val);
5015 /* called to set cr0 as approriate for clts instruction exit. */
5016 static void handle_clts(struct kvm_vcpu *vcpu)
5018 if (is_guest_mode(vcpu)) {
5020 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5021 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5022 * just pretend it's off (also in arch.cr0 for fpu_activate).
5024 vmcs_writel(CR0_READ_SHADOW,
5025 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5026 vcpu->arch.cr0 &= ~X86_CR0_TS;
5028 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5031 static int handle_cr(struct kvm_vcpu *vcpu)
5033 unsigned long exit_qualification, val;
5038 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5039 cr = exit_qualification & 15;
5040 reg = (exit_qualification >> 8) & 15;
5041 switch ((exit_qualification >> 4) & 3) {
5042 case 0: /* mov to cr */
5043 val = kvm_register_read(vcpu, reg);
5044 trace_kvm_cr_write(cr, val);
5047 err = handle_set_cr0(vcpu, val);
5048 kvm_complete_insn_gp(vcpu, err);
5051 err = kvm_set_cr3(vcpu, val);
5052 kvm_complete_insn_gp(vcpu, err);
5055 err = handle_set_cr4(vcpu, val);
5056 kvm_complete_insn_gp(vcpu, err);
5059 u8 cr8_prev = kvm_get_cr8(vcpu);
5060 u8 cr8 = kvm_register_read(vcpu, reg);
5061 err = kvm_set_cr8(vcpu, cr8);
5062 kvm_complete_insn_gp(vcpu, err);
5063 if (irqchip_in_kernel(vcpu->kvm))
5065 if (cr8_prev <= cr8)
5067 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5074 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5075 skip_emulated_instruction(vcpu);
5076 vmx_fpu_activate(vcpu);
5078 case 1: /*mov from cr*/
5081 val = kvm_read_cr3(vcpu);
5082 kvm_register_write(vcpu, reg, val);
5083 trace_kvm_cr_read(cr, val);
5084 skip_emulated_instruction(vcpu);
5087 val = kvm_get_cr8(vcpu);
5088 kvm_register_write(vcpu, reg, val);
5089 trace_kvm_cr_read(cr, val);
5090 skip_emulated_instruction(vcpu);
5095 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5096 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5097 kvm_lmsw(vcpu, val);
5099 skip_emulated_instruction(vcpu);
5104 vcpu->run->exit_reason = 0;
5105 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5106 (int)(exit_qualification >> 4) & 3, cr);
5110 static int handle_dr(struct kvm_vcpu *vcpu)
5112 unsigned long exit_qualification;
5115 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5116 if (!kvm_require_cpl(vcpu, 0))
5118 dr = vmcs_readl(GUEST_DR7);
5121 * As the vm-exit takes precedence over the debug trap, we
5122 * need to emulate the latter, either for the host or the
5123 * guest debugging itself.
5125 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5126 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5127 vcpu->run->debug.arch.dr7 = dr;
5128 vcpu->run->debug.arch.pc =
5129 vmcs_readl(GUEST_CS_BASE) +
5130 vmcs_readl(GUEST_RIP);
5131 vcpu->run->debug.arch.exception = DB_VECTOR;
5132 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5135 vcpu->arch.dr7 &= ~DR7_GD;
5136 vcpu->arch.dr6 |= DR6_BD;
5137 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5138 kvm_queue_exception(vcpu, DB_VECTOR);
5143 if (vcpu->guest_debug == 0) {
5144 u32 cpu_based_vm_exec_control;
5146 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5147 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5148 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5151 * No more DR vmexits; force a reload of the debug registers
5152 * and reenter on this instruction. The next vmexit will
5153 * retrieve the full state of the debug registers.
5155 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5159 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5160 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5161 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5162 if (exit_qualification & TYPE_MOV_FROM_DR) {
5165 if (kvm_get_dr(vcpu, dr, &val))
5167 kvm_register_write(vcpu, reg, val);
5169 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5172 skip_emulated_instruction(vcpu);
5176 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5178 return vcpu->arch.dr6;
5181 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5185 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5187 u32 cpu_based_vm_exec_control;
5189 get_debugreg(vcpu->arch.db[0], 0);
5190 get_debugreg(vcpu->arch.db[1], 1);
5191 get_debugreg(vcpu->arch.db[2], 2);
5192 get_debugreg(vcpu->arch.db[3], 3);
5193 get_debugreg(vcpu->arch.dr6, 6);
5194 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5196 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5198 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5199 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5200 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5203 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5205 vmcs_writel(GUEST_DR7, val);
5208 static int handle_cpuid(struct kvm_vcpu *vcpu)
5210 kvm_emulate_cpuid(vcpu);
5214 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5216 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5219 if (vmx_get_msr(vcpu, ecx, &data)) {
5220 trace_kvm_msr_read_ex(ecx);
5221 kvm_inject_gp(vcpu, 0);
5225 trace_kvm_msr_read(ecx, data);
5227 /* FIXME: handling of bits 32:63 of rax, rdx */
5228 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5229 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5230 skip_emulated_instruction(vcpu);
5234 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5236 struct msr_data msr;
5237 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5238 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5239 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5243 msr.host_initiated = false;
5244 if (vmx_set_msr(vcpu, &msr) != 0) {
5245 trace_kvm_msr_write_ex(ecx, data);
5246 kvm_inject_gp(vcpu, 0);
5250 trace_kvm_msr_write(ecx, data);
5251 skip_emulated_instruction(vcpu);
5255 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5257 kvm_make_request(KVM_REQ_EVENT, vcpu);
5261 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5263 u32 cpu_based_vm_exec_control;
5265 /* clear pending irq */
5266 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5267 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5268 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5270 kvm_make_request(KVM_REQ_EVENT, vcpu);
5272 ++vcpu->stat.irq_window_exits;
5275 * If the user space waits to inject interrupts, exit as soon as
5278 if (!irqchip_in_kernel(vcpu->kvm) &&
5279 vcpu->run->request_interrupt_window &&
5280 !kvm_cpu_has_interrupt(vcpu)) {
5281 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5287 static int handle_halt(struct kvm_vcpu *vcpu)
5289 skip_emulated_instruction(vcpu);
5290 return kvm_emulate_halt(vcpu);
5293 static int handle_vmcall(struct kvm_vcpu *vcpu)
5295 skip_emulated_instruction(vcpu);
5296 kvm_emulate_hypercall(vcpu);
5300 static int handle_invd(struct kvm_vcpu *vcpu)
5302 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5305 static int handle_invlpg(struct kvm_vcpu *vcpu)
5307 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5309 kvm_mmu_invlpg(vcpu, exit_qualification);
5310 skip_emulated_instruction(vcpu);
5314 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5318 err = kvm_rdpmc(vcpu);
5319 kvm_complete_insn_gp(vcpu, err);
5324 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5326 skip_emulated_instruction(vcpu);
5327 kvm_emulate_wbinvd(vcpu);
5331 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5333 u64 new_bv = kvm_read_edx_eax(vcpu);
5334 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5336 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5337 skip_emulated_instruction(vcpu);
5341 static int handle_apic_access(struct kvm_vcpu *vcpu)
5343 if (likely(fasteoi)) {
5344 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5345 int access_type, offset;
5347 access_type = exit_qualification & APIC_ACCESS_TYPE;
5348 offset = exit_qualification & APIC_ACCESS_OFFSET;
5350 * Sane guest uses MOV to write EOI, with written value
5351 * not cared. So make a short-circuit here by avoiding
5352 * heavy instruction emulation.
5354 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5355 (offset == APIC_EOI)) {
5356 kvm_lapic_set_eoi(vcpu);
5357 skip_emulated_instruction(vcpu);
5361 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5364 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5366 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5367 int vector = exit_qualification & 0xff;
5369 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5370 kvm_apic_set_eoi_accelerated(vcpu, vector);
5374 static int handle_apic_write(struct kvm_vcpu *vcpu)
5376 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5377 u32 offset = exit_qualification & 0xfff;
5379 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5380 kvm_apic_write_nodecode(vcpu, offset);
5384 static int handle_task_switch(struct kvm_vcpu *vcpu)
5386 struct vcpu_vmx *vmx = to_vmx(vcpu);
5387 unsigned long exit_qualification;
5388 bool has_error_code = false;
5391 int reason, type, idt_v, idt_index;
5393 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5394 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5395 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5397 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5399 reason = (u32)exit_qualification >> 30;
5400 if (reason == TASK_SWITCH_GATE && idt_v) {
5402 case INTR_TYPE_NMI_INTR:
5403 vcpu->arch.nmi_injected = false;
5404 vmx_set_nmi_mask(vcpu, true);
5406 case INTR_TYPE_EXT_INTR:
5407 case INTR_TYPE_SOFT_INTR:
5408 kvm_clear_interrupt_queue(vcpu);
5410 case INTR_TYPE_HARD_EXCEPTION:
5411 if (vmx->idt_vectoring_info &
5412 VECTORING_INFO_DELIVER_CODE_MASK) {
5413 has_error_code = true;
5415 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5418 case INTR_TYPE_SOFT_EXCEPTION:
5419 kvm_clear_exception_queue(vcpu);
5425 tss_selector = exit_qualification;
5427 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5428 type != INTR_TYPE_EXT_INTR &&
5429 type != INTR_TYPE_NMI_INTR))
5430 skip_emulated_instruction(vcpu);
5432 if (kvm_task_switch(vcpu, tss_selector,
5433 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5434 has_error_code, error_code) == EMULATE_FAIL) {
5435 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5436 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5437 vcpu->run->internal.ndata = 0;
5441 /* clear all local breakpoint enable flags */
5442 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5445 * TODO: What about debug traps on tss switch?
5446 * Are we supposed to inject them and update dr6?
5452 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5454 unsigned long exit_qualification;
5459 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5461 gla_validity = (exit_qualification >> 7) & 0x3;
5462 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5463 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5464 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5465 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5466 vmcs_readl(GUEST_LINEAR_ADDRESS));
5467 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5468 (long unsigned int)exit_qualification);
5469 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5470 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5475 * EPT violation happened while executing iret from NMI,
5476 * "blocked by NMI" bit has to be set before next VM entry.
5477 * There are errata that may cause this bit to not be set:
5480 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5481 cpu_has_virtual_nmis() &&
5482 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5483 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5485 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5486 trace_kvm_page_fault(gpa, exit_qualification);
5488 /* It is a write fault? */
5489 error_code = exit_qualification & (1U << 1);
5490 /* It is a fetch fault? */
5491 error_code |= (exit_qualification & (1U << 2)) << 2;
5492 /* ept page table is present? */
5493 error_code |= (exit_qualification >> 3) & 0x1;
5495 vcpu->arch.exit_qualification = exit_qualification;
5497 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5500 static u64 ept_rsvd_mask(u64 spte, int level)
5505 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5506 mask |= (1ULL << i);
5509 /* bits 7:3 reserved */
5511 else if (level == 2) {
5512 if (spte & (1ULL << 7))
5513 /* 2MB ref, bits 20:12 reserved */
5516 /* bits 6:3 reserved */
5523 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5526 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5528 /* 010b (write-only) */
5529 WARN_ON((spte & 0x7) == 0x2);
5531 /* 110b (write/execute) */
5532 WARN_ON((spte & 0x7) == 0x6);
5534 /* 100b (execute-only) and value not supported by logical processor */
5535 if (!cpu_has_vmx_ept_execute_only())
5536 WARN_ON((spte & 0x7) == 0x4);
5540 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5542 if (rsvd_bits != 0) {
5543 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5544 __func__, rsvd_bits);
5548 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5549 u64 ept_mem_type = (spte & 0x38) >> 3;
5551 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5552 ept_mem_type == 7) {
5553 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5554 __func__, ept_mem_type);
5561 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5564 int nr_sptes, i, ret;
5567 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5569 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5570 if (likely(ret == RET_MMIO_PF_EMULATE))
5571 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5574 if (unlikely(ret == RET_MMIO_PF_INVALID))
5575 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5577 if (unlikely(ret == RET_MMIO_PF_RETRY))
5580 /* It is the real ept misconfig */
5581 printk(KERN_ERR "EPT: Misconfiguration.\n");
5582 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5584 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5586 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5587 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5589 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5590 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5595 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5597 u32 cpu_based_vm_exec_control;
5599 /* clear pending NMI */
5600 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5601 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5602 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5603 ++vcpu->stat.nmi_window_exits;
5604 kvm_make_request(KVM_REQ_EVENT, vcpu);
5609 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5611 struct vcpu_vmx *vmx = to_vmx(vcpu);
5612 enum emulation_result err = EMULATE_DONE;
5615 bool intr_window_requested;
5616 unsigned count = 130;
5618 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5619 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5621 while (!guest_state_valid(vcpu) && count-- != 0) {
5622 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5623 return handle_interrupt_window(&vmx->vcpu);
5625 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5628 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5630 if (err == EMULATE_USER_EXIT) {
5631 ++vcpu->stat.mmio_exits;
5636 if (err != EMULATE_DONE) {
5637 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5638 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5639 vcpu->run->internal.ndata = 0;
5643 if (vcpu->arch.halt_request) {
5644 vcpu->arch.halt_request = 0;
5645 ret = kvm_emulate_halt(vcpu);
5649 if (signal_pending(current))
5655 vmx->emulation_required = emulation_required(vcpu);
5661 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5662 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5664 static int handle_pause(struct kvm_vcpu *vcpu)
5666 skip_emulated_instruction(vcpu);
5667 kvm_vcpu_on_spin(vcpu);
5672 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5674 kvm_queue_exception(vcpu, UD_VECTOR);
5679 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5680 * We could reuse a single VMCS for all the L2 guests, but we also want the
5681 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5682 * allows keeping them loaded on the processor, and in the future will allow
5683 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5684 * every entry if they never change.
5685 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5686 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5688 * The following functions allocate and free a vmcs02 in this pool.
5691 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5692 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5694 struct vmcs02_list *item;
5695 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5696 if (item->vmptr == vmx->nested.current_vmptr) {
5697 list_move(&item->list, &vmx->nested.vmcs02_pool);
5698 return &item->vmcs02;
5701 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5702 /* Recycle the least recently used VMCS. */
5703 item = list_entry(vmx->nested.vmcs02_pool.prev,
5704 struct vmcs02_list, list);
5705 item->vmptr = vmx->nested.current_vmptr;
5706 list_move(&item->list, &vmx->nested.vmcs02_pool);
5707 return &item->vmcs02;
5710 /* Create a new VMCS */
5711 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5714 item->vmcs02.vmcs = alloc_vmcs();
5715 if (!item->vmcs02.vmcs) {
5719 loaded_vmcs_init(&item->vmcs02);
5720 item->vmptr = vmx->nested.current_vmptr;
5721 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5722 vmx->nested.vmcs02_num++;
5723 return &item->vmcs02;
5726 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5727 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5729 struct vmcs02_list *item;
5730 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5731 if (item->vmptr == vmptr) {
5732 free_loaded_vmcs(&item->vmcs02);
5733 list_del(&item->list);
5735 vmx->nested.vmcs02_num--;
5741 * Free all VMCSs saved for this vcpu, except the one pointed by
5742 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5743 * currently used, if running L2), and vmcs01 when running L2.
5745 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5747 struct vmcs02_list *item, *n;
5748 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5749 if (vmx->loaded_vmcs != &item->vmcs02)
5750 free_loaded_vmcs(&item->vmcs02);
5751 list_del(&item->list);
5754 vmx->nested.vmcs02_num = 0;
5756 if (vmx->loaded_vmcs != &vmx->vmcs01)
5757 free_loaded_vmcs(&vmx->vmcs01);
5761 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5762 * set the success or error code of an emulated VMX instruction, as specified
5763 * by Vol 2B, VMX Instruction Reference, "Conventions".
5765 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5767 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5768 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5769 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5772 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5774 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5775 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5776 X86_EFLAGS_SF | X86_EFLAGS_OF))
5780 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5781 u32 vm_instruction_error)
5783 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5785 * failValid writes the error number to the current VMCS, which
5786 * can't be done there isn't a current VMCS.
5788 nested_vmx_failInvalid(vcpu);
5791 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5792 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5793 X86_EFLAGS_SF | X86_EFLAGS_OF))
5795 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5797 * We don't need to force a shadow sync because
5798 * VM_INSTRUCTION_ERROR is not shadowed
5802 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5804 struct vcpu_vmx *vmx =
5805 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5807 vmx->nested.preemption_timer_expired = true;
5808 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5809 kvm_vcpu_kick(&vmx->vcpu);
5811 return HRTIMER_NORESTART;
5815 * Emulate the VMXON instruction.
5816 * Currently, we just remember that VMX is active, and do not save or even
5817 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5818 * do not currently need to store anything in that guest-allocated memory
5819 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5820 * argument is different from the VMXON pointer (which the spec says they do).
5822 static int handle_vmon(struct kvm_vcpu *vcpu)
5824 struct kvm_segment cs;
5825 struct vcpu_vmx *vmx = to_vmx(vcpu);
5826 struct vmcs *shadow_vmcs;
5827 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5828 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5830 /* The Intel VMX Instruction Reference lists a bunch of bits that
5831 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5832 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5833 * Otherwise, we should fail with #UD. We test these now:
5835 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5836 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5837 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5838 kvm_queue_exception(vcpu, UD_VECTOR);
5842 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5843 if (is_long_mode(vcpu) && !cs.l) {
5844 kvm_queue_exception(vcpu, UD_VECTOR);
5848 if (vmx_get_cpl(vcpu)) {
5849 kvm_inject_gp(vcpu, 0);
5852 if (vmx->nested.vmxon) {
5853 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5854 skip_emulated_instruction(vcpu);
5858 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5859 != VMXON_NEEDED_FEATURES) {
5860 kvm_inject_gp(vcpu, 0);
5864 if (enable_shadow_vmcs) {
5865 shadow_vmcs = alloc_vmcs();
5868 /* mark vmcs as shadow */
5869 shadow_vmcs->revision_id |= (1u << 31);
5870 /* init shadow vmcs */
5871 vmcs_clear(shadow_vmcs);
5872 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5875 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5876 vmx->nested.vmcs02_num = 0;
5878 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5880 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5882 vmx->nested.vmxon = true;
5884 skip_emulated_instruction(vcpu);
5885 nested_vmx_succeed(vcpu);
5890 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5891 * for running VMX instructions (except VMXON, whose prerequisites are
5892 * slightly different). It also specifies what exception to inject otherwise.
5894 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5896 struct kvm_segment cs;
5897 struct vcpu_vmx *vmx = to_vmx(vcpu);
5899 if (!vmx->nested.vmxon) {
5900 kvm_queue_exception(vcpu, UD_VECTOR);
5904 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5905 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5906 (is_long_mode(vcpu) && !cs.l)) {
5907 kvm_queue_exception(vcpu, UD_VECTOR);
5911 if (vmx_get_cpl(vcpu)) {
5912 kvm_inject_gp(vcpu, 0);
5919 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5922 if (enable_shadow_vmcs) {
5923 if (vmx->nested.current_vmcs12 != NULL) {
5924 /* copy to memory all shadowed fields in case
5925 they were modified */
5926 copy_shadow_to_vmcs12(vmx);
5927 vmx->nested.sync_shadow_vmcs = false;
5928 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5929 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5930 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5931 vmcs_write64(VMCS_LINK_POINTER, -1ull);
5934 kunmap(vmx->nested.current_vmcs12_page);
5935 nested_release_page(vmx->nested.current_vmcs12_page);
5939 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5940 * just stops using VMX.
5942 static void free_nested(struct vcpu_vmx *vmx)
5944 if (!vmx->nested.vmxon)
5946 vmx->nested.vmxon = false;
5947 if (vmx->nested.current_vmptr != -1ull) {
5948 nested_release_vmcs12(vmx);
5949 vmx->nested.current_vmptr = -1ull;
5950 vmx->nested.current_vmcs12 = NULL;
5952 if (enable_shadow_vmcs)
5953 free_vmcs(vmx->nested.current_shadow_vmcs);
5954 /* Unpin physical memory we referred to in current vmcs02 */
5955 if (vmx->nested.apic_access_page) {
5956 nested_release_page(vmx->nested.apic_access_page);
5957 vmx->nested.apic_access_page = 0;
5960 nested_free_all_saved_vmcss(vmx);
5963 /* Emulate the VMXOFF instruction */
5964 static int handle_vmoff(struct kvm_vcpu *vcpu)
5966 if (!nested_vmx_check_permission(vcpu))
5968 free_nested(to_vmx(vcpu));
5969 skip_emulated_instruction(vcpu);
5970 nested_vmx_succeed(vcpu);
5975 * Decode the memory-address operand of a vmx instruction, as recorded on an
5976 * exit caused by such an instruction (run by a guest hypervisor).
5977 * On success, returns 0. When the operand is invalid, returns 1 and throws
5980 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5981 unsigned long exit_qualification,
5982 u32 vmx_instruction_info, gva_t *ret)
5985 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5986 * Execution", on an exit, vmx_instruction_info holds most of the
5987 * addressing components of the operand. Only the displacement part
5988 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5989 * For how an actual address is calculated from all these components,
5990 * refer to Vol. 1, "Operand Addressing".
5992 int scaling = vmx_instruction_info & 3;
5993 int addr_size = (vmx_instruction_info >> 7) & 7;
5994 bool is_reg = vmx_instruction_info & (1u << 10);
5995 int seg_reg = (vmx_instruction_info >> 15) & 7;
5996 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5997 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5998 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5999 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6002 kvm_queue_exception(vcpu, UD_VECTOR);
6006 /* Addr = segment_base + offset */
6007 /* offset = base + [index * scale] + displacement */
6008 *ret = vmx_get_segment_base(vcpu, seg_reg);
6010 *ret += kvm_register_read(vcpu, base_reg);
6012 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6013 *ret += exit_qualification; /* holds the displacement */
6015 if (addr_size == 1) /* 32 bit */
6019 * TODO: throw #GP (and return 1) in various cases that the VM*
6020 * instructions require it - e.g., offset beyond segment limit,
6021 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6022 * address, and so on. Currently these are not checked.
6027 /* Emulate the VMCLEAR instruction */
6028 static int handle_vmclear(struct kvm_vcpu *vcpu)
6030 struct vcpu_vmx *vmx = to_vmx(vcpu);
6033 struct vmcs12 *vmcs12;
6035 struct x86_exception e;
6037 if (!nested_vmx_check_permission(vcpu))
6040 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6041 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6044 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6045 sizeof(vmptr), &e)) {
6046 kvm_inject_page_fault(vcpu, &e);
6050 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6051 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6052 skip_emulated_instruction(vcpu);
6056 if (vmptr == vmx->nested.current_vmptr) {
6057 nested_release_vmcs12(vmx);
6058 vmx->nested.current_vmptr = -1ull;
6059 vmx->nested.current_vmcs12 = NULL;
6062 page = nested_get_page(vcpu, vmptr);
6065 * For accurate processor emulation, VMCLEAR beyond available
6066 * physical memory should do nothing at all. However, it is
6067 * possible that a nested vmx bug, not a guest hypervisor bug,
6068 * resulted in this case, so let's shut down before doing any
6071 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6074 vmcs12 = kmap(page);
6075 vmcs12->launch_state = 0;
6077 nested_release_page(page);
6079 nested_free_vmcs02(vmx, vmptr);
6081 skip_emulated_instruction(vcpu);
6082 nested_vmx_succeed(vcpu);
6086 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6088 /* Emulate the VMLAUNCH instruction */
6089 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6091 return nested_vmx_run(vcpu, true);
6094 /* Emulate the VMRESUME instruction */
6095 static int handle_vmresume(struct kvm_vcpu *vcpu)
6098 return nested_vmx_run(vcpu, false);
6101 enum vmcs_field_type {
6102 VMCS_FIELD_TYPE_U16 = 0,
6103 VMCS_FIELD_TYPE_U64 = 1,
6104 VMCS_FIELD_TYPE_U32 = 2,
6105 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6108 static inline int vmcs_field_type(unsigned long field)
6110 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6111 return VMCS_FIELD_TYPE_U32;
6112 return (field >> 13) & 0x3 ;
6115 static inline int vmcs_field_readonly(unsigned long field)
6117 return (((field >> 10) & 0x3) == 1);
6121 * Read a vmcs12 field. Since these can have varying lengths and we return
6122 * one type, we chose the biggest type (u64) and zero-extend the return value
6123 * to that size. Note that the caller, handle_vmread, might need to use only
6124 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6125 * 64-bit fields are to be returned).
6127 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6128 unsigned long field, u64 *ret)
6130 short offset = vmcs_field_to_offset(field);
6136 p = ((char *)(get_vmcs12(vcpu))) + offset;
6138 switch (vmcs_field_type(field)) {
6139 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6140 *ret = *((natural_width *)p);
6142 case VMCS_FIELD_TYPE_U16:
6145 case VMCS_FIELD_TYPE_U32:
6148 case VMCS_FIELD_TYPE_U64:
6152 return 0; /* can never happen. */
6157 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6158 unsigned long field, u64 field_value){
6159 short offset = vmcs_field_to_offset(field);
6160 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6164 switch (vmcs_field_type(field)) {
6165 case VMCS_FIELD_TYPE_U16:
6166 *(u16 *)p = field_value;
6168 case VMCS_FIELD_TYPE_U32:
6169 *(u32 *)p = field_value;
6171 case VMCS_FIELD_TYPE_U64:
6172 *(u64 *)p = field_value;
6174 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6175 *(natural_width *)p = field_value;
6178 return false; /* can never happen. */
6183 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6186 unsigned long field;
6188 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6189 const unsigned long *fields = shadow_read_write_fields;
6190 const int num_fields = max_shadow_read_write_fields;
6192 vmcs_load(shadow_vmcs);
6194 for (i = 0; i < num_fields; i++) {
6196 switch (vmcs_field_type(field)) {
6197 case VMCS_FIELD_TYPE_U16:
6198 field_value = vmcs_read16(field);
6200 case VMCS_FIELD_TYPE_U32:
6201 field_value = vmcs_read32(field);
6203 case VMCS_FIELD_TYPE_U64:
6204 field_value = vmcs_read64(field);
6206 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6207 field_value = vmcs_readl(field);
6210 vmcs12_write_any(&vmx->vcpu, field, field_value);
6213 vmcs_clear(shadow_vmcs);
6214 vmcs_load(vmx->loaded_vmcs->vmcs);
6217 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6219 const unsigned long *fields[] = {
6220 shadow_read_write_fields,
6221 shadow_read_only_fields
6223 const int max_fields[] = {
6224 max_shadow_read_write_fields,
6225 max_shadow_read_only_fields
6228 unsigned long field;
6229 u64 field_value = 0;
6230 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6232 vmcs_load(shadow_vmcs);
6234 for (q = 0; q < ARRAY_SIZE(fields); q++) {
6235 for (i = 0; i < max_fields[q]; i++) {
6236 field = fields[q][i];
6237 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6239 switch (vmcs_field_type(field)) {
6240 case VMCS_FIELD_TYPE_U16:
6241 vmcs_write16(field, (u16)field_value);
6243 case VMCS_FIELD_TYPE_U32:
6244 vmcs_write32(field, (u32)field_value);
6246 case VMCS_FIELD_TYPE_U64:
6247 vmcs_write64(field, (u64)field_value);
6249 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6250 vmcs_writel(field, (long)field_value);
6256 vmcs_clear(shadow_vmcs);
6257 vmcs_load(vmx->loaded_vmcs->vmcs);
6261 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6262 * used before) all generate the same failure when it is missing.
6264 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6266 struct vcpu_vmx *vmx = to_vmx(vcpu);
6267 if (vmx->nested.current_vmptr == -1ull) {
6268 nested_vmx_failInvalid(vcpu);
6269 skip_emulated_instruction(vcpu);
6275 static int handle_vmread(struct kvm_vcpu *vcpu)
6277 unsigned long field;
6279 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6280 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6283 if (!nested_vmx_check_permission(vcpu) ||
6284 !nested_vmx_check_vmcs12(vcpu))
6287 /* Decode instruction info and find the field to read */
6288 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6289 /* Read the field, zero-extended to a u64 field_value */
6290 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6291 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6292 skip_emulated_instruction(vcpu);
6296 * Now copy part of this value to register or memory, as requested.
6297 * Note that the number of bits actually copied is 32 or 64 depending
6298 * on the guest's mode (32 or 64 bit), not on the given field's length.
6300 if (vmx_instruction_info & (1u << 10)) {
6301 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6304 if (get_vmx_mem_address(vcpu, exit_qualification,
6305 vmx_instruction_info, &gva))
6307 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6308 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6309 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6312 nested_vmx_succeed(vcpu);
6313 skip_emulated_instruction(vcpu);
6318 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6320 unsigned long field;
6322 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6323 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6324 /* The value to write might be 32 or 64 bits, depending on L1's long
6325 * mode, and eventually we need to write that into a field of several
6326 * possible lengths. The code below first zero-extends the value to 64
6327 * bit (field_value), and then copies only the approriate number of
6328 * bits into the vmcs12 field.
6330 u64 field_value = 0;
6331 struct x86_exception e;
6333 if (!nested_vmx_check_permission(vcpu) ||
6334 !nested_vmx_check_vmcs12(vcpu))
6337 if (vmx_instruction_info & (1u << 10))
6338 field_value = kvm_register_read(vcpu,
6339 (((vmx_instruction_info) >> 3) & 0xf));
6341 if (get_vmx_mem_address(vcpu, exit_qualification,
6342 vmx_instruction_info, &gva))
6344 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6345 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6346 kvm_inject_page_fault(vcpu, &e);
6352 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6353 if (vmcs_field_readonly(field)) {
6354 nested_vmx_failValid(vcpu,
6355 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6356 skip_emulated_instruction(vcpu);
6360 if (!vmcs12_write_any(vcpu, field, field_value)) {
6361 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6362 skip_emulated_instruction(vcpu);
6366 nested_vmx_succeed(vcpu);
6367 skip_emulated_instruction(vcpu);
6371 /* Emulate the VMPTRLD instruction */
6372 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6374 struct vcpu_vmx *vmx = to_vmx(vcpu);
6377 struct x86_exception e;
6380 if (!nested_vmx_check_permission(vcpu))
6383 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6384 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6387 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6388 sizeof(vmptr), &e)) {
6389 kvm_inject_page_fault(vcpu, &e);
6393 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6394 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6395 skip_emulated_instruction(vcpu);
6399 if (vmx->nested.current_vmptr != vmptr) {
6400 struct vmcs12 *new_vmcs12;
6402 page = nested_get_page(vcpu, vmptr);
6404 nested_vmx_failInvalid(vcpu);
6405 skip_emulated_instruction(vcpu);
6408 new_vmcs12 = kmap(page);
6409 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6411 nested_release_page_clean(page);
6412 nested_vmx_failValid(vcpu,
6413 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6414 skip_emulated_instruction(vcpu);
6417 if (vmx->nested.current_vmptr != -1ull)
6418 nested_release_vmcs12(vmx);
6420 vmx->nested.current_vmptr = vmptr;
6421 vmx->nested.current_vmcs12 = new_vmcs12;
6422 vmx->nested.current_vmcs12_page = page;
6423 if (enable_shadow_vmcs) {
6424 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6425 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6426 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6427 vmcs_write64(VMCS_LINK_POINTER,
6428 __pa(vmx->nested.current_shadow_vmcs));
6429 vmx->nested.sync_shadow_vmcs = true;
6433 nested_vmx_succeed(vcpu);
6434 skip_emulated_instruction(vcpu);
6438 /* Emulate the VMPTRST instruction */
6439 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6441 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6442 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6444 struct x86_exception e;
6446 if (!nested_vmx_check_permission(vcpu))
6449 if (get_vmx_mem_address(vcpu, exit_qualification,
6450 vmx_instruction_info, &vmcs_gva))
6452 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6453 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6454 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6456 kvm_inject_page_fault(vcpu, &e);
6459 nested_vmx_succeed(vcpu);
6460 skip_emulated_instruction(vcpu);
6464 /* Emulate the INVEPT instruction */
6465 static int handle_invept(struct kvm_vcpu *vcpu)
6467 u32 vmx_instruction_info, types;
6470 struct x86_exception e;
6474 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6476 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6477 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6478 kvm_queue_exception(vcpu, UD_VECTOR);
6482 if (!nested_vmx_check_permission(vcpu))
6485 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6486 kvm_queue_exception(vcpu, UD_VECTOR);
6490 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6491 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6493 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6495 if (!(types & (1UL << type))) {
6496 nested_vmx_failValid(vcpu,
6497 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6501 /* According to the Intel VMX instruction reference, the memory
6502 * operand is read even if it isn't needed (e.g., for type==global)
6504 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6505 vmx_instruction_info, &gva))
6507 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6508 sizeof(operand), &e)) {
6509 kvm_inject_page_fault(vcpu, &e);
6514 case VMX_EPT_EXTENT_CONTEXT:
6515 if ((operand.eptp & eptp_mask) !=
6516 (nested_ept_get_cr3(vcpu) & eptp_mask))
6518 case VMX_EPT_EXTENT_GLOBAL:
6519 kvm_mmu_sync_roots(vcpu);
6520 kvm_mmu_flush_tlb(vcpu);
6521 nested_vmx_succeed(vcpu);
6528 skip_emulated_instruction(vcpu);
6533 * The exit handlers return 1 if the exit was handled fully and guest execution
6534 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6535 * to be done to userspace and return 0.
6537 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6538 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6539 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
6540 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6541 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6542 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6543 [EXIT_REASON_CR_ACCESS] = handle_cr,
6544 [EXIT_REASON_DR_ACCESS] = handle_dr,
6545 [EXIT_REASON_CPUID] = handle_cpuid,
6546 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6547 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6548 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6549 [EXIT_REASON_HLT] = handle_halt,
6550 [EXIT_REASON_INVD] = handle_invd,
6551 [EXIT_REASON_INVLPG] = handle_invlpg,
6552 [EXIT_REASON_RDPMC] = handle_rdpmc,
6553 [EXIT_REASON_VMCALL] = handle_vmcall,
6554 [EXIT_REASON_VMCLEAR] = handle_vmclear,
6555 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
6556 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6557 [EXIT_REASON_VMPTRST] = handle_vmptrst,
6558 [EXIT_REASON_VMREAD] = handle_vmread,
6559 [EXIT_REASON_VMRESUME] = handle_vmresume,
6560 [EXIT_REASON_VMWRITE] = handle_vmwrite,
6561 [EXIT_REASON_VMOFF] = handle_vmoff,
6562 [EXIT_REASON_VMON] = handle_vmon,
6563 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6564 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
6565 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
6566 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
6567 [EXIT_REASON_WBINVD] = handle_wbinvd,
6568 [EXIT_REASON_XSETBV] = handle_xsetbv,
6569 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
6570 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
6571 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6572 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6573 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
6574 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6575 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6576 [EXIT_REASON_INVEPT] = handle_invept,
6579 static const int kvm_vmx_max_exit_handlers =
6580 ARRAY_SIZE(kvm_vmx_exit_handlers);
6582 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6583 struct vmcs12 *vmcs12)
6585 unsigned long exit_qualification;
6586 gpa_t bitmap, last_bitmap;
6591 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6592 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6594 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6596 port = exit_qualification >> 16;
6597 size = (exit_qualification & 7) + 1;
6599 last_bitmap = (gpa_t)-1;
6604 bitmap = vmcs12->io_bitmap_a;
6605 else if (port < 0x10000)
6606 bitmap = vmcs12->io_bitmap_b;
6609 bitmap += (port & 0x7fff) / 8;
6611 if (last_bitmap != bitmap)
6612 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6614 if (b & (1 << (port & 7)))
6619 last_bitmap = bitmap;
6626 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6627 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6628 * disinterest in the current event (read or write a specific MSR) by using an
6629 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6631 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6632 struct vmcs12 *vmcs12, u32 exit_reason)
6634 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6637 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6641 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6642 * for the four combinations of read/write and low/high MSR numbers.
6643 * First we need to figure out which of the four to use:
6645 bitmap = vmcs12->msr_bitmap;
6646 if (exit_reason == EXIT_REASON_MSR_WRITE)
6648 if (msr_index >= 0xc0000000) {
6649 msr_index -= 0xc0000000;
6653 /* Then read the msr_index'th bit from this bitmap: */
6654 if (msr_index < 1024*8) {
6656 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6658 return 1 & (b >> (msr_index & 7));
6660 return 1; /* let L1 handle the wrong parameter */
6664 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6665 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6666 * intercept (via guest_host_mask etc.) the current event.
6668 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6669 struct vmcs12 *vmcs12)
6671 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6672 int cr = exit_qualification & 15;
6673 int reg = (exit_qualification >> 8) & 15;
6674 unsigned long val = kvm_register_read(vcpu, reg);
6676 switch ((exit_qualification >> 4) & 3) {
6677 case 0: /* mov to cr */
6680 if (vmcs12->cr0_guest_host_mask &
6681 (val ^ vmcs12->cr0_read_shadow))
6685 if ((vmcs12->cr3_target_count >= 1 &&
6686 vmcs12->cr3_target_value0 == val) ||
6687 (vmcs12->cr3_target_count >= 2 &&
6688 vmcs12->cr3_target_value1 == val) ||
6689 (vmcs12->cr3_target_count >= 3 &&
6690 vmcs12->cr3_target_value2 == val) ||
6691 (vmcs12->cr3_target_count >= 4 &&
6692 vmcs12->cr3_target_value3 == val))
6694 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6698 if (vmcs12->cr4_guest_host_mask &
6699 (vmcs12->cr4_read_shadow ^ val))
6703 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6709 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6710 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6713 case 1: /* mov from cr */
6716 if (vmcs12->cpu_based_vm_exec_control &
6717 CPU_BASED_CR3_STORE_EXITING)
6721 if (vmcs12->cpu_based_vm_exec_control &
6722 CPU_BASED_CR8_STORE_EXITING)
6729 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6730 * cr0. Other attempted changes are ignored, with no exit.
6732 if (vmcs12->cr0_guest_host_mask & 0xe &
6733 (val ^ vmcs12->cr0_read_shadow))
6735 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6736 !(vmcs12->cr0_read_shadow & 0x1) &&
6745 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6746 * should handle it ourselves in L0 (and then continue L2). Only call this
6747 * when in is_guest_mode (L2).
6749 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6751 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6752 struct vcpu_vmx *vmx = to_vmx(vcpu);
6753 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6754 u32 exit_reason = vmx->exit_reason;
6756 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6757 vmcs_readl(EXIT_QUALIFICATION),
6758 vmx->idt_vectoring_info,
6760 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6763 if (vmx->nested.nested_run_pending)
6766 if (unlikely(vmx->fail)) {
6767 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6768 vmcs_read32(VM_INSTRUCTION_ERROR));
6772 switch (exit_reason) {
6773 case EXIT_REASON_EXCEPTION_NMI:
6774 if (!is_exception(intr_info))
6776 else if (is_page_fault(intr_info))
6778 else if (is_no_device(intr_info) &&
6779 !(vmcs12->guest_cr0 & X86_CR0_TS))
6781 return vmcs12->exception_bitmap &
6782 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6783 case EXIT_REASON_EXTERNAL_INTERRUPT:
6785 case EXIT_REASON_TRIPLE_FAULT:
6787 case EXIT_REASON_PENDING_INTERRUPT:
6788 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6789 case EXIT_REASON_NMI_WINDOW:
6790 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6791 case EXIT_REASON_TASK_SWITCH:
6793 case EXIT_REASON_CPUID:
6795 case EXIT_REASON_HLT:
6796 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6797 case EXIT_REASON_INVD:
6799 case EXIT_REASON_INVLPG:
6800 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6801 case EXIT_REASON_RDPMC:
6802 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6803 case EXIT_REASON_RDTSC:
6804 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6805 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6806 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6807 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6808 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6809 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6810 case EXIT_REASON_INVEPT:
6812 * VMX instructions trap unconditionally. This allows L1 to
6813 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6816 case EXIT_REASON_CR_ACCESS:
6817 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6818 case EXIT_REASON_DR_ACCESS:
6819 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6820 case EXIT_REASON_IO_INSTRUCTION:
6821 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6822 case EXIT_REASON_MSR_READ:
6823 case EXIT_REASON_MSR_WRITE:
6824 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6825 case EXIT_REASON_INVALID_STATE:
6827 case EXIT_REASON_MWAIT_INSTRUCTION:
6828 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6829 case EXIT_REASON_MONITOR_INSTRUCTION:
6830 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6831 case EXIT_REASON_PAUSE_INSTRUCTION:
6832 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6833 nested_cpu_has2(vmcs12,
6834 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6835 case EXIT_REASON_MCE_DURING_VMENTRY:
6837 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6839 case EXIT_REASON_APIC_ACCESS:
6840 return nested_cpu_has2(vmcs12,
6841 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6842 case EXIT_REASON_EPT_VIOLATION:
6844 * L0 always deals with the EPT violation. If nested EPT is
6845 * used, and the nested mmu code discovers that the address is
6846 * missing in the guest EPT table (EPT12), the EPT violation
6847 * will be injected with nested_ept_inject_page_fault()
6850 case EXIT_REASON_EPT_MISCONFIG:
6852 * L2 never uses directly L1's EPT, but rather L0's own EPT
6853 * table (shadow on EPT) or a merged EPT table that L0 built
6854 * (EPT on EPT). So any problems with the structure of the
6855 * table is L0's fault.
6858 case EXIT_REASON_WBINVD:
6859 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6860 case EXIT_REASON_XSETBV:
6867 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6869 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6870 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6874 * The guest has exited. See if we can fix it or if we need userspace
6877 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6879 struct vcpu_vmx *vmx = to_vmx(vcpu);
6880 u32 exit_reason = vmx->exit_reason;
6881 u32 vectoring_info = vmx->idt_vectoring_info;
6883 /* If guest state is invalid, start emulating */
6884 if (vmx->emulation_required)
6885 return handle_invalid_guest_state(vcpu);
6887 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6888 nested_vmx_vmexit(vcpu, exit_reason,
6889 vmcs_read32(VM_EXIT_INTR_INFO),
6890 vmcs_readl(EXIT_QUALIFICATION));
6894 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6895 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6896 vcpu->run->fail_entry.hardware_entry_failure_reason
6901 if (unlikely(vmx->fail)) {
6902 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6903 vcpu->run->fail_entry.hardware_entry_failure_reason
6904 = vmcs_read32(VM_INSTRUCTION_ERROR);
6910 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6911 * delivery event since it indicates guest is accessing MMIO.
6912 * The vm-exit can be triggered again after return to guest that
6913 * will cause infinite loop.
6915 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6916 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6917 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6918 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6919 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6920 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6921 vcpu->run->internal.ndata = 2;
6922 vcpu->run->internal.data[0] = vectoring_info;
6923 vcpu->run->internal.data[1] = exit_reason;
6927 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6928 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6929 get_vmcs12(vcpu))))) {
6930 if (vmx_interrupt_allowed(vcpu)) {
6931 vmx->soft_vnmi_blocked = 0;
6932 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6933 vcpu->arch.nmi_pending) {
6935 * This CPU don't support us in finding the end of an
6936 * NMI-blocked window if the guest runs with IRQs
6937 * disabled. So we pull the trigger after 1 s of
6938 * futile waiting, but inform the user about this.
6940 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6941 "state on VCPU %d after 1 s timeout\n",
6942 __func__, vcpu->vcpu_id);
6943 vmx->soft_vnmi_blocked = 0;
6947 if (exit_reason < kvm_vmx_max_exit_handlers
6948 && kvm_vmx_exit_handlers[exit_reason])
6949 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6951 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6952 vcpu->run->hw.hardware_exit_reason = exit_reason;
6957 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6959 if (irr == -1 || tpr < irr) {
6960 vmcs_write32(TPR_THRESHOLD, 0);
6964 vmcs_write32(TPR_THRESHOLD, irr);
6967 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6969 u32 sec_exec_control;
6972 * There is not point to enable virtualize x2apic without enable
6975 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6976 !vmx_vm_has_apicv(vcpu->kvm))
6979 if (!vm_need_tpr_shadow(vcpu->kvm))
6982 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6985 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6986 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6988 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6989 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6991 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6993 vmx_set_msr_bitmap(vcpu);
6996 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7001 if (!vmx_vm_has_apicv(kvm))
7007 status = vmcs_read16(GUEST_INTR_STATUS);
7012 vmcs_write16(GUEST_INTR_STATUS, status);
7016 static void vmx_set_rvi(int vector)
7021 status = vmcs_read16(GUEST_INTR_STATUS);
7022 old = (u8)status & 0xff;
7023 if ((u8)vector != old) {
7025 status |= (u8)vector;
7026 vmcs_write16(GUEST_INTR_STATUS, status);
7030 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7035 vmx_set_rvi(max_irr);
7038 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7040 if (!vmx_vm_has_apicv(vcpu->kvm))
7043 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7044 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7045 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7046 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7049 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7053 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7054 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7057 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7058 exit_intr_info = vmx->exit_intr_info;
7060 /* Handle machine checks before interrupts are enabled */
7061 if (is_machine_check(exit_intr_info))
7062 kvm_machine_check();
7064 /* We need to handle NMIs before interrupts are enabled */
7065 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7066 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7067 kvm_before_handle_nmi(&vmx->vcpu);
7069 kvm_after_handle_nmi(&vmx->vcpu);
7073 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7075 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7078 * If external interrupt exists, IF bit is set in rflags/eflags on the
7079 * interrupt stack frame, and interrupt will be enabled on a return
7080 * from interrupt handler.
7082 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7083 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7084 unsigned int vector;
7085 unsigned long entry;
7087 struct vcpu_vmx *vmx = to_vmx(vcpu);
7088 #ifdef CONFIG_X86_64
7092 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7093 desc = (gate_desc *)vmx->host_idt_base + vector;
7094 entry = gate_offset(*desc);
7096 #ifdef CONFIG_X86_64
7097 "mov %%" _ASM_SP ", %[sp]\n\t"
7098 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7103 "orl $0x200, (%%" _ASM_SP ")\n\t"
7104 __ASM_SIZE(push) " $%c[cs]\n\t"
7105 "call *%[entry]\n\t"
7107 #ifdef CONFIG_X86_64
7112 [ss]"i"(__KERNEL_DS),
7113 [cs]"i"(__KERNEL_CS)
7119 static bool vmx_mpx_supported(void)
7121 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7122 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7125 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7130 bool idtv_info_valid;
7132 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7134 if (cpu_has_virtual_nmis()) {
7135 if (vmx->nmi_known_unmasked)
7138 * Can't use vmx->exit_intr_info since we're not sure what
7139 * the exit reason is.
7141 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7142 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7143 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7145 * SDM 3: 27.7.1.2 (September 2008)
7146 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7147 * a guest IRET fault.
7148 * SDM 3: 23.2.2 (September 2008)
7149 * Bit 12 is undefined in any of the following cases:
7150 * If the VM exit sets the valid bit in the IDT-vectoring
7151 * information field.
7152 * If the VM exit is due to a double fault.
7154 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7155 vector != DF_VECTOR && !idtv_info_valid)
7156 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7157 GUEST_INTR_STATE_NMI);
7159 vmx->nmi_known_unmasked =
7160 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7161 & GUEST_INTR_STATE_NMI);
7162 } else if (unlikely(vmx->soft_vnmi_blocked))
7163 vmx->vnmi_blocked_time +=
7164 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7167 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7168 u32 idt_vectoring_info,
7169 int instr_len_field,
7170 int error_code_field)
7174 bool idtv_info_valid;
7176 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7178 vcpu->arch.nmi_injected = false;
7179 kvm_clear_exception_queue(vcpu);
7180 kvm_clear_interrupt_queue(vcpu);
7182 if (!idtv_info_valid)
7185 kvm_make_request(KVM_REQ_EVENT, vcpu);
7187 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7188 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7191 case INTR_TYPE_NMI_INTR:
7192 vcpu->arch.nmi_injected = true;
7194 * SDM 3: 27.7.1.2 (September 2008)
7195 * Clear bit "block by NMI" before VM entry if a NMI
7198 vmx_set_nmi_mask(vcpu, false);
7200 case INTR_TYPE_SOFT_EXCEPTION:
7201 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7203 case INTR_TYPE_HARD_EXCEPTION:
7204 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7205 u32 err = vmcs_read32(error_code_field);
7206 kvm_requeue_exception_e(vcpu, vector, err);
7208 kvm_requeue_exception(vcpu, vector);
7210 case INTR_TYPE_SOFT_INTR:
7211 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7213 case INTR_TYPE_EXT_INTR:
7214 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7221 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7223 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7224 VM_EXIT_INSTRUCTION_LEN,
7225 IDT_VECTORING_ERROR_CODE);
7228 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7230 __vmx_complete_interrupts(vcpu,
7231 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7232 VM_ENTRY_INSTRUCTION_LEN,
7233 VM_ENTRY_EXCEPTION_ERROR_CODE);
7235 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7238 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7241 struct perf_guest_switch_msr *msrs;
7243 msrs = perf_guest_get_msrs(&nr_msrs);
7248 for (i = 0; i < nr_msrs; i++)
7249 if (msrs[i].host == msrs[i].guest)
7250 clear_atomic_switch_msr(vmx, msrs[i].msr);
7252 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7256 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7258 struct vcpu_vmx *vmx = to_vmx(vcpu);
7259 unsigned long debugctlmsr;
7261 /* Record the guest's net vcpu time for enforced NMI injections. */
7262 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7263 vmx->entry_time = ktime_get();
7265 /* Don't enter VMX if guest state is invalid, let the exit handler
7266 start emulation until we arrive back to a valid state */
7267 if (vmx->emulation_required)
7270 if (vmx->nested.sync_shadow_vmcs) {
7271 copy_vmcs12_to_shadow(vmx);
7272 vmx->nested.sync_shadow_vmcs = false;
7275 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7276 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7277 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7278 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7280 /* When single-stepping over STI and MOV SS, we must clear the
7281 * corresponding interruptibility bits in the guest state. Otherwise
7282 * vmentry fails as it then expects bit 14 (BS) in pending debug
7283 * exceptions being set, but that's not correct for the guest debugging
7285 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7286 vmx_set_interrupt_shadow(vcpu, 0);
7288 atomic_switch_perf_msrs(vmx);
7289 debugctlmsr = get_debugctlmsr();
7291 vmx->__launched = vmx->loaded_vmcs->launched;
7293 /* Store host registers */
7294 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7295 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7296 "push %%" _ASM_CX " \n\t"
7297 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7299 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7300 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7302 /* Reload cr2 if changed */
7303 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7304 "mov %%cr2, %%" _ASM_DX " \n\t"
7305 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7307 "mov %%" _ASM_AX", %%cr2 \n\t"
7309 /* Check if vmlaunch of vmresume is needed */
7310 "cmpl $0, %c[launched](%0) \n\t"
7311 /* Load guest registers. Don't clobber flags. */
7312 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7313 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7314 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7315 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7316 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7317 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7318 #ifdef CONFIG_X86_64
7319 "mov %c[r8](%0), %%r8 \n\t"
7320 "mov %c[r9](%0), %%r9 \n\t"
7321 "mov %c[r10](%0), %%r10 \n\t"
7322 "mov %c[r11](%0), %%r11 \n\t"
7323 "mov %c[r12](%0), %%r12 \n\t"
7324 "mov %c[r13](%0), %%r13 \n\t"
7325 "mov %c[r14](%0), %%r14 \n\t"
7326 "mov %c[r15](%0), %%r15 \n\t"
7328 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7330 /* Enter guest mode */
7332 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7334 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7336 /* Save guest registers, load host registers, keep flags */
7337 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7339 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7340 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7341 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7342 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7343 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7344 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7345 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7346 #ifdef CONFIG_X86_64
7347 "mov %%r8, %c[r8](%0) \n\t"
7348 "mov %%r9, %c[r9](%0) \n\t"
7349 "mov %%r10, %c[r10](%0) \n\t"
7350 "mov %%r11, %c[r11](%0) \n\t"
7351 "mov %%r12, %c[r12](%0) \n\t"
7352 "mov %%r13, %c[r13](%0) \n\t"
7353 "mov %%r14, %c[r14](%0) \n\t"
7354 "mov %%r15, %c[r15](%0) \n\t"
7356 "mov %%cr2, %%" _ASM_AX " \n\t"
7357 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7359 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
7360 "setbe %c[fail](%0) \n\t"
7361 ".pushsection .rodata \n\t"
7362 ".global vmx_return \n\t"
7363 "vmx_return: " _ASM_PTR " 2b \n\t"
7365 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7366 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7367 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7368 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7369 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7370 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7371 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7372 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7373 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7374 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7375 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7376 #ifdef CONFIG_X86_64
7377 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7378 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7379 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7380 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7381 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7382 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7383 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7384 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7386 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7387 [wordsize]"i"(sizeof(ulong))
7389 #ifdef CONFIG_X86_64
7390 , "rax", "rbx", "rdi", "rsi"
7391 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7393 , "eax", "ebx", "edi", "esi"
7397 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7399 update_debugctlmsr(debugctlmsr);
7401 #ifndef CONFIG_X86_64
7403 * The sysexit path does not restore ds/es, so we must set them to
7404 * a reasonable value ourselves.
7406 * We can't defer this to vmx_load_host_state() since that function
7407 * may be executed in interrupt context, which saves and restore segments
7408 * around it, nullifying its effect.
7410 loadsegment(ds, __USER_DS);
7411 loadsegment(es, __USER_DS);
7414 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7415 | (1 << VCPU_EXREG_RFLAGS)
7416 | (1 << VCPU_EXREG_CPL)
7417 | (1 << VCPU_EXREG_PDPTR)
7418 | (1 << VCPU_EXREG_SEGMENTS)
7419 | (1 << VCPU_EXREG_CR3));
7420 vcpu->arch.regs_dirty = 0;
7422 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7424 vmx->loaded_vmcs->launched = 1;
7426 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7427 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7430 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7431 * we did not inject a still-pending event to L1 now because of
7432 * nested_run_pending, we need to re-enable this bit.
7434 if (vmx->nested.nested_run_pending)
7435 kvm_make_request(KVM_REQ_EVENT, vcpu);
7437 vmx->nested.nested_run_pending = 0;
7439 vmx_complete_atomic_exit(vmx);
7440 vmx_recover_nmi_blocking(vmx);
7441 vmx_complete_interrupts(vmx);
7444 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7446 struct vcpu_vmx *vmx = to_vmx(vcpu);
7449 free_loaded_vmcs(vmx->loaded_vmcs);
7451 kfree(vmx->guest_msrs);
7452 kvm_vcpu_uninit(vcpu);
7453 kmem_cache_free(kvm_vcpu_cache, vmx);
7456 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7459 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7463 return ERR_PTR(-ENOMEM);
7467 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7471 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7473 if (!vmx->guest_msrs) {
7477 vmx->loaded_vmcs = &vmx->vmcs01;
7478 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7479 if (!vmx->loaded_vmcs->vmcs)
7482 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7483 loaded_vmcs_init(vmx->loaded_vmcs);
7488 vmx_vcpu_load(&vmx->vcpu, cpu);
7489 vmx->vcpu.cpu = cpu;
7490 err = vmx_vcpu_setup(vmx);
7491 vmx_vcpu_put(&vmx->vcpu);
7495 if (vm_need_virtualize_apic_accesses(kvm)) {
7496 err = alloc_apic_access_page(kvm);
7502 if (!kvm->arch.ept_identity_map_addr)
7503 kvm->arch.ept_identity_map_addr =
7504 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7506 if (alloc_identity_pagetable(kvm) != 0)
7508 if (!init_rmode_identity_map(kvm))
7512 vmx->nested.current_vmptr = -1ull;
7513 vmx->nested.current_vmcs12 = NULL;
7518 free_loaded_vmcs(vmx->loaded_vmcs);
7520 kfree(vmx->guest_msrs);
7522 kvm_vcpu_uninit(&vmx->vcpu);
7525 kmem_cache_free(kvm_vcpu_cache, vmx);
7526 return ERR_PTR(err);
7529 static void __init vmx_check_processor_compat(void *rtn)
7531 struct vmcs_config vmcs_conf;
7534 if (setup_vmcs_config(&vmcs_conf) < 0)
7536 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7537 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7538 smp_processor_id());
7543 static int get_ept_level(void)
7545 return VMX_EPT_DEFAULT_GAW + 1;
7548 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7552 /* For VT-d and EPT combination
7553 * 1. MMIO: always map as UC
7555 * a. VT-d without snooping control feature: can't guarantee the
7556 * result, try to trust guest.
7557 * b. VT-d with snooping control feature: snooping control feature of
7558 * VT-d engine can guarantee the cache correctness. Just set it
7559 * to WB to keep consistent with host. So the same as item 3.
7560 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7561 * consistent with host MTRR
7564 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7565 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7566 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7567 VMX_EPT_MT_EPTE_SHIFT;
7569 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7575 static int vmx_get_lpage_level(void)
7577 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7578 return PT_DIRECTORY_LEVEL;
7580 /* For shadow and EPT supported 1GB page */
7581 return PT_PDPE_LEVEL;
7584 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7586 struct kvm_cpuid_entry2 *best;
7587 struct vcpu_vmx *vmx = to_vmx(vcpu);
7590 vmx->rdtscp_enabled = false;
7591 if (vmx_rdtscp_supported()) {
7592 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7593 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7594 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7595 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7596 vmx->rdtscp_enabled = true;
7598 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7599 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7605 /* Exposing INVPCID only when PCID is exposed */
7606 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7607 if (vmx_invpcid_supported() &&
7608 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7609 guest_cpuid_has_pcid(vcpu)) {
7610 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7611 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7612 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7615 if (cpu_has_secondary_exec_ctrls()) {
7616 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7617 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7618 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7622 best->ebx &= ~bit(X86_FEATURE_INVPCID);
7626 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7628 if (func == 1 && nested)
7629 entry->ecx |= bit(X86_FEATURE_VMX);
7632 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7633 struct x86_exception *fault)
7635 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7638 if (fault->error_code & PFERR_RSVD_MASK)
7639 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7641 exit_reason = EXIT_REASON_EPT_VIOLATION;
7642 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7643 vmcs12->guest_physical_address = fault->address;
7646 /* Callbacks for nested_ept_init_mmu_context: */
7648 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7650 /* return the page table to be shadowed - in our case, EPT12 */
7651 return get_vmcs12(vcpu)->ept_pointer;
7654 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7656 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7657 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7659 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7660 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7661 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7663 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7666 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7668 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7671 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7672 struct x86_exception *fault)
7674 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7676 WARN_ON(!is_guest_mode(vcpu));
7678 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7679 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7680 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7681 vmcs_read32(VM_EXIT_INTR_INFO),
7682 vmcs_readl(EXIT_QUALIFICATION));
7684 kvm_inject_page_fault(vcpu, fault);
7687 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7689 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7690 struct vcpu_vmx *vmx = to_vmx(vcpu);
7692 if (vcpu->arch.virtual_tsc_khz == 0)
7695 /* Make sure short timeouts reliably trigger an immediate vmexit.
7696 * hrtimer_start does not guarantee this. */
7697 if (preemption_timeout <= 1) {
7698 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7702 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7703 preemption_timeout *= 1000000;
7704 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7705 hrtimer_start(&vmx->nested.preemption_timer,
7706 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7710 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7711 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7712 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7713 * guest in a way that will both be appropriate to L1's requests, and our
7714 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7715 * function also has additional necessary side-effects, like setting various
7716 * vcpu->arch fields.
7718 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7720 struct vcpu_vmx *vmx = to_vmx(vcpu);
7723 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7724 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7725 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7726 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7727 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7728 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7729 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7730 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7731 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7732 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7733 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7734 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7735 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7736 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7737 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7738 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7739 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7740 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7741 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7742 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7743 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7744 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7745 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7746 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7747 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7748 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7749 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7750 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7751 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7752 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7753 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7754 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7755 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7756 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7757 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7758 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7760 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7761 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7762 vmcs12->vm_entry_intr_info_field);
7763 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7764 vmcs12->vm_entry_exception_error_code);
7765 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7766 vmcs12->vm_entry_instruction_len);
7767 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7768 vmcs12->guest_interruptibility_info);
7769 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7770 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7771 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7772 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7773 vmcs12->guest_pending_dbg_exceptions);
7774 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7775 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7777 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7779 exec_control = vmcs12->pin_based_vm_exec_control;
7780 exec_control |= vmcs_config.pin_based_exec_ctrl;
7781 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7782 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
7784 vmx->nested.preemption_timer_expired = false;
7785 if (nested_cpu_has_preemption_timer(vmcs12))
7786 vmx_start_preemption_timer(vcpu);
7789 * Whether page-faults are trapped is determined by a combination of
7790 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7791 * If enable_ept, L0 doesn't care about page faults and we should
7792 * set all of these to L1's desires. However, if !enable_ept, L0 does
7793 * care about (at least some) page faults, and because it is not easy
7794 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7795 * to exit on each and every L2 page fault. This is done by setting
7796 * MASK=MATCH=0 and (see below) EB.PF=1.
7797 * Note that below we don't need special code to set EB.PF beyond the
7798 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7799 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7800 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7802 * A problem with this approach (when !enable_ept) is that L1 may be
7803 * injected with more page faults than it asked for. This could have
7804 * caused problems, but in practice existing hypervisors don't care.
7805 * To fix this, we will need to emulate the PFEC checking (on the L1
7806 * page tables), using walk_addr(), when injecting PFs to L1.
7808 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7809 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7810 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7811 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7813 if (cpu_has_secondary_exec_ctrls()) {
7814 exec_control = vmx_secondary_exec_control(vmx);
7815 if (!vmx->rdtscp_enabled)
7816 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7817 /* Take the following fields only from vmcs12 */
7818 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7819 if (nested_cpu_has(vmcs12,
7820 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7821 exec_control |= vmcs12->secondary_vm_exec_control;
7823 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7825 * Translate L1 physical address to host physical
7826 * address for vmcs02. Keep the page pinned, so this
7827 * physical address remains valid. We keep a reference
7828 * to it so we can release it later.
7830 if (vmx->nested.apic_access_page) /* shouldn't happen */
7831 nested_release_page(vmx->nested.apic_access_page);
7832 vmx->nested.apic_access_page =
7833 nested_get_page(vcpu, vmcs12->apic_access_addr);
7835 * If translation failed, no matter: This feature asks
7836 * to exit when accessing the given address, and if it
7837 * can never be accessed, this feature won't do
7840 if (!vmx->nested.apic_access_page)
7842 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7844 vmcs_write64(APIC_ACCESS_ADDR,
7845 page_to_phys(vmx->nested.apic_access_page));
7846 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7848 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7849 vmcs_write64(APIC_ACCESS_ADDR,
7850 page_to_phys(vcpu->kvm->arch.apic_access_page));
7853 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7858 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7859 * Some constant fields are set here by vmx_set_constant_host_state().
7860 * Other fields are different per CPU, and will be set later when
7861 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7863 vmx_set_constant_host_state(vmx);
7866 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7867 * entry, but only if the current (host) sp changed from the value
7868 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7869 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7870 * here we just force the write to happen on entry.
7874 exec_control = vmx_exec_control(vmx); /* L0's desires */
7875 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7876 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7877 exec_control &= ~CPU_BASED_TPR_SHADOW;
7878 exec_control |= vmcs12->cpu_based_vm_exec_control;
7880 * Merging of IO and MSR bitmaps not currently supported.
7881 * Rather, exit every time.
7883 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7884 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7885 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7887 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7889 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7890 * bitwise-or of what L1 wants to trap for L2, and what we want to
7891 * trap. Note that CR0.TS also needs updating - we do this later.
7893 update_exception_bitmap(vcpu);
7894 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7895 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7897 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7898 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7899 * bits are further modified by vmx_set_efer() below.
7901 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7903 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7904 * emulated by vmx_set_efer(), below.
7906 vm_entry_controls_init(vmx,
7907 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7908 ~VM_ENTRY_IA32E_MODE) |
7909 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7911 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7912 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7913 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7914 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7915 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7918 set_cr4_guest_host_mask(vmx);
7920 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7921 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7923 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7924 vmcs_write64(TSC_OFFSET,
7925 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7927 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7931 * Trivially support vpid by letting L2s share their parent
7932 * L1's vpid. TODO: move to a more elaborate solution, giving
7933 * each L2 its own vpid and exposing the vpid feature to L1.
7935 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7936 vmx_flush_tlb(vcpu);
7939 if (nested_cpu_has_ept(vmcs12)) {
7940 kvm_mmu_unload(vcpu);
7941 nested_ept_init_mmu_context(vcpu);
7944 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7945 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7946 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7947 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7949 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7950 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7951 vmx_set_efer(vcpu, vcpu->arch.efer);
7954 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7955 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7956 * The CR0_READ_SHADOW is what L2 should have expected to read given
7957 * the specifications by L1; It's not enough to take
7958 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7959 * have more bits than L1 expected.
7961 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7962 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7964 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7965 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7967 /* shadow page tables on either EPT or shadow page tables */
7968 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7969 kvm_mmu_reset_context(vcpu);
7972 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7975 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7978 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7979 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7980 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7981 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7984 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7985 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7989 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7990 * for running an L2 nested guest.
7992 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7994 struct vmcs12 *vmcs12;
7995 struct vcpu_vmx *vmx = to_vmx(vcpu);
7997 struct loaded_vmcs *vmcs02;
8000 if (!nested_vmx_check_permission(vcpu) ||
8001 !nested_vmx_check_vmcs12(vcpu))
8004 skip_emulated_instruction(vcpu);
8005 vmcs12 = get_vmcs12(vcpu);
8007 if (enable_shadow_vmcs)
8008 copy_shadow_to_vmcs12(vmx);
8011 * The nested entry process starts with enforcing various prerequisites
8012 * on vmcs12 as required by the Intel SDM, and act appropriately when
8013 * they fail: As the SDM explains, some conditions should cause the
8014 * instruction to fail, while others will cause the instruction to seem
8015 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8016 * To speed up the normal (success) code path, we should avoid checking
8017 * for misconfigurations which will anyway be caught by the processor
8018 * when using the merged vmcs02.
8020 if (vmcs12->launch_state == launch) {
8021 nested_vmx_failValid(vcpu,
8022 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8023 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8027 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8028 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8029 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8033 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8034 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8035 /*TODO: Also verify bits beyond physical address width are 0*/
8036 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8040 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8041 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8042 /*TODO: Also verify bits beyond physical address width are 0*/
8043 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8047 if (vmcs12->vm_entry_msr_load_count > 0 ||
8048 vmcs12->vm_exit_msr_load_count > 0 ||
8049 vmcs12->vm_exit_msr_store_count > 0) {
8050 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8052 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8056 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8057 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8058 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8059 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8060 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8061 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8062 !vmx_control_verify(vmcs12->vm_exit_controls,
8063 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8064 !vmx_control_verify(vmcs12->vm_entry_controls,
8065 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8067 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8071 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8072 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8073 nested_vmx_failValid(vcpu,
8074 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8078 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8079 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8080 nested_vmx_entry_failure(vcpu, vmcs12,
8081 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8084 if (vmcs12->vmcs_link_pointer != -1ull) {
8085 nested_vmx_entry_failure(vcpu, vmcs12,
8086 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8091 * If the load IA32_EFER VM-entry control is 1, the following checks
8092 * are performed on the field for the IA32_EFER MSR:
8093 * - Bits reserved in the IA32_EFER MSR must be 0.
8094 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8095 * the IA-32e mode guest VM-exit control. It must also be identical
8096 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8099 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8100 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8101 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8102 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8103 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8104 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8105 nested_vmx_entry_failure(vcpu, vmcs12,
8106 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8112 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8113 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8114 * the values of the LMA and LME bits in the field must each be that of
8115 * the host address-space size VM-exit control.
8117 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8118 ia32e = (vmcs12->vm_exit_controls &
8119 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8120 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8121 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8122 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8123 nested_vmx_entry_failure(vcpu, vmcs12,
8124 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8130 * We're finally done with prerequisite checking, and can start with
8134 vmcs02 = nested_get_current_vmcs02(vmx);
8138 enter_guest_mode(vcpu);
8140 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8143 vmx->loaded_vmcs = vmcs02;
8145 vmx_vcpu_load(vcpu, cpu);
8149 vmx_segment_cache_clear(vmx);
8151 vmcs12->launch_state = 1;
8153 prepare_vmcs02(vcpu, vmcs12);
8155 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8156 return kvm_emulate_halt(vcpu);
8158 vmx->nested.nested_run_pending = 1;
8161 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8162 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8163 * returned as far as L1 is concerned. It will only return (and set
8164 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8170 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8171 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8172 * This function returns the new value we should put in vmcs12.guest_cr0.
8173 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8174 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8175 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8176 * didn't trap the bit, because if L1 did, so would L0).
8177 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8178 * been modified by L2, and L1 knows it. So just leave the old value of
8179 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8180 * isn't relevant, because if L0 traps this bit it can set it to anything.
8181 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8182 * changed these bits, and therefore they need to be updated, but L0
8183 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8184 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8186 static inline unsigned long
8187 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8190 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8191 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8192 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8193 vcpu->arch.cr0_guest_owned_bits));
8196 static inline unsigned long
8197 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8200 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8201 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8202 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8203 vcpu->arch.cr4_guest_owned_bits));
8206 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8207 struct vmcs12 *vmcs12)
8212 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8213 nr = vcpu->arch.exception.nr;
8214 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8216 if (kvm_exception_is_soft(nr)) {
8217 vmcs12->vm_exit_instruction_len =
8218 vcpu->arch.event_exit_inst_len;
8219 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8221 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8223 if (vcpu->arch.exception.has_error_code) {
8224 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8225 vmcs12->idt_vectoring_error_code =
8226 vcpu->arch.exception.error_code;
8229 vmcs12->idt_vectoring_info_field = idt_vectoring;
8230 } else if (vcpu->arch.nmi_injected) {
8231 vmcs12->idt_vectoring_info_field =
8232 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8233 } else if (vcpu->arch.interrupt.pending) {
8234 nr = vcpu->arch.interrupt.nr;
8235 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8237 if (vcpu->arch.interrupt.soft) {
8238 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8239 vmcs12->vm_entry_instruction_len =
8240 vcpu->arch.event_exit_inst_len;
8242 idt_vectoring |= INTR_TYPE_EXT_INTR;
8244 vmcs12->idt_vectoring_info_field = idt_vectoring;
8248 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8250 struct vcpu_vmx *vmx = to_vmx(vcpu);
8252 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8253 vmx->nested.preemption_timer_expired) {
8254 if (vmx->nested.nested_run_pending)
8256 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8260 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8261 if (vmx->nested.nested_run_pending ||
8262 vcpu->arch.interrupt.pending)
8264 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8265 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8266 INTR_INFO_VALID_MASK, 0);
8268 * The NMI-triggered VM exit counts as injection:
8269 * clear this one and block further NMIs.
8271 vcpu->arch.nmi_pending = 0;
8272 vmx_set_nmi_mask(vcpu, true);
8276 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8277 nested_exit_on_intr(vcpu)) {
8278 if (vmx->nested.nested_run_pending)
8280 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8286 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8289 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8292 if (ktime_to_ns(remaining) <= 0)
8295 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8296 do_div(value, 1000000);
8297 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8301 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8302 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8303 * and this function updates it to reflect the changes to the guest state while
8304 * L2 was running (and perhaps made some exits which were handled directly by L0
8305 * without going back to L1), and to reflect the exit reason.
8306 * Note that we do not have to copy here all VMCS fields, just those that
8307 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8308 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8309 * which already writes to vmcs12 directly.
8311 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8312 u32 exit_reason, u32 exit_intr_info,
8313 unsigned long exit_qualification)
8315 /* update guest state fields: */
8316 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8317 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8319 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8320 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8321 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8322 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8324 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8325 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8326 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8327 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8328 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8329 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8330 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8331 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8332 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8333 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8334 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8335 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8336 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8337 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8338 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8339 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8340 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8341 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8342 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8343 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8344 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8345 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8346 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8347 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8348 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8349 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8350 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8351 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8352 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8353 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8354 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8355 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8356 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8357 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8358 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8359 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8361 vmcs12->guest_interruptibility_info =
8362 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8363 vmcs12->guest_pending_dbg_exceptions =
8364 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8365 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8366 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8368 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8370 if (nested_cpu_has_preemption_timer(vmcs12)) {
8371 if (vmcs12->vm_exit_controls &
8372 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8373 vmcs12->vmx_preemption_timer_value =
8374 vmx_get_preemption_timer_value(vcpu);
8375 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8379 * In some cases (usually, nested EPT), L2 is allowed to change its
8380 * own CR3 without exiting. If it has changed it, we must keep it.
8381 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8382 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8384 * Additionally, restore L2's PDPTR to vmcs12.
8387 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8388 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8389 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8390 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8391 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8394 vmcs12->vm_entry_controls =
8395 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8396 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8398 /* TODO: These cannot have changed unless we have MSR bitmaps and
8399 * the relevant bit asks not to trap the change */
8400 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8401 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8402 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8403 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8404 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8405 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8406 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8407 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8408 if (vmx_mpx_supported())
8409 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8411 /* update exit information fields: */
8413 vmcs12->vm_exit_reason = exit_reason;
8414 vmcs12->exit_qualification = exit_qualification;
8416 vmcs12->vm_exit_intr_info = exit_intr_info;
8417 if ((vmcs12->vm_exit_intr_info &
8418 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8419 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8420 vmcs12->vm_exit_intr_error_code =
8421 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8422 vmcs12->idt_vectoring_info_field = 0;
8423 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8424 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8426 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8427 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8428 * instead of reading the real value. */
8429 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8432 * Transfer the event that L0 or L1 may wanted to inject into
8433 * L2 to IDT_VECTORING_INFO_FIELD.
8435 vmcs12_save_pending_event(vcpu, vmcs12);
8439 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8440 * preserved above and would only end up incorrectly in L1.
8442 vcpu->arch.nmi_injected = false;
8443 kvm_clear_exception_queue(vcpu);
8444 kvm_clear_interrupt_queue(vcpu);
8448 * A part of what we need to when the nested L2 guest exits and we want to
8449 * run its L1 parent, is to reset L1's guest state to the host state specified
8451 * This function is to be called not only on normal nested exit, but also on
8452 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8453 * Failures During or After Loading Guest State").
8454 * This function should be called when the active VMCS is L1's (vmcs01).
8456 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8457 struct vmcs12 *vmcs12)
8459 struct kvm_segment seg;
8461 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8462 vcpu->arch.efer = vmcs12->host_ia32_efer;
8463 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8464 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8466 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8467 vmx_set_efer(vcpu, vcpu->arch.efer);
8469 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8470 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8471 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8473 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8474 * actually changed, because it depends on the current state of
8475 * fpu_active (which may have changed).
8476 * Note that vmx_set_cr0 refers to efer set above.
8478 vmx_set_cr0(vcpu, vmcs12->host_cr0);
8480 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8481 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8482 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8484 update_exception_bitmap(vcpu);
8485 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8486 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8489 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8490 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8492 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8493 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8495 nested_ept_uninit_mmu_context(vcpu);
8497 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8498 kvm_mmu_reset_context(vcpu);
8501 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8505 * Trivially support vpid by letting L2s share their parent
8506 * L1's vpid. TODO: move to a more elaborate solution, giving
8507 * each L2 its own vpid and exposing the vpid feature to L1.
8509 vmx_flush_tlb(vcpu);
8513 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8514 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8515 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8516 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8517 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8519 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8520 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8521 vmcs_write64(GUEST_BNDCFGS, 0);
8523 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8524 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8525 vcpu->arch.pat = vmcs12->host_ia32_pat;
8527 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8528 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8529 vmcs12->host_ia32_perf_global_ctrl);
8531 /* Set L1 segment info according to Intel SDM
8532 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8533 seg = (struct kvm_segment) {
8535 .limit = 0xFFFFFFFF,
8536 .selector = vmcs12->host_cs_selector,
8542 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8546 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8547 seg = (struct kvm_segment) {
8549 .limit = 0xFFFFFFFF,
8556 seg.selector = vmcs12->host_ds_selector;
8557 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8558 seg.selector = vmcs12->host_es_selector;
8559 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8560 seg.selector = vmcs12->host_ss_selector;
8561 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8562 seg.selector = vmcs12->host_fs_selector;
8563 seg.base = vmcs12->host_fs_base;
8564 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8565 seg.selector = vmcs12->host_gs_selector;
8566 seg.base = vmcs12->host_gs_base;
8567 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8568 seg = (struct kvm_segment) {
8569 .base = vmcs12->host_tr_base,
8571 .selector = vmcs12->host_tr_selector,
8575 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8577 kvm_set_dr(vcpu, 7, 0x400);
8578 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8582 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8583 * and modify vmcs12 to make it see what it would expect to see there if
8584 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8586 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8588 unsigned long exit_qualification)
8590 struct vcpu_vmx *vmx = to_vmx(vcpu);
8592 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8594 /* trying to cancel vmlaunch/vmresume is a bug */
8595 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8597 leave_guest_mode(vcpu);
8598 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8599 exit_qualification);
8601 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8602 vmcs12->exit_qualification,
8603 vmcs12->idt_vectoring_info_field,
8604 vmcs12->vm_exit_intr_info,
8605 vmcs12->vm_exit_intr_error_code,
8609 vmx->loaded_vmcs = &vmx->vmcs01;
8611 vmx_vcpu_load(vcpu, cpu);
8615 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8616 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8617 vmx_segment_cache_clear(vmx);
8619 /* if no vmcs02 cache requested, remove the one we used */
8620 if (VMCS02_POOL_SIZE == 0)
8621 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8623 load_vmcs12_host_state(vcpu, vmcs12);
8625 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8626 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8628 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8631 /* Unpin physical memory we referred to in vmcs02 */
8632 if (vmx->nested.apic_access_page) {
8633 nested_release_page(vmx->nested.apic_access_page);
8634 vmx->nested.apic_access_page = 0;
8638 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8639 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8640 * success or failure flag accordingly.
8642 if (unlikely(vmx->fail)) {
8644 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8646 nested_vmx_succeed(vcpu);
8647 if (enable_shadow_vmcs)
8648 vmx->nested.sync_shadow_vmcs = true;
8650 /* in case we halted in L2 */
8651 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8655 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8657 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8659 if (is_guest_mode(vcpu))
8660 nested_vmx_vmexit(vcpu, -1, 0, 0);
8661 free_nested(to_vmx(vcpu));
8665 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8666 * 23.7 "VM-entry failures during or after loading guest state" (this also
8667 * lists the acceptable exit-reason and exit-qualification parameters).
8668 * It should only be called before L2 actually succeeded to run, and when
8669 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8671 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8672 struct vmcs12 *vmcs12,
8673 u32 reason, unsigned long qualification)
8675 load_vmcs12_host_state(vcpu, vmcs12);
8676 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8677 vmcs12->exit_qualification = qualification;
8678 nested_vmx_succeed(vcpu);
8679 if (enable_shadow_vmcs)
8680 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8683 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8684 struct x86_instruction_info *info,
8685 enum x86_intercept_stage stage)
8687 return X86EMUL_CONTINUE;
8690 static struct kvm_x86_ops vmx_x86_ops = {
8691 .cpu_has_kvm_support = cpu_has_kvm_support,
8692 .disabled_by_bios = vmx_disabled_by_bios,
8693 .hardware_setup = hardware_setup,
8694 .hardware_unsetup = hardware_unsetup,
8695 .check_processor_compatibility = vmx_check_processor_compat,
8696 .hardware_enable = hardware_enable,
8697 .hardware_disable = hardware_disable,
8698 .cpu_has_accelerated_tpr = report_flexpriority,
8700 .vcpu_create = vmx_create_vcpu,
8701 .vcpu_free = vmx_free_vcpu,
8702 .vcpu_reset = vmx_vcpu_reset,
8704 .prepare_guest_switch = vmx_save_host_state,
8705 .vcpu_load = vmx_vcpu_load,
8706 .vcpu_put = vmx_vcpu_put,
8708 .update_db_bp_intercept = update_exception_bitmap,
8709 .get_msr = vmx_get_msr,
8710 .set_msr = vmx_set_msr,
8711 .get_segment_base = vmx_get_segment_base,
8712 .get_segment = vmx_get_segment,
8713 .set_segment = vmx_set_segment,
8714 .get_cpl = vmx_get_cpl,
8715 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8716 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8717 .decache_cr3 = vmx_decache_cr3,
8718 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8719 .set_cr0 = vmx_set_cr0,
8720 .set_cr3 = vmx_set_cr3,
8721 .set_cr4 = vmx_set_cr4,
8722 .set_efer = vmx_set_efer,
8723 .get_idt = vmx_get_idt,
8724 .set_idt = vmx_set_idt,
8725 .get_gdt = vmx_get_gdt,
8726 .set_gdt = vmx_set_gdt,
8727 .get_dr6 = vmx_get_dr6,
8728 .set_dr6 = vmx_set_dr6,
8729 .set_dr7 = vmx_set_dr7,
8730 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8731 .cache_reg = vmx_cache_reg,
8732 .get_rflags = vmx_get_rflags,
8733 .set_rflags = vmx_set_rflags,
8734 .fpu_activate = vmx_fpu_activate,
8735 .fpu_deactivate = vmx_fpu_deactivate,
8737 .tlb_flush = vmx_flush_tlb,
8739 .run = vmx_vcpu_run,
8740 .handle_exit = vmx_handle_exit,
8741 .skip_emulated_instruction = skip_emulated_instruction,
8742 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8743 .get_interrupt_shadow = vmx_get_interrupt_shadow,
8744 .patch_hypercall = vmx_patch_hypercall,
8745 .set_irq = vmx_inject_irq,
8746 .set_nmi = vmx_inject_nmi,
8747 .queue_exception = vmx_queue_exception,
8748 .cancel_injection = vmx_cancel_injection,
8749 .interrupt_allowed = vmx_interrupt_allowed,
8750 .nmi_allowed = vmx_nmi_allowed,
8751 .get_nmi_mask = vmx_get_nmi_mask,
8752 .set_nmi_mask = vmx_set_nmi_mask,
8753 .enable_nmi_window = enable_nmi_window,
8754 .enable_irq_window = enable_irq_window,
8755 .update_cr8_intercept = update_cr8_intercept,
8756 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8757 .vm_has_apicv = vmx_vm_has_apicv,
8758 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8759 .hwapic_irr_update = vmx_hwapic_irr_update,
8760 .hwapic_isr_update = vmx_hwapic_isr_update,
8761 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8762 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8764 .set_tss_addr = vmx_set_tss_addr,
8765 .get_tdp_level = get_ept_level,
8766 .get_mt_mask = vmx_get_mt_mask,
8768 .get_exit_info = vmx_get_exit_info,
8770 .get_lpage_level = vmx_get_lpage_level,
8772 .cpuid_update = vmx_cpuid_update,
8774 .rdtscp_supported = vmx_rdtscp_supported,
8775 .invpcid_supported = vmx_invpcid_supported,
8777 .set_supported_cpuid = vmx_set_supported_cpuid,
8779 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8781 .set_tsc_khz = vmx_set_tsc_khz,
8782 .read_tsc_offset = vmx_read_tsc_offset,
8783 .write_tsc_offset = vmx_write_tsc_offset,
8784 .adjust_tsc_offset = vmx_adjust_tsc_offset,
8785 .compute_tsc_offset = vmx_compute_tsc_offset,
8786 .read_l1_tsc = vmx_read_l1_tsc,
8788 .set_tdp_cr3 = vmx_set_cr3,
8790 .check_intercept = vmx_check_intercept,
8791 .handle_external_intr = vmx_handle_external_intr,
8792 .mpx_supported = vmx_mpx_supported,
8794 .check_nested_events = vmx_check_nested_events,
8797 static int __init vmx_init(void)
8801 rdmsrl_safe(MSR_EFER, &host_efer);
8803 for (i = 0; i < NR_VMX_MSR; ++i)
8804 kvm_define_shared_msr(i, vmx_msr_index[i]);
8806 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8807 if (!vmx_io_bitmap_a)
8812 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8813 if (!vmx_io_bitmap_b)
8816 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8817 if (!vmx_msr_bitmap_legacy)
8820 vmx_msr_bitmap_legacy_x2apic =
8821 (unsigned long *)__get_free_page(GFP_KERNEL);
8822 if (!vmx_msr_bitmap_legacy_x2apic)
8825 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8826 if (!vmx_msr_bitmap_longmode)
8829 vmx_msr_bitmap_longmode_x2apic =
8830 (unsigned long *)__get_free_page(GFP_KERNEL);
8831 if (!vmx_msr_bitmap_longmode_x2apic)
8833 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8834 if (!vmx_vmread_bitmap)
8837 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8838 if (!vmx_vmwrite_bitmap)
8841 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8842 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8845 * Allow direct access to the PC debug port (it is often used for I/O
8846 * delays, but the vmexits simply slow things down).
8848 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8849 clear_bit(0x80, vmx_io_bitmap_a);
8851 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8853 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8854 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8856 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8858 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8859 __alignof__(struct vcpu_vmx), THIS_MODULE);
8864 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8865 crash_vmclear_local_loaded_vmcss);
8868 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8869 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8870 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8871 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8872 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8873 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8874 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8876 memcpy(vmx_msr_bitmap_legacy_x2apic,
8877 vmx_msr_bitmap_legacy, PAGE_SIZE);
8878 memcpy(vmx_msr_bitmap_longmode_x2apic,
8879 vmx_msr_bitmap_longmode, PAGE_SIZE);
8882 for (msr = 0x800; msr <= 0x8ff; msr++)
8883 vmx_disable_intercept_msr_read_x2apic(msr);
8885 /* According SDM, in x2apic mode, the whole id reg is used.
8886 * But in KVM, it only use the highest eight bits. Need to
8888 vmx_enable_intercept_msr_read_x2apic(0x802);
8890 vmx_enable_intercept_msr_read_x2apic(0x839);
8892 vmx_disable_intercept_msr_write_x2apic(0x808);
8894 vmx_disable_intercept_msr_write_x2apic(0x80b);
8896 vmx_disable_intercept_msr_write_x2apic(0x83f);
8900 kvm_mmu_set_mask_ptes(0ull,
8901 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8902 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8903 0ull, VMX_EPT_EXECUTABLE_MASK);
8904 ept_set_mmio_spte_mask();
8912 free_page((unsigned long)vmx_vmwrite_bitmap);
8914 free_page((unsigned long)vmx_vmread_bitmap);
8916 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8918 free_page((unsigned long)vmx_msr_bitmap_longmode);
8920 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8922 free_page((unsigned long)vmx_msr_bitmap_legacy);
8924 free_page((unsigned long)vmx_io_bitmap_b);
8926 free_page((unsigned long)vmx_io_bitmap_a);
8930 static void __exit vmx_exit(void)
8932 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8933 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8934 free_page((unsigned long)vmx_msr_bitmap_legacy);
8935 free_page((unsigned long)vmx_msr_bitmap_longmode);
8936 free_page((unsigned long)vmx_io_bitmap_b);
8937 free_page((unsigned long)vmx_io_bitmap_a);
8938 free_page((unsigned long)vmx_vmwrite_bitmap);
8939 free_page((unsigned long)vmx_vmread_bitmap);
8942 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8949 module_init(vmx_init)
8950 module_exit(vmx_exit)