arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_ept(void)
1243 {
1244         return vmcs_config.cpu_based_2nd_exec_ctrl &
1245                 SECONDARY_EXEC_ENABLE_EPT;
1246 }
1247
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1249 {
1250         return vmcs_config.cpu_based_2nd_exec_ctrl &
1251                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252 }
1253
1254 static inline bool cpu_has_vmx_ple(void)
1255 {
1256         return vmcs_config.cpu_based_2nd_exec_ctrl &
1257                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258 }
1259
1260 static inline bool cpu_has_vmx_basic_inout(void)
1261 {
1262         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263 }
1264
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1266 {
1267         return flexpriority_enabled && lapic_in_kernel(vcpu);
1268 }
1269
1270 static inline bool cpu_has_vmx_vpid(void)
1271 {
1272         return vmcs_config.cpu_based_2nd_exec_ctrl &
1273                 SECONDARY_EXEC_ENABLE_VPID;
1274 }
1275
1276 static inline bool cpu_has_vmx_rdtscp(void)
1277 {
1278         return vmcs_config.cpu_based_2nd_exec_ctrl &
1279                 SECONDARY_EXEC_RDTSCP;
1280 }
1281
1282 static inline bool cpu_has_vmx_invpcid(void)
1283 {
1284         return vmcs_config.cpu_based_2nd_exec_ctrl &
1285                 SECONDARY_EXEC_ENABLE_INVPCID;
1286 }
1287
1288 static inline bool cpu_has_virtual_nmis(void)
1289 {
1290         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1291 }
1292
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl &
1296                 SECONDARY_EXEC_WBINVD_EXITING;
1297 }
1298
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 {
1301         u64 vmx_msr;
1302         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303         /* check if the cpu supports writing r/o exit information fields */
1304         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1305                 return false;
1306
1307         return vmcs_config.cpu_based_2nd_exec_ctrl &
1308                 SECONDARY_EXEC_SHADOW_VMCS;
1309 }
1310
1311 static inline bool cpu_has_vmx_pml(void)
1312 {
1313         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1314 }
1315
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl &
1319                 SECONDARY_EXEC_TSC_SCALING;
1320 }
1321
1322 static inline bool report_flexpriority(void)
1323 {
1324         return flexpriority_enabled;
1325 }
1326
1327 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328 {
1329         return vmcs12->cpu_based_vm_exec_control & bit;
1330 }
1331
1332 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return (vmcs12->cpu_based_vm_exec_control &
1335                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336                 (vmcs12->secondary_vm_exec_control & bit);
1337 }
1338
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1340 {
1341         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342 }
1343
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control &
1347                 PIN_BASED_VMX_PREEMPTION_TIMER;
1348 }
1349
1350 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351 {
1352         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353 }
1354
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358                 vmx_xsaves_supported();
1359 }
1360
1361 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1362 {
1363         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1364 }
1365
1366 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1369 }
1370
1371 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1374 }
1375
1376 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1379 }
1380
1381 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1382 {
1383         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1384 }
1385
1386 static inline bool is_nmi(u32 intr_info)
1387 {
1388         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1389                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1390 }
1391
1392 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1393                               u32 exit_intr_info,
1394                               unsigned long exit_qualification);
1395 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1396                         struct vmcs12 *vmcs12,
1397                         u32 reason, unsigned long qualification);
1398
1399 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1400 {
1401         int i;
1402
1403         for (i = 0; i < vmx->nmsrs; ++i)
1404                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1405                         return i;
1406         return -1;
1407 }
1408
1409 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1410 {
1411     struct {
1412         u64 vpid : 16;
1413         u64 rsvd : 48;
1414         u64 gva;
1415     } operand = { vpid, 0, gva };
1416
1417     asm volatile (__ex(ASM_VMX_INVVPID)
1418                   /* CF==1 or ZF==1 --> rc = -1 */
1419                   "; ja 1f ; ud2 ; 1:"
1420                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1421 }
1422
1423 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1424 {
1425         struct {
1426                 u64 eptp, gpa;
1427         } operand = {eptp, gpa};
1428
1429         asm volatile (__ex(ASM_VMX_INVEPT)
1430                         /* CF==1 or ZF==1 --> rc = -1 */
1431                         "; ja 1f ; ud2 ; 1:\n"
1432                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1433 }
1434
1435 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1436 {
1437         int i;
1438
1439         i = __find_msr_index(vmx, msr);
1440         if (i >= 0)
1441                 return &vmx->guest_msrs[i];
1442         return NULL;
1443 }
1444
1445 static void vmcs_clear(struct vmcs *vmcs)
1446 {
1447         u64 phys_addr = __pa(vmcs);
1448         u8 error;
1449
1450         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1451                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1452                       : "cc", "memory");
1453         if (error)
1454                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1455                        vmcs, phys_addr);
1456 }
1457
1458 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1459 {
1460         vmcs_clear(loaded_vmcs->vmcs);
1461         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1462                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1463         loaded_vmcs->cpu = -1;
1464         loaded_vmcs->launched = 0;
1465 }
1466
1467 static void vmcs_load(struct vmcs *vmcs)
1468 {
1469         u64 phys_addr = __pa(vmcs);
1470         u8 error;
1471
1472         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1473                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1474                         : "cc", "memory");
1475         if (error)
1476                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1477                        vmcs, phys_addr);
1478 }
1479
1480 #ifdef CONFIG_KEXEC_CORE
1481 /*
1482  * This bitmap is used to indicate whether the vmclear
1483  * operation is enabled on all cpus. All disabled by
1484  * default.
1485  */
1486 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1487
1488 static inline void crash_enable_local_vmclear(int cpu)
1489 {
1490         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1491 }
1492
1493 static inline void crash_disable_local_vmclear(int cpu)
1494 {
1495         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline int crash_local_vmclear_enabled(int cpu)
1499 {
1500         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static void crash_vmclear_local_loaded_vmcss(void)
1504 {
1505         int cpu = raw_smp_processor_id();
1506         struct loaded_vmcs *v;
1507
1508         if (!crash_local_vmclear_enabled(cpu))
1509                 return;
1510
1511         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1512                             loaded_vmcss_on_cpu_link)
1513                 vmcs_clear(v->vmcs);
1514 }
1515 #else
1516 static inline void crash_enable_local_vmclear(int cpu) { }
1517 static inline void crash_disable_local_vmclear(int cpu) { }
1518 #endif /* CONFIG_KEXEC_CORE */
1519
1520 static void __loaded_vmcs_clear(void *arg)
1521 {
1522         struct loaded_vmcs *loaded_vmcs = arg;
1523         int cpu = raw_smp_processor_id();
1524
1525         if (loaded_vmcs->cpu != cpu)
1526                 return; /* vcpu migration can race with cpu offline */
1527         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1528                 per_cpu(current_vmcs, cpu) = NULL;
1529         crash_disable_local_vmclear(cpu);
1530         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1531
1532         /*
1533          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534          * is before setting loaded_vmcs->vcpu to -1 which is done in
1535          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536          * then adds the vmcs into percpu list before it is deleted.
1537          */
1538         smp_wmb();
1539
1540         loaded_vmcs_init(loaded_vmcs);
1541         crash_enable_local_vmclear(cpu);
1542 }
1543
1544 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1545 {
1546         int cpu = loaded_vmcs->cpu;
1547
1548         if (cpu != -1)
1549                 smp_call_function_single(cpu,
1550                          __loaded_vmcs_clear, loaded_vmcs, 1);
1551 }
1552
1553 static inline void vpid_sync_vcpu_single(int vpid)
1554 {
1555         if (vpid == 0)
1556                 return;
1557
1558         if (cpu_has_vmx_invvpid_single())
1559                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1560 }
1561
1562 static inline void vpid_sync_vcpu_global(void)
1563 {
1564         if (cpu_has_vmx_invvpid_global())
1565                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1566 }
1567
1568 static inline void vpid_sync_context(int vpid)
1569 {
1570         if (cpu_has_vmx_invvpid_single())
1571                 vpid_sync_vcpu_single(vpid);
1572         else
1573                 vpid_sync_vcpu_global();
1574 }
1575
1576 static inline void ept_sync_global(void)
1577 {
1578         if (cpu_has_vmx_invept_global())
1579                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1580 }
1581
1582 static inline void ept_sync_context(u64 eptp)
1583 {
1584         if (enable_ept) {
1585                 if (cpu_has_vmx_invept_context())
1586                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1587                 else
1588                         ept_sync_global();
1589         }
1590 }
1591
1592 static __always_inline void vmcs_check16(unsigned long field)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595                          "16-bit accessor invalid for 64-bit field");
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597                          "16-bit accessor invalid for 64-bit high field");
1598         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599                          "16-bit accessor invalid for 32-bit high field");
1600         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601                          "16-bit accessor invalid for natural width field");
1602 }
1603
1604 static __always_inline void vmcs_check32(unsigned long field)
1605 {
1606         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607                          "32-bit accessor invalid for 16-bit field");
1608         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609                          "32-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check64(unsigned long field)
1613 {
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615                          "64-bit accessor invalid for 16-bit field");
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617                          "64-bit accessor invalid for 64-bit high field");
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619                          "64-bit accessor invalid for 32-bit field");
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621                          "64-bit accessor invalid for natural width field");
1622 }
1623
1624 static __always_inline void vmcs_checkl(unsigned long field)
1625 {
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627                          "Natural width accessor invalid for 16-bit field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629                          "Natural width accessor invalid for 64-bit field");
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631                          "Natural width accessor invalid for 64-bit high field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633                          "Natural width accessor invalid for 32-bit field");
1634 }
1635
1636 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1637 {
1638         unsigned long value;
1639
1640         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641                       : "=a"(value) : "d"(field) : "cc");
1642         return value;
1643 }
1644
1645 static __always_inline u16 vmcs_read16(unsigned long field)
1646 {
1647         vmcs_check16(field);
1648         return __vmcs_readl(field);
1649 }
1650
1651 static __always_inline u32 vmcs_read32(unsigned long field)
1652 {
1653         vmcs_check32(field);
1654         return __vmcs_readl(field);
1655 }
1656
1657 static __always_inline u64 vmcs_read64(unsigned long field)
1658 {
1659         vmcs_check64(field);
1660 #ifdef CONFIG_X86_64
1661         return __vmcs_readl(field);
1662 #else
1663         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1664 #endif
1665 }
1666
1667 static __always_inline unsigned long vmcs_readl(unsigned long field)
1668 {
1669         vmcs_checkl(field);
1670         return __vmcs_readl(field);
1671 }
1672
1673 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1674 {
1675         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1677         dump_stack();
1678 }
1679
1680 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1681 {
1682         u8 error;
1683
1684         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1685                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1686         if (unlikely(error))
1687                 vmwrite_error(field, value);
1688 }
1689
1690 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1691 {
1692         vmcs_check16(field);
1693         __vmcs_writel(field, value);
1694 }
1695
1696 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1697 {
1698         vmcs_check32(field);
1699         __vmcs_writel(field, value);
1700 }
1701
1702 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1703 {
1704         vmcs_check64(field);
1705         __vmcs_writel(field, value);
1706 #ifndef CONFIG_X86_64
1707         asm volatile ("");
1708         __vmcs_writel(field+1, value >> 32);
1709 #endif
1710 }
1711
1712 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1713 {
1714         vmcs_checkl(field);
1715         __vmcs_writel(field, value);
1716 }
1717
1718 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1719 {
1720         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721                          "vmcs_clear_bits does not support 64-bit fields");
1722         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1723 }
1724
1725 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1726 {
1727         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728                          "vmcs_set_bits does not support 64-bit fields");
1729         __vmcs_writel(field, __vmcs_readl(field) | mask);
1730 }
1731
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1733 {
1734         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1735 }
1736
1737 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1738 {
1739         vmcs_write32(VM_ENTRY_CONTROLS, val);
1740         vmx->vm_entry_controls_shadow = val;
1741 }
1742
1743 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1744 {
1745         if (vmx->vm_entry_controls_shadow != val)
1746                 vm_entry_controls_init(vmx, val);
1747 }
1748
1749 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1750 {
1751         return vmx->vm_entry_controls_shadow;
1752 }
1753
1754
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1756 {
1757         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1758 }
1759
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1763 }
1764
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1766 {
1767         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1768 }
1769
1770 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1771 {
1772         vmcs_write32(VM_EXIT_CONTROLS, val);
1773         vmx->vm_exit_controls_shadow = val;
1774 }
1775
1776 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1777 {
1778         if (vmx->vm_exit_controls_shadow != val)
1779                 vm_exit_controls_init(vmx, val);
1780 }
1781
1782 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1783 {
1784         return vmx->vm_exit_controls_shadow;
1785 }
1786
1787
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1789 {
1790         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1791 }
1792
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1796 }
1797
1798 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1799 {
1800         vmx->segment_cache.bitmask = 0;
1801 }
1802
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1804                                        unsigned field)
1805 {
1806         bool ret;
1807         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1808
1809         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811                 vmx->segment_cache.bitmask = 0;
1812         }
1813         ret = vmx->segment_cache.bitmask & mask;
1814         vmx->segment_cache.bitmask |= mask;
1815         return ret;
1816 }
1817
1818 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1819 {
1820         u16 *p = &vmx->segment_cache.seg[seg].selector;
1821
1822         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1824         return *p;
1825 }
1826
1827 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         ulong *p = &vmx->segment_cache.seg[seg].base;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1833         return *p;
1834 }
1835
1836 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         u32 *p = &vmx->segment_cache.seg[seg].limit;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].ar;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1851         return *p;
1852 }
1853
1854 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1855 {
1856         u32 eb;
1857
1858         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1859              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1860         if ((vcpu->guest_debug &
1861              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863                 eb |= 1u << BP_VECTOR;
1864         if (to_vmx(vcpu)->rmode.vm86_active)
1865                 eb = ~0;
1866         if (enable_ept)
1867                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1868
1869         /* When we are running a nested L2 guest and L1 specified for it a
1870          * certain exception bitmap, we must trap the same exceptions and pass
1871          * them to L1. When running L2, we will only handle the exceptions
1872          * specified above if L1 did not want them.
1873          */
1874         if (is_guest_mode(vcpu))
1875                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1876
1877         vmcs_write32(EXCEPTION_BITMAP, eb);
1878 }
1879
1880 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1881                 unsigned long entry, unsigned long exit)
1882 {
1883         vm_entry_controls_clearbit(vmx, entry);
1884         vm_exit_controls_clearbit(vmx, exit);
1885 }
1886
1887 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1888 {
1889         unsigned i;
1890         struct msr_autoload *m = &vmx->msr_autoload;
1891
1892         switch (msr) {
1893         case MSR_EFER:
1894                 if (cpu_has_load_ia32_efer) {
1895                         clear_atomic_switch_msr_special(vmx,
1896                                         VM_ENTRY_LOAD_IA32_EFER,
1897                                         VM_EXIT_LOAD_IA32_EFER);
1898                         return;
1899                 }
1900                 break;
1901         case MSR_CORE_PERF_GLOBAL_CTRL:
1902                 if (cpu_has_load_perf_global_ctrl) {
1903                         clear_atomic_switch_msr_special(vmx,
1904                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1905                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1906                         return;
1907                 }
1908                 break;
1909         }
1910
1911         for (i = 0; i < m->nr; ++i)
1912                 if (m->guest[i].index == msr)
1913                         break;
1914
1915         if (i == m->nr)
1916                 return;
1917         --m->nr;
1918         m->guest[i] = m->guest[m->nr];
1919         m->host[i] = m->host[m->nr];
1920         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1921         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1922 }
1923
1924 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1925                 unsigned long entry, unsigned long exit,
1926                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1927                 u64 guest_val, u64 host_val)
1928 {
1929         vmcs_write64(guest_val_vmcs, guest_val);
1930         vmcs_write64(host_val_vmcs, host_val);
1931         vm_entry_controls_setbit(vmx, entry);
1932         vm_exit_controls_setbit(vmx, exit);
1933 }
1934
1935 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1936                                   u64 guest_val, u64 host_val)
1937 {
1938         unsigned i;
1939         struct msr_autoload *m = &vmx->msr_autoload;
1940
1941         switch (msr) {
1942         case MSR_EFER:
1943                 if (cpu_has_load_ia32_efer) {
1944                         add_atomic_switch_msr_special(vmx,
1945                                         VM_ENTRY_LOAD_IA32_EFER,
1946                                         VM_EXIT_LOAD_IA32_EFER,
1947                                         GUEST_IA32_EFER,
1948                                         HOST_IA32_EFER,
1949                                         guest_val, host_val);
1950                         return;
1951                 }
1952                 break;
1953         case MSR_CORE_PERF_GLOBAL_CTRL:
1954                 if (cpu_has_load_perf_global_ctrl) {
1955                         add_atomic_switch_msr_special(vmx,
1956                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1957                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1958                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1959                                         HOST_IA32_PERF_GLOBAL_CTRL,
1960                                         guest_val, host_val);
1961                         return;
1962                 }
1963                 break;
1964         case MSR_IA32_PEBS_ENABLE:
1965                 /* PEBS needs a quiescent period after being disabled (to write
1966                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1967                  * provide that period, so a CPU could write host's record into
1968                  * guest's memory.
1969                  */
1970                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1971         }
1972
1973         for (i = 0; i < m->nr; ++i)
1974                 if (m->guest[i].index == msr)
1975                         break;
1976
1977         if (i == NR_AUTOLOAD_MSRS) {
1978                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1979                                 "Can't add msr %x\n", msr);
1980                 return;
1981         } else if (i == m->nr) {
1982                 ++m->nr;
1983                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1984                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1985         }
1986
1987         m->guest[i].index = msr;
1988         m->guest[i].value = guest_val;
1989         m->host[i].index = msr;
1990         m->host[i].value = host_val;
1991 }
1992
1993 static void reload_tss(void)
1994 {
1995         /*
1996          * VT restores TR but not its size.  Useless.
1997          */
1998         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1999         struct desc_struct *descs;
2000
2001         descs = (void *)gdt->address;
2002         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
2003         load_TR_desc();
2004 }
2005
2006 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2007 {
2008         u64 guest_efer = vmx->vcpu.arch.efer;
2009         u64 ignore_bits = 0;
2010
2011         if (!enable_ept) {
2012                 /*
2013                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2014                  * host CPUID is more efficient than testing guest CPUID
2015                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2016                  */
2017                 if (boot_cpu_has(X86_FEATURE_SMEP))
2018                         guest_efer |= EFER_NX;
2019                 else if (!(guest_efer & EFER_NX))
2020                         ignore_bits |= EFER_NX;
2021         }
2022
2023         /*
2024          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2025          */
2026         ignore_bits |= EFER_SCE;
2027 #ifdef CONFIG_X86_64
2028         ignore_bits |= EFER_LMA | EFER_LME;
2029         /* SCE is meaningful only in long mode on Intel */
2030         if (guest_efer & EFER_LMA)
2031                 ignore_bits &= ~(u64)EFER_SCE;
2032 #endif
2033
2034         clear_atomic_switch_msr(vmx, MSR_EFER);
2035
2036         /*
2037          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2038          * On CPUs that support "load IA32_EFER", always switch EFER
2039          * atomically, since it's faster than switching it manually.
2040          */
2041         if (cpu_has_load_ia32_efer ||
2042             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2043                 if (!(guest_efer & EFER_LMA))
2044                         guest_efer &= ~EFER_LME;
2045                 if (guest_efer != host_efer)
2046                         add_atomic_switch_msr(vmx, MSR_EFER,
2047                                               guest_efer, host_efer);
2048                 return false;
2049         } else {
2050                 guest_efer &= ~ignore_bits;
2051                 guest_efer |= host_efer & ignore_bits;
2052
2053                 vmx->guest_msrs[efer_offset].data = guest_efer;
2054                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2055
2056                 return true;
2057         }
2058 }
2059
2060 static unsigned long segment_base(u16 selector)
2061 {
2062         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2063         struct desc_struct *d;
2064         unsigned long table_base;
2065         unsigned long v;
2066
2067         if (!(selector & ~3))
2068                 return 0;
2069
2070         table_base = gdt->address;
2071
2072         if (selector & 4) {           /* from ldt */
2073                 u16 ldt_selector = kvm_read_ldt();
2074
2075                 if (!(ldt_selector & ~3))
2076                         return 0;
2077
2078                 table_base = segment_base(ldt_selector);
2079         }
2080         d = (struct desc_struct *)(table_base + (selector & ~7));
2081         v = get_desc_base(d);
2082 #ifdef CONFIG_X86_64
2083        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2084                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2085 #endif
2086         return v;
2087 }
2088
2089 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2090 {
2091         struct vcpu_vmx *vmx = to_vmx(vcpu);
2092         int i;
2093
2094         if (vmx->host_state.loaded)
2095                 return;
2096
2097         vmx->host_state.loaded = 1;
2098         /*
2099          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2100          * allow segment selectors with cpl > 0 or ti == 1.
2101          */
2102         vmx->host_state.ldt_sel = kvm_read_ldt();
2103         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2104         savesegment(fs, vmx->host_state.fs_sel);
2105         if (!(vmx->host_state.fs_sel & 7)) {
2106                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2107                 vmx->host_state.fs_reload_needed = 0;
2108         } else {
2109                 vmcs_write16(HOST_FS_SELECTOR, 0);
2110                 vmx->host_state.fs_reload_needed = 1;
2111         }
2112         savesegment(gs, vmx->host_state.gs_sel);
2113         if (!(vmx->host_state.gs_sel & 7))
2114                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2115         else {
2116                 vmcs_write16(HOST_GS_SELECTOR, 0);
2117                 vmx->host_state.gs_ldt_reload_needed = 1;
2118         }
2119
2120 #ifdef CONFIG_X86_64
2121         savesegment(ds, vmx->host_state.ds_sel);
2122         savesegment(es, vmx->host_state.es_sel);
2123 #endif
2124
2125 #ifdef CONFIG_X86_64
2126         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2127         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2128 #else
2129         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2130         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2131 #endif
2132
2133 #ifdef CONFIG_X86_64
2134         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2135         if (is_long_mode(&vmx->vcpu))
2136                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2137 #endif
2138         if (boot_cpu_has(X86_FEATURE_MPX))
2139                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2140         for (i = 0; i < vmx->save_nmsrs; ++i)
2141                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2142                                    vmx->guest_msrs[i].data,
2143                                    vmx->guest_msrs[i].mask);
2144 }
2145
2146 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2147 {
2148         if (!vmx->host_state.loaded)
2149                 return;
2150
2151         ++vmx->vcpu.stat.host_state_reload;
2152         vmx->host_state.loaded = 0;
2153 #ifdef CONFIG_X86_64
2154         if (is_long_mode(&vmx->vcpu))
2155                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2156 #endif
2157         if (vmx->host_state.gs_ldt_reload_needed) {
2158                 kvm_load_ldt(vmx->host_state.ldt_sel);
2159 #ifdef CONFIG_X86_64
2160                 load_gs_index(vmx->host_state.gs_sel);
2161 #else
2162                 loadsegment(gs, vmx->host_state.gs_sel);
2163 #endif
2164         }
2165         if (vmx->host_state.fs_reload_needed)
2166                 loadsegment(fs, vmx->host_state.fs_sel);
2167 #ifdef CONFIG_X86_64
2168         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2169                 loadsegment(ds, vmx->host_state.ds_sel);
2170                 loadsegment(es, vmx->host_state.es_sel);
2171         }
2172 #endif
2173         reload_tss();
2174 #ifdef CONFIG_X86_64
2175         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2176 #endif
2177         if (vmx->host_state.msr_host_bndcfgs)
2178                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2179         load_gdt(this_cpu_ptr(&host_gdt));
2180 }
2181
2182 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2183 {
2184         preempt_disable();
2185         __vmx_load_host_state(vmx);
2186         preempt_enable();
2187 }
2188
2189 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2190 {
2191         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2192         struct pi_desc old, new;
2193         unsigned int dest;
2194
2195         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2196                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2197                 !kvm_vcpu_apicv_active(vcpu))
2198                 return;
2199
2200         do {
2201                 old.control = new.control = pi_desc->control;
2202
2203                 /*
2204                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2205                  * are two possible cases:
2206                  * 1. After running 'pre_block', context switch
2207                  *    happened. For this case, 'sn' was set in
2208                  *    vmx_vcpu_put(), so we need to clear it here.
2209                  * 2. After running 'pre_block', we were blocked,
2210                  *    and woken up by some other guy. For this case,
2211                  *    we don't need to do anything, 'pi_post_block'
2212                  *    will do everything for us. However, we cannot
2213                  *    check whether it is case #1 or case #2 here
2214                  *    (maybe, not needed), so we also clear sn here,
2215                  *    I think it is not a big deal.
2216                  */
2217                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2218                         if (vcpu->cpu != cpu) {
2219                                 dest = cpu_physical_id(cpu);
2220
2221                                 if (x2apic_enabled())
2222                                         new.ndst = dest;
2223                                 else
2224                                         new.ndst = (dest << 8) & 0xFF00;
2225                         }
2226
2227                         /* set 'NV' to 'notification vector' */
2228                         new.nv = POSTED_INTR_VECTOR;
2229                 }
2230
2231                 /* Allow posting non-urgent interrupts */
2232                 new.sn = 0;
2233         } while (cmpxchg(&pi_desc->control, old.control,
2234                         new.control) != old.control);
2235 }
2236
2237 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2238 {
2239         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2240         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2241 }
2242
2243 /*
2244  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2245  * vcpu mutex is already taken.
2246  */
2247 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2248 {
2249         struct vcpu_vmx *vmx = to_vmx(vcpu);
2250         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2251         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2252
2253         if (!vmm_exclusive)
2254                 kvm_cpu_vmxon(phys_addr);
2255         else if (!already_loaded)
2256                 loaded_vmcs_clear(vmx->loaded_vmcs);
2257
2258         if (!already_loaded) {
2259                 local_irq_disable();
2260                 crash_disable_local_vmclear(cpu);
2261
2262                 /*
2263                  * Read loaded_vmcs->cpu should be before fetching
2264                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2265                  * See the comments in __loaded_vmcs_clear().
2266                  */
2267                 smp_rmb();
2268
2269                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2270                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2271                 crash_enable_local_vmclear(cpu);
2272                 local_irq_enable();
2273         }
2274
2275         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2276                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2277                 vmcs_load(vmx->loaded_vmcs->vmcs);
2278         }
2279
2280         if (!already_loaded) {
2281                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2282                 unsigned long sysenter_esp;
2283
2284                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2285
2286                 /*
2287                  * Linux uses per-cpu TSS and GDT, so set these when switching
2288                  * processors.  See 22.2.4.
2289                  */
2290                 vmcs_writel(HOST_TR_BASE,
2291                             (unsigned long)this_cpu_ptr(&cpu_tss));
2292                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2293
2294                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2295                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2296
2297                 vmx->loaded_vmcs->cpu = cpu;
2298         }
2299
2300         /* Setup TSC multiplier */
2301         if (kvm_has_tsc_control &&
2302             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2303                 decache_tsc_multiplier(vmx);
2304
2305         vmx_vcpu_pi_load(vcpu, cpu);
2306         vmx->host_pkru = read_pkru();
2307 }
2308
2309 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2310 {
2311         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2312
2313         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2314                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2315                 !kvm_vcpu_apicv_active(vcpu))
2316                 return;
2317
2318         /* Set SN when the vCPU is preempted */
2319         if (vcpu->preempted)
2320                 pi_set_sn(pi_desc);
2321 }
2322
2323 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2324 {
2325         vmx_vcpu_pi_put(vcpu);
2326
2327         __vmx_load_host_state(to_vmx(vcpu));
2328         if (!vmm_exclusive) {
2329                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2330                 vcpu->cpu = -1;
2331                 kvm_cpu_vmxoff();
2332         }
2333 }
2334
2335 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2336
2337 /*
2338  * Return the cr0 value that a nested guest would read. This is a combination
2339  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2340  * its hypervisor (cr0_read_shadow).
2341  */
2342 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2343 {
2344         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2345                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2346 }
2347 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2348 {
2349         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2350                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2351 }
2352
2353 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2354 {
2355         unsigned long rflags, save_rflags;
2356
2357         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2358                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2359                 rflags = vmcs_readl(GUEST_RFLAGS);
2360                 if (to_vmx(vcpu)->rmode.vm86_active) {
2361                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2362                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2363                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2364                 }
2365                 to_vmx(vcpu)->rflags = rflags;
2366         }
2367         return to_vmx(vcpu)->rflags;
2368 }
2369
2370 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2371 {
2372         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2373         to_vmx(vcpu)->rflags = rflags;
2374         if (to_vmx(vcpu)->rmode.vm86_active) {
2375                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2376                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2377         }
2378         vmcs_writel(GUEST_RFLAGS, rflags);
2379 }
2380
2381 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2382 {
2383         return to_vmx(vcpu)->guest_pkru;
2384 }
2385
2386 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2387 {
2388         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2389         int ret = 0;
2390
2391         if (interruptibility & GUEST_INTR_STATE_STI)
2392                 ret |= KVM_X86_SHADOW_INT_STI;
2393         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2394                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2395
2396         return ret;
2397 }
2398
2399 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2400 {
2401         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2402         u32 interruptibility = interruptibility_old;
2403
2404         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2405
2406         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2407                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2408         else if (mask & KVM_X86_SHADOW_INT_STI)
2409                 interruptibility |= GUEST_INTR_STATE_STI;
2410
2411         if ((interruptibility != interruptibility_old))
2412                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2413 }
2414
2415 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2416 {
2417         unsigned long rip;
2418
2419         rip = kvm_rip_read(vcpu);
2420         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2421         kvm_rip_write(vcpu, rip);
2422
2423         /* skipping an emulated instruction also counts */
2424         vmx_set_interrupt_shadow(vcpu, 0);
2425 }
2426
2427 /*
2428  * KVM wants to inject page-faults which it got to the guest. This function
2429  * checks whether in a nested guest, we need to inject them to L1 or L2.
2430  */
2431 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2432 {
2433         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2434
2435         if (!(vmcs12->exception_bitmap & (1u << nr)))
2436                 return 0;
2437
2438         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2439                           vmcs_read32(VM_EXIT_INTR_INFO),
2440                           vmcs_readl(EXIT_QUALIFICATION));
2441         return 1;
2442 }
2443
2444 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2445                                 bool has_error_code, u32 error_code,
2446                                 bool reinject)
2447 {
2448         struct vcpu_vmx *vmx = to_vmx(vcpu);
2449         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2450
2451         if (!reinject && is_guest_mode(vcpu) &&
2452             nested_vmx_check_exception(vcpu, nr))
2453                 return;
2454
2455         if (has_error_code) {
2456                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2457                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2458         }
2459
2460         if (vmx->rmode.vm86_active) {
2461                 int inc_eip = 0;
2462                 if (kvm_exception_is_soft(nr))
2463                         inc_eip = vcpu->arch.event_exit_inst_len;
2464                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2465                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2466                 return;
2467         }
2468
2469         if (kvm_exception_is_soft(nr)) {
2470                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2471                              vmx->vcpu.arch.event_exit_inst_len);
2472                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2473         } else
2474                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2475
2476         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2477 }
2478
2479 static bool vmx_rdtscp_supported(void)
2480 {
2481         return cpu_has_vmx_rdtscp();
2482 }
2483
2484 static bool vmx_invpcid_supported(void)
2485 {
2486         return cpu_has_vmx_invpcid() && enable_ept;
2487 }
2488
2489 /*
2490  * Swap MSR entry in host/guest MSR entry array.
2491  */
2492 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2493 {
2494         struct shared_msr_entry tmp;
2495
2496         tmp = vmx->guest_msrs[to];
2497         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2498         vmx->guest_msrs[from] = tmp;
2499 }
2500
2501 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2502 {
2503         unsigned long *msr_bitmap;
2504
2505         if (is_guest_mode(vcpu))
2506                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2507         else if (cpu_has_secondary_exec_ctrls() &&
2508                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2509                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2510                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2511                         if (is_long_mode(vcpu))
2512                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2513                         else
2514                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2515                 } else {
2516                         if (is_long_mode(vcpu))
2517                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2518                         else
2519                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2520                 }
2521         } else {
2522                 if (is_long_mode(vcpu))
2523                         msr_bitmap = vmx_msr_bitmap_longmode;
2524                 else
2525                         msr_bitmap = vmx_msr_bitmap_legacy;
2526         }
2527
2528         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2529 }
2530
2531 /*
2532  * Set up the vmcs to automatically save and restore system
2533  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2534  * mode, as fiddling with msrs is very expensive.
2535  */
2536 static void setup_msrs(struct vcpu_vmx *vmx)
2537 {
2538         int save_nmsrs, index;
2539
2540         save_nmsrs = 0;
2541 #ifdef CONFIG_X86_64
2542         if (is_long_mode(&vmx->vcpu)) {
2543                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2544                 if (index >= 0)
2545                         move_msr_up(vmx, index, save_nmsrs++);
2546                 index = __find_msr_index(vmx, MSR_LSTAR);
2547                 if (index >= 0)
2548                         move_msr_up(vmx, index, save_nmsrs++);
2549                 index = __find_msr_index(vmx, MSR_CSTAR);
2550                 if (index >= 0)
2551                         move_msr_up(vmx, index, save_nmsrs++);
2552                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2553                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2554                         move_msr_up(vmx, index, save_nmsrs++);
2555                 /*
2556                  * MSR_STAR is only needed on long mode guests, and only
2557                  * if efer.sce is enabled.
2558                  */
2559                 index = __find_msr_index(vmx, MSR_STAR);
2560                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2561                         move_msr_up(vmx, index, save_nmsrs++);
2562         }
2563 #endif
2564         index = __find_msr_index(vmx, MSR_EFER);
2565         if (index >= 0 && update_transition_efer(vmx, index))
2566                 move_msr_up(vmx, index, save_nmsrs++);
2567
2568         vmx->save_nmsrs = save_nmsrs;
2569
2570         if (cpu_has_vmx_msr_bitmap())
2571                 vmx_set_msr_bitmap(&vmx->vcpu);
2572 }
2573
2574 /*
2575  * reads and returns guest's timestamp counter "register"
2576  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2577  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2578  */
2579 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2580 {
2581         u64 host_tsc, tsc_offset;
2582
2583         host_tsc = rdtsc();
2584         tsc_offset = vmcs_read64(TSC_OFFSET);
2585         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2586 }
2587
2588 /*
2589  * writes 'offset' into guest's timestamp counter offset register
2590  */
2591 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2592 {
2593         if (is_guest_mode(vcpu)) {
2594                 /*
2595                  * We're here if L1 chose not to trap WRMSR to TSC. According
2596                  * to the spec, this should set L1's TSC; The offset that L1
2597                  * set for L2 remains unchanged, and still needs to be added
2598                  * to the newly set TSC to get L2's TSC.
2599                  */
2600                 struct vmcs12 *vmcs12;
2601                 /* recalculate vmcs02.TSC_OFFSET: */
2602                 vmcs12 = get_vmcs12(vcpu);
2603                 vmcs_write64(TSC_OFFSET, offset +
2604                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2605                          vmcs12->tsc_offset : 0));
2606         } else {
2607                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2608                                            vmcs_read64(TSC_OFFSET), offset);
2609                 vmcs_write64(TSC_OFFSET, offset);
2610         }
2611 }
2612
2613 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2614 {
2615         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2616         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2617 }
2618
2619 /*
2620  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2621  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2622  * all guests if the "nested" module option is off, and can also be disabled
2623  * for a single guest by disabling its VMX cpuid bit.
2624  */
2625 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2626 {
2627         return nested && guest_cpuid_has_vmx(vcpu);
2628 }
2629
2630 /*
2631  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2632  * returned for the various VMX controls MSRs when nested VMX is enabled.
2633  * The same values should also be used to verify that vmcs12 control fields are
2634  * valid during nested entry from L1 to L2.
2635  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2636  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2637  * bit in the high half is on if the corresponding bit in the control field
2638  * may be on. See also vmx_control_verify().
2639  */
2640 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2641 {
2642         /*
2643          * Note that as a general rule, the high half of the MSRs (bits in
2644          * the control fields which may be 1) should be initialized by the
2645          * intersection of the underlying hardware's MSR (i.e., features which
2646          * can be supported) and the list of features we want to expose -
2647          * because they are known to be properly supported in our code.
2648          * Also, usually, the low half of the MSRs (bits which must be 1) can
2649          * be set to 0, meaning that L1 may turn off any of these bits. The
2650          * reason is that if one of these bits is necessary, it will appear
2651          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2652          * fields of vmcs01 and vmcs02, will turn these bits off - and
2653          * nested_vmx_exit_handled() will not pass related exits to L1.
2654          * These rules have exceptions below.
2655          */
2656
2657         /* pin-based controls */
2658         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2659                 vmx->nested.nested_vmx_pinbased_ctls_low,
2660                 vmx->nested.nested_vmx_pinbased_ctls_high);
2661         vmx->nested.nested_vmx_pinbased_ctls_low |=
2662                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2663         vmx->nested.nested_vmx_pinbased_ctls_high &=
2664                 PIN_BASED_EXT_INTR_MASK |
2665                 PIN_BASED_NMI_EXITING |
2666                 PIN_BASED_VIRTUAL_NMIS;
2667         vmx->nested.nested_vmx_pinbased_ctls_high |=
2668                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2669                 PIN_BASED_VMX_PREEMPTION_TIMER;
2670         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2671                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2672                         PIN_BASED_POSTED_INTR;
2673
2674         /* exit controls */
2675         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2676                 vmx->nested.nested_vmx_exit_ctls_low,
2677                 vmx->nested.nested_vmx_exit_ctls_high);
2678         vmx->nested.nested_vmx_exit_ctls_low =
2679                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2680
2681         vmx->nested.nested_vmx_exit_ctls_high &=
2682 #ifdef CONFIG_X86_64
2683                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2684 #endif
2685                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2686         vmx->nested.nested_vmx_exit_ctls_high |=
2687                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2688                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2689                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2690
2691         if (kvm_mpx_supported())
2692                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2693
2694         /* We support free control of debug control saving. */
2695         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2696
2697         /* entry controls */
2698         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2699                 vmx->nested.nested_vmx_entry_ctls_low,
2700                 vmx->nested.nested_vmx_entry_ctls_high);
2701         vmx->nested.nested_vmx_entry_ctls_low =
2702                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2703         vmx->nested.nested_vmx_entry_ctls_high &=
2704 #ifdef CONFIG_X86_64
2705                 VM_ENTRY_IA32E_MODE |
2706 #endif
2707                 VM_ENTRY_LOAD_IA32_PAT;
2708         vmx->nested.nested_vmx_entry_ctls_high |=
2709                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2710         if (kvm_mpx_supported())
2711                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2712
2713         /* We support free control of debug control loading. */
2714         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2715
2716         /* cpu-based controls */
2717         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2718                 vmx->nested.nested_vmx_procbased_ctls_low,
2719                 vmx->nested.nested_vmx_procbased_ctls_high);
2720         vmx->nested.nested_vmx_procbased_ctls_low =
2721                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2722         vmx->nested.nested_vmx_procbased_ctls_high &=
2723                 CPU_BASED_VIRTUAL_INTR_PENDING |
2724                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2725                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2726                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2727                 CPU_BASED_CR3_STORE_EXITING |
2728 #ifdef CONFIG_X86_64
2729                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2730 #endif
2731                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2732                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2733                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2734                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2735                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2736         /*
2737          * We can allow some features even when not supported by the
2738          * hardware. For example, L1 can specify an MSR bitmap - and we
2739          * can use it to avoid exits to L1 - even when L0 runs L2
2740          * without MSR bitmaps.
2741          */
2742         vmx->nested.nested_vmx_procbased_ctls_high |=
2743                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2744                 CPU_BASED_USE_MSR_BITMAPS;
2745
2746         /* We support free control of CR3 access interception. */
2747         vmx->nested.nested_vmx_procbased_ctls_low &=
2748                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2749
2750         /* secondary cpu-based controls */
2751         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2752                 vmx->nested.nested_vmx_secondary_ctls_low,
2753                 vmx->nested.nested_vmx_secondary_ctls_high);
2754         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2755         vmx->nested.nested_vmx_secondary_ctls_high &=
2756                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2757                 SECONDARY_EXEC_RDTSCP |
2758                 SECONDARY_EXEC_DESC |
2759                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2760                 SECONDARY_EXEC_ENABLE_VPID |
2761                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2762                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2763                 SECONDARY_EXEC_WBINVD_EXITING |
2764                 SECONDARY_EXEC_XSAVES;
2765
2766         if (enable_ept) {
2767                 /* nested EPT: emulate EPT also to L1 */
2768                 vmx->nested.nested_vmx_secondary_ctls_high |=
2769                         SECONDARY_EXEC_ENABLE_EPT;
2770                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2771                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2772                          VMX_EPT_INVEPT_BIT;
2773                 if (cpu_has_vmx_ept_execute_only())
2774                         vmx->nested.nested_vmx_ept_caps |=
2775                                 VMX_EPT_EXECUTE_ONLY_BIT;
2776                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2777                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2778                         VMX_EPT_EXTENT_CONTEXT_BIT;
2779         } else
2780                 vmx->nested.nested_vmx_ept_caps = 0;
2781
2782         /*
2783          * Old versions of KVM use the single-context version without
2784          * checking for support, so declare that it is supported even
2785          * though it is treated as global context.  The alternative is
2786          * not failing the single-context invvpid, and it is worse.
2787          */
2788         if (enable_vpid)
2789                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2790                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2791         else
2792                 vmx->nested.nested_vmx_vpid_caps = 0;
2793
2794         if (enable_unrestricted_guest)
2795                 vmx->nested.nested_vmx_secondary_ctls_high |=
2796                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2797
2798         /* miscellaneous data */
2799         rdmsr(MSR_IA32_VMX_MISC,
2800                 vmx->nested.nested_vmx_misc_low,
2801                 vmx->nested.nested_vmx_misc_high);
2802         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2803         vmx->nested.nested_vmx_misc_low |=
2804                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2805                 VMX_MISC_ACTIVITY_HLT;
2806         vmx->nested.nested_vmx_misc_high = 0;
2807
2808         /*
2809          * This MSR reports some information about VMX support. We
2810          * should return information about the VMX we emulate for the
2811          * guest, and the VMCS structure we give it - not about the
2812          * VMX support of the underlying hardware.
2813          */
2814         vmx->nested.nested_vmx_basic =
2815                 VMCS12_REVISION |
2816                 VMX_BASIC_TRUE_CTLS |
2817                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2818                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2819
2820         if (cpu_has_vmx_basic_inout())
2821                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2822
2823         /*
2824          * These MSRs specify bits which the guest must keep fixed on
2825          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2826          * We picked the standard core2 setting.
2827          */
2828 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2829 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2830         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2831         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2832
2833         /* These MSRs specify bits which the guest must keep fixed off. */
2834         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2835         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2836
2837         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2838         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2839 }
2840
2841 /*
2842  * if fixed0[i] == 1: val[i] must be 1
2843  * if fixed1[i] == 0: val[i] must be 0
2844  */
2845 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2846 {
2847         return ((val & fixed1) | fixed0) == val;
2848 }
2849
2850 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2851 {
2852         return fixed_bits_valid(control, low, high);
2853 }
2854
2855 static inline u64 vmx_control_msr(u32 low, u32 high)
2856 {
2857         return low | ((u64)high << 32);
2858 }
2859
2860 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2861 {
2862         superset &= mask;
2863         subset &= mask;
2864
2865         return (superset | subset) == superset;
2866 }
2867
2868 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2869 {
2870         const u64 feature_and_reserved =
2871                 /* feature (except bit 48; see below) */
2872                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2873                 /* reserved */
2874                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2875         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2876
2877         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2878                 return -EINVAL;
2879
2880         /*
2881          * KVM does not emulate a version of VMX that constrains physical
2882          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2883          */
2884         if (data & BIT_ULL(48))
2885                 return -EINVAL;
2886
2887         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2888             vmx_basic_vmcs_revision_id(data))
2889                 return -EINVAL;
2890
2891         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2892                 return -EINVAL;
2893
2894         vmx->nested.nested_vmx_basic = data;
2895         return 0;
2896 }
2897
2898 static int
2899 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2900 {
2901         u64 supported;
2902         u32 *lowp, *highp;
2903
2904         switch (msr_index) {
2905         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2906                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2907                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2908                 break;
2909         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2910                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2911                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2912                 break;
2913         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2914                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2915                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2916                 break;
2917         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2918                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2919                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2920                 break;
2921         case MSR_IA32_VMX_PROCBASED_CTLS2:
2922                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2923                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2924                 break;
2925         default:
2926                 BUG();
2927         }
2928
2929         supported = vmx_control_msr(*lowp, *highp);
2930
2931         /* Check must-be-1 bits are still 1. */
2932         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2933                 return -EINVAL;
2934
2935         /* Check must-be-0 bits are still 0. */
2936         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2937                 return -EINVAL;
2938
2939         *lowp = data;
2940         *highp = data >> 32;
2941         return 0;
2942 }
2943
2944 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2945 {
2946         const u64 feature_and_reserved_bits =
2947                 /* feature */
2948                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2949                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2950                 /* reserved */
2951                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2952         u64 vmx_misc;
2953
2954         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2955                                    vmx->nested.nested_vmx_misc_high);
2956
2957         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2958                 return -EINVAL;
2959
2960         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2961              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2962             vmx_misc_preemption_timer_rate(data) !=
2963             vmx_misc_preemption_timer_rate(vmx_misc))
2964                 return -EINVAL;
2965
2966         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2967                 return -EINVAL;
2968
2969         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2970                 return -EINVAL;
2971
2972         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2973                 return -EINVAL;
2974
2975         vmx->nested.nested_vmx_misc_low = data;
2976         vmx->nested.nested_vmx_misc_high = data >> 32;
2977         return 0;
2978 }
2979
2980 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2981 {
2982         u64 vmx_ept_vpid_cap;
2983
2984         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2985                                            vmx->nested.nested_vmx_vpid_caps);
2986
2987         /* Every bit is either reserved or a feature bit. */
2988         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2989                 return -EINVAL;
2990
2991         vmx->nested.nested_vmx_ept_caps = data;
2992         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2993         return 0;
2994 }
2995
2996 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2997 {
2998         u64 *msr;
2999
3000         switch (msr_index) {
3001         case MSR_IA32_VMX_CR0_FIXED0:
3002                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3003                 break;
3004         case MSR_IA32_VMX_CR4_FIXED0:
3005                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3006                 break;
3007         default:
3008                 BUG();
3009         }
3010
3011         /*
3012          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3013          * must be 1 in the restored value.
3014          */
3015         if (!is_bitwise_subset(data, *msr, -1ULL))
3016                 return -EINVAL;
3017
3018         *msr = data;
3019         return 0;
3020 }
3021
3022 /*
3023  * Called when userspace is restoring VMX MSRs.
3024  *
3025  * Returns 0 on success, non-0 otherwise.
3026  */
3027 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3028 {
3029         struct vcpu_vmx *vmx = to_vmx(vcpu);
3030
3031         switch (msr_index) {
3032         case MSR_IA32_VMX_BASIC:
3033                 return vmx_restore_vmx_basic(vmx, data);
3034         case MSR_IA32_VMX_PINBASED_CTLS:
3035         case MSR_IA32_VMX_PROCBASED_CTLS:
3036         case MSR_IA32_VMX_EXIT_CTLS:
3037         case MSR_IA32_VMX_ENTRY_CTLS:
3038                 /*
3039                  * The "non-true" VMX capability MSRs are generated from the
3040                  * "true" MSRs, so we do not support restoring them directly.
3041                  *
3042                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3043                  * should restore the "true" MSRs with the must-be-1 bits
3044                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3045                  * DEFAULT SETTINGS".
3046                  */
3047                 return -EINVAL;
3048         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3049         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3050         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3051         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3052         case MSR_IA32_VMX_PROCBASED_CTLS2:
3053                 return vmx_restore_control_msr(vmx, msr_index, data);
3054         case MSR_IA32_VMX_MISC:
3055                 return vmx_restore_vmx_misc(vmx, data);
3056         case MSR_IA32_VMX_CR0_FIXED0:
3057         case MSR_IA32_VMX_CR4_FIXED0:
3058                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3059         case MSR_IA32_VMX_CR0_FIXED1:
3060         case MSR_IA32_VMX_CR4_FIXED1:
3061                 /*
3062                  * These MSRs are generated based on the vCPU's CPUID, so we
3063                  * do not support restoring them directly.
3064                  */
3065                 return -EINVAL;
3066         case MSR_IA32_VMX_EPT_VPID_CAP:
3067                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3068         case MSR_IA32_VMX_VMCS_ENUM:
3069                 vmx->nested.nested_vmx_vmcs_enum = data;
3070                 return 0;
3071         default:
3072                 /*
3073                  * The rest of the VMX capability MSRs do not support restore.
3074                  */
3075                 return -EINVAL;
3076         }
3077 }
3078
3079 /* Returns 0 on success, non-0 otherwise. */
3080 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3081 {
3082         struct vcpu_vmx *vmx = to_vmx(vcpu);
3083
3084         switch (msr_index) {
3085         case MSR_IA32_VMX_BASIC:
3086                 *pdata = vmx->nested.nested_vmx_basic;
3087                 break;
3088         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3089         case MSR_IA32_VMX_PINBASED_CTLS:
3090                 *pdata = vmx_control_msr(
3091                         vmx->nested.nested_vmx_pinbased_ctls_low,
3092                         vmx->nested.nested_vmx_pinbased_ctls_high);
3093                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3094                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3095                 break;
3096         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3097         case MSR_IA32_VMX_PROCBASED_CTLS:
3098                 *pdata = vmx_control_msr(
3099                         vmx->nested.nested_vmx_procbased_ctls_low,
3100                         vmx->nested.nested_vmx_procbased_ctls_high);
3101                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3102                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3103                 break;
3104         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3105         case MSR_IA32_VMX_EXIT_CTLS:
3106                 *pdata = vmx_control_msr(
3107                         vmx->nested.nested_vmx_exit_ctls_low,
3108                         vmx->nested.nested_vmx_exit_ctls_high);
3109                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3110                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3111                 break;
3112         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3113         case MSR_IA32_VMX_ENTRY_CTLS:
3114                 *pdata = vmx_control_msr(
3115                         vmx->nested.nested_vmx_entry_ctls_low,
3116                         vmx->nested.nested_vmx_entry_ctls_high);
3117                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3118                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3119                 break;
3120         case MSR_IA32_VMX_MISC:
3121                 *pdata = vmx_control_msr(
3122                         vmx->nested.nested_vmx_misc_low,
3123                         vmx->nested.nested_vmx_misc_high);
3124                 break;
3125         case MSR_IA32_VMX_CR0_FIXED0:
3126                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3127                 break;
3128         case MSR_IA32_VMX_CR0_FIXED1:
3129                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3130                 break;
3131         case MSR_IA32_VMX_CR4_FIXED0:
3132                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3133                 break;
3134         case MSR_IA32_VMX_CR4_FIXED1:
3135                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3136                 break;
3137         case MSR_IA32_VMX_VMCS_ENUM:
3138                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3139                 break;
3140         case MSR_IA32_VMX_PROCBASED_CTLS2:
3141                 *pdata = vmx_control_msr(
3142                         vmx->nested.nested_vmx_secondary_ctls_low,
3143                         vmx->nested.nested_vmx_secondary_ctls_high);
3144                 break;
3145         case MSR_IA32_VMX_EPT_VPID_CAP:
3146                 *pdata = vmx->nested.nested_vmx_ept_caps |
3147                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3148                 break;
3149         default:
3150                 return 1;
3151         }
3152
3153         return 0;
3154 }
3155
3156 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3157                                                  uint64_t val)
3158 {
3159         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3160
3161         return !(val & ~valid_bits);
3162 }
3163
3164 /*
3165  * Reads an msr value (of 'msr_index') into 'pdata'.
3166  * Returns 0 on success, non-0 otherwise.
3167  * Assumes vcpu_load() was already called.
3168  */
3169 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3170 {
3171         struct shared_msr_entry *msr;
3172
3173         switch (msr_info->index) {
3174 #ifdef CONFIG_X86_64
3175         case MSR_FS_BASE:
3176                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3177                 break;
3178         case MSR_GS_BASE:
3179                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3180                 break;
3181         case MSR_KERNEL_GS_BASE:
3182                 vmx_load_host_state(to_vmx(vcpu));
3183                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3184                 break;
3185 #endif
3186         case MSR_EFER:
3187                 return kvm_get_msr_common(vcpu, msr_info);
3188         case MSR_IA32_TSC:
3189                 msr_info->data = guest_read_tsc(vcpu);
3190                 break;
3191         case MSR_IA32_SYSENTER_CS:
3192                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3193                 break;
3194         case MSR_IA32_SYSENTER_EIP:
3195                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3196                 break;
3197         case MSR_IA32_SYSENTER_ESP:
3198                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3199                 break;
3200         case MSR_IA32_BNDCFGS:
3201                 if (!kvm_mpx_supported())
3202                         return 1;
3203                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3204                 break;
3205         case MSR_IA32_MCG_EXT_CTL:
3206                 if (!msr_info->host_initiated &&
3207                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3208                       FEATURE_CONTROL_LMCE))
3209                         return 1;
3210                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3211                 break;
3212         case MSR_IA32_FEATURE_CONTROL:
3213                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3214                 break;
3215         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3216                 if (!nested_vmx_allowed(vcpu))
3217                         return 1;
3218                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3219         case MSR_IA32_XSS:
3220                 if (!vmx_xsaves_supported())
3221                         return 1;
3222                 msr_info->data = vcpu->arch.ia32_xss;
3223                 break;
3224         case MSR_TSC_AUX:
3225                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3226                         return 1;
3227                 /* Otherwise falls through */
3228         default:
3229                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3230                 if (msr) {
3231                         msr_info->data = msr->data;
3232                         break;
3233                 }
3234                 return kvm_get_msr_common(vcpu, msr_info);
3235         }
3236
3237         return 0;
3238 }
3239
3240 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3241
3242 /*
3243  * Writes msr value into into the appropriate "register".
3244  * Returns 0 on success, non-0 otherwise.
3245  * Assumes vcpu_load() was already called.
3246  */
3247 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3248 {
3249         struct vcpu_vmx *vmx = to_vmx(vcpu);
3250         struct shared_msr_entry *msr;
3251         int ret = 0;
3252         u32 msr_index = msr_info->index;
3253         u64 data = msr_info->data;
3254
3255         switch (msr_index) {
3256         case MSR_EFER:
3257                 ret = kvm_set_msr_common(vcpu, msr_info);
3258                 break;
3259 #ifdef CONFIG_X86_64
3260         case MSR_FS_BASE:
3261                 vmx_segment_cache_clear(vmx);
3262                 vmcs_writel(GUEST_FS_BASE, data);
3263                 break;
3264         case MSR_GS_BASE:
3265                 vmx_segment_cache_clear(vmx);
3266                 vmcs_writel(GUEST_GS_BASE, data);
3267                 break;
3268         case MSR_KERNEL_GS_BASE:
3269                 vmx_load_host_state(vmx);
3270                 vmx->msr_guest_kernel_gs_base = data;
3271                 break;
3272 #endif
3273         case MSR_IA32_SYSENTER_CS:
3274                 vmcs_write32(GUEST_SYSENTER_CS, data);
3275                 break;
3276         case MSR_IA32_SYSENTER_EIP:
3277                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3278                 break;
3279         case MSR_IA32_SYSENTER_ESP:
3280                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3281                 break;
3282         case MSR_IA32_BNDCFGS:
3283                 if (!kvm_mpx_supported())
3284                         return 1;
3285                 vmcs_write64(GUEST_BNDCFGS, data);
3286                 break;
3287         case MSR_IA32_TSC:
3288                 kvm_write_tsc(vcpu, msr_info);
3289                 break;
3290         case MSR_IA32_CR_PAT:
3291                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3292                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3293                                 return 1;
3294                         vmcs_write64(GUEST_IA32_PAT, data);
3295                         vcpu->arch.pat = data;
3296                         break;
3297                 }
3298                 ret = kvm_set_msr_common(vcpu, msr_info);
3299                 break;
3300         case MSR_IA32_TSC_ADJUST:
3301                 ret = kvm_set_msr_common(vcpu, msr_info);
3302                 break;
3303         case MSR_IA32_MCG_EXT_CTL:
3304                 if ((!msr_info->host_initiated &&
3305                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3306                        FEATURE_CONTROL_LMCE)) ||
3307                     (data & ~MCG_EXT_CTL_LMCE_EN))
3308                         return 1;
3309                 vcpu->arch.mcg_ext_ctl = data;
3310                 break;
3311         case MSR_IA32_FEATURE_CONTROL:
3312                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3313                     (to_vmx(vcpu)->msr_ia32_feature_control &
3314                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3315                         return 1;
3316                 vmx->msr_ia32_feature_control = data;
3317                 if (msr_info->host_initiated && data == 0)
3318                         vmx_leave_nested(vcpu);
3319                 break;
3320         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3321                 if (!msr_info->host_initiated)
3322                         return 1; /* they are read-only */
3323                 if (!nested_vmx_allowed(vcpu))
3324                         return 1;
3325                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3326         case MSR_IA32_XSS:
3327                 if (!vmx_xsaves_supported())
3328                         return 1;
3329                 /*
3330                  * The only supported bit as of Skylake is bit 8, but
3331                  * it is not supported on KVM.
3332                  */
3333                 if (data != 0)
3334                         return 1;
3335                 vcpu->arch.ia32_xss = data;
3336                 if (vcpu->arch.ia32_xss != host_xss)
3337                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3338                                 vcpu->arch.ia32_xss, host_xss);
3339                 else
3340                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3341                 break;
3342         case MSR_TSC_AUX:
3343                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3344                         return 1;
3345                 /* Check reserved bit, higher 32 bits should be zero */
3346                 if ((data >> 32) != 0)
3347                         return 1;
3348                 /* Otherwise falls through */
3349         default:
3350                 msr = find_msr_entry(vmx, msr_index);
3351                 if (msr) {
3352                         u64 old_msr_data = msr->data;
3353                         msr->data = data;
3354                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3355                                 preempt_disable();
3356                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3357                                                          msr->mask);
3358                                 preempt_enable();
3359                                 if (ret)
3360                                         msr->data = old_msr_data;
3361                         }
3362                         break;
3363                 }
3364                 ret = kvm_set_msr_common(vcpu, msr_info);
3365         }
3366
3367         return ret;
3368 }
3369
3370 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3371 {
3372         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3373         switch (reg) {
3374         case VCPU_REGS_RSP:
3375                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3376                 break;
3377         case VCPU_REGS_RIP:
3378                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3379                 break;
3380         case VCPU_EXREG_PDPTR:
3381                 if (enable_ept)
3382                         ept_save_pdptrs(vcpu);
3383                 break;
3384         default:
3385                 break;
3386         }
3387 }
3388
3389 static __init int cpu_has_kvm_support(void)
3390 {
3391         return cpu_has_vmx();
3392 }
3393
3394 static __init int vmx_disabled_by_bios(void)
3395 {
3396         u64 msr;
3397
3398         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3399         if (msr & FEATURE_CONTROL_LOCKED) {
3400                 /* launched w/ TXT and VMX disabled */
3401                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3402                         && tboot_enabled())
3403                         return 1;
3404                 /* launched w/o TXT and VMX only enabled w/ TXT */
3405                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3406                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3407                         && !tboot_enabled()) {
3408                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3409                                 "activate TXT before enabling KVM\n");
3410                         return 1;
3411                 }
3412                 /* launched w/o TXT and VMX disabled */
3413                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3414                         && !tboot_enabled())
3415                         return 1;
3416         }
3417
3418         return 0;
3419 }
3420
3421 static void kvm_cpu_vmxon(u64 addr)
3422 {
3423         intel_pt_handle_vmx(1);
3424
3425         asm volatile (ASM_VMX_VMXON_RAX
3426                         : : "a"(&addr), "m"(addr)
3427                         : "memory", "cc");
3428 }
3429
3430 static int hardware_enable(void)
3431 {
3432         int cpu = raw_smp_processor_id();
3433         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3434         u64 old, test_bits;
3435
3436         if (cr4_read_shadow() & X86_CR4_VMXE)
3437                 return -EBUSY;
3438
3439         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3440         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3441         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3442
3443         /*
3444          * Now we can enable the vmclear operation in kdump
3445          * since the loaded_vmcss_on_cpu list on this cpu
3446          * has been initialized.
3447          *
3448          * Though the cpu is not in VMX operation now, there
3449          * is no problem to enable the vmclear operation
3450          * for the loaded_vmcss_on_cpu list is empty!
3451          */
3452         crash_enable_local_vmclear(cpu);
3453
3454         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3455
3456         test_bits = FEATURE_CONTROL_LOCKED;
3457         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3458         if (tboot_enabled())
3459                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3460
3461         if ((old & test_bits) != test_bits) {
3462                 /* enable and lock */
3463                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3464         }
3465         cr4_set_bits(X86_CR4_VMXE);
3466
3467         if (vmm_exclusive) {
3468                 kvm_cpu_vmxon(phys_addr);
3469                 ept_sync_global();
3470         }
3471
3472         native_store_gdt(this_cpu_ptr(&host_gdt));
3473
3474         return 0;
3475 }
3476
3477 static void vmclear_local_loaded_vmcss(void)
3478 {
3479         int cpu = raw_smp_processor_id();
3480         struct loaded_vmcs *v, *n;
3481
3482         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3483                                  loaded_vmcss_on_cpu_link)
3484                 __loaded_vmcs_clear(v);
3485 }
3486
3487
3488 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3489  * tricks.
3490  */
3491 static void kvm_cpu_vmxoff(void)
3492 {
3493         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3494
3495         intel_pt_handle_vmx(0);
3496 }
3497
3498 static void hardware_disable(void)
3499 {
3500         if (vmm_exclusive) {
3501                 vmclear_local_loaded_vmcss();
3502                 kvm_cpu_vmxoff();
3503         }
3504         cr4_clear_bits(X86_CR4_VMXE);
3505 }
3506
3507 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3508                                       u32 msr, u32 *result)
3509 {
3510         u32 vmx_msr_low, vmx_msr_high;
3511         u32 ctl = ctl_min | ctl_opt;
3512
3513         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3514
3515         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3516         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3517
3518         /* Ensure minimum (required) set of control bits are supported. */
3519         if (ctl_min & ~ctl)
3520                 return -EIO;
3521
3522         *result = ctl;
3523         return 0;
3524 }
3525
3526 static __init bool allow_1_setting(u32 msr, u32 ctl)
3527 {
3528         u32 vmx_msr_low, vmx_msr_high;
3529
3530         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3531         return vmx_msr_high & ctl;
3532 }
3533
3534 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3535 {
3536         u32 vmx_msr_low, vmx_msr_high;
3537         u32 min, opt, min2, opt2;
3538         u32 _pin_based_exec_control = 0;
3539         u32 _cpu_based_exec_control = 0;
3540         u32 _cpu_based_2nd_exec_control = 0;
3541         u32 _vmexit_control = 0;
3542         u32 _vmentry_control = 0;
3543
3544         min = CPU_BASED_HLT_EXITING |
3545 #ifdef CONFIG_X86_64
3546               CPU_BASED_CR8_LOAD_EXITING |
3547               CPU_BASED_CR8_STORE_EXITING |
3548 #endif
3549               CPU_BASED_CR3_LOAD_EXITING |
3550               CPU_BASED_CR3_STORE_EXITING |
3551               CPU_BASED_USE_IO_BITMAPS |
3552               CPU_BASED_MOV_DR_EXITING |
3553               CPU_BASED_USE_TSC_OFFSETING |
3554               CPU_BASED_MWAIT_EXITING |
3555               CPU_BASED_MONITOR_EXITING |
3556               CPU_BASED_INVLPG_EXITING |
3557               CPU_BASED_RDPMC_EXITING;
3558
3559         opt = CPU_BASED_TPR_SHADOW |
3560               CPU_BASED_USE_MSR_BITMAPS |
3561               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3562         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3563                                 &_cpu_based_exec_control) < 0)
3564                 return -EIO;
3565 #ifdef CONFIG_X86_64
3566         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3567                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3568                                            ~CPU_BASED_CR8_STORE_EXITING;
3569 #endif
3570         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3571                 min2 = 0;
3572                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3573                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3574                         SECONDARY_EXEC_WBINVD_EXITING |
3575                         SECONDARY_EXEC_ENABLE_VPID |
3576                         SECONDARY_EXEC_ENABLE_EPT |
3577                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3578                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3579                         SECONDARY_EXEC_RDTSCP |
3580                         SECONDARY_EXEC_ENABLE_INVPCID |
3581                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3582                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3583                         SECONDARY_EXEC_SHADOW_VMCS |
3584                         SECONDARY_EXEC_XSAVES |
3585                         SECONDARY_EXEC_ENABLE_PML |
3586                         SECONDARY_EXEC_TSC_SCALING;
3587                 if (adjust_vmx_controls(min2, opt2,
3588                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3589                                         &_cpu_based_2nd_exec_control) < 0)
3590                         return -EIO;
3591         }
3592 #ifndef CONFIG_X86_64
3593         if (!(_cpu_based_2nd_exec_control &
3594                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3595                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3596 #endif
3597
3598         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3599                 _cpu_based_2nd_exec_control &= ~(
3600                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3601                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3602                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3603
3604         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3605                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3606                    enabled */
3607                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3608                                              CPU_BASED_CR3_STORE_EXITING |
3609                                              CPU_BASED_INVLPG_EXITING);
3610                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3611                       vmx_capability.ept, vmx_capability.vpid);
3612         }
3613
3614         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3615 #ifdef CONFIG_X86_64
3616         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3617 #endif
3618         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3619                 VM_EXIT_CLEAR_BNDCFGS;
3620         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3621                                 &_vmexit_control) < 0)
3622                 return -EIO;
3623
3624         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3625         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3626                  PIN_BASED_VMX_PREEMPTION_TIMER;
3627         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3628                                 &_pin_based_exec_control) < 0)
3629                 return -EIO;
3630
3631         if (cpu_has_broken_vmx_preemption_timer())
3632                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3633         if (!(_cpu_based_2nd_exec_control &
3634                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3635                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3636
3637         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3638         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3639         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3640                                 &_vmentry_control) < 0)
3641                 return -EIO;
3642
3643         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3644
3645         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3646         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3647                 return -EIO;
3648
3649 #ifdef CONFIG_X86_64
3650         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3651         if (vmx_msr_high & (1u<<16))
3652                 return -EIO;
3653 #endif
3654
3655         /* Require Write-Back (WB) memory type for VMCS accesses. */
3656         if (((vmx_msr_high >> 18) & 15) != 6)
3657                 return -EIO;
3658
3659         vmcs_conf->size = vmx_msr_high & 0x1fff;
3660         vmcs_conf->order = get_order(vmcs_conf->size);
3661         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3662         vmcs_conf->revision_id = vmx_msr_low;
3663
3664         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3665         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3666         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3667         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3668         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3669
3670         cpu_has_load_ia32_efer =
3671                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3672                                 VM_ENTRY_LOAD_IA32_EFER)
3673                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3674                                    VM_EXIT_LOAD_IA32_EFER);
3675
3676         cpu_has_load_perf_global_ctrl =
3677                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3678                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3679                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3680                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3681
3682         /*
3683          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3684          * but due to errata below it can't be used. Workaround is to use
3685          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3686          *
3687          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3688          *
3689          * AAK155             (model 26)
3690          * AAP115             (model 30)
3691          * AAT100             (model 37)
3692          * BC86,AAY89,BD102   (model 44)
3693          * BA97               (model 46)
3694          *
3695          */
3696         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3697                 switch (boot_cpu_data.x86_model) {
3698                 case 26:
3699                 case 30:
3700                 case 37:
3701                 case 44:
3702                 case 46:
3703                         cpu_has_load_perf_global_ctrl = false;
3704                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3705                                         "does not work properly. Using workaround\n");
3706                         break;
3707                 default:
3708                         break;
3709                 }
3710         }
3711
3712         if (boot_cpu_has(X86_FEATURE_XSAVES))
3713                 rdmsrl(MSR_IA32_XSS, host_xss);
3714
3715         return 0;
3716 }
3717
3718 static struct vmcs *alloc_vmcs_cpu(int cpu)
3719 {
3720         int node = cpu_to_node(cpu);
3721         struct page *pages;
3722         struct vmcs *vmcs;
3723
3724         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3725         if (!pages)
3726                 return NULL;
3727         vmcs = page_address(pages);
3728         memset(vmcs, 0, vmcs_config.size);
3729         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3730         return vmcs;
3731 }
3732
3733 static struct vmcs *alloc_vmcs(void)
3734 {
3735         return alloc_vmcs_cpu(raw_smp_processor_id());
3736 }
3737
3738 static void free_vmcs(struct vmcs *vmcs)
3739 {
3740         free_pages((unsigned long)vmcs, vmcs_config.order);
3741 }
3742
3743 /*
3744  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3745  */
3746 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3747 {
3748         if (!loaded_vmcs->vmcs)
3749                 return;
3750         loaded_vmcs_clear(loaded_vmcs);
3751         free_vmcs(loaded_vmcs->vmcs);
3752         loaded_vmcs->vmcs = NULL;
3753         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3754 }
3755
3756 static void free_kvm_area(void)
3757 {
3758         int cpu;
3759
3760         for_each_possible_cpu(cpu) {
3761                 free_vmcs(per_cpu(vmxarea, cpu));
3762                 per_cpu(vmxarea, cpu) = NULL;
3763         }
3764 }
3765
3766 static void init_vmcs_shadow_fields(void)
3767 {
3768         int i, j;
3769
3770         /* No checks for read only fields yet */
3771
3772         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3773                 switch (shadow_read_write_fields[i]) {
3774                 case GUEST_BNDCFGS:
3775                         if (!kvm_mpx_supported())
3776                                 continue;
3777                         break;
3778                 default:
3779                         break;
3780                 }
3781
3782                 if (j < i)
3783                         shadow_read_write_fields[j] =
3784                                 shadow_read_write_fields[i];
3785                 j++;
3786         }
3787         max_shadow_read_write_fields = j;
3788
3789         /* shadowed fields guest access without vmexit */
3790         for (i = 0; i < max_shadow_read_write_fields; i++) {
3791                 clear_bit(shadow_read_write_fields[i],
3792                           vmx_vmwrite_bitmap);
3793                 clear_bit(shadow_read_write_fields[i],
3794                           vmx_vmread_bitmap);
3795         }
3796         for (i = 0; i < max_shadow_read_only_fields; i++)
3797                 clear_bit(shadow_read_only_fields[i],
3798                           vmx_vmread_bitmap);
3799 }
3800
3801 static __init int alloc_kvm_area(void)
3802 {
3803         int cpu;
3804
3805         for_each_possible_cpu(cpu) {
3806                 struct vmcs *vmcs;
3807
3808                 vmcs = alloc_vmcs_cpu(cpu);
3809                 if (!vmcs) {
3810                         free_kvm_area();
3811                         return -ENOMEM;
3812                 }
3813
3814                 per_cpu(vmxarea, cpu) = vmcs;
3815         }
3816         return 0;
3817 }
3818
3819 static bool emulation_required(struct kvm_vcpu *vcpu)
3820 {
3821         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3822 }
3823
3824 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3825                 struct kvm_segment *save)
3826 {
3827         if (!emulate_invalid_guest_state) {
3828                 /*
3829                  * CS and SS RPL should be equal during guest entry according
3830                  * to VMX spec, but in reality it is not always so. Since vcpu
3831                  * is in the middle of the transition from real mode to
3832                  * protected mode it is safe to assume that RPL 0 is a good
3833                  * default value.
3834                  */
3835                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3836                         save->selector &= ~SEGMENT_RPL_MASK;
3837                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3838                 save->s = 1;
3839         }
3840         vmx_set_segment(vcpu, save, seg);
3841 }
3842
3843 static void enter_pmode(struct kvm_vcpu *vcpu)
3844 {
3845         unsigned long flags;
3846         struct vcpu_vmx *vmx = to_vmx(vcpu);
3847
3848         /*
3849          * Update real mode segment cache. It may be not up-to-date if sement
3850          * register was written while vcpu was in a guest mode.
3851          */
3852         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3853         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3855         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3856         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3857         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3858
3859         vmx->rmode.vm86_active = 0;
3860
3861         vmx_segment_cache_clear(vmx);
3862
3863         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3864
3865         flags = vmcs_readl(GUEST_RFLAGS);
3866         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3867         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3868         vmcs_writel(GUEST_RFLAGS, flags);
3869
3870         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3871                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3872
3873         update_exception_bitmap(vcpu);
3874
3875         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3876         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3877         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3878         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3879         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3880         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3881 }
3882
3883 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3884 {
3885         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3886         struct kvm_segment var = *save;
3887
3888         var.dpl = 0x3;
3889         if (seg == VCPU_SREG_CS)
3890                 var.type = 0x3;
3891
3892         if (!emulate_invalid_guest_state) {
3893                 var.selector = var.base >> 4;
3894                 var.base = var.base & 0xffff0;
3895                 var.limit = 0xffff;
3896                 var.g = 0;
3897                 var.db = 0;
3898                 var.present = 1;
3899                 var.s = 1;
3900                 var.l = 0;
3901                 var.unusable = 0;
3902                 var.type = 0x3;
3903                 var.avl = 0;
3904                 if (save->base & 0xf)
3905                         printk_once(KERN_WARNING "kvm: segment base is not "
3906                                         "paragraph aligned when entering "
3907                                         "protected mode (seg=%d)", seg);
3908         }
3909
3910         vmcs_write16(sf->selector, var.selector);
3911         vmcs_write32(sf->base, var.base);
3912         vmcs_write32(sf->limit, var.limit);
3913         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3914 }
3915
3916 static void enter_rmode(struct kvm_vcpu *vcpu)
3917 {
3918         unsigned long flags;
3919         struct vcpu_vmx *vmx = to_vmx(vcpu);
3920
3921         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3922         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3923         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3924         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3925         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3926         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3927         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3928
3929         vmx->rmode.vm86_active = 1;
3930
3931         /*
3932          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3933          * vcpu. Warn the user that an update is overdue.
3934          */
3935         if (!vcpu->kvm->arch.tss_addr)
3936                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3937                              "called before entering vcpu\n");
3938
3939         vmx_segment_cache_clear(vmx);
3940
3941         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3942         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3943         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3944
3945         flags = vmcs_readl(GUEST_RFLAGS);
3946         vmx->rmode.save_rflags = flags;
3947
3948         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3949
3950         vmcs_writel(GUEST_RFLAGS, flags);
3951         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3952         update_exception_bitmap(vcpu);
3953
3954         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3955         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3956         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3957         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3958         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3959         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3960
3961         kvm_mmu_reset_context(vcpu);
3962 }
3963
3964 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3965 {
3966         struct vcpu_vmx *vmx = to_vmx(vcpu);
3967         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3968
3969         if (!msr)
3970                 return;
3971
3972         /*
3973          * Force kernel_gs_base reloading before EFER changes, as control
3974          * of this msr depends on is_long_mode().
3975          */
3976         vmx_load_host_state(to_vmx(vcpu));
3977         vcpu->arch.efer = efer;
3978         if (efer & EFER_LMA) {
3979                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3980                 msr->data = efer;
3981         } else {
3982                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3983
3984                 msr->data = efer & ~EFER_LME;
3985         }
3986         setup_msrs(vmx);
3987 }
3988
3989 #ifdef CONFIG_X86_64
3990
3991 static void enter_lmode(struct kvm_vcpu *vcpu)
3992 {
3993         u32 guest_tr_ar;
3994
3995         vmx_segment_cache_clear(to_vmx(vcpu));
3996
3997         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3998         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3999                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4000                                      __func__);
4001                 vmcs_write32(GUEST_TR_AR_BYTES,
4002                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4003                              | VMX_AR_TYPE_BUSY_64_TSS);
4004         }
4005         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4006 }
4007
4008 static void exit_lmode(struct kvm_vcpu *vcpu)
4009 {
4010         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4011         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4012 }
4013
4014 #endif
4015
4016 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4017 {
4018         vpid_sync_context(vpid);
4019         if (enable_ept) {
4020                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4021                         return;
4022                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4023         }
4024 }
4025
4026 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4027 {
4028         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4029 }
4030
4031 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4032 {
4033         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4034
4035         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4036         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4037 }
4038
4039 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4040 {
4041         if (enable_ept && is_paging(vcpu))
4042                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4043         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4044 }
4045
4046 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4047 {
4048         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4049
4050         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4051         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4052 }
4053
4054 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4055 {
4056         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4057
4058         if (!test_bit(VCPU_EXREG_PDPTR,
4059                       (unsigned long *)&vcpu->arch.regs_dirty))
4060                 return;
4061
4062         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4063                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4064                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4065                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4066                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4067         }
4068 }
4069
4070 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4071 {
4072         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4073
4074         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4075                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4076                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4077                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4078                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4079         }
4080
4081         __set_bit(VCPU_EXREG_PDPTR,
4082                   (unsigned long *)&vcpu->arch.regs_avail);
4083         __set_bit(VCPU_EXREG_PDPTR,
4084                   (unsigned long *)&vcpu->arch.regs_dirty);
4085 }
4086
4087 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4088 {
4089         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4090         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4091         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4092
4093         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4094                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4095             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4096                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4097
4098         return fixed_bits_valid(val, fixed0, fixed1);
4099 }
4100
4101 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4102 {
4103         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4104         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4105
4106         return fixed_bits_valid(val, fixed0, fixed1);
4107 }
4108
4109 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4110 {
4111         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4112         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4113
4114         return fixed_bits_valid(val, fixed0, fixed1);
4115 }
4116
4117 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4118 #define nested_guest_cr4_valid  nested_cr4_valid
4119 #define nested_host_cr4_valid   nested_cr4_valid
4120
4121 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4122
4123 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4124                                         unsigned long cr0,
4125                                         struct kvm_vcpu *vcpu)
4126 {
4127         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4128                 vmx_decache_cr3(vcpu);
4129         if (!(cr0 & X86_CR0_PG)) {
4130                 /* From paging/starting to nonpaging */
4131                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4132                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4133                              (CPU_BASED_CR3_LOAD_EXITING |
4134                               CPU_BASED_CR3_STORE_EXITING));
4135                 vcpu->arch.cr0 = cr0;
4136                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4137         } else if (!is_paging(vcpu)) {
4138                 /* From nonpaging to paging */
4139                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4140                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4141                              ~(CPU_BASED_CR3_LOAD_EXITING |
4142                                CPU_BASED_CR3_STORE_EXITING));
4143                 vcpu->arch.cr0 = cr0;
4144                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4145         }
4146
4147         if (!(cr0 & X86_CR0_WP))
4148                 *hw_cr0 &= ~X86_CR0_WP;
4149 }
4150
4151 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4152 {
4153         struct vcpu_vmx *vmx = to_vmx(vcpu);
4154         unsigned long hw_cr0;
4155
4156         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4157         if (enable_unrestricted_guest)
4158                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4159         else {
4160                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4161
4162                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4163                         enter_pmode(vcpu);
4164
4165                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4166                         enter_rmode(vcpu);
4167         }
4168
4169 #ifdef CONFIG_X86_64
4170         if (vcpu->arch.efer & EFER_LME) {
4171                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4172                         enter_lmode(vcpu);
4173                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4174                         exit_lmode(vcpu);
4175         }
4176 #endif
4177
4178         if (enable_ept)
4179                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4180
4181         vmcs_writel(CR0_READ_SHADOW, cr0);
4182         vmcs_writel(GUEST_CR0, hw_cr0);
4183         vcpu->arch.cr0 = cr0;
4184
4185         /* depends on vcpu->arch.cr0 to be set to a new value */
4186         vmx->emulation_required = emulation_required(vcpu);
4187 }
4188
4189 static u64 construct_eptp(unsigned long root_hpa)
4190 {
4191         u64 eptp;
4192
4193         /* TODO write the value reading from MSR */
4194         eptp = VMX_EPT_DEFAULT_MT |
4195                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4196         if (enable_ept_ad_bits)
4197                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4198         eptp |= (root_hpa & PAGE_MASK);
4199
4200         return eptp;
4201 }
4202
4203 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4204 {
4205         unsigned long guest_cr3;
4206         u64 eptp;
4207
4208         guest_cr3 = cr3;
4209         if (enable_ept) {
4210                 eptp = construct_eptp(cr3);
4211                 vmcs_write64(EPT_POINTER, eptp);
4212                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4213                         guest_cr3 = kvm_read_cr3(vcpu);
4214                 else
4215                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4216                 ept_load_pdptrs(vcpu);
4217         }
4218
4219         vmx_flush_tlb(vcpu);
4220         vmcs_writel(GUEST_CR3, guest_cr3);
4221 }
4222
4223 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4224 {
4225         /*
4226          * Pass through host's Machine Check Enable value to hw_cr4, which
4227          * is in force while we are in guest mode.  Do not let guests control
4228          * this bit, even if host CR4.MCE == 0.
4229          */
4230         unsigned long hw_cr4 =
4231                 (cr4_read_shadow() & X86_CR4_MCE) |
4232                 (cr4 & ~X86_CR4_MCE) |
4233                 (to_vmx(vcpu)->rmode.vm86_active ?
4234                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4235
4236         if (cr4 & X86_CR4_VMXE) {
4237                 /*
4238                  * To use VMXON (and later other VMX instructions), a guest
4239                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4240                  * So basically the check on whether to allow nested VMX
4241                  * is here.
4242                  */
4243                 if (!nested_vmx_allowed(vcpu))
4244                         return 1;
4245         }
4246
4247         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4248                 return 1;
4249
4250         vcpu->arch.cr4 = cr4;
4251         if (enable_ept) {
4252                 if (!is_paging(vcpu)) {
4253                         hw_cr4 &= ~X86_CR4_PAE;
4254                         hw_cr4 |= X86_CR4_PSE;
4255                 } else if (!(cr4 & X86_CR4_PAE)) {
4256                         hw_cr4 &= ~X86_CR4_PAE;
4257                 }
4258         }
4259
4260         if (!enable_unrestricted_guest && !is_paging(vcpu))
4261                 /*
4262                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4263                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4264                  * to be manually disabled when guest switches to non-paging
4265                  * mode.
4266                  *
4267                  * If !enable_unrestricted_guest, the CPU is always running
4268                  * with CR0.PG=1 and CR4 needs to be modified.
4269                  * If enable_unrestricted_guest, the CPU automatically
4270                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4271                  */
4272                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4273
4274         vmcs_writel(CR4_READ_SHADOW, cr4);
4275         vmcs_writel(GUEST_CR4, hw_cr4);
4276         return 0;
4277 }
4278
4279 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4280                             struct kvm_segment *var, int seg)
4281 {
4282         struct vcpu_vmx *vmx = to_vmx(vcpu);
4283         u32 ar;
4284
4285         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4286                 *var = vmx->rmode.segs[seg];
4287                 if (seg == VCPU_SREG_TR
4288                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4289                         return;
4290                 var->base = vmx_read_guest_seg_base(vmx, seg);
4291                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4292                 return;
4293         }
4294         var->base = vmx_read_guest_seg_base(vmx, seg);
4295         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4296         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4297         ar = vmx_read_guest_seg_ar(vmx, seg);
4298         var->unusable = (ar >> 16) & 1;
4299         var->type = ar & 15;
4300         var->s = (ar >> 4) & 1;
4301         var->dpl = (ar >> 5) & 3;
4302         /*
4303          * Some userspaces do not preserve unusable property. Since usable
4304          * segment has to be present according to VMX spec we can use present
4305          * property to amend userspace bug by making unusable segment always
4306          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4307          * segment as unusable.
4308          */
4309         var->present = !var->unusable;
4310         var->avl = (ar >> 12) & 1;
4311         var->l = (ar >> 13) & 1;
4312         var->db = (ar >> 14) & 1;
4313         var->g = (ar >> 15) & 1;
4314 }
4315
4316 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4317 {
4318         struct kvm_segment s;
4319
4320         if (to_vmx(vcpu)->rmode.vm86_active) {
4321                 vmx_get_segment(vcpu, &s, seg);
4322                 return s.base;
4323         }
4324         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4325 }
4326
4327 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4328 {
4329         struct vcpu_vmx *vmx = to_vmx(vcpu);
4330
4331         if (unlikely(vmx->rmode.vm86_active))
4332                 return 0;
4333         else {
4334                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4335                 return VMX_AR_DPL(ar);
4336         }
4337 }
4338
4339 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4340 {
4341         u32 ar;
4342
4343         if (var->unusable || !var->present)
4344                 ar = 1 << 16;
4345         else {
4346                 ar = var->type & 15;
4347                 ar |= (var->s & 1) << 4;
4348                 ar |= (var->dpl & 3) << 5;
4349                 ar |= (var->present & 1) << 7;
4350                 ar |= (var->avl & 1) << 12;
4351                 ar |= (var->l & 1) << 13;
4352                 ar |= (var->db & 1) << 14;
4353                 ar |= (var->g & 1) << 15;
4354         }
4355
4356         return ar;
4357 }
4358
4359 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4360                             struct kvm_segment *var, int seg)
4361 {
4362         struct vcpu_vmx *vmx = to_vmx(vcpu);
4363         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4364
4365         vmx_segment_cache_clear(vmx);
4366
4367         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4368                 vmx->rmode.segs[seg] = *var;
4369                 if (seg == VCPU_SREG_TR)
4370                         vmcs_write16(sf->selector, var->selector);
4371                 else if (var->s)
4372                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4373                 goto out;
4374         }
4375
4376         vmcs_writel(sf->base, var->base);
4377         vmcs_write32(sf->limit, var->limit);
4378         vmcs_write16(sf->selector, var->selector);
4379
4380         /*
4381          *   Fix the "Accessed" bit in AR field of segment registers for older
4382          * qemu binaries.
4383          *   IA32 arch specifies that at the time of processor reset the
4384          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4385          * is setting it to 0 in the userland code. This causes invalid guest
4386          * state vmexit when "unrestricted guest" mode is turned on.
4387          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4388          * tree. Newer qemu binaries with that qemu fix would not need this
4389          * kvm hack.
4390          */
4391         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4392                 var->type |= 0x1; /* Accessed */
4393
4394         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4395
4396 out:
4397         vmx->emulation_required = emulation_required(vcpu);
4398 }
4399
4400 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4401 {
4402         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4403
4404         *db = (ar >> 14) & 1;
4405         *l = (ar >> 13) & 1;
4406 }
4407
4408 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4409 {
4410         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4411         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4412 }
4413
4414 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4415 {
4416         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4417         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4418 }
4419
4420 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4421 {
4422         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4423         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4424 }
4425
4426 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4427 {
4428         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4429         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4430 }
4431
4432 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4433 {
4434         struct kvm_segment var;
4435         u32 ar;
4436
4437         vmx_get_segment(vcpu, &var, seg);
4438         var.dpl = 0x3;
4439         if (seg == VCPU_SREG_CS)
4440                 var.type = 0x3;
4441         ar = vmx_segment_access_rights(&var);
4442
4443         if (var.base != (var.selector << 4))
4444                 return false;
4445         if (var.limit != 0xffff)
4446                 return false;
4447         if (ar != 0xf3)
4448                 return false;
4449
4450         return true;
4451 }
4452
4453 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4454 {
4455         struct kvm_segment cs;
4456         unsigned int cs_rpl;
4457
4458         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4459         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4460
4461         if (cs.unusable)
4462                 return false;
4463         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4464                 return false;
4465         if (!cs.s)
4466                 return false;
4467         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4468                 if (cs.dpl > cs_rpl)
4469                         return false;
4470         } else {
4471                 if (cs.dpl != cs_rpl)
4472                         return false;
4473         }
4474         if (!cs.present)
4475                 return false;
4476
4477         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4478         return true;
4479 }
4480
4481 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4482 {
4483         struct kvm_segment ss;
4484         unsigned int ss_rpl;
4485
4486         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4487         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4488
4489         if (ss.unusable)
4490                 return true;
4491         if (ss.type != 3 && ss.type != 7)
4492                 return false;
4493         if (!ss.s)
4494                 return false;
4495         if (ss.dpl != ss_rpl) /* DPL != RPL */
4496                 return false;
4497         if (!ss.present)
4498                 return false;
4499
4500         return true;
4501 }
4502
4503 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4504 {
4505         struct kvm_segment var;
4506         unsigned int rpl;
4507
4508         vmx_get_segment(vcpu, &var, seg);
4509         rpl = var.selector & SEGMENT_RPL_MASK;
4510
4511         if (var.unusable)
4512                 return true;
4513         if (!var.s)
4514                 return false;
4515         if (!var.present)
4516                 return false;
4517         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4518                 if (var.dpl < rpl) /* DPL < RPL */
4519                         return false;
4520         }
4521
4522         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4523          * rights flags
4524          */
4525         return true;
4526 }
4527
4528 static bool tr_valid(struct kvm_vcpu *vcpu)
4529 {
4530         struct kvm_segment tr;
4531
4532         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4533
4534         if (tr.unusable)
4535                 return false;
4536         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4537                 return false;
4538         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4539                 return false;
4540         if (!tr.present)
4541                 return false;
4542
4543         return true;
4544 }
4545
4546 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4547 {
4548         struct kvm_segment ldtr;
4549
4550         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4551
4552         if (ldtr.unusable)
4553                 return true;
4554         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4555                 return false;
4556         if (ldtr.type != 2)
4557                 return false;
4558         if (!ldtr.present)
4559                 return false;
4560
4561         return true;
4562 }
4563
4564 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4565 {
4566         struct kvm_segment cs, ss;
4567
4568         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4569         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4570
4571         return ((cs.selector & SEGMENT_RPL_MASK) ==
4572                  (ss.selector & SEGMENT_RPL_MASK));
4573 }
4574
4575 /*
4576  * Check if guest state is valid. Returns true if valid, false if
4577  * not.
4578  * We assume that registers are always usable
4579  */
4580 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4581 {
4582         if (enable_unrestricted_guest)
4583                 return true;
4584
4585         /* real mode guest state checks */
4586         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4587                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4588                         return false;
4589                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4590                         return false;
4591                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4592                         return false;
4593                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4594                         return false;
4595                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4596                         return false;
4597                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4598                         return false;
4599         } else {
4600         /* protected mode guest state checks */
4601                 if (!cs_ss_rpl_check(vcpu))
4602                         return false;
4603                 if (!code_segment_valid(vcpu))
4604                         return false;
4605                 if (!stack_segment_valid(vcpu))
4606                         return false;
4607                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4608                         return false;
4609                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4610                         return false;
4611                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4612                         return false;
4613                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4614                         return false;
4615                 if (!tr_valid(vcpu))
4616                         return false;
4617                 if (!ldtr_valid(vcpu))
4618                         return false;
4619         }
4620         /* TODO:
4621          * - Add checks on RIP
4622          * - Add checks on RFLAGS
4623          */
4624
4625         return true;
4626 }
4627
4628 static int init_rmode_tss(struct kvm *kvm)
4629 {
4630         gfn_t fn;
4631         u16 data = 0;
4632         int idx, r;
4633
4634         idx = srcu_read_lock(&kvm->srcu);
4635         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4636         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4637         if (r < 0)
4638                 goto out;
4639         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4640         r = kvm_write_guest_page(kvm, fn++, &data,
4641                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4642         if (r < 0)
4643                 goto out;
4644         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4645         if (r < 0)
4646                 goto out;
4647         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4648         if (r < 0)
4649                 goto out;
4650         data = ~0;
4651         r = kvm_write_guest_page(kvm, fn, &data,
4652                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4653                                  sizeof(u8));
4654 out:
4655         srcu_read_unlock(&kvm->srcu, idx);
4656         return r;
4657 }
4658
4659 static int init_rmode_identity_map(struct kvm *kvm)
4660 {
4661         int i, idx, r = 0;
4662         kvm_pfn_t identity_map_pfn;
4663         u32 tmp;
4664
4665         if (!enable_ept)
4666                 return 0;
4667
4668         /* Protect kvm->arch.ept_identity_pagetable_done. */
4669         mutex_lock(&kvm->slots_lock);
4670
4671         if (likely(kvm->arch.ept_identity_pagetable_done))
4672                 goto out2;
4673
4674         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4675
4676         r = alloc_identity_pagetable(kvm);
4677         if (r < 0)
4678                 goto out2;
4679
4680         idx = srcu_read_lock(&kvm->srcu);
4681         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4682         if (r < 0)
4683                 goto out;
4684         /* Set up identity-mapping pagetable for EPT in real mode */
4685         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4686                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4687                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4688                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4689                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4690                 if (r < 0)
4691                         goto out;
4692         }
4693         kvm->arch.ept_identity_pagetable_done = true;
4694
4695 out:
4696         srcu_read_unlock(&kvm->srcu, idx);
4697
4698 out2:
4699         mutex_unlock(&kvm->slots_lock);
4700         return r;
4701 }
4702
4703 static void seg_setup(int seg)
4704 {
4705         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4706         unsigned int ar;
4707
4708         vmcs_write16(sf->selector, 0);
4709         vmcs_writel(sf->base, 0);
4710         vmcs_write32(sf->limit, 0xffff);
4711         ar = 0x93;
4712         if (seg == VCPU_SREG_CS)
4713                 ar |= 0x08; /* code segment */
4714
4715         vmcs_write32(sf->ar_bytes, ar);
4716 }
4717
4718 static int alloc_apic_access_page(struct kvm *kvm)
4719 {
4720         struct page *page;
4721         int r = 0;
4722
4723         mutex_lock(&kvm->slots_lock);
4724         if (kvm->arch.apic_access_page_done)
4725                 goto out;
4726         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4727                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4728         if (r)
4729                 goto out;
4730
4731         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4732         if (is_error_page(page)) {
4733                 r = -EFAULT;
4734                 goto out;
4735         }
4736
4737         /*
4738          * Do not pin the page in memory, so that memory hot-unplug
4739          * is able to migrate it.
4740          */
4741         put_page(page);
4742         kvm->arch.apic_access_page_done = true;
4743 out:
4744         mutex_unlock(&kvm->slots_lock);
4745         return r;
4746 }
4747
4748 static int alloc_identity_pagetable(struct kvm *kvm)
4749 {
4750         /* Called with kvm->slots_lock held. */
4751
4752         int r = 0;
4753
4754         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4755
4756         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4757                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4758
4759         return r;
4760 }
4761
4762 static int allocate_vpid(void)
4763 {
4764         int vpid;
4765
4766         if (!enable_vpid)
4767                 return 0;
4768         spin_lock(&vmx_vpid_lock);
4769         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4770         if (vpid < VMX_NR_VPIDS)
4771                 __set_bit(vpid, vmx_vpid_bitmap);
4772         else
4773                 vpid = 0;
4774         spin_unlock(&vmx_vpid_lock);
4775         return vpid;
4776 }
4777
4778 static void free_vpid(int vpid)
4779 {
4780         if (!enable_vpid || vpid == 0)
4781                 return;
4782         spin_lock(&vmx_vpid_lock);
4783         __clear_bit(vpid, vmx_vpid_bitmap);
4784         spin_unlock(&vmx_vpid_lock);
4785 }
4786
4787 #define MSR_TYPE_R      1
4788 #define MSR_TYPE_W      2
4789 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4790                                                 u32 msr, int type)
4791 {
4792         int f = sizeof(unsigned long);
4793
4794         if (!cpu_has_vmx_msr_bitmap())
4795                 return;
4796
4797         /*
4798          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4799          * have the write-low and read-high bitmap offsets the wrong way round.
4800          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4801          */
4802         if (msr <= 0x1fff) {
4803                 if (type & MSR_TYPE_R)
4804                         /* read-low */
4805                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4806
4807                 if (type & MSR_TYPE_W)
4808                         /* write-low */
4809                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4810
4811         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4812                 msr &= 0x1fff;
4813                 if (type & MSR_TYPE_R)
4814                         /* read-high */
4815                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4816
4817                 if (type & MSR_TYPE_W)
4818                         /* write-high */
4819                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4820
4821         }
4822 }
4823
4824 /*
4825  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4826  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4827  */
4828 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4829                                                unsigned long *msr_bitmap_nested,
4830                                                u32 msr, int type)
4831 {
4832         int f = sizeof(unsigned long);
4833
4834         if (!cpu_has_vmx_msr_bitmap()) {
4835                 WARN_ON(1);
4836                 return;
4837         }
4838
4839         /*
4840          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4841          * have the write-low and read-high bitmap offsets the wrong way round.
4842          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4843          */
4844         if (msr <= 0x1fff) {
4845                 if (type & MSR_TYPE_R &&
4846                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4847                         /* read-low */
4848                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4849
4850                 if (type & MSR_TYPE_W &&
4851                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4852                         /* write-low */
4853                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4854
4855         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4856                 msr &= 0x1fff;
4857                 if (type & MSR_TYPE_R &&
4858                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4859                         /* read-high */
4860                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4861
4862                 if (type & MSR_TYPE_W &&
4863                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4864                         /* write-high */
4865                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4866
4867         }
4868 }
4869
4870 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4871 {
4872         if (!longmode_only)
4873                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4874                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4875         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4876                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4877 }
4878
4879 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4880 {
4881         if (apicv_active) {
4882                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4883                                 msr, type);
4884                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4885                                 msr, type);
4886         } else {
4887                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4888                                 msr, type);
4889                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4890                                 msr, type);
4891         }
4892 }
4893
4894 static bool vmx_get_enable_apicv(void)
4895 {
4896         return enable_apicv;
4897 }
4898
4899 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4900 {
4901         struct vcpu_vmx *vmx = to_vmx(vcpu);
4902         int max_irr;
4903         void *vapic_page;
4904         u16 status;
4905
4906         if (vmx->nested.pi_desc &&
4907             vmx->nested.pi_pending) {
4908                 vmx->nested.pi_pending = false;
4909                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4910                         return;
4911
4912                 max_irr = find_last_bit(
4913                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4914
4915                 if (max_irr == 256)
4916                         return;
4917
4918                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4919                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4920                 kunmap(vmx->nested.virtual_apic_page);
4921
4922                 status = vmcs_read16(GUEST_INTR_STATUS);
4923                 if ((u8)max_irr > ((u8)status & 0xff)) {
4924                         status &= ~0xff;
4925                         status |= (u8)max_irr;
4926                         vmcs_write16(GUEST_INTR_STATUS, status);
4927                 }
4928         }
4929 }
4930
4931 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4932 {
4933 #ifdef CONFIG_SMP
4934         if (vcpu->mode == IN_GUEST_MODE) {
4935                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4936
4937                 /*
4938                  * Currently, we don't support urgent interrupt,
4939                  * all interrupts are recognized as non-urgent
4940                  * interrupt, so we cannot post interrupts when
4941                  * 'SN' is set.
4942                  *
4943                  * If the vcpu is in guest mode, it means it is
4944                  * running instead of being scheduled out and
4945                  * waiting in the run queue, and that's the only
4946                  * case when 'SN' is set currently, warning if
4947                  * 'SN' is set.
4948                  */
4949                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4950
4951                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4952                                 POSTED_INTR_VECTOR);
4953                 return true;
4954         }
4955 #endif
4956         return false;
4957 }
4958
4959 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4960                                                 int vector)
4961 {
4962         struct vcpu_vmx *vmx = to_vmx(vcpu);
4963
4964         if (is_guest_mode(vcpu) &&
4965             vector == vmx->nested.posted_intr_nv) {
4966                 /* the PIR and ON have been set by L1. */
4967                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4968                 /*
4969                  * If a posted intr is not recognized by hardware,
4970                  * we will accomplish it in the next vmentry.
4971                  */
4972                 vmx->nested.pi_pending = true;
4973                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4974                 return 0;
4975         }
4976         return -1;
4977 }
4978 /*
4979  * Send interrupt to vcpu via posted interrupt way.
4980  * 1. If target vcpu is running(non-root mode), send posted interrupt
4981  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4982  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4983  * interrupt from PIR in next vmentry.
4984  */
4985 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4986 {
4987         struct vcpu_vmx *vmx = to_vmx(vcpu);
4988         int r;
4989
4990         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4991         if (!r)
4992                 return;
4993
4994         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4995                 return;
4996
4997         /* If a previous notification has sent the IPI, nothing to do.  */
4998         if (pi_test_and_set_on(&vmx->pi_desc))
4999                 return;
5000
5001         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5002                 kvm_vcpu_kick(vcpu);
5003 }
5004
5005 /*
5006  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5007  * will not change in the lifetime of the guest.
5008  * Note that host-state that does change is set elsewhere. E.g., host-state
5009  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5010  */
5011 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5012 {
5013         u32 low32, high32;
5014         unsigned long tmpl;
5015         struct desc_ptr dt;
5016         unsigned long cr0, cr4;
5017
5018         cr0 = read_cr0();
5019         WARN_ON(cr0 & X86_CR0_TS);
5020         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5021         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5022
5023         /* Save the most likely value for this task's CR4 in the VMCS. */
5024         cr4 = cr4_read_shadow();
5025         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5026         vmx->host_state.vmcs_host_cr4 = cr4;
5027
5028         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5029 #ifdef CONFIG_X86_64
5030         /*
5031          * Load null selectors, so we can avoid reloading them in
5032          * __vmx_load_host_state(), in case userspace uses the null selectors
5033          * too (the expected case).
5034          */
5035         vmcs_write16(HOST_DS_SELECTOR, 0);
5036         vmcs_write16(HOST_ES_SELECTOR, 0);
5037 #else
5038         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5039         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5040 #endif
5041         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5042         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5043
5044         native_store_idt(&dt);
5045         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5046         vmx->host_idt_base = dt.address;
5047
5048         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5049
5050         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5051         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5052         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5053         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5054
5055         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5056                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5057                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5058         }
5059 }
5060
5061 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5062 {
5063         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5064         if (enable_ept)
5065                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5066         if (is_guest_mode(&vmx->vcpu))
5067                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5068                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5069         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5070 }
5071
5072 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5073 {
5074         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5075
5076         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5077                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5078         /* Enable the preemption timer dynamically */
5079         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5080         return pin_based_exec_ctrl;
5081 }
5082
5083 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5084 {
5085         struct vcpu_vmx *vmx = to_vmx(vcpu);
5086
5087         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5088         if (cpu_has_secondary_exec_ctrls()) {
5089                 if (kvm_vcpu_apicv_active(vcpu))
5090                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5091                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5092                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5093                 else
5094                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5095                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5096                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5097         }
5098
5099         if (cpu_has_vmx_msr_bitmap())
5100                 vmx_set_msr_bitmap(vcpu);
5101 }
5102
5103 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5104 {
5105         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5106
5107         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5108                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5109
5110         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5111                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5112 #ifdef CONFIG_X86_64
5113                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5114                                 CPU_BASED_CR8_LOAD_EXITING;
5115 #endif
5116         }
5117         if (!enable_ept)
5118                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5119                                 CPU_BASED_CR3_LOAD_EXITING  |
5120                                 CPU_BASED_INVLPG_EXITING;
5121         return exec_control;
5122 }
5123
5124 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5125 {
5126         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5127         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5128                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5129         if (vmx->vpid == 0)
5130                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5131         if (!enable_ept) {
5132                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5133                 enable_unrestricted_guest = 0;
5134                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5135                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5136         }
5137         if (!enable_unrestricted_guest)
5138                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5139         if (!ple_gap)
5140                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5141         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5142                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5143                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5144         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5145         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5146            (handle_vmptrld).
5147            We can NOT enable shadow_vmcs here because we don't have yet
5148            a current VMCS12
5149         */
5150         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5151
5152         if (!enable_pml)
5153                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5154
5155         return exec_control;
5156 }
5157
5158 static void ept_set_mmio_spte_mask(void)
5159 {
5160         /*
5161          * EPT Misconfigurations can be generated if the value of bits 2:0
5162          * of an EPT paging-structure entry is 110b (write/execute).
5163          */
5164         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5165 }
5166
5167 #define VMX_XSS_EXIT_BITMAP 0
5168 /*
5169  * Sets up the vmcs for emulated real mode.
5170  */
5171 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5172 {
5173 #ifdef CONFIG_X86_64
5174         unsigned long a;
5175 #endif
5176         int i;
5177
5178         /* I/O */
5179         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5180         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5181
5182         if (enable_shadow_vmcs) {
5183                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5184                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5185         }
5186         if (cpu_has_vmx_msr_bitmap())
5187                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5188
5189         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5190
5191         /* Control */
5192         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5193         vmx->hv_deadline_tsc = -1;
5194
5195         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5196
5197         if (cpu_has_secondary_exec_ctrls()) {
5198                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5199                                 vmx_secondary_exec_control(vmx));
5200         }
5201
5202         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5203                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5204                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5205                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5206                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5207
5208                 vmcs_write16(GUEST_INTR_STATUS, 0);
5209
5210                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5211                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5212         }
5213
5214         if (ple_gap) {
5215                 vmcs_write32(PLE_GAP, ple_gap);
5216                 vmx->ple_window = ple_window;
5217                 vmx->ple_window_dirty = true;
5218         }
5219
5220         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5221         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5222         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5223
5224         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5225         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5226         vmx_set_constant_host_state(vmx);
5227 #ifdef CONFIG_X86_64
5228         rdmsrl(MSR_FS_BASE, a);
5229         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5230         rdmsrl(MSR_GS_BASE, a);
5231         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5232 #else
5233         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5234         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5235 #endif
5236
5237         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5238         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5239         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5240         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5241         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5242
5243         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5244                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5245
5246         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5247                 u32 index = vmx_msr_index[i];
5248                 u32 data_low, data_high;
5249                 int j = vmx->nmsrs;
5250
5251                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5252                         continue;
5253                 if (wrmsr_safe(index, data_low, data_high) < 0)
5254                         continue;
5255                 vmx->guest_msrs[j].index = i;
5256                 vmx->guest_msrs[j].data = 0;
5257                 vmx->guest_msrs[j].mask = -1ull;
5258                 ++vmx->nmsrs;
5259         }
5260
5261
5262         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5263
5264         /* 22.2.1, 20.8.1 */
5265         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5266
5267         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5268         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5269
5270         set_cr4_guest_host_mask(vmx);
5271
5272         if (vmx_xsaves_supported())
5273                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5274
5275         if (enable_pml) {
5276                 ASSERT(vmx->pml_pg);
5277                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5278                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5279         }
5280
5281         return 0;
5282 }
5283
5284 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5285 {
5286         struct vcpu_vmx *vmx = to_vmx(vcpu);
5287         struct msr_data apic_base_msr;
5288         u64 cr0;
5289
5290         vmx->rmode.vm86_active = 0;
5291
5292         vmx->soft_vnmi_blocked = 0;
5293
5294         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5295         kvm_set_cr8(vcpu, 0);
5296
5297         if (!init_event) {
5298                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5299                                      MSR_IA32_APICBASE_ENABLE;
5300                 if (kvm_vcpu_is_reset_bsp(vcpu))
5301                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5302                 apic_base_msr.host_initiated = true;
5303                 kvm_set_apic_base(vcpu, &apic_base_msr);
5304         }
5305
5306         vmx_segment_cache_clear(vmx);
5307
5308         seg_setup(VCPU_SREG_CS);
5309         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5310         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5311
5312         seg_setup(VCPU_SREG_DS);
5313         seg_setup(VCPU_SREG_ES);
5314         seg_setup(VCPU_SREG_FS);
5315         seg_setup(VCPU_SREG_GS);
5316         seg_setup(VCPU_SREG_SS);
5317
5318         vmcs_write16(GUEST_TR_SELECTOR, 0);
5319         vmcs_writel(GUEST_TR_BASE, 0);
5320         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5321         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5322
5323         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5324         vmcs_writel(GUEST_LDTR_BASE, 0);
5325         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5326         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5327
5328         if (!init_event) {
5329                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5330                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5331                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5332                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5333         }
5334
5335         vmcs_writel(GUEST_RFLAGS, 0x02);
5336         kvm_rip_write(vcpu, 0xfff0);
5337
5338         vmcs_writel(GUEST_GDTR_BASE, 0);
5339         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5340
5341         vmcs_writel(GUEST_IDTR_BASE, 0);
5342         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5343
5344         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5345         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5346         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5347
5348         setup_msrs(vmx);
5349
5350         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5351
5352         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5353                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5354                 if (cpu_need_tpr_shadow(vcpu))
5355                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5356                                      __pa(vcpu->arch.apic->regs));
5357                 vmcs_write32(TPR_THRESHOLD, 0);
5358         }
5359
5360         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5361
5362         if (kvm_vcpu_apicv_active(vcpu))
5363                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5364
5365         if (vmx->vpid != 0)
5366                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5367
5368         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5369         vmx->vcpu.arch.cr0 = cr0;
5370         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5371         vmx_set_cr4(vcpu, 0);
5372         vmx_set_efer(vcpu, 0);
5373
5374         update_exception_bitmap(vcpu);
5375
5376         vpid_sync_context(vmx->vpid);
5377 }
5378
5379 /*
5380  * In nested virtualization, check if L1 asked to exit on external interrupts.
5381  * For most existing hypervisors, this will always return true.
5382  */
5383 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5384 {
5385         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5386                 PIN_BASED_EXT_INTR_MASK;
5387 }
5388
5389 /*
5390  * In nested virtualization, check if L1 has set
5391  * VM_EXIT_ACK_INTR_ON_EXIT
5392  */
5393 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5394 {
5395         return get_vmcs12(vcpu)->vm_exit_controls &
5396                 VM_EXIT_ACK_INTR_ON_EXIT;
5397 }
5398
5399 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5400 {
5401         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5402                 PIN_BASED_NMI_EXITING;
5403 }
5404
5405 static void enable_irq_window(struct kvm_vcpu *vcpu)
5406 {
5407         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5408                       CPU_BASED_VIRTUAL_INTR_PENDING);
5409 }
5410
5411 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5412 {
5413         if (!cpu_has_virtual_nmis() ||
5414             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5415                 enable_irq_window(vcpu);
5416                 return;
5417         }
5418
5419         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5420                       CPU_BASED_VIRTUAL_NMI_PENDING);
5421 }
5422
5423 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5424 {
5425         struct vcpu_vmx *vmx = to_vmx(vcpu);
5426         uint32_t intr;
5427         int irq = vcpu->arch.interrupt.nr;
5428
5429         trace_kvm_inj_virq(irq);
5430
5431         ++vcpu->stat.irq_injections;
5432         if (vmx->rmode.vm86_active) {
5433                 int inc_eip = 0;
5434                 if (vcpu->arch.interrupt.soft)
5435                         inc_eip = vcpu->arch.event_exit_inst_len;
5436                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5437                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5438                 return;
5439         }
5440         intr = irq | INTR_INFO_VALID_MASK;
5441         if (vcpu->arch.interrupt.soft) {
5442                 intr |= INTR_TYPE_SOFT_INTR;
5443                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5444                              vmx->vcpu.arch.event_exit_inst_len);
5445         } else
5446                 intr |= INTR_TYPE_EXT_INTR;
5447         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5448 }
5449
5450 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5451 {
5452         struct vcpu_vmx *vmx = to_vmx(vcpu);
5453
5454         if (!is_guest_mode(vcpu)) {
5455                 if (!cpu_has_virtual_nmis()) {
5456                         /*
5457                          * Tracking the NMI-blocked state in software is built upon
5458                          * finding the next open IRQ window. This, in turn, depends on
5459                          * well-behaving guests: They have to keep IRQs disabled at
5460                          * least as long as the NMI handler runs. Otherwise we may
5461                          * cause NMI nesting, maybe breaking the guest. But as this is
5462                          * highly unlikely, we can live with the residual risk.
5463                          */
5464                         vmx->soft_vnmi_blocked = 1;
5465                         vmx->vnmi_blocked_time = 0;
5466                 }
5467
5468                 ++vcpu->stat.nmi_injections;
5469                 vmx->nmi_known_unmasked = false;
5470         }
5471
5472         if (vmx->rmode.vm86_active) {
5473                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5474                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5475                 return;
5476         }
5477
5478         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5479                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5480 }
5481
5482 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5483 {
5484         if (!cpu_has_virtual_nmis())
5485                 return to_vmx(vcpu)->soft_vnmi_blocked;
5486         if (to_vmx(vcpu)->nmi_known_unmasked)
5487                 return false;
5488         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5489 }
5490
5491 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5492 {
5493         struct vcpu_vmx *vmx = to_vmx(vcpu);
5494
5495         if (!cpu_has_virtual_nmis()) {
5496                 if (vmx->soft_vnmi_blocked != masked) {
5497                         vmx->soft_vnmi_blocked = masked;
5498                         vmx->vnmi_blocked_time = 0;
5499                 }
5500         } else {
5501                 vmx->nmi_known_unmasked = !masked;
5502                 if (masked)
5503                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5504                                       GUEST_INTR_STATE_NMI);
5505                 else
5506                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5507                                         GUEST_INTR_STATE_NMI);
5508         }
5509 }
5510
5511 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5512 {
5513         if (to_vmx(vcpu)->nested.nested_run_pending)
5514                 return 0;
5515
5516         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5517                 return 0;
5518
5519         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5520                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5521                    | GUEST_INTR_STATE_NMI));
5522 }
5523
5524 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5525 {
5526         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5527                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5528                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5529                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5530 }
5531
5532 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5533 {
5534         int ret;
5535
5536         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5537                                     PAGE_SIZE * 3);
5538         if (ret)
5539                 return ret;
5540         kvm->arch.tss_addr = addr;
5541         return init_rmode_tss(kvm);
5542 }
5543
5544 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5545 {
5546         switch (vec) {
5547         case BP_VECTOR:
5548                 /*
5549                  * Update instruction length as we may reinject the exception
5550                  * from user space while in guest debugging mode.
5551                  */
5552                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5553                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5554                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5555                         return false;
5556                 /* fall through */
5557         case DB_VECTOR:
5558                 if (vcpu->guest_debug &
5559                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5560                         return false;
5561                 /* fall through */
5562         case DE_VECTOR:
5563         case OF_VECTOR:
5564         case BR_VECTOR:
5565         case UD_VECTOR:
5566         case DF_VECTOR:
5567         case SS_VECTOR:
5568         case GP_VECTOR:
5569         case MF_VECTOR:
5570                 return true;
5571         break;
5572         }
5573         return false;
5574 }
5575
5576 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5577                                   int vec, u32 err_code)
5578 {
5579         /*
5580          * Instruction with address size override prefix opcode 0x67
5581          * Cause the #SS fault with 0 error code in VM86 mode.
5582          */
5583         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5584                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5585                         if (vcpu->arch.halt_request) {
5586                                 vcpu->arch.halt_request = 0;
5587                                 return kvm_vcpu_halt(vcpu);
5588                         }
5589                         return 1;
5590                 }
5591                 return 0;
5592         }
5593
5594         /*
5595          * Forward all other exceptions that are valid in real mode.
5596          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5597          *        the required debugging infrastructure rework.
5598          */
5599         kvm_queue_exception(vcpu, vec);
5600         return 1;
5601 }
5602
5603 /*
5604  * Trigger machine check on the host. We assume all the MSRs are already set up
5605  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5606  * We pass a fake environment to the machine check handler because we want
5607  * the guest to be always treated like user space, no matter what context
5608  * it used internally.
5609  */
5610 static void kvm_machine_check(void)
5611 {
5612 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5613         struct pt_regs regs = {
5614                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5615                 .flags = X86_EFLAGS_IF,
5616         };
5617
5618         do_machine_check(&regs, 0);
5619 #endif
5620 }
5621
5622 static int handle_machine_check(struct kvm_vcpu *vcpu)
5623 {
5624         /* already handled by vcpu_run */
5625         return 1;
5626 }
5627
5628 static int handle_exception(struct kvm_vcpu *vcpu)
5629 {
5630         struct vcpu_vmx *vmx = to_vmx(vcpu);
5631         struct kvm_run *kvm_run = vcpu->run;
5632         u32 intr_info, ex_no, error_code;
5633         unsigned long cr2, rip, dr6;
5634         u32 vect_info;
5635         enum emulation_result er;
5636
5637         vect_info = vmx->idt_vectoring_info;
5638         intr_info = vmx->exit_intr_info;
5639
5640         if (is_machine_check(intr_info))
5641                 return handle_machine_check(vcpu);
5642
5643         if (is_nmi(intr_info))
5644                 return 1;  /* already handled by vmx_vcpu_run() */
5645
5646         if (is_invalid_opcode(intr_info)) {
5647                 if (is_guest_mode(vcpu)) {
5648                         kvm_queue_exception(vcpu, UD_VECTOR);
5649                         return 1;
5650                 }
5651                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5652                 if (er != EMULATE_DONE)
5653                         kvm_queue_exception(vcpu, UD_VECTOR);
5654                 return 1;
5655         }
5656
5657         error_code = 0;
5658         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5659                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5660
5661         /*
5662          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5663          * MMIO, it is better to report an internal error.
5664          * See the comments in vmx_handle_exit.
5665          */
5666         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5667             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5668                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5669                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5670                 vcpu->run->internal.ndata = 3;
5671                 vcpu->run->internal.data[0] = vect_info;
5672                 vcpu->run->internal.data[1] = intr_info;
5673                 vcpu->run->internal.data[2] = error_code;
5674                 return 0;
5675         }
5676
5677         if (is_page_fault(intr_info)) {
5678                 /* EPT won't cause page fault directly */
5679                 BUG_ON(enable_ept);
5680                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5681                 trace_kvm_page_fault(cr2, error_code);
5682
5683                 if (kvm_event_needs_reinjection(vcpu))
5684                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5685                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5686         }
5687
5688         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5689
5690         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5691                 return handle_rmode_exception(vcpu, ex_no, error_code);
5692
5693         switch (ex_no) {
5694         case AC_VECTOR:
5695                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5696                 return 1;
5697         case DB_VECTOR:
5698                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5699                 if (!(vcpu->guest_debug &
5700                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5701                         vcpu->arch.dr6 &= ~15;
5702                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5703                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5704                                 skip_emulated_instruction(vcpu);
5705
5706                         kvm_queue_exception(vcpu, DB_VECTOR);
5707                         return 1;
5708                 }
5709                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5710                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5711                 /* fall through */
5712         case BP_VECTOR:
5713                 /*
5714                  * Update instruction length as we may reinject #BP from
5715                  * user space while in guest debugging mode. Reading it for
5716                  * #DB as well causes no harm, it is not used in that case.
5717                  */
5718                 vmx->vcpu.arch.event_exit_inst_len =
5719                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5720                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5721                 rip = kvm_rip_read(vcpu);
5722                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5723                 kvm_run->debug.arch.exception = ex_no;
5724                 break;
5725         default:
5726                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5727                 kvm_run->ex.exception = ex_no;
5728                 kvm_run->ex.error_code = error_code;
5729                 break;
5730         }
5731         return 0;
5732 }
5733
5734 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5735 {
5736         ++vcpu->stat.irq_exits;
5737         return 1;
5738 }
5739
5740 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5741 {
5742         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5743         return 0;
5744 }
5745
5746 static int handle_io(struct kvm_vcpu *vcpu)
5747 {
5748         unsigned long exit_qualification;
5749         int size, in, string, ret;
5750         unsigned port;
5751
5752         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5753         string = (exit_qualification & 16) != 0;
5754         in = (exit_qualification & 8) != 0;
5755
5756         ++vcpu->stat.io_exits;
5757
5758         if (string || in)
5759                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5760
5761         port = exit_qualification >> 16;
5762         size = (exit_qualification & 7) + 1;
5763
5764         ret = kvm_skip_emulated_instruction(vcpu);
5765
5766         /*
5767          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5768          * KVM_EXIT_DEBUG here.
5769          */
5770         return kvm_fast_pio_out(vcpu, size, port) && ret;
5771 }
5772
5773 static void
5774 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5775 {
5776         /*
5777          * Patch in the VMCALL instruction:
5778          */
5779         hypercall[0] = 0x0f;
5780         hypercall[1] = 0x01;
5781         hypercall[2] = 0xc1;
5782 }
5783
5784 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5785 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5786 {
5787         if (is_guest_mode(vcpu)) {
5788                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5789                 unsigned long orig_val = val;
5790
5791                 /*
5792                  * We get here when L2 changed cr0 in a way that did not change
5793                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5794                  * but did change L0 shadowed bits. So we first calculate the
5795                  * effective cr0 value that L1 would like to write into the
5796                  * hardware. It consists of the L2-owned bits from the new
5797                  * value combined with the L1-owned bits from L1's guest_cr0.
5798                  */
5799                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5800                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5801
5802                 if (!nested_guest_cr0_valid(vcpu, val))
5803                         return 1;
5804
5805                 if (kvm_set_cr0(vcpu, val))
5806                         return 1;
5807                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5808                 return 0;
5809         } else {
5810                 if (to_vmx(vcpu)->nested.vmxon &&
5811                     !nested_host_cr0_valid(vcpu, val))
5812                         return 1;
5813
5814                 return kvm_set_cr0(vcpu, val);
5815         }
5816 }
5817
5818 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5819 {
5820         if (is_guest_mode(vcpu)) {
5821                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5822                 unsigned long orig_val = val;
5823
5824                 /* analogously to handle_set_cr0 */
5825                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5826                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5827                 if (kvm_set_cr4(vcpu, val))
5828                         return 1;
5829                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5830                 return 0;
5831         } else
5832                 return kvm_set_cr4(vcpu, val);
5833 }
5834
5835 static int handle_cr(struct kvm_vcpu *vcpu)
5836 {
5837         unsigned long exit_qualification, val;
5838         int cr;
5839         int reg;
5840         int err;
5841         int ret;
5842
5843         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5844         cr = exit_qualification & 15;
5845         reg = (exit_qualification >> 8) & 15;
5846         switch ((exit_qualification >> 4) & 3) {
5847         case 0: /* mov to cr */
5848                 val = kvm_register_readl(vcpu, reg);
5849                 trace_kvm_cr_write(cr, val);
5850                 switch (cr) {
5851                 case 0:
5852                         err = handle_set_cr0(vcpu, val);
5853                         return kvm_complete_insn_gp(vcpu, err);
5854                 case 3:
5855                         err = kvm_set_cr3(vcpu, val);
5856                         return kvm_complete_insn_gp(vcpu, err);
5857                 case 4:
5858                         err = handle_set_cr4(vcpu, val);
5859                         return kvm_complete_insn_gp(vcpu, err);
5860                 case 8: {
5861                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5862                                 u8 cr8 = (u8)val;
5863                                 err = kvm_set_cr8(vcpu, cr8);
5864                                 ret = kvm_complete_insn_gp(vcpu, err);
5865                                 if (lapic_in_kernel(vcpu))
5866                                         return ret;
5867                                 if (cr8_prev <= cr8)
5868                                         return ret;
5869                                 /*
5870                                  * TODO: we might be squashing a
5871                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5872                                  * KVM_EXIT_DEBUG here.
5873                                  */
5874                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5875                                 return 0;
5876                         }
5877                 }
5878                 break;
5879         case 2: /* clts */
5880                 WARN_ONCE(1, "Guest should always own CR0.TS");
5881                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5882                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5883                 return kvm_skip_emulated_instruction(vcpu);
5884         case 1: /*mov from cr*/
5885                 switch (cr) {
5886                 case 3:
5887                         val = kvm_read_cr3(vcpu);
5888                         kvm_register_write(vcpu, reg, val);
5889                         trace_kvm_cr_read(cr, val);
5890                         return kvm_skip_emulated_instruction(vcpu);
5891                 case 8:
5892                         val = kvm_get_cr8(vcpu);
5893                         kvm_register_write(vcpu, reg, val);
5894                         trace_kvm_cr_read(cr, val);
5895                         return kvm_skip_emulated_instruction(vcpu);
5896                 }
5897                 break;
5898         case 3: /* lmsw */
5899                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5900                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5901                 kvm_lmsw(vcpu, val);
5902
5903                 return kvm_skip_emulated_instruction(vcpu);
5904         default:
5905                 break;
5906         }
5907         vcpu->run->exit_reason = 0;
5908         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5909                (int)(exit_qualification >> 4) & 3, cr);
5910         return 0;
5911 }
5912
5913 static int handle_dr(struct kvm_vcpu *vcpu)
5914 {
5915         unsigned long exit_qualification;
5916         int dr, dr7, reg;
5917
5918         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5919         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5920
5921         /* First, if DR does not exist, trigger UD */
5922         if (!kvm_require_dr(vcpu, dr))
5923                 return 1;
5924
5925         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5926         if (!kvm_require_cpl(vcpu, 0))
5927                 return 1;
5928         dr7 = vmcs_readl(GUEST_DR7);
5929         if (dr7 & DR7_GD) {
5930                 /*
5931                  * As the vm-exit takes precedence over the debug trap, we
5932                  * need to emulate the latter, either for the host or the
5933                  * guest debugging itself.
5934                  */
5935                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5936                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5937                         vcpu->run->debug.arch.dr7 = dr7;
5938                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5939                         vcpu->run->debug.arch.exception = DB_VECTOR;
5940                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5941                         return 0;
5942                 } else {
5943                         vcpu->arch.dr6 &= ~15;
5944                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5945                         kvm_queue_exception(vcpu, DB_VECTOR);
5946                         return 1;
5947                 }
5948         }
5949
5950         if (vcpu->guest_debug == 0) {
5951                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5952                                 CPU_BASED_MOV_DR_EXITING);
5953
5954                 /*
5955                  * No more DR vmexits; force a reload of the debug registers
5956                  * and reenter on this instruction.  The next vmexit will
5957                  * retrieve the full state of the debug registers.
5958                  */
5959                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5960                 return 1;
5961         }
5962
5963         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5964         if (exit_qualification & TYPE_MOV_FROM_DR) {
5965                 unsigned long val;
5966
5967                 if (kvm_get_dr(vcpu, dr, &val))
5968                         return 1;
5969                 kvm_register_write(vcpu, reg, val);
5970         } else
5971                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5972                         return 1;
5973
5974         return kvm_skip_emulated_instruction(vcpu);
5975 }
5976
5977 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5978 {
5979         return vcpu->arch.dr6;
5980 }
5981
5982 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5983 {
5984 }
5985
5986 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5987 {
5988         get_debugreg(vcpu->arch.db[0], 0);
5989         get_debugreg(vcpu->arch.db[1], 1);
5990         get_debugreg(vcpu->arch.db[2], 2);
5991         get_debugreg(vcpu->arch.db[3], 3);
5992         get_debugreg(vcpu->arch.dr6, 6);
5993         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5994
5995         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5996         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5997 }
5998
5999 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6000 {
6001         vmcs_writel(GUEST_DR7, val);
6002 }
6003
6004 static int handle_cpuid(struct kvm_vcpu *vcpu)
6005 {
6006         return kvm_emulate_cpuid(vcpu);
6007 }
6008
6009 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6010 {
6011         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6012         struct msr_data msr_info;
6013
6014         msr_info.index = ecx;
6015         msr_info.host_initiated = false;
6016         if (vmx_get_msr(vcpu, &msr_info)) {
6017                 trace_kvm_msr_read_ex(ecx);
6018                 kvm_inject_gp(vcpu, 0);
6019                 return 1;
6020         }
6021
6022         trace_kvm_msr_read(ecx, msr_info.data);
6023
6024         /* FIXME: handling of bits 32:63 of rax, rdx */
6025         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6026         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6027         return kvm_skip_emulated_instruction(vcpu);
6028 }
6029
6030 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6031 {
6032         struct msr_data msr;
6033         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6034         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6035                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6036
6037         msr.data = data;
6038         msr.index = ecx;
6039         msr.host_initiated = false;
6040         if (kvm_set_msr(vcpu, &msr) != 0) {
6041                 trace_kvm_msr_write_ex(ecx, data);
6042                 kvm_inject_gp(vcpu, 0);
6043                 return 1;
6044         }
6045
6046         trace_kvm_msr_write(ecx, data);
6047         return kvm_skip_emulated_instruction(vcpu);
6048 }
6049
6050 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6051 {
6052         kvm_apic_update_ppr(vcpu);
6053         return 1;
6054 }
6055
6056 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6057 {
6058         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6059                         CPU_BASED_VIRTUAL_INTR_PENDING);
6060
6061         kvm_make_request(KVM_REQ_EVENT, vcpu);
6062
6063         ++vcpu->stat.irq_window_exits;
6064         return 1;
6065 }
6066
6067 static int handle_halt(struct kvm_vcpu *vcpu)
6068 {
6069         return kvm_emulate_halt(vcpu);
6070 }
6071
6072 static int handle_vmcall(struct kvm_vcpu *vcpu)
6073 {
6074         return kvm_emulate_hypercall(vcpu);
6075 }
6076
6077 static int handle_invd(struct kvm_vcpu *vcpu)
6078 {
6079         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6080 }
6081
6082 static int handle_invlpg(struct kvm_vcpu *vcpu)
6083 {
6084         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6085
6086         kvm_mmu_invlpg(vcpu, exit_qualification);
6087         return kvm_skip_emulated_instruction(vcpu);
6088 }
6089
6090 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6091 {
6092         int err;
6093
6094         err = kvm_rdpmc(vcpu);
6095         return kvm_complete_insn_gp(vcpu, err);
6096 }
6097
6098 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6099 {
6100         return kvm_emulate_wbinvd(vcpu);
6101 }
6102
6103 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6104 {
6105         u64 new_bv = kvm_read_edx_eax(vcpu);
6106         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6107
6108         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6109                 return kvm_skip_emulated_instruction(vcpu);
6110         return 1;
6111 }
6112
6113 static int handle_xsaves(struct kvm_vcpu *vcpu)
6114 {
6115         kvm_skip_emulated_instruction(vcpu);
6116         WARN(1, "this should never happen\n");
6117         return 1;
6118 }
6119
6120 static int handle_xrstors(struct kvm_vcpu *vcpu)
6121 {
6122         kvm_skip_emulated_instruction(vcpu);
6123         WARN(1, "this should never happen\n");
6124         return 1;
6125 }
6126
6127 static int handle_apic_access(struct kvm_vcpu *vcpu)
6128 {
6129         if (likely(fasteoi)) {
6130                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6131                 int access_type, offset;
6132
6133                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6134                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6135                 /*
6136                  * Sane guest uses MOV to write EOI, with written value
6137                  * not cared. So make a short-circuit here by avoiding
6138                  * heavy instruction emulation.
6139                  */
6140                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6141                     (offset == APIC_EOI)) {
6142                         kvm_lapic_set_eoi(vcpu);
6143                         return kvm_skip_emulated_instruction(vcpu);
6144                 }
6145         }
6146         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6147 }
6148
6149 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6150 {
6151         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6152         int vector = exit_qualification & 0xff;
6153
6154         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6155         kvm_apic_set_eoi_accelerated(vcpu, vector);
6156         return 1;
6157 }
6158
6159 static int handle_apic_write(struct kvm_vcpu *vcpu)
6160 {
6161         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6162         u32 offset = exit_qualification & 0xfff;
6163
6164         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6165         kvm_apic_write_nodecode(vcpu, offset);
6166         return 1;
6167 }
6168
6169 static int handle_task_switch(struct kvm_vcpu *vcpu)
6170 {
6171         struct vcpu_vmx *vmx = to_vmx(vcpu);
6172         unsigned long exit_qualification;
6173         bool has_error_code = false;
6174         u32 error_code = 0;
6175         u16 tss_selector;
6176         int reason, type, idt_v, idt_index;
6177
6178         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6179         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6180         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6181
6182         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6183
6184         reason = (u32)exit_qualification >> 30;
6185         if (reason == TASK_SWITCH_GATE && idt_v) {
6186                 switch (type) {
6187                 case INTR_TYPE_NMI_INTR:
6188                         vcpu->arch.nmi_injected = false;
6189                         vmx_set_nmi_mask(vcpu, true);
6190                         break;
6191                 case INTR_TYPE_EXT_INTR:
6192                 case INTR_TYPE_SOFT_INTR:
6193                         kvm_clear_interrupt_queue(vcpu);
6194                         break;
6195                 case INTR_TYPE_HARD_EXCEPTION:
6196                         if (vmx->idt_vectoring_info &
6197                             VECTORING_INFO_DELIVER_CODE_MASK) {
6198                                 has_error_code = true;
6199                                 error_code =
6200                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6201                         }
6202                         /* fall through */
6203                 case INTR_TYPE_SOFT_EXCEPTION:
6204                         kvm_clear_exception_queue(vcpu);
6205                         break;
6206                 default:
6207                         break;
6208                 }
6209         }
6210         tss_selector = exit_qualification;
6211
6212         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6213                        type != INTR_TYPE_EXT_INTR &&
6214                        type != INTR_TYPE_NMI_INTR))
6215                 skip_emulated_instruction(vcpu);
6216
6217         if (kvm_task_switch(vcpu, tss_selector,
6218                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6219                             has_error_code, error_code) == EMULATE_FAIL) {
6220                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6221                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6222                 vcpu->run->internal.ndata = 0;
6223                 return 0;
6224         }
6225
6226         /*
6227          * TODO: What about debug traps on tss switch?
6228          *       Are we supposed to inject them and update dr6?
6229          */
6230
6231         return 1;
6232 }
6233
6234 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6235 {
6236         unsigned long exit_qualification;
6237         gpa_t gpa;
6238         u32 error_code;
6239         int gla_validity;
6240
6241         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6242
6243         gla_validity = (exit_qualification >> 7) & 0x3;
6244         if (gla_validity == 0x2) {
6245                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6246                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6247                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6248                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6249                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6250                         (long unsigned int)exit_qualification);
6251                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6252                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6253                 return 0;
6254         }
6255
6256         /*
6257          * EPT violation happened while executing iret from NMI,
6258          * "blocked by NMI" bit has to be set before next VM entry.
6259          * There are errata that may cause this bit to not be set:
6260          * AAK134, BY25.
6261          */
6262         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6263                         cpu_has_virtual_nmis() &&
6264                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6265                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6266
6267         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6268         trace_kvm_page_fault(gpa, exit_qualification);
6269
6270         /* Is it a read fault? */
6271         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6272                      ? PFERR_USER_MASK : 0;
6273         /* Is it a write fault? */
6274         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6275                       ? PFERR_WRITE_MASK : 0;
6276         /* Is it a fetch fault? */
6277         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6278                       ? PFERR_FETCH_MASK : 0;
6279         /* ept page table entry is present? */
6280         error_code |= (exit_qualification &
6281                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6282                         EPT_VIOLATION_EXECUTABLE))
6283                       ? PFERR_PRESENT_MASK : 0;
6284
6285         vcpu->arch.gpa_available = true;
6286         vcpu->arch.exit_qualification = exit_qualification;
6287
6288         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6289 }
6290
6291 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6292 {
6293         int ret;
6294         gpa_t gpa;
6295
6296         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6297         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6298                 trace_kvm_fast_mmio(gpa);
6299                 return kvm_skip_emulated_instruction(vcpu);
6300         }
6301
6302         ret = handle_mmio_page_fault(vcpu, gpa, true);
6303         vcpu->arch.gpa_available = true;
6304         if (likely(ret == RET_MMIO_PF_EMULATE))
6305                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6306                                               EMULATE_DONE;
6307
6308         if (unlikely(ret == RET_MMIO_PF_INVALID))
6309                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6310
6311         if (unlikely(ret == RET_MMIO_PF_RETRY))
6312                 return 1;
6313
6314         /* It is the real ept misconfig */
6315         WARN_ON(1);
6316
6317         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6318         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6319
6320         return 0;
6321 }
6322
6323 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6324 {
6325         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6326                         CPU_BASED_VIRTUAL_NMI_PENDING);
6327         ++vcpu->stat.nmi_window_exits;
6328         kvm_make_request(KVM_REQ_EVENT, vcpu);
6329
6330         return 1;
6331 }
6332
6333 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6334 {
6335         struct vcpu_vmx *vmx = to_vmx(vcpu);
6336         enum emulation_result err = EMULATE_DONE;
6337         int ret = 1;
6338         u32 cpu_exec_ctrl;
6339         bool intr_window_requested;
6340         unsigned count = 130;
6341
6342         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6343         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6344
6345         while (vmx->emulation_required && count-- != 0) {
6346                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6347                         return handle_interrupt_window(&vmx->vcpu);
6348
6349                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6350                         return 1;
6351
6352                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6353
6354                 if (err == EMULATE_USER_EXIT) {
6355                         ++vcpu->stat.mmio_exits;
6356                         ret = 0;
6357                         goto out;
6358                 }
6359
6360                 if (err != EMULATE_DONE) {
6361                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6362                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6363                         vcpu->run->internal.ndata = 0;
6364                         return 0;
6365                 }
6366
6367                 if (vcpu->arch.halt_request) {
6368                         vcpu->arch.halt_request = 0;
6369                         ret = kvm_vcpu_halt(vcpu);
6370                         goto out;
6371                 }
6372
6373                 if (signal_pending(current))
6374                         goto out;
6375                 if (need_resched())
6376                         schedule();
6377         }
6378
6379 out:
6380         return ret;
6381 }
6382
6383 static int __grow_ple_window(int val)
6384 {
6385         if (ple_window_grow < 1)
6386                 return ple_window;
6387
6388         val = min(val, ple_window_actual_max);
6389
6390         if (ple_window_grow < ple_window)
6391                 val *= ple_window_grow;
6392         else
6393                 val += ple_window_grow;
6394
6395         return val;
6396 }
6397
6398 static int __shrink_ple_window(int val, int modifier, int minimum)
6399 {
6400         if (modifier < 1)
6401                 return ple_window;
6402
6403         if (modifier < ple_window)
6404                 val /= modifier;
6405         else
6406                 val -= modifier;
6407
6408         return max(val, minimum);
6409 }
6410
6411 static void grow_ple_window(struct kvm_vcpu *vcpu)
6412 {
6413         struct vcpu_vmx *vmx = to_vmx(vcpu);
6414         int old = vmx->ple_window;
6415
6416         vmx->ple_window = __grow_ple_window(old);
6417
6418         if (vmx->ple_window != old)
6419                 vmx->ple_window_dirty = true;
6420
6421         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6422 }
6423
6424 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6425 {
6426         struct vcpu_vmx *vmx = to_vmx(vcpu);
6427         int old = vmx->ple_window;
6428
6429         vmx->ple_window = __shrink_ple_window(old,
6430                                               ple_window_shrink, ple_window);
6431
6432         if (vmx->ple_window != old)
6433                 vmx->ple_window_dirty = true;
6434
6435         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6436 }
6437
6438 /*
6439  * ple_window_actual_max is computed to be one grow_ple_window() below
6440  * ple_window_max. (See __grow_ple_window for the reason.)
6441  * This prevents overflows, because ple_window_max is int.
6442  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6443  * this process.
6444  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6445  */
6446 static void update_ple_window_actual_max(void)
6447 {
6448         ple_window_actual_max =
6449                         __shrink_ple_window(max(ple_window_max, ple_window),
6450                                             ple_window_grow, INT_MIN);
6451 }
6452
6453 /*
6454  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6455  */
6456 static void wakeup_handler(void)
6457 {
6458         struct kvm_vcpu *vcpu;
6459         int cpu = smp_processor_id();
6460
6461         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6462         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6463                         blocked_vcpu_list) {
6464                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6465
6466                 if (pi_test_on(pi_desc) == 1)
6467                         kvm_vcpu_kick(vcpu);
6468         }
6469         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6470 }
6471
6472 void vmx_enable_tdp(void)
6473 {
6474         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6475                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6476                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6477                 0ull, VMX_EPT_EXECUTABLE_MASK,
6478                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6479                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6480
6481         ept_set_mmio_spte_mask();
6482         kvm_enable_tdp();
6483 }
6484
6485 static __init int hardware_setup(void)
6486 {
6487         int r = -ENOMEM, i, msr;
6488
6489         rdmsrl_safe(MSR_EFER, &host_efer);
6490
6491         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6492                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6493
6494         for (i = 0; i < VMX_BITMAP_NR; i++) {
6495                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6496                 if (!vmx_bitmap[i])
6497                         goto out;
6498         }
6499
6500         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6501         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6502         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6503
6504         /*
6505          * Allow direct access to the PC debug port (it is often used for I/O
6506          * delays, but the vmexits simply slow things down).
6507          */
6508         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6509         clear_bit(0x80, vmx_io_bitmap_a);
6510
6511         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6512
6513         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6514         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6515
6516         if (setup_vmcs_config(&vmcs_config) < 0) {
6517                 r = -EIO;
6518                 goto out;
6519         }
6520
6521         if (boot_cpu_has(X86_FEATURE_NX))
6522                 kvm_enable_efer_bits(EFER_NX);
6523
6524         if (!cpu_has_vmx_vpid())
6525                 enable_vpid = 0;
6526         if (!cpu_has_vmx_shadow_vmcs())
6527                 enable_shadow_vmcs = 0;
6528         if (enable_shadow_vmcs)
6529                 init_vmcs_shadow_fields();
6530
6531         if (!cpu_has_vmx_ept() ||
6532             !cpu_has_vmx_ept_4levels()) {
6533                 enable_ept = 0;
6534                 enable_unrestricted_guest = 0;
6535                 enable_ept_ad_bits = 0;
6536         }
6537
6538         if (!cpu_has_vmx_ept_ad_bits())
6539                 enable_ept_ad_bits = 0;
6540
6541         if (!cpu_has_vmx_unrestricted_guest())
6542                 enable_unrestricted_guest = 0;
6543
6544         if (!cpu_has_vmx_flexpriority())
6545                 flexpriority_enabled = 0;
6546
6547         /*
6548          * set_apic_access_page_addr() is used to reload apic access
6549          * page upon invalidation.  No need to do anything if not
6550          * using the APIC_ACCESS_ADDR VMCS field.
6551          */
6552         if (!flexpriority_enabled)
6553                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6554
6555         if (!cpu_has_vmx_tpr_shadow())
6556                 kvm_x86_ops->update_cr8_intercept = NULL;
6557
6558         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6559                 kvm_disable_largepages();
6560
6561         if (!cpu_has_vmx_ple())
6562                 ple_gap = 0;
6563
6564         if (!cpu_has_vmx_apicv()) {
6565                 enable_apicv = 0;
6566                 kvm_x86_ops->sync_pir_to_irr = NULL;
6567         }
6568
6569         if (cpu_has_vmx_tsc_scaling()) {
6570                 kvm_has_tsc_control = true;
6571                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6572                 kvm_tsc_scaling_ratio_frac_bits = 48;
6573         }
6574
6575         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6576         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6577         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6578         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6579         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6580         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6581         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6582
6583         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6584                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6585         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6586                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6587         memcpy(vmx_msr_bitmap_legacy_x2apic,
6588                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6589         memcpy(vmx_msr_bitmap_longmode_x2apic,
6590                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6591
6592         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6593
6594         for (msr = 0x800; msr <= 0x8ff; msr++) {
6595                 if (msr == 0x839 /* TMCCT */)
6596                         continue;
6597                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6598         }
6599
6600         /*
6601          * TPR reads and writes can be virtualized even if virtual interrupt
6602          * delivery is not in use.
6603          */
6604         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6605         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6606
6607         /* EOI */
6608         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6609         /* SELF-IPI */
6610         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6611
6612         if (enable_ept)
6613                 vmx_enable_tdp();
6614         else
6615                 kvm_disable_tdp();
6616
6617         update_ple_window_actual_max();
6618
6619         /*
6620          * Only enable PML when hardware supports PML feature, and both EPT
6621          * and EPT A/D bit features are enabled -- PML depends on them to work.
6622          */
6623         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6624                 enable_pml = 0;
6625
6626         if (!enable_pml) {
6627                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6628                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6629                 kvm_x86_ops->flush_log_dirty = NULL;
6630                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6631         }
6632
6633         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6634                 u64 vmx_msr;
6635
6636                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6637                 cpu_preemption_timer_multi =
6638                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6639         } else {
6640                 kvm_x86_ops->set_hv_timer = NULL;
6641                 kvm_x86_ops->cancel_hv_timer = NULL;
6642         }
6643
6644         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6645
6646         kvm_mce_cap_supported |= MCG_LMCE_P;
6647
6648         return alloc_kvm_area();
6649
6650 out:
6651         for (i = 0; i < VMX_BITMAP_NR; i++)
6652                 free_page((unsigned long)vmx_bitmap[i]);
6653
6654     return r;
6655 }
6656
6657 static __exit void hardware_unsetup(void)
6658 {
6659         int i;
6660
6661         for (i = 0; i < VMX_BITMAP_NR; i++)
6662                 free_page((unsigned long)vmx_bitmap[i]);
6663
6664         free_kvm_area();
6665 }
6666
6667 /*
6668  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6669  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6670  */
6671 static int handle_pause(struct kvm_vcpu *vcpu)
6672 {
6673         if (ple_gap)
6674                 grow_ple_window(vcpu);
6675
6676         kvm_vcpu_on_spin(vcpu);
6677         return kvm_skip_emulated_instruction(vcpu);
6678 }
6679
6680 static int handle_nop(struct kvm_vcpu *vcpu)
6681 {
6682         return kvm_skip_emulated_instruction(vcpu);
6683 }
6684
6685 static int handle_mwait(struct kvm_vcpu *vcpu)
6686 {
6687         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6688         return handle_nop(vcpu);
6689 }
6690
6691 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6692 {
6693         return 1;
6694 }
6695
6696 static int handle_monitor(struct kvm_vcpu *vcpu)
6697 {
6698         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6699         return handle_nop(vcpu);
6700 }
6701
6702 /*
6703  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6704  * We could reuse a single VMCS for all the L2 guests, but we also want the
6705  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6706  * allows keeping them loaded on the processor, and in the future will allow
6707  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6708  * every entry if they never change.
6709  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6710  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6711  *
6712  * The following functions allocate and free a vmcs02 in this pool.
6713  */
6714
6715 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6716 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6717 {
6718         struct vmcs02_list *item;
6719         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6720                 if (item->vmptr == vmx->nested.current_vmptr) {
6721                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6722                         return &item->vmcs02;
6723                 }
6724
6725         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6726                 /* Recycle the least recently used VMCS. */
6727                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6728                                        struct vmcs02_list, list);
6729                 item->vmptr = vmx->nested.current_vmptr;
6730                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6731                 return &item->vmcs02;
6732         }
6733
6734         /* Create a new VMCS */
6735         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6736         if (!item)
6737                 return NULL;
6738         item->vmcs02.vmcs = alloc_vmcs();
6739         item->vmcs02.shadow_vmcs = NULL;
6740         if (!item->vmcs02.vmcs) {
6741                 kfree(item);
6742                 return NULL;
6743         }
6744         loaded_vmcs_init(&item->vmcs02);
6745         item->vmptr = vmx->nested.current_vmptr;
6746         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6747         vmx->nested.vmcs02_num++;
6748         return &item->vmcs02;
6749 }
6750
6751 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6752 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6753 {
6754         struct vmcs02_list *item;
6755         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6756                 if (item->vmptr == vmptr) {
6757                         free_loaded_vmcs(&item->vmcs02);
6758                         list_del(&item->list);
6759                         kfree(item);
6760                         vmx->nested.vmcs02_num--;
6761                         return;
6762                 }
6763 }
6764
6765 /*
6766  * Free all VMCSs saved for this vcpu, except the one pointed by
6767  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6768  * must be &vmx->vmcs01.
6769  */
6770 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6771 {
6772         struct vmcs02_list *item, *n;
6773
6774         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6775         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6776                 /*
6777                  * Something will leak if the above WARN triggers.  Better than
6778                  * a use-after-free.
6779                  */
6780                 if (vmx->loaded_vmcs == &item->vmcs02)
6781                         continue;
6782
6783                 free_loaded_vmcs(&item->vmcs02);
6784                 list_del(&item->list);
6785                 kfree(item);
6786                 vmx->nested.vmcs02_num--;
6787         }
6788 }
6789
6790 /*
6791  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6792  * set the success or error code of an emulated VMX instruction, as specified
6793  * by Vol 2B, VMX Instruction Reference, "Conventions".
6794  */
6795 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6796 {
6797         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6798                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6799                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6800 }
6801
6802 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6803 {
6804         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6805                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6806                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6807                         | X86_EFLAGS_CF);
6808 }
6809
6810 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6811                                         u32 vm_instruction_error)
6812 {
6813         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6814                 /*
6815                  * failValid writes the error number to the current VMCS, which
6816                  * can't be done there isn't a current VMCS.
6817                  */
6818                 nested_vmx_failInvalid(vcpu);
6819                 return;
6820         }
6821         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6822                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6823                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6824                         | X86_EFLAGS_ZF);
6825         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6826         /*
6827          * We don't need to force a shadow sync because
6828          * VM_INSTRUCTION_ERROR is not shadowed
6829          */
6830 }
6831
6832 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6833 {
6834         /* TODO: not to reset guest simply here. */
6835         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6836         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6837 }
6838
6839 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6840 {
6841         struct vcpu_vmx *vmx =
6842                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6843
6844         vmx->nested.preemption_timer_expired = true;
6845         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6846         kvm_vcpu_kick(&vmx->vcpu);
6847
6848         return HRTIMER_NORESTART;
6849 }
6850
6851 /*
6852  * Decode the memory-address operand of a vmx instruction, as recorded on an
6853  * exit caused by such an instruction (run by a guest hypervisor).
6854  * On success, returns 0. When the operand is invalid, returns 1 and throws
6855  * #UD or #GP.
6856  */
6857 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6858                                  unsigned long exit_qualification,
6859                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6860 {
6861         gva_t off;
6862         bool exn;
6863         struct kvm_segment s;
6864
6865         /*
6866          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6867          * Execution", on an exit, vmx_instruction_info holds most of the
6868          * addressing components of the operand. Only the displacement part
6869          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6870          * For how an actual address is calculated from all these components,
6871          * refer to Vol. 1, "Operand Addressing".
6872          */
6873         int  scaling = vmx_instruction_info & 3;
6874         int  addr_size = (vmx_instruction_info >> 7) & 7;
6875         bool is_reg = vmx_instruction_info & (1u << 10);
6876         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6877         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6878         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6879         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6880         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6881
6882         if (is_reg) {
6883                 kvm_queue_exception(vcpu, UD_VECTOR);
6884                 return 1;
6885         }
6886
6887         /* Addr = segment_base + offset */
6888         /* offset = base + [index * scale] + displacement */
6889         off = exit_qualification; /* holds the displacement */
6890         if (base_is_valid)
6891                 off += kvm_register_read(vcpu, base_reg);
6892         if (index_is_valid)
6893                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6894         vmx_get_segment(vcpu, &s, seg_reg);
6895         *ret = s.base + off;
6896
6897         if (addr_size == 1) /* 32 bit */
6898                 *ret &= 0xffffffff;
6899
6900         /* Checks for #GP/#SS exceptions. */
6901         exn = false;
6902         if (is_long_mode(vcpu)) {
6903                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6904                  * non-canonical form. This is the only check on the memory
6905                  * destination for long mode!
6906                  */
6907                 exn = is_noncanonical_address(*ret);
6908         } else if (is_protmode(vcpu)) {
6909                 /* Protected mode: apply checks for segment validity in the
6910                  * following order:
6911                  * - segment type check (#GP(0) may be thrown)
6912                  * - usability check (#GP(0)/#SS(0))
6913                  * - limit check (#GP(0)/#SS(0))
6914                  */
6915                 if (wr)
6916                         /* #GP(0) if the destination operand is located in a
6917                          * read-only data segment or any code segment.
6918                          */
6919                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6920                 else
6921                         /* #GP(0) if the source operand is located in an
6922                          * execute-only code segment
6923                          */
6924                         exn = ((s.type & 0xa) == 8);
6925                 if (exn) {
6926                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6927                         return 1;
6928                 }
6929                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6930                  */
6931                 exn = (s.unusable != 0);
6932                 /* Protected mode: #GP(0)/#SS(0) if the memory
6933                  * operand is outside the segment limit.
6934                  */
6935                 exn = exn || (off + sizeof(u64) > s.limit);
6936         }
6937         if (exn) {
6938                 kvm_queue_exception_e(vcpu,
6939                                       seg_reg == VCPU_SREG_SS ?
6940                                                 SS_VECTOR : GP_VECTOR,
6941                                       0);
6942                 return 1;
6943         }
6944
6945         return 0;
6946 }
6947
6948 /*
6949  * This function performs the various checks including
6950  * - if it's 4KB aligned
6951  * - No bits beyond the physical address width are set
6952  * - Returns 0 on success or else 1
6953  * (Intel SDM Section 30.3)
6954  */
6955 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6956                                   gpa_t *vmpointer)
6957 {
6958         gva_t gva;
6959         gpa_t vmptr;
6960         struct x86_exception e;
6961         struct page *page;
6962         struct vcpu_vmx *vmx = to_vmx(vcpu);
6963         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6964
6965         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6966                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6967                 return 1;
6968
6969         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6970                                 sizeof(vmptr), &e)) {
6971                 kvm_inject_page_fault(vcpu, &e);
6972                 return 1;
6973         }
6974
6975         switch (exit_reason) {
6976         case EXIT_REASON_VMON:
6977                 /*
6978                  * SDM 3: 24.11.5
6979                  * The first 4 bytes of VMXON region contain the supported
6980                  * VMCS revision identifier
6981                  *
6982                  * Note - IA32_VMX_BASIC[48] will never be 1
6983                  * for the nested case;
6984                  * which replaces physical address width with 32
6985                  *
6986                  */
6987                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6988                         nested_vmx_failInvalid(vcpu);
6989                         return kvm_skip_emulated_instruction(vcpu);
6990                 }
6991
6992                 page = nested_get_page(vcpu, vmptr);
6993                 if (page == NULL) {
6994                         nested_vmx_failInvalid(vcpu);
6995                         return kvm_skip_emulated_instruction(vcpu);
6996                 }
6997                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6998                         kunmap(page);
6999                         nested_release_page_clean(page);
7000                         nested_vmx_failInvalid(vcpu);
7001                         return kvm_skip_emulated_instruction(vcpu);
7002                 }
7003                 kunmap(page);
7004                 nested_release_page_clean(page);
7005                 vmx->nested.vmxon_ptr = vmptr;
7006                 break;
7007         case EXIT_REASON_VMCLEAR:
7008                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7009                         nested_vmx_failValid(vcpu,
7010                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7011                         return kvm_skip_emulated_instruction(vcpu);
7012                 }
7013
7014                 if (vmptr == vmx->nested.vmxon_ptr) {
7015                         nested_vmx_failValid(vcpu,
7016                                              VMXERR_VMCLEAR_VMXON_POINTER);
7017                         return kvm_skip_emulated_instruction(vcpu);
7018                 }
7019                 break;
7020         case EXIT_REASON_VMPTRLD:
7021                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7022                         nested_vmx_failValid(vcpu,
7023                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7024                         return kvm_skip_emulated_instruction(vcpu);
7025                 }
7026
7027                 if (vmptr == vmx->nested.vmxon_ptr) {
7028                         nested_vmx_failValid(vcpu,
7029                                              VMXERR_VMPTRLD_VMXON_POINTER);
7030                         return kvm_skip_emulated_instruction(vcpu);
7031                 }
7032                 break;
7033         default:
7034                 return 1; /* shouldn't happen */
7035         }
7036
7037         if (vmpointer)
7038                 *vmpointer = vmptr;
7039         return 0;
7040 }
7041
7042 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7043 {
7044         struct vcpu_vmx *vmx = to_vmx(vcpu);
7045         struct vmcs *shadow_vmcs;
7046
7047         if (cpu_has_vmx_msr_bitmap()) {
7048                 vmx->nested.msr_bitmap =
7049                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7050                 if (!vmx->nested.msr_bitmap)
7051                         goto out_msr_bitmap;
7052         }
7053
7054         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7055         if (!vmx->nested.cached_vmcs12)
7056                 goto out_cached_vmcs12;
7057
7058         if (enable_shadow_vmcs) {
7059                 shadow_vmcs = alloc_vmcs();
7060                 if (!shadow_vmcs)
7061                         goto out_shadow_vmcs;
7062                 /* mark vmcs as shadow */
7063                 shadow_vmcs->revision_id |= (1u << 31);
7064                 /* init shadow vmcs */
7065                 vmcs_clear(shadow_vmcs);
7066                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7067         }
7068
7069         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7070         vmx->nested.vmcs02_num = 0;
7071
7072         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7073                      HRTIMER_MODE_REL_PINNED);
7074         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7075
7076         vmx->nested.vmxon = true;
7077         return 0;
7078
7079 out_shadow_vmcs:
7080         kfree(vmx->nested.cached_vmcs12);
7081
7082 out_cached_vmcs12:
7083         free_page((unsigned long)vmx->nested.msr_bitmap);
7084
7085 out_msr_bitmap:
7086         return -ENOMEM;
7087 }
7088
7089 /*
7090  * Emulate the VMXON instruction.
7091  * Currently, we just remember that VMX is active, and do not save or even
7092  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7093  * do not currently need to store anything in that guest-allocated memory
7094  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7095  * argument is different from the VMXON pointer (which the spec says they do).
7096  */
7097 static int handle_vmon(struct kvm_vcpu *vcpu)
7098 {
7099         int ret;
7100         struct kvm_segment cs;
7101         struct vcpu_vmx *vmx = to_vmx(vcpu);
7102         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7103                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7104
7105         /* The Intel VMX Instruction Reference lists a bunch of bits that
7106          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7107          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7108          * Otherwise, we should fail with #UD. We test these now:
7109          */
7110         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7111             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7112             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7113                 kvm_queue_exception(vcpu, UD_VECTOR);
7114                 return 1;
7115         }
7116
7117         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7118         if (is_long_mode(vcpu) && !cs.l) {
7119                 kvm_queue_exception(vcpu, UD_VECTOR);
7120                 return 1;
7121         }
7122
7123         if (vmx_get_cpl(vcpu)) {
7124                 kvm_inject_gp(vcpu, 0);
7125                 return 1;
7126         }
7127
7128         if (vmx->nested.vmxon) {
7129                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7130                 return kvm_skip_emulated_instruction(vcpu);
7131         }
7132
7133         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7134                         != VMXON_NEEDED_FEATURES) {
7135                 kvm_inject_gp(vcpu, 0);
7136                 return 1;
7137         }
7138
7139         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7140                 return 1;
7141
7142         ret = enter_vmx_operation(vcpu);
7143         if (ret)
7144                 return ret;
7145
7146         nested_vmx_succeed(vcpu);
7147         return kvm_skip_emulated_instruction(vcpu);
7148 }
7149
7150 /*
7151  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7152  * for running VMX instructions (except VMXON, whose prerequisites are
7153  * slightly different). It also specifies what exception to inject otherwise.
7154  */
7155 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7156 {
7157         struct kvm_segment cs;
7158         struct vcpu_vmx *vmx = to_vmx(vcpu);
7159
7160         if (!vmx->nested.vmxon) {
7161                 kvm_queue_exception(vcpu, UD_VECTOR);
7162                 return 0;
7163         }
7164
7165         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7166         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7167             (is_long_mode(vcpu) && !cs.l)) {
7168                 kvm_queue_exception(vcpu, UD_VECTOR);
7169                 return 0;
7170         }
7171
7172         if (vmx_get_cpl(vcpu)) {
7173                 kvm_inject_gp(vcpu, 0);
7174                 return 0;
7175         }
7176
7177         return 1;
7178 }
7179
7180 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7181 {
7182         if (vmx->nested.current_vmptr == -1ull)
7183                 return;
7184
7185         /* current_vmptr and current_vmcs12 are always set/reset together */
7186         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7187                 return;
7188
7189         if (enable_shadow_vmcs) {
7190                 /* copy to memory all shadowed fields in case
7191                    they were modified */
7192                 copy_shadow_to_vmcs12(vmx);
7193                 vmx->nested.sync_shadow_vmcs = false;
7194                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7195                                 SECONDARY_EXEC_SHADOW_VMCS);
7196                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7197         }
7198         vmx->nested.posted_intr_nv = -1;
7199
7200         /* Flush VMCS12 to guest memory */
7201         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7202                VMCS12_SIZE);
7203
7204         kunmap(vmx->nested.current_vmcs12_page);
7205         nested_release_page(vmx->nested.current_vmcs12_page);
7206         vmx->nested.current_vmptr = -1ull;
7207         vmx->nested.current_vmcs12 = NULL;
7208 }
7209
7210 /*
7211  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7212  * just stops using VMX.
7213  */
7214 static void free_nested(struct vcpu_vmx *vmx)
7215 {
7216         if (!vmx->nested.vmxon)
7217                 return;
7218
7219         vmx->nested.vmxon = false;
7220         free_vpid(vmx->nested.vpid02);
7221         nested_release_vmcs12(vmx);
7222         if (vmx->nested.msr_bitmap) {
7223                 free_page((unsigned long)vmx->nested.msr_bitmap);
7224                 vmx->nested.msr_bitmap = NULL;
7225         }
7226         if (enable_shadow_vmcs) {
7227                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7228                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7229                 vmx->vmcs01.shadow_vmcs = NULL;
7230         }
7231         kfree(vmx->nested.cached_vmcs12);
7232         /* Unpin physical memory we referred to in current vmcs02 */
7233         if (vmx->nested.apic_access_page) {
7234                 nested_release_page(vmx->nested.apic_access_page);
7235                 vmx->nested.apic_access_page = NULL;
7236         }
7237         if (vmx->nested.virtual_apic_page) {
7238                 nested_release_page(vmx->nested.virtual_apic_page);
7239                 vmx->nested.virtual_apic_page = NULL;
7240         }
7241         if (vmx->nested.pi_desc_page) {
7242                 kunmap(vmx->nested.pi_desc_page);
7243                 nested_release_page(vmx->nested.pi_desc_page);
7244                 vmx->nested.pi_desc_page = NULL;
7245                 vmx->nested.pi_desc = NULL;
7246         }
7247
7248         nested_free_all_saved_vmcss(vmx);
7249 }
7250
7251 /* Emulate the VMXOFF instruction */
7252 static int handle_vmoff(struct kvm_vcpu *vcpu)
7253 {
7254         if (!nested_vmx_check_permission(vcpu))
7255                 return 1;
7256         free_nested(to_vmx(vcpu));
7257         nested_vmx_succeed(vcpu);
7258         return kvm_skip_emulated_instruction(vcpu);
7259 }
7260
7261 /* Emulate the VMCLEAR instruction */
7262 static int handle_vmclear(struct kvm_vcpu *vcpu)
7263 {
7264         struct vcpu_vmx *vmx = to_vmx(vcpu);
7265         gpa_t vmptr;
7266         struct vmcs12 *vmcs12;
7267         struct page *page;
7268
7269         if (!nested_vmx_check_permission(vcpu))
7270                 return 1;
7271
7272         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7273                 return 1;
7274
7275         if (vmptr == vmx->nested.current_vmptr)
7276                 nested_release_vmcs12(vmx);
7277
7278         page = nested_get_page(vcpu, vmptr);
7279         if (page == NULL) {
7280                 /*
7281                  * For accurate processor emulation, VMCLEAR beyond available
7282                  * physical memory should do nothing at all. However, it is
7283                  * possible that a nested vmx bug, not a guest hypervisor bug,
7284                  * resulted in this case, so let's shut down before doing any
7285                  * more damage:
7286                  */
7287                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7288                 return 1;
7289         }
7290         vmcs12 = kmap(page);
7291         vmcs12->launch_state = 0;
7292         kunmap(page);
7293         nested_release_page(page);
7294
7295         nested_free_vmcs02(vmx, vmptr);
7296
7297         nested_vmx_succeed(vcpu);
7298         return kvm_skip_emulated_instruction(vcpu);
7299 }
7300
7301 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7302
7303 /* Emulate the VMLAUNCH instruction */
7304 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7305 {
7306         return nested_vmx_run(vcpu, true);
7307 }
7308
7309 /* Emulate the VMRESUME instruction */
7310 static int handle_vmresume(struct kvm_vcpu *vcpu)
7311 {
7312
7313         return nested_vmx_run(vcpu, false);
7314 }
7315
7316 enum vmcs_field_type {
7317         VMCS_FIELD_TYPE_U16 = 0,
7318         VMCS_FIELD_TYPE_U64 = 1,
7319         VMCS_FIELD_TYPE_U32 = 2,
7320         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7321 };
7322
7323 static inline int vmcs_field_type(unsigned long field)
7324 {
7325         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7326                 return VMCS_FIELD_TYPE_U32;
7327         return (field >> 13) & 0x3 ;
7328 }
7329
7330 static inline int vmcs_field_readonly(unsigned long field)
7331 {
7332         return (((field >> 10) & 0x3) == 1);
7333 }
7334
7335 /*
7336  * Read a vmcs12 field. Since these can have varying lengths and we return
7337  * one type, we chose the biggest type (u64) and zero-extend the return value
7338  * to that size. Note that the caller, handle_vmread, might need to use only
7339  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7340  * 64-bit fields are to be returned).
7341  */
7342 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7343                                   unsigned long field, u64 *ret)
7344 {
7345         short offset = vmcs_field_to_offset(field);
7346         char *p;
7347
7348         if (offset < 0)
7349                 return offset;
7350
7351         p = ((char *)(get_vmcs12(vcpu))) + offset;
7352
7353         switch (vmcs_field_type(field)) {
7354         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7355                 *ret = *((natural_width *)p);
7356                 return 0;
7357         case VMCS_FIELD_TYPE_U16:
7358                 *ret = *((u16 *)p);
7359                 return 0;
7360         case VMCS_FIELD_TYPE_U32:
7361                 *ret = *((u32 *)p);
7362                 return 0;
7363         case VMCS_FIELD_TYPE_U64:
7364                 *ret = *((u64 *)p);
7365                 return 0;
7366         default:
7367                 WARN_ON(1);
7368                 return -ENOENT;
7369         }
7370 }
7371
7372
7373 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7374                                    unsigned long field, u64 field_value){
7375         short offset = vmcs_field_to_offset(field);
7376         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7377         if (offset < 0)
7378                 return offset;
7379
7380         switch (vmcs_field_type(field)) {
7381         case VMCS_FIELD_TYPE_U16:
7382                 *(u16 *)p = field_value;
7383                 return 0;
7384         case VMCS_FIELD_TYPE_U32:
7385                 *(u32 *)p = field_value;
7386                 return 0;
7387         case VMCS_FIELD_TYPE_U64:
7388                 *(u64 *)p = field_value;
7389                 return 0;
7390         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7391                 *(natural_width *)p = field_value;
7392                 return 0;
7393         default:
7394                 WARN_ON(1);
7395                 return -ENOENT;
7396         }
7397
7398 }
7399
7400 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7401 {
7402         int i;
7403         unsigned long field;
7404         u64 field_value;
7405         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7406         const unsigned long *fields = shadow_read_write_fields;
7407         const int num_fields = max_shadow_read_write_fields;
7408
7409         preempt_disable();
7410
7411         vmcs_load(shadow_vmcs);
7412
7413         for (i = 0; i < num_fields; i++) {
7414                 field = fields[i];
7415                 switch (vmcs_field_type(field)) {
7416                 case VMCS_FIELD_TYPE_U16:
7417                         field_value = vmcs_read16(field);
7418                         break;
7419                 case VMCS_FIELD_TYPE_U32:
7420                         field_value = vmcs_read32(field);
7421                         break;
7422                 case VMCS_FIELD_TYPE_U64:
7423                         field_value = vmcs_read64(field);
7424                         break;
7425                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7426                         field_value = vmcs_readl(field);
7427                         break;
7428                 default:
7429                         WARN_ON(1);
7430                         continue;
7431                 }
7432                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7433         }
7434
7435         vmcs_clear(shadow_vmcs);
7436         vmcs_load(vmx->loaded_vmcs->vmcs);
7437
7438         preempt_enable();
7439 }
7440
7441 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7442 {
7443         const unsigned long *fields[] = {
7444                 shadow_read_write_fields,
7445                 shadow_read_only_fields
7446         };
7447         const int max_fields[] = {
7448                 max_shadow_read_write_fields,
7449                 max_shadow_read_only_fields
7450         };
7451         int i, q;
7452         unsigned long field;
7453         u64 field_value = 0;
7454         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7455
7456         vmcs_load(shadow_vmcs);
7457
7458         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7459                 for (i = 0; i < max_fields[q]; i++) {
7460                         field = fields[q][i];
7461                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7462
7463                         switch (vmcs_field_type(field)) {
7464                         case VMCS_FIELD_TYPE_U16:
7465                                 vmcs_write16(field, (u16)field_value);
7466                                 break;
7467                         case VMCS_FIELD_TYPE_U32:
7468                                 vmcs_write32(field, (u32)field_value);
7469                                 break;
7470                         case VMCS_FIELD_TYPE_U64:
7471                                 vmcs_write64(field, (u64)field_value);
7472                                 break;
7473                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7474                                 vmcs_writel(field, (long)field_value);
7475                                 break;
7476                         default:
7477                                 WARN_ON(1);
7478                                 break;
7479                         }
7480                 }
7481         }
7482
7483         vmcs_clear(shadow_vmcs);
7484         vmcs_load(vmx->loaded_vmcs->vmcs);
7485 }
7486
7487 /*
7488  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7489  * used before) all generate the same failure when it is missing.
7490  */
7491 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7492 {
7493         struct vcpu_vmx *vmx = to_vmx(vcpu);
7494         if (vmx->nested.current_vmptr == -1ull) {
7495                 nested_vmx_failInvalid(vcpu);
7496                 return 0;
7497         }
7498         return 1;
7499 }
7500
7501 static int handle_vmread(struct kvm_vcpu *vcpu)
7502 {
7503         unsigned long field;
7504         u64 field_value;
7505         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7506         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7507         gva_t gva = 0;
7508
7509         if (!nested_vmx_check_permission(vcpu))
7510                 return 1;
7511
7512         if (!nested_vmx_check_vmcs12(vcpu))
7513                 return kvm_skip_emulated_instruction(vcpu);
7514
7515         /* Decode instruction info and find the field to read */
7516         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7517         /* Read the field, zero-extended to a u64 field_value */
7518         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7519                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7520                 return kvm_skip_emulated_instruction(vcpu);
7521         }
7522         /*
7523          * Now copy part of this value to register or memory, as requested.
7524          * Note that the number of bits actually copied is 32 or 64 depending
7525          * on the guest's mode (32 or 64 bit), not on the given field's length.
7526          */
7527         if (vmx_instruction_info & (1u << 10)) {
7528                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7529                         field_value);
7530         } else {
7531                 if (get_vmx_mem_address(vcpu, exit_qualification,
7532                                 vmx_instruction_info, true, &gva))
7533                         return 1;
7534                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7535                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7536                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7537         }
7538
7539         nested_vmx_succeed(vcpu);
7540         return kvm_skip_emulated_instruction(vcpu);
7541 }
7542
7543
7544 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7545 {
7546         unsigned long field;
7547         gva_t gva;
7548         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7549         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7550         /* The value to write might be 32 or 64 bits, depending on L1's long
7551          * mode, and eventually we need to write that into a field of several
7552          * possible lengths. The code below first zero-extends the value to 64
7553          * bit (field_value), and then copies only the appropriate number of
7554          * bits into the vmcs12 field.
7555          */
7556         u64 field_value = 0;
7557         struct x86_exception e;
7558
7559         if (!nested_vmx_check_permission(vcpu))
7560                 return 1;
7561
7562         if (!nested_vmx_check_vmcs12(vcpu))
7563                 return kvm_skip_emulated_instruction(vcpu);
7564
7565         if (vmx_instruction_info & (1u << 10))
7566                 field_value = kvm_register_readl(vcpu,
7567                         (((vmx_instruction_info) >> 3) & 0xf));
7568         else {
7569                 if (get_vmx_mem_address(vcpu, exit_qualification,
7570                                 vmx_instruction_info, false, &gva))
7571                         return 1;
7572                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7573                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7574                         kvm_inject_page_fault(vcpu, &e);
7575                         return 1;
7576                 }
7577         }
7578
7579
7580         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7581         if (vmcs_field_readonly(field)) {
7582                 nested_vmx_failValid(vcpu,
7583                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7584                 return kvm_skip_emulated_instruction(vcpu);
7585         }
7586
7587         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7588                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7589                 return kvm_skip_emulated_instruction(vcpu);
7590         }
7591
7592         nested_vmx_succeed(vcpu);
7593         return kvm_skip_emulated_instruction(vcpu);
7594 }
7595
7596 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7597 {
7598         vmx->nested.current_vmptr = vmptr;
7599         if (enable_shadow_vmcs) {
7600                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7601                               SECONDARY_EXEC_SHADOW_VMCS);
7602                 vmcs_write64(VMCS_LINK_POINTER,
7603                              __pa(vmx->vmcs01.shadow_vmcs));
7604                 vmx->nested.sync_shadow_vmcs = true;
7605         }
7606 }
7607
7608 /* Emulate the VMPTRLD instruction */
7609 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7610 {
7611         struct vcpu_vmx *vmx = to_vmx(vcpu);
7612         gpa_t vmptr;
7613
7614         if (!nested_vmx_check_permission(vcpu))
7615                 return 1;
7616
7617         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7618                 return 1;
7619
7620         if (vmx->nested.current_vmptr != vmptr) {
7621                 struct vmcs12 *new_vmcs12;
7622                 struct page *page;
7623                 page = nested_get_page(vcpu, vmptr);
7624                 if (page == NULL) {
7625                         nested_vmx_failInvalid(vcpu);
7626                         return kvm_skip_emulated_instruction(vcpu);
7627                 }
7628                 new_vmcs12 = kmap(page);
7629                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7630                         kunmap(page);
7631                         nested_release_page_clean(page);
7632                         nested_vmx_failValid(vcpu,
7633                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7634                         return kvm_skip_emulated_instruction(vcpu);
7635                 }
7636
7637                 nested_release_vmcs12(vmx);
7638                 vmx->nested.current_vmcs12 = new_vmcs12;
7639                 vmx->nested.current_vmcs12_page = page;
7640                 /*
7641                  * Load VMCS12 from guest memory since it is not already
7642                  * cached.
7643                  */
7644                 memcpy(vmx->nested.cached_vmcs12,
7645                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7646                 set_current_vmptr(vmx, vmptr);
7647         }
7648
7649         nested_vmx_succeed(vcpu);
7650         return kvm_skip_emulated_instruction(vcpu);
7651 }
7652
7653 /* Emulate the VMPTRST instruction */
7654 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7655 {
7656         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7657         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7658         gva_t vmcs_gva;
7659         struct x86_exception e;
7660
7661         if (!nested_vmx_check_permission(vcpu))
7662                 return 1;
7663
7664         if (get_vmx_mem_address(vcpu, exit_qualification,
7665                         vmx_instruction_info, true, &vmcs_gva))
7666                 return 1;
7667         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7668         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7669                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7670                                  sizeof(u64), &e)) {
7671                 kvm_inject_page_fault(vcpu, &e);
7672                 return 1;
7673         }
7674         nested_vmx_succeed(vcpu);
7675         return kvm_skip_emulated_instruction(vcpu);
7676 }
7677
7678 /* Emulate the INVEPT instruction */
7679 static int handle_invept(struct kvm_vcpu *vcpu)
7680 {
7681         struct vcpu_vmx *vmx = to_vmx(vcpu);
7682         u32 vmx_instruction_info, types;
7683         unsigned long type;
7684         gva_t gva;
7685         struct x86_exception e;
7686         struct {
7687                 u64 eptp, gpa;
7688         } operand;
7689
7690         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7691               SECONDARY_EXEC_ENABLE_EPT) ||
7692             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7693                 kvm_queue_exception(vcpu, UD_VECTOR);
7694                 return 1;
7695         }
7696
7697         if (!nested_vmx_check_permission(vcpu))
7698                 return 1;
7699
7700         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7701                 kvm_queue_exception(vcpu, UD_VECTOR);
7702                 return 1;
7703         }
7704
7705         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7706         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7707
7708         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7709
7710         if (type >= 32 || !(types & (1 << type))) {
7711                 nested_vmx_failValid(vcpu,
7712                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7713                 return kvm_skip_emulated_instruction(vcpu);
7714         }
7715
7716         /* According to the Intel VMX instruction reference, the memory
7717          * operand is read even if it isn't needed (e.g., for type==global)
7718          */
7719         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7720                         vmx_instruction_info, false, &gva))
7721                 return 1;
7722         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7723                                 sizeof(operand), &e)) {
7724                 kvm_inject_page_fault(vcpu, &e);
7725                 return 1;
7726         }
7727
7728         switch (type) {
7729         case VMX_EPT_EXTENT_GLOBAL:
7730         /*
7731          * TODO: track mappings and invalidate
7732          * single context requests appropriately
7733          */
7734         case VMX_EPT_EXTENT_CONTEXT:
7735                 kvm_mmu_sync_roots(vcpu);
7736                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7737                 nested_vmx_succeed(vcpu);
7738                 break;
7739         default:
7740                 BUG_ON(1);
7741                 break;
7742         }
7743
7744         return kvm_skip_emulated_instruction(vcpu);
7745 }
7746
7747 static int handle_invvpid(struct kvm_vcpu *vcpu)
7748 {
7749         struct vcpu_vmx *vmx = to_vmx(vcpu);
7750         u32 vmx_instruction_info;
7751         unsigned long type, types;
7752         gva_t gva;
7753         struct x86_exception e;
7754         int vpid;
7755
7756         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7757               SECONDARY_EXEC_ENABLE_VPID) ||
7758                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7759                 kvm_queue_exception(vcpu, UD_VECTOR);
7760                 return 1;
7761         }
7762
7763         if (!nested_vmx_check_permission(vcpu))
7764                 return 1;
7765
7766         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7767         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7768
7769         types = (vmx->nested.nested_vmx_vpid_caps &
7770                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7771
7772         if (type >= 32 || !(types & (1 << type))) {
7773                 nested_vmx_failValid(vcpu,
7774                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7775                 return kvm_skip_emulated_instruction(vcpu);
7776         }
7777
7778         /* according to the intel vmx instruction reference, the memory
7779          * operand is read even if it isn't needed (e.g., for type==global)
7780          */
7781         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7782                         vmx_instruction_info, false, &gva))
7783                 return 1;
7784         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7785                                 sizeof(u32), &e)) {
7786                 kvm_inject_page_fault(vcpu, &e);
7787                 return 1;
7788         }
7789
7790         switch (type) {
7791         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7792         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7793         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7794                 if (!vpid) {
7795                         nested_vmx_failValid(vcpu,
7796                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7797                         return kvm_skip_emulated_instruction(vcpu);
7798                 }
7799                 break;
7800         case VMX_VPID_EXTENT_ALL_CONTEXT:
7801                 break;
7802         default:
7803                 WARN_ON_ONCE(1);
7804                 return kvm_skip_emulated_instruction(vcpu);
7805         }
7806
7807         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7808         nested_vmx_succeed(vcpu);
7809
7810         return kvm_skip_emulated_instruction(vcpu);
7811 }
7812
7813 static int handle_pml_full(struct kvm_vcpu *vcpu)
7814 {
7815         unsigned long exit_qualification;
7816
7817         trace_kvm_pml_full(vcpu->vcpu_id);
7818
7819         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7820
7821         /*
7822          * PML buffer FULL happened while executing iret from NMI,
7823          * "blocked by NMI" bit has to be set before next VM entry.
7824          */
7825         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7826                         cpu_has_virtual_nmis() &&
7827                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7828                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7829                                 GUEST_INTR_STATE_NMI);
7830
7831         /*
7832          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7833          * here.., and there's no userspace involvement needed for PML.
7834          */
7835         return 1;
7836 }
7837
7838 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7839 {
7840         kvm_lapic_expired_hv_timer(vcpu);
7841         return 1;
7842 }
7843
7844 /*
7845  * The exit handlers return 1 if the exit was handled fully and guest execution
7846  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7847  * to be done to userspace and return 0.
7848  */
7849 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7850         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7851         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7852         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7853         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7854         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7855         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7856         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7857         [EXIT_REASON_CPUID]                   = handle_cpuid,
7858         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7859         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7860         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7861         [EXIT_REASON_HLT]                     = handle_halt,
7862         [EXIT_REASON_INVD]                    = handle_invd,
7863         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7864         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7865         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7866         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7867         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7868         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7869         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7870         [EXIT_REASON_VMREAD]                  = handle_vmread,
7871         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7872         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7873         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7874         [EXIT_REASON_VMON]                    = handle_vmon,
7875         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7876         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7877         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7878         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7879         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7880         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7881         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7882         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7883         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7884         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7885         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7886         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7887         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7888         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7889         [EXIT_REASON_INVEPT]                  = handle_invept,
7890         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7891         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7892         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7893         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7894         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7895 };
7896
7897 static const int kvm_vmx_max_exit_handlers =
7898         ARRAY_SIZE(kvm_vmx_exit_handlers);
7899
7900 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7901                                        struct vmcs12 *vmcs12)
7902 {
7903         unsigned long exit_qualification;
7904         gpa_t bitmap, last_bitmap;
7905         unsigned int port;
7906         int size;
7907         u8 b;
7908
7909         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7910                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7911
7912         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7913
7914         port = exit_qualification >> 16;
7915         size = (exit_qualification & 7) + 1;
7916
7917         last_bitmap = (gpa_t)-1;
7918         b = -1;
7919
7920         while (size > 0) {
7921                 if (port < 0x8000)
7922                         bitmap = vmcs12->io_bitmap_a;
7923                 else if (port < 0x10000)
7924                         bitmap = vmcs12->io_bitmap_b;
7925                 else
7926                         return true;
7927                 bitmap += (port & 0x7fff) / 8;
7928
7929                 if (last_bitmap != bitmap)
7930                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7931                                 return true;
7932                 if (b & (1 << (port & 7)))
7933                         return true;
7934
7935                 port++;
7936                 size--;
7937                 last_bitmap = bitmap;
7938         }
7939
7940         return false;
7941 }
7942
7943 /*
7944  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7945  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7946  * disinterest in the current event (read or write a specific MSR) by using an
7947  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7948  */
7949 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7950         struct vmcs12 *vmcs12, u32 exit_reason)
7951 {
7952         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7953         gpa_t bitmap;
7954
7955         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7956                 return true;
7957
7958         /*
7959          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7960          * for the four combinations of read/write and low/high MSR numbers.
7961          * First we need to figure out which of the four to use:
7962          */
7963         bitmap = vmcs12->msr_bitmap;
7964         if (exit_reason == EXIT_REASON_MSR_WRITE)
7965                 bitmap += 2048;
7966         if (msr_index >= 0xc0000000) {
7967                 msr_index -= 0xc0000000;
7968                 bitmap += 1024;
7969         }
7970
7971         /* Then read the msr_index'th bit from this bitmap: */
7972         if (msr_index < 1024*8) {
7973                 unsigned char b;
7974                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7975                         return true;
7976                 return 1 & (b >> (msr_index & 7));
7977         } else
7978                 return true; /* let L1 handle the wrong parameter */
7979 }
7980
7981 /*
7982  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7983  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7984  * intercept (via guest_host_mask etc.) the current event.
7985  */
7986 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7987         struct vmcs12 *vmcs12)
7988 {
7989         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7990         int cr = exit_qualification & 15;
7991         int reg = (exit_qualification >> 8) & 15;
7992         unsigned long val = kvm_register_readl(vcpu, reg);
7993
7994         switch ((exit_qualification >> 4) & 3) {
7995         case 0: /* mov to cr */
7996                 switch (cr) {
7997                 case 0:
7998                         if (vmcs12->cr0_guest_host_mask &
7999                             (val ^ vmcs12->cr0_read_shadow))
8000                                 return true;
8001                         break;
8002                 case 3:
8003                         if ((vmcs12->cr3_target_count >= 1 &&
8004                                         vmcs12->cr3_target_value0 == val) ||
8005                                 (vmcs12->cr3_target_count >= 2 &&
8006                                         vmcs12->cr3_target_value1 == val) ||
8007                                 (vmcs12->cr3_target_count >= 3 &&
8008                                         vmcs12->cr3_target_value2 == val) ||
8009                                 (vmcs12->cr3_target_count >= 4 &&
8010                                         vmcs12->cr3_target_value3 == val))
8011                                 return false;
8012                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8013                                 return true;
8014                         break;
8015                 case 4:
8016                         if (vmcs12->cr4_guest_host_mask &
8017                             (vmcs12->cr4_read_shadow ^ val))
8018                                 return true;
8019                         break;
8020                 case 8:
8021                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8022                                 return true;
8023                         break;
8024                 }
8025                 break;
8026         case 2: /* clts */
8027                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8028                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8029                         return true;
8030                 break;
8031         case 1: /* mov from cr */
8032                 switch (cr) {
8033                 case 3:
8034                         if (vmcs12->cpu_based_vm_exec_control &
8035                             CPU_BASED_CR3_STORE_EXITING)
8036                                 return true;
8037                         break;
8038                 case 8:
8039                         if (vmcs12->cpu_based_vm_exec_control &
8040                             CPU_BASED_CR8_STORE_EXITING)
8041                                 return true;
8042                         break;
8043                 }
8044                 break;
8045         case 3: /* lmsw */
8046                 /*
8047                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8048                  * cr0. Other attempted changes are ignored, with no exit.
8049                  */
8050                 if (vmcs12->cr0_guest_host_mask & 0xe &
8051                     (val ^ vmcs12->cr0_read_shadow))
8052                         return true;
8053                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8054                     !(vmcs12->cr0_read_shadow & 0x1) &&
8055                     (val & 0x1))
8056                         return true;
8057                 break;
8058         }
8059         return false;
8060 }
8061
8062 /*
8063  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8064  * should handle it ourselves in L0 (and then continue L2). Only call this
8065  * when in is_guest_mode (L2).
8066  */
8067 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8068 {
8069         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8070         struct vcpu_vmx *vmx = to_vmx(vcpu);
8071         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8072         u32 exit_reason = vmx->exit_reason;
8073
8074         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8075                                 vmcs_readl(EXIT_QUALIFICATION),
8076                                 vmx->idt_vectoring_info,
8077                                 intr_info,
8078                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8079                                 KVM_ISA_VMX);
8080
8081         if (vmx->nested.nested_run_pending)
8082                 return false;
8083
8084         if (unlikely(vmx->fail)) {
8085                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8086                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8087                 return true;
8088         }
8089
8090         switch (exit_reason) {
8091         case EXIT_REASON_EXCEPTION_NMI:
8092                 if (is_nmi(intr_info))
8093                         return false;
8094                 else if (is_page_fault(intr_info))
8095                         return enable_ept;
8096                 else if (is_no_device(intr_info) &&
8097                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8098                         return false;
8099                 else if (is_debug(intr_info) &&
8100                          vcpu->guest_debug &
8101                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8102                         return false;
8103                 else if (is_breakpoint(intr_info) &&
8104                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8105                         return false;
8106                 return vmcs12->exception_bitmap &
8107                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8108         case EXIT_REASON_EXTERNAL_INTERRUPT:
8109                 return false;
8110         case EXIT_REASON_TRIPLE_FAULT:
8111                 return true;
8112         case EXIT_REASON_PENDING_INTERRUPT:
8113                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8114         case EXIT_REASON_NMI_WINDOW:
8115                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8116         case EXIT_REASON_TASK_SWITCH:
8117                 return true;
8118         case EXIT_REASON_CPUID:
8119                 return true;
8120         case EXIT_REASON_HLT:
8121                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8122         case EXIT_REASON_INVD:
8123                 return true;
8124         case EXIT_REASON_INVLPG:
8125                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8126         case EXIT_REASON_RDPMC:
8127                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8128         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8129                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8130         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8131         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8132         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8133         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8134         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8135         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8136                 /*
8137                  * VMX instructions trap unconditionally. This allows L1 to
8138                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8139                  */
8140                 return true;
8141         case EXIT_REASON_CR_ACCESS:
8142                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8143         case EXIT_REASON_DR_ACCESS:
8144                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8145         case EXIT_REASON_IO_INSTRUCTION:
8146                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8147         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8148                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8149         case EXIT_REASON_MSR_READ:
8150         case EXIT_REASON_MSR_WRITE:
8151                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8152         case EXIT_REASON_INVALID_STATE:
8153                 return true;
8154         case EXIT_REASON_MWAIT_INSTRUCTION:
8155                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8156         case EXIT_REASON_MONITOR_TRAP_FLAG:
8157                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8158         case EXIT_REASON_MONITOR_INSTRUCTION:
8159                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8160         case EXIT_REASON_PAUSE_INSTRUCTION:
8161                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8162                         nested_cpu_has2(vmcs12,
8163                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8164         case EXIT_REASON_MCE_DURING_VMENTRY:
8165                 return false;
8166         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8167                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8168         case EXIT_REASON_APIC_ACCESS:
8169                 return nested_cpu_has2(vmcs12,
8170                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8171         case EXIT_REASON_APIC_WRITE:
8172         case EXIT_REASON_EOI_INDUCED:
8173                 /* apic_write and eoi_induced should exit unconditionally. */
8174                 return true;
8175         case EXIT_REASON_EPT_VIOLATION:
8176                 /*
8177                  * L0 always deals with the EPT violation. If nested EPT is
8178                  * used, and the nested mmu code discovers that the address is
8179                  * missing in the guest EPT table (EPT12), the EPT violation
8180                  * will be injected with nested_ept_inject_page_fault()
8181                  */
8182                 return false;
8183         case EXIT_REASON_EPT_MISCONFIG:
8184                 /*
8185                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8186                  * table (shadow on EPT) or a merged EPT table that L0 built
8187                  * (EPT on EPT). So any problems with the structure of the
8188                  * table is L0's fault.
8189                  */
8190                 return false;
8191         case EXIT_REASON_WBINVD:
8192                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8193         case EXIT_REASON_XSETBV:
8194                 return true;
8195         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8196                 /*
8197                  * This should never happen, since it is not possible to
8198                  * set XSS to a non-zero value---neither in L1 nor in L2.
8199                  * If if it were, XSS would have to be checked against
8200                  * the XSS exit bitmap in vmcs12.
8201                  */
8202                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8203         case EXIT_REASON_PREEMPTION_TIMER:
8204                 return false;
8205         default:
8206                 return true;
8207         }
8208 }
8209
8210 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8211 {
8212         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8213         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8214 }
8215
8216 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8217 {
8218         if (vmx->pml_pg) {
8219                 __free_page(vmx->pml_pg);
8220                 vmx->pml_pg = NULL;
8221         }
8222 }
8223
8224 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8225 {
8226         struct vcpu_vmx *vmx = to_vmx(vcpu);
8227         u64 *pml_buf;
8228         u16 pml_idx;
8229
8230         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8231
8232         /* Do nothing if PML buffer is empty */
8233         if (pml_idx == (PML_ENTITY_NUM - 1))
8234                 return;
8235
8236         /* PML index always points to next available PML buffer entity */
8237         if (pml_idx >= PML_ENTITY_NUM)
8238                 pml_idx = 0;
8239         else
8240                 pml_idx++;
8241
8242         pml_buf = page_address(vmx->pml_pg);
8243         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8244                 u64 gpa;
8245
8246                 gpa = pml_buf[pml_idx];
8247                 WARN_ON(gpa & (PAGE_SIZE - 1));
8248                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8249         }
8250
8251         /* reset PML index */
8252         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8253 }
8254
8255 /*
8256  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8257  * Called before reporting dirty_bitmap to userspace.
8258  */
8259 static void kvm_flush_pml_buffers(struct kvm *kvm)
8260 {
8261         int i;
8262         struct kvm_vcpu *vcpu;
8263         /*
8264          * We only need to kick vcpu out of guest mode here, as PML buffer
8265          * is flushed at beginning of all VMEXITs, and it's obvious that only
8266          * vcpus running in guest are possible to have unflushed GPAs in PML
8267          * buffer.
8268          */
8269         kvm_for_each_vcpu(i, vcpu, kvm)
8270                 kvm_vcpu_kick(vcpu);
8271 }
8272
8273 static void vmx_dump_sel(char *name, uint32_t sel)
8274 {
8275         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8276                name, vmcs_read32(sel),
8277                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8278                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8279                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8280 }
8281
8282 static void vmx_dump_dtsel(char *name, uint32_t limit)
8283 {
8284         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8285                name, vmcs_read32(limit),
8286                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8287 }
8288
8289 static void dump_vmcs(void)
8290 {
8291         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8292         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8293         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8294         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8295         u32 secondary_exec_control = 0;
8296         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8297         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8298         int i, n;
8299
8300         if (cpu_has_secondary_exec_ctrls())
8301                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8302
8303         pr_err("*** Guest State ***\n");
8304         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8305                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8306                vmcs_readl(CR0_GUEST_HOST_MASK));
8307         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8308                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8309         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8310         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8311             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8312         {
8313                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8314                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8315                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8316                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8317         }
8318         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8319                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8320         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8321                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8322         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8323                vmcs_readl(GUEST_SYSENTER_ESP),
8324                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8325         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8326         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8327         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8328         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8329         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8330         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8331         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8332         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8333         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8334         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8335         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8336             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8337                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8338                        efer, vmcs_read64(GUEST_IA32_PAT));
8339         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8340                vmcs_read64(GUEST_IA32_DEBUGCTL),
8341                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8342         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8343                 pr_err("PerfGlobCtl = 0x%016llx\n",
8344                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8345         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8346                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8347         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8348                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8349                vmcs_read32(GUEST_ACTIVITY_STATE));
8350         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8351                 pr_err("InterruptStatus = %04x\n",
8352                        vmcs_read16(GUEST_INTR_STATUS));
8353
8354         pr_err("*** Host State ***\n");
8355         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8356                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8357         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8358                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8359                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8360                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8361                vmcs_read16(HOST_TR_SELECTOR));
8362         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8363                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8364                vmcs_readl(HOST_TR_BASE));
8365         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8366                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8367         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8368                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8369                vmcs_readl(HOST_CR4));
8370         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8371                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8372                vmcs_read32(HOST_IA32_SYSENTER_CS),
8373                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8374         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8375                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8376                        vmcs_read64(HOST_IA32_EFER),
8377                        vmcs_read64(HOST_IA32_PAT));
8378         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8379                 pr_err("PerfGlobCtl = 0x%016llx\n",
8380                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8381
8382         pr_err("*** Control State ***\n");
8383         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8384                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8385         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8386         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8387                vmcs_read32(EXCEPTION_BITMAP),
8388                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8389                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8390         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8391                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8392                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8393                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8394         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8395                vmcs_read32(VM_EXIT_INTR_INFO),
8396                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8397                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8398         pr_err("        reason=%08x qualification=%016lx\n",
8399                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8400         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8401                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8402                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8403         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8404         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8405                 pr_err("TSC Multiplier = 0x%016llx\n",
8406                        vmcs_read64(TSC_MULTIPLIER));
8407         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8408                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8409         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8410                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8411         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8412                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8413         n = vmcs_read32(CR3_TARGET_COUNT);
8414         for (i = 0; i + 1 < n; i += 4)
8415                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8416                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8417                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8418         if (i < n)
8419                 pr_err("CR3 target%u=%016lx\n",
8420                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8421         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8422                 pr_err("PLE Gap=%08x Window=%08x\n",
8423                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8424         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8425                 pr_err("Virtual processor ID = 0x%04x\n",
8426                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8427 }
8428
8429 /*
8430  * The guest has exited.  See if we can fix it or if we need userspace
8431  * assistance.
8432  */
8433 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8434 {
8435         struct vcpu_vmx *vmx = to_vmx(vcpu);
8436         u32 exit_reason = vmx->exit_reason;
8437         u32 vectoring_info = vmx->idt_vectoring_info;
8438
8439         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8440         vcpu->arch.gpa_available = false;
8441
8442         /*
8443          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8444          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8445          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8446          * mode as if vcpus is in root mode, the PML buffer must has been
8447          * flushed already.
8448          */
8449         if (enable_pml)
8450                 vmx_flush_pml_buffer(vcpu);
8451
8452         /* If guest state is invalid, start emulating */
8453         if (vmx->emulation_required)
8454                 return handle_invalid_guest_state(vcpu);
8455
8456         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8457                 nested_vmx_vmexit(vcpu, exit_reason,
8458                                   vmcs_read32(VM_EXIT_INTR_INFO),
8459                                   vmcs_readl(EXIT_QUALIFICATION));
8460                 return 1;
8461         }
8462
8463         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8464                 dump_vmcs();
8465                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8466                 vcpu->run->fail_entry.hardware_entry_failure_reason
8467                         = exit_reason;
8468                 return 0;
8469         }
8470
8471         if (unlikely(vmx->fail)) {
8472                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8473                 vcpu->run->fail_entry.hardware_entry_failure_reason
8474                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8475                 return 0;
8476         }
8477
8478         /*
8479          * Note:
8480          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8481          * delivery event since it indicates guest is accessing MMIO.
8482          * The vm-exit can be triggered again after return to guest that
8483          * will cause infinite loop.
8484          */
8485         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8486                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8487                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8488                         exit_reason != EXIT_REASON_PML_FULL &&
8489                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8490                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8491                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8492                 vcpu->run->internal.ndata = 2;
8493                 vcpu->run->internal.data[0] = vectoring_info;
8494                 vcpu->run->internal.data[1] = exit_reason;
8495                 return 0;
8496         }
8497
8498         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8499             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8500                                         get_vmcs12(vcpu))))) {
8501                 if (vmx_interrupt_allowed(vcpu)) {
8502                         vmx->soft_vnmi_blocked = 0;
8503                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8504                            vcpu->arch.nmi_pending) {
8505                         /*
8506                          * This CPU don't support us in finding the end of an
8507                          * NMI-blocked window if the guest runs with IRQs
8508                          * disabled. So we pull the trigger after 1 s of
8509                          * futile waiting, but inform the user about this.
8510                          */
8511                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8512                                "state on VCPU %d after 1 s timeout\n",
8513                                __func__, vcpu->vcpu_id);
8514                         vmx->soft_vnmi_blocked = 0;
8515                 }
8516         }
8517
8518         if (exit_reason < kvm_vmx_max_exit_handlers
8519             && kvm_vmx_exit_handlers[exit_reason])
8520                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8521         else {
8522                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8523                 kvm_queue_exception(vcpu, UD_VECTOR);
8524                 return 1;
8525         }
8526 }
8527
8528 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8529 {
8530         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8531
8532         if (is_guest_mode(vcpu) &&
8533                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8534                 return;
8535
8536         if (irr == -1 || tpr < irr) {
8537                 vmcs_write32(TPR_THRESHOLD, 0);
8538                 return;
8539         }
8540
8541         vmcs_write32(TPR_THRESHOLD, irr);
8542 }
8543
8544 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8545 {
8546         u32 sec_exec_control;
8547
8548         /* Postpone execution until vmcs01 is the current VMCS. */
8549         if (is_guest_mode(vcpu)) {
8550                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8551                 return;
8552         }
8553
8554         if (!cpu_has_vmx_virtualize_x2apic_mode())
8555                 return;
8556
8557         if (!cpu_need_tpr_shadow(vcpu))
8558                 return;
8559
8560         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8561
8562         if (set) {
8563                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8564                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8565         } else {
8566                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8567                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8568         }
8569         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8570
8571         vmx_set_msr_bitmap(vcpu);
8572 }
8573
8574 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8575 {
8576         struct vcpu_vmx *vmx = to_vmx(vcpu);
8577
8578         /*
8579          * Currently we do not handle the nested case where L2 has an
8580          * APIC access page of its own; that page is still pinned.
8581          * Hence, we skip the case where the VCPU is in guest mode _and_
8582          * L1 prepared an APIC access page for L2.
8583          *
8584          * For the case where L1 and L2 share the same APIC access page
8585          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8586          * in the vmcs12), this function will only update either the vmcs01
8587          * or the vmcs02.  If the former, the vmcs02 will be updated by
8588          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8589          * the next L2->L1 exit.
8590          */
8591         if (!is_guest_mode(vcpu) ||
8592             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8593                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8594                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8595 }
8596
8597 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8598 {
8599         u16 status;
8600         u8 old;
8601
8602         if (max_isr == -1)
8603                 max_isr = 0;
8604
8605         status = vmcs_read16(GUEST_INTR_STATUS);
8606         old = status >> 8;
8607         if (max_isr != old) {
8608                 status &= 0xff;
8609                 status |= max_isr << 8;
8610                 vmcs_write16(GUEST_INTR_STATUS, status);
8611         }
8612 }
8613
8614 static void vmx_set_rvi(int vector)
8615 {
8616         u16 status;
8617         u8 old;
8618
8619         if (vector == -1)
8620                 vector = 0;
8621
8622         status = vmcs_read16(GUEST_INTR_STATUS);
8623         old = (u8)status & 0xff;
8624         if ((u8)vector != old) {
8625                 status &= ~0xff;
8626                 status |= (u8)vector;
8627                 vmcs_write16(GUEST_INTR_STATUS, status);
8628         }
8629 }
8630
8631 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8632 {
8633         if (!is_guest_mode(vcpu)) {
8634                 vmx_set_rvi(max_irr);
8635                 return;
8636         }
8637
8638         if (max_irr == -1)
8639                 return;
8640
8641         /*
8642          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8643          * handles it.
8644          */
8645         if (nested_exit_on_intr(vcpu))
8646                 return;
8647
8648         /*
8649          * Else, fall back to pre-APICv interrupt injection since L2
8650          * is run without virtual interrupt delivery.
8651          */
8652         if (!kvm_event_needs_reinjection(vcpu) &&
8653             vmx_interrupt_allowed(vcpu)) {
8654                 kvm_queue_interrupt(vcpu, max_irr, false);
8655                 vmx_inject_irq(vcpu);
8656         }
8657 }
8658
8659 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8660 {
8661         struct vcpu_vmx *vmx = to_vmx(vcpu);
8662         int max_irr;
8663
8664         WARN_ON(!vcpu->arch.apicv_active);
8665         if (pi_test_on(&vmx->pi_desc)) {
8666                 pi_clear_on(&vmx->pi_desc);
8667                 /*
8668                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8669                  * But on x86 this is just a compiler barrier anyway.
8670                  */
8671                 smp_mb__after_atomic();
8672                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8673         } else {
8674                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8675         }
8676         vmx_hwapic_irr_update(vcpu, max_irr);
8677         return max_irr;
8678 }
8679
8680 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8681 {
8682         if (!kvm_vcpu_apicv_active(vcpu))
8683                 return;
8684
8685         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8686         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8687         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8688         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8689 }
8690
8691 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8692 {
8693         struct vcpu_vmx *vmx = to_vmx(vcpu);
8694
8695         pi_clear_on(&vmx->pi_desc);
8696         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8697 }
8698
8699 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8700 {
8701         u32 exit_intr_info;
8702
8703         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8704               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8705                 return;
8706
8707         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8708         exit_intr_info = vmx->exit_intr_info;
8709
8710         /* Handle machine checks before interrupts are enabled */
8711         if (is_machine_check(exit_intr_info))
8712                 kvm_machine_check();
8713
8714         /* We need to handle NMIs before interrupts are enabled */
8715         if (is_nmi(exit_intr_info)) {
8716                 kvm_before_handle_nmi(&vmx->vcpu);
8717                 asm("int $2");
8718                 kvm_after_handle_nmi(&vmx->vcpu);
8719         }
8720 }
8721
8722 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8723 {
8724         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8725         register void *__sp asm(_ASM_SP);
8726
8727         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8728                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8729                 unsigned int vector;
8730                 unsigned long entry;
8731                 gate_desc *desc;
8732                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8733 #ifdef CONFIG_X86_64
8734                 unsigned long tmp;
8735 #endif
8736
8737                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8738                 desc = (gate_desc *)vmx->host_idt_base + vector;
8739                 entry = gate_offset(*desc);
8740                 asm volatile(
8741 #ifdef CONFIG_X86_64
8742                         "mov %%" _ASM_SP ", %[sp]\n\t"
8743                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8744                         "push $%c[ss]\n\t"
8745                         "push %[sp]\n\t"
8746 #endif
8747                         "pushf\n\t"
8748                         __ASM_SIZE(push) " $%c[cs]\n\t"
8749                         "call *%[entry]\n\t"
8750                         :
8751 #ifdef CONFIG_X86_64
8752                         [sp]"=&r"(tmp),
8753 #endif
8754                         "+r"(__sp)
8755                         :
8756                         [entry]"r"(entry),
8757                         [ss]"i"(__KERNEL_DS),
8758                         [cs]"i"(__KERNEL_CS)
8759                         );
8760         }
8761 }
8762
8763 static bool vmx_has_high_real_mode_segbase(void)
8764 {
8765         return enable_unrestricted_guest || emulate_invalid_guest_state;
8766 }
8767
8768 static bool vmx_mpx_supported(void)
8769 {
8770         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8771                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8772 }
8773
8774 static bool vmx_xsaves_supported(void)
8775 {
8776         return vmcs_config.cpu_based_2nd_exec_ctrl &
8777                 SECONDARY_EXEC_XSAVES;
8778 }
8779
8780 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8781 {
8782         u32 exit_intr_info;
8783         bool unblock_nmi;
8784         u8 vector;
8785         bool idtv_info_valid;
8786
8787         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8788
8789         if (cpu_has_virtual_nmis()) {
8790                 if (vmx->nmi_known_unmasked)
8791                         return;
8792                 /*
8793                  * Can't use vmx->exit_intr_info since we're not sure what
8794                  * the exit reason is.
8795                  */
8796                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8797                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8798                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8799                 /*
8800                  * SDM 3: 27.7.1.2 (September 2008)
8801                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8802                  * a guest IRET fault.
8803                  * SDM 3: 23.2.2 (September 2008)
8804                  * Bit 12 is undefined in any of the following cases:
8805                  *  If the VM exit sets the valid bit in the IDT-vectoring
8806                  *   information field.
8807                  *  If the VM exit is due to a double fault.
8808                  */
8809                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8810                     vector != DF_VECTOR && !idtv_info_valid)
8811                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8812                                       GUEST_INTR_STATE_NMI);
8813                 else
8814                         vmx->nmi_known_unmasked =
8815                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8816                                   & GUEST_INTR_STATE_NMI);
8817         } else if (unlikely(vmx->soft_vnmi_blocked))
8818                 vmx->vnmi_blocked_time +=
8819                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8820 }
8821
8822 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8823                                       u32 idt_vectoring_info,
8824                                       int instr_len_field,
8825                                       int error_code_field)
8826 {
8827         u8 vector;
8828         int type;
8829         bool idtv_info_valid;
8830
8831         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8832
8833         vcpu->arch.nmi_injected = false;
8834         kvm_clear_exception_queue(vcpu);
8835         kvm_clear_interrupt_queue(vcpu);
8836
8837         if (!idtv_info_valid)
8838                 return;
8839
8840         kvm_make_request(KVM_REQ_EVENT, vcpu);
8841
8842         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8843         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8844
8845         switch (type) {
8846         case INTR_TYPE_NMI_INTR:
8847                 vcpu->arch.nmi_injected = true;
8848                 /*
8849                  * SDM 3: 27.7.1.2 (September 2008)
8850                  * Clear bit "block by NMI" before VM entry if a NMI
8851                  * delivery faulted.
8852                  */
8853                 vmx_set_nmi_mask(vcpu, false);
8854                 break;
8855         case INTR_TYPE_SOFT_EXCEPTION:
8856                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8857                 /* fall through */
8858         case INTR_TYPE_HARD_EXCEPTION:
8859                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8860                         u32 err = vmcs_read32(error_code_field);
8861                         kvm_requeue_exception_e(vcpu, vector, err);
8862                 } else
8863                         kvm_requeue_exception(vcpu, vector);
8864                 break;
8865         case INTR_TYPE_SOFT_INTR:
8866                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8867                 /* fall through */
8868         case INTR_TYPE_EXT_INTR:
8869                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8870                 break;
8871         default:
8872                 break;
8873         }
8874 }
8875
8876 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8877 {
8878         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8879                                   VM_EXIT_INSTRUCTION_LEN,
8880                                   IDT_VECTORING_ERROR_CODE);
8881 }
8882
8883 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8884 {
8885         __vmx_complete_interrupts(vcpu,
8886                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8887                                   VM_ENTRY_INSTRUCTION_LEN,
8888                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8889
8890         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8891 }
8892
8893 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8894 {
8895         int i, nr_msrs;
8896         struct perf_guest_switch_msr *msrs;
8897
8898         msrs = perf_guest_get_msrs(&nr_msrs);
8899
8900         if (!msrs)
8901                 return;
8902
8903         for (i = 0; i < nr_msrs; i++)
8904                 if (msrs[i].host == msrs[i].guest)
8905                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8906                 else
8907                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8908                                         msrs[i].host);
8909 }
8910
8911 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8912 {
8913         struct vcpu_vmx *vmx = to_vmx(vcpu);
8914         u64 tscl;
8915         u32 delta_tsc;
8916
8917         if (vmx->hv_deadline_tsc == -1)
8918                 return;
8919
8920         tscl = rdtsc();
8921         if (vmx->hv_deadline_tsc > tscl)
8922                 /* sure to be 32 bit only because checked on set_hv_timer */
8923                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8924                         cpu_preemption_timer_multi);
8925         else
8926                 delta_tsc = 0;
8927
8928         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8929 }
8930
8931 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8932 {
8933         struct vcpu_vmx *vmx = to_vmx(vcpu);
8934         unsigned long debugctlmsr, cr4;
8935
8936         /* Record the guest's net vcpu time for enforced NMI injections. */
8937         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8938                 vmx->entry_time = ktime_get();
8939
8940         /* Don't enter VMX if guest state is invalid, let the exit handler
8941            start emulation until we arrive back to a valid state */
8942         if (vmx->emulation_required)
8943                 return;
8944
8945         if (vmx->ple_window_dirty) {
8946                 vmx->ple_window_dirty = false;
8947                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8948         }
8949
8950         if (vmx->nested.sync_shadow_vmcs) {
8951                 copy_vmcs12_to_shadow(vmx);
8952                 vmx->nested.sync_shadow_vmcs = false;
8953         }
8954
8955         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8956                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8957         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8958                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8959
8960         cr4 = cr4_read_shadow();
8961         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8962                 vmcs_writel(HOST_CR4, cr4);
8963                 vmx->host_state.vmcs_host_cr4 = cr4;
8964         }
8965
8966         /* When single-stepping over STI and MOV SS, we must clear the
8967          * corresponding interruptibility bits in the guest state. Otherwise
8968          * vmentry fails as it then expects bit 14 (BS) in pending debug
8969          * exceptions being set, but that's not correct for the guest debugging
8970          * case. */
8971         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8972                 vmx_set_interrupt_shadow(vcpu, 0);
8973
8974         if (vmx->guest_pkru_valid)
8975                 __write_pkru(vmx->guest_pkru);
8976
8977         atomic_switch_perf_msrs(vmx);
8978         debugctlmsr = get_debugctlmsr();
8979
8980         vmx_arm_hv_timer(vcpu);
8981
8982         vmx->__launched = vmx->loaded_vmcs->launched;
8983         asm(
8984                 /* Store host registers */
8985                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8986                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8987                 "push %%" _ASM_CX " \n\t"
8988                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8989                 "je 1f \n\t"
8990                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8991                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8992                 "1: \n\t"
8993                 /* Reload cr2 if changed */
8994                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8995                 "mov %%cr2, %%" _ASM_DX " \n\t"
8996                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8997                 "je 2f \n\t"
8998                 "mov %%" _ASM_AX", %%cr2 \n\t"
8999                 "2: \n\t"
9000                 /* Check if vmlaunch of vmresume is needed */
9001                 "cmpl $0, %c[launched](%0) \n\t"
9002                 /* Load guest registers.  Don't clobber flags. */
9003                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9004                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9005                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9006                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9007                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9008                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9009 #ifdef CONFIG_X86_64
9010                 "mov %c[r8](%0),  %%r8  \n\t"
9011                 "mov %c[r9](%0),  %%r9  \n\t"
9012                 "mov %c[r10](%0), %%r10 \n\t"
9013                 "mov %c[r11](%0), %%r11 \n\t"
9014                 "mov %c[r12](%0), %%r12 \n\t"
9015                 "mov %c[r13](%0), %%r13 \n\t"
9016                 "mov %c[r14](%0), %%r14 \n\t"
9017                 "mov %c[r15](%0), %%r15 \n\t"
9018 #endif
9019                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9020
9021                 /* Enter guest mode */
9022                 "jne 1f \n\t"
9023                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9024                 "jmp 2f \n\t"
9025                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9026                 "2: "
9027                 /* Save guest registers, load host registers, keep flags */
9028                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9029                 "pop %0 \n\t"
9030                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9031                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9032                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9033                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9034                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9035                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9036                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9037 #ifdef CONFIG_X86_64
9038                 "mov %%r8,  %c[r8](%0) \n\t"
9039                 "mov %%r9,  %c[r9](%0) \n\t"
9040                 "mov %%r10, %c[r10](%0) \n\t"
9041                 "mov %%r11, %c[r11](%0) \n\t"
9042                 "mov %%r12, %c[r12](%0) \n\t"
9043                 "mov %%r13, %c[r13](%0) \n\t"
9044                 "mov %%r14, %c[r14](%0) \n\t"
9045                 "mov %%r15, %c[r15](%0) \n\t"
9046 #endif
9047                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9048                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9049
9050                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9051                 "setbe %c[fail](%0) \n\t"
9052                 ".pushsection .rodata \n\t"
9053                 ".global vmx_return \n\t"
9054                 "vmx_return: " _ASM_PTR " 2b \n\t"
9055                 ".popsection"
9056               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9057                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9058                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9059                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9060                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9061                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9062                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9063                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9064                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9065                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9066                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9067 #ifdef CONFIG_X86_64
9068                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9069                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9070                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9071                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9072                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9073                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9074                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9075                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9076 #endif
9077                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9078                 [wordsize]"i"(sizeof(ulong))
9079               : "cc", "memory"
9080 #ifdef CONFIG_X86_64
9081                 , "rax", "rbx", "rdi", "rsi"
9082                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9083 #else
9084                 , "eax", "ebx", "edi", "esi"
9085 #endif
9086               );
9087
9088         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9089         if (debugctlmsr)
9090                 update_debugctlmsr(debugctlmsr);
9091
9092 #ifndef CONFIG_X86_64
9093         /*
9094          * The sysexit path does not restore ds/es, so we must set them to
9095          * a reasonable value ourselves.
9096          *
9097          * We can't defer this to vmx_load_host_state() since that function
9098          * may be executed in interrupt context, which saves and restore segments
9099          * around it, nullifying its effect.
9100          */
9101         loadsegment(ds, __USER_DS);
9102         loadsegment(es, __USER_DS);
9103 #endif
9104
9105         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9106                                   | (1 << VCPU_EXREG_RFLAGS)
9107                                   | (1 << VCPU_EXREG_PDPTR)
9108                                   | (1 << VCPU_EXREG_SEGMENTS)
9109                                   | (1 << VCPU_EXREG_CR3));
9110         vcpu->arch.regs_dirty = 0;
9111
9112         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9113
9114         vmx->loaded_vmcs->launched = 1;
9115
9116         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9117
9118         /*
9119          * eager fpu is enabled if PKEY is supported and CR4 is switched
9120          * back on host, so it is safe to read guest PKRU from current
9121          * XSAVE.
9122          */
9123         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9124                 vmx->guest_pkru = __read_pkru();
9125                 if (vmx->guest_pkru != vmx->host_pkru) {
9126                         vmx->guest_pkru_valid = true;
9127                         __write_pkru(vmx->host_pkru);
9128                 } else
9129                         vmx->guest_pkru_valid = false;
9130         }
9131
9132         /*
9133          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9134          * we did not inject a still-pending event to L1 now because of
9135          * nested_run_pending, we need to re-enable this bit.
9136          */
9137         if (vmx->nested.nested_run_pending)
9138                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9139
9140         vmx->nested.nested_run_pending = 0;
9141
9142         vmx_complete_atomic_exit(vmx);
9143         vmx_recover_nmi_blocking(vmx);
9144         vmx_complete_interrupts(vmx);
9145 }
9146
9147 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9148 {
9149         struct vcpu_vmx *vmx = to_vmx(vcpu);
9150         int cpu;
9151
9152         if (vmx->loaded_vmcs == &vmx->vmcs01)
9153                 return;
9154
9155         cpu = get_cpu();
9156         vmx->loaded_vmcs = &vmx->vmcs01;
9157         vmx_vcpu_put(vcpu);
9158         vmx_vcpu_load(vcpu, cpu);
9159         vcpu->cpu = cpu;
9160         put_cpu();
9161 }
9162
9163 /*
9164  * Ensure that the current vmcs of the logical processor is the
9165  * vmcs01 of the vcpu before calling free_nested().
9166  */
9167 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9168 {
9169        struct vcpu_vmx *vmx = to_vmx(vcpu);
9170        int r;
9171
9172        r = vcpu_load(vcpu);
9173        BUG_ON(r);
9174        vmx_load_vmcs01(vcpu);
9175        free_nested(vmx);
9176        vcpu_put(vcpu);
9177 }
9178
9179 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9180 {
9181         struct vcpu_vmx *vmx = to_vmx(vcpu);
9182
9183         if (enable_pml)
9184                 vmx_destroy_pml_buffer(vmx);
9185         free_vpid(vmx->vpid);
9186         leave_guest_mode(vcpu);
9187         vmx_free_vcpu_nested(vcpu);
9188         free_loaded_vmcs(vmx->loaded_vmcs);
9189         kfree(vmx->guest_msrs);
9190         kvm_vcpu_uninit(vcpu);
9191         kmem_cache_free(kvm_vcpu_cache, vmx);
9192 }
9193
9194 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9195 {
9196         int err;
9197         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9198         int cpu;
9199
9200         if (!vmx)
9201                 return ERR_PTR(-ENOMEM);
9202
9203         vmx->vpid = allocate_vpid();
9204
9205         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9206         if (err)
9207                 goto free_vcpu;
9208
9209         err = -ENOMEM;
9210
9211         /*
9212          * If PML is turned on, failure on enabling PML just results in failure
9213          * of creating the vcpu, therefore we can simplify PML logic (by
9214          * avoiding dealing with cases, such as enabling PML partially on vcpus
9215          * for the guest, etc.
9216          */
9217         if (enable_pml) {
9218                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9219                 if (!vmx->pml_pg)
9220                         goto uninit_vcpu;
9221         }
9222
9223         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9224         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9225                      > PAGE_SIZE);
9226
9227         if (!vmx->guest_msrs)
9228                 goto free_pml;
9229
9230         vmx->loaded_vmcs = &vmx->vmcs01;
9231         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9232         vmx->loaded_vmcs->shadow_vmcs = NULL;
9233         if (!vmx->loaded_vmcs->vmcs)
9234                 goto free_msrs;
9235         if (!vmm_exclusive)
9236                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9237         loaded_vmcs_init(vmx->loaded_vmcs);
9238         if (!vmm_exclusive)
9239                 kvm_cpu_vmxoff();
9240
9241         cpu = get_cpu();
9242         vmx_vcpu_load(&vmx->vcpu, cpu);
9243         vmx->vcpu.cpu = cpu;
9244         err = vmx_vcpu_setup(vmx);
9245         vmx_vcpu_put(&vmx->vcpu);
9246         put_cpu();
9247         if (err)
9248                 goto free_vmcs;
9249         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9250                 err = alloc_apic_access_page(kvm);
9251                 if (err)
9252                         goto free_vmcs;
9253         }
9254
9255         if (enable_ept) {
9256                 if (!kvm->arch.ept_identity_map_addr)
9257                         kvm->arch.ept_identity_map_addr =
9258                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9259                 err = init_rmode_identity_map(kvm);
9260                 if (err)
9261                         goto free_vmcs;
9262         }
9263
9264         if (nested) {
9265                 nested_vmx_setup_ctls_msrs(vmx);
9266                 vmx->nested.vpid02 = allocate_vpid();
9267         }
9268
9269         vmx->nested.posted_intr_nv = -1;
9270         vmx->nested.current_vmptr = -1ull;
9271         vmx->nested.current_vmcs12 = NULL;
9272
9273         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9274
9275         return &vmx->vcpu;
9276
9277 free_vmcs:
9278         free_vpid(vmx->nested.vpid02);
9279         free_loaded_vmcs(vmx->loaded_vmcs);
9280 free_msrs:
9281         kfree(vmx->guest_msrs);
9282 free_pml:
9283         vmx_destroy_pml_buffer(vmx);
9284 uninit_vcpu:
9285         kvm_vcpu_uninit(&vmx->vcpu);
9286 free_vcpu:
9287         free_vpid(vmx->vpid);
9288         kmem_cache_free(kvm_vcpu_cache, vmx);
9289         return ERR_PTR(err);
9290 }
9291
9292 static void __init vmx_check_processor_compat(void *rtn)
9293 {
9294         struct vmcs_config vmcs_conf;
9295
9296         *(int *)rtn = 0;
9297         if (setup_vmcs_config(&vmcs_conf) < 0)
9298                 *(int *)rtn = -EIO;
9299         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9300                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9301                                 smp_processor_id());
9302                 *(int *)rtn = -EIO;
9303         }
9304 }
9305
9306 static int get_ept_level(void)
9307 {
9308         return VMX_EPT_DEFAULT_GAW + 1;
9309 }
9310
9311 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9312 {
9313         u8 cache;
9314         u64 ipat = 0;
9315
9316         /* For VT-d and EPT combination
9317          * 1. MMIO: always map as UC
9318          * 2. EPT with VT-d:
9319          *   a. VT-d without snooping control feature: can't guarantee the
9320          *      result, try to trust guest.
9321          *   b. VT-d with snooping control feature: snooping control feature of
9322          *      VT-d engine can guarantee the cache correctness. Just set it
9323          *      to WB to keep consistent with host. So the same as item 3.
9324          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9325          *    consistent with host MTRR
9326          */
9327         if (is_mmio) {
9328                 cache = MTRR_TYPE_UNCACHABLE;
9329                 goto exit;
9330         }
9331
9332         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9333                 ipat = VMX_EPT_IPAT_BIT;
9334                 cache = MTRR_TYPE_WRBACK;
9335                 goto exit;
9336         }
9337
9338         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9339                 ipat = VMX_EPT_IPAT_BIT;
9340                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9341                         cache = MTRR_TYPE_WRBACK;
9342                 else
9343                         cache = MTRR_TYPE_UNCACHABLE;
9344                 goto exit;
9345         }
9346
9347         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9348
9349 exit:
9350         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9351 }
9352
9353 static int vmx_get_lpage_level(void)
9354 {
9355         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9356                 return PT_DIRECTORY_LEVEL;
9357         else
9358                 /* For shadow and EPT supported 1GB page */
9359                 return PT_PDPE_LEVEL;
9360 }
9361
9362 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9363 {
9364         /*
9365          * These bits in the secondary execution controls field
9366          * are dynamic, the others are mostly based on the hypervisor
9367          * architecture and the guest's CPUID.  Do not touch the
9368          * dynamic bits.
9369          */
9370         u32 mask =
9371                 SECONDARY_EXEC_SHADOW_VMCS |
9372                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9373                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9374
9375         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9376
9377         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9378                      (new_ctl & ~mask) | (cur_ctl & mask));
9379 }
9380
9381 /*
9382  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9383  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9384  */
9385 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9386 {
9387         struct vcpu_vmx *vmx = to_vmx(vcpu);
9388         struct kvm_cpuid_entry2 *entry;
9389
9390         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9391         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9392
9393 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9394         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9395                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9396 } while (0)
9397
9398         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9399         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9400         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9401         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9402         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9403         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9404         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9405         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9406         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9407         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9408         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9409         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9410         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9411         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9412         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9413
9414         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9415         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9416         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9417         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9418         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9419         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9420         cr4_fixed1_update(bit(11),            ecx, bit(2));
9421
9422 #undef cr4_fixed1_update
9423 }
9424
9425 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9426 {
9427         struct kvm_cpuid_entry2 *best;
9428         struct vcpu_vmx *vmx = to_vmx(vcpu);
9429         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9430
9431         if (vmx_rdtscp_supported()) {
9432                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9433                 if (!rdtscp_enabled)
9434                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9435
9436                 if (nested) {
9437                         if (rdtscp_enabled)
9438                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9439                                         SECONDARY_EXEC_RDTSCP;
9440                         else
9441                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9442                                         ~SECONDARY_EXEC_RDTSCP;
9443                 }
9444         }
9445
9446         /* Exposing INVPCID only when PCID is exposed */
9447         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9448         if (vmx_invpcid_supported() &&
9449             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9450             !guest_cpuid_has_pcid(vcpu))) {
9451                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9452
9453                 if (best)
9454                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9455         }
9456
9457         if (cpu_has_secondary_exec_ctrls())
9458                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9459
9460         if (nested_vmx_allowed(vcpu))
9461                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9462                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9463         else
9464                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9465                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9466
9467         if (nested_vmx_allowed(vcpu))
9468                 nested_vmx_cr_fixed1_bits_update(vcpu);
9469 }
9470
9471 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9472 {
9473         if (func == 1 && nested)
9474                 entry->ecx |= bit(X86_FEATURE_VMX);
9475 }
9476
9477 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9478                 struct x86_exception *fault)
9479 {
9480         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9481         u32 exit_reason;
9482
9483         if (fault->error_code & PFERR_RSVD_MASK)
9484                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9485         else
9486                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9487         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9488         vmcs12->guest_physical_address = fault->address;
9489 }
9490
9491 /* Callbacks for nested_ept_init_mmu_context: */
9492
9493 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9494 {
9495         /* return the page table to be shadowed - in our case, EPT12 */
9496         return get_vmcs12(vcpu)->ept_pointer;
9497 }
9498
9499 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9500 {
9501         WARN_ON(mmu_is_nested(vcpu));
9502         kvm_init_shadow_ept_mmu(vcpu,
9503                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9504                         VMX_EPT_EXECUTE_ONLY_BIT);
9505         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9506         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9507         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9508
9509         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9510 }
9511
9512 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9513 {
9514         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9515 }
9516
9517 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9518                                             u16 error_code)
9519 {
9520         bool inequality, bit;
9521
9522         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9523         inequality =
9524                 (error_code & vmcs12->page_fault_error_code_mask) !=
9525                  vmcs12->page_fault_error_code_match;
9526         return inequality ^ bit;
9527 }
9528
9529 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9530                 struct x86_exception *fault)
9531 {
9532         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9533
9534         WARN_ON(!is_guest_mode(vcpu));
9535
9536         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9537                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9538                                   vmcs_read32(VM_EXIT_INTR_INFO),
9539                                   vmcs_readl(EXIT_QUALIFICATION));
9540         else
9541                 kvm_inject_page_fault(vcpu, fault);
9542 }
9543
9544 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9545                                                struct vmcs12 *vmcs12);
9546
9547 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9548                                         struct vmcs12 *vmcs12)
9549 {
9550         struct vcpu_vmx *vmx = to_vmx(vcpu);
9551         u64 hpa;
9552
9553         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9554                 /*
9555                  * Translate L1 physical address to host physical
9556                  * address for vmcs02. Keep the page pinned, so this
9557                  * physical address remains valid. We keep a reference
9558                  * to it so we can release it later.
9559                  */
9560                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9561                         nested_release_page(vmx->nested.apic_access_page);
9562                 vmx->nested.apic_access_page =
9563                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9564                 /*
9565                  * If translation failed, no matter: This feature asks
9566                  * to exit when accessing the given address, and if it
9567                  * can never be accessed, this feature won't do
9568                  * anything anyway.
9569                  */
9570                 if (vmx->nested.apic_access_page) {
9571                         hpa = page_to_phys(vmx->nested.apic_access_page);
9572                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9573                 } else {
9574                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9575                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9576                 }
9577         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9578                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9579                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9580                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9581                 kvm_vcpu_reload_apic_access_page(vcpu);
9582         }
9583
9584         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9585                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9586                         nested_release_page(vmx->nested.virtual_apic_page);
9587                 vmx->nested.virtual_apic_page =
9588                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9589
9590                 /*
9591                  * If translation failed, VM entry will fail because
9592                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9593                  * Failing the vm entry is _not_ what the processor
9594                  * does but it's basically the only possibility we
9595                  * have.  We could still enter the guest if CR8 load
9596                  * exits are enabled, CR8 store exits are enabled, and
9597                  * virtualize APIC access is disabled; in this case
9598                  * the processor would never use the TPR shadow and we
9599                  * could simply clear the bit from the execution
9600                  * control.  But such a configuration is useless, so
9601                  * let's keep the code simple.
9602                  */
9603                 if (vmx->nested.virtual_apic_page) {
9604                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9605                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9606                 }
9607         }
9608
9609         if (nested_cpu_has_posted_intr(vmcs12)) {
9610                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9611                         kunmap(vmx->nested.pi_desc_page);
9612                         nested_release_page(vmx->nested.pi_desc_page);
9613                 }
9614                 vmx->nested.pi_desc_page =
9615                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9616                 vmx->nested.pi_desc =
9617                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9618                 if (!vmx->nested.pi_desc) {
9619                         nested_release_page_clean(vmx->nested.pi_desc_page);
9620                         return;
9621                 }
9622                 vmx->nested.pi_desc =
9623                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9624                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9625                         (PAGE_SIZE - 1)));
9626                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9627                         page_to_phys(vmx->nested.pi_desc_page) +
9628                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9629                         (PAGE_SIZE - 1)));
9630         }
9631         if (cpu_has_vmx_msr_bitmap() &&
9632             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9633             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9634                 ;
9635         else
9636                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9637                                 CPU_BASED_USE_MSR_BITMAPS);
9638 }
9639
9640 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9641 {
9642         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9643         struct vcpu_vmx *vmx = to_vmx(vcpu);
9644
9645         if (vcpu->arch.virtual_tsc_khz == 0)
9646                 return;
9647
9648         /* Make sure short timeouts reliably trigger an immediate vmexit.
9649          * hrtimer_start does not guarantee this. */
9650         if (preemption_timeout <= 1) {
9651                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9652                 return;
9653         }
9654
9655         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9656         preemption_timeout *= 1000000;
9657         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9658         hrtimer_start(&vmx->nested.preemption_timer,
9659                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9660 }
9661
9662 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9663                                                 struct vmcs12 *vmcs12)
9664 {
9665         int maxphyaddr;
9666         u64 addr;
9667
9668         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9669                 return 0;
9670
9671         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9672                 WARN_ON(1);
9673                 return -EINVAL;
9674         }
9675         maxphyaddr = cpuid_maxphyaddr(vcpu);
9676
9677         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9678            ((addr + PAGE_SIZE) >> maxphyaddr))
9679                 return -EINVAL;
9680
9681         return 0;
9682 }
9683
9684 /*
9685  * Merge L0's and L1's MSR bitmap, return false to indicate that
9686  * we do not use the hardware.
9687  */
9688 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9689                                                struct vmcs12 *vmcs12)
9690 {
9691         int msr;
9692         struct page *page;
9693         unsigned long *msr_bitmap_l1;
9694         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9695
9696         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9697         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9698                 return false;
9699
9700         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9701         if (!page) {
9702                 WARN_ON(1);
9703                 return false;
9704         }
9705         msr_bitmap_l1 = (unsigned long *)kmap(page);
9706
9707         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9708
9709         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9710                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9711                         for (msr = 0x800; msr <= 0x8ff; msr++)
9712                                 nested_vmx_disable_intercept_for_msr(
9713                                         msr_bitmap_l1, msr_bitmap_l0,
9714                                         msr, MSR_TYPE_R);
9715
9716                 nested_vmx_disable_intercept_for_msr(
9717                                 msr_bitmap_l1, msr_bitmap_l0,
9718                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9719                                 MSR_TYPE_R | MSR_TYPE_W);
9720
9721                 if (nested_cpu_has_vid(vmcs12)) {
9722                         nested_vmx_disable_intercept_for_msr(
9723                                 msr_bitmap_l1, msr_bitmap_l0,
9724                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9725                                 MSR_TYPE_W);
9726                         nested_vmx_disable_intercept_for_msr(
9727                                 msr_bitmap_l1, msr_bitmap_l0,
9728                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9729                                 MSR_TYPE_W);
9730                 }
9731         }
9732         kunmap(page);
9733         nested_release_page_clean(page);
9734
9735         return true;
9736 }
9737
9738 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9739                                            struct vmcs12 *vmcs12)
9740 {
9741         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9742             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9743             !nested_cpu_has_vid(vmcs12) &&
9744             !nested_cpu_has_posted_intr(vmcs12))
9745                 return 0;
9746
9747         /*
9748          * If virtualize x2apic mode is enabled,
9749          * virtualize apic access must be disabled.
9750          */
9751         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9752             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9753                 return -EINVAL;
9754
9755         /*
9756          * If virtual interrupt delivery is enabled,
9757          * we must exit on external interrupts.
9758          */
9759         if (nested_cpu_has_vid(vmcs12) &&
9760            !nested_exit_on_intr(vcpu))
9761                 return -EINVAL;
9762
9763         /*
9764          * bits 15:8 should be zero in posted_intr_nv,
9765          * the descriptor address has been already checked
9766          * in nested_get_vmcs12_pages.
9767          */
9768         if (nested_cpu_has_posted_intr(vmcs12) &&
9769            (!nested_cpu_has_vid(vmcs12) ||
9770             !nested_exit_intr_ack_set(vcpu) ||
9771             vmcs12->posted_intr_nv & 0xff00))
9772                 return -EINVAL;
9773
9774         /* tpr shadow is needed by all apicv features. */
9775         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9776                 return -EINVAL;
9777
9778         return 0;
9779 }
9780
9781 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9782                                        unsigned long count_field,
9783                                        unsigned long addr_field)
9784 {
9785         int maxphyaddr;
9786         u64 count, addr;
9787
9788         if (vmcs12_read_any(vcpu, count_field, &count) ||
9789             vmcs12_read_any(vcpu, addr_field, &addr)) {
9790                 WARN_ON(1);
9791                 return -EINVAL;
9792         }
9793         if (count == 0)
9794                 return 0;
9795         maxphyaddr = cpuid_maxphyaddr(vcpu);
9796         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9797             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9798                 pr_debug_ratelimited(
9799                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9800                         addr_field, maxphyaddr, count, addr);
9801                 return -EINVAL;
9802         }
9803         return 0;
9804 }
9805
9806 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9807                                                 struct vmcs12 *vmcs12)
9808 {
9809         if (vmcs12->vm_exit_msr_load_count == 0 &&
9810             vmcs12->vm_exit_msr_store_count == 0 &&
9811             vmcs12->vm_entry_msr_load_count == 0)
9812                 return 0; /* Fast path */
9813         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9814                                         VM_EXIT_MSR_LOAD_ADDR) ||
9815             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9816                                         VM_EXIT_MSR_STORE_ADDR) ||
9817             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9818                                         VM_ENTRY_MSR_LOAD_ADDR))
9819                 return -EINVAL;
9820         return 0;
9821 }
9822
9823 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9824                                        struct vmx_msr_entry *e)
9825 {
9826         /* x2APIC MSR accesses are not allowed */
9827         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9828                 return -EINVAL;
9829         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9830             e->index == MSR_IA32_UCODE_REV)
9831                 return -EINVAL;
9832         if (e->reserved != 0)
9833                 return -EINVAL;
9834         return 0;
9835 }
9836
9837 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9838                                      struct vmx_msr_entry *e)
9839 {
9840         if (e->index == MSR_FS_BASE ||
9841             e->index == MSR_GS_BASE ||
9842             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9843             nested_vmx_msr_check_common(vcpu, e))
9844                 return -EINVAL;
9845         return 0;
9846 }
9847
9848 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9849                                       struct vmx_msr_entry *e)
9850 {
9851         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9852             nested_vmx_msr_check_common(vcpu, e))
9853                 return -EINVAL;
9854         return 0;
9855 }
9856
9857 /*
9858  * Load guest's/host's msr at nested entry/exit.
9859  * return 0 for success, entry index for failure.
9860  */
9861 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9862 {
9863         u32 i;
9864         struct vmx_msr_entry e;
9865         struct msr_data msr;
9866
9867         msr.host_initiated = false;
9868         for (i = 0; i < count; i++) {
9869                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9870                                         &e, sizeof(e))) {
9871                         pr_debug_ratelimited(
9872                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9873                                 __func__, i, gpa + i * sizeof(e));
9874                         goto fail;
9875                 }
9876                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9877                         pr_debug_ratelimited(
9878                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9879                                 __func__, i, e.index, e.reserved);
9880                         goto fail;
9881                 }
9882                 msr.index = e.index;
9883                 msr.data = e.value;
9884                 if (kvm_set_msr(vcpu, &msr)) {
9885                         pr_debug_ratelimited(
9886                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9887                                 __func__, i, e.index, e.value);
9888                         goto fail;
9889                 }
9890         }
9891         return 0;
9892 fail:
9893         return i + 1;
9894 }
9895
9896 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9897 {
9898         u32 i;
9899         struct vmx_msr_entry e;
9900
9901         for (i = 0; i < count; i++) {
9902                 struct msr_data msr_info;
9903                 if (kvm_vcpu_read_guest(vcpu,
9904                                         gpa + i * sizeof(e),
9905                                         &e, 2 * sizeof(u32))) {
9906                         pr_debug_ratelimited(
9907                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9908                                 __func__, i, gpa + i * sizeof(e));
9909                         return -EINVAL;
9910                 }
9911                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9912                         pr_debug_ratelimited(
9913                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9914                                 __func__, i, e.index, e.reserved);
9915                         return -EINVAL;
9916                 }
9917                 msr_info.host_initiated = false;
9918                 msr_info.index = e.index;
9919                 if (kvm_get_msr(vcpu, &msr_info)) {
9920                         pr_debug_ratelimited(
9921                                 "%s cannot read MSR (%u, 0x%x)\n",
9922                                 __func__, i, e.index);
9923                         return -EINVAL;
9924                 }
9925                 if (kvm_vcpu_write_guest(vcpu,
9926                                          gpa + i * sizeof(e) +
9927                                              offsetof(struct vmx_msr_entry, value),
9928                                          &msr_info.data, sizeof(msr_info.data))) {
9929                         pr_debug_ratelimited(
9930                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9931                                 __func__, i, e.index, msr_info.data);
9932                         return -EINVAL;
9933                 }
9934         }
9935         return 0;
9936 }
9937
9938 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9939 {
9940         unsigned long invalid_mask;
9941
9942         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9943         return (val & invalid_mask) == 0;
9944 }
9945
9946 /*
9947  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9948  * emulating VM entry into a guest with EPT enabled.
9949  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9950  * is assigned to entry_failure_code on failure.
9951  */
9952 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9953                                u32 *entry_failure_code)
9954 {
9955         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9956                 if (!nested_cr3_valid(vcpu, cr3)) {
9957                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9958                         return 1;
9959                 }
9960
9961                 /*
9962                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9963                  * must not be dereferenced.
9964                  */
9965                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9966                     !nested_ept) {
9967                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9968                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9969                                 return 1;
9970                         }
9971                 }
9972
9973                 vcpu->arch.cr3 = cr3;
9974                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9975         }
9976
9977         kvm_mmu_reset_context(vcpu);
9978         return 0;
9979 }
9980
9981 /*
9982  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9983  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9984  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9985  * guest in a way that will both be appropriate to L1's requests, and our
9986  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9987  * function also has additional necessary side-effects, like setting various
9988  * vcpu->arch fields.
9989  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9990  * is assigned to entry_failure_code on failure.
9991  */
9992 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9993                           bool from_vmentry, u32 *entry_failure_code)
9994 {
9995         struct vcpu_vmx *vmx = to_vmx(vcpu);
9996         u32 exec_control;
9997         bool nested_ept_enabled = false;
9998
9999         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10000         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10001         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10002         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10003         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10004         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10005         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10006         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10007         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10008         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10009         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10010         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10011         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10012         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10013         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10014         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10015         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10016         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10017         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10018         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10019         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10020         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10021         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10022         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10023         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10024         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10025         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10026         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10027         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10028         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10029         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10030         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10031         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10032         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10033         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10034         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10035
10036         if (from_vmentry &&
10037             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10038                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10039                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10040         } else {
10041                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10042                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10043         }
10044         if (from_vmentry) {
10045                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10046                              vmcs12->vm_entry_intr_info_field);
10047                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10048                              vmcs12->vm_entry_exception_error_code);
10049                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10050                              vmcs12->vm_entry_instruction_len);
10051                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10052                              vmcs12->guest_interruptibility_info);
10053         } else {
10054                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10055         }
10056         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10057         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10058         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10059                 vmcs12->guest_pending_dbg_exceptions);
10060         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10061         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10062
10063         if (nested_cpu_has_xsaves(vmcs12))
10064                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10065         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10066
10067         exec_control = vmcs12->pin_based_vm_exec_control;
10068
10069         /* Preemption timer setting is only taken from vmcs01.  */
10070         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10071         exec_control |= vmcs_config.pin_based_exec_ctrl;
10072         if (vmx->hv_deadline_tsc == -1)
10073                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10074
10075         /* Posted interrupts setting is only taken from vmcs12.  */
10076         if (nested_cpu_has_posted_intr(vmcs12)) {
10077                 /*
10078                  * Note that we use L0's vector here and in
10079                  * vmx_deliver_nested_posted_interrupt.
10080                  */
10081                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10082                 vmx->nested.pi_pending = false;
10083                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10084         } else {
10085                 exec_control &= ~PIN_BASED_POSTED_INTR;
10086         }
10087
10088         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10089
10090         vmx->nested.preemption_timer_expired = false;
10091         if (nested_cpu_has_preemption_timer(vmcs12))
10092                 vmx_start_preemption_timer(vcpu);
10093
10094         /*
10095          * Whether page-faults are trapped is determined by a combination of
10096          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10097          * If enable_ept, L0 doesn't care about page faults and we should
10098          * set all of these to L1's desires. However, if !enable_ept, L0 does
10099          * care about (at least some) page faults, and because it is not easy
10100          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10101          * to exit on each and every L2 page fault. This is done by setting
10102          * MASK=MATCH=0 and (see below) EB.PF=1.
10103          * Note that below we don't need special code to set EB.PF beyond the
10104          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10105          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10106          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10107          *
10108          * A problem with this approach (when !enable_ept) is that L1 may be
10109          * injected with more page faults than it asked for. This could have
10110          * caused problems, but in practice existing hypervisors don't care.
10111          * To fix this, we will need to emulate the PFEC checking (on the L1
10112          * page tables), using walk_addr(), when injecting PFs to L1.
10113          */
10114         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10115                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10116         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10117                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10118
10119         if (cpu_has_secondary_exec_ctrls()) {
10120                 exec_control = vmx_secondary_exec_control(vmx);
10121
10122                 /* Take the following fields only from vmcs12 */
10123                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10124                                   SECONDARY_EXEC_RDTSCP |
10125                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10126                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10127                 if (nested_cpu_has(vmcs12,
10128                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10129                         exec_control |= vmcs12->secondary_vm_exec_control;
10130
10131                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10132                         vmcs_write64(EOI_EXIT_BITMAP0,
10133                                 vmcs12->eoi_exit_bitmap0);
10134                         vmcs_write64(EOI_EXIT_BITMAP1,
10135                                 vmcs12->eoi_exit_bitmap1);
10136                         vmcs_write64(EOI_EXIT_BITMAP2,
10137                                 vmcs12->eoi_exit_bitmap2);
10138                         vmcs_write64(EOI_EXIT_BITMAP3,
10139                                 vmcs12->eoi_exit_bitmap3);
10140                         vmcs_write16(GUEST_INTR_STATUS,
10141                                 vmcs12->guest_intr_status);
10142                 }
10143
10144                 nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0;
10145
10146                 /*
10147                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10148                  * nested_get_vmcs12_pages will either fix it up or
10149                  * remove the VM execution control.
10150                  */
10151                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10152                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10153
10154                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10155         }
10156
10157
10158         /*
10159          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10160          * Some constant fields are set here by vmx_set_constant_host_state().
10161          * Other fields are different per CPU, and will be set later when
10162          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10163          */
10164         vmx_set_constant_host_state(vmx);
10165
10166         /*
10167          * Set the MSR load/store lists to match L0's settings.
10168          */
10169         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10170         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10171         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10172         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10173         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10174
10175         /*
10176          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10177          * entry, but only if the current (host) sp changed from the value
10178          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10179          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10180          * here we just force the write to happen on entry.
10181          */
10182         vmx->host_rsp = 0;
10183
10184         exec_control = vmx_exec_control(vmx); /* L0's desires */
10185         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10186         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10187         exec_control &= ~CPU_BASED_TPR_SHADOW;
10188         exec_control |= vmcs12->cpu_based_vm_exec_control;
10189
10190         /*
10191          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10192          * nested_get_vmcs12_pages can't fix it up, the illegal value
10193          * will result in a VM entry failure.
10194          */
10195         if (exec_control & CPU_BASED_TPR_SHADOW) {
10196                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10197                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10198         }
10199
10200         /*
10201          * Merging of IO bitmap not currently supported.
10202          * Rather, exit every time.
10203          */
10204         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10205         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10206
10207         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10208
10209         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10210          * bitwise-or of what L1 wants to trap for L2, and what we want to
10211          * trap. Note that CR0.TS also needs updating - we do this later.
10212          */
10213         update_exception_bitmap(vcpu);
10214         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10215         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10216
10217         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10218          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10219          * bits are further modified by vmx_set_efer() below.
10220          */
10221         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10222
10223         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10224          * emulated by vmx_set_efer(), below.
10225          */
10226         vm_entry_controls_init(vmx,
10227                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10228                         ~VM_ENTRY_IA32E_MODE) |
10229                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10230
10231         if (from_vmentry &&
10232             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10233                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10234                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10235         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10236                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10237         }
10238
10239         set_cr4_guest_host_mask(vmx);
10240
10241         if (from_vmentry &&
10242             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10243                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10244
10245         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10246                 vmcs_write64(TSC_OFFSET,
10247                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10248         else
10249                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10250         if (kvm_has_tsc_control)
10251                 decache_tsc_multiplier(vmx);
10252
10253         if (enable_vpid) {
10254                 /*
10255                  * There is no direct mapping between vpid02 and vpid12, the
10256                  * vpid02 is per-vCPU for L0 and reused while the value of
10257                  * vpid12 is changed w/ one invvpid during nested vmentry.
10258                  * The vpid12 is allocated by L1 for L2, so it will not
10259                  * influence global bitmap(for vpid01 and vpid02 allocation)
10260                  * even if spawn a lot of nested vCPUs.
10261                  */
10262                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10263                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10264                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10265                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10266                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10267                         }
10268                 } else {
10269                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10270                         vmx_flush_tlb(vcpu);
10271                 }
10272
10273         }
10274
10275         if (nested_cpu_has_ept(vmcs12)) {
10276                 kvm_mmu_unload(vcpu);
10277                 nested_ept_init_mmu_context(vcpu);
10278         }
10279
10280         /*
10281          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10282          * bits which we consider mandatory enabled.
10283          * The CR0_READ_SHADOW is what L2 should have expected to read given
10284          * the specifications by L1; It's not enough to take
10285          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10286          * have more bits than L1 expected.
10287          */
10288         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10289         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10290
10291         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10292         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10293
10294         if (from_vmentry &&
10295             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10296                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10297         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10298                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10299         else
10300                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10301         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10302         vmx_set_efer(vcpu, vcpu->arch.efer);
10303
10304         /* Shadow page tables on either EPT or shadow page tables. */
10305         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled,
10306                                 entry_failure_code))
10307                 return 1;
10308
10309         kvm_mmu_reset_context(vcpu);
10310
10311         if (!enable_ept)
10312                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10313
10314         /*
10315          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10316          */
10317         if (enable_ept) {
10318                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10319                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10320                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10321                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10322         }
10323
10324         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10325         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10326         return 0;
10327 }
10328
10329 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10330 {
10331         struct vcpu_vmx *vmx = to_vmx(vcpu);
10332
10333         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10334             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10335                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10336
10337         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10338                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10339
10340         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10341                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10342
10343         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10344                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10345
10346         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10347                                 vmx->nested.nested_vmx_procbased_ctls_low,
10348                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10349             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10350                                 vmx->nested.nested_vmx_secondary_ctls_low,
10351                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10352             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10353                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10354                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10355             !vmx_control_verify(vmcs12->vm_exit_controls,
10356                                 vmx->nested.nested_vmx_exit_ctls_low,
10357                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10358             !vmx_control_verify(vmcs12->vm_entry_controls,
10359                                 vmx->nested.nested_vmx_entry_ctls_low,
10360                                 vmx->nested.nested_vmx_entry_ctls_high))
10361                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10362
10363         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10364             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10365             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10366                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10367
10368         return 0;
10369 }
10370
10371 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10372                                   u32 *exit_qual)
10373 {
10374         bool ia32e;
10375
10376         *exit_qual = ENTRY_FAIL_DEFAULT;
10377
10378         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10379             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10380                 return 1;
10381
10382         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10383             vmcs12->vmcs_link_pointer != -1ull) {
10384                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10385                 return 1;
10386         }
10387
10388         /*
10389          * If the load IA32_EFER VM-entry control is 1, the following checks
10390          * are performed on the field for the IA32_EFER MSR:
10391          * - Bits reserved in the IA32_EFER MSR must be 0.
10392          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10393          *   the IA-32e mode guest VM-exit control. It must also be identical
10394          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10395          *   CR0.PG) is 1.
10396          */
10397         if (to_vmx(vcpu)->nested.nested_run_pending &&
10398             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10399                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10400                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10401                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10402                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10403                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10404                         return 1;
10405         }
10406
10407         /*
10408          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10409          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10410          * the values of the LMA and LME bits in the field must each be that of
10411          * the host address-space size VM-exit control.
10412          */
10413         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10414                 ia32e = (vmcs12->vm_exit_controls &
10415                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10416                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10417                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10418                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10419                         return 1;
10420         }
10421
10422         return 0;
10423 }
10424
10425 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10426 {
10427         struct vcpu_vmx *vmx = to_vmx(vcpu);
10428         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10429         struct loaded_vmcs *vmcs02;
10430         int cpu;
10431         u32 msr_entry_idx;
10432         u32 exit_qual;
10433
10434         vmcs02 = nested_get_current_vmcs02(vmx);
10435         if (!vmcs02)
10436                 return -ENOMEM;
10437
10438         enter_guest_mode(vcpu);
10439
10440         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10441                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10442
10443         cpu = get_cpu();
10444         vmx->loaded_vmcs = vmcs02;
10445         vmx_vcpu_put(vcpu);
10446         vmx_vcpu_load(vcpu, cpu);
10447         vcpu->cpu = cpu;
10448         put_cpu();
10449
10450         vmx_segment_cache_clear(vmx);
10451
10452         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10453                 leave_guest_mode(vcpu);
10454                 vmx_load_vmcs01(vcpu);
10455                 nested_vmx_entry_failure(vcpu, vmcs12,
10456                                          EXIT_REASON_INVALID_STATE, exit_qual);
10457                 return 1;
10458         }
10459
10460         nested_get_vmcs12_pages(vcpu, vmcs12);
10461
10462         msr_entry_idx = nested_vmx_load_msr(vcpu,
10463                                             vmcs12->vm_entry_msr_load_addr,
10464                                             vmcs12->vm_entry_msr_load_count);
10465         if (msr_entry_idx) {
10466                 leave_guest_mode(vcpu);
10467                 vmx_load_vmcs01(vcpu);
10468                 nested_vmx_entry_failure(vcpu, vmcs12,
10469                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10470                 return 1;
10471         }
10472
10473         vmcs12->launch_state = 1;
10474
10475         /*
10476          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10477          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10478          * returned as far as L1 is concerned. It will only return (and set
10479          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10480          */
10481         return 0;
10482 }
10483
10484 /*
10485  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10486  * for running an L2 nested guest.
10487  */
10488 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10489 {
10490         struct vmcs12 *vmcs12;
10491         struct vcpu_vmx *vmx = to_vmx(vcpu);
10492         u32 exit_qual;
10493         int ret;
10494
10495         if (!nested_vmx_check_permission(vcpu))
10496                 return 1;
10497
10498         if (!nested_vmx_check_vmcs12(vcpu))
10499                 goto out;
10500
10501         vmcs12 = get_vmcs12(vcpu);
10502
10503         if (enable_shadow_vmcs)
10504                 copy_shadow_to_vmcs12(vmx);
10505
10506         /*
10507          * The nested entry process starts with enforcing various prerequisites
10508          * on vmcs12 as required by the Intel SDM, and act appropriately when
10509          * they fail: As the SDM explains, some conditions should cause the
10510          * instruction to fail, while others will cause the instruction to seem
10511          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10512          * To speed up the normal (success) code path, we should avoid checking
10513          * for misconfigurations which will anyway be caught by the processor
10514          * when using the merged vmcs02.
10515          */
10516         if (vmcs12->launch_state == launch) {
10517                 nested_vmx_failValid(vcpu,
10518                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10519                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10520                 goto out;
10521         }
10522
10523         ret = check_vmentry_prereqs(vcpu, vmcs12);
10524         if (ret) {
10525                 nested_vmx_failValid(vcpu, ret);
10526                 goto out;
10527         }
10528
10529         /*
10530          * After this point, the trap flag no longer triggers a singlestep trap
10531          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10532          * This is not 100% correct; for performance reasons, we delegate most
10533          * of the checks on host state to the processor.  If those fail,
10534          * the singlestep trap is missed.
10535          */
10536         skip_emulated_instruction(vcpu);
10537
10538         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10539         if (ret) {
10540                 nested_vmx_entry_failure(vcpu, vmcs12,
10541                                          EXIT_REASON_INVALID_STATE, exit_qual);
10542                 return 1;
10543         }
10544
10545         /*
10546          * We're finally done with prerequisite checking, and can start with
10547          * the nested entry.
10548          */
10549
10550         ret = enter_vmx_non_root_mode(vcpu, true);
10551         if (ret)
10552                 return ret;
10553
10554         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10555                 return kvm_vcpu_halt(vcpu);
10556
10557         vmx->nested.nested_run_pending = 1;
10558
10559         return 1;
10560
10561 out:
10562         return kvm_skip_emulated_instruction(vcpu);
10563 }
10564
10565 /*
10566  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10567  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10568  * This function returns the new value we should put in vmcs12.guest_cr0.
10569  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10570  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10571  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10572  *     didn't trap the bit, because if L1 did, so would L0).
10573  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10574  *     been modified by L2, and L1 knows it. So just leave the old value of
10575  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10576  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10577  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10578  *     changed these bits, and therefore they need to be updated, but L0
10579  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10580  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10581  */
10582 static inline unsigned long
10583 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10584 {
10585         return
10586         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10587         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10588         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10589                         vcpu->arch.cr0_guest_owned_bits));
10590 }
10591
10592 static inline unsigned long
10593 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10594 {
10595         return
10596         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10597         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10598         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10599                         vcpu->arch.cr4_guest_owned_bits));
10600 }
10601
10602 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10603                                        struct vmcs12 *vmcs12)
10604 {
10605         u32 idt_vectoring;
10606         unsigned int nr;
10607
10608         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10609                 nr = vcpu->arch.exception.nr;
10610                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10611
10612                 if (kvm_exception_is_soft(nr)) {
10613                         vmcs12->vm_exit_instruction_len =
10614                                 vcpu->arch.event_exit_inst_len;
10615                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10616                 } else
10617                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10618
10619                 if (vcpu->arch.exception.has_error_code) {
10620                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10621                         vmcs12->idt_vectoring_error_code =
10622                                 vcpu->arch.exception.error_code;
10623                 }
10624
10625                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10626         } else if (vcpu->arch.nmi_injected) {
10627                 vmcs12->idt_vectoring_info_field =
10628                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10629         } else if (vcpu->arch.interrupt.pending) {
10630                 nr = vcpu->arch.interrupt.nr;
10631                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10632
10633                 if (vcpu->arch.interrupt.soft) {
10634                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10635                         vmcs12->vm_entry_instruction_len =
10636                                 vcpu->arch.event_exit_inst_len;
10637                 } else
10638                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10639
10640                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10641         }
10642 }
10643
10644 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10645 {
10646         struct vcpu_vmx *vmx = to_vmx(vcpu);
10647
10648         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10649             vmx->nested.preemption_timer_expired) {
10650                 if (vmx->nested.nested_run_pending)
10651                         return -EBUSY;
10652                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10653                 return 0;
10654         }
10655
10656         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10657                 if (vmx->nested.nested_run_pending ||
10658                     vcpu->arch.interrupt.pending)
10659                         return -EBUSY;
10660                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10661                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10662                                   INTR_INFO_VALID_MASK, 0);
10663                 /*
10664                  * The NMI-triggered VM exit counts as injection:
10665                  * clear this one and block further NMIs.
10666                  */
10667                 vcpu->arch.nmi_pending = 0;
10668                 vmx_set_nmi_mask(vcpu, true);
10669                 return 0;
10670         }
10671
10672         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10673             nested_exit_on_intr(vcpu)) {
10674                 if (vmx->nested.nested_run_pending)
10675                         return -EBUSY;
10676                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10677                 return 0;
10678         }
10679
10680         vmx_complete_nested_posted_interrupt(vcpu);
10681         return 0;
10682 }
10683
10684 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10685 {
10686         ktime_t remaining =
10687                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10688         u64 value;
10689
10690         if (ktime_to_ns(remaining) <= 0)
10691                 return 0;
10692
10693         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10694         do_div(value, 1000000);
10695         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10696 }
10697
10698 /*
10699  * Update the guest state fields of vmcs12 to reflect changes that
10700  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10701  * VM-entry controls is also updated, since this is really a guest
10702  * state bit.)
10703  */
10704 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10705 {
10706         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10707         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10708
10709         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10710         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10711         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10712
10713         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10714         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10715         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10716         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10717         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10718         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10719         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10720         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10721         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10722         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10723         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10724         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10725         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10726         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10727         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10728         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10729         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10730         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10731         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10732         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10733         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10734         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10735         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10736         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10737         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10738         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10739         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10740         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10741         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10742         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10743         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10744         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10745         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10746         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10747         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10748         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10749
10750         vmcs12->guest_interruptibility_info =
10751                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10752         vmcs12->guest_pending_dbg_exceptions =
10753                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10754         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10755                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10756         else
10757                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10758
10759         if (nested_cpu_has_preemption_timer(vmcs12)) {
10760                 if (vmcs12->vm_exit_controls &
10761                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10762                         vmcs12->vmx_preemption_timer_value =
10763                                 vmx_get_preemption_timer_value(vcpu);
10764                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10765         }
10766
10767         /*
10768          * In some cases (usually, nested EPT), L2 is allowed to change its
10769          * own CR3 without exiting. If it has changed it, we must keep it.
10770          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10771          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10772          *
10773          * Additionally, restore L2's PDPTR to vmcs12.
10774          */
10775         if (enable_ept) {
10776                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10777                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10778                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10779                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10780                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10781         }
10782
10783         if (nested_cpu_has_ept(vmcs12))
10784                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10785
10786         if (nested_cpu_has_vid(vmcs12))
10787                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10788
10789         vmcs12->vm_entry_controls =
10790                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10791                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10792
10793         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10794                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10795                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10796         }
10797
10798         /* TODO: These cannot have changed unless we have MSR bitmaps and
10799          * the relevant bit asks not to trap the change */
10800         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10801                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10802         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10803                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10804         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10805         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10806         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10807         if (kvm_mpx_supported())
10808                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10809         if (nested_cpu_has_xsaves(vmcs12))
10810                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10811 }
10812
10813 /*
10814  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10815  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10816  * and this function updates it to reflect the changes to the guest state while
10817  * L2 was running (and perhaps made some exits which were handled directly by L0
10818  * without going back to L1), and to reflect the exit reason.
10819  * Note that we do not have to copy here all VMCS fields, just those that
10820  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10821  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10822  * which already writes to vmcs12 directly.
10823  */
10824 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10825                            u32 exit_reason, u32 exit_intr_info,
10826                            unsigned long exit_qualification)
10827 {
10828         /* update guest state fields: */
10829         sync_vmcs12(vcpu, vmcs12);
10830
10831         /* update exit information fields: */
10832
10833         vmcs12->vm_exit_reason = exit_reason;
10834         vmcs12->exit_qualification = exit_qualification;
10835
10836         vmcs12->vm_exit_intr_info = exit_intr_info;
10837         if ((vmcs12->vm_exit_intr_info &
10838              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10839             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10840                 vmcs12->vm_exit_intr_error_code =
10841                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10842         vmcs12->idt_vectoring_info_field = 0;
10843         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10844         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10845
10846         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10847                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10848                  * instead of reading the real value. */
10849                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10850
10851                 /*
10852                  * Transfer the event that L0 or L1 may wanted to inject into
10853                  * L2 to IDT_VECTORING_INFO_FIELD.
10854                  */
10855                 vmcs12_save_pending_event(vcpu, vmcs12);
10856         }
10857
10858         /*
10859          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10860          * preserved above and would only end up incorrectly in L1.
10861          */
10862         vcpu->arch.nmi_injected = false;
10863         kvm_clear_exception_queue(vcpu);
10864         kvm_clear_interrupt_queue(vcpu);
10865 }
10866
10867 /*
10868  * A part of what we need to when the nested L2 guest exits and we want to
10869  * run its L1 parent, is to reset L1's guest state to the host state specified
10870  * in vmcs12.
10871  * This function is to be called not only on normal nested exit, but also on
10872  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10873  * Failures During or After Loading Guest State").
10874  * This function should be called when the active VMCS is L1's (vmcs01).
10875  */
10876 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10877                                    struct vmcs12 *vmcs12)
10878 {
10879         struct kvm_segment seg;
10880         u32 entry_failure_code;
10881
10882         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10883                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10884         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10885                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10886         else
10887                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10888         vmx_set_efer(vcpu, vcpu->arch.efer);
10889
10890         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10891         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10892         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10893         /*
10894          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10895          * actually changed, because vmx_set_cr0 refers to efer set above.
10896          *
10897          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10898          * (KVM doesn't change it);
10899          */
10900         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10901         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10902
10903         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10904         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10905         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10906
10907         nested_ept_uninit_mmu_context(vcpu);
10908
10909         /*
10910          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10911          * couldn't have changed.
10912          */
10913         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10914                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10915
10916         if (!enable_ept)
10917                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10918
10919         if (enable_vpid) {
10920                 /*
10921                  * Trivially support vpid by letting L2s share their parent
10922                  * L1's vpid. TODO: move to a more elaborate solution, giving
10923                  * each L2 its own vpid and exposing the vpid feature to L1.
10924                  */
10925                 vmx_flush_tlb(vcpu);
10926         }
10927
10928
10929         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10930         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10931         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10932         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10933         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10934
10935         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10936         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10937                 vmcs_write64(GUEST_BNDCFGS, 0);
10938
10939         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10940                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10941                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10942         }
10943         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10944                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10945                         vmcs12->host_ia32_perf_global_ctrl);
10946
10947         /* Set L1 segment info according to Intel SDM
10948             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10949         seg = (struct kvm_segment) {
10950                 .base = 0,
10951                 .limit = 0xFFFFFFFF,
10952                 .selector = vmcs12->host_cs_selector,
10953                 .type = 11,
10954                 .present = 1,
10955                 .s = 1,
10956                 .g = 1
10957         };
10958         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10959                 seg.l = 1;
10960         else
10961                 seg.db = 1;
10962         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10963         seg = (struct kvm_segment) {
10964                 .base = 0,
10965                 .limit = 0xFFFFFFFF,
10966                 .type = 3,
10967                 .present = 1,
10968                 .s = 1,
10969                 .db = 1,
10970                 .g = 1
10971         };
10972         seg.selector = vmcs12->host_ds_selector;
10973         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10974         seg.selector = vmcs12->host_es_selector;
10975         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10976         seg.selector = vmcs12->host_ss_selector;
10977         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10978         seg.selector = vmcs12->host_fs_selector;
10979         seg.base = vmcs12->host_fs_base;
10980         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10981         seg.selector = vmcs12->host_gs_selector;
10982         seg.base = vmcs12->host_gs_base;
10983         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10984         seg = (struct kvm_segment) {
10985                 .base = vmcs12->host_tr_base,
10986                 .limit = 0x67,
10987                 .selector = vmcs12->host_tr_selector,
10988                 .type = 11,
10989                 .present = 1
10990         };
10991         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10992
10993         kvm_set_dr(vcpu, 7, 0x400);
10994         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10995
10996         if (cpu_has_vmx_msr_bitmap())
10997                 vmx_set_msr_bitmap(vcpu);
10998
10999         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11000                                 vmcs12->vm_exit_msr_load_count))
11001                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11002 }
11003
11004 /*
11005  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11006  * and modify vmcs12 to make it see what it would expect to see there if
11007  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11008  */
11009 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11010                               u32 exit_intr_info,
11011                               unsigned long exit_qualification)
11012 {
11013         struct vcpu_vmx *vmx = to_vmx(vcpu);
11014         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11015         u32 vm_inst_error = 0;
11016
11017         /* trying to cancel vmlaunch/vmresume is a bug */
11018         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11019
11020         leave_guest_mode(vcpu);
11021         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11022                        exit_qualification);
11023
11024         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11025                                  vmcs12->vm_exit_msr_store_count))
11026                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11027
11028         if (unlikely(vmx->fail))
11029                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11030
11031         vmx_load_vmcs01(vcpu);
11032
11033         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11034             && nested_exit_intr_ack_set(vcpu)) {
11035                 int irq = kvm_cpu_get_interrupt(vcpu);
11036                 WARN_ON(irq < 0);
11037                 vmcs12->vm_exit_intr_info = irq |
11038                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11039         }
11040
11041         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11042                                        vmcs12->exit_qualification,
11043                                        vmcs12->idt_vectoring_info_field,
11044                                        vmcs12->vm_exit_intr_info,
11045                                        vmcs12->vm_exit_intr_error_code,
11046                                        KVM_ISA_VMX);
11047
11048         vm_entry_controls_reset_shadow(vmx);
11049         vm_exit_controls_reset_shadow(vmx);
11050         vmx_segment_cache_clear(vmx);
11051
11052         /* if no vmcs02 cache requested, remove the one we used */
11053         if (VMCS02_POOL_SIZE == 0)
11054                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11055
11056         load_vmcs12_host_state(vcpu, vmcs12);
11057
11058         /* Update any VMCS fields that might have changed while L2 ran */
11059         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11060         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11061         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11062         if (vmx->hv_deadline_tsc == -1)
11063                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11064                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11065         else
11066                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11067                               PIN_BASED_VMX_PREEMPTION_TIMER);
11068         if (kvm_has_tsc_control)
11069                 decache_tsc_multiplier(vmx);
11070
11071         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11072                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11073                 vmx_set_virtual_x2apic_mode(vcpu,
11074                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11075         }
11076
11077         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11078         vmx->host_rsp = 0;
11079
11080         /* Unpin physical memory we referred to in vmcs02 */
11081         if (vmx->nested.apic_access_page) {
11082                 nested_release_page(vmx->nested.apic_access_page);
11083                 vmx->nested.apic_access_page = NULL;
11084         }
11085         if (vmx->nested.virtual_apic_page) {
11086                 nested_release_page(vmx->nested.virtual_apic_page);
11087                 vmx->nested.virtual_apic_page = NULL;
11088         }
11089         if (vmx->nested.pi_desc_page) {
11090                 kunmap(vmx->nested.pi_desc_page);
11091                 nested_release_page(vmx->nested.pi_desc_page);
11092                 vmx->nested.pi_desc_page = NULL;
11093                 vmx->nested.pi_desc = NULL;
11094         }
11095
11096         /*
11097          * We are now running in L2, mmu_notifier will force to reload the
11098          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11099          */
11100         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11101
11102         /*
11103          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11104          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11105          * success or failure flag accordingly.
11106          */
11107         if (unlikely(vmx->fail)) {
11108                 vmx->fail = 0;
11109                 nested_vmx_failValid(vcpu, vm_inst_error);
11110         } else
11111                 nested_vmx_succeed(vcpu);
11112         if (enable_shadow_vmcs)
11113                 vmx->nested.sync_shadow_vmcs = true;
11114
11115         /* in case we halted in L2 */
11116         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11117 }
11118
11119 /*
11120  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11121  */
11122 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11123 {
11124         if (is_guest_mode(vcpu))
11125                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11126         free_nested(to_vmx(vcpu));
11127 }
11128
11129 /*
11130  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11131  * 23.7 "VM-entry failures during or after loading guest state" (this also
11132  * lists the acceptable exit-reason and exit-qualification parameters).
11133  * It should only be called before L2 actually succeeded to run, and when
11134  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11135  */
11136 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11137                         struct vmcs12 *vmcs12,
11138                         u32 reason, unsigned long qualification)
11139 {
11140         load_vmcs12_host_state(vcpu, vmcs12);
11141         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11142         vmcs12->exit_qualification = qualification;
11143         nested_vmx_succeed(vcpu);
11144         if (enable_shadow_vmcs)
11145                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11146 }
11147
11148 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11149                                struct x86_instruction_info *info,
11150                                enum x86_intercept_stage stage)
11151 {
11152         return X86EMUL_CONTINUE;
11153 }
11154
11155 #ifdef CONFIG_X86_64
11156 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11157 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11158                                   u64 divisor, u64 *result)
11159 {
11160         u64 low = a << shift, high = a >> (64 - shift);
11161
11162         /* To avoid the overflow on divq */
11163         if (high >= divisor)
11164                 return 1;
11165
11166         /* Low hold the result, high hold rem which is discarded */
11167         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11168             "rm" (divisor), "0" (low), "1" (high));
11169         *result = low;
11170
11171         return 0;
11172 }
11173
11174 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11175 {
11176         struct vcpu_vmx *vmx = to_vmx(vcpu);
11177         u64 tscl = rdtsc();
11178         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11179         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11180
11181         /* Convert to host delta tsc if tsc scaling is enabled */
11182         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11183                         u64_shl_div_u64(delta_tsc,
11184                                 kvm_tsc_scaling_ratio_frac_bits,
11185                                 vcpu->arch.tsc_scaling_ratio,
11186                                 &delta_tsc))
11187                 return -ERANGE;
11188
11189         /*
11190          * If the delta tsc can't fit in the 32 bit after the multi shift,
11191          * we can't use the preemption timer.
11192          * It's possible that it fits on later vmentries, but checking
11193          * on every vmentry is costly so we just use an hrtimer.
11194          */
11195         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11196                 return -ERANGE;
11197
11198         vmx->hv_deadline_tsc = tscl + delta_tsc;
11199         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11200                         PIN_BASED_VMX_PREEMPTION_TIMER);
11201         return 0;
11202 }
11203
11204 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11205 {
11206         struct vcpu_vmx *vmx = to_vmx(vcpu);
11207         vmx->hv_deadline_tsc = -1;
11208         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11209                         PIN_BASED_VMX_PREEMPTION_TIMER);
11210 }
11211 #endif
11212
11213 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11214 {
11215         if (ple_gap)
11216                 shrink_ple_window(vcpu);
11217 }
11218
11219 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11220                                      struct kvm_memory_slot *slot)
11221 {
11222         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11223         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11224 }
11225
11226 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11227                                        struct kvm_memory_slot *slot)
11228 {
11229         kvm_mmu_slot_set_dirty(kvm, slot);
11230 }
11231
11232 static void vmx_flush_log_dirty(struct kvm *kvm)
11233 {
11234         kvm_flush_pml_buffers(kvm);
11235 }
11236
11237 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11238                                            struct kvm_memory_slot *memslot,
11239                                            gfn_t offset, unsigned long mask)
11240 {
11241         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11242 }
11243
11244 /*
11245  * This routine does the following things for vCPU which is going
11246  * to be blocked if VT-d PI is enabled.
11247  * - Store the vCPU to the wakeup list, so when interrupts happen
11248  *   we can find the right vCPU to wake up.
11249  * - Change the Posted-interrupt descriptor as below:
11250  *      'NDST' <-- vcpu->pre_pcpu
11251  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11252  * - If 'ON' is set during this process, which means at least one
11253  *   interrupt is posted for this vCPU, we cannot block it, in
11254  *   this case, return 1, otherwise, return 0.
11255  *
11256  */
11257 static int pi_pre_block(struct kvm_vcpu *vcpu)
11258 {
11259         unsigned long flags;
11260         unsigned int dest;
11261         struct pi_desc old, new;
11262         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11263
11264         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11265                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11266                 !kvm_vcpu_apicv_active(vcpu))
11267                 return 0;
11268
11269         vcpu->pre_pcpu = vcpu->cpu;
11270         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11271                           vcpu->pre_pcpu), flags);
11272         list_add_tail(&vcpu->blocked_vcpu_list,
11273                       &per_cpu(blocked_vcpu_on_cpu,
11274                       vcpu->pre_pcpu));
11275         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11276                                vcpu->pre_pcpu), flags);
11277
11278         do {
11279                 old.control = new.control = pi_desc->control;
11280
11281                 /*
11282                  * We should not block the vCPU if
11283                  * an interrupt is posted for it.
11284                  */
11285                 if (pi_test_on(pi_desc) == 1) {
11286                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11287                                           vcpu->pre_pcpu), flags);
11288                         list_del(&vcpu->blocked_vcpu_list);
11289                         spin_unlock_irqrestore(
11290                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11291                                         vcpu->pre_pcpu), flags);
11292                         vcpu->pre_pcpu = -1;
11293
11294                         return 1;
11295                 }
11296
11297                 WARN((pi_desc->sn == 1),
11298                      "Warning: SN field of posted-interrupts "
11299                      "is set before blocking\n");
11300
11301                 /*
11302                  * Since vCPU can be preempted during this process,
11303                  * vcpu->cpu could be different with pre_pcpu, we
11304                  * need to set pre_pcpu as the destination of wakeup
11305                  * notification event, then we can find the right vCPU
11306                  * to wakeup in wakeup handler if interrupts happen
11307                  * when the vCPU is in blocked state.
11308                  */
11309                 dest = cpu_physical_id(vcpu->pre_pcpu);
11310
11311                 if (x2apic_enabled())
11312                         new.ndst = dest;
11313                 else
11314                         new.ndst = (dest << 8) & 0xFF00;
11315
11316                 /* set 'NV' to 'wakeup vector' */
11317                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11318         } while (cmpxchg(&pi_desc->control, old.control,
11319                         new.control) != old.control);
11320
11321         return 0;
11322 }
11323
11324 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11325 {
11326         if (pi_pre_block(vcpu))
11327                 return 1;
11328
11329         if (kvm_lapic_hv_timer_in_use(vcpu))
11330                 kvm_lapic_switch_to_sw_timer(vcpu);
11331
11332         return 0;
11333 }
11334
11335 static void pi_post_block(struct kvm_vcpu *vcpu)
11336 {
11337         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11338         struct pi_desc old, new;
11339         unsigned int dest;
11340         unsigned long flags;
11341
11342         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11343                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11344                 !kvm_vcpu_apicv_active(vcpu))
11345                 return;
11346
11347         do {
11348                 old.control = new.control = pi_desc->control;
11349
11350                 dest = cpu_physical_id(vcpu->cpu);
11351
11352                 if (x2apic_enabled())
11353                         new.ndst = dest;
11354                 else
11355                         new.ndst = (dest << 8) & 0xFF00;
11356
11357                 /* Allow posting non-urgent interrupts */
11358                 new.sn = 0;
11359
11360                 /* set 'NV' to 'notification vector' */
11361                 new.nv = POSTED_INTR_VECTOR;
11362         } while (cmpxchg(&pi_desc->control, old.control,
11363                         new.control) != old.control);
11364
11365         if(vcpu->pre_pcpu != -1) {
11366                 spin_lock_irqsave(
11367                         &per_cpu(blocked_vcpu_on_cpu_lock,
11368                         vcpu->pre_pcpu), flags);
11369                 list_del(&vcpu->blocked_vcpu_list);
11370                 spin_unlock_irqrestore(
11371                         &per_cpu(blocked_vcpu_on_cpu_lock,
11372                         vcpu->pre_pcpu), flags);
11373                 vcpu->pre_pcpu = -1;
11374         }
11375 }
11376
11377 static void vmx_post_block(struct kvm_vcpu *vcpu)
11378 {
11379         if (kvm_x86_ops->set_hv_timer)
11380                 kvm_lapic_switch_to_hv_timer(vcpu);
11381
11382         pi_post_block(vcpu);
11383 }
11384
11385 /*
11386  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11387  *
11388  * @kvm: kvm
11389  * @host_irq: host irq of the interrupt
11390  * @guest_irq: gsi of the interrupt
11391  * @set: set or unset PI
11392  * returns 0 on success, < 0 on failure
11393  */
11394 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11395                               uint32_t guest_irq, bool set)
11396 {
11397         struct kvm_kernel_irq_routing_entry *e;
11398         struct kvm_irq_routing_table *irq_rt;
11399         struct kvm_lapic_irq irq;
11400         struct kvm_vcpu *vcpu;
11401         struct vcpu_data vcpu_info;
11402         int idx, ret = -EINVAL;
11403
11404         if (!kvm_arch_has_assigned_device(kvm) ||
11405                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11406                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11407                 return 0;
11408
11409         idx = srcu_read_lock(&kvm->irq_srcu);
11410         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11411         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11412
11413         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11414                 if (e->type != KVM_IRQ_ROUTING_MSI)
11415                         continue;
11416                 /*
11417                  * VT-d PI cannot support posting multicast/broadcast
11418                  * interrupts to a vCPU, we still use interrupt remapping
11419                  * for these kind of interrupts.
11420                  *
11421                  * For lowest-priority interrupts, we only support
11422                  * those with single CPU as the destination, e.g. user
11423                  * configures the interrupts via /proc/irq or uses
11424                  * irqbalance to make the interrupts single-CPU.
11425                  *
11426                  * We will support full lowest-priority interrupt later.
11427                  */
11428
11429                 kvm_set_msi_irq(kvm, e, &irq);
11430                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11431                         /*
11432                          * Make sure the IRTE is in remapped mode if
11433                          * we don't handle it in posted mode.
11434                          */
11435                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11436                         if (ret < 0) {
11437                                 printk(KERN_INFO
11438                                    "failed to back to remapped mode, irq: %u\n",
11439                                    host_irq);
11440                                 goto out;
11441                         }
11442
11443                         continue;
11444                 }
11445
11446                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11447                 vcpu_info.vector = irq.vector;
11448
11449                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11450                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11451
11452                 if (set)
11453                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11454                 else {
11455                         /* suppress notification event before unposting */
11456                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11457                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11458                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11459                 }
11460
11461                 if (ret < 0) {
11462                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11463                                         __func__);
11464                         goto out;
11465                 }
11466         }
11467
11468         ret = 0;
11469 out:
11470         srcu_read_unlock(&kvm->irq_srcu, idx);
11471         return ret;
11472 }
11473
11474 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11475 {
11476         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11477                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11478                         FEATURE_CONTROL_LMCE;
11479         else
11480                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11481                         ~FEATURE_CONTROL_LMCE;
11482 }
11483
11484 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11485         .cpu_has_kvm_support = cpu_has_kvm_support,
11486         .disabled_by_bios = vmx_disabled_by_bios,
11487         .hardware_setup = hardware_setup,
11488         .hardware_unsetup = hardware_unsetup,
11489         .check_processor_compatibility = vmx_check_processor_compat,
11490         .hardware_enable = hardware_enable,
11491         .hardware_disable = hardware_disable,
11492         .cpu_has_accelerated_tpr = report_flexpriority,
11493         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11494
11495         .vcpu_create = vmx_create_vcpu,
11496         .vcpu_free = vmx_free_vcpu,
11497         .vcpu_reset = vmx_vcpu_reset,
11498
11499         .prepare_guest_switch = vmx_save_host_state,
11500         .vcpu_load = vmx_vcpu_load,
11501         .vcpu_put = vmx_vcpu_put,
11502
11503         .update_bp_intercept = update_exception_bitmap,
11504         .get_msr = vmx_get_msr,
11505         .set_msr = vmx_set_msr,
11506         .get_segment_base = vmx_get_segment_base,
11507         .get_segment = vmx_get_segment,
11508         .set_segment = vmx_set_segment,
11509         .get_cpl = vmx_get_cpl,
11510         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11511         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11512         .decache_cr3 = vmx_decache_cr3,
11513         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11514         .set_cr0 = vmx_set_cr0,
11515         .set_cr3 = vmx_set_cr3,
11516         .set_cr4 = vmx_set_cr4,
11517         .set_efer = vmx_set_efer,
11518         .get_idt = vmx_get_idt,
11519         .set_idt = vmx_set_idt,
11520         .get_gdt = vmx_get_gdt,
11521         .set_gdt = vmx_set_gdt,
11522         .get_dr6 = vmx_get_dr6,
11523         .set_dr6 = vmx_set_dr6,
11524         .set_dr7 = vmx_set_dr7,
11525         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11526         .cache_reg = vmx_cache_reg,
11527         .get_rflags = vmx_get_rflags,
11528         .set_rflags = vmx_set_rflags,
11529
11530         .get_pkru = vmx_get_pkru,
11531
11532         .tlb_flush = vmx_flush_tlb,
11533
11534         .run = vmx_vcpu_run,
11535         .handle_exit = vmx_handle_exit,
11536         .skip_emulated_instruction = skip_emulated_instruction,
11537         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11538         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11539         .patch_hypercall = vmx_patch_hypercall,
11540         .set_irq = vmx_inject_irq,
11541         .set_nmi = vmx_inject_nmi,
11542         .queue_exception = vmx_queue_exception,
11543         .cancel_injection = vmx_cancel_injection,
11544         .interrupt_allowed = vmx_interrupt_allowed,
11545         .nmi_allowed = vmx_nmi_allowed,
11546         .get_nmi_mask = vmx_get_nmi_mask,
11547         .set_nmi_mask = vmx_set_nmi_mask,
11548         .enable_nmi_window = enable_nmi_window,
11549         .enable_irq_window = enable_irq_window,
11550         .update_cr8_intercept = update_cr8_intercept,
11551         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11552         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11553         .get_enable_apicv = vmx_get_enable_apicv,
11554         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11555         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11556         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11557         .hwapic_irr_update = vmx_hwapic_irr_update,
11558         .hwapic_isr_update = vmx_hwapic_isr_update,
11559         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11560         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11561
11562         .set_tss_addr = vmx_set_tss_addr,
11563         .get_tdp_level = get_ept_level,
11564         .get_mt_mask = vmx_get_mt_mask,
11565
11566         .get_exit_info = vmx_get_exit_info,
11567
11568         .get_lpage_level = vmx_get_lpage_level,
11569
11570         .cpuid_update = vmx_cpuid_update,
11571
11572         .rdtscp_supported = vmx_rdtscp_supported,
11573         .invpcid_supported = vmx_invpcid_supported,
11574
11575         .set_supported_cpuid = vmx_set_supported_cpuid,
11576
11577         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11578
11579         .write_tsc_offset = vmx_write_tsc_offset,
11580
11581         .set_tdp_cr3 = vmx_set_cr3,
11582
11583         .check_intercept = vmx_check_intercept,
11584         .handle_external_intr = vmx_handle_external_intr,
11585         .mpx_supported = vmx_mpx_supported,
11586         .xsaves_supported = vmx_xsaves_supported,
11587
11588         .check_nested_events = vmx_check_nested_events,
11589
11590         .sched_in = vmx_sched_in,
11591
11592         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11593         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11594         .flush_log_dirty = vmx_flush_log_dirty,
11595         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11596
11597         .pre_block = vmx_pre_block,
11598         .post_block = vmx_post_block,
11599
11600         .pmu_ops = &intel_pmu_ops,
11601
11602         .update_pi_irte = vmx_update_pi_irte,
11603
11604 #ifdef CONFIG_X86_64
11605         .set_hv_timer = vmx_set_hv_timer,
11606         .cancel_hv_timer = vmx_cancel_hv_timer,
11607 #endif
11608
11609         .setup_mce = vmx_setup_mce,
11610 };
11611
11612 static int __init vmx_init(void)
11613 {
11614         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11615                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11616         if (r)
11617                 return r;
11618
11619 #ifdef CONFIG_KEXEC_CORE
11620         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11621                            crash_vmclear_local_loaded_vmcss);
11622 #endif
11623
11624         return 0;
11625 }
11626
11627 static void __exit vmx_exit(void)
11628 {
11629 #ifdef CONFIG_KEXEC_CORE
11630         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11631         synchronize_rcu();
11632 #endif
11633
11634         kvm_exit();
11635 }
11636
11637 module_init(vmx_init)
11638 module_exit(vmx_exit)