2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
68 static bool __read_mostly enable_vpid = 1;
69 module_param_named(vpid, enable_vpid, bool, 0444);
71 static bool __read_mostly flexpriority_enabled = 1;
72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
74 static bool __read_mostly enable_ept = 1;
75 module_param_named(ept, enable_ept, bool, S_IRUGO);
77 static bool __read_mostly enable_unrestricted_guest = 1;
78 module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
81 static bool __read_mostly enable_ept_ad_bits = 1;
82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
84 static bool __read_mostly emulate_invalid_guest_state = true;
85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
87 static bool __read_mostly vmm_exclusive = 1;
88 module_param(vmm_exclusive, bool, S_IRUGO);
90 static bool __read_mostly fasteoi = 1;
91 module_param(fasteoi, bool, S_IRUGO);
93 static bool __read_mostly enable_apicv = 1;
94 module_param(enable_apicv, bool, S_IRUGO);
96 static bool __read_mostly enable_shadow_vmcs = 1;
97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested = 0;
104 module_param(nested, bool, S_IRUGO);
106 static u64 __read_mostly host_xss;
108 static bool __read_mostly enable_pml = 1;
109 module_param_named(pml, enable_pml, bool, S_IRUGO);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi;
115 static bool __read_mostly enable_preemption_timer = 1;
117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
137 * ple_gap: upper bound on the amount of time between two successive
138 * executions of PAUSE in a loop. Also indicate if ple enabled.
139 * According to test, this time is usually smaller than 128 cycles.
140 * ple_window: upper bound on the amount of time a guest is allowed to execute
141 * in a PAUSE loop. Tests indicate that most spinlocks are held for
142 * less than 2^12 cycles
143 * Time is measured based on a counter that runs at the same rate as the TSC,
144 * refer SDM volume 3b section 21.6.13 & 22.1.3.
146 #define KVM_VMX_DEFAULT_PLE_GAP 128
147 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
151 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
154 module_param(ple_gap, int, S_IRUGO);
156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
157 module_param(ple_window, int, S_IRUGO);
159 /* Default doubles per-vcpu window every exit. */
160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
161 module_param(ple_window_grow, int, S_IRUGO);
163 /* Default resets per-vcpu window every exit to ple_window. */
164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
165 module_param(ple_window_shrink, int, S_IRUGO);
167 /* Default is to compute the maximum so we can never overflow. */
168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
169 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
170 module_param(ple_window_max, int, S_IRUGO);
172 extern const ulong vmx_return;
174 #define NR_AUTOLOAD_MSRS 8
175 #define VMCS02_POOL_SIZE 1
184 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
185 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
186 * loaded on this CPU (so we can clear them if the CPU goes down).
190 struct vmcs *shadow_vmcs;
193 struct list_head loaded_vmcss_on_cpu_link;
196 struct shared_msr_entry {
203 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
204 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
205 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
206 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
207 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
208 * More than one of these structures may exist, if L1 runs multiple L2 guests.
209 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
210 * underlying hardware which will be used to run L2.
211 * This structure is packed to ensure that its layout is identical across
212 * machines (necessary for live migration).
213 * If there are changes in this struct, VMCS12_REVISION must be changed.
215 typedef u64 natural_width;
216 struct __packed vmcs12 {
217 /* According to the Intel spec, a VMCS region must start with the
218 * following two fields. Then follow implementation-specific data.
223 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
224 u32 padding[7]; /* room for future expansion */
229 u64 vm_exit_msr_store_addr;
230 u64 vm_exit_msr_load_addr;
231 u64 vm_entry_msr_load_addr;
233 u64 virtual_apic_page_addr;
234 u64 apic_access_addr;
235 u64 posted_intr_desc_addr;
237 u64 eoi_exit_bitmap0;
238 u64 eoi_exit_bitmap1;
239 u64 eoi_exit_bitmap2;
240 u64 eoi_exit_bitmap3;
242 u64 guest_physical_address;
243 u64 vmcs_link_pointer;
244 u64 guest_ia32_debugctl;
247 u64 guest_ia32_perf_global_ctrl;
255 u64 host_ia32_perf_global_ctrl;
256 u64 padding64[8]; /* room for future expansion */
258 * To allow migration of L1 (complete with its L2 guests) between
259 * machines of different natural widths (32 or 64 bit), we cannot have
260 * unsigned long fields with no explict size. We use u64 (aliased
261 * natural_width) instead. Luckily, x86 is little-endian.
263 natural_width cr0_guest_host_mask;
264 natural_width cr4_guest_host_mask;
265 natural_width cr0_read_shadow;
266 natural_width cr4_read_shadow;
267 natural_width cr3_target_value0;
268 natural_width cr3_target_value1;
269 natural_width cr3_target_value2;
270 natural_width cr3_target_value3;
271 natural_width exit_qualification;
272 natural_width guest_linear_address;
273 natural_width guest_cr0;
274 natural_width guest_cr3;
275 natural_width guest_cr4;
276 natural_width guest_es_base;
277 natural_width guest_cs_base;
278 natural_width guest_ss_base;
279 natural_width guest_ds_base;
280 natural_width guest_fs_base;
281 natural_width guest_gs_base;
282 natural_width guest_ldtr_base;
283 natural_width guest_tr_base;
284 natural_width guest_gdtr_base;
285 natural_width guest_idtr_base;
286 natural_width guest_dr7;
287 natural_width guest_rsp;
288 natural_width guest_rip;
289 natural_width guest_rflags;
290 natural_width guest_pending_dbg_exceptions;
291 natural_width guest_sysenter_esp;
292 natural_width guest_sysenter_eip;
293 natural_width host_cr0;
294 natural_width host_cr3;
295 natural_width host_cr4;
296 natural_width host_fs_base;
297 natural_width host_gs_base;
298 natural_width host_tr_base;
299 natural_width host_gdtr_base;
300 natural_width host_idtr_base;
301 natural_width host_ia32_sysenter_esp;
302 natural_width host_ia32_sysenter_eip;
303 natural_width host_rsp;
304 natural_width host_rip;
305 natural_width paddingl[8]; /* room for future expansion */
306 u32 pin_based_vm_exec_control;
307 u32 cpu_based_vm_exec_control;
308 u32 exception_bitmap;
309 u32 page_fault_error_code_mask;
310 u32 page_fault_error_code_match;
311 u32 cr3_target_count;
312 u32 vm_exit_controls;
313 u32 vm_exit_msr_store_count;
314 u32 vm_exit_msr_load_count;
315 u32 vm_entry_controls;
316 u32 vm_entry_msr_load_count;
317 u32 vm_entry_intr_info_field;
318 u32 vm_entry_exception_error_code;
319 u32 vm_entry_instruction_len;
321 u32 secondary_vm_exec_control;
322 u32 vm_instruction_error;
324 u32 vm_exit_intr_info;
325 u32 vm_exit_intr_error_code;
326 u32 idt_vectoring_info_field;
327 u32 idt_vectoring_error_code;
328 u32 vm_exit_instruction_len;
329 u32 vmx_instruction_info;
336 u32 guest_ldtr_limit;
338 u32 guest_gdtr_limit;
339 u32 guest_idtr_limit;
340 u32 guest_es_ar_bytes;
341 u32 guest_cs_ar_bytes;
342 u32 guest_ss_ar_bytes;
343 u32 guest_ds_ar_bytes;
344 u32 guest_fs_ar_bytes;
345 u32 guest_gs_ar_bytes;
346 u32 guest_ldtr_ar_bytes;
347 u32 guest_tr_ar_bytes;
348 u32 guest_interruptibility_info;
349 u32 guest_activity_state;
350 u32 guest_sysenter_cs;
351 u32 host_ia32_sysenter_cs;
352 u32 vmx_preemption_timer_value;
353 u32 padding32[7]; /* room for future expansion */
354 u16 virtual_processor_id;
356 u16 guest_es_selector;
357 u16 guest_cs_selector;
358 u16 guest_ss_selector;
359 u16 guest_ds_selector;
360 u16 guest_fs_selector;
361 u16 guest_gs_selector;
362 u16 guest_ldtr_selector;
363 u16 guest_tr_selector;
364 u16 guest_intr_status;
365 u16 host_es_selector;
366 u16 host_cs_selector;
367 u16 host_ss_selector;
368 u16 host_ds_selector;
369 u16 host_fs_selector;
370 u16 host_gs_selector;
371 u16 host_tr_selector;
375 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
376 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
377 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
379 #define VMCS12_REVISION 0x11e57ed0
382 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
383 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
384 * current implementation, 4K are reserved to avoid future complications.
386 #define VMCS12_SIZE 0x1000
388 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
390 struct list_head list;
392 struct loaded_vmcs vmcs02;
396 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
397 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
400 /* Has the level1 guest done vmxon? */
404 /* The guest-physical address of the current VMCS L1 keeps for L2 */
406 /* The host-usable pointer to the above */
407 struct page *current_vmcs12_page;
408 struct vmcs12 *current_vmcs12;
410 * Cache of the guest's VMCS, existing outside of guest memory.
411 * Loaded from guest memory during VMPTRLD. Flushed to guest
412 * memory during VMXOFF, VMCLEAR, VMPTRLD.
414 struct vmcs12 *cached_vmcs12;
416 * Indicates if the shadow vmcs must be updated with the
417 * data hold by vmcs12
419 bool sync_shadow_vmcs;
421 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
422 struct list_head vmcs02_pool;
424 bool change_vmcs01_virtual_x2apic_mode;
425 /* L2 must run next, and mustn't decide to exit to L1. */
426 bool nested_run_pending;
428 * Guest pages referred to in vmcs02 with host-physical pointers, so
429 * we must keep them pinned while L2 runs.
431 struct page *apic_access_page;
432 struct page *virtual_apic_page;
433 struct page *pi_desc_page;
434 struct pi_desc *pi_desc;
438 unsigned long *msr_bitmap;
440 struct hrtimer preemption_timer;
441 bool preemption_timer_expired;
443 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
449 u32 nested_vmx_procbased_ctls_low;
450 u32 nested_vmx_procbased_ctls_high;
451 u32 nested_vmx_true_procbased_ctls_low;
452 u32 nested_vmx_secondary_ctls_low;
453 u32 nested_vmx_secondary_ctls_high;
454 u32 nested_vmx_pinbased_ctls_low;
455 u32 nested_vmx_pinbased_ctls_high;
456 u32 nested_vmx_exit_ctls_low;
457 u32 nested_vmx_exit_ctls_high;
458 u32 nested_vmx_true_exit_ctls_low;
459 u32 nested_vmx_entry_ctls_low;
460 u32 nested_vmx_entry_ctls_high;
461 u32 nested_vmx_true_entry_ctls_low;
462 u32 nested_vmx_misc_low;
463 u32 nested_vmx_misc_high;
464 u32 nested_vmx_ept_caps;
465 u32 nested_vmx_vpid_caps;
468 #define POSTED_INTR_ON 0
469 #define POSTED_INTR_SN 1
471 /* Posted-Interrupt Descriptor */
473 u32 pir[8]; /* Posted interrupt requested */
476 /* bit 256 - Outstanding Notification */
478 /* bit 257 - Suppress Notification */
480 /* bit 271:258 - Reserved */
482 /* bit 279:272 - Notification Vector */
484 /* bit 287:280 - Reserved */
486 /* bit 319:288 - Notification Destination */
494 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
496 return test_and_set_bit(POSTED_INTR_ON,
497 (unsigned long *)&pi_desc->control);
500 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
502 return test_and_clear_bit(POSTED_INTR_ON,
503 (unsigned long *)&pi_desc->control);
506 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
508 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
511 static inline void pi_clear_sn(struct pi_desc *pi_desc)
513 return clear_bit(POSTED_INTR_SN,
514 (unsigned long *)&pi_desc->control);
517 static inline void pi_set_sn(struct pi_desc *pi_desc)
519 return set_bit(POSTED_INTR_SN,
520 (unsigned long *)&pi_desc->control);
523 static inline int pi_test_on(struct pi_desc *pi_desc)
525 return test_bit(POSTED_INTR_ON,
526 (unsigned long *)&pi_desc->control);
529 static inline int pi_test_sn(struct pi_desc *pi_desc)
531 return test_bit(POSTED_INTR_SN,
532 (unsigned long *)&pi_desc->control);
536 struct kvm_vcpu vcpu;
537 unsigned long host_rsp;
539 bool nmi_known_unmasked;
541 u32 idt_vectoring_info;
543 struct shared_msr_entry *guest_msrs;
546 unsigned long host_idt_base;
548 u64 msr_host_kernel_gs_base;
549 u64 msr_guest_kernel_gs_base;
551 u32 vm_entry_controls_shadow;
552 u32 vm_exit_controls_shadow;
554 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
555 * non-nested (L1) guest, it always points to vmcs01. For a nested
556 * guest (L2), it points to a different VMCS.
558 struct loaded_vmcs vmcs01;
559 struct loaded_vmcs *loaded_vmcs;
560 bool __launched; /* temporary, used in vmx_vcpu_run */
561 struct msr_autoload {
563 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
564 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
568 u16 fs_sel, gs_sel, ldt_sel;
572 int gs_ldt_reload_needed;
573 int fs_reload_needed;
574 u64 msr_host_bndcfgs;
575 unsigned long vmcs_host_cr4; /* May not match real cr4 */
580 struct kvm_segment segs[8];
583 u32 bitmask; /* 4 bits per segment (1 bit per field) */
584 struct kvm_save_segment {
592 bool emulation_required;
594 /* Support for vnmi-less CPUs */
595 int soft_vnmi_blocked;
597 s64 vnmi_blocked_time;
600 /* Posted interrupt descriptor */
601 struct pi_desc pi_desc;
603 /* Support for a guest hypervisor (nested VMX) */
604 struct nested_vmx nested;
606 /* Dynamic PLE window. */
608 bool ple_window_dirty;
610 /* Support for PML */
611 #define PML_ENTITY_NUM 512
614 /* apic deadline value in host tsc */
617 u64 current_tsc_ratio;
619 bool guest_pkru_valid;
624 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
625 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
626 * in msr_ia32_feature_control_valid_bits.
628 u64 msr_ia32_feature_control;
629 u64 msr_ia32_feature_control_valid_bits;
632 enum segment_cache_field {
641 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
643 return container_of(vcpu, struct vcpu_vmx, vcpu);
646 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
648 return &(to_vmx(vcpu)->pi_desc);
651 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
652 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
653 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
654 [number##_HIGH] = VMCS12_OFFSET(name)+4
657 static unsigned long shadow_read_only_fields[] = {
659 * We do NOT shadow fields that are modified when L0
660 * traps and emulates any vmx instruction (e.g. VMPTRLD,
661 * VMXON...) executed by L1.
662 * For example, VM_INSTRUCTION_ERROR is read
663 * by L1 if a vmx instruction fails (part of the error path).
664 * Note the code assumes this logic. If for some reason
665 * we start shadowing these fields then we need to
666 * force a shadow sync when L0 emulates vmx instructions
667 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
668 * by nested_vmx_failValid)
672 VM_EXIT_INSTRUCTION_LEN,
673 IDT_VECTORING_INFO_FIELD,
674 IDT_VECTORING_ERROR_CODE,
675 VM_EXIT_INTR_ERROR_CODE,
677 GUEST_LINEAR_ADDRESS,
678 GUEST_PHYSICAL_ADDRESS
680 static int max_shadow_read_only_fields =
681 ARRAY_SIZE(shadow_read_only_fields);
683 static unsigned long shadow_read_write_fields[] = {
690 GUEST_INTERRUPTIBILITY_INFO,
703 CPU_BASED_VM_EXEC_CONTROL,
704 VM_ENTRY_EXCEPTION_ERROR_CODE,
705 VM_ENTRY_INTR_INFO_FIELD,
706 VM_ENTRY_INSTRUCTION_LEN,
707 VM_ENTRY_EXCEPTION_ERROR_CODE,
713 static int max_shadow_read_write_fields =
714 ARRAY_SIZE(shadow_read_write_fields);
716 static const unsigned short vmcs_field_to_offset_table[] = {
717 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
718 FIELD(POSTED_INTR_NV, posted_intr_nv),
719 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
720 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
721 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
722 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
723 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
724 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
725 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
726 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
727 FIELD(GUEST_INTR_STATUS, guest_intr_status),
728 FIELD(HOST_ES_SELECTOR, host_es_selector),
729 FIELD(HOST_CS_SELECTOR, host_cs_selector),
730 FIELD(HOST_SS_SELECTOR, host_ss_selector),
731 FIELD(HOST_DS_SELECTOR, host_ds_selector),
732 FIELD(HOST_FS_SELECTOR, host_fs_selector),
733 FIELD(HOST_GS_SELECTOR, host_gs_selector),
734 FIELD(HOST_TR_SELECTOR, host_tr_selector),
735 FIELD64(IO_BITMAP_A, io_bitmap_a),
736 FIELD64(IO_BITMAP_B, io_bitmap_b),
737 FIELD64(MSR_BITMAP, msr_bitmap),
738 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
739 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
740 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
741 FIELD64(TSC_OFFSET, tsc_offset),
742 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
743 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
744 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
745 FIELD64(EPT_POINTER, ept_pointer),
746 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
747 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
748 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
749 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
750 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
751 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
752 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
753 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
754 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
755 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
756 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
757 FIELD64(GUEST_PDPTR0, guest_pdptr0),
758 FIELD64(GUEST_PDPTR1, guest_pdptr1),
759 FIELD64(GUEST_PDPTR2, guest_pdptr2),
760 FIELD64(GUEST_PDPTR3, guest_pdptr3),
761 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
762 FIELD64(HOST_IA32_PAT, host_ia32_pat),
763 FIELD64(HOST_IA32_EFER, host_ia32_efer),
764 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
765 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
766 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
767 FIELD(EXCEPTION_BITMAP, exception_bitmap),
768 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
769 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
770 FIELD(CR3_TARGET_COUNT, cr3_target_count),
771 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
772 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
773 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
774 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
775 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
776 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
777 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
778 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
779 FIELD(TPR_THRESHOLD, tpr_threshold),
780 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
781 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
782 FIELD(VM_EXIT_REASON, vm_exit_reason),
783 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
784 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
785 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
786 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
787 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
788 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
789 FIELD(GUEST_ES_LIMIT, guest_es_limit),
790 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
791 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
792 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
793 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
794 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
795 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
796 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
797 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
798 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
799 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
800 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
801 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
802 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
803 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
804 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
805 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
806 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
807 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
808 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
809 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
810 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
811 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
812 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
813 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
814 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
815 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
816 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
817 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
818 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
819 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
820 FIELD(EXIT_QUALIFICATION, exit_qualification),
821 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
822 FIELD(GUEST_CR0, guest_cr0),
823 FIELD(GUEST_CR3, guest_cr3),
824 FIELD(GUEST_CR4, guest_cr4),
825 FIELD(GUEST_ES_BASE, guest_es_base),
826 FIELD(GUEST_CS_BASE, guest_cs_base),
827 FIELD(GUEST_SS_BASE, guest_ss_base),
828 FIELD(GUEST_DS_BASE, guest_ds_base),
829 FIELD(GUEST_FS_BASE, guest_fs_base),
830 FIELD(GUEST_GS_BASE, guest_gs_base),
831 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
832 FIELD(GUEST_TR_BASE, guest_tr_base),
833 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
834 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
835 FIELD(GUEST_DR7, guest_dr7),
836 FIELD(GUEST_RSP, guest_rsp),
837 FIELD(GUEST_RIP, guest_rip),
838 FIELD(GUEST_RFLAGS, guest_rflags),
839 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
840 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
841 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
842 FIELD(HOST_CR0, host_cr0),
843 FIELD(HOST_CR3, host_cr3),
844 FIELD(HOST_CR4, host_cr4),
845 FIELD(HOST_FS_BASE, host_fs_base),
846 FIELD(HOST_GS_BASE, host_gs_base),
847 FIELD(HOST_TR_BASE, host_tr_base),
848 FIELD(HOST_GDTR_BASE, host_gdtr_base),
849 FIELD(HOST_IDTR_BASE, host_idtr_base),
850 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
851 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
852 FIELD(HOST_RSP, host_rsp),
853 FIELD(HOST_RIP, host_rip),
856 static inline short vmcs_field_to_offset(unsigned long field)
858 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
860 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
861 vmcs_field_to_offset_table[field] == 0)
864 return vmcs_field_to_offset_table[field];
867 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
869 return to_vmx(vcpu)->nested.cached_vmcs12;
872 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
874 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
875 if (is_error_page(page))
881 static void nested_release_page(struct page *page)
883 kvm_release_page_dirty(page);
886 static void nested_release_page_clean(struct page *page)
888 kvm_release_page_clean(page);
891 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
892 static u64 construct_eptp(unsigned long root_hpa);
893 static void kvm_cpu_vmxon(u64 addr);
894 static void kvm_cpu_vmxoff(void);
895 static bool vmx_xsaves_supported(void);
896 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
897 static void vmx_set_segment(struct kvm_vcpu *vcpu,
898 struct kvm_segment *var, int seg);
899 static void vmx_get_segment(struct kvm_vcpu *vcpu,
900 struct kvm_segment *var, int seg);
901 static bool guest_state_valid(struct kvm_vcpu *vcpu);
902 static u32 vmx_segment_access_rights(struct kvm_segment *var);
903 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
904 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
905 static int alloc_identity_pagetable(struct kvm *kvm);
907 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
908 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
910 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
911 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
913 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
914 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
917 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
918 * can find which vCPU should be waken up.
920 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
921 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
923 static unsigned long *vmx_io_bitmap_a;
924 static unsigned long *vmx_io_bitmap_b;
925 static unsigned long *vmx_msr_bitmap_legacy;
926 static unsigned long *vmx_msr_bitmap_longmode;
927 static unsigned long *vmx_msr_bitmap_legacy_x2apic_apicv;
928 static unsigned long *vmx_msr_bitmap_longmode_x2apic_apicv;
929 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
930 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
931 static unsigned long *vmx_vmread_bitmap;
932 static unsigned long *vmx_vmwrite_bitmap;
934 static bool cpu_has_load_ia32_efer;
935 static bool cpu_has_load_perf_global_ctrl;
937 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
938 static DEFINE_SPINLOCK(vmx_vpid_lock);
940 static struct vmcs_config {
945 u32 pin_based_exec_ctrl;
946 u32 cpu_based_exec_ctrl;
947 u32 cpu_based_2nd_exec_ctrl;
952 static struct vmx_capability {
957 #define VMX_SEGMENT_FIELD(seg) \
958 [VCPU_SREG_##seg] = { \
959 .selector = GUEST_##seg##_SELECTOR, \
960 .base = GUEST_##seg##_BASE, \
961 .limit = GUEST_##seg##_LIMIT, \
962 .ar_bytes = GUEST_##seg##_AR_BYTES, \
965 static const struct kvm_vmx_segment_field {
970 } kvm_vmx_segment_fields[] = {
971 VMX_SEGMENT_FIELD(CS),
972 VMX_SEGMENT_FIELD(DS),
973 VMX_SEGMENT_FIELD(ES),
974 VMX_SEGMENT_FIELD(FS),
975 VMX_SEGMENT_FIELD(GS),
976 VMX_SEGMENT_FIELD(SS),
977 VMX_SEGMENT_FIELD(TR),
978 VMX_SEGMENT_FIELD(LDTR),
981 static u64 host_efer;
983 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
986 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
987 * away by decrementing the array size.
989 static const u32 vmx_msr_index[] = {
991 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
993 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
996 static inline bool is_exception_n(u32 intr_info, u8 vector)
998 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
999 INTR_INFO_VALID_MASK)) ==
1000 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1003 static inline bool is_debug(u32 intr_info)
1005 return is_exception_n(intr_info, DB_VECTOR);
1008 static inline bool is_breakpoint(u32 intr_info)
1010 return is_exception_n(intr_info, BP_VECTOR);
1013 static inline bool is_page_fault(u32 intr_info)
1015 return is_exception_n(intr_info, PF_VECTOR);
1018 static inline bool is_no_device(u32 intr_info)
1020 return is_exception_n(intr_info, NM_VECTOR);
1023 static inline bool is_invalid_opcode(u32 intr_info)
1025 return is_exception_n(intr_info, UD_VECTOR);
1028 static inline bool is_external_interrupt(u32 intr_info)
1030 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1031 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1034 static inline bool is_machine_check(u32 intr_info)
1036 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1037 INTR_INFO_VALID_MASK)) ==
1038 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1041 static inline bool cpu_has_vmx_msr_bitmap(void)
1043 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1046 static inline bool cpu_has_vmx_tpr_shadow(void)
1048 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1051 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1053 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1056 static inline bool cpu_has_secondary_exec_ctrls(void)
1058 return vmcs_config.cpu_based_exec_ctrl &
1059 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1062 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1064 return vmcs_config.cpu_based_2nd_exec_ctrl &
1065 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1068 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1070 return vmcs_config.cpu_based_2nd_exec_ctrl &
1071 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1074 static inline bool cpu_has_vmx_apic_register_virt(void)
1076 return vmcs_config.cpu_based_2nd_exec_ctrl &
1077 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1080 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1082 return vmcs_config.cpu_based_2nd_exec_ctrl &
1083 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1087 * Comment's format: document - errata name - stepping - processor name.
1089 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1091 static u32 vmx_preemption_cpu_tfms[] = {
1092 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1094 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1095 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1096 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1098 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1100 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1101 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1103 * 320767.pdf - AAP86 - B1 -
1104 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1107 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1109 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1111 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1113 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1114 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1115 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1119 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1121 u32 eax = cpuid_eax(0x00000001), i;
1123 /* Clear the reserved bits */
1124 eax &= ~(0x3U << 14 | 0xfU << 28);
1125 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1126 if (eax == vmx_preemption_cpu_tfms[i])
1132 static inline bool cpu_has_vmx_preemption_timer(void)
1134 return vmcs_config.pin_based_exec_ctrl &
1135 PIN_BASED_VMX_PREEMPTION_TIMER;
1138 static inline bool cpu_has_vmx_posted_intr(void)
1140 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1141 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1144 static inline bool cpu_has_vmx_apicv(void)
1146 return cpu_has_vmx_apic_register_virt() &&
1147 cpu_has_vmx_virtual_intr_delivery() &&
1148 cpu_has_vmx_posted_intr();
1151 static inline bool cpu_has_vmx_flexpriority(void)
1153 return cpu_has_vmx_tpr_shadow() &&
1154 cpu_has_vmx_virtualize_apic_accesses();
1157 static inline bool cpu_has_vmx_ept_execute_only(void)
1159 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1162 static inline bool cpu_has_vmx_ept_2m_page(void)
1164 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1167 static inline bool cpu_has_vmx_ept_1g_page(void)
1169 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1172 static inline bool cpu_has_vmx_ept_4levels(void)
1174 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1177 static inline bool cpu_has_vmx_ept_ad_bits(void)
1179 return vmx_capability.ept & VMX_EPT_AD_BIT;
1182 static inline bool cpu_has_vmx_invept_context(void)
1184 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1187 static inline bool cpu_has_vmx_invept_global(void)
1189 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1192 static inline bool cpu_has_vmx_invvpid_single(void)
1194 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1197 static inline bool cpu_has_vmx_invvpid_global(void)
1199 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1202 static inline bool cpu_has_vmx_ept(void)
1204 return vmcs_config.cpu_based_2nd_exec_ctrl &
1205 SECONDARY_EXEC_ENABLE_EPT;
1208 static inline bool cpu_has_vmx_unrestricted_guest(void)
1210 return vmcs_config.cpu_based_2nd_exec_ctrl &
1211 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1214 static inline bool cpu_has_vmx_ple(void)
1216 return vmcs_config.cpu_based_2nd_exec_ctrl &
1217 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1220 static inline bool cpu_has_vmx_basic_inout(void)
1222 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1225 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1227 return flexpriority_enabled && lapic_in_kernel(vcpu);
1230 static inline bool cpu_has_vmx_vpid(void)
1232 return vmcs_config.cpu_based_2nd_exec_ctrl &
1233 SECONDARY_EXEC_ENABLE_VPID;
1236 static inline bool cpu_has_vmx_rdtscp(void)
1238 return vmcs_config.cpu_based_2nd_exec_ctrl &
1239 SECONDARY_EXEC_RDTSCP;
1242 static inline bool cpu_has_vmx_invpcid(void)
1244 return vmcs_config.cpu_based_2nd_exec_ctrl &
1245 SECONDARY_EXEC_ENABLE_INVPCID;
1248 static inline bool cpu_has_virtual_nmis(void)
1250 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1253 static inline bool cpu_has_vmx_wbinvd_exit(void)
1255 return vmcs_config.cpu_based_2nd_exec_ctrl &
1256 SECONDARY_EXEC_WBINVD_EXITING;
1259 static inline bool cpu_has_vmx_shadow_vmcs(void)
1262 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1263 /* check if the cpu supports writing r/o exit information fields */
1264 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1267 return vmcs_config.cpu_based_2nd_exec_ctrl &
1268 SECONDARY_EXEC_SHADOW_VMCS;
1271 static inline bool cpu_has_vmx_pml(void)
1273 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1276 static inline bool cpu_has_vmx_tsc_scaling(void)
1278 return vmcs_config.cpu_based_2nd_exec_ctrl &
1279 SECONDARY_EXEC_TSC_SCALING;
1282 static inline bool report_flexpriority(void)
1284 return flexpriority_enabled;
1287 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1289 return vmcs12->cpu_based_vm_exec_control & bit;
1292 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1294 return (vmcs12->cpu_based_vm_exec_control &
1295 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1296 (vmcs12->secondary_vm_exec_control & bit);
1299 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1301 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1304 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1306 return vmcs12->pin_based_vm_exec_control &
1307 PIN_BASED_VMX_PREEMPTION_TIMER;
1310 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1312 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1315 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1317 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1318 vmx_xsaves_supported();
1321 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1323 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1326 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1328 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1331 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1333 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1336 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1338 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1341 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1343 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1346 static inline bool is_exception(u32 intr_info)
1348 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1349 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1352 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1354 unsigned long exit_qualification);
1355 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1356 struct vmcs12 *vmcs12,
1357 u32 reason, unsigned long qualification);
1359 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1363 for (i = 0; i < vmx->nmsrs; ++i)
1364 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1369 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1375 } operand = { vpid, 0, gva };
1377 asm volatile (__ex(ASM_VMX_INVVPID)
1378 /* CF==1 or ZF==1 --> rc = -1 */
1379 "; ja 1f ; ud2 ; 1:"
1380 : : "a"(&operand), "c"(ext) : "cc", "memory");
1383 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1387 } operand = {eptp, gpa};
1389 asm volatile (__ex(ASM_VMX_INVEPT)
1390 /* CF==1 or ZF==1 --> rc = -1 */
1391 "; ja 1f ; ud2 ; 1:\n"
1392 : : "a" (&operand), "c" (ext) : "cc", "memory");
1395 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1399 i = __find_msr_index(vmx, msr);
1401 return &vmx->guest_msrs[i];
1405 static void vmcs_clear(struct vmcs *vmcs)
1407 u64 phys_addr = __pa(vmcs);
1410 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1411 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1414 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1418 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1420 vmcs_clear(loaded_vmcs->vmcs);
1421 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1422 vmcs_clear(loaded_vmcs->shadow_vmcs);
1423 loaded_vmcs->cpu = -1;
1424 loaded_vmcs->launched = 0;
1427 static void vmcs_load(struct vmcs *vmcs)
1429 u64 phys_addr = __pa(vmcs);
1432 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1433 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1436 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1440 #ifdef CONFIG_KEXEC_CORE
1442 * This bitmap is used to indicate whether the vmclear
1443 * operation is enabled on all cpus. All disabled by
1446 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1448 static inline void crash_enable_local_vmclear(int cpu)
1450 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1453 static inline void crash_disable_local_vmclear(int cpu)
1455 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1458 static inline int crash_local_vmclear_enabled(int cpu)
1460 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1463 static void crash_vmclear_local_loaded_vmcss(void)
1465 int cpu = raw_smp_processor_id();
1466 struct loaded_vmcs *v;
1468 if (!crash_local_vmclear_enabled(cpu))
1471 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1472 loaded_vmcss_on_cpu_link)
1473 vmcs_clear(v->vmcs);
1476 static inline void crash_enable_local_vmclear(int cpu) { }
1477 static inline void crash_disable_local_vmclear(int cpu) { }
1478 #endif /* CONFIG_KEXEC_CORE */
1480 static void __loaded_vmcs_clear(void *arg)
1482 struct loaded_vmcs *loaded_vmcs = arg;
1483 int cpu = raw_smp_processor_id();
1485 if (loaded_vmcs->cpu != cpu)
1486 return; /* vcpu migration can race with cpu offline */
1487 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1488 per_cpu(current_vmcs, cpu) = NULL;
1489 crash_disable_local_vmclear(cpu);
1490 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1493 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1494 * is before setting loaded_vmcs->vcpu to -1 which is done in
1495 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1496 * then adds the vmcs into percpu list before it is deleted.
1500 loaded_vmcs_init(loaded_vmcs);
1501 crash_enable_local_vmclear(cpu);
1504 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1506 int cpu = loaded_vmcs->cpu;
1509 smp_call_function_single(cpu,
1510 __loaded_vmcs_clear, loaded_vmcs, 1);
1513 static inline void vpid_sync_vcpu_single(int vpid)
1518 if (cpu_has_vmx_invvpid_single())
1519 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1522 static inline void vpid_sync_vcpu_global(void)
1524 if (cpu_has_vmx_invvpid_global())
1525 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1528 static inline void vpid_sync_context(int vpid)
1530 if (cpu_has_vmx_invvpid_single())
1531 vpid_sync_vcpu_single(vpid);
1533 vpid_sync_vcpu_global();
1536 static inline void ept_sync_global(void)
1538 if (cpu_has_vmx_invept_global())
1539 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1542 static inline void ept_sync_context(u64 eptp)
1545 if (cpu_has_vmx_invept_context())
1546 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1552 static __always_inline void vmcs_check16(unsigned long field)
1554 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1555 "16-bit accessor invalid for 64-bit field");
1556 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1557 "16-bit accessor invalid for 64-bit high field");
1558 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1559 "16-bit accessor invalid for 32-bit high field");
1560 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1561 "16-bit accessor invalid for natural width field");
1564 static __always_inline void vmcs_check32(unsigned long field)
1566 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1567 "32-bit accessor invalid for 16-bit field");
1568 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1569 "32-bit accessor invalid for natural width field");
1572 static __always_inline void vmcs_check64(unsigned long field)
1574 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1575 "64-bit accessor invalid for 16-bit field");
1576 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1577 "64-bit accessor invalid for 64-bit high field");
1578 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1579 "64-bit accessor invalid for 32-bit field");
1580 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1581 "64-bit accessor invalid for natural width field");
1584 static __always_inline void vmcs_checkl(unsigned long field)
1586 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1587 "Natural width accessor invalid for 16-bit field");
1588 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1589 "Natural width accessor invalid for 64-bit field");
1590 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1591 "Natural width accessor invalid for 64-bit high field");
1592 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1593 "Natural width accessor invalid for 32-bit field");
1596 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1598 unsigned long value;
1600 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1601 : "=a"(value) : "d"(field) : "cc");
1605 static __always_inline u16 vmcs_read16(unsigned long field)
1607 vmcs_check16(field);
1608 return __vmcs_readl(field);
1611 static __always_inline u32 vmcs_read32(unsigned long field)
1613 vmcs_check32(field);
1614 return __vmcs_readl(field);
1617 static __always_inline u64 vmcs_read64(unsigned long field)
1619 vmcs_check64(field);
1620 #ifdef CONFIG_X86_64
1621 return __vmcs_readl(field);
1623 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1627 static __always_inline unsigned long vmcs_readl(unsigned long field)
1630 return __vmcs_readl(field);
1633 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1635 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1636 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1640 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1644 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1645 : "=q"(error) : "a"(value), "d"(field) : "cc");
1646 if (unlikely(error))
1647 vmwrite_error(field, value);
1650 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1652 vmcs_check16(field);
1653 __vmcs_writel(field, value);
1656 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1658 vmcs_check32(field);
1659 __vmcs_writel(field, value);
1662 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1664 vmcs_check64(field);
1665 __vmcs_writel(field, value);
1666 #ifndef CONFIG_X86_64
1668 __vmcs_writel(field+1, value >> 32);
1672 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1675 __vmcs_writel(field, value);
1678 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1680 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1681 "vmcs_clear_bits does not support 64-bit fields");
1682 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1685 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1687 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1688 "vmcs_set_bits does not support 64-bit fields");
1689 __vmcs_writel(field, __vmcs_readl(field) | mask);
1692 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1694 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1697 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1699 vmcs_write32(VM_ENTRY_CONTROLS, val);
1700 vmx->vm_entry_controls_shadow = val;
1703 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1705 if (vmx->vm_entry_controls_shadow != val)
1706 vm_entry_controls_init(vmx, val);
1709 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1711 return vmx->vm_entry_controls_shadow;
1715 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1717 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1720 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1722 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1725 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1727 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1730 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1732 vmcs_write32(VM_EXIT_CONTROLS, val);
1733 vmx->vm_exit_controls_shadow = val;
1736 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1738 if (vmx->vm_exit_controls_shadow != val)
1739 vm_exit_controls_init(vmx, val);
1742 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1744 return vmx->vm_exit_controls_shadow;
1748 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1750 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1753 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1755 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1758 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1760 vmx->segment_cache.bitmask = 0;
1763 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1767 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1769 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1770 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1771 vmx->segment_cache.bitmask = 0;
1773 ret = vmx->segment_cache.bitmask & mask;
1774 vmx->segment_cache.bitmask |= mask;
1778 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1780 u16 *p = &vmx->segment_cache.seg[seg].selector;
1782 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1783 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1787 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1789 ulong *p = &vmx->segment_cache.seg[seg].base;
1791 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1792 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1796 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1798 u32 *p = &vmx->segment_cache.seg[seg].limit;
1800 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1801 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1805 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1807 u32 *p = &vmx->segment_cache.seg[seg].ar;
1809 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1810 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1814 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1818 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1819 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1820 if ((vcpu->guest_debug &
1821 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1822 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1823 eb |= 1u << BP_VECTOR;
1824 if (to_vmx(vcpu)->rmode.vm86_active)
1827 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1828 if (vcpu->fpu_active)
1829 eb &= ~(1u << NM_VECTOR);
1831 /* When we are running a nested L2 guest and L1 specified for it a
1832 * certain exception bitmap, we must trap the same exceptions and pass
1833 * them to L1. When running L2, we will only handle the exceptions
1834 * specified above if L1 did not want them.
1836 if (is_guest_mode(vcpu))
1837 eb |= get_vmcs12(vcpu)->exception_bitmap;
1839 vmcs_write32(EXCEPTION_BITMAP, eb);
1842 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1843 unsigned long entry, unsigned long exit)
1845 vm_entry_controls_clearbit(vmx, entry);
1846 vm_exit_controls_clearbit(vmx, exit);
1849 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1852 struct msr_autoload *m = &vmx->msr_autoload;
1856 if (cpu_has_load_ia32_efer) {
1857 clear_atomic_switch_msr_special(vmx,
1858 VM_ENTRY_LOAD_IA32_EFER,
1859 VM_EXIT_LOAD_IA32_EFER);
1863 case MSR_CORE_PERF_GLOBAL_CTRL:
1864 if (cpu_has_load_perf_global_ctrl) {
1865 clear_atomic_switch_msr_special(vmx,
1866 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1867 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1873 for (i = 0; i < m->nr; ++i)
1874 if (m->guest[i].index == msr)
1880 m->guest[i] = m->guest[m->nr];
1881 m->host[i] = m->host[m->nr];
1882 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1883 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1886 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1887 unsigned long entry, unsigned long exit,
1888 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1889 u64 guest_val, u64 host_val)
1891 vmcs_write64(guest_val_vmcs, guest_val);
1892 vmcs_write64(host_val_vmcs, host_val);
1893 vm_entry_controls_setbit(vmx, entry);
1894 vm_exit_controls_setbit(vmx, exit);
1897 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1898 u64 guest_val, u64 host_val)
1901 struct msr_autoload *m = &vmx->msr_autoload;
1905 if (cpu_has_load_ia32_efer) {
1906 add_atomic_switch_msr_special(vmx,
1907 VM_ENTRY_LOAD_IA32_EFER,
1908 VM_EXIT_LOAD_IA32_EFER,
1911 guest_val, host_val);
1915 case MSR_CORE_PERF_GLOBAL_CTRL:
1916 if (cpu_has_load_perf_global_ctrl) {
1917 add_atomic_switch_msr_special(vmx,
1918 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1919 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1920 GUEST_IA32_PERF_GLOBAL_CTRL,
1921 HOST_IA32_PERF_GLOBAL_CTRL,
1922 guest_val, host_val);
1926 case MSR_IA32_PEBS_ENABLE:
1927 /* PEBS needs a quiescent period after being disabled (to write
1928 * a record). Disabling PEBS through VMX MSR swapping doesn't
1929 * provide that period, so a CPU could write host's record into
1932 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1935 for (i = 0; i < m->nr; ++i)
1936 if (m->guest[i].index == msr)
1939 if (i == NR_AUTOLOAD_MSRS) {
1940 printk_once(KERN_WARNING "Not enough msr switch entries. "
1941 "Can't add msr %x\n", msr);
1943 } else if (i == m->nr) {
1945 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1946 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1949 m->guest[i].index = msr;
1950 m->guest[i].value = guest_val;
1951 m->host[i].index = msr;
1952 m->host[i].value = host_val;
1955 static void reload_tss(void)
1958 * VT restores TR but not its size. Useless.
1960 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1961 struct desc_struct *descs;
1963 descs = (void *)gdt->address;
1964 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1968 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1970 u64 guest_efer = vmx->vcpu.arch.efer;
1971 u64 ignore_bits = 0;
1975 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1976 * host CPUID is more efficient than testing guest CPUID
1977 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1979 if (boot_cpu_has(X86_FEATURE_SMEP))
1980 guest_efer |= EFER_NX;
1981 else if (!(guest_efer & EFER_NX))
1982 ignore_bits |= EFER_NX;
1986 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1988 ignore_bits |= EFER_SCE;
1989 #ifdef CONFIG_X86_64
1990 ignore_bits |= EFER_LMA | EFER_LME;
1991 /* SCE is meaningful only in long mode on Intel */
1992 if (guest_efer & EFER_LMA)
1993 ignore_bits &= ~(u64)EFER_SCE;
1996 clear_atomic_switch_msr(vmx, MSR_EFER);
1999 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2000 * On CPUs that support "load IA32_EFER", always switch EFER
2001 * atomically, since it's faster than switching it manually.
2003 if (cpu_has_load_ia32_efer ||
2004 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2005 if (!(guest_efer & EFER_LMA))
2006 guest_efer &= ~EFER_LME;
2007 if (guest_efer != host_efer)
2008 add_atomic_switch_msr(vmx, MSR_EFER,
2009 guest_efer, host_efer);
2012 guest_efer &= ~ignore_bits;
2013 guest_efer |= host_efer & ignore_bits;
2015 vmx->guest_msrs[efer_offset].data = guest_efer;
2016 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2022 static unsigned long segment_base(u16 selector)
2024 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2025 struct desc_struct *d;
2026 unsigned long table_base;
2029 if (!(selector & ~3))
2032 table_base = gdt->address;
2034 if (selector & 4) { /* from ldt */
2035 u16 ldt_selector = kvm_read_ldt();
2037 if (!(ldt_selector & ~3))
2040 table_base = segment_base(ldt_selector);
2042 d = (struct desc_struct *)(table_base + (selector & ~7));
2043 v = get_desc_base(d);
2044 #ifdef CONFIG_X86_64
2045 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2046 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2051 static inline unsigned long kvm_read_tr_base(void)
2054 asm("str %0" : "=g"(tr));
2055 return segment_base(tr);
2058 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2060 struct vcpu_vmx *vmx = to_vmx(vcpu);
2063 if (vmx->host_state.loaded)
2066 vmx->host_state.loaded = 1;
2068 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2069 * allow segment selectors with cpl > 0 or ti == 1.
2071 vmx->host_state.ldt_sel = kvm_read_ldt();
2072 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2073 savesegment(fs, vmx->host_state.fs_sel);
2074 if (!(vmx->host_state.fs_sel & 7)) {
2075 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2076 vmx->host_state.fs_reload_needed = 0;
2078 vmcs_write16(HOST_FS_SELECTOR, 0);
2079 vmx->host_state.fs_reload_needed = 1;
2081 savesegment(gs, vmx->host_state.gs_sel);
2082 if (!(vmx->host_state.gs_sel & 7))
2083 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2085 vmcs_write16(HOST_GS_SELECTOR, 0);
2086 vmx->host_state.gs_ldt_reload_needed = 1;
2089 #ifdef CONFIG_X86_64
2090 savesegment(ds, vmx->host_state.ds_sel);
2091 savesegment(es, vmx->host_state.es_sel);
2094 #ifdef CONFIG_X86_64
2095 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2096 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2098 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2099 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2102 #ifdef CONFIG_X86_64
2103 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2104 if (is_long_mode(&vmx->vcpu))
2105 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2107 if (boot_cpu_has(X86_FEATURE_MPX))
2108 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2109 for (i = 0; i < vmx->save_nmsrs; ++i)
2110 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2111 vmx->guest_msrs[i].data,
2112 vmx->guest_msrs[i].mask);
2115 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2117 if (!vmx->host_state.loaded)
2120 ++vmx->vcpu.stat.host_state_reload;
2121 vmx->host_state.loaded = 0;
2122 #ifdef CONFIG_X86_64
2123 if (is_long_mode(&vmx->vcpu))
2124 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2126 if (vmx->host_state.gs_ldt_reload_needed) {
2127 kvm_load_ldt(vmx->host_state.ldt_sel);
2128 #ifdef CONFIG_X86_64
2129 load_gs_index(vmx->host_state.gs_sel);
2131 loadsegment(gs, vmx->host_state.gs_sel);
2134 if (vmx->host_state.fs_reload_needed)
2135 loadsegment(fs, vmx->host_state.fs_sel);
2136 #ifdef CONFIG_X86_64
2137 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2138 loadsegment(ds, vmx->host_state.ds_sel);
2139 loadsegment(es, vmx->host_state.es_sel);
2143 #ifdef CONFIG_X86_64
2144 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2146 if (vmx->host_state.msr_host_bndcfgs)
2147 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2149 * If the FPU is not active (through the host task or
2150 * the guest vcpu), then restore the cr0.TS bit.
2152 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2154 load_gdt(this_cpu_ptr(&host_gdt));
2157 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2160 __vmx_load_host_state(vmx);
2164 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2166 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2167 struct pi_desc old, new;
2170 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2171 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2172 !kvm_vcpu_apicv_active(vcpu))
2176 old.control = new.control = pi_desc->control;
2179 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2180 * are two possible cases:
2181 * 1. After running 'pre_block', context switch
2182 * happened. For this case, 'sn' was set in
2183 * vmx_vcpu_put(), so we need to clear it here.
2184 * 2. After running 'pre_block', we were blocked,
2185 * and woken up by some other guy. For this case,
2186 * we don't need to do anything, 'pi_post_block'
2187 * will do everything for us. However, we cannot
2188 * check whether it is case #1 or case #2 here
2189 * (maybe, not needed), so we also clear sn here,
2190 * I think it is not a big deal.
2192 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2193 if (vcpu->cpu != cpu) {
2194 dest = cpu_physical_id(cpu);
2196 if (x2apic_enabled())
2199 new.ndst = (dest << 8) & 0xFF00;
2202 /* set 'NV' to 'notification vector' */
2203 new.nv = POSTED_INTR_VECTOR;
2206 /* Allow posting non-urgent interrupts */
2208 } while (cmpxchg(&pi_desc->control, old.control,
2209 new.control) != old.control);
2212 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2214 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2215 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2219 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2220 * vcpu mutex is already taken.
2222 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2224 struct vcpu_vmx *vmx = to_vmx(vcpu);
2225 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2226 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2229 kvm_cpu_vmxon(phys_addr);
2230 else if (!already_loaded)
2231 loaded_vmcs_clear(vmx->loaded_vmcs);
2233 if (!already_loaded) {
2234 local_irq_disable();
2235 crash_disable_local_vmclear(cpu);
2238 * Read loaded_vmcs->cpu should be before fetching
2239 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2240 * See the comments in __loaded_vmcs_clear().
2244 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2245 &per_cpu(loaded_vmcss_on_cpu, cpu));
2246 crash_enable_local_vmclear(cpu);
2250 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2251 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2252 vmcs_load(vmx->loaded_vmcs->vmcs);
2255 if (!already_loaded) {
2256 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2257 unsigned long sysenter_esp;
2259 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2262 * Linux uses per-cpu TSS and GDT, so set these when switching
2265 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2266 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2268 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2269 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2271 vmx->loaded_vmcs->cpu = cpu;
2274 /* Setup TSC multiplier */
2275 if (kvm_has_tsc_control &&
2276 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2277 decache_tsc_multiplier(vmx);
2279 vmx_vcpu_pi_load(vcpu, cpu);
2280 vmx->host_pkru = read_pkru();
2283 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2285 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2287 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2288 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2289 !kvm_vcpu_apicv_active(vcpu))
2292 /* Set SN when the vCPU is preempted */
2293 if (vcpu->preempted)
2297 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2299 vmx_vcpu_pi_put(vcpu);
2301 __vmx_load_host_state(to_vmx(vcpu));
2302 if (!vmm_exclusive) {
2303 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2309 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2313 if (vcpu->fpu_active)
2315 vcpu->fpu_active = 1;
2316 cr0 = vmcs_readl(GUEST_CR0);
2317 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2318 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2319 vmcs_writel(GUEST_CR0, cr0);
2320 update_exception_bitmap(vcpu);
2321 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2322 if (is_guest_mode(vcpu))
2323 vcpu->arch.cr0_guest_owned_bits &=
2324 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2325 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2328 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2331 * Return the cr0 value that a nested guest would read. This is a combination
2332 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2333 * its hypervisor (cr0_read_shadow).
2335 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2337 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2338 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2340 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2342 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2343 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2346 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2348 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2349 * set this *before* calling this function.
2351 vmx_decache_cr0_guest_bits(vcpu);
2352 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2353 update_exception_bitmap(vcpu);
2354 vcpu->arch.cr0_guest_owned_bits = 0;
2355 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2356 if (is_guest_mode(vcpu)) {
2358 * L1's specified read shadow might not contain the TS bit,
2359 * so now that we turned on shadowing of this bit, we need to
2360 * set this bit of the shadow. Like in nested_vmx_run we need
2361 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2362 * up-to-date here because we just decached cr0.TS (and we'll
2363 * only update vmcs12->guest_cr0 on nested exit).
2365 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2366 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2367 (vcpu->arch.cr0 & X86_CR0_TS);
2368 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2370 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2373 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2375 unsigned long rflags, save_rflags;
2377 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2378 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2379 rflags = vmcs_readl(GUEST_RFLAGS);
2380 if (to_vmx(vcpu)->rmode.vm86_active) {
2381 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2382 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2383 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2385 to_vmx(vcpu)->rflags = rflags;
2387 return to_vmx(vcpu)->rflags;
2390 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2392 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2393 to_vmx(vcpu)->rflags = rflags;
2394 if (to_vmx(vcpu)->rmode.vm86_active) {
2395 to_vmx(vcpu)->rmode.save_rflags = rflags;
2396 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2398 vmcs_writel(GUEST_RFLAGS, rflags);
2401 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2403 return to_vmx(vcpu)->guest_pkru;
2406 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2408 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2411 if (interruptibility & GUEST_INTR_STATE_STI)
2412 ret |= KVM_X86_SHADOW_INT_STI;
2413 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2414 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2419 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2421 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2422 u32 interruptibility = interruptibility_old;
2424 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2426 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2427 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2428 else if (mask & KVM_X86_SHADOW_INT_STI)
2429 interruptibility |= GUEST_INTR_STATE_STI;
2431 if ((interruptibility != interruptibility_old))
2432 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2435 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2439 rip = kvm_rip_read(vcpu);
2440 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2441 kvm_rip_write(vcpu, rip);
2443 /* skipping an emulated instruction also counts */
2444 vmx_set_interrupt_shadow(vcpu, 0);
2448 * KVM wants to inject page-faults which it got to the guest. This function
2449 * checks whether in a nested guest, we need to inject them to L1 or L2.
2451 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2453 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2455 if (!(vmcs12->exception_bitmap & (1u << nr)))
2458 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2459 vmcs_read32(VM_EXIT_INTR_INFO),
2460 vmcs_readl(EXIT_QUALIFICATION));
2464 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2465 bool has_error_code, u32 error_code,
2468 struct vcpu_vmx *vmx = to_vmx(vcpu);
2469 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2471 if (!reinject && is_guest_mode(vcpu) &&
2472 nested_vmx_check_exception(vcpu, nr))
2475 if (has_error_code) {
2476 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2477 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2480 if (vmx->rmode.vm86_active) {
2482 if (kvm_exception_is_soft(nr))
2483 inc_eip = vcpu->arch.event_exit_inst_len;
2484 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2485 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2489 if (kvm_exception_is_soft(nr)) {
2490 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2491 vmx->vcpu.arch.event_exit_inst_len);
2492 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2494 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2496 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2499 static bool vmx_rdtscp_supported(void)
2501 return cpu_has_vmx_rdtscp();
2504 static bool vmx_invpcid_supported(void)
2506 return cpu_has_vmx_invpcid() && enable_ept;
2510 * Swap MSR entry in host/guest MSR entry array.
2512 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2514 struct shared_msr_entry tmp;
2516 tmp = vmx->guest_msrs[to];
2517 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2518 vmx->guest_msrs[from] = tmp;
2521 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2523 unsigned long *msr_bitmap;
2525 if (is_guest_mode(vcpu))
2526 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2527 else if (cpu_has_secondary_exec_ctrls() &&
2528 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2529 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2530 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2531 if (is_long_mode(vcpu))
2532 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2534 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2536 if (is_long_mode(vcpu))
2537 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2539 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2542 if (is_long_mode(vcpu))
2543 msr_bitmap = vmx_msr_bitmap_longmode;
2545 msr_bitmap = vmx_msr_bitmap_legacy;
2548 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2552 * Set up the vmcs to automatically save and restore system
2553 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2554 * mode, as fiddling with msrs is very expensive.
2556 static void setup_msrs(struct vcpu_vmx *vmx)
2558 int save_nmsrs, index;
2561 #ifdef CONFIG_X86_64
2562 if (is_long_mode(&vmx->vcpu)) {
2563 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2565 move_msr_up(vmx, index, save_nmsrs++);
2566 index = __find_msr_index(vmx, MSR_LSTAR);
2568 move_msr_up(vmx, index, save_nmsrs++);
2569 index = __find_msr_index(vmx, MSR_CSTAR);
2571 move_msr_up(vmx, index, save_nmsrs++);
2572 index = __find_msr_index(vmx, MSR_TSC_AUX);
2573 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2574 move_msr_up(vmx, index, save_nmsrs++);
2576 * MSR_STAR is only needed on long mode guests, and only
2577 * if efer.sce is enabled.
2579 index = __find_msr_index(vmx, MSR_STAR);
2580 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2581 move_msr_up(vmx, index, save_nmsrs++);
2584 index = __find_msr_index(vmx, MSR_EFER);
2585 if (index >= 0 && update_transition_efer(vmx, index))
2586 move_msr_up(vmx, index, save_nmsrs++);
2588 vmx->save_nmsrs = save_nmsrs;
2590 if (cpu_has_vmx_msr_bitmap())
2591 vmx_set_msr_bitmap(&vmx->vcpu);
2595 * reads and returns guest's timestamp counter "register"
2596 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2597 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2599 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2601 u64 host_tsc, tsc_offset;
2604 tsc_offset = vmcs_read64(TSC_OFFSET);
2605 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2609 * writes 'offset' into guest's timestamp counter offset register
2611 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2613 if (is_guest_mode(vcpu)) {
2615 * We're here if L1 chose not to trap WRMSR to TSC. According
2616 * to the spec, this should set L1's TSC; The offset that L1
2617 * set for L2 remains unchanged, and still needs to be added
2618 * to the newly set TSC to get L2's TSC.
2620 struct vmcs12 *vmcs12;
2621 /* recalculate vmcs02.TSC_OFFSET: */
2622 vmcs12 = get_vmcs12(vcpu);
2623 vmcs_write64(TSC_OFFSET, offset +
2624 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2625 vmcs12->tsc_offset : 0));
2627 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2628 vmcs_read64(TSC_OFFSET), offset);
2629 vmcs_write64(TSC_OFFSET, offset);
2633 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2635 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2636 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2640 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2641 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2642 * all guests if the "nested" module option is off, and can also be disabled
2643 * for a single guest by disabling its VMX cpuid bit.
2645 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2647 return nested && guest_cpuid_has_vmx(vcpu);
2651 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2652 * returned for the various VMX controls MSRs when nested VMX is enabled.
2653 * The same values should also be used to verify that vmcs12 control fields are
2654 * valid during nested entry from L1 to L2.
2655 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2656 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2657 * bit in the high half is on if the corresponding bit in the control field
2658 * may be on. See also vmx_control_verify().
2660 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2663 * Note that as a general rule, the high half of the MSRs (bits in
2664 * the control fields which may be 1) should be initialized by the
2665 * intersection of the underlying hardware's MSR (i.e., features which
2666 * can be supported) and the list of features we want to expose -
2667 * because they are known to be properly supported in our code.
2668 * Also, usually, the low half of the MSRs (bits which must be 1) can
2669 * be set to 0, meaning that L1 may turn off any of these bits. The
2670 * reason is that if one of these bits is necessary, it will appear
2671 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2672 * fields of vmcs01 and vmcs02, will turn these bits off - and
2673 * nested_vmx_exit_handled() will not pass related exits to L1.
2674 * These rules have exceptions below.
2677 /* pin-based controls */
2678 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2679 vmx->nested.nested_vmx_pinbased_ctls_low,
2680 vmx->nested.nested_vmx_pinbased_ctls_high);
2681 vmx->nested.nested_vmx_pinbased_ctls_low |=
2682 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2683 vmx->nested.nested_vmx_pinbased_ctls_high &=
2684 PIN_BASED_EXT_INTR_MASK |
2685 PIN_BASED_NMI_EXITING |
2686 PIN_BASED_VIRTUAL_NMIS;
2687 vmx->nested.nested_vmx_pinbased_ctls_high |=
2688 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2689 PIN_BASED_VMX_PREEMPTION_TIMER;
2690 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2691 vmx->nested.nested_vmx_pinbased_ctls_high |=
2692 PIN_BASED_POSTED_INTR;
2695 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2696 vmx->nested.nested_vmx_exit_ctls_low,
2697 vmx->nested.nested_vmx_exit_ctls_high);
2698 vmx->nested.nested_vmx_exit_ctls_low =
2699 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2701 vmx->nested.nested_vmx_exit_ctls_high &=
2702 #ifdef CONFIG_X86_64
2703 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2705 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2706 vmx->nested.nested_vmx_exit_ctls_high |=
2707 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2708 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2709 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2711 if (kvm_mpx_supported())
2712 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2714 /* We support free control of debug control saving. */
2715 vmx->nested.nested_vmx_true_exit_ctls_low =
2716 vmx->nested.nested_vmx_exit_ctls_low &
2717 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2719 /* entry controls */
2720 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2721 vmx->nested.nested_vmx_entry_ctls_low,
2722 vmx->nested.nested_vmx_entry_ctls_high);
2723 vmx->nested.nested_vmx_entry_ctls_low =
2724 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2725 vmx->nested.nested_vmx_entry_ctls_high &=
2726 #ifdef CONFIG_X86_64
2727 VM_ENTRY_IA32E_MODE |
2729 VM_ENTRY_LOAD_IA32_PAT;
2730 vmx->nested.nested_vmx_entry_ctls_high |=
2731 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2732 if (kvm_mpx_supported())
2733 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2735 /* We support free control of debug control loading. */
2736 vmx->nested.nested_vmx_true_entry_ctls_low =
2737 vmx->nested.nested_vmx_entry_ctls_low &
2738 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2740 /* cpu-based controls */
2741 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2742 vmx->nested.nested_vmx_procbased_ctls_low,
2743 vmx->nested.nested_vmx_procbased_ctls_high);
2744 vmx->nested.nested_vmx_procbased_ctls_low =
2745 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2746 vmx->nested.nested_vmx_procbased_ctls_high &=
2747 CPU_BASED_VIRTUAL_INTR_PENDING |
2748 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2749 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2750 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2751 CPU_BASED_CR3_STORE_EXITING |
2752 #ifdef CONFIG_X86_64
2753 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2755 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2756 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2757 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2758 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2759 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2761 * We can allow some features even when not supported by the
2762 * hardware. For example, L1 can specify an MSR bitmap - and we
2763 * can use it to avoid exits to L1 - even when L0 runs L2
2764 * without MSR bitmaps.
2766 vmx->nested.nested_vmx_procbased_ctls_high |=
2767 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2768 CPU_BASED_USE_MSR_BITMAPS;
2770 /* We support free control of CR3 access interception. */
2771 vmx->nested.nested_vmx_true_procbased_ctls_low =
2772 vmx->nested.nested_vmx_procbased_ctls_low &
2773 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2775 /* secondary cpu-based controls */
2776 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2777 vmx->nested.nested_vmx_secondary_ctls_low,
2778 vmx->nested.nested_vmx_secondary_ctls_high);
2779 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2780 vmx->nested.nested_vmx_secondary_ctls_high &=
2781 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2782 SECONDARY_EXEC_RDTSCP |
2783 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2784 SECONDARY_EXEC_ENABLE_VPID |
2785 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2786 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2787 SECONDARY_EXEC_WBINVD_EXITING |
2788 SECONDARY_EXEC_XSAVES;
2791 /* nested EPT: emulate EPT also to L1 */
2792 vmx->nested.nested_vmx_secondary_ctls_high |=
2793 SECONDARY_EXEC_ENABLE_EPT;
2794 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2795 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2797 if (cpu_has_vmx_ept_execute_only())
2798 vmx->nested.nested_vmx_ept_caps |=
2799 VMX_EPT_EXECUTE_ONLY_BIT;
2800 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2801 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2802 VMX_EPT_EXTENT_CONTEXT_BIT;
2804 vmx->nested.nested_vmx_ept_caps = 0;
2807 * Old versions of KVM use the single-context version without
2808 * checking for support, so declare that it is supported even
2809 * though it is treated as global context. The alternative is
2810 * not failing the single-context invvpid, and it is worse.
2813 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2814 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2815 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2817 vmx->nested.nested_vmx_vpid_caps = 0;
2819 if (enable_unrestricted_guest)
2820 vmx->nested.nested_vmx_secondary_ctls_high |=
2821 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2823 /* miscellaneous data */
2824 rdmsr(MSR_IA32_VMX_MISC,
2825 vmx->nested.nested_vmx_misc_low,
2826 vmx->nested.nested_vmx_misc_high);
2827 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2828 vmx->nested.nested_vmx_misc_low |=
2829 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2830 VMX_MISC_ACTIVITY_HLT;
2831 vmx->nested.nested_vmx_misc_high = 0;
2834 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2837 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2839 return ((control & high) | low) == control;
2842 static inline u64 vmx_control_msr(u32 low, u32 high)
2844 return low | ((u64)high << 32);
2847 /* Returns 0 on success, non-0 otherwise. */
2848 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2850 struct vcpu_vmx *vmx = to_vmx(vcpu);
2852 switch (msr_index) {
2853 case MSR_IA32_VMX_BASIC:
2855 * This MSR reports some information about VMX support. We
2856 * should return information about the VMX we emulate for the
2857 * guest, and the VMCS structure we give it - not about the
2858 * VMX support of the underlying hardware.
2860 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2861 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2862 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2863 if (cpu_has_vmx_basic_inout())
2864 *pdata |= VMX_BASIC_INOUT;
2866 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2867 case MSR_IA32_VMX_PINBASED_CTLS:
2868 *pdata = vmx_control_msr(
2869 vmx->nested.nested_vmx_pinbased_ctls_low,
2870 vmx->nested.nested_vmx_pinbased_ctls_high);
2872 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2873 *pdata = vmx_control_msr(
2874 vmx->nested.nested_vmx_true_procbased_ctls_low,
2875 vmx->nested.nested_vmx_procbased_ctls_high);
2877 case MSR_IA32_VMX_PROCBASED_CTLS:
2878 *pdata = vmx_control_msr(
2879 vmx->nested.nested_vmx_procbased_ctls_low,
2880 vmx->nested.nested_vmx_procbased_ctls_high);
2882 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2883 *pdata = vmx_control_msr(
2884 vmx->nested.nested_vmx_true_exit_ctls_low,
2885 vmx->nested.nested_vmx_exit_ctls_high);
2887 case MSR_IA32_VMX_EXIT_CTLS:
2888 *pdata = vmx_control_msr(
2889 vmx->nested.nested_vmx_exit_ctls_low,
2890 vmx->nested.nested_vmx_exit_ctls_high);
2892 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2893 *pdata = vmx_control_msr(
2894 vmx->nested.nested_vmx_true_entry_ctls_low,
2895 vmx->nested.nested_vmx_entry_ctls_high);
2897 case MSR_IA32_VMX_ENTRY_CTLS:
2898 *pdata = vmx_control_msr(
2899 vmx->nested.nested_vmx_entry_ctls_low,
2900 vmx->nested.nested_vmx_entry_ctls_high);
2902 case MSR_IA32_VMX_MISC:
2903 *pdata = vmx_control_msr(
2904 vmx->nested.nested_vmx_misc_low,
2905 vmx->nested.nested_vmx_misc_high);
2908 * These MSRs specify bits which the guest must keep fixed (on or off)
2909 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2910 * We picked the standard core2 setting.
2912 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2913 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2914 case MSR_IA32_VMX_CR0_FIXED0:
2915 *pdata = VMXON_CR0_ALWAYSON;
2917 case MSR_IA32_VMX_CR0_FIXED1:
2920 case MSR_IA32_VMX_CR4_FIXED0:
2921 *pdata = VMXON_CR4_ALWAYSON;
2923 case MSR_IA32_VMX_CR4_FIXED1:
2926 case MSR_IA32_VMX_VMCS_ENUM:
2927 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2929 case MSR_IA32_VMX_PROCBASED_CTLS2:
2930 *pdata = vmx_control_msr(
2931 vmx->nested.nested_vmx_secondary_ctls_low,
2932 vmx->nested.nested_vmx_secondary_ctls_high);
2934 case MSR_IA32_VMX_EPT_VPID_CAP:
2935 *pdata = vmx->nested.nested_vmx_ept_caps |
2936 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2945 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2948 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2950 return !(val & ~valid_bits);
2954 * Reads an msr value (of 'msr_index') into 'pdata'.
2955 * Returns 0 on success, non-0 otherwise.
2956 * Assumes vcpu_load() was already called.
2958 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2960 struct shared_msr_entry *msr;
2962 switch (msr_info->index) {
2963 #ifdef CONFIG_X86_64
2965 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2968 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2970 case MSR_KERNEL_GS_BASE:
2971 vmx_load_host_state(to_vmx(vcpu));
2972 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2976 return kvm_get_msr_common(vcpu, msr_info);
2978 msr_info->data = guest_read_tsc(vcpu);
2980 case MSR_IA32_SYSENTER_CS:
2981 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2983 case MSR_IA32_SYSENTER_EIP:
2984 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2986 case MSR_IA32_SYSENTER_ESP:
2987 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2989 case MSR_IA32_BNDCFGS:
2990 if (!kvm_mpx_supported())
2992 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2994 case MSR_IA32_MCG_EXT_CTL:
2995 if (!msr_info->host_initiated &&
2996 !(to_vmx(vcpu)->msr_ia32_feature_control &
2997 FEATURE_CONTROL_LMCE))
2999 msr_info->data = vcpu->arch.mcg_ext_ctl;
3001 case MSR_IA32_FEATURE_CONTROL:
3002 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3004 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3005 if (!nested_vmx_allowed(vcpu))
3007 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3009 if (!vmx_xsaves_supported())
3011 msr_info->data = vcpu->arch.ia32_xss;
3014 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3016 /* Otherwise falls through */
3018 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3020 msr_info->data = msr->data;
3023 return kvm_get_msr_common(vcpu, msr_info);
3029 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3032 * Writes msr value into into the appropriate "register".
3033 * Returns 0 on success, non-0 otherwise.
3034 * Assumes vcpu_load() was already called.
3036 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3038 struct vcpu_vmx *vmx = to_vmx(vcpu);
3039 struct shared_msr_entry *msr;
3041 u32 msr_index = msr_info->index;
3042 u64 data = msr_info->data;
3044 switch (msr_index) {
3046 ret = kvm_set_msr_common(vcpu, msr_info);
3048 #ifdef CONFIG_X86_64
3050 vmx_segment_cache_clear(vmx);
3051 vmcs_writel(GUEST_FS_BASE, data);
3054 vmx_segment_cache_clear(vmx);
3055 vmcs_writel(GUEST_GS_BASE, data);
3057 case MSR_KERNEL_GS_BASE:
3058 vmx_load_host_state(vmx);
3059 vmx->msr_guest_kernel_gs_base = data;
3062 case MSR_IA32_SYSENTER_CS:
3063 vmcs_write32(GUEST_SYSENTER_CS, data);
3065 case MSR_IA32_SYSENTER_EIP:
3066 vmcs_writel(GUEST_SYSENTER_EIP, data);
3068 case MSR_IA32_SYSENTER_ESP:
3069 vmcs_writel(GUEST_SYSENTER_ESP, data);
3071 case MSR_IA32_BNDCFGS:
3072 if (!kvm_mpx_supported())
3074 vmcs_write64(GUEST_BNDCFGS, data);
3077 kvm_write_tsc(vcpu, msr_info);
3079 case MSR_IA32_CR_PAT:
3080 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3081 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3083 vmcs_write64(GUEST_IA32_PAT, data);
3084 vcpu->arch.pat = data;
3087 ret = kvm_set_msr_common(vcpu, msr_info);
3089 case MSR_IA32_TSC_ADJUST:
3090 ret = kvm_set_msr_common(vcpu, msr_info);
3092 case MSR_IA32_MCG_EXT_CTL:
3093 if ((!msr_info->host_initiated &&
3094 !(to_vmx(vcpu)->msr_ia32_feature_control &
3095 FEATURE_CONTROL_LMCE)) ||
3096 (data & ~MCG_EXT_CTL_LMCE_EN))
3098 vcpu->arch.mcg_ext_ctl = data;
3100 case MSR_IA32_FEATURE_CONTROL:
3101 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3102 (to_vmx(vcpu)->msr_ia32_feature_control &
3103 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3105 vmx->msr_ia32_feature_control = data;
3106 if (msr_info->host_initiated && data == 0)
3107 vmx_leave_nested(vcpu);
3109 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3110 return 1; /* they are read-only */
3112 if (!vmx_xsaves_supported())
3115 * The only supported bit as of Skylake is bit 8, but
3116 * it is not supported on KVM.
3120 vcpu->arch.ia32_xss = data;
3121 if (vcpu->arch.ia32_xss != host_xss)
3122 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3123 vcpu->arch.ia32_xss, host_xss);
3125 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3128 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3130 /* Check reserved bit, higher 32 bits should be zero */
3131 if ((data >> 32) != 0)
3133 /* Otherwise falls through */
3135 msr = find_msr_entry(vmx, msr_index);
3137 u64 old_msr_data = msr->data;
3139 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3141 ret = kvm_set_shared_msr(msr->index, msr->data,
3145 msr->data = old_msr_data;
3149 ret = kvm_set_msr_common(vcpu, msr_info);
3155 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3157 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3160 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3163 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3165 case VCPU_EXREG_PDPTR:
3167 ept_save_pdptrs(vcpu);
3174 static __init int cpu_has_kvm_support(void)
3176 return cpu_has_vmx();
3179 static __init int vmx_disabled_by_bios(void)
3183 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3184 if (msr & FEATURE_CONTROL_LOCKED) {
3185 /* launched w/ TXT and VMX disabled */
3186 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3189 /* launched w/o TXT and VMX only enabled w/ TXT */
3190 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3191 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3192 && !tboot_enabled()) {
3193 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3194 "activate TXT before enabling KVM\n");
3197 /* launched w/o TXT and VMX disabled */
3198 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3199 && !tboot_enabled())
3206 static void kvm_cpu_vmxon(u64 addr)
3208 intel_pt_handle_vmx(1);
3210 asm volatile (ASM_VMX_VMXON_RAX
3211 : : "a"(&addr), "m"(addr)
3215 static int hardware_enable(void)
3217 int cpu = raw_smp_processor_id();
3218 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3221 if (cr4_read_shadow() & X86_CR4_VMXE)
3224 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3225 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3226 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3229 * Now we can enable the vmclear operation in kdump
3230 * since the loaded_vmcss_on_cpu list on this cpu
3231 * has been initialized.
3233 * Though the cpu is not in VMX operation now, there
3234 * is no problem to enable the vmclear operation
3235 * for the loaded_vmcss_on_cpu list is empty!
3237 crash_enable_local_vmclear(cpu);
3239 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3241 test_bits = FEATURE_CONTROL_LOCKED;
3242 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3243 if (tboot_enabled())
3244 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3246 if ((old & test_bits) != test_bits) {
3247 /* enable and lock */
3248 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3250 cr4_set_bits(X86_CR4_VMXE);
3252 if (vmm_exclusive) {
3253 kvm_cpu_vmxon(phys_addr);
3257 native_store_gdt(this_cpu_ptr(&host_gdt));
3262 static void vmclear_local_loaded_vmcss(void)
3264 int cpu = raw_smp_processor_id();
3265 struct loaded_vmcs *v, *n;
3267 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3268 loaded_vmcss_on_cpu_link)
3269 __loaded_vmcs_clear(v);
3273 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3276 static void kvm_cpu_vmxoff(void)
3278 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3280 intel_pt_handle_vmx(0);
3283 static void hardware_disable(void)
3285 if (vmm_exclusive) {
3286 vmclear_local_loaded_vmcss();
3289 cr4_clear_bits(X86_CR4_VMXE);
3292 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3293 u32 msr, u32 *result)
3295 u32 vmx_msr_low, vmx_msr_high;
3296 u32 ctl = ctl_min | ctl_opt;
3298 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3300 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3301 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3303 /* Ensure minimum (required) set of control bits are supported. */
3311 static __init bool allow_1_setting(u32 msr, u32 ctl)
3313 u32 vmx_msr_low, vmx_msr_high;
3315 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3316 return vmx_msr_high & ctl;
3319 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3321 u32 vmx_msr_low, vmx_msr_high;
3322 u32 min, opt, min2, opt2;
3323 u32 _pin_based_exec_control = 0;
3324 u32 _cpu_based_exec_control = 0;
3325 u32 _cpu_based_2nd_exec_control = 0;
3326 u32 _vmexit_control = 0;
3327 u32 _vmentry_control = 0;
3329 min = CPU_BASED_HLT_EXITING |
3330 #ifdef CONFIG_X86_64
3331 CPU_BASED_CR8_LOAD_EXITING |
3332 CPU_BASED_CR8_STORE_EXITING |
3334 CPU_BASED_CR3_LOAD_EXITING |
3335 CPU_BASED_CR3_STORE_EXITING |
3336 CPU_BASED_USE_IO_BITMAPS |
3337 CPU_BASED_MOV_DR_EXITING |
3338 CPU_BASED_USE_TSC_OFFSETING |
3339 CPU_BASED_MWAIT_EXITING |
3340 CPU_BASED_MONITOR_EXITING |
3341 CPU_BASED_INVLPG_EXITING |
3342 CPU_BASED_RDPMC_EXITING;
3344 opt = CPU_BASED_TPR_SHADOW |
3345 CPU_BASED_USE_MSR_BITMAPS |
3346 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3347 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3348 &_cpu_based_exec_control) < 0)
3350 #ifdef CONFIG_X86_64
3351 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3352 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3353 ~CPU_BASED_CR8_STORE_EXITING;
3355 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3357 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3358 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3359 SECONDARY_EXEC_WBINVD_EXITING |
3360 SECONDARY_EXEC_ENABLE_VPID |
3361 SECONDARY_EXEC_ENABLE_EPT |
3362 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3363 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3364 SECONDARY_EXEC_RDTSCP |
3365 SECONDARY_EXEC_ENABLE_INVPCID |
3366 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3367 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3368 SECONDARY_EXEC_SHADOW_VMCS |
3369 SECONDARY_EXEC_XSAVES |
3370 SECONDARY_EXEC_ENABLE_PML |
3371 SECONDARY_EXEC_TSC_SCALING;
3372 if (adjust_vmx_controls(min2, opt2,
3373 MSR_IA32_VMX_PROCBASED_CTLS2,
3374 &_cpu_based_2nd_exec_control) < 0)
3377 #ifndef CONFIG_X86_64
3378 if (!(_cpu_based_2nd_exec_control &
3379 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3380 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3383 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3384 _cpu_based_2nd_exec_control &= ~(
3385 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3386 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3387 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3389 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3390 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3392 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3393 CPU_BASED_CR3_STORE_EXITING |
3394 CPU_BASED_INVLPG_EXITING);
3395 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3396 vmx_capability.ept, vmx_capability.vpid);
3399 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3400 #ifdef CONFIG_X86_64
3401 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3403 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3404 VM_EXIT_CLEAR_BNDCFGS;
3405 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3406 &_vmexit_control) < 0)
3409 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3410 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3411 PIN_BASED_VMX_PREEMPTION_TIMER;
3412 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3413 &_pin_based_exec_control) < 0)
3416 if (cpu_has_broken_vmx_preemption_timer())
3417 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3418 if (!(_cpu_based_2nd_exec_control &
3419 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3420 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3422 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3423 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3424 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3425 &_vmentry_control) < 0)
3428 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3430 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3431 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3434 #ifdef CONFIG_X86_64
3435 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3436 if (vmx_msr_high & (1u<<16))
3440 /* Require Write-Back (WB) memory type for VMCS accesses. */
3441 if (((vmx_msr_high >> 18) & 15) != 6)
3444 vmcs_conf->size = vmx_msr_high & 0x1fff;
3445 vmcs_conf->order = get_order(vmcs_conf->size);
3446 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3447 vmcs_conf->revision_id = vmx_msr_low;
3449 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3450 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3451 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3452 vmcs_conf->vmexit_ctrl = _vmexit_control;
3453 vmcs_conf->vmentry_ctrl = _vmentry_control;
3455 cpu_has_load_ia32_efer =
3456 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3457 VM_ENTRY_LOAD_IA32_EFER)
3458 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3459 VM_EXIT_LOAD_IA32_EFER);
3461 cpu_has_load_perf_global_ctrl =
3462 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3463 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3464 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3465 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3468 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3469 * but due to errata below it can't be used. Workaround is to use
3470 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3472 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3477 * BC86,AAY89,BD102 (model 44)
3481 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3482 switch (boot_cpu_data.x86_model) {
3488 cpu_has_load_perf_global_ctrl = false;
3489 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3490 "does not work properly. Using workaround\n");
3497 if (boot_cpu_has(X86_FEATURE_XSAVES))
3498 rdmsrl(MSR_IA32_XSS, host_xss);
3503 static struct vmcs *alloc_vmcs_cpu(int cpu)
3505 int node = cpu_to_node(cpu);
3509 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3512 vmcs = page_address(pages);
3513 memset(vmcs, 0, vmcs_config.size);
3514 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3518 static struct vmcs *alloc_vmcs(void)
3520 return alloc_vmcs_cpu(raw_smp_processor_id());
3523 static void free_vmcs(struct vmcs *vmcs)
3525 free_pages((unsigned long)vmcs, vmcs_config.order);
3529 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3531 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3533 if (!loaded_vmcs->vmcs)
3535 loaded_vmcs_clear(loaded_vmcs);
3536 free_vmcs(loaded_vmcs->vmcs);
3537 loaded_vmcs->vmcs = NULL;
3538 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3541 static void free_kvm_area(void)
3545 for_each_possible_cpu(cpu) {
3546 free_vmcs(per_cpu(vmxarea, cpu));
3547 per_cpu(vmxarea, cpu) = NULL;
3551 static void init_vmcs_shadow_fields(void)
3555 /* No checks for read only fields yet */
3557 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3558 switch (shadow_read_write_fields[i]) {
3560 if (!kvm_mpx_supported())
3568 shadow_read_write_fields[j] =
3569 shadow_read_write_fields[i];
3572 max_shadow_read_write_fields = j;
3574 /* shadowed fields guest access without vmexit */
3575 for (i = 0; i < max_shadow_read_write_fields; i++) {
3576 clear_bit(shadow_read_write_fields[i],
3577 vmx_vmwrite_bitmap);
3578 clear_bit(shadow_read_write_fields[i],
3581 for (i = 0; i < max_shadow_read_only_fields; i++)
3582 clear_bit(shadow_read_only_fields[i],
3586 static __init int alloc_kvm_area(void)
3590 for_each_possible_cpu(cpu) {
3593 vmcs = alloc_vmcs_cpu(cpu);
3599 per_cpu(vmxarea, cpu) = vmcs;
3604 static bool emulation_required(struct kvm_vcpu *vcpu)
3606 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3609 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3610 struct kvm_segment *save)
3612 if (!emulate_invalid_guest_state) {
3614 * CS and SS RPL should be equal during guest entry according
3615 * to VMX spec, but in reality it is not always so. Since vcpu
3616 * is in the middle of the transition from real mode to
3617 * protected mode it is safe to assume that RPL 0 is a good
3620 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3621 save->selector &= ~SEGMENT_RPL_MASK;
3622 save->dpl = save->selector & SEGMENT_RPL_MASK;
3625 vmx_set_segment(vcpu, save, seg);
3628 static void enter_pmode(struct kvm_vcpu *vcpu)
3630 unsigned long flags;
3631 struct vcpu_vmx *vmx = to_vmx(vcpu);
3634 * Update real mode segment cache. It may be not up-to-date if sement
3635 * register was written while vcpu was in a guest mode.
3637 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3638 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3639 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3640 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3641 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3642 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3644 vmx->rmode.vm86_active = 0;
3646 vmx_segment_cache_clear(vmx);
3648 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3650 flags = vmcs_readl(GUEST_RFLAGS);
3651 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3652 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3653 vmcs_writel(GUEST_RFLAGS, flags);
3655 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3656 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3658 update_exception_bitmap(vcpu);
3660 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3661 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3662 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3663 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3664 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3665 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3668 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3670 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3671 struct kvm_segment var = *save;
3674 if (seg == VCPU_SREG_CS)
3677 if (!emulate_invalid_guest_state) {
3678 var.selector = var.base >> 4;
3679 var.base = var.base & 0xffff0;
3689 if (save->base & 0xf)
3690 printk_once(KERN_WARNING "kvm: segment base is not "
3691 "paragraph aligned when entering "
3692 "protected mode (seg=%d)", seg);
3695 vmcs_write16(sf->selector, var.selector);
3696 vmcs_write32(sf->base, var.base);
3697 vmcs_write32(sf->limit, var.limit);
3698 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3701 static void enter_rmode(struct kvm_vcpu *vcpu)
3703 unsigned long flags;
3704 struct vcpu_vmx *vmx = to_vmx(vcpu);
3706 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3707 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3708 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3709 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3710 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3711 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3712 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3714 vmx->rmode.vm86_active = 1;
3717 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3718 * vcpu. Warn the user that an update is overdue.
3720 if (!vcpu->kvm->arch.tss_addr)
3721 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3722 "called before entering vcpu\n");
3724 vmx_segment_cache_clear(vmx);
3726 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3727 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3728 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3730 flags = vmcs_readl(GUEST_RFLAGS);
3731 vmx->rmode.save_rflags = flags;
3733 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3735 vmcs_writel(GUEST_RFLAGS, flags);
3736 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3737 update_exception_bitmap(vcpu);
3739 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3740 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3741 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3742 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3743 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3744 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3746 kvm_mmu_reset_context(vcpu);
3749 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3751 struct vcpu_vmx *vmx = to_vmx(vcpu);
3752 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3758 * Force kernel_gs_base reloading before EFER changes, as control
3759 * of this msr depends on is_long_mode().
3761 vmx_load_host_state(to_vmx(vcpu));
3762 vcpu->arch.efer = efer;
3763 if (efer & EFER_LMA) {
3764 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3767 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3769 msr->data = efer & ~EFER_LME;
3774 #ifdef CONFIG_X86_64
3776 static void enter_lmode(struct kvm_vcpu *vcpu)
3780 vmx_segment_cache_clear(to_vmx(vcpu));
3782 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3783 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3784 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3786 vmcs_write32(GUEST_TR_AR_BYTES,
3787 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3788 | VMX_AR_TYPE_BUSY_64_TSS);
3790 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3793 static void exit_lmode(struct kvm_vcpu *vcpu)
3795 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3796 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3801 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3803 vpid_sync_context(vpid);
3805 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3807 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3811 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3813 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3816 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3818 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3820 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3821 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3824 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3826 if (enable_ept && is_paging(vcpu))
3827 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3828 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3831 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3833 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3835 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3836 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3839 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3841 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3843 if (!test_bit(VCPU_EXREG_PDPTR,
3844 (unsigned long *)&vcpu->arch.regs_dirty))
3847 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3848 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3849 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3850 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3851 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3855 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3857 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3859 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3860 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3861 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3862 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3863 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3866 __set_bit(VCPU_EXREG_PDPTR,
3867 (unsigned long *)&vcpu->arch.regs_avail);
3868 __set_bit(VCPU_EXREG_PDPTR,
3869 (unsigned long *)&vcpu->arch.regs_dirty);
3872 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3874 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3876 struct kvm_vcpu *vcpu)
3878 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3879 vmx_decache_cr3(vcpu);
3880 if (!(cr0 & X86_CR0_PG)) {
3881 /* From paging/starting to nonpaging */
3882 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3883 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3884 (CPU_BASED_CR3_LOAD_EXITING |
3885 CPU_BASED_CR3_STORE_EXITING));
3886 vcpu->arch.cr0 = cr0;
3887 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3888 } else if (!is_paging(vcpu)) {
3889 /* From nonpaging to paging */
3890 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3891 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3892 ~(CPU_BASED_CR3_LOAD_EXITING |
3893 CPU_BASED_CR3_STORE_EXITING));
3894 vcpu->arch.cr0 = cr0;
3895 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3898 if (!(cr0 & X86_CR0_WP))
3899 *hw_cr0 &= ~X86_CR0_WP;
3902 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3904 struct vcpu_vmx *vmx = to_vmx(vcpu);
3905 unsigned long hw_cr0;
3907 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3908 if (enable_unrestricted_guest)
3909 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3911 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3913 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3916 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3920 #ifdef CONFIG_X86_64
3921 if (vcpu->arch.efer & EFER_LME) {
3922 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3924 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3930 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3932 if (!vcpu->fpu_active)
3933 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3935 vmcs_writel(CR0_READ_SHADOW, cr0);
3936 vmcs_writel(GUEST_CR0, hw_cr0);
3937 vcpu->arch.cr0 = cr0;
3939 /* depends on vcpu->arch.cr0 to be set to a new value */
3940 vmx->emulation_required = emulation_required(vcpu);
3943 static u64 construct_eptp(unsigned long root_hpa)
3947 /* TODO write the value reading from MSR */
3948 eptp = VMX_EPT_DEFAULT_MT |
3949 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3950 if (enable_ept_ad_bits)
3951 eptp |= VMX_EPT_AD_ENABLE_BIT;
3952 eptp |= (root_hpa & PAGE_MASK);
3957 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3959 unsigned long guest_cr3;
3964 eptp = construct_eptp(cr3);
3965 vmcs_write64(EPT_POINTER, eptp);
3966 if (is_paging(vcpu) || is_guest_mode(vcpu))
3967 guest_cr3 = kvm_read_cr3(vcpu);
3969 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3970 ept_load_pdptrs(vcpu);
3973 vmx_flush_tlb(vcpu);
3974 vmcs_writel(GUEST_CR3, guest_cr3);
3977 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3980 * Pass through host's Machine Check Enable value to hw_cr4, which
3981 * is in force while we are in guest mode. Do not let guests control
3982 * this bit, even if host CR4.MCE == 0.
3984 unsigned long hw_cr4 =
3985 (cr4_read_shadow() & X86_CR4_MCE) |
3986 (cr4 & ~X86_CR4_MCE) |
3987 (to_vmx(vcpu)->rmode.vm86_active ?
3988 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3990 if (cr4 & X86_CR4_VMXE) {
3992 * To use VMXON (and later other VMX instructions), a guest
3993 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3994 * So basically the check on whether to allow nested VMX
3997 if (!nested_vmx_allowed(vcpu))
4000 if (to_vmx(vcpu)->nested.vmxon &&
4001 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
4004 vcpu->arch.cr4 = cr4;
4006 if (!is_paging(vcpu)) {
4007 hw_cr4 &= ~X86_CR4_PAE;
4008 hw_cr4 |= X86_CR4_PSE;
4009 } else if (!(cr4 & X86_CR4_PAE)) {
4010 hw_cr4 &= ~X86_CR4_PAE;
4014 if (!enable_unrestricted_guest && !is_paging(vcpu))
4016 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4017 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4018 * to be manually disabled when guest switches to non-paging
4021 * If !enable_unrestricted_guest, the CPU is always running
4022 * with CR0.PG=1 and CR4 needs to be modified.
4023 * If enable_unrestricted_guest, the CPU automatically
4024 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4026 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4028 vmcs_writel(CR4_READ_SHADOW, cr4);
4029 vmcs_writel(GUEST_CR4, hw_cr4);
4033 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4034 struct kvm_segment *var, int seg)
4036 struct vcpu_vmx *vmx = to_vmx(vcpu);
4039 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4040 *var = vmx->rmode.segs[seg];
4041 if (seg == VCPU_SREG_TR
4042 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4044 var->base = vmx_read_guest_seg_base(vmx, seg);
4045 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4048 var->base = vmx_read_guest_seg_base(vmx, seg);
4049 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4050 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4051 ar = vmx_read_guest_seg_ar(vmx, seg);
4052 var->unusable = (ar >> 16) & 1;
4053 var->type = ar & 15;
4054 var->s = (ar >> 4) & 1;
4055 var->dpl = (ar >> 5) & 3;
4057 * Some userspaces do not preserve unusable property. Since usable
4058 * segment has to be present according to VMX spec we can use present
4059 * property to amend userspace bug by making unusable segment always
4060 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4061 * segment as unusable.
4063 var->present = !var->unusable;
4064 var->avl = (ar >> 12) & 1;
4065 var->l = (ar >> 13) & 1;
4066 var->db = (ar >> 14) & 1;
4067 var->g = (ar >> 15) & 1;
4070 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4072 struct kvm_segment s;
4074 if (to_vmx(vcpu)->rmode.vm86_active) {
4075 vmx_get_segment(vcpu, &s, seg);
4078 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4081 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4083 struct vcpu_vmx *vmx = to_vmx(vcpu);
4085 if (unlikely(vmx->rmode.vm86_active))
4088 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4089 return VMX_AR_DPL(ar);
4093 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4097 if (var->unusable || !var->present)
4100 ar = var->type & 15;
4101 ar |= (var->s & 1) << 4;
4102 ar |= (var->dpl & 3) << 5;
4103 ar |= (var->present & 1) << 7;
4104 ar |= (var->avl & 1) << 12;
4105 ar |= (var->l & 1) << 13;
4106 ar |= (var->db & 1) << 14;
4107 ar |= (var->g & 1) << 15;
4113 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4114 struct kvm_segment *var, int seg)
4116 struct vcpu_vmx *vmx = to_vmx(vcpu);
4117 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4119 vmx_segment_cache_clear(vmx);
4121 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4122 vmx->rmode.segs[seg] = *var;
4123 if (seg == VCPU_SREG_TR)
4124 vmcs_write16(sf->selector, var->selector);
4126 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4130 vmcs_writel(sf->base, var->base);
4131 vmcs_write32(sf->limit, var->limit);
4132 vmcs_write16(sf->selector, var->selector);
4135 * Fix the "Accessed" bit in AR field of segment registers for older
4137 * IA32 arch specifies that at the time of processor reset the
4138 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4139 * is setting it to 0 in the userland code. This causes invalid guest
4140 * state vmexit when "unrestricted guest" mode is turned on.
4141 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4142 * tree. Newer qemu binaries with that qemu fix would not need this
4145 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4146 var->type |= 0x1; /* Accessed */
4148 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4151 vmx->emulation_required = emulation_required(vcpu);
4154 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4156 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4158 *db = (ar >> 14) & 1;
4159 *l = (ar >> 13) & 1;
4162 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4164 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4165 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4168 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4170 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4171 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4174 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4176 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4177 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4180 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4182 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4183 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4186 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4188 struct kvm_segment var;
4191 vmx_get_segment(vcpu, &var, seg);
4193 if (seg == VCPU_SREG_CS)
4195 ar = vmx_segment_access_rights(&var);
4197 if (var.base != (var.selector << 4))
4199 if (var.limit != 0xffff)
4207 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4209 struct kvm_segment cs;
4210 unsigned int cs_rpl;
4212 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4213 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4217 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4221 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4222 if (cs.dpl > cs_rpl)
4225 if (cs.dpl != cs_rpl)
4231 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4235 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4237 struct kvm_segment ss;
4238 unsigned int ss_rpl;
4240 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4241 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4245 if (ss.type != 3 && ss.type != 7)
4249 if (ss.dpl != ss_rpl) /* DPL != RPL */
4257 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4259 struct kvm_segment var;
4262 vmx_get_segment(vcpu, &var, seg);
4263 rpl = var.selector & SEGMENT_RPL_MASK;
4271 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4272 if (var.dpl < rpl) /* DPL < RPL */
4276 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4282 static bool tr_valid(struct kvm_vcpu *vcpu)
4284 struct kvm_segment tr;
4286 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4290 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4292 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4300 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4302 struct kvm_segment ldtr;
4304 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4308 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4318 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4320 struct kvm_segment cs, ss;
4322 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4323 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4325 return ((cs.selector & SEGMENT_RPL_MASK) ==
4326 (ss.selector & SEGMENT_RPL_MASK));
4330 * Check if guest state is valid. Returns true if valid, false if
4332 * We assume that registers are always usable
4334 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4336 if (enable_unrestricted_guest)
4339 /* real mode guest state checks */
4340 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4341 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4343 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4345 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4347 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4349 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4351 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4354 /* protected mode guest state checks */
4355 if (!cs_ss_rpl_check(vcpu))
4357 if (!code_segment_valid(vcpu))
4359 if (!stack_segment_valid(vcpu))
4361 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4363 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4365 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4367 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4369 if (!tr_valid(vcpu))
4371 if (!ldtr_valid(vcpu))
4375 * - Add checks on RIP
4376 * - Add checks on RFLAGS
4382 static int init_rmode_tss(struct kvm *kvm)
4388 idx = srcu_read_lock(&kvm->srcu);
4389 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4390 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4393 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4394 r = kvm_write_guest_page(kvm, fn++, &data,
4395 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4398 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4401 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4405 r = kvm_write_guest_page(kvm, fn, &data,
4406 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4409 srcu_read_unlock(&kvm->srcu, idx);
4413 static int init_rmode_identity_map(struct kvm *kvm)
4416 kvm_pfn_t identity_map_pfn;
4422 /* Protect kvm->arch.ept_identity_pagetable_done. */
4423 mutex_lock(&kvm->slots_lock);
4425 if (likely(kvm->arch.ept_identity_pagetable_done))
4428 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4430 r = alloc_identity_pagetable(kvm);
4434 idx = srcu_read_lock(&kvm->srcu);
4435 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4438 /* Set up identity-mapping pagetable for EPT in real mode */
4439 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4440 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4441 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4442 r = kvm_write_guest_page(kvm, identity_map_pfn,
4443 &tmp, i * sizeof(tmp), sizeof(tmp));
4447 kvm->arch.ept_identity_pagetable_done = true;
4450 srcu_read_unlock(&kvm->srcu, idx);
4453 mutex_unlock(&kvm->slots_lock);
4457 static void seg_setup(int seg)
4459 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4462 vmcs_write16(sf->selector, 0);
4463 vmcs_writel(sf->base, 0);
4464 vmcs_write32(sf->limit, 0xffff);
4466 if (seg == VCPU_SREG_CS)
4467 ar |= 0x08; /* code segment */
4469 vmcs_write32(sf->ar_bytes, ar);
4472 static int alloc_apic_access_page(struct kvm *kvm)
4477 mutex_lock(&kvm->slots_lock);
4478 if (kvm->arch.apic_access_page_done)
4480 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4481 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4485 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4486 if (is_error_page(page)) {
4492 * Do not pin the page in memory, so that memory hot-unplug
4493 * is able to migrate it.
4496 kvm->arch.apic_access_page_done = true;
4498 mutex_unlock(&kvm->slots_lock);
4502 static int alloc_identity_pagetable(struct kvm *kvm)
4504 /* Called with kvm->slots_lock held. */
4508 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4510 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4511 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4516 static int allocate_vpid(void)
4522 spin_lock(&vmx_vpid_lock);
4523 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4524 if (vpid < VMX_NR_VPIDS)
4525 __set_bit(vpid, vmx_vpid_bitmap);
4528 spin_unlock(&vmx_vpid_lock);
4532 static void free_vpid(int vpid)
4534 if (!enable_vpid || vpid == 0)
4536 spin_lock(&vmx_vpid_lock);
4537 __clear_bit(vpid, vmx_vpid_bitmap);
4538 spin_unlock(&vmx_vpid_lock);
4541 #define MSR_TYPE_R 1
4542 #define MSR_TYPE_W 2
4543 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4546 int f = sizeof(unsigned long);
4548 if (!cpu_has_vmx_msr_bitmap())
4552 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4553 * have the write-low and read-high bitmap offsets the wrong way round.
4554 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4556 if (msr <= 0x1fff) {
4557 if (type & MSR_TYPE_R)
4559 __clear_bit(msr, msr_bitmap + 0x000 / f);
4561 if (type & MSR_TYPE_W)
4563 __clear_bit(msr, msr_bitmap + 0x800 / f);
4565 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4567 if (type & MSR_TYPE_R)
4569 __clear_bit(msr, msr_bitmap + 0x400 / f);
4571 if (type & MSR_TYPE_W)
4573 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4579 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4580 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4582 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4583 unsigned long *msr_bitmap_nested,
4586 int f = sizeof(unsigned long);
4588 if (!cpu_has_vmx_msr_bitmap()) {
4594 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4595 * have the write-low and read-high bitmap offsets the wrong way round.
4596 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4598 if (msr <= 0x1fff) {
4599 if (type & MSR_TYPE_R &&
4600 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4602 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4604 if (type & MSR_TYPE_W &&
4605 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4607 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4609 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4611 if (type & MSR_TYPE_R &&
4612 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4614 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4616 if (type & MSR_TYPE_W &&
4617 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4619 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4624 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4627 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4628 msr, MSR_TYPE_R | MSR_TYPE_W);
4629 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4630 msr, MSR_TYPE_R | MSR_TYPE_W);
4633 static void vmx_disable_intercept_msr_read_x2apic(u32 msr, bool apicv_active)
4636 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4638 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4641 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4643 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4648 static void vmx_disable_intercept_msr_write_x2apic(u32 msr, bool apicv_active)
4651 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4653 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4656 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4658 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4663 static bool vmx_get_enable_apicv(void)
4665 return enable_apicv;
4668 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4670 struct vcpu_vmx *vmx = to_vmx(vcpu);
4675 if (vmx->nested.pi_desc &&
4676 vmx->nested.pi_pending) {
4677 vmx->nested.pi_pending = false;
4678 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4681 max_irr = find_last_bit(
4682 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4687 vapic_page = kmap(vmx->nested.virtual_apic_page);
4692 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4693 kunmap(vmx->nested.virtual_apic_page);
4695 status = vmcs_read16(GUEST_INTR_STATUS);
4696 if ((u8)max_irr > ((u8)status & 0xff)) {
4698 status |= (u8)max_irr;
4699 vmcs_write16(GUEST_INTR_STATUS, status);
4705 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4708 if (vcpu->mode == IN_GUEST_MODE) {
4709 struct vcpu_vmx *vmx = to_vmx(vcpu);
4712 * Currently, we don't support urgent interrupt,
4713 * all interrupts are recognized as non-urgent
4714 * interrupt, so we cannot post interrupts when
4717 * If the vcpu is in guest mode, it means it is
4718 * running instead of being scheduled out and
4719 * waiting in the run queue, and that's the only
4720 * case when 'SN' is set currently, warning if
4723 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4725 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4726 POSTED_INTR_VECTOR);
4733 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4736 struct vcpu_vmx *vmx = to_vmx(vcpu);
4738 if (is_guest_mode(vcpu) &&
4739 vector == vmx->nested.posted_intr_nv) {
4740 /* the PIR and ON have been set by L1. */
4741 kvm_vcpu_trigger_posted_interrupt(vcpu);
4743 * If a posted intr is not recognized by hardware,
4744 * we will accomplish it in the next vmentry.
4746 vmx->nested.pi_pending = true;
4747 kvm_make_request(KVM_REQ_EVENT, vcpu);
4753 * Send interrupt to vcpu via posted interrupt way.
4754 * 1. If target vcpu is running(non-root mode), send posted interrupt
4755 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4756 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4757 * interrupt from PIR in next vmentry.
4759 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4761 struct vcpu_vmx *vmx = to_vmx(vcpu);
4764 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4768 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4771 r = pi_test_and_set_on(&vmx->pi_desc);
4772 kvm_make_request(KVM_REQ_EVENT, vcpu);
4773 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4774 kvm_vcpu_kick(vcpu);
4777 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4779 struct vcpu_vmx *vmx = to_vmx(vcpu);
4781 if (!pi_test_and_clear_on(&vmx->pi_desc))
4784 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4788 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4789 * will not change in the lifetime of the guest.
4790 * Note that host-state that does change is set elsewhere. E.g., host-state
4791 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4793 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4800 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4801 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4803 /* Save the most likely value for this task's CR4 in the VMCS. */
4804 cr4 = cr4_read_shadow();
4805 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4806 vmx->host_state.vmcs_host_cr4 = cr4;
4808 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4809 #ifdef CONFIG_X86_64
4811 * Load null selectors, so we can avoid reloading them in
4812 * __vmx_load_host_state(), in case userspace uses the null selectors
4813 * too (the expected case).
4815 vmcs_write16(HOST_DS_SELECTOR, 0);
4816 vmcs_write16(HOST_ES_SELECTOR, 0);
4818 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4819 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4821 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4822 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4824 native_store_idt(&dt);
4825 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4826 vmx->host_idt_base = dt.address;
4828 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4830 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4831 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4832 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4833 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4835 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4836 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4837 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4841 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4843 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4845 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4846 if (is_guest_mode(&vmx->vcpu))
4847 vmx->vcpu.arch.cr4_guest_owned_bits &=
4848 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4849 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4852 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4854 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4856 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4857 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4858 /* Enable the preemption timer dynamically */
4859 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4860 return pin_based_exec_ctrl;
4863 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4865 struct vcpu_vmx *vmx = to_vmx(vcpu);
4867 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4868 if (cpu_has_secondary_exec_ctrls()) {
4869 if (kvm_vcpu_apicv_active(vcpu))
4870 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4871 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4872 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4874 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4875 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4876 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4879 if (cpu_has_vmx_msr_bitmap())
4880 vmx_set_msr_bitmap(vcpu);
4883 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4885 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4887 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4888 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4890 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4891 exec_control &= ~CPU_BASED_TPR_SHADOW;
4892 #ifdef CONFIG_X86_64
4893 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4894 CPU_BASED_CR8_LOAD_EXITING;
4898 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4899 CPU_BASED_CR3_LOAD_EXITING |
4900 CPU_BASED_INVLPG_EXITING;
4901 return exec_control;
4904 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4906 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4907 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4908 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4910 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4912 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4913 enable_unrestricted_guest = 0;
4914 /* Enable INVPCID for non-ept guests may cause performance regression. */
4915 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4917 if (!enable_unrestricted_guest)
4918 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4920 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4921 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4922 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4923 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4924 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4925 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4927 We can NOT enable shadow_vmcs here because we don't have yet
4930 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4933 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4935 return exec_control;
4938 static void ept_set_mmio_spte_mask(void)
4941 * EPT Misconfigurations can be generated if the value of bits 2:0
4942 * of an EPT paging-structure entry is 110b (write/execute).
4943 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4946 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4949 #define VMX_XSS_EXIT_BITMAP 0
4951 * Sets up the vmcs for emulated real mode.
4953 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4955 #ifdef CONFIG_X86_64
4961 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4962 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4964 if (enable_shadow_vmcs) {
4965 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4966 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4968 if (cpu_has_vmx_msr_bitmap())
4969 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4971 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4974 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4975 vmx->hv_deadline_tsc = -1;
4977 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4979 if (cpu_has_secondary_exec_ctrls()) {
4980 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4981 vmx_secondary_exec_control(vmx));
4984 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4985 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4986 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4987 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4988 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4990 vmcs_write16(GUEST_INTR_STATUS, 0);
4992 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4993 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4997 vmcs_write32(PLE_GAP, ple_gap);
4998 vmx->ple_window = ple_window;
4999 vmx->ple_window_dirty = true;
5002 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5003 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5004 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5006 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5007 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5008 vmx_set_constant_host_state(vmx);
5009 #ifdef CONFIG_X86_64
5010 rdmsrl(MSR_FS_BASE, a);
5011 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5012 rdmsrl(MSR_GS_BASE, a);
5013 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5015 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5016 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5019 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5020 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5021 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5022 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5023 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5025 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5026 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5028 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5029 u32 index = vmx_msr_index[i];
5030 u32 data_low, data_high;
5033 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5035 if (wrmsr_safe(index, data_low, data_high) < 0)
5037 vmx->guest_msrs[j].index = i;
5038 vmx->guest_msrs[j].data = 0;
5039 vmx->guest_msrs[j].mask = -1ull;
5044 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5046 /* 22.2.1, 20.8.1 */
5047 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5049 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5050 set_cr4_guest_host_mask(vmx);
5052 if (vmx_xsaves_supported())
5053 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5056 ASSERT(vmx->pml_pg);
5057 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5058 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5064 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5066 struct vcpu_vmx *vmx = to_vmx(vcpu);
5067 struct msr_data apic_base_msr;
5070 vmx->rmode.vm86_active = 0;
5072 vmx->soft_vnmi_blocked = 0;
5074 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5075 kvm_set_cr8(vcpu, 0);
5078 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5079 MSR_IA32_APICBASE_ENABLE;
5080 if (kvm_vcpu_is_reset_bsp(vcpu))
5081 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5082 apic_base_msr.host_initiated = true;
5083 kvm_set_apic_base(vcpu, &apic_base_msr);
5086 vmx_segment_cache_clear(vmx);
5088 seg_setup(VCPU_SREG_CS);
5089 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5090 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5092 seg_setup(VCPU_SREG_DS);
5093 seg_setup(VCPU_SREG_ES);
5094 seg_setup(VCPU_SREG_FS);
5095 seg_setup(VCPU_SREG_GS);
5096 seg_setup(VCPU_SREG_SS);
5098 vmcs_write16(GUEST_TR_SELECTOR, 0);
5099 vmcs_writel(GUEST_TR_BASE, 0);
5100 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5101 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5103 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5104 vmcs_writel(GUEST_LDTR_BASE, 0);
5105 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5106 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5109 vmcs_write32(GUEST_SYSENTER_CS, 0);
5110 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5111 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5112 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5115 vmcs_writel(GUEST_RFLAGS, 0x02);
5116 kvm_rip_write(vcpu, 0xfff0);
5118 vmcs_writel(GUEST_GDTR_BASE, 0);
5119 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5121 vmcs_writel(GUEST_IDTR_BASE, 0);
5122 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5124 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5125 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5126 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5130 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5132 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5133 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5134 if (cpu_need_tpr_shadow(vcpu))
5135 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5136 __pa(vcpu->arch.apic->regs));
5137 vmcs_write32(TPR_THRESHOLD, 0);
5140 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5142 if (kvm_vcpu_apicv_active(vcpu))
5143 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5146 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5148 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5149 vmx->vcpu.arch.cr0 = cr0;
5150 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5151 vmx_set_cr4(vcpu, 0);
5152 vmx_set_efer(vcpu, 0);
5153 vmx_fpu_activate(vcpu);
5154 update_exception_bitmap(vcpu);
5156 vpid_sync_context(vmx->vpid);
5160 * In nested virtualization, check if L1 asked to exit on external interrupts.
5161 * For most existing hypervisors, this will always return true.
5163 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5165 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5166 PIN_BASED_EXT_INTR_MASK;
5170 * In nested virtualization, check if L1 has set
5171 * VM_EXIT_ACK_INTR_ON_EXIT
5173 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5175 return get_vmcs12(vcpu)->vm_exit_controls &
5176 VM_EXIT_ACK_INTR_ON_EXIT;
5179 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5181 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5182 PIN_BASED_NMI_EXITING;
5185 static void enable_irq_window(struct kvm_vcpu *vcpu)
5187 u32 cpu_based_vm_exec_control;
5189 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5190 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5191 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5194 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5196 u32 cpu_based_vm_exec_control;
5198 if (!cpu_has_virtual_nmis() ||
5199 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5200 enable_irq_window(vcpu);
5204 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5205 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5206 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5209 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5211 struct vcpu_vmx *vmx = to_vmx(vcpu);
5213 int irq = vcpu->arch.interrupt.nr;
5215 trace_kvm_inj_virq(irq);
5217 ++vcpu->stat.irq_injections;
5218 if (vmx->rmode.vm86_active) {
5220 if (vcpu->arch.interrupt.soft)
5221 inc_eip = vcpu->arch.event_exit_inst_len;
5222 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5223 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5226 intr = irq | INTR_INFO_VALID_MASK;
5227 if (vcpu->arch.interrupt.soft) {
5228 intr |= INTR_TYPE_SOFT_INTR;
5229 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5230 vmx->vcpu.arch.event_exit_inst_len);
5232 intr |= INTR_TYPE_EXT_INTR;
5233 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5236 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5238 struct vcpu_vmx *vmx = to_vmx(vcpu);
5240 if (!is_guest_mode(vcpu)) {
5241 if (!cpu_has_virtual_nmis()) {
5243 * Tracking the NMI-blocked state in software is built upon
5244 * finding the next open IRQ window. This, in turn, depends on
5245 * well-behaving guests: They have to keep IRQs disabled at
5246 * least as long as the NMI handler runs. Otherwise we may
5247 * cause NMI nesting, maybe breaking the guest. But as this is
5248 * highly unlikely, we can live with the residual risk.
5250 vmx->soft_vnmi_blocked = 1;
5251 vmx->vnmi_blocked_time = 0;
5254 ++vcpu->stat.nmi_injections;
5255 vmx->nmi_known_unmasked = false;
5258 if (vmx->rmode.vm86_active) {
5259 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5260 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5264 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5265 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5268 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5270 if (!cpu_has_virtual_nmis())
5271 return to_vmx(vcpu)->soft_vnmi_blocked;
5272 if (to_vmx(vcpu)->nmi_known_unmasked)
5274 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5277 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5279 struct vcpu_vmx *vmx = to_vmx(vcpu);
5281 if (!cpu_has_virtual_nmis()) {
5282 if (vmx->soft_vnmi_blocked != masked) {
5283 vmx->soft_vnmi_blocked = masked;
5284 vmx->vnmi_blocked_time = 0;
5287 vmx->nmi_known_unmasked = !masked;
5289 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5290 GUEST_INTR_STATE_NMI);
5292 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5293 GUEST_INTR_STATE_NMI);
5297 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5299 if (to_vmx(vcpu)->nested.nested_run_pending)
5302 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5305 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5306 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5307 | GUEST_INTR_STATE_NMI));
5310 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5312 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5313 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5314 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5315 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5318 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5322 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5326 kvm->arch.tss_addr = addr;
5327 return init_rmode_tss(kvm);
5330 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5335 * Update instruction length as we may reinject the exception
5336 * from user space while in guest debugging mode.
5338 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5339 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5340 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5344 if (vcpu->guest_debug &
5345 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5362 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5363 int vec, u32 err_code)
5366 * Instruction with address size override prefix opcode 0x67
5367 * Cause the #SS fault with 0 error code in VM86 mode.
5369 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5370 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5371 if (vcpu->arch.halt_request) {
5372 vcpu->arch.halt_request = 0;
5373 return kvm_vcpu_halt(vcpu);
5381 * Forward all other exceptions that are valid in real mode.
5382 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5383 * the required debugging infrastructure rework.
5385 kvm_queue_exception(vcpu, vec);
5390 * Trigger machine check on the host. We assume all the MSRs are already set up
5391 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5392 * We pass a fake environment to the machine check handler because we want
5393 * the guest to be always treated like user space, no matter what context
5394 * it used internally.
5396 static void kvm_machine_check(void)
5398 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5399 struct pt_regs regs = {
5400 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5401 .flags = X86_EFLAGS_IF,
5404 do_machine_check(®s, 0);
5408 static int handle_machine_check(struct kvm_vcpu *vcpu)
5410 /* already handled by vcpu_run */
5414 static int handle_exception(struct kvm_vcpu *vcpu)
5416 struct vcpu_vmx *vmx = to_vmx(vcpu);
5417 struct kvm_run *kvm_run = vcpu->run;
5418 u32 intr_info, ex_no, error_code;
5419 unsigned long cr2, rip, dr6;
5421 enum emulation_result er;
5423 vect_info = vmx->idt_vectoring_info;
5424 intr_info = vmx->exit_intr_info;
5426 if (is_machine_check(intr_info))
5427 return handle_machine_check(vcpu);
5429 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5430 return 1; /* already handled by vmx_vcpu_run() */
5432 if (is_no_device(intr_info)) {
5433 vmx_fpu_activate(vcpu);
5437 if (is_invalid_opcode(intr_info)) {
5438 if (is_guest_mode(vcpu)) {
5439 kvm_queue_exception(vcpu, UD_VECTOR);
5442 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5443 if (er != EMULATE_DONE)
5444 kvm_queue_exception(vcpu, UD_VECTOR);
5449 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5450 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5453 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5454 * MMIO, it is better to report an internal error.
5455 * See the comments in vmx_handle_exit.
5457 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5458 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5459 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5460 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5461 vcpu->run->internal.ndata = 3;
5462 vcpu->run->internal.data[0] = vect_info;
5463 vcpu->run->internal.data[1] = intr_info;
5464 vcpu->run->internal.data[2] = error_code;
5468 if (is_page_fault(intr_info)) {
5469 /* EPT won't cause page fault directly */
5471 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5472 trace_kvm_page_fault(cr2, error_code);
5474 if (kvm_event_needs_reinjection(vcpu))
5475 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5476 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5479 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5481 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5482 return handle_rmode_exception(vcpu, ex_no, error_code);
5486 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5489 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5490 if (!(vcpu->guest_debug &
5491 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5492 vcpu->arch.dr6 &= ~15;
5493 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5494 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5495 skip_emulated_instruction(vcpu);
5497 kvm_queue_exception(vcpu, DB_VECTOR);
5500 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5501 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5505 * Update instruction length as we may reinject #BP from
5506 * user space while in guest debugging mode. Reading it for
5507 * #DB as well causes no harm, it is not used in that case.
5509 vmx->vcpu.arch.event_exit_inst_len =
5510 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5511 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5512 rip = kvm_rip_read(vcpu);
5513 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5514 kvm_run->debug.arch.exception = ex_no;
5517 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5518 kvm_run->ex.exception = ex_no;
5519 kvm_run->ex.error_code = error_code;
5525 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5527 ++vcpu->stat.irq_exits;
5531 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5533 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5537 static int handle_io(struct kvm_vcpu *vcpu)
5539 unsigned long exit_qualification;
5540 int size, in, string;
5543 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5544 string = (exit_qualification & 16) != 0;
5545 in = (exit_qualification & 8) != 0;
5547 ++vcpu->stat.io_exits;
5550 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5552 port = exit_qualification >> 16;
5553 size = (exit_qualification & 7) + 1;
5554 skip_emulated_instruction(vcpu);
5556 return kvm_fast_pio_out(vcpu, size, port);
5560 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5563 * Patch in the VMCALL instruction:
5565 hypercall[0] = 0x0f;
5566 hypercall[1] = 0x01;
5567 hypercall[2] = 0xc1;
5570 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5572 unsigned long always_on = VMXON_CR0_ALWAYSON;
5573 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5575 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5576 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5577 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5578 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5579 return (val & always_on) == always_on;
5582 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5583 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5585 if (is_guest_mode(vcpu)) {
5586 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5587 unsigned long orig_val = val;
5590 * We get here when L2 changed cr0 in a way that did not change
5591 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5592 * but did change L0 shadowed bits. So we first calculate the
5593 * effective cr0 value that L1 would like to write into the
5594 * hardware. It consists of the L2-owned bits from the new
5595 * value combined with the L1-owned bits from L1's guest_cr0.
5597 val = (val & ~vmcs12->cr0_guest_host_mask) |
5598 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5600 if (!nested_cr0_valid(vcpu, val))
5603 if (kvm_set_cr0(vcpu, val))
5605 vmcs_writel(CR0_READ_SHADOW, orig_val);
5608 if (to_vmx(vcpu)->nested.vmxon &&
5609 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5611 return kvm_set_cr0(vcpu, val);
5615 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5617 if (is_guest_mode(vcpu)) {
5618 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5619 unsigned long orig_val = val;
5621 /* analogously to handle_set_cr0 */
5622 val = (val & ~vmcs12->cr4_guest_host_mask) |
5623 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5624 if (kvm_set_cr4(vcpu, val))
5626 vmcs_writel(CR4_READ_SHADOW, orig_val);
5629 return kvm_set_cr4(vcpu, val);
5632 /* called to set cr0 as appropriate for clts instruction exit. */
5633 static void handle_clts(struct kvm_vcpu *vcpu)
5635 if (is_guest_mode(vcpu)) {
5637 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5638 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5639 * just pretend it's off (also in arch.cr0 for fpu_activate).
5641 vmcs_writel(CR0_READ_SHADOW,
5642 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5643 vcpu->arch.cr0 &= ~X86_CR0_TS;
5645 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5648 static int handle_cr(struct kvm_vcpu *vcpu)
5650 unsigned long exit_qualification, val;
5655 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5656 cr = exit_qualification & 15;
5657 reg = (exit_qualification >> 8) & 15;
5658 switch ((exit_qualification >> 4) & 3) {
5659 case 0: /* mov to cr */
5660 val = kvm_register_readl(vcpu, reg);
5661 trace_kvm_cr_write(cr, val);
5664 err = handle_set_cr0(vcpu, val);
5665 kvm_complete_insn_gp(vcpu, err);
5668 err = kvm_set_cr3(vcpu, val);
5669 kvm_complete_insn_gp(vcpu, err);
5672 err = handle_set_cr4(vcpu, val);
5673 kvm_complete_insn_gp(vcpu, err);
5676 u8 cr8_prev = kvm_get_cr8(vcpu);
5678 err = kvm_set_cr8(vcpu, cr8);
5679 kvm_complete_insn_gp(vcpu, err);
5680 if (lapic_in_kernel(vcpu))
5682 if (cr8_prev <= cr8)
5684 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5691 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5692 skip_emulated_instruction(vcpu);
5693 vmx_fpu_activate(vcpu);
5695 case 1: /*mov from cr*/
5698 val = kvm_read_cr3(vcpu);
5699 kvm_register_write(vcpu, reg, val);
5700 trace_kvm_cr_read(cr, val);
5701 skip_emulated_instruction(vcpu);
5704 val = kvm_get_cr8(vcpu);
5705 kvm_register_write(vcpu, reg, val);
5706 trace_kvm_cr_read(cr, val);
5707 skip_emulated_instruction(vcpu);
5712 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5713 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5714 kvm_lmsw(vcpu, val);
5716 skip_emulated_instruction(vcpu);
5721 vcpu->run->exit_reason = 0;
5722 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5723 (int)(exit_qualification >> 4) & 3, cr);
5727 static int handle_dr(struct kvm_vcpu *vcpu)
5729 unsigned long exit_qualification;
5732 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5733 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5735 /* First, if DR does not exist, trigger UD */
5736 if (!kvm_require_dr(vcpu, dr))
5739 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5740 if (!kvm_require_cpl(vcpu, 0))
5742 dr7 = vmcs_readl(GUEST_DR7);
5745 * As the vm-exit takes precedence over the debug trap, we
5746 * need to emulate the latter, either for the host or the
5747 * guest debugging itself.
5749 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5750 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5751 vcpu->run->debug.arch.dr7 = dr7;
5752 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5753 vcpu->run->debug.arch.exception = DB_VECTOR;
5754 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5757 vcpu->arch.dr6 &= ~15;
5758 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5759 kvm_queue_exception(vcpu, DB_VECTOR);
5764 if (vcpu->guest_debug == 0) {
5765 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5766 CPU_BASED_MOV_DR_EXITING);
5769 * No more DR vmexits; force a reload of the debug registers
5770 * and reenter on this instruction. The next vmexit will
5771 * retrieve the full state of the debug registers.
5773 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5777 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5778 if (exit_qualification & TYPE_MOV_FROM_DR) {
5781 if (kvm_get_dr(vcpu, dr, &val))
5783 kvm_register_write(vcpu, reg, val);
5785 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5788 skip_emulated_instruction(vcpu);
5792 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5794 return vcpu->arch.dr6;
5797 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5801 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5803 get_debugreg(vcpu->arch.db[0], 0);
5804 get_debugreg(vcpu->arch.db[1], 1);
5805 get_debugreg(vcpu->arch.db[2], 2);
5806 get_debugreg(vcpu->arch.db[3], 3);
5807 get_debugreg(vcpu->arch.dr6, 6);
5808 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5810 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5811 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5814 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5816 vmcs_writel(GUEST_DR7, val);
5819 static int handle_cpuid(struct kvm_vcpu *vcpu)
5821 kvm_emulate_cpuid(vcpu);
5825 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5827 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5828 struct msr_data msr_info;
5830 msr_info.index = ecx;
5831 msr_info.host_initiated = false;
5832 if (vmx_get_msr(vcpu, &msr_info)) {
5833 trace_kvm_msr_read_ex(ecx);
5834 kvm_inject_gp(vcpu, 0);
5838 trace_kvm_msr_read(ecx, msr_info.data);
5840 /* FIXME: handling of bits 32:63 of rax, rdx */
5841 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5842 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5843 skip_emulated_instruction(vcpu);
5847 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5849 struct msr_data msr;
5850 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5851 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5852 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5856 msr.host_initiated = false;
5857 if (kvm_set_msr(vcpu, &msr) != 0) {
5858 trace_kvm_msr_write_ex(ecx, data);
5859 kvm_inject_gp(vcpu, 0);
5863 trace_kvm_msr_write(ecx, data);
5864 skip_emulated_instruction(vcpu);
5868 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5870 kvm_make_request(KVM_REQ_EVENT, vcpu);
5874 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5876 u32 cpu_based_vm_exec_control;
5878 /* clear pending irq */
5879 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5880 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5881 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5883 kvm_make_request(KVM_REQ_EVENT, vcpu);
5885 ++vcpu->stat.irq_window_exits;
5889 static int handle_halt(struct kvm_vcpu *vcpu)
5891 return kvm_emulate_halt(vcpu);
5894 static int handle_vmcall(struct kvm_vcpu *vcpu)
5896 return kvm_emulate_hypercall(vcpu);
5899 static int handle_invd(struct kvm_vcpu *vcpu)
5901 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5904 static int handle_invlpg(struct kvm_vcpu *vcpu)
5906 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5908 kvm_mmu_invlpg(vcpu, exit_qualification);
5909 skip_emulated_instruction(vcpu);
5913 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5917 err = kvm_rdpmc(vcpu);
5918 kvm_complete_insn_gp(vcpu, err);
5923 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5925 kvm_emulate_wbinvd(vcpu);
5929 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5931 u64 new_bv = kvm_read_edx_eax(vcpu);
5932 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5934 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5935 skip_emulated_instruction(vcpu);
5939 static int handle_xsaves(struct kvm_vcpu *vcpu)
5941 skip_emulated_instruction(vcpu);
5942 WARN(1, "this should never happen\n");
5946 static int handle_xrstors(struct kvm_vcpu *vcpu)
5948 skip_emulated_instruction(vcpu);
5949 WARN(1, "this should never happen\n");
5953 static int handle_apic_access(struct kvm_vcpu *vcpu)
5955 if (likely(fasteoi)) {
5956 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5957 int access_type, offset;
5959 access_type = exit_qualification & APIC_ACCESS_TYPE;
5960 offset = exit_qualification & APIC_ACCESS_OFFSET;
5962 * Sane guest uses MOV to write EOI, with written value
5963 * not cared. So make a short-circuit here by avoiding
5964 * heavy instruction emulation.
5966 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5967 (offset == APIC_EOI)) {
5968 kvm_lapic_set_eoi(vcpu);
5969 skip_emulated_instruction(vcpu);
5973 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5976 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5978 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5979 int vector = exit_qualification & 0xff;
5981 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5982 kvm_apic_set_eoi_accelerated(vcpu, vector);
5986 static int handle_apic_write(struct kvm_vcpu *vcpu)
5988 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5989 u32 offset = exit_qualification & 0xfff;
5991 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5992 kvm_apic_write_nodecode(vcpu, offset);
5996 static int handle_task_switch(struct kvm_vcpu *vcpu)
5998 struct vcpu_vmx *vmx = to_vmx(vcpu);
5999 unsigned long exit_qualification;
6000 bool has_error_code = false;
6003 int reason, type, idt_v, idt_index;
6005 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6006 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6007 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6009 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6011 reason = (u32)exit_qualification >> 30;
6012 if (reason == TASK_SWITCH_GATE && idt_v) {
6014 case INTR_TYPE_NMI_INTR:
6015 vcpu->arch.nmi_injected = false;
6016 vmx_set_nmi_mask(vcpu, true);
6018 case INTR_TYPE_EXT_INTR:
6019 case INTR_TYPE_SOFT_INTR:
6020 kvm_clear_interrupt_queue(vcpu);
6022 case INTR_TYPE_HARD_EXCEPTION:
6023 if (vmx->idt_vectoring_info &
6024 VECTORING_INFO_DELIVER_CODE_MASK) {
6025 has_error_code = true;
6027 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6030 case INTR_TYPE_SOFT_EXCEPTION:
6031 kvm_clear_exception_queue(vcpu);
6037 tss_selector = exit_qualification;
6039 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6040 type != INTR_TYPE_EXT_INTR &&
6041 type != INTR_TYPE_NMI_INTR))
6042 skip_emulated_instruction(vcpu);
6044 if (kvm_task_switch(vcpu, tss_selector,
6045 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6046 has_error_code, error_code) == EMULATE_FAIL) {
6047 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6048 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6049 vcpu->run->internal.ndata = 0;
6054 * TODO: What about debug traps on tss switch?
6055 * Are we supposed to inject them and update dr6?
6061 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6063 unsigned long exit_qualification;
6068 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6070 gla_validity = (exit_qualification >> 7) & 0x3;
6071 if (gla_validity == 0x2) {
6072 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6073 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6074 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6075 vmcs_readl(GUEST_LINEAR_ADDRESS));
6076 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6077 (long unsigned int)exit_qualification);
6078 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6079 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6084 * EPT violation happened while executing iret from NMI,
6085 * "blocked by NMI" bit has to be set before next VM entry.
6086 * There are errata that may cause this bit to not be set:
6089 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6090 cpu_has_virtual_nmis() &&
6091 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6092 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6094 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6095 trace_kvm_page_fault(gpa, exit_qualification);
6097 /* it is a read fault? */
6098 error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6099 /* it is a write fault? */
6100 error_code |= exit_qualification & PFERR_WRITE_MASK;
6101 /* It is a fetch fault? */
6102 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6103 /* ept page table is present? */
6104 error_code |= (exit_qualification & 0x38) != 0;
6106 vcpu->arch.exit_qualification = exit_qualification;
6108 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6111 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6116 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6117 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6118 skip_emulated_instruction(vcpu);
6119 trace_kvm_fast_mmio(gpa);
6123 ret = handle_mmio_page_fault(vcpu, gpa, true);
6124 if (likely(ret == RET_MMIO_PF_EMULATE))
6125 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6128 if (unlikely(ret == RET_MMIO_PF_INVALID))
6129 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6131 if (unlikely(ret == RET_MMIO_PF_RETRY))
6134 /* It is the real ept misconfig */
6137 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6138 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6143 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6145 u32 cpu_based_vm_exec_control;
6147 /* clear pending NMI */
6148 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6149 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6150 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6151 ++vcpu->stat.nmi_window_exits;
6152 kvm_make_request(KVM_REQ_EVENT, vcpu);
6157 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6159 struct vcpu_vmx *vmx = to_vmx(vcpu);
6160 enum emulation_result err = EMULATE_DONE;
6163 bool intr_window_requested;
6164 unsigned count = 130;
6166 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6167 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6169 while (vmx->emulation_required && count-- != 0) {
6170 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6171 return handle_interrupt_window(&vmx->vcpu);
6173 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6176 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6178 if (err == EMULATE_USER_EXIT) {
6179 ++vcpu->stat.mmio_exits;
6184 if (err != EMULATE_DONE) {
6185 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6186 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6187 vcpu->run->internal.ndata = 0;
6191 if (vcpu->arch.halt_request) {
6192 vcpu->arch.halt_request = 0;
6193 ret = kvm_vcpu_halt(vcpu);
6197 if (signal_pending(current))
6207 static int __grow_ple_window(int val)
6209 if (ple_window_grow < 1)
6212 val = min(val, ple_window_actual_max);
6214 if (ple_window_grow < ple_window)
6215 val *= ple_window_grow;
6217 val += ple_window_grow;
6222 static int __shrink_ple_window(int val, int modifier, int minimum)
6227 if (modifier < ple_window)
6232 return max(val, minimum);
6235 static void grow_ple_window(struct kvm_vcpu *vcpu)
6237 struct vcpu_vmx *vmx = to_vmx(vcpu);
6238 int old = vmx->ple_window;
6240 vmx->ple_window = __grow_ple_window(old);
6242 if (vmx->ple_window != old)
6243 vmx->ple_window_dirty = true;
6245 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6248 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6250 struct vcpu_vmx *vmx = to_vmx(vcpu);
6251 int old = vmx->ple_window;
6253 vmx->ple_window = __shrink_ple_window(old,
6254 ple_window_shrink, ple_window);
6256 if (vmx->ple_window != old)
6257 vmx->ple_window_dirty = true;
6259 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6263 * ple_window_actual_max is computed to be one grow_ple_window() below
6264 * ple_window_max. (See __grow_ple_window for the reason.)
6265 * This prevents overflows, because ple_window_max is int.
6266 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6268 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6270 static void update_ple_window_actual_max(void)
6272 ple_window_actual_max =
6273 __shrink_ple_window(max(ple_window_max, ple_window),
6274 ple_window_grow, INT_MIN);
6278 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6280 static void wakeup_handler(void)
6282 struct kvm_vcpu *vcpu;
6283 int cpu = smp_processor_id();
6285 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6286 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6287 blocked_vcpu_list) {
6288 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6290 if (pi_test_on(pi_desc) == 1)
6291 kvm_vcpu_kick(vcpu);
6293 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6296 static __init int hardware_setup(void)
6298 int r = -ENOMEM, i, msr;
6300 rdmsrl_safe(MSR_EFER, &host_efer);
6302 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6303 kvm_define_shared_msr(i, vmx_msr_index[i]);
6305 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6306 if (!vmx_io_bitmap_a)
6309 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6310 if (!vmx_io_bitmap_b)
6313 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6314 if (!vmx_msr_bitmap_legacy)
6317 vmx_msr_bitmap_legacy_x2apic_apicv =
6318 (unsigned long *)__get_free_page(GFP_KERNEL);
6319 if (!vmx_msr_bitmap_legacy_x2apic_apicv)
6322 vmx_msr_bitmap_legacy_x2apic =
6323 (unsigned long *)__get_free_page(GFP_KERNEL);
6324 if (!vmx_msr_bitmap_legacy_x2apic)
6327 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6328 if (!vmx_msr_bitmap_longmode)
6331 vmx_msr_bitmap_longmode_x2apic_apicv =
6332 (unsigned long *)__get_free_page(GFP_KERNEL);
6333 if (!vmx_msr_bitmap_longmode_x2apic_apicv)
6336 vmx_msr_bitmap_longmode_x2apic =
6337 (unsigned long *)__get_free_page(GFP_KERNEL);
6338 if (!vmx_msr_bitmap_longmode_x2apic)
6341 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6342 if (!vmx_vmread_bitmap)
6345 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6346 if (!vmx_vmwrite_bitmap)
6349 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6350 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6353 * Allow direct access to the PC debug port (it is often used for I/O
6354 * delays, but the vmexits simply slow things down).
6356 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6357 clear_bit(0x80, vmx_io_bitmap_a);
6359 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6361 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6362 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6364 if (setup_vmcs_config(&vmcs_config) < 0) {
6369 if (boot_cpu_has(X86_FEATURE_NX))
6370 kvm_enable_efer_bits(EFER_NX);
6372 if (!cpu_has_vmx_vpid())
6374 if (!cpu_has_vmx_shadow_vmcs())
6375 enable_shadow_vmcs = 0;
6376 if (enable_shadow_vmcs)
6377 init_vmcs_shadow_fields();
6379 if (!cpu_has_vmx_ept() ||
6380 !cpu_has_vmx_ept_4levels()) {
6382 enable_unrestricted_guest = 0;
6383 enable_ept_ad_bits = 0;
6386 if (!cpu_has_vmx_ept_ad_bits())
6387 enable_ept_ad_bits = 0;
6389 if (!cpu_has_vmx_unrestricted_guest())
6390 enable_unrestricted_guest = 0;
6392 if (!cpu_has_vmx_flexpriority())
6393 flexpriority_enabled = 0;
6396 * set_apic_access_page_addr() is used to reload apic access
6397 * page upon invalidation. No need to do anything if not
6398 * using the APIC_ACCESS_ADDR VMCS field.
6400 if (!flexpriority_enabled)
6401 kvm_x86_ops->set_apic_access_page_addr = NULL;
6403 if (!cpu_has_vmx_tpr_shadow())
6404 kvm_x86_ops->update_cr8_intercept = NULL;
6406 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6407 kvm_disable_largepages();
6409 if (!cpu_has_vmx_ple())
6412 if (!cpu_has_vmx_apicv())
6415 if (cpu_has_vmx_tsc_scaling()) {
6416 kvm_has_tsc_control = true;
6417 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6418 kvm_tsc_scaling_ratio_frac_bits = 48;
6421 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6422 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6423 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6424 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6425 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6426 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6427 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6429 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6430 vmx_msr_bitmap_legacy, PAGE_SIZE);
6431 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6432 vmx_msr_bitmap_longmode, PAGE_SIZE);
6433 memcpy(vmx_msr_bitmap_legacy_x2apic,
6434 vmx_msr_bitmap_legacy, PAGE_SIZE);
6435 memcpy(vmx_msr_bitmap_longmode_x2apic,
6436 vmx_msr_bitmap_longmode, PAGE_SIZE);
6438 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6441 * enable_apicv && kvm_vcpu_apicv_active()
6443 for (msr = 0x800; msr <= 0x8ff; msr++) {
6444 if (msr == 0x839 /* TMCCT */)
6446 vmx_disable_intercept_msr_read_x2apic(msr, true);
6450 vmx_disable_intercept_msr_write_x2apic(0x808, true);
6452 vmx_disable_intercept_msr_write_x2apic(0x80b, true);
6454 vmx_disable_intercept_msr_write_x2apic(0x83f, true);
6457 * (enable_apicv && !kvm_vcpu_apicv_active()) ||
6461 vmx_disable_intercept_msr_read_x2apic(0x808, false);
6462 vmx_disable_intercept_msr_write_x2apic(0x808, false);
6465 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6466 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6467 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6468 0ull, VMX_EPT_EXECUTABLE_MASK,
6469 cpu_has_vmx_ept_execute_only() ?
6470 0ull : VMX_EPT_READABLE_MASK);
6471 ept_set_mmio_spte_mask();
6476 update_ple_window_actual_max();
6479 * Only enable PML when hardware supports PML feature, and both EPT
6480 * and EPT A/D bit features are enabled -- PML depends on them to work.
6482 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6486 kvm_x86_ops->slot_enable_log_dirty = NULL;
6487 kvm_x86_ops->slot_disable_log_dirty = NULL;
6488 kvm_x86_ops->flush_log_dirty = NULL;
6489 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6492 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6495 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6496 cpu_preemption_timer_multi =
6497 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6499 kvm_x86_ops->set_hv_timer = NULL;
6500 kvm_x86_ops->cancel_hv_timer = NULL;
6503 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6505 kvm_mce_cap_supported |= MCG_LMCE_P;
6507 return alloc_kvm_area();
6510 free_page((unsigned long)vmx_vmwrite_bitmap);
6512 free_page((unsigned long)vmx_vmread_bitmap);
6514 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6516 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic_apicv);
6518 free_page((unsigned long)vmx_msr_bitmap_longmode);
6520 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6522 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic_apicv);
6524 free_page((unsigned long)vmx_msr_bitmap_legacy);
6526 free_page((unsigned long)vmx_io_bitmap_b);
6528 free_page((unsigned long)vmx_io_bitmap_a);
6533 static __exit void hardware_unsetup(void)
6535 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic_apicv);
6536 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6537 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic_apicv);
6538 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6539 free_page((unsigned long)vmx_msr_bitmap_legacy);
6540 free_page((unsigned long)vmx_msr_bitmap_longmode);
6541 free_page((unsigned long)vmx_io_bitmap_b);
6542 free_page((unsigned long)vmx_io_bitmap_a);
6543 free_page((unsigned long)vmx_vmwrite_bitmap);
6544 free_page((unsigned long)vmx_vmread_bitmap);
6550 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6551 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6553 static int handle_pause(struct kvm_vcpu *vcpu)
6556 grow_ple_window(vcpu);
6558 skip_emulated_instruction(vcpu);
6559 kvm_vcpu_on_spin(vcpu);
6564 static int handle_nop(struct kvm_vcpu *vcpu)
6566 skip_emulated_instruction(vcpu);
6570 static int handle_mwait(struct kvm_vcpu *vcpu)
6572 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6573 return handle_nop(vcpu);
6576 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6581 static int handle_monitor(struct kvm_vcpu *vcpu)
6583 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6584 return handle_nop(vcpu);
6588 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6589 * We could reuse a single VMCS for all the L2 guests, but we also want the
6590 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6591 * allows keeping them loaded on the processor, and in the future will allow
6592 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6593 * every entry if they never change.
6594 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6595 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6597 * The following functions allocate and free a vmcs02 in this pool.
6600 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6601 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6603 struct vmcs02_list *item;
6604 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6605 if (item->vmptr == vmx->nested.current_vmptr) {
6606 list_move(&item->list, &vmx->nested.vmcs02_pool);
6607 return &item->vmcs02;
6610 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6611 /* Recycle the least recently used VMCS. */
6612 item = list_last_entry(&vmx->nested.vmcs02_pool,
6613 struct vmcs02_list, list);
6614 item->vmptr = vmx->nested.current_vmptr;
6615 list_move(&item->list, &vmx->nested.vmcs02_pool);
6616 return &item->vmcs02;
6619 /* Create a new VMCS */
6620 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6623 item->vmcs02.vmcs = alloc_vmcs();
6624 item->vmcs02.shadow_vmcs = NULL;
6625 if (!item->vmcs02.vmcs) {
6629 loaded_vmcs_init(&item->vmcs02);
6630 item->vmptr = vmx->nested.current_vmptr;
6631 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6632 vmx->nested.vmcs02_num++;
6633 return &item->vmcs02;
6636 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6637 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6639 struct vmcs02_list *item;
6640 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6641 if (item->vmptr == vmptr) {
6642 free_loaded_vmcs(&item->vmcs02);
6643 list_del(&item->list);
6645 vmx->nested.vmcs02_num--;
6651 * Free all VMCSs saved for this vcpu, except the one pointed by
6652 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6653 * must be &vmx->vmcs01.
6655 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6657 struct vmcs02_list *item, *n;
6659 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6660 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6662 * Something will leak if the above WARN triggers. Better than
6665 if (vmx->loaded_vmcs == &item->vmcs02)
6668 free_loaded_vmcs(&item->vmcs02);
6669 list_del(&item->list);
6671 vmx->nested.vmcs02_num--;
6676 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6677 * set the success or error code of an emulated VMX instruction, as specified
6678 * by Vol 2B, VMX Instruction Reference, "Conventions".
6680 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6682 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6683 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6684 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6687 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6689 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6690 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6691 X86_EFLAGS_SF | X86_EFLAGS_OF))
6695 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6696 u32 vm_instruction_error)
6698 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6700 * failValid writes the error number to the current VMCS, which
6701 * can't be done there isn't a current VMCS.
6703 nested_vmx_failInvalid(vcpu);
6706 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6707 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6708 X86_EFLAGS_SF | X86_EFLAGS_OF))
6710 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6712 * We don't need to force a shadow sync because
6713 * VM_INSTRUCTION_ERROR is not shadowed
6717 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6719 /* TODO: not to reset guest simply here. */
6720 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6721 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6724 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6726 struct vcpu_vmx *vmx =
6727 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6729 vmx->nested.preemption_timer_expired = true;
6730 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6731 kvm_vcpu_kick(&vmx->vcpu);
6733 return HRTIMER_NORESTART;
6737 * Decode the memory-address operand of a vmx instruction, as recorded on an
6738 * exit caused by such an instruction (run by a guest hypervisor).
6739 * On success, returns 0. When the operand is invalid, returns 1 and throws
6742 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6743 unsigned long exit_qualification,
6744 u32 vmx_instruction_info, bool wr, gva_t *ret)
6748 struct kvm_segment s;
6751 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6752 * Execution", on an exit, vmx_instruction_info holds most of the
6753 * addressing components of the operand. Only the displacement part
6754 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6755 * For how an actual address is calculated from all these components,
6756 * refer to Vol. 1, "Operand Addressing".
6758 int scaling = vmx_instruction_info & 3;
6759 int addr_size = (vmx_instruction_info >> 7) & 7;
6760 bool is_reg = vmx_instruction_info & (1u << 10);
6761 int seg_reg = (vmx_instruction_info >> 15) & 7;
6762 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6763 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6764 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6765 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6768 kvm_queue_exception(vcpu, UD_VECTOR);
6772 /* Addr = segment_base + offset */
6773 /* offset = base + [index * scale] + displacement */
6774 off = exit_qualification; /* holds the displacement */
6776 off += kvm_register_read(vcpu, base_reg);
6778 off += kvm_register_read(vcpu, index_reg)<<scaling;
6779 vmx_get_segment(vcpu, &s, seg_reg);
6780 *ret = s.base + off;
6782 if (addr_size == 1) /* 32 bit */
6785 /* Checks for #GP/#SS exceptions. */
6787 if (is_long_mode(vcpu)) {
6788 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6789 * non-canonical form. This is the only check on the memory
6790 * destination for long mode!
6792 exn = is_noncanonical_address(*ret);
6793 } else if (is_protmode(vcpu)) {
6794 /* Protected mode: apply checks for segment validity in the
6796 * - segment type check (#GP(0) may be thrown)
6797 * - usability check (#GP(0)/#SS(0))
6798 * - limit check (#GP(0)/#SS(0))
6801 /* #GP(0) if the destination operand is located in a
6802 * read-only data segment or any code segment.
6804 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6806 /* #GP(0) if the source operand is located in an
6807 * execute-only code segment
6809 exn = ((s.type & 0xa) == 8);
6811 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6814 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6816 exn = (s.unusable != 0);
6817 /* Protected mode: #GP(0)/#SS(0) if the memory
6818 * operand is outside the segment limit.
6820 exn = exn || (off + sizeof(u64) > s.limit);
6823 kvm_queue_exception_e(vcpu,
6824 seg_reg == VCPU_SREG_SS ?
6825 SS_VECTOR : GP_VECTOR,
6834 * This function performs the various checks including
6835 * - if it's 4KB aligned
6836 * - No bits beyond the physical address width are set
6837 * - Returns 0 on success or else 1
6838 * (Intel SDM Section 30.3)
6840 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6845 struct x86_exception e;
6847 struct vcpu_vmx *vmx = to_vmx(vcpu);
6848 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6850 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6851 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6854 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6855 sizeof(vmptr), &e)) {
6856 kvm_inject_page_fault(vcpu, &e);
6860 switch (exit_reason) {
6861 case EXIT_REASON_VMON:
6864 * The first 4 bytes of VMXON region contain the supported
6865 * VMCS revision identifier
6867 * Note - IA32_VMX_BASIC[48] will never be 1
6868 * for the nested case;
6869 * which replaces physical address width with 32
6872 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6873 nested_vmx_failInvalid(vcpu);
6874 skip_emulated_instruction(vcpu);
6878 page = nested_get_page(vcpu, vmptr);
6880 *(u32 *)kmap(page) != VMCS12_REVISION) {
6881 nested_vmx_failInvalid(vcpu);
6883 skip_emulated_instruction(vcpu);
6887 vmx->nested.vmxon_ptr = vmptr;
6889 case EXIT_REASON_VMCLEAR:
6890 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6891 nested_vmx_failValid(vcpu,
6892 VMXERR_VMCLEAR_INVALID_ADDRESS);
6893 skip_emulated_instruction(vcpu);
6897 if (vmptr == vmx->nested.vmxon_ptr) {
6898 nested_vmx_failValid(vcpu,
6899 VMXERR_VMCLEAR_VMXON_POINTER);
6900 skip_emulated_instruction(vcpu);
6904 case EXIT_REASON_VMPTRLD:
6905 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6906 nested_vmx_failValid(vcpu,
6907 VMXERR_VMPTRLD_INVALID_ADDRESS);
6908 skip_emulated_instruction(vcpu);
6912 if (vmptr == vmx->nested.vmxon_ptr) {
6913 nested_vmx_failValid(vcpu,
6914 VMXERR_VMCLEAR_VMXON_POINTER);
6915 skip_emulated_instruction(vcpu);
6920 return 1; /* shouldn't happen */
6929 * Emulate the VMXON instruction.
6930 * Currently, we just remember that VMX is active, and do not save or even
6931 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6932 * do not currently need to store anything in that guest-allocated memory
6933 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6934 * argument is different from the VMXON pointer (which the spec says they do).
6936 static int handle_vmon(struct kvm_vcpu *vcpu)
6938 struct kvm_segment cs;
6939 struct vcpu_vmx *vmx = to_vmx(vcpu);
6940 struct vmcs *shadow_vmcs;
6941 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6942 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6944 /* The Intel VMX Instruction Reference lists a bunch of bits that
6945 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6946 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6947 * Otherwise, we should fail with #UD. We test these now:
6949 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6950 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6951 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6952 kvm_queue_exception(vcpu, UD_VECTOR);
6956 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6957 if (is_long_mode(vcpu) && !cs.l) {
6958 kvm_queue_exception(vcpu, UD_VECTOR);
6962 if (vmx_get_cpl(vcpu)) {
6963 kvm_inject_gp(vcpu, 0);
6967 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6970 if (vmx->nested.vmxon) {
6971 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6972 skip_emulated_instruction(vcpu);
6976 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6977 != VMXON_NEEDED_FEATURES) {
6978 kvm_inject_gp(vcpu, 0);
6982 if (cpu_has_vmx_msr_bitmap()) {
6983 vmx->nested.msr_bitmap =
6984 (unsigned long *)__get_free_page(GFP_KERNEL);
6985 if (!vmx->nested.msr_bitmap)
6986 goto out_msr_bitmap;
6989 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6990 if (!vmx->nested.cached_vmcs12)
6991 goto out_cached_vmcs12;
6993 if (enable_shadow_vmcs) {
6994 shadow_vmcs = alloc_vmcs();
6996 goto out_shadow_vmcs;
6997 /* mark vmcs as shadow */
6998 shadow_vmcs->revision_id |= (1u << 31);
6999 /* init shadow vmcs */
7000 vmcs_clear(shadow_vmcs);
7001 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7004 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7005 vmx->nested.vmcs02_num = 0;
7007 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7008 HRTIMER_MODE_REL_PINNED);
7009 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7011 vmx->nested.vmxon = true;
7013 skip_emulated_instruction(vcpu);
7014 nested_vmx_succeed(vcpu);
7018 kfree(vmx->nested.cached_vmcs12);
7021 free_page((unsigned long)vmx->nested.msr_bitmap);
7028 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7029 * for running VMX instructions (except VMXON, whose prerequisites are
7030 * slightly different). It also specifies what exception to inject otherwise.
7032 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7034 struct kvm_segment cs;
7035 struct vcpu_vmx *vmx = to_vmx(vcpu);
7037 if (!vmx->nested.vmxon) {
7038 kvm_queue_exception(vcpu, UD_VECTOR);
7042 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7043 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7044 (is_long_mode(vcpu) && !cs.l)) {
7045 kvm_queue_exception(vcpu, UD_VECTOR);
7049 if (vmx_get_cpl(vcpu)) {
7050 kvm_inject_gp(vcpu, 0);
7057 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7059 if (vmx->nested.current_vmptr == -1ull)
7062 /* current_vmptr and current_vmcs12 are always set/reset together */
7063 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7066 if (enable_shadow_vmcs) {
7067 /* copy to memory all shadowed fields in case
7068 they were modified */
7069 copy_shadow_to_vmcs12(vmx);
7070 vmx->nested.sync_shadow_vmcs = false;
7071 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7072 SECONDARY_EXEC_SHADOW_VMCS);
7073 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7075 vmx->nested.posted_intr_nv = -1;
7077 /* Flush VMCS12 to guest memory */
7078 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7081 kunmap(vmx->nested.current_vmcs12_page);
7082 nested_release_page(vmx->nested.current_vmcs12_page);
7083 vmx->nested.current_vmptr = -1ull;
7084 vmx->nested.current_vmcs12 = NULL;
7088 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7089 * just stops using VMX.
7091 static void free_nested(struct vcpu_vmx *vmx)
7093 if (!vmx->nested.vmxon)
7096 vmx->nested.vmxon = false;
7097 free_vpid(vmx->nested.vpid02);
7098 nested_release_vmcs12(vmx);
7099 if (vmx->nested.msr_bitmap) {
7100 free_page((unsigned long)vmx->nested.msr_bitmap);
7101 vmx->nested.msr_bitmap = NULL;
7103 if (enable_shadow_vmcs) {
7104 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7105 free_vmcs(vmx->vmcs01.shadow_vmcs);
7106 vmx->vmcs01.shadow_vmcs = NULL;
7108 kfree(vmx->nested.cached_vmcs12);
7109 /* Unpin physical memory we referred to in current vmcs02 */
7110 if (vmx->nested.apic_access_page) {
7111 nested_release_page(vmx->nested.apic_access_page);
7112 vmx->nested.apic_access_page = NULL;
7114 if (vmx->nested.virtual_apic_page) {
7115 nested_release_page(vmx->nested.virtual_apic_page);
7116 vmx->nested.virtual_apic_page = NULL;
7118 if (vmx->nested.pi_desc_page) {
7119 kunmap(vmx->nested.pi_desc_page);
7120 nested_release_page(vmx->nested.pi_desc_page);
7121 vmx->nested.pi_desc_page = NULL;
7122 vmx->nested.pi_desc = NULL;
7125 nested_free_all_saved_vmcss(vmx);
7128 /* Emulate the VMXOFF instruction */
7129 static int handle_vmoff(struct kvm_vcpu *vcpu)
7131 if (!nested_vmx_check_permission(vcpu))
7133 free_nested(to_vmx(vcpu));
7134 skip_emulated_instruction(vcpu);
7135 nested_vmx_succeed(vcpu);
7139 /* Emulate the VMCLEAR instruction */
7140 static int handle_vmclear(struct kvm_vcpu *vcpu)
7142 struct vcpu_vmx *vmx = to_vmx(vcpu);
7144 struct vmcs12 *vmcs12;
7147 if (!nested_vmx_check_permission(vcpu))
7150 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7153 if (vmptr == vmx->nested.current_vmptr)
7154 nested_release_vmcs12(vmx);
7156 page = nested_get_page(vcpu, vmptr);
7159 * For accurate processor emulation, VMCLEAR beyond available
7160 * physical memory should do nothing at all. However, it is
7161 * possible that a nested vmx bug, not a guest hypervisor bug,
7162 * resulted in this case, so let's shut down before doing any
7165 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7168 vmcs12 = kmap(page);
7169 vmcs12->launch_state = 0;
7171 nested_release_page(page);
7173 nested_free_vmcs02(vmx, vmptr);
7175 skip_emulated_instruction(vcpu);
7176 nested_vmx_succeed(vcpu);
7180 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7182 /* Emulate the VMLAUNCH instruction */
7183 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7185 return nested_vmx_run(vcpu, true);
7188 /* Emulate the VMRESUME instruction */
7189 static int handle_vmresume(struct kvm_vcpu *vcpu)
7192 return nested_vmx_run(vcpu, false);
7195 enum vmcs_field_type {
7196 VMCS_FIELD_TYPE_U16 = 0,
7197 VMCS_FIELD_TYPE_U64 = 1,
7198 VMCS_FIELD_TYPE_U32 = 2,
7199 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7202 static inline int vmcs_field_type(unsigned long field)
7204 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7205 return VMCS_FIELD_TYPE_U32;
7206 return (field >> 13) & 0x3 ;
7209 static inline int vmcs_field_readonly(unsigned long field)
7211 return (((field >> 10) & 0x3) == 1);
7215 * Read a vmcs12 field. Since these can have varying lengths and we return
7216 * one type, we chose the biggest type (u64) and zero-extend the return value
7217 * to that size. Note that the caller, handle_vmread, might need to use only
7218 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7219 * 64-bit fields are to be returned).
7221 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7222 unsigned long field, u64 *ret)
7224 short offset = vmcs_field_to_offset(field);
7230 p = ((char *)(get_vmcs12(vcpu))) + offset;
7232 switch (vmcs_field_type(field)) {
7233 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7234 *ret = *((natural_width *)p);
7236 case VMCS_FIELD_TYPE_U16:
7239 case VMCS_FIELD_TYPE_U32:
7242 case VMCS_FIELD_TYPE_U64:
7252 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7253 unsigned long field, u64 field_value){
7254 short offset = vmcs_field_to_offset(field);
7255 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7259 switch (vmcs_field_type(field)) {
7260 case VMCS_FIELD_TYPE_U16:
7261 *(u16 *)p = field_value;
7263 case VMCS_FIELD_TYPE_U32:
7264 *(u32 *)p = field_value;
7266 case VMCS_FIELD_TYPE_U64:
7267 *(u64 *)p = field_value;
7269 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7270 *(natural_width *)p = field_value;
7279 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7282 unsigned long field;
7284 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7285 const unsigned long *fields = shadow_read_write_fields;
7286 const int num_fields = max_shadow_read_write_fields;
7290 vmcs_load(shadow_vmcs);
7292 for (i = 0; i < num_fields; i++) {
7294 switch (vmcs_field_type(field)) {
7295 case VMCS_FIELD_TYPE_U16:
7296 field_value = vmcs_read16(field);
7298 case VMCS_FIELD_TYPE_U32:
7299 field_value = vmcs_read32(field);
7301 case VMCS_FIELD_TYPE_U64:
7302 field_value = vmcs_read64(field);
7304 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7305 field_value = vmcs_readl(field);
7311 vmcs12_write_any(&vmx->vcpu, field, field_value);
7314 vmcs_clear(shadow_vmcs);
7315 vmcs_load(vmx->loaded_vmcs->vmcs);
7320 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7322 const unsigned long *fields[] = {
7323 shadow_read_write_fields,
7324 shadow_read_only_fields
7326 const int max_fields[] = {
7327 max_shadow_read_write_fields,
7328 max_shadow_read_only_fields
7331 unsigned long field;
7332 u64 field_value = 0;
7333 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7335 vmcs_load(shadow_vmcs);
7337 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7338 for (i = 0; i < max_fields[q]; i++) {
7339 field = fields[q][i];
7340 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7342 switch (vmcs_field_type(field)) {
7343 case VMCS_FIELD_TYPE_U16:
7344 vmcs_write16(field, (u16)field_value);
7346 case VMCS_FIELD_TYPE_U32:
7347 vmcs_write32(field, (u32)field_value);
7349 case VMCS_FIELD_TYPE_U64:
7350 vmcs_write64(field, (u64)field_value);
7352 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7353 vmcs_writel(field, (long)field_value);
7362 vmcs_clear(shadow_vmcs);
7363 vmcs_load(vmx->loaded_vmcs->vmcs);
7367 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7368 * used before) all generate the same failure when it is missing.
7370 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7372 struct vcpu_vmx *vmx = to_vmx(vcpu);
7373 if (vmx->nested.current_vmptr == -1ull) {
7374 nested_vmx_failInvalid(vcpu);
7375 skip_emulated_instruction(vcpu);
7381 static int handle_vmread(struct kvm_vcpu *vcpu)
7383 unsigned long field;
7385 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7386 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7389 if (!nested_vmx_check_permission(vcpu) ||
7390 !nested_vmx_check_vmcs12(vcpu))
7393 /* Decode instruction info and find the field to read */
7394 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7395 /* Read the field, zero-extended to a u64 field_value */
7396 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7397 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7398 skip_emulated_instruction(vcpu);
7402 * Now copy part of this value to register or memory, as requested.
7403 * Note that the number of bits actually copied is 32 or 64 depending
7404 * on the guest's mode (32 or 64 bit), not on the given field's length.
7406 if (vmx_instruction_info & (1u << 10)) {
7407 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7410 if (get_vmx_mem_address(vcpu, exit_qualification,
7411 vmx_instruction_info, true, &gva))
7413 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7414 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7415 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7418 nested_vmx_succeed(vcpu);
7419 skip_emulated_instruction(vcpu);
7424 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7426 unsigned long field;
7428 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7429 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7430 /* The value to write might be 32 or 64 bits, depending on L1's long
7431 * mode, and eventually we need to write that into a field of several
7432 * possible lengths. The code below first zero-extends the value to 64
7433 * bit (field_value), and then copies only the appropriate number of
7434 * bits into the vmcs12 field.
7436 u64 field_value = 0;
7437 struct x86_exception e;
7439 if (!nested_vmx_check_permission(vcpu) ||
7440 !nested_vmx_check_vmcs12(vcpu))
7443 if (vmx_instruction_info & (1u << 10))
7444 field_value = kvm_register_readl(vcpu,
7445 (((vmx_instruction_info) >> 3) & 0xf));
7447 if (get_vmx_mem_address(vcpu, exit_qualification,
7448 vmx_instruction_info, false, &gva))
7450 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7451 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7452 kvm_inject_page_fault(vcpu, &e);
7458 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7459 if (vmcs_field_readonly(field)) {
7460 nested_vmx_failValid(vcpu,
7461 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7462 skip_emulated_instruction(vcpu);
7466 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7467 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7468 skip_emulated_instruction(vcpu);
7472 nested_vmx_succeed(vcpu);
7473 skip_emulated_instruction(vcpu);
7477 /* Emulate the VMPTRLD instruction */
7478 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7480 struct vcpu_vmx *vmx = to_vmx(vcpu);
7483 if (!nested_vmx_check_permission(vcpu))
7486 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7489 if (vmx->nested.current_vmptr != vmptr) {
7490 struct vmcs12 *new_vmcs12;
7492 page = nested_get_page(vcpu, vmptr);
7494 nested_vmx_failInvalid(vcpu);
7495 skip_emulated_instruction(vcpu);
7498 new_vmcs12 = kmap(page);
7499 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7501 nested_release_page_clean(page);
7502 nested_vmx_failValid(vcpu,
7503 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7504 skip_emulated_instruction(vcpu);
7508 nested_release_vmcs12(vmx);
7509 vmx->nested.current_vmptr = vmptr;
7510 vmx->nested.current_vmcs12 = new_vmcs12;
7511 vmx->nested.current_vmcs12_page = page;
7513 * Load VMCS12 from guest memory since it is not already
7516 memcpy(vmx->nested.cached_vmcs12,
7517 vmx->nested.current_vmcs12, VMCS12_SIZE);
7519 if (enable_shadow_vmcs) {
7520 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7521 SECONDARY_EXEC_SHADOW_VMCS);
7522 vmcs_write64(VMCS_LINK_POINTER,
7523 __pa(vmx->vmcs01.shadow_vmcs));
7524 vmx->nested.sync_shadow_vmcs = true;
7528 nested_vmx_succeed(vcpu);
7529 skip_emulated_instruction(vcpu);
7533 /* Emulate the VMPTRST instruction */
7534 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7536 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7537 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7539 struct x86_exception e;
7541 if (!nested_vmx_check_permission(vcpu))
7544 if (get_vmx_mem_address(vcpu, exit_qualification,
7545 vmx_instruction_info, true, &vmcs_gva))
7547 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7548 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7549 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7551 kvm_inject_page_fault(vcpu, &e);
7554 nested_vmx_succeed(vcpu);
7555 skip_emulated_instruction(vcpu);
7559 /* Emulate the INVEPT instruction */
7560 static int handle_invept(struct kvm_vcpu *vcpu)
7562 struct vcpu_vmx *vmx = to_vmx(vcpu);
7563 u32 vmx_instruction_info, types;
7566 struct x86_exception e;
7571 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7572 SECONDARY_EXEC_ENABLE_EPT) ||
7573 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7574 kvm_queue_exception(vcpu, UD_VECTOR);
7578 if (!nested_vmx_check_permission(vcpu))
7581 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7582 kvm_queue_exception(vcpu, UD_VECTOR);
7586 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7587 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7589 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7591 if (type >= 32 || !(types & (1 << type))) {
7592 nested_vmx_failValid(vcpu,
7593 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7594 skip_emulated_instruction(vcpu);
7598 /* According to the Intel VMX instruction reference, the memory
7599 * operand is read even if it isn't needed (e.g., for type==global)
7601 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7602 vmx_instruction_info, false, &gva))
7604 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7605 sizeof(operand), &e)) {
7606 kvm_inject_page_fault(vcpu, &e);
7611 case VMX_EPT_EXTENT_GLOBAL:
7613 * TODO: track mappings and invalidate
7614 * single context requests appropriately
7616 case VMX_EPT_EXTENT_CONTEXT:
7617 kvm_mmu_sync_roots(vcpu);
7618 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7619 nested_vmx_succeed(vcpu);
7626 skip_emulated_instruction(vcpu);
7630 static int handle_invvpid(struct kvm_vcpu *vcpu)
7632 struct vcpu_vmx *vmx = to_vmx(vcpu);
7633 u32 vmx_instruction_info;
7634 unsigned long type, types;
7636 struct x86_exception e;
7639 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7640 SECONDARY_EXEC_ENABLE_VPID) ||
7641 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7642 kvm_queue_exception(vcpu, UD_VECTOR);
7646 if (!nested_vmx_check_permission(vcpu))
7649 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7650 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7652 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7654 if (type >= 32 || !(types & (1 << type))) {
7655 nested_vmx_failValid(vcpu,
7656 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7657 skip_emulated_instruction(vcpu);
7661 /* according to the intel vmx instruction reference, the memory
7662 * operand is read even if it isn't needed (e.g., for type==global)
7664 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7665 vmx_instruction_info, false, &gva))
7667 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7669 kvm_inject_page_fault(vcpu, &e);
7674 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7676 * Old versions of KVM use the single-context version so we
7677 * have to support it; just treat it the same as all-context.
7679 case VMX_VPID_EXTENT_ALL_CONTEXT:
7680 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7681 nested_vmx_succeed(vcpu);
7684 /* Trap individual address invalidation invvpid calls */
7689 skip_emulated_instruction(vcpu);
7693 static int handle_pml_full(struct kvm_vcpu *vcpu)
7695 unsigned long exit_qualification;
7697 trace_kvm_pml_full(vcpu->vcpu_id);
7699 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7702 * PML buffer FULL happened while executing iret from NMI,
7703 * "blocked by NMI" bit has to be set before next VM entry.
7705 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7706 cpu_has_virtual_nmis() &&
7707 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7708 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7709 GUEST_INTR_STATE_NMI);
7712 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7713 * here.., and there's no userspace involvement needed for PML.
7718 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7720 kvm_lapic_expired_hv_timer(vcpu);
7725 * The exit handlers return 1 if the exit was handled fully and guest execution
7726 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7727 * to be done to userspace and return 0.
7729 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7730 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7731 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7732 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7733 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7734 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7735 [EXIT_REASON_CR_ACCESS] = handle_cr,
7736 [EXIT_REASON_DR_ACCESS] = handle_dr,
7737 [EXIT_REASON_CPUID] = handle_cpuid,
7738 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7739 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7740 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7741 [EXIT_REASON_HLT] = handle_halt,
7742 [EXIT_REASON_INVD] = handle_invd,
7743 [EXIT_REASON_INVLPG] = handle_invlpg,
7744 [EXIT_REASON_RDPMC] = handle_rdpmc,
7745 [EXIT_REASON_VMCALL] = handle_vmcall,
7746 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7747 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7748 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7749 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7750 [EXIT_REASON_VMREAD] = handle_vmread,
7751 [EXIT_REASON_VMRESUME] = handle_vmresume,
7752 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7753 [EXIT_REASON_VMOFF] = handle_vmoff,
7754 [EXIT_REASON_VMON] = handle_vmon,
7755 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7756 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7757 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7758 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7759 [EXIT_REASON_WBINVD] = handle_wbinvd,
7760 [EXIT_REASON_XSETBV] = handle_xsetbv,
7761 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7762 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7763 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7764 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7765 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7766 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7767 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7768 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7769 [EXIT_REASON_INVEPT] = handle_invept,
7770 [EXIT_REASON_INVVPID] = handle_invvpid,
7771 [EXIT_REASON_XSAVES] = handle_xsaves,
7772 [EXIT_REASON_XRSTORS] = handle_xrstors,
7773 [EXIT_REASON_PML_FULL] = handle_pml_full,
7774 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7777 static const int kvm_vmx_max_exit_handlers =
7778 ARRAY_SIZE(kvm_vmx_exit_handlers);
7780 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7781 struct vmcs12 *vmcs12)
7783 unsigned long exit_qualification;
7784 gpa_t bitmap, last_bitmap;
7789 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7790 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7792 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7794 port = exit_qualification >> 16;
7795 size = (exit_qualification & 7) + 1;
7797 last_bitmap = (gpa_t)-1;
7802 bitmap = vmcs12->io_bitmap_a;
7803 else if (port < 0x10000)
7804 bitmap = vmcs12->io_bitmap_b;
7807 bitmap += (port & 0x7fff) / 8;
7809 if (last_bitmap != bitmap)
7810 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7812 if (b & (1 << (port & 7)))
7817 last_bitmap = bitmap;
7824 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7825 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7826 * disinterest in the current event (read or write a specific MSR) by using an
7827 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7829 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7830 struct vmcs12 *vmcs12, u32 exit_reason)
7832 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7835 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7839 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7840 * for the four combinations of read/write and low/high MSR numbers.
7841 * First we need to figure out which of the four to use:
7843 bitmap = vmcs12->msr_bitmap;
7844 if (exit_reason == EXIT_REASON_MSR_WRITE)
7846 if (msr_index >= 0xc0000000) {
7847 msr_index -= 0xc0000000;
7851 /* Then read the msr_index'th bit from this bitmap: */
7852 if (msr_index < 1024*8) {
7854 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7856 return 1 & (b >> (msr_index & 7));
7858 return true; /* let L1 handle the wrong parameter */
7862 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7863 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7864 * intercept (via guest_host_mask etc.) the current event.
7866 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7867 struct vmcs12 *vmcs12)
7869 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7870 int cr = exit_qualification & 15;
7871 int reg = (exit_qualification >> 8) & 15;
7872 unsigned long val = kvm_register_readl(vcpu, reg);
7874 switch ((exit_qualification >> 4) & 3) {
7875 case 0: /* mov to cr */
7878 if (vmcs12->cr0_guest_host_mask &
7879 (val ^ vmcs12->cr0_read_shadow))
7883 if ((vmcs12->cr3_target_count >= 1 &&
7884 vmcs12->cr3_target_value0 == val) ||
7885 (vmcs12->cr3_target_count >= 2 &&
7886 vmcs12->cr3_target_value1 == val) ||
7887 (vmcs12->cr3_target_count >= 3 &&
7888 vmcs12->cr3_target_value2 == val) ||
7889 (vmcs12->cr3_target_count >= 4 &&
7890 vmcs12->cr3_target_value3 == val))
7892 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7896 if (vmcs12->cr4_guest_host_mask &
7897 (vmcs12->cr4_read_shadow ^ val))
7901 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7907 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7908 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7911 case 1: /* mov from cr */
7914 if (vmcs12->cpu_based_vm_exec_control &
7915 CPU_BASED_CR3_STORE_EXITING)
7919 if (vmcs12->cpu_based_vm_exec_control &
7920 CPU_BASED_CR8_STORE_EXITING)
7927 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7928 * cr0. Other attempted changes are ignored, with no exit.
7930 if (vmcs12->cr0_guest_host_mask & 0xe &
7931 (val ^ vmcs12->cr0_read_shadow))
7933 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7934 !(vmcs12->cr0_read_shadow & 0x1) &&
7943 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7944 * should handle it ourselves in L0 (and then continue L2). Only call this
7945 * when in is_guest_mode (L2).
7947 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7949 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7950 struct vcpu_vmx *vmx = to_vmx(vcpu);
7951 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7952 u32 exit_reason = vmx->exit_reason;
7954 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7955 vmcs_readl(EXIT_QUALIFICATION),
7956 vmx->idt_vectoring_info,
7958 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7961 if (vmx->nested.nested_run_pending)
7964 if (unlikely(vmx->fail)) {
7965 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7966 vmcs_read32(VM_INSTRUCTION_ERROR));
7970 switch (exit_reason) {
7971 case EXIT_REASON_EXCEPTION_NMI:
7972 if (!is_exception(intr_info))
7974 else if (is_page_fault(intr_info))
7976 else if (is_no_device(intr_info) &&
7977 !(vmcs12->guest_cr0 & X86_CR0_TS))
7979 else if (is_debug(intr_info) &&
7981 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7983 else if (is_breakpoint(intr_info) &&
7984 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7986 return vmcs12->exception_bitmap &
7987 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7988 case EXIT_REASON_EXTERNAL_INTERRUPT:
7990 case EXIT_REASON_TRIPLE_FAULT:
7992 case EXIT_REASON_PENDING_INTERRUPT:
7993 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7994 case EXIT_REASON_NMI_WINDOW:
7995 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7996 case EXIT_REASON_TASK_SWITCH:
7998 case EXIT_REASON_CPUID:
7999 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
8002 case EXIT_REASON_HLT:
8003 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8004 case EXIT_REASON_INVD:
8006 case EXIT_REASON_INVLPG:
8007 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8008 case EXIT_REASON_RDPMC:
8009 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8010 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8011 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8012 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8013 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8014 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8015 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8016 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8017 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8019 * VMX instructions trap unconditionally. This allows L1 to
8020 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8023 case EXIT_REASON_CR_ACCESS:
8024 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8025 case EXIT_REASON_DR_ACCESS:
8026 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8027 case EXIT_REASON_IO_INSTRUCTION:
8028 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8029 case EXIT_REASON_MSR_READ:
8030 case EXIT_REASON_MSR_WRITE:
8031 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8032 case EXIT_REASON_INVALID_STATE:
8034 case EXIT_REASON_MWAIT_INSTRUCTION:
8035 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8036 case EXIT_REASON_MONITOR_TRAP_FLAG:
8037 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8038 case EXIT_REASON_MONITOR_INSTRUCTION:
8039 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8040 case EXIT_REASON_PAUSE_INSTRUCTION:
8041 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8042 nested_cpu_has2(vmcs12,
8043 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8044 case EXIT_REASON_MCE_DURING_VMENTRY:
8046 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8047 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8048 case EXIT_REASON_APIC_ACCESS:
8049 return nested_cpu_has2(vmcs12,
8050 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8051 case EXIT_REASON_APIC_WRITE:
8052 case EXIT_REASON_EOI_INDUCED:
8053 /* apic_write and eoi_induced should exit unconditionally. */
8055 case EXIT_REASON_EPT_VIOLATION:
8057 * L0 always deals with the EPT violation. If nested EPT is
8058 * used, and the nested mmu code discovers that the address is
8059 * missing in the guest EPT table (EPT12), the EPT violation
8060 * will be injected with nested_ept_inject_page_fault()
8063 case EXIT_REASON_EPT_MISCONFIG:
8065 * L2 never uses directly L1's EPT, but rather L0's own EPT
8066 * table (shadow on EPT) or a merged EPT table that L0 built
8067 * (EPT on EPT). So any problems with the structure of the
8068 * table is L0's fault.
8071 case EXIT_REASON_WBINVD:
8072 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8073 case EXIT_REASON_XSETBV:
8075 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8077 * This should never happen, since it is not possible to
8078 * set XSS to a non-zero value---neither in L1 nor in L2.
8079 * If if it were, XSS would have to be checked against
8080 * the XSS exit bitmap in vmcs12.
8082 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8083 case EXIT_REASON_PREEMPTION_TIMER:
8090 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8092 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8093 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8096 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8099 __free_page(vmx->pml_pg);
8104 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8106 struct vcpu_vmx *vmx = to_vmx(vcpu);
8110 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8112 /* Do nothing if PML buffer is empty */
8113 if (pml_idx == (PML_ENTITY_NUM - 1))
8116 /* PML index always points to next available PML buffer entity */
8117 if (pml_idx >= PML_ENTITY_NUM)
8122 pml_buf = page_address(vmx->pml_pg);
8123 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8126 gpa = pml_buf[pml_idx];
8127 WARN_ON(gpa & (PAGE_SIZE - 1));
8128 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8131 /* reset PML index */
8132 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8136 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8137 * Called before reporting dirty_bitmap to userspace.
8139 static void kvm_flush_pml_buffers(struct kvm *kvm)
8142 struct kvm_vcpu *vcpu;
8144 * We only need to kick vcpu out of guest mode here, as PML buffer
8145 * is flushed at beginning of all VMEXITs, and it's obvious that only
8146 * vcpus running in guest are possible to have unflushed GPAs in PML
8149 kvm_for_each_vcpu(i, vcpu, kvm)
8150 kvm_vcpu_kick(vcpu);
8153 static void vmx_dump_sel(char *name, uint32_t sel)
8155 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8156 name, vmcs_read32(sel),
8157 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8158 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8159 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8162 static void vmx_dump_dtsel(char *name, uint32_t limit)
8164 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8165 name, vmcs_read32(limit),
8166 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8169 static void dump_vmcs(void)
8171 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8172 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8173 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8174 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8175 u32 secondary_exec_control = 0;
8176 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8177 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8180 if (cpu_has_secondary_exec_ctrls())
8181 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8183 pr_err("*** Guest State ***\n");
8184 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8185 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8186 vmcs_readl(CR0_GUEST_HOST_MASK));
8187 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8188 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8189 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8190 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8191 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8193 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8194 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8195 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8196 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8198 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8199 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8200 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8201 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8202 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8203 vmcs_readl(GUEST_SYSENTER_ESP),
8204 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8205 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8206 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8207 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8208 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8209 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8210 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8211 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8212 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8213 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8214 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8215 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8216 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8217 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8218 efer, vmcs_read64(GUEST_IA32_PAT));
8219 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8220 vmcs_read64(GUEST_IA32_DEBUGCTL),
8221 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8222 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8223 pr_err("PerfGlobCtl = 0x%016llx\n",
8224 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8225 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8226 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8227 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8228 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8229 vmcs_read32(GUEST_ACTIVITY_STATE));
8230 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8231 pr_err("InterruptStatus = %04x\n",
8232 vmcs_read16(GUEST_INTR_STATUS));
8234 pr_err("*** Host State ***\n");
8235 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8236 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8237 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8238 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8239 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8240 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8241 vmcs_read16(HOST_TR_SELECTOR));
8242 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8243 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8244 vmcs_readl(HOST_TR_BASE));
8245 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8246 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8247 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8248 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8249 vmcs_readl(HOST_CR4));
8250 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8251 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8252 vmcs_read32(HOST_IA32_SYSENTER_CS),
8253 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8254 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8255 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8256 vmcs_read64(HOST_IA32_EFER),
8257 vmcs_read64(HOST_IA32_PAT));
8258 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8259 pr_err("PerfGlobCtl = 0x%016llx\n",
8260 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8262 pr_err("*** Control State ***\n");
8263 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8264 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8265 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8266 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8267 vmcs_read32(EXCEPTION_BITMAP),
8268 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8269 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8270 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8271 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8272 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8273 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8274 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8275 vmcs_read32(VM_EXIT_INTR_INFO),
8276 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8277 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8278 pr_err(" reason=%08x qualification=%016lx\n",
8279 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8280 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8281 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8282 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8283 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8284 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8285 pr_err("TSC Multiplier = 0x%016llx\n",
8286 vmcs_read64(TSC_MULTIPLIER));
8287 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8288 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8289 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8290 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8291 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8292 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8293 n = vmcs_read32(CR3_TARGET_COUNT);
8294 for (i = 0; i + 1 < n; i += 4)
8295 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8296 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8297 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8299 pr_err("CR3 target%u=%016lx\n",
8300 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8301 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8302 pr_err("PLE Gap=%08x Window=%08x\n",
8303 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8304 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8305 pr_err("Virtual processor ID = 0x%04x\n",
8306 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8310 * The guest has exited. See if we can fix it or if we need userspace
8313 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8315 struct vcpu_vmx *vmx = to_vmx(vcpu);
8316 u32 exit_reason = vmx->exit_reason;
8317 u32 vectoring_info = vmx->idt_vectoring_info;
8319 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8322 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8323 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8324 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8325 * mode as if vcpus is in root mode, the PML buffer must has been
8329 vmx_flush_pml_buffer(vcpu);
8331 /* If guest state is invalid, start emulating */
8332 if (vmx->emulation_required)
8333 return handle_invalid_guest_state(vcpu);
8335 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8336 nested_vmx_vmexit(vcpu, exit_reason,
8337 vmcs_read32(VM_EXIT_INTR_INFO),
8338 vmcs_readl(EXIT_QUALIFICATION));
8342 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8344 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8345 vcpu->run->fail_entry.hardware_entry_failure_reason
8350 if (unlikely(vmx->fail)) {
8351 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8352 vcpu->run->fail_entry.hardware_entry_failure_reason
8353 = vmcs_read32(VM_INSTRUCTION_ERROR);
8359 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8360 * delivery event since it indicates guest is accessing MMIO.
8361 * The vm-exit can be triggered again after return to guest that
8362 * will cause infinite loop.
8364 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8365 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8366 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8367 exit_reason != EXIT_REASON_PML_FULL &&
8368 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8369 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8370 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8371 vcpu->run->internal.ndata = 2;
8372 vcpu->run->internal.data[0] = vectoring_info;
8373 vcpu->run->internal.data[1] = exit_reason;
8377 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8378 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8379 get_vmcs12(vcpu))))) {
8380 if (vmx_interrupt_allowed(vcpu)) {
8381 vmx->soft_vnmi_blocked = 0;
8382 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8383 vcpu->arch.nmi_pending) {
8385 * This CPU don't support us in finding the end of an
8386 * NMI-blocked window if the guest runs with IRQs
8387 * disabled. So we pull the trigger after 1 s of
8388 * futile waiting, but inform the user about this.
8390 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8391 "state on VCPU %d after 1 s timeout\n",
8392 __func__, vcpu->vcpu_id);
8393 vmx->soft_vnmi_blocked = 0;
8397 if (exit_reason < kvm_vmx_max_exit_handlers
8398 && kvm_vmx_exit_handlers[exit_reason])
8399 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8401 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8402 kvm_queue_exception(vcpu, UD_VECTOR);
8407 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8409 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8411 if (is_guest_mode(vcpu) &&
8412 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8415 if (irr == -1 || tpr < irr) {
8416 vmcs_write32(TPR_THRESHOLD, 0);
8420 vmcs_write32(TPR_THRESHOLD, irr);
8423 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8425 u32 sec_exec_control;
8427 /* Postpone execution until vmcs01 is the current VMCS. */
8428 if (is_guest_mode(vcpu)) {
8429 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8433 if (!cpu_has_vmx_virtualize_x2apic_mode())
8436 if (!cpu_need_tpr_shadow(vcpu))
8439 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8442 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8443 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8445 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8446 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8448 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8450 vmx_set_msr_bitmap(vcpu);
8453 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8455 struct vcpu_vmx *vmx = to_vmx(vcpu);
8458 * Currently we do not handle the nested case where L2 has an
8459 * APIC access page of its own; that page is still pinned.
8460 * Hence, we skip the case where the VCPU is in guest mode _and_
8461 * L1 prepared an APIC access page for L2.
8463 * For the case where L1 and L2 share the same APIC access page
8464 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8465 * in the vmcs12), this function will only update either the vmcs01
8466 * or the vmcs02. If the former, the vmcs02 will be updated by
8467 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8468 * the next L2->L1 exit.
8470 if (!is_guest_mode(vcpu) ||
8471 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8473 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8476 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8484 status = vmcs_read16(GUEST_INTR_STATUS);
8486 if (max_isr != old) {
8488 status |= max_isr << 8;
8489 vmcs_write16(GUEST_INTR_STATUS, status);
8493 static void vmx_set_rvi(int vector)
8501 status = vmcs_read16(GUEST_INTR_STATUS);
8502 old = (u8)status & 0xff;
8503 if ((u8)vector != old) {
8505 status |= (u8)vector;
8506 vmcs_write16(GUEST_INTR_STATUS, status);
8510 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8512 if (!is_guest_mode(vcpu)) {
8513 vmx_set_rvi(max_irr);
8521 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8524 if (nested_exit_on_intr(vcpu))
8528 * Else, fall back to pre-APICv interrupt injection since L2
8529 * is run without virtual interrupt delivery.
8531 if (!kvm_event_needs_reinjection(vcpu) &&
8532 vmx_interrupt_allowed(vcpu)) {
8533 kvm_queue_interrupt(vcpu, max_irr, false);
8534 vmx_inject_irq(vcpu);
8538 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8540 if (!kvm_vcpu_apicv_active(vcpu))
8543 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8544 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8545 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8546 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8549 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8553 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8554 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8557 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8558 exit_intr_info = vmx->exit_intr_info;
8560 /* Handle machine checks before interrupts are enabled */
8561 if (is_machine_check(exit_intr_info))
8562 kvm_machine_check();
8564 /* We need to handle NMIs before interrupts are enabled */
8565 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8566 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8567 kvm_before_handle_nmi(&vmx->vcpu);
8569 kvm_after_handle_nmi(&vmx->vcpu);
8573 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8575 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8576 register void *__sp asm(_ASM_SP);
8579 * If external interrupt exists, IF bit is set in rflags/eflags on the
8580 * interrupt stack frame, and interrupt will be enabled on a return
8581 * from interrupt handler.
8583 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8584 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8585 unsigned int vector;
8586 unsigned long entry;
8588 struct vcpu_vmx *vmx = to_vmx(vcpu);
8589 #ifdef CONFIG_X86_64
8593 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8594 desc = (gate_desc *)vmx->host_idt_base + vector;
8595 entry = gate_offset(*desc);
8597 #ifdef CONFIG_X86_64
8598 "mov %%" _ASM_SP ", %[sp]\n\t"
8599 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8604 __ASM_SIZE(push) " $%c[cs]\n\t"
8605 "call *%[entry]\n\t"
8607 #ifdef CONFIG_X86_64
8613 [ss]"i"(__KERNEL_DS),
8614 [cs]"i"(__KERNEL_CS)
8619 static bool vmx_has_high_real_mode_segbase(void)
8621 return enable_unrestricted_guest || emulate_invalid_guest_state;
8624 static bool vmx_mpx_supported(void)
8626 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8627 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8630 static bool vmx_xsaves_supported(void)
8632 return vmcs_config.cpu_based_2nd_exec_ctrl &
8633 SECONDARY_EXEC_XSAVES;
8636 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8641 bool idtv_info_valid;
8643 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8645 if (cpu_has_virtual_nmis()) {
8646 if (vmx->nmi_known_unmasked)
8649 * Can't use vmx->exit_intr_info since we're not sure what
8650 * the exit reason is.
8652 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8653 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8654 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8656 * SDM 3: 27.7.1.2 (September 2008)
8657 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8658 * a guest IRET fault.
8659 * SDM 3: 23.2.2 (September 2008)
8660 * Bit 12 is undefined in any of the following cases:
8661 * If the VM exit sets the valid bit in the IDT-vectoring
8662 * information field.
8663 * If the VM exit is due to a double fault.
8665 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8666 vector != DF_VECTOR && !idtv_info_valid)
8667 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8668 GUEST_INTR_STATE_NMI);
8670 vmx->nmi_known_unmasked =
8671 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8672 & GUEST_INTR_STATE_NMI);
8673 } else if (unlikely(vmx->soft_vnmi_blocked))
8674 vmx->vnmi_blocked_time +=
8675 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8678 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8679 u32 idt_vectoring_info,
8680 int instr_len_field,
8681 int error_code_field)
8685 bool idtv_info_valid;
8687 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8689 vcpu->arch.nmi_injected = false;
8690 kvm_clear_exception_queue(vcpu);
8691 kvm_clear_interrupt_queue(vcpu);
8693 if (!idtv_info_valid)
8696 kvm_make_request(KVM_REQ_EVENT, vcpu);
8698 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8699 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8702 case INTR_TYPE_NMI_INTR:
8703 vcpu->arch.nmi_injected = true;
8705 * SDM 3: 27.7.1.2 (September 2008)
8706 * Clear bit "block by NMI" before VM entry if a NMI
8709 vmx_set_nmi_mask(vcpu, false);
8711 case INTR_TYPE_SOFT_EXCEPTION:
8712 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8714 case INTR_TYPE_HARD_EXCEPTION:
8715 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8716 u32 err = vmcs_read32(error_code_field);
8717 kvm_requeue_exception_e(vcpu, vector, err);
8719 kvm_requeue_exception(vcpu, vector);
8721 case INTR_TYPE_SOFT_INTR:
8722 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8724 case INTR_TYPE_EXT_INTR:
8725 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8732 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8734 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8735 VM_EXIT_INSTRUCTION_LEN,
8736 IDT_VECTORING_ERROR_CODE);
8739 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8741 __vmx_complete_interrupts(vcpu,
8742 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8743 VM_ENTRY_INSTRUCTION_LEN,
8744 VM_ENTRY_EXCEPTION_ERROR_CODE);
8746 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8749 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8752 struct perf_guest_switch_msr *msrs;
8754 msrs = perf_guest_get_msrs(&nr_msrs);
8759 for (i = 0; i < nr_msrs; i++)
8760 if (msrs[i].host == msrs[i].guest)
8761 clear_atomic_switch_msr(vmx, msrs[i].msr);
8763 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8767 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8769 struct vcpu_vmx *vmx = to_vmx(vcpu);
8773 if (vmx->hv_deadline_tsc == -1)
8777 if (vmx->hv_deadline_tsc > tscl)
8778 /* sure to be 32 bit only because checked on set_hv_timer */
8779 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8780 cpu_preemption_timer_multi);
8784 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8787 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8789 struct vcpu_vmx *vmx = to_vmx(vcpu);
8790 unsigned long debugctlmsr, cr4;
8792 /* Record the guest's net vcpu time for enforced NMI injections. */
8793 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8794 vmx->entry_time = ktime_get();
8796 /* Don't enter VMX if guest state is invalid, let the exit handler
8797 start emulation until we arrive back to a valid state */
8798 if (vmx->emulation_required)
8801 if (vmx->ple_window_dirty) {
8802 vmx->ple_window_dirty = false;
8803 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8806 if (vmx->nested.sync_shadow_vmcs) {
8807 copy_vmcs12_to_shadow(vmx);
8808 vmx->nested.sync_shadow_vmcs = false;
8811 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8812 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8813 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8814 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8816 cr4 = cr4_read_shadow();
8817 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8818 vmcs_writel(HOST_CR4, cr4);
8819 vmx->host_state.vmcs_host_cr4 = cr4;
8822 /* When single-stepping over STI and MOV SS, we must clear the
8823 * corresponding interruptibility bits in the guest state. Otherwise
8824 * vmentry fails as it then expects bit 14 (BS) in pending debug
8825 * exceptions being set, but that's not correct for the guest debugging
8827 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8828 vmx_set_interrupt_shadow(vcpu, 0);
8830 if (vmx->guest_pkru_valid)
8831 __write_pkru(vmx->guest_pkru);
8833 atomic_switch_perf_msrs(vmx);
8834 debugctlmsr = get_debugctlmsr();
8836 vmx_arm_hv_timer(vcpu);
8838 vmx->__launched = vmx->loaded_vmcs->launched;
8840 /* Store host registers */
8841 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8842 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8843 "push %%" _ASM_CX " \n\t"
8844 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8846 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8847 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8849 /* Reload cr2 if changed */
8850 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8851 "mov %%cr2, %%" _ASM_DX " \n\t"
8852 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8854 "mov %%" _ASM_AX", %%cr2 \n\t"
8856 /* Check if vmlaunch of vmresume is needed */
8857 "cmpl $0, %c[launched](%0) \n\t"
8858 /* Load guest registers. Don't clobber flags. */
8859 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8860 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8861 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8862 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8863 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8864 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8865 #ifdef CONFIG_X86_64
8866 "mov %c[r8](%0), %%r8 \n\t"
8867 "mov %c[r9](%0), %%r9 \n\t"
8868 "mov %c[r10](%0), %%r10 \n\t"
8869 "mov %c[r11](%0), %%r11 \n\t"
8870 "mov %c[r12](%0), %%r12 \n\t"
8871 "mov %c[r13](%0), %%r13 \n\t"
8872 "mov %c[r14](%0), %%r14 \n\t"
8873 "mov %c[r15](%0), %%r15 \n\t"
8875 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8877 /* Enter guest mode */
8879 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8881 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8883 /* Save guest registers, load host registers, keep flags */
8884 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8886 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8887 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8888 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8889 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8890 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8891 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8892 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8893 #ifdef CONFIG_X86_64
8894 "mov %%r8, %c[r8](%0) \n\t"
8895 "mov %%r9, %c[r9](%0) \n\t"
8896 "mov %%r10, %c[r10](%0) \n\t"
8897 "mov %%r11, %c[r11](%0) \n\t"
8898 "mov %%r12, %c[r12](%0) \n\t"
8899 "mov %%r13, %c[r13](%0) \n\t"
8900 "mov %%r14, %c[r14](%0) \n\t"
8901 "mov %%r15, %c[r15](%0) \n\t"
8903 "mov %%cr2, %%" _ASM_AX " \n\t"
8904 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8906 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8907 "setbe %c[fail](%0) \n\t"
8908 ".pushsection .rodata \n\t"
8909 ".global vmx_return \n\t"
8910 "vmx_return: " _ASM_PTR " 2b \n\t"
8912 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8913 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8914 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8915 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8916 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8917 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8918 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8919 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8920 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8921 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8922 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8923 #ifdef CONFIG_X86_64
8924 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8925 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8926 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8927 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8928 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8929 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8930 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8931 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8933 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8934 [wordsize]"i"(sizeof(ulong))
8936 #ifdef CONFIG_X86_64
8937 , "rax", "rbx", "rdi", "rsi"
8938 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8940 , "eax", "ebx", "edi", "esi"
8944 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8946 update_debugctlmsr(debugctlmsr);
8948 #ifndef CONFIG_X86_64
8950 * The sysexit path does not restore ds/es, so we must set them to
8951 * a reasonable value ourselves.
8953 * We can't defer this to vmx_load_host_state() since that function
8954 * may be executed in interrupt context, which saves and restore segments
8955 * around it, nullifying its effect.
8957 loadsegment(ds, __USER_DS);
8958 loadsegment(es, __USER_DS);
8961 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8962 | (1 << VCPU_EXREG_RFLAGS)
8963 | (1 << VCPU_EXREG_PDPTR)
8964 | (1 << VCPU_EXREG_SEGMENTS)
8965 | (1 << VCPU_EXREG_CR3));
8966 vcpu->arch.regs_dirty = 0;
8968 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8970 vmx->loaded_vmcs->launched = 1;
8972 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8975 * eager fpu is enabled if PKEY is supported and CR4 is switched
8976 * back on host, so it is safe to read guest PKRU from current
8979 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8980 vmx->guest_pkru = __read_pkru();
8981 if (vmx->guest_pkru != vmx->host_pkru) {
8982 vmx->guest_pkru_valid = true;
8983 __write_pkru(vmx->host_pkru);
8985 vmx->guest_pkru_valid = false;
8989 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8990 * we did not inject a still-pending event to L1 now because of
8991 * nested_run_pending, we need to re-enable this bit.
8993 if (vmx->nested.nested_run_pending)
8994 kvm_make_request(KVM_REQ_EVENT, vcpu);
8996 vmx->nested.nested_run_pending = 0;
8998 vmx_complete_atomic_exit(vmx);
8999 vmx_recover_nmi_blocking(vmx);
9000 vmx_complete_interrupts(vmx);
9003 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9005 struct vcpu_vmx *vmx = to_vmx(vcpu);
9008 if (vmx->loaded_vmcs == &vmx->vmcs01)
9012 vmx->loaded_vmcs = &vmx->vmcs01;
9014 vmx_vcpu_load(vcpu, cpu);
9020 * Ensure that the current vmcs of the logical processor is the
9021 * vmcs01 of the vcpu before calling free_nested().
9023 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9025 struct vcpu_vmx *vmx = to_vmx(vcpu);
9028 r = vcpu_load(vcpu);
9030 vmx_load_vmcs01(vcpu);
9035 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9037 struct vcpu_vmx *vmx = to_vmx(vcpu);
9040 vmx_destroy_pml_buffer(vmx);
9041 free_vpid(vmx->vpid);
9042 leave_guest_mode(vcpu);
9043 vmx_free_vcpu_nested(vcpu);
9044 free_loaded_vmcs(vmx->loaded_vmcs);
9045 kfree(vmx->guest_msrs);
9046 kvm_vcpu_uninit(vcpu);
9047 kmem_cache_free(kvm_vcpu_cache, vmx);
9050 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9053 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9057 return ERR_PTR(-ENOMEM);
9059 vmx->vpid = allocate_vpid();
9061 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9068 * If PML is turned on, failure on enabling PML just results in failure
9069 * of creating the vcpu, therefore we can simplify PML logic (by
9070 * avoiding dealing with cases, such as enabling PML partially on vcpus
9071 * for the guest, etc.
9074 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9079 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9080 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9083 if (!vmx->guest_msrs)
9086 vmx->loaded_vmcs = &vmx->vmcs01;
9087 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9088 vmx->loaded_vmcs->shadow_vmcs = NULL;
9089 if (!vmx->loaded_vmcs->vmcs)
9092 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9093 loaded_vmcs_init(vmx->loaded_vmcs);
9098 vmx_vcpu_load(&vmx->vcpu, cpu);
9099 vmx->vcpu.cpu = cpu;
9100 err = vmx_vcpu_setup(vmx);
9101 vmx_vcpu_put(&vmx->vcpu);
9105 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9106 err = alloc_apic_access_page(kvm);
9112 if (!kvm->arch.ept_identity_map_addr)
9113 kvm->arch.ept_identity_map_addr =
9114 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9115 err = init_rmode_identity_map(kvm);
9121 nested_vmx_setup_ctls_msrs(vmx);
9122 vmx->nested.vpid02 = allocate_vpid();
9125 vmx->nested.posted_intr_nv = -1;
9126 vmx->nested.current_vmptr = -1ull;
9127 vmx->nested.current_vmcs12 = NULL;
9129 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9134 free_vpid(vmx->nested.vpid02);
9135 free_loaded_vmcs(vmx->loaded_vmcs);
9137 kfree(vmx->guest_msrs);
9139 vmx_destroy_pml_buffer(vmx);
9141 kvm_vcpu_uninit(&vmx->vcpu);
9143 free_vpid(vmx->vpid);
9144 kmem_cache_free(kvm_vcpu_cache, vmx);
9145 return ERR_PTR(err);
9148 static void __init vmx_check_processor_compat(void *rtn)
9150 struct vmcs_config vmcs_conf;
9153 if (setup_vmcs_config(&vmcs_conf) < 0)
9155 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9156 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9157 smp_processor_id());
9162 static int get_ept_level(void)
9164 return VMX_EPT_DEFAULT_GAW + 1;
9167 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9172 /* For VT-d and EPT combination
9173 * 1. MMIO: always map as UC
9175 * a. VT-d without snooping control feature: can't guarantee the
9176 * result, try to trust guest.
9177 * b. VT-d with snooping control feature: snooping control feature of
9178 * VT-d engine can guarantee the cache correctness. Just set it
9179 * to WB to keep consistent with host. So the same as item 3.
9180 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9181 * consistent with host MTRR
9184 cache = MTRR_TYPE_UNCACHABLE;
9188 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9189 ipat = VMX_EPT_IPAT_BIT;
9190 cache = MTRR_TYPE_WRBACK;
9194 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9195 ipat = VMX_EPT_IPAT_BIT;
9196 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9197 cache = MTRR_TYPE_WRBACK;
9199 cache = MTRR_TYPE_UNCACHABLE;
9203 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9206 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9209 static int vmx_get_lpage_level(void)
9211 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9212 return PT_DIRECTORY_LEVEL;
9214 /* For shadow and EPT supported 1GB page */
9215 return PT_PDPE_LEVEL;
9218 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9221 * These bits in the secondary execution controls field
9222 * are dynamic, the others are mostly based on the hypervisor
9223 * architecture and the guest's CPUID. Do not touch the
9227 SECONDARY_EXEC_SHADOW_VMCS |
9228 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9229 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9231 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9233 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9234 (new_ctl & ~mask) | (cur_ctl & mask));
9237 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9239 struct kvm_cpuid_entry2 *best;
9240 struct vcpu_vmx *vmx = to_vmx(vcpu);
9241 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9243 if (vmx_rdtscp_supported()) {
9244 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9245 if (!rdtscp_enabled)
9246 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9250 vmx->nested.nested_vmx_secondary_ctls_high |=
9251 SECONDARY_EXEC_RDTSCP;
9253 vmx->nested.nested_vmx_secondary_ctls_high &=
9254 ~SECONDARY_EXEC_RDTSCP;
9258 /* Exposing INVPCID only when PCID is exposed */
9259 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9260 if (vmx_invpcid_supported() &&
9261 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9262 !guest_cpuid_has_pcid(vcpu))) {
9263 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9266 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9269 if (cpu_has_secondary_exec_ctrls())
9270 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9272 if (nested_vmx_allowed(vcpu))
9273 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9274 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9276 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9277 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9280 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9282 if (func == 1 && nested)
9283 entry->ecx |= bit(X86_FEATURE_VMX);
9286 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9287 struct x86_exception *fault)
9289 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9292 if (fault->error_code & PFERR_RSVD_MASK)
9293 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9295 exit_reason = EXIT_REASON_EPT_VIOLATION;
9296 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9297 vmcs12->guest_physical_address = fault->address;
9300 /* Callbacks for nested_ept_init_mmu_context: */
9302 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9304 /* return the page table to be shadowed - in our case, EPT12 */
9305 return get_vmcs12(vcpu)->ept_pointer;
9308 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9310 WARN_ON(mmu_is_nested(vcpu));
9311 kvm_init_shadow_ept_mmu(vcpu,
9312 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9313 VMX_EPT_EXECUTE_ONLY_BIT);
9314 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9315 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9316 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9318 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9321 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9323 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9326 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9329 bool inequality, bit;
9331 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9333 (error_code & vmcs12->page_fault_error_code_mask) !=
9334 vmcs12->page_fault_error_code_match;
9335 return inequality ^ bit;
9338 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9339 struct x86_exception *fault)
9341 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9343 WARN_ON(!is_guest_mode(vcpu));
9345 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9346 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9347 vmcs_read32(VM_EXIT_INTR_INFO),
9348 vmcs_readl(EXIT_QUALIFICATION));
9350 kvm_inject_page_fault(vcpu, fault);
9353 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9354 struct vmcs12 *vmcs12)
9356 struct vcpu_vmx *vmx = to_vmx(vcpu);
9357 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9359 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9360 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9361 vmcs12->apic_access_addr >> maxphyaddr)
9365 * Translate L1 physical address to host physical
9366 * address for vmcs02. Keep the page pinned, so this
9367 * physical address remains valid. We keep a reference
9368 * to it so we can release it later.
9370 if (vmx->nested.apic_access_page) /* shouldn't happen */
9371 nested_release_page(vmx->nested.apic_access_page);
9372 vmx->nested.apic_access_page =
9373 nested_get_page(vcpu, vmcs12->apic_access_addr);
9376 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9377 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9378 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9381 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9382 nested_release_page(vmx->nested.virtual_apic_page);
9383 vmx->nested.virtual_apic_page =
9384 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9387 * Failing the vm entry is _not_ what the processor does
9388 * but it's basically the only possibility we have.
9389 * We could still enter the guest if CR8 load exits are
9390 * enabled, CR8 store exits are enabled, and virtualize APIC
9391 * access is disabled; in this case the processor would never
9392 * use the TPR shadow and we could simply clear the bit from
9393 * the execution control. But such a configuration is useless,
9394 * so let's keep the code simple.
9396 if (!vmx->nested.virtual_apic_page)
9400 if (nested_cpu_has_posted_intr(vmcs12)) {
9401 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9402 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9405 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9406 kunmap(vmx->nested.pi_desc_page);
9407 nested_release_page(vmx->nested.pi_desc_page);
9409 vmx->nested.pi_desc_page =
9410 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9411 if (!vmx->nested.pi_desc_page)
9414 vmx->nested.pi_desc =
9415 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9416 if (!vmx->nested.pi_desc) {
9417 nested_release_page_clean(vmx->nested.pi_desc_page);
9420 vmx->nested.pi_desc =
9421 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9422 (unsigned long)(vmcs12->posted_intr_desc_addr &
9429 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9431 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9432 struct vcpu_vmx *vmx = to_vmx(vcpu);
9434 if (vcpu->arch.virtual_tsc_khz == 0)
9437 /* Make sure short timeouts reliably trigger an immediate vmexit.
9438 * hrtimer_start does not guarantee this. */
9439 if (preemption_timeout <= 1) {
9440 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9444 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9445 preemption_timeout *= 1000000;
9446 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9447 hrtimer_start(&vmx->nested.preemption_timer,
9448 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9451 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9452 struct vmcs12 *vmcs12)
9457 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9460 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9464 maxphyaddr = cpuid_maxphyaddr(vcpu);
9466 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9467 ((addr + PAGE_SIZE) >> maxphyaddr))
9474 * Merge L0's and L1's MSR bitmap, return false to indicate that
9475 * we do not use the hardware.
9477 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9478 struct vmcs12 *vmcs12)
9482 unsigned long *msr_bitmap_l1;
9483 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9485 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9486 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9489 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9494 msr_bitmap_l1 = (unsigned long *)kmap(page);
9495 if (!msr_bitmap_l1) {
9496 nested_release_page_clean(page);
9501 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9503 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9504 if (nested_cpu_has_apic_reg_virt(vmcs12))
9505 for (msr = 0x800; msr <= 0x8ff; msr++)
9506 nested_vmx_disable_intercept_for_msr(
9507 msr_bitmap_l1, msr_bitmap_l0,
9510 nested_vmx_disable_intercept_for_msr(
9511 msr_bitmap_l1, msr_bitmap_l0,
9512 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9513 MSR_TYPE_R | MSR_TYPE_W);
9515 if (nested_cpu_has_vid(vmcs12)) {
9516 nested_vmx_disable_intercept_for_msr(
9517 msr_bitmap_l1, msr_bitmap_l0,
9518 APIC_BASE_MSR + (APIC_EOI >> 4),
9520 nested_vmx_disable_intercept_for_msr(
9521 msr_bitmap_l1, msr_bitmap_l0,
9522 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9527 nested_release_page_clean(page);
9532 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9533 struct vmcs12 *vmcs12)
9535 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9536 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9537 !nested_cpu_has_vid(vmcs12) &&
9538 !nested_cpu_has_posted_intr(vmcs12))
9542 * If virtualize x2apic mode is enabled,
9543 * virtualize apic access must be disabled.
9545 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9546 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9550 * If virtual interrupt delivery is enabled,
9551 * we must exit on external interrupts.
9553 if (nested_cpu_has_vid(vmcs12) &&
9554 !nested_exit_on_intr(vcpu))
9558 * bits 15:8 should be zero in posted_intr_nv,
9559 * the descriptor address has been already checked
9560 * in nested_get_vmcs12_pages.
9562 if (nested_cpu_has_posted_intr(vmcs12) &&
9563 (!nested_cpu_has_vid(vmcs12) ||
9564 !nested_exit_intr_ack_set(vcpu) ||
9565 vmcs12->posted_intr_nv & 0xff00))
9568 /* tpr shadow is needed by all apicv features. */
9569 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9575 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9576 unsigned long count_field,
9577 unsigned long addr_field)
9582 if (vmcs12_read_any(vcpu, count_field, &count) ||
9583 vmcs12_read_any(vcpu, addr_field, &addr)) {
9589 maxphyaddr = cpuid_maxphyaddr(vcpu);
9590 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9591 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9592 pr_debug_ratelimited(
9593 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9594 addr_field, maxphyaddr, count, addr);
9600 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9601 struct vmcs12 *vmcs12)
9603 if (vmcs12->vm_exit_msr_load_count == 0 &&
9604 vmcs12->vm_exit_msr_store_count == 0 &&
9605 vmcs12->vm_entry_msr_load_count == 0)
9606 return 0; /* Fast path */
9607 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9608 VM_EXIT_MSR_LOAD_ADDR) ||
9609 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9610 VM_EXIT_MSR_STORE_ADDR) ||
9611 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9612 VM_ENTRY_MSR_LOAD_ADDR))
9617 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9618 struct vmx_msr_entry *e)
9620 /* x2APIC MSR accesses are not allowed */
9621 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9623 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9624 e->index == MSR_IA32_UCODE_REV)
9626 if (e->reserved != 0)
9631 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9632 struct vmx_msr_entry *e)
9634 if (e->index == MSR_FS_BASE ||
9635 e->index == MSR_GS_BASE ||
9636 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9637 nested_vmx_msr_check_common(vcpu, e))
9642 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9643 struct vmx_msr_entry *e)
9645 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9646 nested_vmx_msr_check_common(vcpu, e))
9652 * Load guest's/host's msr at nested entry/exit.
9653 * return 0 for success, entry index for failure.
9655 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9658 struct vmx_msr_entry e;
9659 struct msr_data msr;
9661 msr.host_initiated = false;
9662 for (i = 0; i < count; i++) {
9663 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9665 pr_debug_ratelimited(
9666 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9667 __func__, i, gpa + i * sizeof(e));
9670 if (nested_vmx_load_msr_check(vcpu, &e)) {
9671 pr_debug_ratelimited(
9672 "%s check failed (%u, 0x%x, 0x%x)\n",
9673 __func__, i, e.index, e.reserved);
9676 msr.index = e.index;
9678 if (kvm_set_msr(vcpu, &msr)) {
9679 pr_debug_ratelimited(
9680 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9681 __func__, i, e.index, e.value);
9690 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9693 struct vmx_msr_entry e;
9695 for (i = 0; i < count; i++) {
9696 struct msr_data msr_info;
9697 if (kvm_vcpu_read_guest(vcpu,
9698 gpa + i * sizeof(e),
9699 &e, 2 * sizeof(u32))) {
9700 pr_debug_ratelimited(
9701 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9702 __func__, i, gpa + i * sizeof(e));
9705 if (nested_vmx_store_msr_check(vcpu, &e)) {
9706 pr_debug_ratelimited(
9707 "%s check failed (%u, 0x%x, 0x%x)\n",
9708 __func__, i, e.index, e.reserved);
9711 msr_info.host_initiated = false;
9712 msr_info.index = e.index;
9713 if (kvm_get_msr(vcpu, &msr_info)) {
9714 pr_debug_ratelimited(
9715 "%s cannot read MSR (%u, 0x%x)\n",
9716 __func__, i, e.index);
9719 if (kvm_vcpu_write_guest(vcpu,
9720 gpa + i * sizeof(e) +
9721 offsetof(struct vmx_msr_entry, value),
9722 &msr_info.data, sizeof(msr_info.data))) {
9723 pr_debug_ratelimited(
9724 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9725 __func__, i, e.index, msr_info.data);
9733 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9734 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9735 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9736 * guest in a way that will both be appropriate to L1's requests, and our
9737 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9738 * function also has additional necessary side-effects, like setting various
9739 * vcpu->arch fields.
9741 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9743 struct vcpu_vmx *vmx = to_vmx(vcpu);
9746 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9747 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9748 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9749 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9750 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9751 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9752 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9753 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9754 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9755 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9756 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9757 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9758 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9759 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9760 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9761 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9762 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9763 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9764 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9765 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9766 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9767 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9768 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9769 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9770 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9771 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9772 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9773 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9774 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9775 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9776 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9777 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9778 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9779 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9780 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9781 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9783 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9784 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9785 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9787 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9788 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9790 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9791 vmcs12->vm_entry_intr_info_field);
9792 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9793 vmcs12->vm_entry_exception_error_code);
9794 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9795 vmcs12->vm_entry_instruction_len);
9796 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9797 vmcs12->guest_interruptibility_info);
9798 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9799 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9800 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9801 vmcs12->guest_pending_dbg_exceptions);
9802 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9803 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9805 if (nested_cpu_has_xsaves(vmcs12))
9806 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9807 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9809 exec_control = vmcs12->pin_based_vm_exec_control;
9811 /* Preemption timer setting is only taken from vmcs01. */
9812 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9813 exec_control |= vmcs_config.pin_based_exec_ctrl;
9814 if (vmx->hv_deadline_tsc == -1)
9815 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9817 /* Posted interrupts setting is only taken from vmcs12. */
9818 if (nested_cpu_has_posted_intr(vmcs12)) {
9820 * Note that we use L0's vector here and in
9821 * vmx_deliver_nested_posted_interrupt.
9823 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9824 vmx->nested.pi_pending = false;
9825 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9826 vmcs_write64(POSTED_INTR_DESC_ADDR,
9827 page_to_phys(vmx->nested.pi_desc_page) +
9828 (unsigned long)(vmcs12->posted_intr_desc_addr &
9831 exec_control &= ~PIN_BASED_POSTED_INTR;
9833 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9835 vmx->nested.preemption_timer_expired = false;
9836 if (nested_cpu_has_preemption_timer(vmcs12))
9837 vmx_start_preemption_timer(vcpu);
9840 * Whether page-faults are trapped is determined by a combination of
9841 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9842 * If enable_ept, L0 doesn't care about page faults and we should
9843 * set all of these to L1's desires. However, if !enable_ept, L0 does
9844 * care about (at least some) page faults, and because it is not easy
9845 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9846 * to exit on each and every L2 page fault. This is done by setting
9847 * MASK=MATCH=0 and (see below) EB.PF=1.
9848 * Note that below we don't need special code to set EB.PF beyond the
9849 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9850 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9851 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9853 * A problem with this approach (when !enable_ept) is that L1 may be
9854 * injected with more page faults than it asked for. This could have
9855 * caused problems, but in practice existing hypervisors don't care.
9856 * To fix this, we will need to emulate the PFEC checking (on the L1
9857 * page tables), using walk_addr(), when injecting PFs to L1.
9859 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9860 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9861 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9862 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9864 if (cpu_has_secondary_exec_ctrls()) {
9865 exec_control = vmx_secondary_exec_control(vmx);
9867 /* Take the following fields only from vmcs12 */
9868 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9869 SECONDARY_EXEC_RDTSCP |
9870 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9871 SECONDARY_EXEC_APIC_REGISTER_VIRT);
9872 if (nested_cpu_has(vmcs12,
9873 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9874 exec_control |= vmcs12->secondary_vm_exec_control;
9876 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9878 * If translation failed, no matter: This feature asks
9879 * to exit when accessing the given address, and if it
9880 * can never be accessed, this feature won't do
9883 if (!vmx->nested.apic_access_page)
9885 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9887 vmcs_write64(APIC_ACCESS_ADDR,
9888 page_to_phys(vmx->nested.apic_access_page));
9889 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9890 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9892 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9893 kvm_vcpu_reload_apic_access_page(vcpu);
9896 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9897 vmcs_write64(EOI_EXIT_BITMAP0,
9898 vmcs12->eoi_exit_bitmap0);
9899 vmcs_write64(EOI_EXIT_BITMAP1,
9900 vmcs12->eoi_exit_bitmap1);
9901 vmcs_write64(EOI_EXIT_BITMAP2,
9902 vmcs12->eoi_exit_bitmap2);
9903 vmcs_write64(EOI_EXIT_BITMAP3,
9904 vmcs12->eoi_exit_bitmap3);
9905 vmcs_write16(GUEST_INTR_STATUS,
9906 vmcs12->guest_intr_status);
9909 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9914 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9915 * Some constant fields are set here by vmx_set_constant_host_state().
9916 * Other fields are different per CPU, and will be set later when
9917 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9919 vmx_set_constant_host_state(vmx);
9922 * Set the MSR load/store lists to match L0's settings.
9924 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
9925 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
9926 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
9927 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
9928 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
9931 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9932 * entry, but only if the current (host) sp changed from the value
9933 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9934 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9935 * here we just force the write to happen on entry.
9939 exec_control = vmx_exec_control(vmx); /* L0's desires */
9940 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9941 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9942 exec_control &= ~CPU_BASED_TPR_SHADOW;
9943 exec_control |= vmcs12->cpu_based_vm_exec_control;
9945 if (exec_control & CPU_BASED_TPR_SHADOW) {
9946 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9947 page_to_phys(vmx->nested.virtual_apic_page));
9948 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9951 if (cpu_has_vmx_msr_bitmap() &&
9952 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9953 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9954 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
9956 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9959 * Merging of IO bitmap not currently supported.
9960 * Rather, exit every time.
9962 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9963 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9965 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9967 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9968 * bitwise-or of what L1 wants to trap for L2, and what we want to
9969 * trap. Note that CR0.TS also needs updating - we do this later.
9971 update_exception_bitmap(vcpu);
9972 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9973 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9975 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9976 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9977 * bits are further modified by vmx_set_efer() below.
9979 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9981 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9982 * emulated by vmx_set_efer(), below.
9984 vm_entry_controls_init(vmx,
9985 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9986 ~VM_ENTRY_IA32E_MODE) |
9987 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9989 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9990 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9991 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9992 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9993 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9996 set_cr4_guest_host_mask(vmx);
9998 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9999 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10001 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10002 vmcs_write64(TSC_OFFSET,
10003 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10005 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10006 if (kvm_has_tsc_control)
10007 decache_tsc_multiplier(vmx);
10011 * There is no direct mapping between vpid02 and vpid12, the
10012 * vpid02 is per-vCPU for L0 and reused while the value of
10013 * vpid12 is changed w/ one invvpid during nested vmentry.
10014 * The vpid12 is allocated by L1 for L2, so it will not
10015 * influence global bitmap(for vpid01 and vpid02 allocation)
10016 * even if spawn a lot of nested vCPUs.
10018 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10019 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10020 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10021 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10022 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10025 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10026 vmx_flush_tlb(vcpu);
10031 if (nested_cpu_has_ept(vmcs12)) {
10032 kvm_mmu_unload(vcpu);
10033 nested_ept_init_mmu_context(vcpu);
10036 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10037 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10038 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10039 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10041 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10042 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10043 vmx_set_efer(vcpu, vcpu->arch.efer);
10046 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10047 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10048 * The CR0_READ_SHADOW is what L2 should have expected to read given
10049 * the specifications by L1; It's not enough to take
10050 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10051 * have more bits than L1 expected.
10053 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10054 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10056 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10057 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10059 /* shadow page tables on either EPT or shadow page tables */
10060 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10061 kvm_mmu_reset_context(vcpu);
10064 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10067 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10070 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10071 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10072 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10073 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10076 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10077 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10081 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10082 * for running an L2 nested guest.
10084 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10086 struct vmcs12 *vmcs12;
10087 struct vcpu_vmx *vmx = to_vmx(vcpu);
10089 struct loaded_vmcs *vmcs02;
10093 if (!nested_vmx_check_permission(vcpu) ||
10094 !nested_vmx_check_vmcs12(vcpu))
10097 skip_emulated_instruction(vcpu);
10098 vmcs12 = get_vmcs12(vcpu);
10100 if (enable_shadow_vmcs)
10101 copy_shadow_to_vmcs12(vmx);
10104 * The nested entry process starts with enforcing various prerequisites
10105 * on vmcs12 as required by the Intel SDM, and act appropriately when
10106 * they fail: As the SDM explains, some conditions should cause the
10107 * instruction to fail, while others will cause the instruction to seem
10108 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10109 * To speed up the normal (success) code path, we should avoid checking
10110 * for misconfigurations which will anyway be caught by the processor
10111 * when using the merged vmcs02.
10113 if (vmcs12->launch_state == launch) {
10114 nested_vmx_failValid(vcpu,
10115 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10116 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10120 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10121 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10122 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10126 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10127 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10131 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10132 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10136 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10137 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10141 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10142 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10146 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10147 vmx->nested.nested_vmx_true_procbased_ctls_low,
10148 vmx->nested.nested_vmx_procbased_ctls_high) ||
10149 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10150 vmx->nested.nested_vmx_secondary_ctls_low,
10151 vmx->nested.nested_vmx_secondary_ctls_high) ||
10152 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10153 vmx->nested.nested_vmx_pinbased_ctls_low,
10154 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10155 !vmx_control_verify(vmcs12->vm_exit_controls,
10156 vmx->nested.nested_vmx_true_exit_ctls_low,
10157 vmx->nested.nested_vmx_exit_ctls_high) ||
10158 !vmx_control_verify(vmcs12->vm_entry_controls,
10159 vmx->nested.nested_vmx_true_entry_ctls_low,
10160 vmx->nested.nested_vmx_entry_ctls_high))
10162 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10166 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10167 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10168 nested_vmx_failValid(vcpu,
10169 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10173 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10174 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10175 nested_vmx_entry_failure(vcpu, vmcs12,
10176 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10179 if (vmcs12->vmcs_link_pointer != -1ull) {
10180 nested_vmx_entry_failure(vcpu, vmcs12,
10181 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10186 * If the load IA32_EFER VM-entry control is 1, the following checks
10187 * are performed on the field for the IA32_EFER MSR:
10188 * - Bits reserved in the IA32_EFER MSR must be 0.
10189 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10190 * the IA-32e mode guest VM-exit control. It must also be identical
10191 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10194 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10195 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10196 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10197 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10198 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10199 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10200 nested_vmx_entry_failure(vcpu, vmcs12,
10201 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10207 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10208 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10209 * the values of the LMA and LME bits in the field must each be that of
10210 * the host address-space size VM-exit control.
10212 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10213 ia32e = (vmcs12->vm_exit_controls &
10214 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10215 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10216 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10217 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10218 nested_vmx_entry_failure(vcpu, vmcs12,
10219 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10225 * We're finally done with prerequisite checking, and can start with
10226 * the nested entry.
10229 vmcs02 = nested_get_current_vmcs02(vmx);
10233 enter_guest_mode(vcpu);
10235 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10236 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10239 vmx->loaded_vmcs = vmcs02;
10240 vmx_vcpu_put(vcpu);
10241 vmx_vcpu_load(vcpu, cpu);
10245 vmx_segment_cache_clear(vmx);
10247 prepare_vmcs02(vcpu, vmcs12);
10249 msr_entry_idx = nested_vmx_load_msr(vcpu,
10250 vmcs12->vm_entry_msr_load_addr,
10251 vmcs12->vm_entry_msr_load_count);
10252 if (msr_entry_idx) {
10253 leave_guest_mode(vcpu);
10254 vmx_load_vmcs01(vcpu);
10255 nested_vmx_entry_failure(vcpu, vmcs12,
10256 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10260 vmcs12->launch_state = 1;
10262 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10263 return kvm_vcpu_halt(vcpu);
10265 vmx->nested.nested_run_pending = 1;
10268 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10269 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10270 * returned as far as L1 is concerned. It will only return (and set
10271 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10277 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10278 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10279 * This function returns the new value we should put in vmcs12.guest_cr0.
10280 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10281 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10282 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10283 * didn't trap the bit, because if L1 did, so would L0).
10284 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10285 * been modified by L2, and L1 knows it. So just leave the old value of
10286 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10287 * isn't relevant, because if L0 traps this bit it can set it to anything.
10288 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10289 * changed these bits, and therefore they need to be updated, but L0
10290 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10291 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10293 static inline unsigned long
10294 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10297 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10298 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10299 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10300 vcpu->arch.cr0_guest_owned_bits));
10303 static inline unsigned long
10304 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10307 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10308 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10309 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10310 vcpu->arch.cr4_guest_owned_bits));
10313 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10314 struct vmcs12 *vmcs12)
10319 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10320 nr = vcpu->arch.exception.nr;
10321 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10323 if (kvm_exception_is_soft(nr)) {
10324 vmcs12->vm_exit_instruction_len =
10325 vcpu->arch.event_exit_inst_len;
10326 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10328 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10330 if (vcpu->arch.exception.has_error_code) {
10331 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10332 vmcs12->idt_vectoring_error_code =
10333 vcpu->arch.exception.error_code;
10336 vmcs12->idt_vectoring_info_field = idt_vectoring;
10337 } else if (vcpu->arch.nmi_injected) {
10338 vmcs12->idt_vectoring_info_field =
10339 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10340 } else if (vcpu->arch.interrupt.pending) {
10341 nr = vcpu->arch.interrupt.nr;
10342 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10344 if (vcpu->arch.interrupt.soft) {
10345 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10346 vmcs12->vm_entry_instruction_len =
10347 vcpu->arch.event_exit_inst_len;
10349 idt_vectoring |= INTR_TYPE_EXT_INTR;
10351 vmcs12->idt_vectoring_info_field = idt_vectoring;
10355 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10357 struct vcpu_vmx *vmx = to_vmx(vcpu);
10359 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10360 vmx->nested.preemption_timer_expired) {
10361 if (vmx->nested.nested_run_pending)
10363 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10367 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10368 if (vmx->nested.nested_run_pending ||
10369 vcpu->arch.interrupt.pending)
10371 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10372 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10373 INTR_INFO_VALID_MASK, 0);
10375 * The NMI-triggered VM exit counts as injection:
10376 * clear this one and block further NMIs.
10378 vcpu->arch.nmi_pending = 0;
10379 vmx_set_nmi_mask(vcpu, true);
10383 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10384 nested_exit_on_intr(vcpu)) {
10385 if (vmx->nested.nested_run_pending)
10387 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10391 return vmx_complete_nested_posted_interrupt(vcpu);
10394 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10396 ktime_t remaining =
10397 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10400 if (ktime_to_ns(remaining) <= 0)
10403 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10404 do_div(value, 1000000);
10405 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10409 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10410 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10411 * and this function updates it to reflect the changes to the guest state while
10412 * L2 was running (and perhaps made some exits which were handled directly by L0
10413 * without going back to L1), and to reflect the exit reason.
10414 * Note that we do not have to copy here all VMCS fields, just those that
10415 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10416 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10417 * which already writes to vmcs12 directly.
10419 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10420 u32 exit_reason, u32 exit_intr_info,
10421 unsigned long exit_qualification)
10423 /* update guest state fields: */
10424 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10425 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10427 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10428 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10429 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10431 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10432 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10433 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10434 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10435 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10436 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10437 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10438 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10439 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10440 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10441 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10442 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10443 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10444 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10445 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10446 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10447 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10448 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10449 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10450 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10451 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10452 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10453 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10454 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10455 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10456 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10457 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10458 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10459 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10460 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10461 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10462 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10463 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10464 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10465 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10466 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10468 vmcs12->guest_interruptibility_info =
10469 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10470 vmcs12->guest_pending_dbg_exceptions =
10471 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10472 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10473 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10475 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10477 if (nested_cpu_has_preemption_timer(vmcs12)) {
10478 if (vmcs12->vm_exit_controls &
10479 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10480 vmcs12->vmx_preemption_timer_value =
10481 vmx_get_preemption_timer_value(vcpu);
10482 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10486 * In some cases (usually, nested EPT), L2 is allowed to change its
10487 * own CR3 without exiting. If it has changed it, we must keep it.
10488 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10489 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10491 * Additionally, restore L2's PDPTR to vmcs12.
10494 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10495 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10496 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10497 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10498 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10501 if (nested_cpu_has_ept(vmcs12))
10502 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10504 if (nested_cpu_has_vid(vmcs12))
10505 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10507 vmcs12->vm_entry_controls =
10508 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10509 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10511 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10512 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10513 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10516 /* TODO: These cannot have changed unless we have MSR bitmaps and
10517 * the relevant bit asks not to trap the change */
10518 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10519 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10520 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10521 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10522 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10523 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10524 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10525 if (kvm_mpx_supported())
10526 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10527 if (nested_cpu_has_xsaves(vmcs12))
10528 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10530 /* update exit information fields: */
10532 vmcs12->vm_exit_reason = exit_reason;
10533 vmcs12->exit_qualification = exit_qualification;
10535 vmcs12->vm_exit_intr_info = exit_intr_info;
10536 if ((vmcs12->vm_exit_intr_info &
10537 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10538 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10539 vmcs12->vm_exit_intr_error_code =
10540 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10541 vmcs12->idt_vectoring_info_field = 0;
10542 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10543 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10545 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10546 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10547 * instead of reading the real value. */
10548 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10551 * Transfer the event that L0 or L1 may wanted to inject into
10552 * L2 to IDT_VECTORING_INFO_FIELD.
10554 vmcs12_save_pending_event(vcpu, vmcs12);
10558 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10559 * preserved above and would only end up incorrectly in L1.
10561 vcpu->arch.nmi_injected = false;
10562 kvm_clear_exception_queue(vcpu);
10563 kvm_clear_interrupt_queue(vcpu);
10567 * A part of what we need to when the nested L2 guest exits and we want to
10568 * run its L1 parent, is to reset L1's guest state to the host state specified
10570 * This function is to be called not only on normal nested exit, but also on
10571 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10572 * Failures During or After Loading Guest State").
10573 * This function should be called when the active VMCS is L1's (vmcs01).
10575 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10576 struct vmcs12 *vmcs12)
10578 struct kvm_segment seg;
10580 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10581 vcpu->arch.efer = vmcs12->host_ia32_efer;
10582 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10583 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10585 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10586 vmx_set_efer(vcpu, vcpu->arch.efer);
10588 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10589 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10590 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10592 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10593 * actually changed, because it depends on the current state of
10594 * fpu_active (which may have changed).
10595 * Note that vmx_set_cr0 refers to efer set above.
10597 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10599 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10600 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10601 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10603 update_exception_bitmap(vcpu);
10604 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10605 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10608 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10609 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10611 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10612 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10614 nested_ept_uninit_mmu_context(vcpu);
10616 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10617 kvm_mmu_reset_context(vcpu);
10620 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10624 * Trivially support vpid by letting L2s share their parent
10625 * L1's vpid. TODO: move to a more elaborate solution, giving
10626 * each L2 its own vpid and exposing the vpid feature to L1.
10628 vmx_flush_tlb(vcpu);
10632 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10633 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10634 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10635 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10636 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10638 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10639 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10640 vmcs_write64(GUEST_BNDCFGS, 0);
10642 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10643 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10644 vcpu->arch.pat = vmcs12->host_ia32_pat;
10646 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10647 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10648 vmcs12->host_ia32_perf_global_ctrl);
10650 /* Set L1 segment info according to Intel SDM
10651 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10652 seg = (struct kvm_segment) {
10654 .limit = 0xFFFFFFFF,
10655 .selector = vmcs12->host_cs_selector,
10661 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10665 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10666 seg = (struct kvm_segment) {
10668 .limit = 0xFFFFFFFF,
10675 seg.selector = vmcs12->host_ds_selector;
10676 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10677 seg.selector = vmcs12->host_es_selector;
10678 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10679 seg.selector = vmcs12->host_ss_selector;
10680 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10681 seg.selector = vmcs12->host_fs_selector;
10682 seg.base = vmcs12->host_fs_base;
10683 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10684 seg.selector = vmcs12->host_gs_selector;
10685 seg.base = vmcs12->host_gs_base;
10686 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10687 seg = (struct kvm_segment) {
10688 .base = vmcs12->host_tr_base,
10690 .selector = vmcs12->host_tr_selector,
10694 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10696 kvm_set_dr(vcpu, 7, 0x400);
10697 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10699 if (cpu_has_vmx_msr_bitmap())
10700 vmx_set_msr_bitmap(vcpu);
10702 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10703 vmcs12->vm_exit_msr_load_count))
10704 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10708 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10709 * and modify vmcs12 to make it see what it would expect to see there if
10710 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10712 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10713 u32 exit_intr_info,
10714 unsigned long exit_qualification)
10716 struct vcpu_vmx *vmx = to_vmx(vcpu);
10717 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10718 u32 vm_inst_error = 0;
10720 /* trying to cancel vmlaunch/vmresume is a bug */
10721 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10723 leave_guest_mode(vcpu);
10724 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10725 exit_qualification);
10727 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10728 vmcs12->vm_exit_msr_store_count))
10729 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10731 if (unlikely(vmx->fail))
10732 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10734 vmx_load_vmcs01(vcpu);
10736 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10737 && nested_exit_intr_ack_set(vcpu)) {
10738 int irq = kvm_cpu_get_interrupt(vcpu);
10740 vmcs12->vm_exit_intr_info = irq |
10741 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10744 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10745 vmcs12->exit_qualification,
10746 vmcs12->idt_vectoring_info_field,
10747 vmcs12->vm_exit_intr_info,
10748 vmcs12->vm_exit_intr_error_code,
10751 vm_entry_controls_reset_shadow(vmx);
10752 vm_exit_controls_reset_shadow(vmx);
10753 vmx_segment_cache_clear(vmx);
10755 /* if no vmcs02 cache requested, remove the one we used */
10756 if (VMCS02_POOL_SIZE == 0)
10757 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10759 load_vmcs12_host_state(vcpu, vmcs12);
10761 /* Update any VMCS fields that might have changed while L2 ran */
10762 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10763 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10764 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10765 if (vmx->hv_deadline_tsc == -1)
10766 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10767 PIN_BASED_VMX_PREEMPTION_TIMER);
10769 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10770 PIN_BASED_VMX_PREEMPTION_TIMER);
10771 if (kvm_has_tsc_control)
10772 decache_tsc_multiplier(vmx);
10774 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10775 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10776 vmx_set_virtual_x2apic_mode(vcpu,
10777 vcpu->arch.apic_base & X2APIC_ENABLE);
10780 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10783 /* Unpin physical memory we referred to in vmcs02 */
10784 if (vmx->nested.apic_access_page) {
10785 nested_release_page(vmx->nested.apic_access_page);
10786 vmx->nested.apic_access_page = NULL;
10788 if (vmx->nested.virtual_apic_page) {
10789 nested_release_page(vmx->nested.virtual_apic_page);
10790 vmx->nested.virtual_apic_page = NULL;
10792 if (vmx->nested.pi_desc_page) {
10793 kunmap(vmx->nested.pi_desc_page);
10794 nested_release_page(vmx->nested.pi_desc_page);
10795 vmx->nested.pi_desc_page = NULL;
10796 vmx->nested.pi_desc = NULL;
10800 * We are now running in L2, mmu_notifier will force to reload the
10801 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10803 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
10806 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10807 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10808 * success or failure flag accordingly.
10810 if (unlikely(vmx->fail)) {
10812 nested_vmx_failValid(vcpu, vm_inst_error);
10814 nested_vmx_succeed(vcpu);
10815 if (enable_shadow_vmcs)
10816 vmx->nested.sync_shadow_vmcs = true;
10818 /* in case we halted in L2 */
10819 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10823 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10825 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10827 if (is_guest_mode(vcpu))
10828 nested_vmx_vmexit(vcpu, -1, 0, 0);
10829 free_nested(to_vmx(vcpu));
10833 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10834 * 23.7 "VM-entry failures during or after loading guest state" (this also
10835 * lists the acceptable exit-reason and exit-qualification parameters).
10836 * It should only be called before L2 actually succeeded to run, and when
10837 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10839 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10840 struct vmcs12 *vmcs12,
10841 u32 reason, unsigned long qualification)
10843 load_vmcs12_host_state(vcpu, vmcs12);
10844 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10845 vmcs12->exit_qualification = qualification;
10846 nested_vmx_succeed(vcpu);
10847 if (enable_shadow_vmcs)
10848 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10851 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10852 struct x86_instruction_info *info,
10853 enum x86_intercept_stage stage)
10855 return X86EMUL_CONTINUE;
10858 #ifdef CONFIG_X86_64
10859 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10860 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10861 u64 divisor, u64 *result)
10863 u64 low = a << shift, high = a >> (64 - shift);
10865 /* To avoid the overflow on divq */
10866 if (high >= divisor)
10869 /* Low hold the result, high hold rem which is discarded */
10870 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10871 "rm" (divisor), "0" (low), "1" (high));
10877 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10879 struct vcpu_vmx *vmx = to_vmx(vcpu);
10880 u64 tscl = rdtsc();
10881 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10882 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10884 /* Convert to host delta tsc if tsc scaling is enabled */
10885 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10886 u64_shl_div_u64(delta_tsc,
10887 kvm_tsc_scaling_ratio_frac_bits,
10888 vcpu->arch.tsc_scaling_ratio,
10893 * If the delta tsc can't fit in the 32 bit after the multi shift,
10894 * we can't use the preemption timer.
10895 * It's possible that it fits on later vmentries, but checking
10896 * on every vmentry is costly so we just use an hrtimer.
10898 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10901 vmx->hv_deadline_tsc = tscl + delta_tsc;
10902 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10903 PIN_BASED_VMX_PREEMPTION_TIMER);
10907 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10909 struct vcpu_vmx *vmx = to_vmx(vcpu);
10910 vmx->hv_deadline_tsc = -1;
10911 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10912 PIN_BASED_VMX_PREEMPTION_TIMER);
10916 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10919 shrink_ple_window(vcpu);
10922 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10923 struct kvm_memory_slot *slot)
10925 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10926 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10929 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10930 struct kvm_memory_slot *slot)
10932 kvm_mmu_slot_set_dirty(kvm, slot);
10935 static void vmx_flush_log_dirty(struct kvm *kvm)
10937 kvm_flush_pml_buffers(kvm);
10940 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10941 struct kvm_memory_slot *memslot,
10942 gfn_t offset, unsigned long mask)
10944 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10948 * This routine does the following things for vCPU which is going
10949 * to be blocked if VT-d PI is enabled.
10950 * - Store the vCPU to the wakeup list, so when interrupts happen
10951 * we can find the right vCPU to wake up.
10952 * - Change the Posted-interrupt descriptor as below:
10953 * 'NDST' <-- vcpu->pre_pcpu
10954 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10955 * - If 'ON' is set during this process, which means at least one
10956 * interrupt is posted for this vCPU, we cannot block it, in
10957 * this case, return 1, otherwise, return 0.
10960 static int pi_pre_block(struct kvm_vcpu *vcpu)
10962 unsigned long flags;
10964 struct pi_desc old, new;
10965 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10967 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10968 !irq_remapping_cap(IRQ_POSTING_CAP) ||
10969 !kvm_vcpu_apicv_active(vcpu))
10972 vcpu->pre_pcpu = vcpu->cpu;
10973 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10974 vcpu->pre_pcpu), flags);
10975 list_add_tail(&vcpu->blocked_vcpu_list,
10976 &per_cpu(blocked_vcpu_on_cpu,
10978 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10979 vcpu->pre_pcpu), flags);
10982 old.control = new.control = pi_desc->control;
10985 * We should not block the vCPU if
10986 * an interrupt is posted for it.
10988 if (pi_test_on(pi_desc) == 1) {
10989 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10990 vcpu->pre_pcpu), flags);
10991 list_del(&vcpu->blocked_vcpu_list);
10992 spin_unlock_irqrestore(
10993 &per_cpu(blocked_vcpu_on_cpu_lock,
10994 vcpu->pre_pcpu), flags);
10995 vcpu->pre_pcpu = -1;
11000 WARN((pi_desc->sn == 1),
11001 "Warning: SN field of posted-interrupts "
11002 "is set before blocking\n");
11005 * Since vCPU can be preempted during this process,
11006 * vcpu->cpu could be different with pre_pcpu, we
11007 * need to set pre_pcpu as the destination of wakeup
11008 * notification event, then we can find the right vCPU
11009 * to wakeup in wakeup handler if interrupts happen
11010 * when the vCPU is in blocked state.
11012 dest = cpu_physical_id(vcpu->pre_pcpu);
11014 if (x2apic_enabled())
11017 new.ndst = (dest << 8) & 0xFF00;
11019 /* set 'NV' to 'wakeup vector' */
11020 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11021 } while (cmpxchg(&pi_desc->control, old.control,
11022 new.control) != old.control);
11027 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11029 if (pi_pre_block(vcpu))
11032 if (kvm_lapic_hv_timer_in_use(vcpu))
11033 kvm_lapic_switch_to_sw_timer(vcpu);
11038 static void pi_post_block(struct kvm_vcpu *vcpu)
11040 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11041 struct pi_desc old, new;
11043 unsigned long flags;
11045 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11046 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11047 !kvm_vcpu_apicv_active(vcpu))
11051 old.control = new.control = pi_desc->control;
11053 dest = cpu_physical_id(vcpu->cpu);
11055 if (x2apic_enabled())
11058 new.ndst = (dest << 8) & 0xFF00;
11060 /* Allow posting non-urgent interrupts */
11063 /* set 'NV' to 'notification vector' */
11064 new.nv = POSTED_INTR_VECTOR;
11065 } while (cmpxchg(&pi_desc->control, old.control,
11066 new.control) != old.control);
11068 if(vcpu->pre_pcpu != -1) {
11070 &per_cpu(blocked_vcpu_on_cpu_lock,
11071 vcpu->pre_pcpu), flags);
11072 list_del(&vcpu->blocked_vcpu_list);
11073 spin_unlock_irqrestore(
11074 &per_cpu(blocked_vcpu_on_cpu_lock,
11075 vcpu->pre_pcpu), flags);
11076 vcpu->pre_pcpu = -1;
11080 static void vmx_post_block(struct kvm_vcpu *vcpu)
11082 if (kvm_x86_ops->set_hv_timer)
11083 kvm_lapic_switch_to_hv_timer(vcpu);
11085 pi_post_block(vcpu);
11089 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11092 * @host_irq: host irq of the interrupt
11093 * @guest_irq: gsi of the interrupt
11094 * @set: set or unset PI
11095 * returns 0 on success, < 0 on failure
11097 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11098 uint32_t guest_irq, bool set)
11100 struct kvm_kernel_irq_routing_entry *e;
11101 struct kvm_irq_routing_table *irq_rt;
11102 struct kvm_lapic_irq irq;
11103 struct kvm_vcpu *vcpu;
11104 struct vcpu_data vcpu_info;
11105 int idx, ret = -EINVAL;
11107 if (!kvm_arch_has_assigned_device(kvm) ||
11108 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11109 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11112 idx = srcu_read_lock(&kvm->irq_srcu);
11113 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11114 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11116 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11117 if (e->type != KVM_IRQ_ROUTING_MSI)
11120 * VT-d PI cannot support posting multicast/broadcast
11121 * interrupts to a vCPU, we still use interrupt remapping
11122 * for these kind of interrupts.
11124 * For lowest-priority interrupts, we only support
11125 * those with single CPU as the destination, e.g. user
11126 * configures the interrupts via /proc/irq or uses
11127 * irqbalance to make the interrupts single-CPU.
11129 * We will support full lowest-priority interrupt later.
11132 kvm_set_msi_irq(kvm, e, &irq);
11133 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11135 * Make sure the IRTE is in remapped mode if
11136 * we don't handle it in posted mode.
11138 ret = irq_set_vcpu_affinity(host_irq, NULL);
11141 "failed to back to remapped mode, irq: %u\n",
11149 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11150 vcpu_info.vector = irq.vector;
11152 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11153 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11156 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11158 /* suppress notification event before unposting */
11159 pi_set_sn(vcpu_to_pi_desc(vcpu));
11160 ret = irq_set_vcpu_affinity(host_irq, NULL);
11161 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11165 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11173 srcu_read_unlock(&kvm->irq_srcu, idx);
11177 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11179 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11180 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11181 FEATURE_CONTROL_LMCE;
11183 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11184 ~FEATURE_CONTROL_LMCE;
11187 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11188 .cpu_has_kvm_support = cpu_has_kvm_support,
11189 .disabled_by_bios = vmx_disabled_by_bios,
11190 .hardware_setup = hardware_setup,
11191 .hardware_unsetup = hardware_unsetup,
11192 .check_processor_compatibility = vmx_check_processor_compat,
11193 .hardware_enable = hardware_enable,
11194 .hardware_disable = hardware_disable,
11195 .cpu_has_accelerated_tpr = report_flexpriority,
11196 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11198 .vcpu_create = vmx_create_vcpu,
11199 .vcpu_free = vmx_free_vcpu,
11200 .vcpu_reset = vmx_vcpu_reset,
11202 .prepare_guest_switch = vmx_save_host_state,
11203 .vcpu_load = vmx_vcpu_load,
11204 .vcpu_put = vmx_vcpu_put,
11206 .update_bp_intercept = update_exception_bitmap,
11207 .get_msr = vmx_get_msr,
11208 .set_msr = vmx_set_msr,
11209 .get_segment_base = vmx_get_segment_base,
11210 .get_segment = vmx_get_segment,
11211 .set_segment = vmx_set_segment,
11212 .get_cpl = vmx_get_cpl,
11213 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11214 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11215 .decache_cr3 = vmx_decache_cr3,
11216 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11217 .set_cr0 = vmx_set_cr0,
11218 .set_cr3 = vmx_set_cr3,
11219 .set_cr4 = vmx_set_cr4,
11220 .set_efer = vmx_set_efer,
11221 .get_idt = vmx_get_idt,
11222 .set_idt = vmx_set_idt,
11223 .get_gdt = vmx_get_gdt,
11224 .set_gdt = vmx_set_gdt,
11225 .get_dr6 = vmx_get_dr6,
11226 .set_dr6 = vmx_set_dr6,
11227 .set_dr7 = vmx_set_dr7,
11228 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11229 .cache_reg = vmx_cache_reg,
11230 .get_rflags = vmx_get_rflags,
11231 .set_rflags = vmx_set_rflags,
11233 .get_pkru = vmx_get_pkru,
11235 .fpu_activate = vmx_fpu_activate,
11236 .fpu_deactivate = vmx_fpu_deactivate,
11238 .tlb_flush = vmx_flush_tlb,
11240 .run = vmx_vcpu_run,
11241 .handle_exit = vmx_handle_exit,
11242 .skip_emulated_instruction = skip_emulated_instruction,
11243 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11244 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11245 .patch_hypercall = vmx_patch_hypercall,
11246 .set_irq = vmx_inject_irq,
11247 .set_nmi = vmx_inject_nmi,
11248 .queue_exception = vmx_queue_exception,
11249 .cancel_injection = vmx_cancel_injection,
11250 .interrupt_allowed = vmx_interrupt_allowed,
11251 .nmi_allowed = vmx_nmi_allowed,
11252 .get_nmi_mask = vmx_get_nmi_mask,
11253 .set_nmi_mask = vmx_set_nmi_mask,
11254 .enable_nmi_window = enable_nmi_window,
11255 .enable_irq_window = enable_irq_window,
11256 .update_cr8_intercept = update_cr8_intercept,
11257 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11258 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11259 .get_enable_apicv = vmx_get_enable_apicv,
11260 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11261 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11262 .hwapic_irr_update = vmx_hwapic_irr_update,
11263 .hwapic_isr_update = vmx_hwapic_isr_update,
11264 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11265 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11267 .set_tss_addr = vmx_set_tss_addr,
11268 .get_tdp_level = get_ept_level,
11269 .get_mt_mask = vmx_get_mt_mask,
11271 .get_exit_info = vmx_get_exit_info,
11273 .get_lpage_level = vmx_get_lpage_level,
11275 .cpuid_update = vmx_cpuid_update,
11277 .rdtscp_supported = vmx_rdtscp_supported,
11278 .invpcid_supported = vmx_invpcid_supported,
11280 .set_supported_cpuid = vmx_set_supported_cpuid,
11282 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11284 .write_tsc_offset = vmx_write_tsc_offset,
11286 .set_tdp_cr3 = vmx_set_cr3,
11288 .check_intercept = vmx_check_intercept,
11289 .handle_external_intr = vmx_handle_external_intr,
11290 .mpx_supported = vmx_mpx_supported,
11291 .xsaves_supported = vmx_xsaves_supported,
11293 .check_nested_events = vmx_check_nested_events,
11295 .sched_in = vmx_sched_in,
11297 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11298 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11299 .flush_log_dirty = vmx_flush_log_dirty,
11300 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11302 .pre_block = vmx_pre_block,
11303 .post_block = vmx_post_block,
11305 .pmu_ops = &intel_pmu_ops,
11307 .update_pi_irte = vmx_update_pi_irte,
11309 #ifdef CONFIG_X86_64
11310 .set_hv_timer = vmx_set_hv_timer,
11311 .cancel_hv_timer = vmx_cancel_hv_timer,
11314 .setup_mce = vmx_setup_mce,
11317 static int __init vmx_init(void)
11319 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11320 __alignof__(struct vcpu_vmx), THIS_MODULE);
11324 #ifdef CONFIG_KEXEC_CORE
11325 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11326 crash_vmclear_local_loaded_vmcss);
11332 static void __exit vmx_exit(void)
11334 #ifdef CONFIG_KEXEC_CORE
11335 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11342 module_init(vmx_init)
11343 module_exit(vmx_exit)