arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 137  * ple_gap:    upper bound on the amount of time between two successive
 138  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 139  *             According to test, this time is usually smaller than 128 cycles.
 140  * ple_window: upper bound on the amount of time a guest is allowed to execute
 141  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 142  *             less than 2^12 cycles
 143  * Time is measured based on a counter that runs at the same rate as the TSC,
 144  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 145  */
 146 #define KVM_VMX_DEFAULT_PLE_GAP           128
 147 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 151                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 152
 153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 154 module_param(ple_gap, int, S_IRUGO);
 155
 156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 157 module_param(ple_window, int, S_IRUGO);
 158
 159 /* Default doubles per-vcpu window every exit. */
 160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 161 module_param(ple_window_grow, int, S_IRUGO);
 162
 163 /* Default resets per-vcpu window every exit to ple_window. */
 164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 165 module_param(ple_window_shrink, int, S_IRUGO);
 166
 167 /* Default is to compute the maximum so we can never overflow. */
 168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 169 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 170 module_param(ple_window_max, int, S_IRUGO);
 171
 172 extern const ulong vmx_return;
 173
 174 #define NR_AUTOLOAD_MSRS 8
 175 #define VMCS02_POOL_SIZE 1
 176
 177 struct vmcs {
 178         u32 revision_id;
 179         u32 abort;
 180         char data[0];
 181 };
 182
 183 /*
 184  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 185  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 186  * loaded on this CPU (so we can clear them if the CPU goes down).
 187  */
 188 struct loaded_vmcs {
 189         struct vmcs *vmcs;
 190         struct vmcs *shadow_vmcs;
 191         int cpu;
 192         int launched;
 193         struct list_head loaded_vmcss_on_cpu_link;
 194 };
 195
 196 struct shared_msr_entry {
 197         unsigned index;
 198         u64 data;
 199         u64 mask;
 200 };
 201
 202 /*
 203  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 204  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 205  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 206  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 207  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 208  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 209  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 210  * underlying hardware which will be used to run L2.
 211  * This structure is packed to ensure that its layout is identical across
 212  * machines (necessary for live migration).
 213  * If there are changes in this struct, VMCS12_REVISION must be changed.
 214  */
 215 typedef u64 natural_width;
 216 struct __packed vmcs12 {
 217         /* According to the Intel spec, a VMCS region must start with the
 218          * following two fields. Then follow implementation-specific data.
 219          */
 220         u32 revision_id;
 221         u32 abort;
 222
 223         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 224         u32 padding[7]; /* room for future expansion */
 225
 226         u64 io_bitmap_a;
 227         u64 io_bitmap_b;
 228         u64 msr_bitmap;
 229         u64 vm_exit_msr_store_addr;
 230         u64 vm_exit_msr_load_addr;
 231         u64 vm_entry_msr_load_addr;
 232         u64 tsc_offset;
 233         u64 virtual_apic_page_addr;
 234         u64 apic_access_addr;
 235         u64 posted_intr_desc_addr;
 236         u64 ept_pointer;
 237         u64 eoi_exit_bitmap0;
 238         u64 eoi_exit_bitmap1;
 239         u64 eoi_exit_bitmap2;
 240         u64 eoi_exit_bitmap3;
 241         u64 xss_exit_bitmap;
 242         u64 guest_physical_address;
 243         u64 vmcs_link_pointer;
 244         u64 guest_ia32_debugctl;
 245         u64 guest_ia32_pat;
 246         u64 guest_ia32_efer;
 247         u64 guest_ia32_perf_global_ctrl;
 248         u64 guest_pdptr0;
 249         u64 guest_pdptr1;
 250         u64 guest_pdptr2;
 251         u64 guest_pdptr3;
 252         u64 guest_bndcfgs;
 253         u64 host_ia32_pat;
 254         u64 host_ia32_efer;
 255         u64 host_ia32_perf_global_ctrl;
 256         u64 padding64[8]; /* room for future expansion */
 257         /*
 258          * To allow migration of L1 (complete with its L2 guests) between
 259          * machines of different natural widths (32 or 64 bit), we cannot have
 260          * unsigned long fields with no explict size. We use u64 (aliased
 261          * natural_width) instead. Luckily, x86 is little-endian.
 262          */
 263         natural_width cr0_guest_host_mask;
 264         natural_width cr4_guest_host_mask;
 265         natural_width cr0_read_shadow;
 266         natural_width cr4_read_shadow;
 267         natural_width cr3_target_value0;
 268         natural_width cr3_target_value1;
 269         natural_width cr3_target_value2;
 270         natural_width cr3_target_value3;
 271         natural_width exit_qualification;
 272         natural_width guest_linear_address;
 273         natural_width guest_cr0;
 274         natural_width guest_cr3;
 275         natural_width guest_cr4;
 276         natural_width guest_es_base;
 277         natural_width guest_cs_base;
 278         natural_width guest_ss_base;
 279         natural_width guest_ds_base;
 280         natural_width guest_fs_base;
 281         natural_width guest_gs_base;
 282         natural_width guest_ldtr_base;
 283         natural_width guest_tr_base;
 284         natural_width guest_gdtr_base;
 285         natural_width guest_idtr_base;
 286         natural_width guest_dr7;
 287         natural_width guest_rsp;
 288         natural_width guest_rip;
 289         natural_width guest_rflags;
 290         natural_width guest_pending_dbg_exceptions;
 291         natural_width guest_sysenter_esp;
 292         natural_width guest_sysenter_eip;
 293         natural_width host_cr0;
 294         natural_width host_cr3;
 295         natural_width host_cr4;
 296         natural_width host_fs_base;
 297         natural_width host_gs_base;
 298         natural_width host_tr_base;
 299         natural_width host_gdtr_base;
 300         natural_width host_idtr_base;
 301         natural_width host_ia32_sysenter_esp;
 302         natural_width host_ia32_sysenter_eip;
 303         natural_width host_rsp;
 304         natural_width host_rip;
 305         natural_width paddingl[8]; /* room for future expansion */
 306         u32 pin_based_vm_exec_control;
 307         u32 cpu_based_vm_exec_control;
 308         u32 exception_bitmap;
 309         u32 page_fault_error_code_mask;
 310         u32 page_fault_error_code_match;
 311         u32 cr3_target_count;
 312         u32 vm_exit_controls;
 313         u32 vm_exit_msr_store_count;
 314         u32 vm_exit_msr_load_count;
 315         u32 vm_entry_controls;
 316         u32 vm_entry_msr_load_count;
 317         u32 vm_entry_intr_info_field;
 318         u32 vm_entry_exception_error_code;
 319         u32 vm_entry_instruction_len;
 320         u32 tpr_threshold;
 321         u32 secondary_vm_exec_control;
 322         u32 vm_instruction_error;
 323         u32 vm_exit_reason;
 324         u32 vm_exit_intr_info;
 325         u32 vm_exit_intr_error_code;
 326         u32 idt_vectoring_info_field;
 327         u32 idt_vectoring_error_code;
 328         u32 vm_exit_instruction_len;
 329         u32 vmx_instruction_info;
 330         u32 guest_es_limit;
 331         u32 guest_cs_limit;
 332         u32 guest_ss_limit;
 333         u32 guest_ds_limit;
 334         u32 guest_fs_limit;
 335         u32 guest_gs_limit;
 336         u32 guest_ldtr_limit;
 337         u32 guest_tr_limit;
 338         u32 guest_gdtr_limit;
 339         u32 guest_idtr_limit;
 340         u32 guest_es_ar_bytes;
 341         u32 guest_cs_ar_bytes;
 342         u32 guest_ss_ar_bytes;
 343         u32 guest_ds_ar_bytes;
 344         u32 guest_fs_ar_bytes;
 345         u32 guest_gs_ar_bytes;
 346         u32 guest_ldtr_ar_bytes;
 347         u32 guest_tr_ar_bytes;
 348         u32 guest_interruptibility_info;
 349         u32 guest_activity_state;
 350         u32 guest_sysenter_cs;
 351         u32 host_ia32_sysenter_cs;
 352         u32 vmx_preemption_timer_value;
 353         u32 padding32[7]; /* room for future expansion */
 354         u16 virtual_processor_id;
 355         u16 posted_intr_nv;
 356         u16 guest_es_selector;
 357         u16 guest_cs_selector;
 358         u16 guest_ss_selector;
 359         u16 guest_ds_selector;
 360         u16 guest_fs_selector;
 361         u16 guest_gs_selector;
 362         u16 guest_ldtr_selector;
 363         u16 guest_tr_selector;
 364         u16 guest_intr_status;
 365         u16 host_es_selector;
 366         u16 host_cs_selector;
 367         u16 host_ss_selector;
 368         u16 host_ds_selector;
 369         u16 host_fs_selector;
 370         u16 host_gs_selector;
 371         u16 host_tr_selector;
 372 };
 373
 374 /*
 375  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 376  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 377  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 378  */
 379 #define VMCS12_REVISION 0x11e57ed0
 380
 381 /*
 382  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 383  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 384  * current implementation, 4K are reserved to avoid future complications.
 385  */
 386 #define VMCS12_SIZE 0x1000
 387
 388 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 389 struct vmcs02_list {
 390         struct list_head list;
 391         gpa_t vmptr;
 392         struct loaded_vmcs vmcs02;
 393 };
 394
 395 /*
 396  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 397  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 398  */
 399 struct nested_vmx {
 400         /* Has the level1 guest done vmxon? */
 401         bool vmxon;
 402         gpa_t vmxon_ptr;
 403
 404         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 405         gpa_t current_vmptr;
 406         /* The host-usable pointer to the above */
 407         struct page *current_vmcs12_page;
 408         struct vmcs12 *current_vmcs12;
 409         /*
 410          * Cache of the guest's VMCS, existing outside of guest memory.
 411          * Loaded from guest memory during VMPTRLD. Flushed to guest
 412          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 413          */
 414         struct vmcs12 *cached_vmcs12;
 415         /*
 416          * Indicates if the shadow vmcs must be updated with the
 417          * data hold by vmcs12
 418          */
 419         bool sync_shadow_vmcs;
 420
 421         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 422         struct list_head vmcs02_pool;
 423         int vmcs02_num;
 424         bool change_vmcs01_virtual_x2apic_mode;
 425         /* L2 must run next, and mustn't decide to exit to L1. */
 426         bool nested_run_pending;
 427         /*
 428          * Guest pages referred to in vmcs02 with host-physical pointers, so
 429          * we must keep them pinned while L2 runs.
 430          */
 431         struct page *apic_access_page;
 432         struct page *virtual_apic_page;
 433         struct page *pi_desc_page;
 434         struct pi_desc *pi_desc;
 435         bool pi_pending;
 436         u16 posted_intr_nv;
 437
 438         unsigned long *msr_bitmap;
 439
 440         struct hrtimer preemption_timer;
 441         bool preemption_timer_expired;
 442
 443         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 444         u64 vmcs01_debugctl;
 445
 446         u16 vpid02;
 447         u16 last_vpid;
 448
 449         u32 nested_vmx_procbased_ctls_low;
 450         u32 nested_vmx_procbased_ctls_high;
 451         u32 nested_vmx_true_procbased_ctls_low;
 452         u32 nested_vmx_secondary_ctls_low;
 453         u32 nested_vmx_secondary_ctls_high;
 454         u32 nested_vmx_pinbased_ctls_low;
 455         u32 nested_vmx_pinbased_ctls_high;
 456         u32 nested_vmx_exit_ctls_low;
 457         u32 nested_vmx_exit_ctls_high;
 458         u32 nested_vmx_true_exit_ctls_low;
 459         u32 nested_vmx_entry_ctls_low;
 460         u32 nested_vmx_entry_ctls_high;
 461         u32 nested_vmx_true_entry_ctls_low;
 462         u32 nested_vmx_misc_low;
 463         u32 nested_vmx_misc_high;
 464         u32 nested_vmx_ept_caps;
 465         u32 nested_vmx_vpid_caps;
 466 };
 467
 468 #define POSTED_INTR_ON  0
 469 #define POSTED_INTR_SN  1
 470
 471 /* Posted-Interrupt Descriptor */
 472 struct pi_desc {
 473         u32 pir[8];     /* Posted interrupt requested */
 474         union {
 475                 struct {
 476                                 /* bit 256 - Outstanding Notification */
 477                         u16     on      : 1,
 478                                 /* bit 257 - Suppress Notification */
 479                                 sn      : 1,
 480                                 /* bit 271:258 - Reserved */
 481                                 rsvd_1  : 14;
 482                                 /* bit 279:272 - Notification Vector */
 483                         u8      nv;
 484                                 /* bit 287:280 - Reserved */
 485                         u8      rsvd_2;
 486                                 /* bit 319:288 - Notification Destination */
 487                         u32     ndst;
 488                 };
 489                 u64 control;
 490         };
 491         u32 rsvd[6];
 492 } __aligned(64);
 493
 494 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 495 {
 496         return test_and_set_bit(POSTED_INTR_ON,
 497                         (unsigned long *)&pi_desc->control);
 498 }
 499
 500 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 501 {
 502         return test_and_clear_bit(POSTED_INTR_ON,
 503                         (unsigned long *)&pi_desc->control);
 504 }
 505
 506 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 507 {
 508         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 509 }
 510
 511 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 512 {
 513         return clear_bit(POSTED_INTR_SN,
 514                         (unsigned long *)&pi_desc->control);
 515 }
 516
 517 static inline void pi_set_sn(struct pi_desc *pi_desc)
 518 {
 519         return set_bit(POSTED_INTR_SN,
 520                         (unsigned long *)&pi_desc->control);
 521 }
 522
 523 static inline int pi_test_on(struct pi_desc *pi_desc)
 524 {
 525         return test_bit(POSTED_INTR_ON,
 526                         (unsigned long *)&pi_desc->control);
 527 }
 528
 529 static inline int pi_test_sn(struct pi_desc *pi_desc)
 530 {
 531         return test_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 struct vcpu_vmx {
 536         struct kvm_vcpu       vcpu;
 537         unsigned long         host_rsp;
 538         u8                    fail;
 539         bool                  nmi_known_unmasked;
 540         u32                   exit_intr_info;
 541         u32                   idt_vectoring_info;
 542         ulong                 rflags;
 543         struct shared_msr_entry *guest_msrs;
 544         int                   nmsrs;
 545         int                   save_nmsrs;
 546         unsigned long         host_idt_base;
 547 #ifdef CONFIG_X86_64
 548         u64                   msr_host_kernel_gs_base;
 549         u64                   msr_guest_kernel_gs_base;
 550 #endif
 551         u32 vm_entry_controls_shadow;
 552         u32 vm_exit_controls_shadow;
 553         /*
 554          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 555          * non-nested (L1) guest, it always points to vmcs01. For a nested
 556          * guest (L2), it points to a different VMCS.
 557          */
 558         struct loaded_vmcs    vmcs01;
 559         struct loaded_vmcs   *loaded_vmcs;
 560         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 561         struct msr_autoload {
 562                 unsigned nr;
 563                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 564                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 565         } msr_autoload;
 566         struct {
 567                 int           loaded;
 568                 u16           fs_sel, gs_sel, ldt_sel;
 569 #ifdef CONFIG_X86_64
 570                 u16           ds_sel, es_sel;
 571 #endif
 572                 int           gs_ldt_reload_needed;
 573                 int           fs_reload_needed;
 574                 u64           msr_host_bndcfgs;
 575                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 576         } host_state;
 577         struct {
 578                 int vm86_active;
 579                 ulong save_rflags;
 580                 struct kvm_segment segs[8];
 581         } rmode;
 582         struct {
 583                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 584                 struct kvm_save_segment {
 585                         u16 selector;
 586                         unsigned long base;
 587                         u32 limit;
 588                         u32 ar;
 589                 } seg[8];
 590         } segment_cache;
 591         int vpid;
 592         bool emulation_required;
 593
 594         /* Support for vnmi-less CPUs */
 595         int soft_vnmi_blocked;
 596         ktime_t entry_time;
 597         s64 vnmi_blocked_time;
 598         u32 exit_reason;
 599
 600         /* Posted interrupt descriptor */
 601         struct pi_desc pi_desc;
 602
 603         /* Support for a guest hypervisor (nested VMX) */
 604         struct nested_vmx nested;
 605
 606         /* Dynamic PLE window. */
 607         int ple_window;
 608         bool ple_window_dirty;
 609
 610         /* Support for PML */
 611 #define PML_ENTITY_NUM          512
 612         struct page *pml_pg;
 613
 614         /* apic deadline value in host tsc */
 615         u64 hv_deadline_tsc;
 616
 617         u64 current_tsc_ratio;
 618
 619         bool guest_pkru_valid;
 620         u32 guest_pkru;
 621         u32 host_pkru;
 622
 623         /*
 624          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 625          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 626          * in msr_ia32_feature_control_valid_bits.
 627          */
 628         u64 msr_ia32_feature_control;
 629         u64 msr_ia32_feature_control_valid_bits;
 630 };
 631
 632 enum segment_cache_field {
 633         SEG_FIELD_SEL = 0,
 634         SEG_FIELD_BASE = 1,
 635         SEG_FIELD_LIMIT = 2,
 636         SEG_FIELD_AR = 3,
 637
 638         SEG_FIELD_NR = 4
 639 };
 640
 641 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 642 {
 643         return container_of(vcpu, struct vcpu_vmx, vcpu);
 644 }
 645
 646 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 647 {
 648         return &(to_vmx(vcpu)->pi_desc);
 649 }
 650
 651 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 652 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 653 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 654                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 655
 656
 657 static unsigned long shadow_read_only_fields[] = {
 658         /*
 659          * We do NOT shadow fields that are modified when L0
 660          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 661          * VMXON...) executed by L1.
 662          * For example, VM_INSTRUCTION_ERROR is read
 663          * by L1 if a vmx instruction fails (part of the error path).
 664          * Note the code assumes this logic. If for some reason
 665          * we start shadowing these fields then we need to
 666          * force a shadow sync when L0 emulates vmx instructions
 667          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 668          * by nested_vmx_failValid)
 669          */
 670         VM_EXIT_REASON,
 671         VM_EXIT_INTR_INFO,
 672         VM_EXIT_INSTRUCTION_LEN,
 673         IDT_VECTORING_INFO_FIELD,
 674         IDT_VECTORING_ERROR_CODE,
 675         VM_EXIT_INTR_ERROR_CODE,
 676         EXIT_QUALIFICATION,
 677         GUEST_LINEAR_ADDRESS,
 678         GUEST_PHYSICAL_ADDRESS
 679 };
 680 static int max_shadow_read_only_fields =
 681         ARRAY_SIZE(shadow_read_only_fields);
 682
 683 static unsigned long shadow_read_write_fields[] = {
 684         TPR_THRESHOLD,
 685         GUEST_RIP,
 686         GUEST_RSP,
 687         GUEST_CR0,
 688         GUEST_CR3,
 689         GUEST_CR4,
 690         GUEST_INTERRUPTIBILITY_INFO,
 691         GUEST_RFLAGS,
 692         GUEST_CS_SELECTOR,
 693         GUEST_CS_AR_BYTES,
 694         GUEST_CS_LIMIT,
 695         GUEST_CS_BASE,
 696         GUEST_ES_BASE,
 697         GUEST_BNDCFGS,
 698         CR0_GUEST_HOST_MASK,
 699         CR0_READ_SHADOW,
 700         CR4_READ_SHADOW,
 701         TSC_OFFSET,
 702         EXCEPTION_BITMAP,
 703         CPU_BASED_VM_EXEC_CONTROL,
 704         VM_ENTRY_EXCEPTION_ERROR_CODE,
 705         VM_ENTRY_INTR_INFO_FIELD,
 706         VM_ENTRY_INSTRUCTION_LEN,
 707         VM_ENTRY_EXCEPTION_ERROR_CODE,
 708         HOST_FS_BASE,
 709         HOST_GS_BASE,
 710         HOST_FS_SELECTOR,
 711         HOST_GS_SELECTOR
 712 };
 713 static int max_shadow_read_write_fields =
 714         ARRAY_SIZE(shadow_read_write_fields);
 715
 716 static const unsigned short vmcs_field_to_offset_table[] = {
 717         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 718         FIELD(POSTED_INTR_NV, posted_intr_nv),
 719         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 720         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 721         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 722         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 723         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 724         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 725         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 726         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 727         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 728         FIELD(HOST_ES_SELECTOR, host_es_selector),
 729         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 730         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 731         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 732         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 733         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 734         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 735         FIELD64(IO_BITMAP_A, io_bitmap_a),
 736         FIELD64(IO_BITMAP_B, io_bitmap_b),
 737         FIELD64(MSR_BITMAP, msr_bitmap),
 738         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 739         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 740         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 741         FIELD64(TSC_OFFSET, tsc_offset),
 742         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 743         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 744         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 745         FIELD64(EPT_POINTER, ept_pointer),
 746         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 747         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 748         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 749         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 750         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 751         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 752         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 753         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 754         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 755         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 756         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 757         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 758         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 759         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 760         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 761         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 762         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 763         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 764         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 765         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 766         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 767         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 768         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 769         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 770         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 771         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 772         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 773         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 774         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 775         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 776         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 777         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 778         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 779         FIELD(TPR_THRESHOLD, tpr_threshold),
 780         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 781         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 782         FIELD(VM_EXIT_REASON, vm_exit_reason),
 783         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 784         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 785         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 786         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 787         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 788         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 789         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 790         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 791         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 792         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 793         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 794         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 795         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 796         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 797         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 798         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 799         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 800         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 801         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 802         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 803         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 804         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 805         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 806         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 807         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 808         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 809         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 810         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 811         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 812         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 813         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 814         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 815         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 816         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 817         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 818         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 819         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 820         FIELD(EXIT_QUALIFICATION, exit_qualification),
 821         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 822         FIELD(GUEST_CR0, guest_cr0),
 823         FIELD(GUEST_CR3, guest_cr3),
 824         FIELD(GUEST_CR4, guest_cr4),
 825         FIELD(GUEST_ES_BASE, guest_es_base),
 826         FIELD(GUEST_CS_BASE, guest_cs_base),
 827         FIELD(GUEST_SS_BASE, guest_ss_base),
 828         FIELD(GUEST_DS_BASE, guest_ds_base),
 829         FIELD(GUEST_FS_BASE, guest_fs_base),
 830         FIELD(GUEST_GS_BASE, guest_gs_base),
 831         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 832         FIELD(GUEST_TR_BASE, guest_tr_base),
 833         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 834         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 835         FIELD(GUEST_DR7, guest_dr7),
 836         FIELD(GUEST_RSP, guest_rsp),
 837         FIELD(GUEST_RIP, guest_rip),
 838         FIELD(GUEST_RFLAGS, guest_rflags),
 839         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 840         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 841         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 842         FIELD(HOST_CR0, host_cr0),
 843         FIELD(HOST_CR3, host_cr3),
 844         FIELD(HOST_CR4, host_cr4),
 845         FIELD(HOST_FS_BASE, host_fs_base),
 846         FIELD(HOST_GS_BASE, host_gs_base),
 847         FIELD(HOST_TR_BASE, host_tr_base),
 848         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 849         FIELD(HOST_IDTR_BASE, host_idtr_base),
 850         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 851         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 852         FIELD(HOST_RSP, host_rsp),
 853         FIELD(HOST_RIP, host_rip),
 854 };
 855
 856 static inline short vmcs_field_to_offset(unsigned long field)
 857 {
 858         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 859
 860         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 861             vmcs_field_to_offset_table[field] == 0)
 862                 return -ENOENT;
 863
 864         return vmcs_field_to_offset_table[field];
 865 }
 866
 867 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 868 {
 869         return to_vmx(vcpu)->nested.cached_vmcs12;
 870 }
 871
 872 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 873 {
 874         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 875         if (is_error_page(page))
 876                 return NULL;
 877
 878         return page;
 879 }
 880
 881 static void nested_release_page(struct page *page)
 882 {
 883         kvm_release_page_dirty(page);
 884 }
 885
 886 static void nested_release_page_clean(struct page *page)
 887 {
 888         kvm_release_page_clean(page);
 889 }
 890
 891 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 892 static u64 construct_eptp(unsigned long root_hpa);
 893 static void kvm_cpu_vmxon(u64 addr);
 894 static void kvm_cpu_vmxoff(void);
 895 static bool vmx_xsaves_supported(void);
 896 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 897 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 898                             struct kvm_segment *var, int seg);
 899 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 900                             struct kvm_segment *var, int seg);
 901 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 902 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 903 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 904 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 905 static int alloc_identity_pagetable(struct kvm *kvm);
 906
 907 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 908 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 909 /*
 910  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 911  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 912  */
 913 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 914 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 915
 916 /*
 917  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 918  * can find which vCPU should be waken up.
 919  */
 920 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 921 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 922
 923 static unsigned long *vmx_io_bitmap_a;
 924 static unsigned long *vmx_io_bitmap_b;
 925 static unsigned long *vmx_msr_bitmap_legacy;
 926 static unsigned long *vmx_msr_bitmap_longmode;
 927 static unsigned long *vmx_msr_bitmap_legacy_x2apic_apicv;
 928 static unsigned long *vmx_msr_bitmap_longmode_x2apic_apicv;
 929 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 930 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 931 static unsigned long *vmx_vmread_bitmap;
 932 static unsigned long *vmx_vmwrite_bitmap;
 933
 934 static bool cpu_has_load_ia32_efer;
 935 static bool cpu_has_load_perf_global_ctrl;
 936
 937 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 938 static DEFINE_SPINLOCK(vmx_vpid_lock);
 939
 940 static struct vmcs_config {
 941         int size;
 942         int order;
 943         u32 basic_cap;
 944         u32 revision_id;
 945         u32 pin_based_exec_ctrl;
 946         u32 cpu_based_exec_ctrl;
 947         u32 cpu_based_2nd_exec_ctrl;
 948         u32 vmexit_ctrl;
 949         u32 vmentry_ctrl;
 950 } vmcs_config;
 951
 952 static struct vmx_capability {
 953         u32 ept;
 954         u32 vpid;
 955 } vmx_capability;
 956
 957 #define VMX_SEGMENT_FIELD(seg)                                  \
 958         [VCPU_SREG_##seg] = {                                   \
 959                 .selector = GUEST_##seg##_SELECTOR,             \
 960                 .base = GUEST_##seg##_BASE,                     \
 961                 .limit = GUEST_##seg##_LIMIT,                   \
 962                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 963         }
 964
 965 static const struct kvm_vmx_segment_field {
 966         unsigned selector;
 967         unsigned base;
 968         unsigned limit;
 969         unsigned ar_bytes;
 970 } kvm_vmx_segment_fields[] = {
 971         VMX_SEGMENT_FIELD(CS),
 972         VMX_SEGMENT_FIELD(DS),
 973         VMX_SEGMENT_FIELD(ES),
 974         VMX_SEGMENT_FIELD(FS),
 975         VMX_SEGMENT_FIELD(GS),
 976         VMX_SEGMENT_FIELD(SS),
 977         VMX_SEGMENT_FIELD(TR),
 978         VMX_SEGMENT_FIELD(LDTR),
 979 };
 980
 981 static u64 host_efer;
 982
 983 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 984
 985 /*
 986  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 987  * away by decrementing the array size.
 988  */
 989 static const u32 vmx_msr_index[] = {
 990 #ifdef CONFIG_X86_64
 991         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 992 #endif
 993         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 994 };
 995
 996 static inline bool is_exception_n(u32 intr_info, u8 vector)
 997 {
 998         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 999                              INTR_INFO_VALID_MASK)) ==
1000                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1001 }
1002
1003 static inline bool is_debug(u32 intr_info)
1004 {
1005         return is_exception_n(intr_info, DB_VECTOR);
1006 }
1007
1008 static inline bool is_breakpoint(u32 intr_info)
1009 {
1010         return is_exception_n(intr_info, BP_VECTOR);
1011 }
1012
1013 static inline bool is_page_fault(u32 intr_info)
1014 {
1015         return is_exception_n(intr_info, PF_VECTOR);
1016 }
1017
1018 static inline bool is_no_device(u32 intr_info)
1019 {
1020         return is_exception_n(intr_info, NM_VECTOR);
1021 }
1022
1023 static inline bool is_invalid_opcode(u32 intr_info)
1024 {
1025         return is_exception_n(intr_info, UD_VECTOR);
1026 }
1027
1028 static inline bool is_external_interrupt(u32 intr_info)
1029 {
1030         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1031                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1032 }
1033
1034 static inline bool is_machine_check(u32 intr_info)
1035 {
1036         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1037                              INTR_INFO_VALID_MASK)) ==
1038                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1039 }
1040
1041 static inline bool cpu_has_vmx_msr_bitmap(void)
1042 {
1043         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1044 }
1045
1046 static inline bool cpu_has_vmx_tpr_shadow(void)
1047 {
1048         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1049 }
1050
1051 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1052 {
1053         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1054 }
1055
1056 static inline bool cpu_has_secondary_exec_ctrls(void)
1057 {
1058         return vmcs_config.cpu_based_exec_ctrl &
1059                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1060 }
1061
1062 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1063 {
1064         return vmcs_config.cpu_based_2nd_exec_ctrl &
1065                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1066 }
1067
1068 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1069 {
1070         return vmcs_config.cpu_based_2nd_exec_ctrl &
1071                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1072 }
1073
1074 static inline bool cpu_has_vmx_apic_register_virt(void)
1075 {
1076         return vmcs_config.cpu_based_2nd_exec_ctrl &
1077                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1078 }
1079
1080 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1081 {
1082         return vmcs_config.cpu_based_2nd_exec_ctrl &
1083                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1084 }
1085
1086 /*
1087  * Comment's format: document - errata name - stepping - processor name.
1088  * Refer from
1089  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1090  */
1091 static u32 vmx_preemption_cpu_tfms[] = {
1092 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1093 0x000206E6,
1094 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1095 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1096 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1097 0x00020652,
1098 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1099 0x00020655,
1100 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1101 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1102 /*
1103  * 320767.pdf - AAP86  - B1 -
1104  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1105  */
1106 0x000106E5,
1107 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1108 0x000106A0,
1109 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1110 0x000106A1,
1111 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1112 0x000106A4,
1113  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1114  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1115  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1116 0x000106A5,
1117 };
1118
1119 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1120 {
1121         u32 eax = cpuid_eax(0x00000001), i;
1122
1123         /* Clear the reserved bits */
1124         eax &= ~(0x3U << 14 | 0xfU << 28);
1125         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1126                 if (eax == vmx_preemption_cpu_tfms[i])
1127                         return true;
1128
1129         return false;
1130 }
1131
1132 static inline bool cpu_has_vmx_preemption_timer(void)
1133 {
1134         return vmcs_config.pin_based_exec_ctrl &
1135                 PIN_BASED_VMX_PREEMPTION_TIMER;
1136 }
1137
1138 static inline bool cpu_has_vmx_posted_intr(void)
1139 {
1140         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1141                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1142 }
1143
1144 static inline bool cpu_has_vmx_apicv(void)
1145 {
1146         return cpu_has_vmx_apic_register_virt() &&
1147                 cpu_has_vmx_virtual_intr_delivery() &&
1148                 cpu_has_vmx_posted_intr();
1149 }
1150
1151 static inline bool cpu_has_vmx_flexpriority(void)
1152 {
1153         return cpu_has_vmx_tpr_shadow() &&
1154                 cpu_has_vmx_virtualize_apic_accesses();
1155 }
1156
1157 static inline bool cpu_has_vmx_ept_execute_only(void)
1158 {
1159         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1160 }
1161
1162 static inline bool cpu_has_vmx_ept_2m_page(void)
1163 {
1164         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1165 }
1166
1167 static inline bool cpu_has_vmx_ept_1g_page(void)
1168 {
1169         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1170 }
1171
1172 static inline bool cpu_has_vmx_ept_4levels(void)
1173 {
1174         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1175 }
1176
1177 static inline bool cpu_has_vmx_ept_ad_bits(void)
1178 {
1179         return vmx_capability.ept & VMX_EPT_AD_BIT;
1180 }
1181
1182 static inline bool cpu_has_vmx_invept_context(void)
1183 {
1184         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1185 }
1186
1187 static inline bool cpu_has_vmx_invept_global(void)
1188 {
1189         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1190 }
1191
1192 static inline bool cpu_has_vmx_invvpid_single(void)
1193 {
1194         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1195 }
1196
1197 static inline bool cpu_has_vmx_invvpid_global(void)
1198 {
1199         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept(void)
1203 {
1204         return vmcs_config.cpu_based_2nd_exec_ctrl &
1205                 SECONDARY_EXEC_ENABLE_EPT;
1206 }
1207
1208 static inline bool cpu_has_vmx_unrestricted_guest(void)
1209 {
1210         return vmcs_config.cpu_based_2nd_exec_ctrl &
1211                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1212 }
1213
1214 static inline bool cpu_has_vmx_ple(void)
1215 {
1216         return vmcs_config.cpu_based_2nd_exec_ctrl &
1217                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1218 }
1219
1220 static inline bool cpu_has_vmx_basic_inout(void)
1221 {
1222         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1223 }
1224
1225 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1226 {
1227         return flexpriority_enabled && lapic_in_kernel(vcpu);
1228 }
1229
1230 static inline bool cpu_has_vmx_vpid(void)
1231 {
1232         return vmcs_config.cpu_based_2nd_exec_ctrl &
1233                 SECONDARY_EXEC_ENABLE_VPID;
1234 }
1235
1236 static inline bool cpu_has_vmx_rdtscp(void)
1237 {
1238         return vmcs_config.cpu_based_2nd_exec_ctrl &
1239                 SECONDARY_EXEC_RDTSCP;
1240 }
1241
1242 static inline bool cpu_has_vmx_invpcid(void)
1243 {
1244         return vmcs_config.cpu_based_2nd_exec_ctrl &
1245                 SECONDARY_EXEC_ENABLE_INVPCID;
1246 }
1247
1248 static inline bool cpu_has_virtual_nmis(void)
1249 {
1250         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1251 }
1252
1253 static inline bool cpu_has_vmx_wbinvd_exit(void)
1254 {
1255         return vmcs_config.cpu_based_2nd_exec_ctrl &
1256                 SECONDARY_EXEC_WBINVD_EXITING;
1257 }
1258
1259 static inline bool cpu_has_vmx_shadow_vmcs(void)
1260 {
1261         u64 vmx_msr;
1262         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1263         /* check if the cpu supports writing r/o exit information fields */
1264         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1265                 return false;
1266
1267         return vmcs_config.cpu_based_2nd_exec_ctrl &
1268                 SECONDARY_EXEC_SHADOW_VMCS;
1269 }
1270
1271 static inline bool cpu_has_vmx_pml(void)
1272 {
1273         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1274 }
1275
1276 static inline bool cpu_has_vmx_tsc_scaling(void)
1277 {
1278         return vmcs_config.cpu_based_2nd_exec_ctrl &
1279                 SECONDARY_EXEC_TSC_SCALING;
1280 }
1281
1282 static inline bool report_flexpriority(void)
1283 {
1284         return flexpriority_enabled;
1285 }
1286
1287 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1288 {
1289         return vmcs12->cpu_based_vm_exec_control & bit;
1290 }
1291
1292 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1293 {
1294         return (vmcs12->cpu_based_vm_exec_control &
1295                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1296                 (vmcs12->secondary_vm_exec_control & bit);
1297 }
1298
1299 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1300 {
1301         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1302 }
1303
1304 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1305 {
1306         return vmcs12->pin_based_vm_exec_control &
1307                 PIN_BASED_VMX_PREEMPTION_TIMER;
1308 }
1309
1310 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1311 {
1312         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1313 }
1314
1315 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1316 {
1317         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1318                 vmx_xsaves_supported();
1319 }
1320
1321 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1322 {
1323         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1324 }
1325
1326 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1327 {
1328         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1329 }
1330
1331 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1332 {
1333         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1334 }
1335
1336 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1337 {
1338         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1339 }
1340
1341 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1342 {
1343         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1344 }
1345
1346 static inline bool is_exception(u32 intr_info)
1347 {
1348         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1349                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1350 }
1351
1352 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1353                               u32 exit_intr_info,
1354                               unsigned long exit_qualification);
1355 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1356                         struct vmcs12 *vmcs12,
1357                         u32 reason, unsigned long qualification);
1358
1359 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1360 {
1361         int i;
1362
1363         for (i = 0; i < vmx->nmsrs; ++i)
1364                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1365                         return i;
1366         return -1;
1367 }
1368
1369 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1370 {
1371     struct {
1372         u64 vpid : 16;
1373         u64 rsvd : 48;
1374         u64 gva;
1375     } operand = { vpid, 0, gva };
1376
1377     asm volatile (__ex(ASM_VMX_INVVPID)
1378                   /* CF==1 or ZF==1 --> rc = -1 */
1379                   "; ja 1f ; ud2 ; 1:"
1380                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1381 }
1382
1383 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1384 {
1385         struct {
1386                 u64 eptp, gpa;
1387         } operand = {eptp, gpa};
1388
1389         asm volatile (__ex(ASM_VMX_INVEPT)
1390                         /* CF==1 or ZF==1 --> rc = -1 */
1391                         "; ja 1f ; ud2 ; 1:\n"
1392                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1393 }
1394
1395 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1396 {
1397         int i;
1398
1399         i = __find_msr_index(vmx, msr);
1400         if (i >= 0)
1401                 return &vmx->guest_msrs[i];
1402         return NULL;
1403 }
1404
1405 static void vmcs_clear(struct vmcs *vmcs)
1406 {
1407         u64 phys_addr = __pa(vmcs);
1408         u8 error;
1409
1410         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1411                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1412                       : "cc", "memory");
1413         if (error)
1414                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1415                        vmcs, phys_addr);
1416 }
1417
1418 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1419 {
1420         vmcs_clear(loaded_vmcs->vmcs);
1421         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1422                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1423         loaded_vmcs->cpu = -1;
1424         loaded_vmcs->launched = 0;
1425 }
1426
1427 static void vmcs_load(struct vmcs *vmcs)
1428 {
1429         u64 phys_addr = __pa(vmcs);
1430         u8 error;
1431
1432         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1433                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1434                         : "cc", "memory");
1435         if (error)
1436                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1437                        vmcs, phys_addr);
1438 }
1439
1440 #ifdef CONFIG_KEXEC_CORE
1441 /*
1442  * This bitmap is used to indicate whether the vmclear
1443  * operation is enabled on all cpus. All disabled by
1444  * default.
1445  */
1446 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1447
1448 static inline void crash_enable_local_vmclear(int cpu)
1449 {
1450         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1451 }
1452
1453 static inline void crash_disable_local_vmclear(int cpu)
1454 {
1455         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1456 }
1457
1458 static inline int crash_local_vmclear_enabled(int cpu)
1459 {
1460         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1461 }
1462
1463 static void crash_vmclear_local_loaded_vmcss(void)
1464 {
1465         int cpu = raw_smp_processor_id();
1466         struct loaded_vmcs *v;
1467
1468         if (!crash_local_vmclear_enabled(cpu))
1469                 return;
1470
1471         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1472                             loaded_vmcss_on_cpu_link)
1473                 vmcs_clear(v->vmcs);
1474 }
1475 #else
1476 static inline void crash_enable_local_vmclear(int cpu) { }
1477 static inline void crash_disable_local_vmclear(int cpu) { }
1478 #endif /* CONFIG_KEXEC_CORE */
1479
1480 static void __loaded_vmcs_clear(void *arg)
1481 {
1482         struct loaded_vmcs *loaded_vmcs = arg;
1483         int cpu = raw_smp_processor_id();
1484
1485         if (loaded_vmcs->cpu != cpu)
1486                 return; /* vcpu migration can race with cpu offline */
1487         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1488                 per_cpu(current_vmcs, cpu) = NULL;
1489         crash_disable_local_vmclear(cpu);
1490         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1491
1492         /*
1493          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1494          * is before setting loaded_vmcs->vcpu to -1 which is done in
1495          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1496          * then adds the vmcs into percpu list before it is deleted.
1497          */
1498         smp_wmb();
1499
1500         loaded_vmcs_init(loaded_vmcs);
1501         crash_enable_local_vmclear(cpu);
1502 }
1503
1504 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1505 {
1506         int cpu = loaded_vmcs->cpu;
1507
1508         if (cpu != -1)
1509                 smp_call_function_single(cpu,
1510                          __loaded_vmcs_clear, loaded_vmcs, 1);
1511 }
1512
1513 static inline void vpid_sync_vcpu_single(int vpid)
1514 {
1515         if (vpid == 0)
1516                 return;
1517
1518         if (cpu_has_vmx_invvpid_single())
1519                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1520 }
1521
1522 static inline void vpid_sync_vcpu_global(void)
1523 {
1524         if (cpu_has_vmx_invvpid_global())
1525                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1526 }
1527
1528 static inline void vpid_sync_context(int vpid)
1529 {
1530         if (cpu_has_vmx_invvpid_single())
1531                 vpid_sync_vcpu_single(vpid);
1532         else
1533                 vpid_sync_vcpu_global();
1534 }
1535
1536 static inline void ept_sync_global(void)
1537 {
1538         if (cpu_has_vmx_invept_global())
1539                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1540 }
1541
1542 static inline void ept_sync_context(u64 eptp)
1543 {
1544         if (enable_ept) {
1545                 if (cpu_has_vmx_invept_context())
1546                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1547                 else
1548                         ept_sync_global();
1549         }
1550 }
1551
1552 static __always_inline void vmcs_check16(unsigned long field)
1553 {
1554         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1555                          "16-bit accessor invalid for 64-bit field");
1556         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1557                          "16-bit accessor invalid for 64-bit high field");
1558         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1559                          "16-bit accessor invalid for 32-bit high field");
1560         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1561                          "16-bit accessor invalid for natural width field");
1562 }
1563
1564 static __always_inline void vmcs_check32(unsigned long field)
1565 {
1566         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1567                          "32-bit accessor invalid for 16-bit field");
1568         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1569                          "32-bit accessor invalid for natural width field");
1570 }
1571
1572 static __always_inline void vmcs_check64(unsigned long field)
1573 {
1574         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1575                          "64-bit accessor invalid for 16-bit field");
1576         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1577                          "64-bit accessor invalid for 64-bit high field");
1578         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1579                          "64-bit accessor invalid for 32-bit field");
1580         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1581                          "64-bit accessor invalid for natural width field");
1582 }
1583
1584 static __always_inline void vmcs_checkl(unsigned long field)
1585 {
1586         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1587                          "Natural width accessor invalid for 16-bit field");
1588         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1589                          "Natural width accessor invalid for 64-bit field");
1590         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1591                          "Natural width accessor invalid for 64-bit high field");
1592         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1593                          "Natural width accessor invalid for 32-bit field");
1594 }
1595
1596 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1597 {
1598         unsigned long value;
1599
1600         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1601                       : "=a"(value) : "d"(field) : "cc");
1602         return value;
1603 }
1604
1605 static __always_inline u16 vmcs_read16(unsigned long field)
1606 {
1607         vmcs_check16(field);
1608         return __vmcs_readl(field);
1609 }
1610
1611 static __always_inline u32 vmcs_read32(unsigned long field)
1612 {
1613         vmcs_check32(field);
1614         return __vmcs_readl(field);
1615 }
1616
1617 static __always_inline u64 vmcs_read64(unsigned long field)
1618 {
1619         vmcs_check64(field);
1620 #ifdef CONFIG_X86_64
1621         return __vmcs_readl(field);
1622 #else
1623         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1624 #endif
1625 }
1626
1627 static __always_inline unsigned long vmcs_readl(unsigned long field)
1628 {
1629         vmcs_checkl(field);
1630         return __vmcs_readl(field);
1631 }
1632
1633 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1634 {
1635         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1636                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1637         dump_stack();
1638 }
1639
1640 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1641 {
1642         u8 error;
1643
1644         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1645                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1646         if (unlikely(error))
1647                 vmwrite_error(field, value);
1648 }
1649
1650 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1651 {
1652         vmcs_check16(field);
1653         __vmcs_writel(field, value);
1654 }
1655
1656 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1657 {
1658         vmcs_check32(field);
1659         __vmcs_writel(field, value);
1660 }
1661
1662 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1663 {
1664         vmcs_check64(field);
1665         __vmcs_writel(field, value);
1666 #ifndef CONFIG_X86_64
1667         asm volatile ("");
1668         __vmcs_writel(field+1, value >> 32);
1669 #endif
1670 }
1671
1672 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1673 {
1674         vmcs_checkl(field);
1675         __vmcs_writel(field, value);
1676 }
1677
1678 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1679 {
1680         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1681                          "vmcs_clear_bits does not support 64-bit fields");
1682         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1683 }
1684
1685 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1686 {
1687         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1688                          "vmcs_set_bits does not support 64-bit fields");
1689         __vmcs_writel(field, __vmcs_readl(field) | mask);
1690 }
1691
1692 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1693 {
1694         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1695 }
1696
1697 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1698 {
1699         vmcs_write32(VM_ENTRY_CONTROLS, val);
1700         vmx->vm_entry_controls_shadow = val;
1701 }
1702
1703 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1704 {
1705         if (vmx->vm_entry_controls_shadow != val)
1706                 vm_entry_controls_init(vmx, val);
1707 }
1708
1709 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1710 {
1711         return vmx->vm_entry_controls_shadow;
1712 }
1713
1714
1715 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1716 {
1717         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1718 }
1719
1720 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1721 {
1722         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1723 }
1724
1725 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1726 {
1727         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1728 }
1729
1730 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1731 {
1732         vmcs_write32(VM_EXIT_CONTROLS, val);
1733         vmx->vm_exit_controls_shadow = val;
1734 }
1735
1736 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1737 {
1738         if (vmx->vm_exit_controls_shadow != val)
1739                 vm_exit_controls_init(vmx, val);
1740 }
1741
1742 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1743 {
1744         return vmx->vm_exit_controls_shadow;
1745 }
1746
1747
1748 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1749 {
1750         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1751 }
1752
1753 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1754 {
1755         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1756 }
1757
1758 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1759 {
1760         vmx->segment_cache.bitmask = 0;
1761 }
1762
1763 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1764                                        unsigned field)
1765 {
1766         bool ret;
1767         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1768
1769         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1770                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1771                 vmx->segment_cache.bitmask = 0;
1772         }
1773         ret = vmx->segment_cache.bitmask & mask;
1774         vmx->segment_cache.bitmask |= mask;
1775         return ret;
1776 }
1777
1778 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1779 {
1780         u16 *p = &vmx->segment_cache.seg[seg].selector;
1781
1782         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1783                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1784         return *p;
1785 }
1786
1787 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1788 {
1789         ulong *p = &vmx->segment_cache.seg[seg].base;
1790
1791         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1792                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1793         return *p;
1794 }
1795
1796 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1797 {
1798         u32 *p = &vmx->segment_cache.seg[seg].limit;
1799
1800         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1801                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1802         return *p;
1803 }
1804
1805 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1806 {
1807         u32 *p = &vmx->segment_cache.seg[seg].ar;
1808
1809         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1810                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1811         return *p;
1812 }
1813
1814 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1815 {
1816         u32 eb;
1817
1818         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1819              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1820         if ((vcpu->guest_debug &
1821              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1822             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1823                 eb |= 1u << BP_VECTOR;
1824         if (to_vmx(vcpu)->rmode.vm86_active)
1825                 eb = ~0;
1826         if (enable_ept)
1827                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1828         if (vcpu->fpu_active)
1829                 eb &= ~(1u << NM_VECTOR);
1830
1831         /* When we are running a nested L2 guest and L1 specified for it a
1832          * certain exception bitmap, we must trap the same exceptions and pass
1833          * them to L1. When running L2, we will only handle the exceptions
1834          * specified above if L1 did not want them.
1835          */
1836         if (is_guest_mode(vcpu))
1837                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1838
1839         vmcs_write32(EXCEPTION_BITMAP, eb);
1840 }
1841
1842 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1843                 unsigned long entry, unsigned long exit)
1844 {
1845         vm_entry_controls_clearbit(vmx, entry);
1846         vm_exit_controls_clearbit(vmx, exit);
1847 }
1848
1849 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1850 {
1851         unsigned i;
1852         struct msr_autoload *m = &vmx->msr_autoload;
1853
1854         switch (msr) {
1855         case MSR_EFER:
1856                 if (cpu_has_load_ia32_efer) {
1857                         clear_atomic_switch_msr_special(vmx,
1858                                         VM_ENTRY_LOAD_IA32_EFER,
1859                                         VM_EXIT_LOAD_IA32_EFER);
1860                         return;
1861                 }
1862                 break;
1863         case MSR_CORE_PERF_GLOBAL_CTRL:
1864                 if (cpu_has_load_perf_global_ctrl) {
1865                         clear_atomic_switch_msr_special(vmx,
1866                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1867                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1868                         return;
1869                 }
1870                 break;
1871         }
1872
1873         for (i = 0; i < m->nr; ++i)
1874                 if (m->guest[i].index == msr)
1875                         break;
1876
1877         if (i == m->nr)
1878                 return;
1879         --m->nr;
1880         m->guest[i] = m->guest[m->nr];
1881         m->host[i] = m->host[m->nr];
1882         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1883         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1884 }
1885
1886 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1887                 unsigned long entry, unsigned long exit,
1888                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1889                 u64 guest_val, u64 host_val)
1890 {
1891         vmcs_write64(guest_val_vmcs, guest_val);
1892         vmcs_write64(host_val_vmcs, host_val);
1893         vm_entry_controls_setbit(vmx, entry);
1894         vm_exit_controls_setbit(vmx, exit);
1895 }
1896
1897 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1898                                   u64 guest_val, u64 host_val)
1899 {
1900         unsigned i;
1901         struct msr_autoload *m = &vmx->msr_autoload;
1902
1903         switch (msr) {
1904         case MSR_EFER:
1905                 if (cpu_has_load_ia32_efer) {
1906                         add_atomic_switch_msr_special(vmx,
1907                                         VM_ENTRY_LOAD_IA32_EFER,
1908                                         VM_EXIT_LOAD_IA32_EFER,
1909                                         GUEST_IA32_EFER,
1910                                         HOST_IA32_EFER,
1911                                         guest_val, host_val);
1912                         return;
1913                 }
1914                 break;
1915         case MSR_CORE_PERF_GLOBAL_CTRL:
1916                 if (cpu_has_load_perf_global_ctrl) {
1917                         add_atomic_switch_msr_special(vmx,
1918                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1919                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1920                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1921                                         HOST_IA32_PERF_GLOBAL_CTRL,
1922                                         guest_val, host_val);
1923                         return;
1924                 }
1925                 break;
1926         case MSR_IA32_PEBS_ENABLE:
1927                 /* PEBS needs a quiescent period after being disabled (to write
1928                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1929                  * provide that period, so a CPU could write host's record into
1930                  * guest's memory.
1931                  */
1932                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1933         }
1934
1935         for (i = 0; i < m->nr; ++i)
1936                 if (m->guest[i].index == msr)
1937                         break;
1938
1939         if (i == NR_AUTOLOAD_MSRS) {
1940                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1941                                 "Can't add msr %x\n", msr);
1942                 return;
1943         } else if (i == m->nr) {
1944                 ++m->nr;
1945                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1946                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1947         }
1948
1949         m->guest[i].index = msr;
1950         m->guest[i].value = guest_val;
1951         m->host[i].index = msr;
1952         m->host[i].value = host_val;
1953 }
1954
1955 static void reload_tss(void)
1956 {
1957         /*
1958          * VT restores TR but not its size.  Useless.
1959          */
1960         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1961         struct desc_struct *descs;
1962
1963         descs = (void *)gdt->address;
1964         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1965         load_TR_desc();
1966 }
1967
1968 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1969 {
1970         u64 guest_efer = vmx->vcpu.arch.efer;
1971         u64 ignore_bits = 0;
1972
1973         if (!enable_ept) {
1974                 /*
1975                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1976                  * host CPUID is more efficient than testing guest CPUID
1977                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1978                  */
1979                 if (boot_cpu_has(X86_FEATURE_SMEP))
1980                         guest_efer |= EFER_NX;
1981                 else if (!(guest_efer & EFER_NX))
1982                         ignore_bits |= EFER_NX;
1983         }
1984
1985         /*
1986          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1987          */
1988         ignore_bits |= EFER_SCE;
1989 #ifdef CONFIG_X86_64
1990         ignore_bits |= EFER_LMA | EFER_LME;
1991         /* SCE is meaningful only in long mode on Intel */
1992         if (guest_efer & EFER_LMA)
1993                 ignore_bits &= ~(u64)EFER_SCE;
1994 #endif
1995
1996         clear_atomic_switch_msr(vmx, MSR_EFER);
1997
1998         /*
1999          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2000          * On CPUs that support "load IA32_EFER", always switch EFER
2001          * atomically, since it's faster than switching it manually.
2002          */
2003         if (cpu_has_load_ia32_efer ||
2004             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2005                 if (!(guest_efer & EFER_LMA))
2006                         guest_efer &= ~EFER_LME;
2007                 if (guest_efer != host_efer)
2008                         add_atomic_switch_msr(vmx, MSR_EFER,
2009                                               guest_efer, host_efer);
2010                 return false;
2011         } else {
2012                 guest_efer &= ~ignore_bits;
2013                 guest_efer |= host_efer & ignore_bits;
2014
2015                 vmx->guest_msrs[efer_offset].data = guest_efer;
2016                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2017
2018                 return true;
2019         }
2020 }
2021
2022 static unsigned long segment_base(u16 selector)
2023 {
2024         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2025         struct desc_struct *d;
2026         unsigned long table_base;
2027         unsigned long v;
2028
2029         if (!(selector & ~3))
2030                 return 0;
2031
2032         table_base = gdt->address;
2033
2034         if (selector & 4) {           /* from ldt */
2035                 u16 ldt_selector = kvm_read_ldt();
2036
2037                 if (!(ldt_selector & ~3))
2038                         return 0;
2039
2040                 table_base = segment_base(ldt_selector);
2041         }
2042         d = (struct desc_struct *)(table_base + (selector & ~7));
2043         v = get_desc_base(d);
2044 #ifdef CONFIG_X86_64
2045        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2046                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2047 #endif
2048         return v;
2049 }
2050
2051 static inline unsigned long kvm_read_tr_base(void)
2052 {
2053         u16 tr;
2054         asm("str %0" : "=g"(tr));
2055         return segment_base(tr);
2056 }
2057
2058 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2059 {
2060         struct vcpu_vmx *vmx = to_vmx(vcpu);
2061         int i;
2062
2063         if (vmx->host_state.loaded)
2064                 return;
2065
2066         vmx->host_state.loaded = 1;
2067         /*
2068          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2069          * allow segment selectors with cpl > 0 or ti == 1.
2070          */
2071         vmx->host_state.ldt_sel = kvm_read_ldt();
2072         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2073         savesegment(fs, vmx->host_state.fs_sel);
2074         if (!(vmx->host_state.fs_sel & 7)) {
2075                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2076                 vmx->host_state.fs_reload_needed = 0;
2077         } else {
2078                 vmcs_write16(HOST_FS_SELECTOR, 0);
2079                 vmx->host_state.fs_reload_needed = 1;
2080         }
2081         savesegment(gs, vmx->host_state.gs_sel);
2082         if (!(vmx->host_state.gs_sel & 7))
2083                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2084         else {
2085                 vmcs_write16(HOST_GS_SELECTOR, 0);
2086                 vmx->host_state.gs_ldt_reload_needed = 1;
2087         }
2088
2089 #ifdef CONFIG_X86_64
2090         savesegment(ds, vmx->host_state.ds_sel);
2091         savesegment(es, vmx->host_state.es_sel);
2092 #endif
2093
2094 #ifdef CONFIG_X86_64
2095         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2096         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2097 #else
2098         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2099         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2100 #endif
2101
2102 #ifdef CONFIG_X86_64
2103         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2104         if (is_long_mode(&vmx->vcpu))
2105                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2106 #endif
2107         if (boot_cpu_has(X86_FEATURE_MPX))
2108                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2109         for (i = 0; i < vmx->save_nmsrs; ++i)
2110                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2111                                    vmx->guest_msrs[i].data,
2112                                    vmx->guest_msrs[i].mask);
2113 }
2114
2115 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2116 {
2117         if (!vmx->host_state.loaded)
2118                 return;
2119
2120         ++vmx->vcpu.stat.host_state_reload;
2121         vmx->host_state.loaded = 0;
2122 #ifdef CONFIG_X86_64
2123         if (is_long_mode(&vmx->vcpu))
2124                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2125 #endif
2126         if (vmx->host_state.gs_ldt_reload_needed) {
2127                 kvm_load_ldt(vmx->host_state.ldt_sel);
2128 #ifdef CONFIG_X86_64
2129                 load_gs_index(vmx->host_state.gs_sel);
2130 #else
2131                 loadsegment(gs, vmx->host_state.gs_sel);
2132 #endif
2133         }
2134         if (vmx->host_state.fs_reload_needed)
2135                 loadsegment(fs, vmx->host_state.fs_sel);
2136 #ifdef CONFIG_X86_64
2137         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2138                 loadsegment(ds, vmx->host_state.ds_sel);
2139                 loadsegment(es, vmx->host_state.es_sel);
2140         }
2141 #endif
2142         reload_tss();
2143 #ifdef CONFIG_X86_64
2144         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2145 #endif
2146         if (vmx->host_state.msr_host_bndcfgs)
2147                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2148         /*
2149          * If the FPU is not active (through the host task or
2150          * the guest vcpu), then restore the cr0.TS bit.
2151          */
2152         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2153                 stts();
2154         load_gdt(this_cpu_ptr(&host_gdt));
2155 }
2156
2157 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2158 {
2159         preempt_disable();
2160         __vmx_load_host_state(vmx);
2161         preempt_enable();
2162 }
2163
2164 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2165 {
2166         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2167         struct pi_desc old, new;
2168         unsigned int dest;
2169
2170         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2171                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2172                 !kvm_vcpu_apicv_active(vcpu))
2173                 return;
2174
2175         do {
2176                 old.control = new.control = pi_desc->control;
2177
2178                 /*
2179                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2180                  * are two possible cases:
2181                  * 1. After running 'pre_block', context switch
2182                  *    happened. For this case, 'sn' was set in
2183                  *    vmx_vcpu_put(), so we need to clear it here.
2184                  * 2. After running 'pre_block', we were blocked,
2185                  *    and woken up by some other guy. For this case,
2186                  *    we don't need to do anything, 'pi_post_block'
2187                  *    will do everything for us. However, we cannot
2188                  *    check whether it is case #1 or case #2 here
2189                  *    (maybe, not needed), so we also clear sn here,
2190                  *    I think it is not a big deal.
2191                  */
2192                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2193                         if (vcpu->cpu != cpu) {
2194                                 dest = cpu_physical_id(cpu);
2195
2196                                 if (x2apic_enabled())
2197                                         new.ndst = dest;
2198                                 else
2199                                         new.ndst = (dest << 8) & 0xFF00;
2200                         }
2201
2202                         /* set 'NV' to 'notification vector' */
2203                         new.nv = POSTED_INTR_VECTOR;
2204                 }
2205
2206                 /* Allow posting non-urgent interrupts */
2207                 new.sn = 0;
2208         } while (cmpxchg(&pi_desc->control, old.control,
2209                         new.control) != old.control);
2210 }
2211
2212 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2213 {
2214         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2215         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2216 }
2217
2218 /*
2219  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2220  * vcpu mutex is already taken.
2221  */
2222 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2223 {
2224         struct vcpu_vmx *vmx = to_vmx(vcpu);
2225         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2226         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2227
2228         if (!vmm_exclusive)
2229                 kvm_cpu_vmxon(phys_addr);
2230         else if (!already_loaded)
2231                 loaded_vmcs_clear(vmx->loaded_vmcs);
2232
2233         if (!already_loaded) {
2234                 local_irq_disable();
2235                 crash_disable_local_vmclear(cpu);
2236
2237                 /*
2238                  * Read loaded_vmcs->cpu should be before fetching
2239                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2240                  * See the comments in __loaded_vmcs_clear().
2241                  */
2242                 smp_rmb();
2243
2244                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2245                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2246                 crash_enable_local_vmclear(cpu);
2247                 local_irq_enable();
2248         }
2249
2250         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2251                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2252                 vmcs_load(vmx->loaded_vmcs->vmcs);
2253         }
2254
2255         if (!already_loaded) {
2256                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2257                 unsigned long sysenter_esp;
2258
2259                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2260
2261                 /*
2262                  * Linux uses per-cpu TSS and GDT, so set these when switching
2263                  * processors.
2264                  */
2265                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2266                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2267
2268                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2269                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2270
2271                 vmx->loaded_vmcs->cpu = cpu;
2272         }
2273
2274         /* Setup TSC multiplier */
2275         if (kvm_has_tsc_control &&
2276             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2277                 decache_tsc_multiplier(vmx);
2278
2279         vmx_vcpu_pi_load(vcpu, cpu);
2280         vmx->host_pkru = read_pkru();
2281 }
2282
2283 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2284 {
2285         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2286
2287         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2288                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2289                 !kvm_vcpu_apicv_active(vcpu))
2290                 return;
2291
2292         /* Set SN when the vCPU is preempted */
2293         if (vcpu->preempted)
2294                 pi_set_sn(pi_desc);
2295 }
2296
2297 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2298 {
2299         vmx_vcpu_pi_put(vcpu);
2300
2301         __vmx_load_host_state(to_vmx(vcpu));
2302         if (!vmm_exclusive) {
2303                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2304                 vcpu->cpu = -1;
2305                 kvm_cpu_vmxoff();
2306         }
2307 }
2308
2309 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2310 {
2311         ulong cr0;
2312
2313         if (vcpu->fpu_active)
2314                 return;
2315         vcpu->fpu_active = 1;
2316         cr0 = vmcs_readl(GUEST_CR0);
2317         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2318         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2319         vmcs_writel(GUEST_CR0, cr0);
2320         update_exception_bitmap(vcpu);
2321         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2322         if (is_guest_mode(vcpu))
2323                 vcpu->arch.cr0_guest_owned_bits &=
2324                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2325         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2326 }
2327
2328 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2329
2330 /*
2331  * Return the cr0 value that a nested guest would read. This is a combination
2332  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2333  * its hypervisor (cr0_read_shadow).
2334  */
2335 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2336 {
2337         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2338                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2339 }
2340 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2341 {
2342         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2343                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2344 }
2345
2346 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2347 {
2348         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2349          * set this *before* calling this function.
2350          */
2351         vmx_decache_cr0_guest_bits(vcpu);
2352         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2353         update_exception_bitmap(vcpu);
2354         vcpu->arch.cr0_guest_owned_bits = 0;
2355         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2356         if (is_guest_mode(vcpu)) {
2357                 /*
2358                  * L1's specified read shadow might not contain the TS bit,
2359                  * so now that we turned on shadowing of this bit, we need to
2360                  * set this bit of the shadow. Like in nested_vmx_run we need
2361                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2362                  * up-to-date here because we just decached cr0.TS (and we'll
2363                  * only update vmcs12->guest_cr0 on nested exit).
2364                  */
2365                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2366                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2367                         (vcpu->arch.cr0 & X86_CR0_TS);
2368                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2369         } else
2370                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2371 }
2372
2373 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2374 {
2375         unsigned long rflags, save_rflags;
2376
2377         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2378                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2379                 rflags = vmcs_readl(GUEST_RFLAGS);
2380                 if (to_vmx(vcpu)->rmode.vm86_active) {
2381                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2382                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2383                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2384                 }
2385                 to_vmx(vcpu)->rflags = rflags;
2386         }
2387         return to_vmx(vcpu)->rflags;
2388 }
2389
2390 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2391 {
2392         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2393         to_vmx(vcpu)->rflags = rflags;
2394         if (to_vmx(vcpu)->rmode.vm86_active) {
2395                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2396                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2397         }
2398         vmcs_writel(GUEST_RFLAGS, rflags);
2399 }
2400
2401 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2402 {
2403         return to_vmx(vcpu)->guest_pkru;
2404 }
2405
2406 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2407 {
2408         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2409         int ret = 0;
2410
2411         if (interruptibility & GUEST_INTR_STATE_STI)
2412                 ret |= KVM_X86_SHADOW_INT_STI;
2413         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2414                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2415
2416         return ret;
2417 }
2418
2419 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2420 {
2421         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2422         u32 interruptibility = interruptibility_old;
2423
2424         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2425
2426         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2427                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2428         else if (mask & KVM_X86_SHADOW_INT_STI)
2429                 interruptibility |= GUEST_INTR_STATE_STI;
2430
2431         if ((interruptibility != interruptibility_old))
2432                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2433 }
2434
2435 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2436 {
2437         unsigned long rip;
2438
2439         rip = kvm_rip_read(vcpu);
2440         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2441         kvm_rip_write(vcpu, rip);
2442
2443         /* skipping an emulated instruction also counts */
2444         vmx_set_interrupt_shadow(vcpu, 0);
2445 }
2446
2447 /*
2448  * KVM wants to inject page-faults which it got to the guest. This function
2449  * checks whether in a nested guest, we need to inject them to L1 or L2.
2450  */
2451 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2452 {
2453         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2454
2455         if (!(vmcs12->exception_bitmap & (1u << nr)))
2456                 return 0;
2457
2458         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2459                           vmcs_read32(VM_EXIT_INTR_INFO),
2460                           vmcs_readl(EXIT_QUALIFICATION));
2461         return 1;
2462 }
2463
2464 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2465                                 bool has_error_code, u32 error_code,
2466                                 bool reinject)
2467 {
2468         struct vcpu_vmx *vmx = to_vmx(vcpu);
2469         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2470
2471         if (!reinject && is_guest_mode(vcpu) &&
2472             nested_vmx_check_exception(vcpu, nr))
2473                 return;
2474
2475         if (has_error_code) {
2476                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2477                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2478         }
2479
2480         if (vmx->rmode.vm86_active) {
2481                 int inc_eip = 0;
2482                 if (kvm_exception_is_soft(nr))
2483                         inc_eip = vcpu->arch.event_exit_inst_len;
2484                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2485                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2486                 return;
2487         }
2488
2489         if (kvm_exception_is_soft(nr)) {
2490                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2491                              vmx->vcpu.arch.event_exit_inst_len);
2492                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2493         } else
2494                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2495
2496         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2497 }
2498
2499 static bool vmx_rdtscp_supported(void)
2500 {
2501         return cpu_has_vmx_rdtscp();
2502 }
2503
2504 static bool vmx_invpcid_supported(void)
2505 {
2506         return cpu_has_vmx_invpcid() && enable_ept;
2507 }
2508
2509 /*
2510  * Swap MSR entry in host/guest MSR entry array.
2511  */
2512 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2513 {
2514         struct shared_msr_entry tmp;
2515
2516         tmp = vmx->guest_msrs[to];
2517         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2518         vmx->guest_msrs[from] = tmp;
2519 }
2520
2521 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2522 {
2523         unsigned long *msr_bitmap;
2524
2525         if (is_guest_mode(vcpu))
2526                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2527         else if (cpu_has_secondary_exec_ctrls() &&
2528                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2529                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2530                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2531                         if (is_long_mode(vcpu))
2532                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2533                         else
2534                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2535                 } else {
2536                         if (is_long_mode(vcpu))
2537                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2538                         else
2539                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2540                 }
2541         } else {
2542                 if (is_long_mode(vcpu))
2543                         msr_bitmap = vmx_msr_bitmap_longmode;
2544                 else
2545                         msr_bitmap = vmx_msr_bitmap_legacy;
2546         }
2547
2548         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2549 }
2550
2551 /*
2552  * Set up the vmcs to automatically save and restore system
2553  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2554  * mode, as fiddling with msrs is very expensive.
2555  */
2556 static void setup_msrs(struct vcpu_vmx *vmx)
2557 {
2558         int save_nmsrs, index;
2559
2560         save_nmsrs = 0;
2561 #ifdef CONFIG_X86_64
2562         if (is_long_mode(&vmx->vcpu)) {
2563                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2564                 if (index >= 0)
2565                         move_msr_up(vmx, index, save_nmsrs++);
2566                 index = __find_msr_index(vmx, MSR_LSTAR);
2567                 if (index >= 0)
2568                         move_msr_up(vmx, index, save_nmsrs++);
2569                 index = __find_msr_index(vmx, MSR_CSTAR);
2570                 if (index >= 0)
2571                         move_msr_up(vmx, index, save_nmsrs++);
2572                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2573                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2574                         move_msr_up(vmx, index, save_nmsrs++);
2575                 /*
2576                  * MSR_STAR is only needed on long mode guests, and only
2577                  * if efer.sce is enabled.
2578                  */
2579                 index = __find_msr_index(vmx, MSR_STAR);
2580                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2581                         move_msr_up(vmx, index, save_nmsrs++);
2582         }
2583 #endif
2584         index = __find_msr_index(vmx, MSR_EFER);
2585         if (index >= 0 && update_transition_efer(vmx, index))
2586                 move_msr_up(vmx, index, save_nmsrs++);
2587
2588         vmx->save_nmsrs = save_nmsrs;
2589
2590         if (cpu_has_vmx_msr_bitmap())
2591                 vmx_set_msr_bitmap(&vmx->vcpu);
2592 }
2593
2594 /*
2595  * reads and returns guest's timestamp counter "register"
2596  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2597  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2598  */
2599 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2600 {
2601         u64 host_tsc, tsc_offset;
2602
2603         host_tsc = rdtsc();
2604         tsc_offset = vmcs_read64(TSC_OFFSET);
2605         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2606 }
2607
2608 /*
2609  * writes 'offset' into guest's timestamp counter offset register
2610  */
2611 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2612 {
2613         if (is_guest_mode(vcpu)) {
2614                 /*
2615                  * We're here if L1 chose not to trap WRMSR to TSC. According
2616                  * to the spec, this should set L1's TSC; The offset that L1
2617                  * set for L2 remains unchanged, and still needs to be added
2618                  * to the newly set TSC to get L2's TSC.
2619                  */
2620                 struct vmcs12 *vmcs12;
2621                 /* recalculate vmcs02.TSC_OFFSET: */
2622                 vmcs12 = get_vmcs12(vcpu);
2623                 vmcs_write64(TSC_OFFSET, offset +
2624                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2625                          vmcs12->tsc_offset : 0));
2626         } else {
2627                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2628                                            vmcs_read64(TSC_OFFSET), offset);
2629                 vmcs_write64(TSC_OFFSET, offset);
2630         }
2631 }
2632
2633 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2634 {
2635         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2636         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2637 }
2638
2639 /*
2640  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2641  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2642  * all guests if the "nested" module option is off, and can also be disabled
2643  * for a single guest by disabling its VMX cpuid bit.
2644  */
2645 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2646 {
2647         return nested && guest_cpuid_has_vmx(vcpu);
2648 }
2649
2650 /*
2651  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2652  * returned for the various VMX controls MSRs when nested VMX is enabled.
2653  * The same values should also be used to verify that vmcs12 control fields are
2654  * valid during nested entry from L1 to L2.
2655  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2656  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2657  * bit in the high half is on if the corresponding bit in the control field
2658  * may be on. See also vmx_control_verify().
2659  */
2660 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2661 {
2662         /*
2663          * Note that as a general rule, the high half of the MSRs (bits in
2664          * the control fields which may be 1) should be initialized by the
2665          * intersection of the underlying hardware's MSR (i.e., features which
2666          * can be supported) and the list of features we want to expose -
2667          * because they are known to be properly supported in our code.
2668          * Also, usually, the low half of the MSRs (bits which must be 1) can
2669          * be set to 0, meaning that L1 may turn off any of these bits. The
2670          * reason is that if one of these bits is necessary, it will appear
2671          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2672          * fields of vmcs01 and vmcs02, will turn these bits off - and
2673          * nested_vmx_exit_handled() will not pass related exits to L1.
2674          * These rules have exceptions below.
2675          */
2676
2677         /* pin-based controls */
2678         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2679                 vmx->nested.nested_vmx_pinbased_ctls_low,
2680                 vmx->nested.nested_vmx_pinbased_ctls_high);
2681         vmx->nested.nested_vmx_pinbased_ctls_low |=
2682                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2683         vmx->nested.nested_vmx_pinbased_ctls_high &=
2684                 PIN_BASED_EXT_INTR_MASK |
2685                 PIN_BASED_NMI_EXITING |
2686                 PIN_BASED_VIRTUAL_NMIS;
2687         vmx->nested.nested_vmx_pinbased_ctls_high |=
2688                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2689                 PIN_BASED_VMX_PREEMPTION_TIMER;
2690         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2691                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2692                         PIN_BASED_POSTED_INTR;
2693
2694         /* exit controls */
2695         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2696                 vmx->nested.nested_vmx_exit_ctls_low,
2697                 vmx->nested.nested_vmx_exit_ctls_high);
2698         vmx->nested.nested_vmx_exit_ctls_low =
2699                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2700
2701         vmx->nested.nested_vmx_exit_ctls_high &=
2702 #ifdef CONFIG_X86_64
2703                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2704 #endif
2705                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2706         vmx->nested.nested_vmx_exit_ctls_high |=
2707                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2708                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2709                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2710
2711         if (kvm_mpx_supported())
2712                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2713
2714         /* We support free control of debug control saving. */
2715         vmx->nested.nested_vmx_true_exit_ctls_low =
2716                 vmx->nested.nested_vmx_exit_ctls_low &
2717                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2718
2719         /* entry controls */
2720         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2721                 vmx->nested.nested_vmx_entry_ctls_low,
2722                 vmx->nested.nested_vmx_entry_ctls_high);
2723         vmx->nested.nested_vmx_entry_ctls_low =
2724                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2725         vmx->nested.nested_vmx_entry_ctls_high &=
2726 #ifdef CONFIG_X86_64
2727                 VM_ENTRY_IA32E_MODE |
2728 #endif
2729                 VM_ENTRY_LOAD_IA32_PAT;
2730         vmx->nested.nested_vmx_entry_ctls_high |=
2731                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2732         if (kvm_mpx_supported())
2733                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2734
2735         /* We support free control of debug control loading. */
2736         vmx->nested.nested_vmx_true_entry_ctls_low =
2737                 vmx->nested.nested_vmx_entry_ctls_low &
2738                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2739
2740         /* cpu-based controls */
2741         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2742                 vmx->nested.nested_vmx_procbased_ctls_low,
2743                 vmx->nested.nested_vmx_procbased_ctls_high);
2744         vmx->nested.nested_vmx_procbased_ctls_low =
2745                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2746         vmx->nested.nested_vmx_procbased_ctls_high &=
2747                 CPU_BASED_VIRTUAL_INTR_PENDING |
2748                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2749                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2750                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2751                 CPU_BASED_CR3_STORE_EXITING |
2752 #ifdef CONFIG_X86_64
2753                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2754 #endif
2755                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2756                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2757                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2758                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2759                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2760         /*
2761          * We can allow some features even when not supported by the
2762          * hardware. For example, L1 can specify an MSR bitmap - and we
2763          * can use it to avoid exits to L1 - even when L0 runs L2
2764          * without MSR bitmaps.
2765          */
2766         vmx->nested.nested_vmx_procbased_ctls_high |=
2767                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2768                 CPU_BASED_USE_MSR_BITMAPS;
2769
2770         /* We support free control of CR3 access interception. */
2771         vmx->nested.nested_vmx_true_procbased_ctls_low =
2772                 vmx->nested.nested_vmx_procbased_ctls_low &
2773                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2774
2775         /* secondary cpu-based controls */
2776         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2777                 vmx->nested.nested_vmx_secondary_ctls_low,
2778                 vmx->nested.nested_vmx_secondary_ctls_high);
2779         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2780         vmx->nested.nested_vmx_secondary_ctls_high &=
2781                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2782                 SECONDARY_EXEC_RDTSCP |
2783                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2784                 SECONDARY_EXEC_ENABLE_VPID |
2785                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2786                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2787                 SECONDARY_EXEC_WBINVD_EXITING |
2788                 SECONDARY_EXEC_XSAVES;
2789
2790         if (enable_ept) {
2791                 /* nested EPT: emulate EPT also to L1 */
2792                 vmx->nested.nested_vmx_secondary_ctls_high |=
2793                         SECONDARY_EXEC_ENABLE_EPT;
2794                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2795                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2796                          VMX_EPT_INVEPT_BIT;
2797                 if (cpu_has_vmx_ept_execute_only())
2798                         vmx->nested.nested_vmx_ept_caps |=
2799                                 VMX_EPT_EXECUTE_ONLY_BIT;
2800                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2801                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2802                         VMX_EPT_EXTENT_CONTEXT_BIT;
2803         } else
2804                 vmx->nested.nested_vmx_ept_caps = 0;
2805
2806         /*
2807          * Old versions of KVM use the single-context version without
2808          * checking for support, so declare that it is supported even
2809          * though it is treated as global context.  The alternative is
2810          * not failing the single-context invvpid, and it is worse.
2811          */
2812         if (enable_vpid)
2813                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2814                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2815                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2816         else
2817                 vmx->nested.nested_vmx_vpid_caps = 0;
2818
2819         if (enable_unrestricted_guest)
2820                 vmx->nested.nested_vmx_secondary_ctls_high |=
2821                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2822
2823         /* miscellaneous data */
2824         rdmsr(MSR_IA32_VMX_MISC,
2825                 vmx->nested.nested_vmx_misc_low,
2826                 vmx->nested.nested_vmx_misc_high);
2827         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2828         vmx->nested.nested_vmx_misc_low |=
2829                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2830                 VMX_MISC_ACTIVITY_HLT;
2831         vmx->nested.nested_vmx_misc_high = 0;
2832 }
2833
2834 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2835 {
2836         /*
2837          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2838          */
2839         return ((control & high) | low) == control;
2840 }
2841
2842 static inline u64 vmx_control_msr(u32 low, u32 high)
2843 {
2844         return low | ((u64)high << 32);
2845 }
2846
2847 /* Returns 0 on success, non-0 otherwise. */
2848 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2849 {
2850         struct vcpu_vmx *vmx = to_vmx(vcpu);
2851
2852         switch (msr_index) {
2853         case MSR_IA32_VMX_BASIC:
2854                 /*
2855                  * This MSR reports some information about VMX support. We
2856                  * should return information about the VMX we emulate for the
2857                  * guest, and the VMCS structure we give it - not about the
2858                  * VMX support of the underlying hardware.
2859                  */
2860                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2861                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2862                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2863                 if (cpu_has_vmx_basic_inout())
2864                         *pdata |= VMX_BASIC_INOUT;
2865                 break;
2866         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2867         case MSR_IA32_VMX_PINBASED_CTLS:
2868                 *pdata = vmx_control_msr(
2869                         vmx->nested.nested_vmx_pinbased_ctls_low,
2870                         vmx->nested.nested_vmx_pinbased_ctls_high);
2871                 break;
2872         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2873                 *pdata = vmx_control_msr(
2874                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2875                         vmx->nested.nested_vmx_procbased_ctls_high);
2876                 break;
2877         case MSR_IA32_VMX_PROCBASED_CTLS:
2878                 *pdata = vmx_control_msr(
2879                         vmx->nested.nested_vmx_procbased_ctls_low,
2880                         vmx->nested.nested_vmx_procbased_ctls_high);
2881                 break;
2882         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2883                 *pdata = vmx_control_msr(
2884                         vmx->nested.nested_vmx_true_exit_ctls_low,
2885                         vmx->nested.nested_vmx_exit_ctls_high);
2886                 break;
2887         case MSR_IA32_VMX_EXIT_CTLS:
2888                 *pdata = vmx_control_msr(
2889                         vmx->nested.nested_vmx_exit_ctls_low,
2890                         vmx->nested.nested_vmx_exit_ctls_high);
2891                 break;
2892         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2893                 *pdata = vmx_control_msr(
2894                         vmx->nested.nested_vmx_true_entry_ctls_low,
2895                         vmx->nested.nested_vmx_entry_ctls_high);
2896                 break;
2897         case MSR_IA32_VMX_ENTRY_CTLS:
2898                 *pdata = vmx_control_msr(
2899                         vmx->nested.nested_vmx_entry_ctls_low,
2900                         vmx->nested.nested_vmx_entry_ctls_high);
2901                 break;
2902         case MSR_IA32_VMX_MISC:
2903                 *pdata = vmx_control_msr(
2904                         vmx->nested.nested_vmx_misc_low,
2905                         vmx->nested.nested_vmx_misc_high);
2906                 break;
2907         /*
2908          * These MSRs specify bits which the guest must keep fixed (on or off)
2909          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2910          * We picked the standard core2 setting.
2911          */
2912 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2913 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2914         case MSR_IA32_VMX_CR0_FIXED0:
2915                 *pdata = VMXON_CR0_ALWAYSON;
2916                 break;
2917         case MSR_IA32_VMX_CR0_FIXED1:
2918                 *pdata = -1ULL;
2919                 break;
2920         case MSR_IA32_VMX_CR4_FIXED0:
2921                 *pdata = VMXON_CR4_ALWAYSON;
2922                 break;
2923         case MSR_IA32_VMX_CR4_FIXED1:
2924                 *pdata = -1ULL;
2925                 break;
2926         case MSR_IA32_VMX_VMCS_ENUM:
2927                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2928                 break;
2929         case MSR_IA32_VMX_PROCBASED_CTLS2:
2930                 *pdata = vmx_control_msr(
2931                         vmx->nested.nested_vmx_secondary_ctls_low,
2932                         vmx->nested.nested_vmx_secondary_ctls_high);
2933                 break;
2934         case MSR_IA32_VMX_EPT_VPID_CAP:
2935                 *pdata = vmx->nested.nested_vmx_ept_caps |
2936                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2937                 break;
2938         default:
2939                 return 1;
2940         }
2941
2942         return 0;
2943 }
2944
2945 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2946                                                  uint64_t val)
2947 {
2948         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2949
2950         return !(val & ~valid_bits);
2951 }
2952
2953 /*
2954  * Reads an msr value (of 'msr_index') into 'pdata'.
2955  * Returns 0 on success, non-0 otherwise.
2956  * Assumes vcpu_load() was already called.
2957  */
2958 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2959 {
2960         struct shared_msr_entry *msr;
2961
2962         switch (msr_info->index) {
2963 #ifdef CONFIG_X86_64
2964         case MSR_FS_BASE:
2965                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2966                 break;
2967         case MSR_GS_BASE:
2968                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2969                 break;
2970         case MSR_KERNEL_GS_BASE:
2971                 vmx_load_host_state(to_vmx(vcpu));
2972                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2973                 break;
2974 #endif
2975         case MSR_EFER:
2976                 return kvm_get_msr_common(vcpu, msr_info);
2977         case MSR_IA32_TSC:
2978                 msr_info->data = guest_read_tsc(vcpu);
2979                 break;
2980         case MSR_IA32_SYSENTER_CS:
2981                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2982                 break;
2983         case MSR_IA32_SYSENTER_EIP:
2984                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2985                 break;
2986         case MSR_IA32_SYSENTER_ESP:
2987                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2988                 break;
2989         case MSR_IA32_BNDCFGS:
2990                 if (!kvm_mpx_supported())
2991                         return 1;
2992                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2993                 break;
2994         case MSR_IA32_MCG_EXT_CTL:
2995                 if (!msr_info->host_initiated &&
2996                     !(to_vmx(vcpu)->msr_ia32_feature_control &
2997                       FEATURE_CONTROL_LMCE))
2998                         return 1;
2999                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3000                 break;
3001         case MSR_IA32_FEATURE_CONTROL:
3002                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3003                 break;
3004         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3005                 if (!nested_vmx_allowed(vcpu))
3006                         return 1;
3007                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3008         case MSR_IA32_XSS:
3009                 if (!vmx_xsaves_supported())
3010                         return 1;
3011                 msr_info->data = vcpu->arch.ia32_xss;
3012                 break;
3013         case MSR_TSC_AUX:
3014                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3015                         return 1;
3016                 /* Otherwise falls through */
3017         default:
3018                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3019                 if (msr) {
3020                         msr_info->data = msr->data;
3021                         break;
3022                 }
3023                 return kvm_get_msr_common(vcpu, msr_info);
3024         }
3025
3026         return 0;
3027 }
3028
3029 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3030
3031 /*
3032  * Writes msr value into into the appropriate "register".
3033  * Returns 0 on success, non-0 otherwise.
3034  * Assumes vcpu_load() was already called.
3035  */
3036 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3037 {
3038         struct vcpu_vmx *vmx = to_vmx(vcpu);
3039         struct shared_msr_entry *msr;
3040         int ret = 0;
3041         u32 msr_index = msr_info->index;
3042         u64 data = msr_info->data;
3043
3044         switch (msr_index) {
3045         case MSR_EFER:
3046                 ret = kvm_set_msr_common(vcpu, msr_info);
3047                 break;
3048 #ifdef CONFIG_X86_64
3049         case MSR_FS_BASE:
3050                 vmx_segment_cache_clear(vmx);
3051                 vmcs_writel(GUEST_FS_BASE, data);
3052                 break;
3053         case MSR_GS_BASE:
3054                 vmx_segment_cache_clear(vmx);
3055                 vmcs_writel(GUEST_GS_BASE, data);
3056                 break;
3057         case MSR_KERNEL_GS_BASE:
3058                 vmx_load_host_state(vmx);
3059                 vmx->msr_guest_kernel_gs_base = data;
3060                 break;
3061 #endif
3062         case MSR_IA32_SYSENTER_CS:
3063                 vmcs_write32(GUEST_SYSENTER_CS, data);
3064                 break;
3065         case MSR_IA32_SYSENTER_EIP:
3066                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3067                 break;
3068         case MSR_IA32_SYSENTER_ESP:
3069                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3070                 break;
3071         case MSR_IA32_BNDCFGS:
3072                 if (!kvm_mpx_supported())
3073                         return 1;
3074                 vmcs_write64(GUEST_BNDCFGS, data);
3075                 break;
3076         case MSR_IA32_TSC:
3077                 kvm_write_tsc(vcpu, msr_info);
3078                 break;
3079         case MSR_IA32_CR_PAT:
3080                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3081                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3082                                 return 1;
3083                         vmcs_write64(GUEST_IA32_PAT, data);
3084                         vcpu->arch.pat = data;
3085                         break;
3086                 }
3087                 ret = kvm_set_msr_common(vcpu, msr_info);
3088                 break;
3089         case MSR_IA32_TSC_ADJUST:
3090                 ret = kvm_set_msr_common(vcpu, msr_info);
3091                 break;
3092         case MSR_IA32_MCG_EXT_CTL:
3093                 if ((!msr_info->host_initiated &&
3094                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3095                        FEATURE_CONTROL_LMCE)) ||
3096                     (data & ~MCG_EXT_CTL_LMCE_EN))
3097                         return 1;
3098                 vcpu->arch.mcg_ext_ctl = data;
3099                 break;
3100         case MSR_IA32_FEATURE_CONTROL:
3101                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3102                     (to_vmx(vcpu)->msr_ia32_feature_control &
3103                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3104                         return 1;
3105                 vmx->msr_ia32_feature_control = data;
3106                 if (msr_info->host_initiated && data == 0)
3107                         vmx_leave_nested(vcpu);
3108                 break;
3109         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3110                 return 1; /* they are read-only */
3111         case MSR_IA32_XSS:
3112                 if (!vmx_xsaves_supported())
3113                         return 1;
3114                 /*
3115                  * The only supported bit as of Skylake is bit 8, but
3116                  * it is not supported on KVM.
3117                  */
3118                 if (data != 0)
3119                         return 1;
3120                 vcpu->arch.ia32_xss = data;
3121                 if (vcpu->arch.ia32_xss != host_xss)
3122                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3123                                 vcpu->arch.ia32_xss, host_xss);
3124                 else
3125                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3126                 break;
3127         case MSR_TSC_AUX:
3128                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3129                         return 1;
3130                 /* Check reserved bit, higher 32 bits should be zero */
3131                 if ((data >> 32) != 0)
3132                         return 1;
3133                 /* Otherwise falls through */
3134         default:
3135                 msr = find_msr_entry(vmx, msr_index);
3136                 if (msr) {
3137                         u64 old_msr_data = msr->data;
3138                         msr->data = data;
3139                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3140                                 preempt_disable();
3141                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3142                                                          msr->mask);
3143                                 preempt_enable();
3144                                 if (ret)
3145                                         msr->data = old_msr_data;
3146                         }
3147                         break;
3148                 }
3149                 ret = kvm_set_msr_common(vcpu, msr_info);
3150         }
3151
3152         return ret;
3153 }
3154
3155 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3156 {
3157         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3158         switch (reg) {
3159         case VCPU_REGS_RSP:
3160                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3161                 break;
3162         case VCPU_REGS_RIP:
3163                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3164                 break;
3165         case VCPU_EXREG_PDPTR:
3166                 if (enable_ept)
3167                         ept_save_pdptrs(vcpu);
3168                 break;
3169         default:
3170                 break;
3171         }
3172 }
3173
3174 static __init int cpu_has_kvm_support(void)
3175 {
3176         return cpu_has_vmx();
3177 }
3178
3179 static __init int vmx_disabled_by_bios(void)
3180 {
3181         u64 msr;
3182
3183         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3184         if (msr & FEATURE_CONTROL_LOCKED) {
3185                 /* launched w/ TXT and VMX disabled */
3186                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3187                         && tboot_enabled())
3188                         return 1;
3189                 /* launched w/o TXT and VMX only enabled w/ TXT */
3190                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3191                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3192                         && !tboot_enabled()) {
3193                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3194                                 "activate TXT before enabling KVM\n");
3195                         return 1;
3196                 }
3197                 /* launched w/o TXT and VMX disabled */
3198                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3199                         && !tboot_enabled())
3200                         return 1;
3201         }
3202
3203         return 0;
3204 }
3205
3206 static void kvm_cpu_vmxon(u64 addr)
3207 {
3208         intel_pt_handle_vmx(1);
3209
3210         asm volatile (ASM_VMX_VMXON_RAX
3211                         : : "a"(&addr), "m"(addr)
3212                         : "memory", "cc");
3213 }
3214
3215 static int hardware_enable(void)
3216 {
3217         int cpu = raw_smp_processor_id();
3218         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3219         u64 old, test_bits;
3220
3221         if (cr4_read_shadow() & X86_CR4_VMXE)
3222                 return -EBUSY;
3223
3224         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3225         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3226         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3227
3228         /*
3229          * Now we can enable the vmclear operation in kdump
3230          * since the loaded_vmcss_on_cpu list on this cpu
3231          * has been initialized.
3232          *
3233          * Though the cpu is not in VMX operation now, there
3234          * is no problem to enable the vmclear operation
3235          * for the loaded_vmcss_on_cpu list is empty!
3236          */
3237         crash_enable_local_vmclear(cpu);
3238
3239         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3240
3241         test_bits = FEATURE_CONTROL_LOCKED;
3242         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3243         if (tboot_enabled())
3244                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3245
3246         if ((old & test_bits) != test_bits) {
3247                 /* enable and lock */
3248                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3249         }
3250         cr4_set_bits(X86_CR4_VMXE);
3251
3252         if (vmm_exclusive) {
3253                 kvm_cpu_vmxon(phys_addr);
3254                 ept_sync_global();
3255         }
3256
3257         native_store_gdt(this_cpu_ptr(&host_gdt));
3258
3259         return 0;
3260 }
3261
3262 static void vmclear_local_loaded_vmcss(void)
3263 {
3264         int cpu = raw_smp_processor_id();
3265         struct loaded_vmcs *v, *n;
3266
3267         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3268                                  loaded_vmcss_on_cpu_link)
3269                 __loaded_vmcs_clear(v);
3270 }
3271
3272
3273 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3274  * tricks.
3275  */
3276 static void kvm_cpu_vmxoff(void)
3277 {
3278         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3279
3280         intel_pt_handle_vmx(0);
3281 }
3282
3283 static void hardware_disable(void)
3284 {
3285         if (vmm_exclusive) {
3286                 vmclear_local_loaded_vmcss();
3287                 kvm_cpu_vmxoff();
3288         }
3289         cr4_clear_bits(X86_CR4_VMXE);
3290 }
3291
3292 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3293                                       u32 msr, u32 *result)
3294 {
3295         u32 vmx_msr_low, vmx_msr_high;
3296         u32 ctl = ctl_min | ctl_opt;
3297
3298         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3299
3300         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3301         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3302
3303         /* Ensure minimum (required) set of control bits are supported. */
3304         if (ctl_min & ~ctl)
3305                 return -EIO;
3306
3307         *result = ctl;
3308         return 0;
3309 }
3310
3311 static __init bool allow_1_setting(u32 msr, u32 ctl)
3312 {
3313         u32 vmx_msr_low, vmx_msr_high;
3314
3315         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3316         return vmx_msr_high & ctl;
3317 }
3318
3319 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3320 {
3321         u32 vmx_msr_low, vmx_msr_high;
3322         u32 min, opt, min2, opt2;
3323         u32 _pin_based_exec_control = 0;
3324         u32 _cpu_based_exec_control = 0;
3325         u32 _cpu_based_2nd_exec_control = 0;
3326         u32 _vmexit_control = 0;
3327         u32 _vmentry_control = 0;
3328
3329         min = CPU_BASED_HLT_EXITING |
3330 #ifdef CONFIG_X86_64
3331               CPU_BASED_CR8_LOAD_EXITING |
3332               CPU_BASED_CR8_STORE_EXITING |
3333 #endif
3334               CPU_BASED_CR3_LOAD_EXITING |
3335               CPU_BASED_CR3_STORE_EXITING |
3336               CPU_BASED_USE_IO_BITMAPS |
3337               CPU_BASED_MOV_DR_EXITING |
3338               CPU_BASED_USE_TSC_OFFSETING |
3339               CPU_BASED_MWAIT_EXITING |
3340               CPU_BASED_MONITOR_EXITING |
3341               CPU_BASED_INVLPG_EXITING |
3342               CPU_BASED_RDPMC_EXITING;
3343
3344         opt = CPU_BASED_TPR_SHADOW |
3345               CPU_BASED_USE_MSR_BITMAPS |
3346               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3347         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3348                                 &_cpu_based_exec_control) < 0)
3349                 return -EIO;
3350 #ifdef CONFIG_X86_64
3351         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3352                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3353                                            ~CPU_BASED_CR8_STORE_EXITING;
3354 #endif
3355         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3356                 min2 = 0;
3357                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3358                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3359                         SECONDARY_EXEC_WBINVD_EXITING |
3360                         SECONDARY_EXEC_ENABLE_VPID |
3361                         SECONDARY_EXEC_ENABLE_EPT |
3362                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3363                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3364                         SECONDARY_EXEC_RDTSCP |
3365                         SECONDARY_EXEC_ENABLE_INVPCID |
3366                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3367                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3368                         SECONDARY_EXEC_SHADOW_VMCS |
3369                         SECONDARY_EXEC_XSAVES |
3370                         SECONDARY_EXEC_ENABLE_PML |
3371                         SECONDARY_EXEC_TSC_SCALING;
3372                 if (adjust_vmx_controls(min2, opt2,
3373                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3374                                         &_cpu_based_2nd_exec_control) < 0)
3375                         return -EIO;
3376         }
3377 #ifndef CONFIG_X86_64
3378         if (!(_cpu_based_2nd_exec_control &
3379                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3380                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3381 #endif
3382
3383         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3384                 _cpu_based_2nd_exec_control &= ~(
3385                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3386                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3387                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3388
3389         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3390                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3391                    enabled */
3392                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3393                                              CPU_BASED_CR3_STORE_EXITING |
3394                                              CPU_BASED_INVLPG_EXITING);
3395                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3396                       vmx_capability.ept, vmx_capability.vpid);
3397         }
3398
3399         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3400 #ifdef CONFIG_X86_64
3401         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3402 #endif
3403         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3404                 VM_EXIT_CLEAR_BNDCFGS;
3405         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3406                                 &_vmexit_control) < 0)
3407                 return -EIO;
3408
3409         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3410         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3411                  PIN_BASED_VMX_PREEMPTION_TIMER;
3412         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3413                                 &_pin_based_exec_control) < 0)
3414                 return -EIO;
3415
3416         if (cpu_has_broken_vmx_preemption_timer())
3417                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3418         if (!(_cpu_based_2nd_exec_control &
3419                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3420                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3421
3422         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3423         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3424         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3425                                 &_vmentry_control) < 0)
3426                 return -EIO;
3427
3428         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3429
3430         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3431         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3432                 return -EIO;
3433
3434 #ifdef CONFIG_X86_64
3435         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3436         if (vmx_msr_high & (1u<<16))
3437                 return -EIO;
3438 #endif
3439
3440         /* Require Write-Back (WB) memory type for VMCS accesses. */
3441         if (((vmx_msr_high >> 18) & 15) != 6)
3442                 return -EIO;
3443
3444         vmcs_conf->size = vmx_msr_high & 0x1fff;
3445         vmcs_conf->order = get_order(vmcs_conf->size);
3446         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3447         vmcs_conf->revision_id = vmx_msr_low;
3448
3449         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3450         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3451         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3452         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3453         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3454
3455         cpu_has_load_ia32_efer =
3456                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3457                                 VM_ENTRY_LOAD_IA32_EFER)
3458                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3459                                    VM_EXIT_LOAD_IA32_EFER);
3460
3461         cpu_has_load_perf_global_ctrl =
3462                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3463                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3464                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3465                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3466
3467         /*
3468          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3469          * but due to errata below it can't be used. Workaround is to use
3470          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3471          *
3472          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3473          *
3474          * AAK155             (model 26)
3475          * AAP115             (model 30)
3476          * AAT100             (model 37)
3477          * BC86,AAY89,BD102   (model 44)
3478          * BA97               (model 46)
3479          *
3480          */
3481         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3482                 switch (boot_cpu_data.x86_model) {
3483                 case 26:
3484                 case 30:
3485                 case 37:
3486                 case 44:
3487                 case 46:
3488                         cpu_has_load_perf_global_ctrl = false;
3489                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3490                                         "does not work properly. Using workaround\n");
3491                         break;
3492                 default:
3493                         break;
3494                 }
3495         }
3496
3497         if (boot_cpu_has(X86_FEATURE_XSAVES))
3498                 rdmsrl(MSR_IA32_XSS, host_xss);
3499
3500         return 0;
3501 }
3502
3503 static struct vmcs *alloc_vmcs_cpu(int cpu)
3504 {
3505         int node = cpu_to_node(cpu);
3506         struct page *pages;
3507         struct vmcs *vmcs;
3508
3509         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3510         if (!pages)
3511                 return NULL;
3512         vmcs = page_address(pages);
3513         memset(vmcs, 0, vmcs_config.size);
3514         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3515         return vmcs;
3516 }
3517
3518 static struct vmcs *alloc_vmcs(void)
3519 {
3520         return alloc_vmcs_cpu(raw_smp_processor_id());
3521 }
3522
3523 static void free_vmcs(struct vmcs *vmcs)
3524 {
3525         free_pages((unsigned long)vmcs, vmcs_config.order);
3526 }
3527
3528 /*
3529  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3530  */
3531 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3532 {
3533         if (!loaded_vmcs->vmcs)
3534                 return;
3535         loaded_vmcs_clear(loaded_vmcs);
3536         free_vmcs(loaded_vmcs->vmcs);
3537         loaded_vmcs->vmcs = NULL;
3538         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3539 }
3540
3541 static void free_kvm_area(void)
3542 {
3543         int cpu;
3544
3545         for_each_possible_cpu(cpu) {
3546                 free_vmcs(per_cpu(vmxarea, cpu));
3547                 per_cpu(vmxarea, cpu) = NULL;
3548         }
3549 }
3550
3551 static void init_vmcs_shadow_fields(void)
3552 {
3553         int i, j;
3554
3555         /* No checks for read only fields yet */
3556
3557         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3558                 switch (shadow_read_write_fields[i]) {
3559                 case GUEST_BNDCFGS:
3560                         if (!kvm_mpx_supported())
3561                                 continue;
3562                         break;
3563                 default:
3564                         break;
3565                 }
3566
3567                 if (j < i)
3568                         shadow_read_write_fields[j] =
3569                                 shadow_read_write_fields[i];
3570                 j++;
3571         }
3572         max_shadow_read_write_fields = j;
3573
3574         /* shadowed fields guest access without vmexit */
3575         for (i = 0; i < max_shadow_read_write_fields; i++) {
3576                 clear_bit(shadow_read_write_fields[i],
3577                           vmx_vmwrite_bitmap);
3578                 clear_bit(shadow_read_write_fields[i],
3579                           vmx_vmread_bitmap);
3580         }
3581         for (i = 0; i < max_shadow_read_only_fields; i++)
3582                 clear_bit(shadow_read_only_fields[i],
3583                           vmx_vmread_bitmap);
3584 }
3585
3586 static __init int alloc_kvm_area(void)
3587 {
3588         int cpu;
3589
3590         for_each_possible_cpu(cpu) {
3591                 struct vmcs *vmcs;
3592
3593                 vmcs = alloc_vmcs_cpu(cpu);
3594                 if (!vmcs) {
3595                         free_kvm_area();
3596                         return -ENOMEM;
3597                 }
3598
3599                 per_cpu(vmxarea, cpu) = vmcs;
3600         }
3601         return 0;
3602 }
3603
3604 static bool emulation_required(struct kvm_vcpu *vcpu)
3605 {
3606         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3607 }
3608
3609 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3610                 struct kvm_segment *save)
3611 {
3612         if (!emulate_invalid_guest_state) {
3613                 /*
3614                  * CS and SS RPL should be equal during guest entry according
3615                  * to VMX spec, but in reality it is not always so. Since vcpu
3616                  * is in the middle of the transition from real mode to
3617                  * protected mode it is safe to assume that RPL 0 is a good
3618                  * default value.
3619                  */
3620                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3621                         save->selector &= ~SEGMENT_RPL_MASK;
3622                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3623                 save->s = 1;
3624         }
3625         vmx_set_segment(vcpu, save, seg);
3626 }
3627
3628 static void enter_pmode(struct kvm_vcpu *vcpu)
3629 {
3630         unsigned long flags;
3631         struct vcpu_vmx *vmx = to_vmx(vcpu);
3632
3633         /*
3634          * Update real mode segment cache. It may be not up-to-date if sement
3635          * register was written while vcpu was in a guest mode.
3636          */
3637         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3638         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3639         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3640         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3641         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3642         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3643
3644         vmx->rmode.vm86_active = 0;
3645
3646         vmx_segment_cache_clear(vmx);
3647
3648         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3649
3650         flags = vmcs_readl(GUEST_RFLAGS);
3651         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3652         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3653         vmcs_writel(GUEST_RFLAGS, flags);
3654
3655         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3656                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3657
3658         update_exception_bitmap(vcpu);
3659
3660         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3661         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3662         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3663         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3664         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3665         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3666 }
3667
3668 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3669 {
3670         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3671         struct kvm_segment var = *save;
3672
3673         var.dpl = 0x3;
3674         if (seg == VCPU_SREG_CS)
3675                 var.type = 0x3;
3676
3677         if (!emulate_invalid_guest_state) {
3678                 var.selector = var.base >> 4;
3679                 var.base = var.base & 0xffff0;
3680                 var.limit = 0xffff;
3681                 var.g = 0;
3682                 var.db = 0;
3683                 var.present = 1;
3684                 var.s = 1;
3685                 var.l = 0;
3686                 var.unusable = 0;
3687                 var.type = 0x3;
3688                 var.avl = 0;
3689                 if (save->base & 0xf)
3690                         printk_once(KERN_WARNING "kvm: segment base is not "
3691                                         "paragraph aligned when entering "
3692                                         "protected mode (seg=%d)", seg);
3693         }
3694
3695         vmcs_write16(sf->selector, var.selector);
3696         vmcs_write32(sf->base, var.base);
3697         vmcs_write32(sf->limit, var.limit);
3698         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3699 }
3700
3701 static void enter_rmode(struct kvm_vcpu *vcpu)
3702 {
3703         unsigned long flags;
3704         struct vcpu_vmx *vmx = to_vmx(vcpu);
3705
3706         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3707         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3708         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3709         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3710         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3711         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3712         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3713
3714         vmx->rmode.vm86_active = 1;
3715
3716         /*
3717          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3718          * vcpu. Warn the user that an update is overdue.
3719          */
3720         if (!vcpu->kvm->arch.tss_addr)
3721                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3722                              "called before entering vcpu\n");
3723
3724         vmx_segment_cache_clear(vmx);
3725
3726         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3727         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3728         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3729
3730         flags = vmcs_readl(GUEST_RFLAGS);
3731         vmx->rmode.save_rflags = flags;
3732
3733         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3734
3735         vmcs_writel(GUEST_RFLAGS, flags);
3736         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3737         update_exception_bitmap(vcpu);
3738
3739         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3740         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3741         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3742         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3743         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3744         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3745
3746         kvm_mmu_reset_context(vcpu);
3747 }
3748
3749 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3750 {
3751         struct vcpu_vmx *vmx = to_vmx(vcpu);
3752         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3753
3754         if (!msr)
3755                 return;
3756
3757         /*
3758          * Force kernel_gs_base reloading before EFER changes, as control
3759          * of this msr depends on is_long_mode().
3760          */
3761         vmx_load_host_state(to_vmx(vcpu));
3762         vcpu->arch.efer = efer;
3763         if (efer & EFER_LMA) {
3764                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3765                 msr->data = efer;
3766         } else {
3767                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3768
3769                 msr->data = efer & ~EFER_LME;
3770         }
3771         setup_msrs(vmx);
3772 }
3773
3774 #ifdef CONFIG_X86_64
3775
3776 static void enter_lmode(struct kvm_vcpu *vcpu)
3777 {
3778         u32 guest_tr_ar;
3779
3780         vmx_segment_cache_clear(to_vmx(vcpu));
3781
3782         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3783         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3784                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3785                                      __func__);
3786                 vmcs_write32(GUEST_TR_AR_BYTES,
3787                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3788                              | VMX_AR_TYPE_BUSY_64_TSS);
3789         }
3790         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3791 }
3792
3793 static void exit_lmode(struct kvm_vcpu *vcpu)
3794 {
3795         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3796         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3797 }
3798
3799 #endif
3800
3801 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3802 {
3803         vpid_sync_context(vpid);
3804         if (enable_ept) {
3805                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3806                         return;
3807                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3808         }
3809 }
3810
3811 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3812 {
3813         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3814 }
3815
3816 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3817 {
3818         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3819
3820         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3821         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3822 }
3823
3824 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3825 {
3826         if (enable_ept && is_paging(vcpu))
3827                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3828         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3829 }
3830
3831 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3832 {
3833         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3834
3835         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3836         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3837 }
3838
3839 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3840 {
3841         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3842
3843         if (!test_bit(VCPU_EXREG_PDPTR,
3844                       (unsigned long *)&vcpu->arch.regs_dirty))
3845                 return;
3846
3847         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3848                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3849                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3850                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3851                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3852         }
3853 }
3854
3855 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3856 {
3857         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3858
3859         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3860                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3861                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3862                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3863                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3864         }
3865
3866         __set_bit(VCPU_EXREG_PDPTR,
3867                   (unsigned long *)&vcpu->arch.regs_avail);
3868         __set_bit(VCPU_EXREG_PDPTR,
3869                   (unsigned long *)&vcpu->arch.regs_dirty);
3870 }
3871
3872 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3873
3874 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3875                                         unsigned long cr0,
3876                                         struct kvm_vcpu *vcpu)
3877 {
3878         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3879                 vmx_decache_cr3(vcpu);
3880         if (!(cr0 & X86_CR0_PG)) {
3881                 /* From paging/starting to nonpaging */
3882                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3883                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3884                              (CPU_BASED_CR3_LOAD_EXITING |
3885                               CPU_BASED_CR3_STORE_EXITING));
3886                 vcpu->arch.cr0 = cr0;
3887                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3888         } else if (!is_paging(vcpu)) {
3889                 /* From nonpaging to paging */
3890                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3891                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3892                              ~(CPU_BASED_CR3_LOAD_EXITING |
3893                                CPU_BASED_CR3_STORE_EXITING));
3894                 vcpu->arch.cr0 = cr0;
3895                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3896         }
3897
3898         if (!(cr0 & X86_CR0_WP))
3899                 *hw_cr0 &= ~X86_CR0_WP;
3900 }
3901
3902 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3903 {
3904         struct vcpu_vmx *vmx = to_vmx(vcpu);
3905         unsigned long hw_cr0;
3906
3907         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3908         if (enable_unrestricted_guest)
3909                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3910         else {
3911                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3912
3913                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3914                         enter_pmode(vcpu);
3915
3916                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3917                         enter_rmode(vcpu);
3918         }
3919
3920 #ifdef CONFIG_X86_64
3921         if (vcpu->arch.efer & EFER_LME) {
3922                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3923                         enter_lmode(vcpu);
3924                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3925                         exit_lmode(vcpu);
3926         }
3927 #endif
3928
3929         if (enable_ept)
3930                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3931
3932         if (!vcpu->fpu_active)
3933                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3934
3935         vmcs_writel(CR0_READ_SHADOW, cr0);
3936         vmcs_writel(GUEST_CR0, hw_cr0);
3937         vcpu->arch.cr0 = cr0;
3938
3939         /* depends on vcpu->arch.cr0 to be set to a new value */
3940         vmx->emulation_required = emulation_required(vcpu);
3941 }
3942
3943 static u64 construct_eptp(unsigned long root_hpa)
3944 {
3945         u64 eptp;
3946
3947         /* TODO write the value reading from MSR */
3948         eptp = VMX_EPT_DEFAULT_MT |
3949                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3950         if (enable_ept_ad_bits)
3951                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3952         eptp |= (root_hpa & PAGE_MASK);
3953
3954         return eptp;
3955 }
3956
3957 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3958 {
3959         unsigned long guest_cr3;
3960         u64 eptp;
3961
3962         guest_cr3 = cr3;
3963         if (enable_ept) {
3964                 eptp = construct_eptp(cr3);
3965                 vmcs_write64(EPT_POINTER, eptp);
3966                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3967                         guest_cr3 = kvm_read_cr3(vcpu);
3968                 else
3969                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3970                 ept_load_pdptrs(vcpu);
3971         }
3972
3973         vmx_flush_tlb(vcpu);
3974         vmcs_writel(GUEST_CR3, guest_cr3);
3975 }
3976
3977 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3978 {
3979         /*
3980          * Pass through host's Machine Check Enable value to hw_cr4, which
3981          * is in force while we are in guest mode.  Do not let guests control
3982          * this bit, even if host CR4.MCE == 0.
3983          */
3984         unsigned long hw_cr4 =
3985                 (cr4_read_shadow() & X86_CR4_MCE) |
3986                 (cr4 & ~X86_CR4_MCE) |
3987                 (to_vmx(vcpu)->rmode.vm86_active ?
3988                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3989
3990         if (cr4 & X86_CR4_VMXE) {
3991                 /*
3992                  * To use VMXON (and later other VMX instructions), a guest
3993                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3994                  * So basically the check on whether to allow nested VMX
3995                  * is here.
3996                  */
3997                 if (!nested_vmx_allowed(vcpu))
3998                         return 1;
3999         }
4000         if (to_vmx(vcpu)->nested.vmxon &&
4001             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
4002                 return 1;
4003
4004         vcpu->arch.cr4 = cr4;
4005         if (enable_ept) {
4006                 if (!is_paging(vcpu)) {
4007                         hw_cr4 &= ~X86_CR4_PAE;
4008                         hw_cr4 |= X86_CR4_PSE;
4009                 } else if (!(cr4 & X86_CR4_PAE)) {
4010                         hw_cr4 &= ~X86_CR4_PAE;
4011                 }
4012         }
4013
4014         if (!enable_unrestricted_guest && !is_paging(vcpu))
4015                 /*
4016                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4017                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4018                  * to be manually disabled when guest switches to non-paging
4019                  * mode.
4020                  *
4021                  * If !enable_unrestricted_guest, the CPU is always running
4022                  * with CR0.PG=1 and CR4 needs to be modified.
4023                  * If enable_unrestricted_guest, the CPU automatically
4024                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4025                  */
4026                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4027
4028         vmcs_writel(CR4_READ_SHADOW, cr4);
4029         vmcs_writel(GUEST_CR4, hw_cr4);
4030         return 0;
4031 }
4032
4033 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4034                             struct kvm_segment *var, int seg)
4035 {
4036         struct vcpu_vmx *vmx = to_vmx(vcpu);
4037         u32 ar;
4038
4039         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4040                 *var = vmx->rmode.segs[seg];
4041                 if (seg == VCPU_SREG_TR
4042                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4043                         return;
4044                 var->base = vmx_read_guest_seg_base(vmx, seg);
4045                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4046                 return;
4047         }
4048         var->base = vmx_read_guest_seg_base(vmx, seg);
4049         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4050         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4051         ar = vmx_read_guest_seg_ar(vmx, seg);
4052         var->unusable = (ar >> 16) & 1;
4053         var->type = ar & 15;
4054         var->s = (ar >> 4) & 1;
4055         var->dpl = (ar >> 5) & 3;
4056         /*
4057          * Some userspaces do not preserve unusable property. Since usable
4058          * segment has to be present according to VMX spec we can use present
4059          * property to amend userspace bug by making unusable segment always
4060          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4061          * segment as unusable.
4062          */
4063         var->present = !var->unusable;
4064         var->avl = (ar >> 12) & 1;
4065         var->l = (ar >> 13) & 1;
4066         var->db = (ar >> 14) & 1;
4067         var->g = (ar >> 15) & 1;
4068 }
4069
4070 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4071 {
4072         struct kvm_segment s;
4073
4074         if (to_vmx(vcpu)->rmode.vm86_active) {
4075                 vmx_get_segment(vcpu, &s, seg);
4076                 return s.base;
4077         }
4078         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4079 }
4080
4081 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4082 {
4083         struct vcpu_vmx *vmx = to_vmx(vcpu);
4084
4085         if (unlikely(vmx->rmode.vm86_active))
4086                 return 0;
4087         else {
4088                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4089                 return VMX_AR_DPL(ar);
4090         }
4091 }
4092
4093 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4094 {
4095         u32 ar;
4096
4097         if (var->unusable || !var->present)
4098                 ar = 1 << 16;
4099         else {
4100                 ar = var->type & 15;
4101                 ar |= (var->s & 1) << 4;
4102                 ar |= (var->dpl & 3) << 5;
4103                 ar |= (var->present & 1) << 7;
4104                 ar |= (var->avl & 1) << 12;
4105                 ar |= (var->l & 1) << 13;
4106                 ar |= (var->db & 1) << 14;
4107                 ar |= (var->g & 1) << 15;
4108         }
4109
4110         return ar;
4111 }
4112
4113 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4114                             struct kvm_segment *var, int seg)
4115 {
4116         struct vcpu_vmx *vmx = to_vmx(vcpu);
4117         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4118
4119         vmx_segment_cache_clear(vmx);
4120
4121         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4122                 vmx->rmode.segs[seg] = *var;
4123                 if (seg == VCPU_SREG_TR)
4124                         vmcs_write16(sf->selector, var->selector);
4125                 else if (var->s)
4126                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4127                 goto out;
4128         }
4129
4130         vmcs_writel(sf->base, var->base);
4131         vmcs_write32(sf->limit, var->limit);
4132         vmcs_write16(sf->selector, var->selector);
4133
4134         /*
4135          *   Fix the "Accessed" bit in AR field of segment registers for older
4136          * qemu binaries.
4137          *   IA32 arch specifies that at the time of processor reset the
4138          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4139          * is setting it to 0 in the userland code. This causes invalid guest
4140          * state vmexit when "unrestricted guest" mode is turned on.
4141          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4142          * tree. Newer qemu binaries with that qemu fix would not need this
4143          * kvm hack.
4144          */
4145         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4146                 var->type |= 0x1; /* Accessed */
4147
4148         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4149
4150 out:
4151         vmx->emulation_required = emulation_required(vcpu);
4152 }
4153
4154 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4155 {
4156         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4157
4158         *db = (ar >> 14) & 1;
4159         *l = (ar >> 13) & 1;
4160 }
4161
4162 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4163 {
4164         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4165         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4166 }
4167
4168 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4169 {
4170         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4171         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4172 }
4173
4174 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4175 {
4176         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4177         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4178 }
4179
4180 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4181 {
4182         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4183         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4184 }
4185
4186 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4187 {
4188         struct kvm_segment var;
4189         u32 ar;
4190
4191         vmx_get_segment(vcpu, &var, seg);
4192         var.dpl = 0x3;
4193         if (seg == VCPU_SREG_CS)
4194                 var.type = 0x3;
4195         ar = vmx_segment_access_rights(&var);
4196
4197         if (var.base != (var.selector << 4))
4198                 return false;
4199         if (var.limit != 0xffff)
4200                 return false;
4201         if (ar != 0xf3)
4202                 return false;
4203
4204         return true;
4205 }
4206
4207 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4208 {
4209         struct kvm_segment cs;
4210         unsigned int cs_rpl;
4211
4212         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4213         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4214
4215         if (cs.unusable)
4216                 return false;
4217         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4218                 return false;
4219         if (!cs.s)
4220                 return false;
4221         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4222                 if (cs.dpl > cs_rpl)
4223                         return false;
4224         } else {
4225                 if (cs.dpl != cs_rpl)
4226                         return false;
4227         }
4228         if (!cs.present)
4229                 return false;
4230
4231         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4232         return true;
4233 }
4234
4235 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4236 {
4237         struct kvm_segment ss;
4238         unsigned int ss_rpl;
4239
4240         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4241         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4242
4243         if (ss.unusable)
4244                 return true;
4245         if (ss.type != 3 && ss.type != 7)
4246                 return false;
4247         if (!ss.s)
4248                 return false;
4249         if (ss.dpl != ss_rpl) /* DPL != RPL */
4250                 return false;
4251         if (!ss.present)
4252                 return false;
4253
4254         return true;
4255 }
4256
4257 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4258 {
4259         struct kvm_segment var;
4260         unsigned int rpl;
4261
4262         vmx_get_segment(vcpu, &var, seg);
4263         rpl = var.selector & SEGMENT_RPL_MASK;
4264
4265         if (var.unusable)
4266                 return true;
4267         if (!var.s)
4268                 return false;
4269         if (!var.present)
4270                 return false;
4271         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4272                 if (var.dpl < rpl) /* DPL < RPL */
4273                         return false;
4274         }
4275
4276         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4277          * rights flags
4278          */
4279         return true;
4280 }
4281
4282 static bool tr_valid(struct kvm_vcpu *vcpu)
4283 {
4284         struct kvm_segment tr;
4285
4286         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4287
4288         if (tr.unusable)
4289                 return false;
4290         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4291                 return false;
4292         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4293                 return false;
4294         if (!tr.present)
4295                 return false;
4296
4297         return true;
4298 }
4299
4300 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4301 {
4302         struct kvm_segment ldtr;
4303
4304         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4305
4306         if (ldtr.unusable)
4307                 return true;
4308         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4309                 return false;
4310         if (ldtr.type != 2)
4311                 return false;
4312         if (!ldtr.present)
4313                 return false;
4314
4315         return true;
4316 }
4317
4318 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4319 {
4320         struct kvm_segment cs, ss;
4321
4322         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4323         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4324
4325         return ((cs.selector & SEGMENT_RPL_MASK) ==
4326                  (ss.selector & SEGMENT_RPL_MASK));
4327 }
4328
4329 /*
4330  * Check if guest state is valid. Returns true if valid, false if
4331  * not.
4332  * We assume that registers are always usable
4333  */
4334 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4335 {
4336         if (enable_unrestricted_guest)
4337                 return true;
4338
4339         /* real mode guest state checks */
4340         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4341                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4342                         return false;
4343                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4344                         return false;
4345                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4346                         return false;
4347                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4348                         return false;
4349                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4350                         return false;
4351                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4352                         return false;
4353         } else {
4354         /* protected mode guest state checks */
4355                 if (!cs_ss_rpl_check(vcpu))
4356                         return false;
4357                 if (!code_segment_valid(vcpu))
4358                         return false;
4359                 if (!stack_segment_valid(vcpu))
4360                         return false;
4361                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4362                         return false;
4363                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4364                         return false;
4365                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4366                         return false;
4367                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4368                         return false;
4369                 if (!tr_valid(vcpu))
4370                         return false;
4371                 if (!ldtr_valid(vcpu))
4372                         return false;
4373         }
4374         /* TODO:
4375          * - Add checks on RIP
4376          * - Add checks on RFLAGS
4377          */
4378
4379         return true;
4380 }
4381
4382 static int init_rmode_tss(struct kvm *kvm)
4383 {
4384         gfn_t fn;
4385         u16 data = 0;
4386         int idx, r;
4387
4388         idx = srcu_read_lock(&kvm->srcu);
4389         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4390         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4391         if (r < 0)
4392                 goto out;
4393         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4394         r = kvm_write_guest_page(kvm, fn++, &data,
4395                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4396         if (r < 0)
4397                 goto out;
4398         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4399         if (r < 0)
4400                 goto out;
4401         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4402         if (r < 0)
4403                 goto out;
4404         data = ~0;
4405         r = kvm_write_guest_page(kvm, fn, &data,
4406                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4407                                  sizeof(u8));
4408 out:
4409         srcu_read_unlock(&kvm->srcu, idx);
4410         return r;
4411 }
4412
4413 static int init_rmode_identity_map(struct kvm *kvm)
4414 {
4415         int i, idx, r = 0;
4416         kvm_pfn_t identity_map_pfn;
4417         u32 tmp;
4418
4419         if (!enable_ept)
4420                 return 0;
4421
4422         /* Protect kvm->arch.ept_identity_pagetable_done. */
4423         mutex_lock(&kvm->slots_lock);
4424
4425         if (likely(kvm->arch.ept_identity_pagetable_done))
4426                 goto out2;
4427
4428         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4429
4430         r = alloc_identity_pagetable(kvm);
4431         if (r < 0)
4432                 goto out2;
4433
4434         idx = srcu_read_lock(&kvm->srcu);
4435         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4436         if (r < 0)
4437                 goto out;
4438         /* Set up identity-mapping pagetable for EPT in real mode */
4439         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4440                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4441                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4442                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4443                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4444                 if (r < 0)
4445                         goto out;
4446         }
4447         kvm->arch.ept_identity_pagetable_done = true;
4448
4449 out:
4450         srcu_read_unlock(&kvm->srcu, idx);
4451
4452 out2:
4453         mutex_unlock(&kvm->slots_lock);
4454         return r;
4455 }
4456
4457 static void seg_setup(int seg)
4458 {
4459         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4460         unsigned int ar;
4461
4462         vmcs_write16(sf->selector, 0);
4463         vmcs_writel(sf->base, 0);
4464         vmcs_write32(sf->limit, 0xffff);
4465         ar = 0x93;
4466         if (seg == VCPU_SREG_CS)
4467                 ar |= 0x08; /* code segment */
4468
4469         vmcs_write32(sf->ar_bytes, ar);
4470 }
4471
4472 static int alloc_apic_access_page(struct kvm *kvm)
4473 {
4474         struct page *page;
4475         int r = 0;
4476
4477         mutex_lock(&kvm->slots_lock);
4478         if (kvm->arch.apic_access_page_done)
4479                 goto out;
4480         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4481                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4482         if (r)
4483                 goto out;
4484
4485         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4486         if (is_error_page(page)) {
4487                 r = -EFAULT;
4488                 goto out;
4489         }
4490
4491         /*
4492          * Do not pin the page in memory, so that memory hot-unplug
4493          * is able to migrate it.
4494          */
4495         put_page(page);
4496         kvm->arch.apic_access_page_done = true;
4497 out:
4498         mutex_unlock(&kvm->slots_lock);
4499         return r;
4500 }
4501
4502 static int alloc_identity_pagetable(struct kvm *kvm)
4503 {
4504         /* Called with kvm->slots_lock held. */
4505
4506         int r = 0;
4507
4508         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4509
4510         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4511                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4512
4513         return r;
4514 }
4515
4516 static int allocate_vpid(void)
4517 {
4518         int vpid;
4519
4520         if (!enable_vpid)
4521                 return 0;
4522         spin_lock(&vmx_vpid_lock);
4523         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4524         if (vpid < VMX_NR_VPIDS)
4525                 __set_bit(vpid, vmx_vpid_bitmap);
4526         else
4527                 vpid = 0;
4528         spin_unlock(&vmx_vpid_lock);
4529         return vpid;
4530 }
4531
4532 static void free_vpid(int vpid)
4533 {
4534         if (!enable_vpid || vpid == 0)
4535                 return;
4536         spin_lock(&vmx_vpid_lock);
4537         __clear_bit(vpid, vmx_vpid_bitmap);
4538         spin_unlock(&vmx_vpid_lock);
4539 }
4540
4541 #define MSR_TYPE_R      1
4542 #define MSR_TYPE_W      2
4543 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4544                                                 u32 msr, int type)
4545 {
4546         int f = sizeof(unsigned long);
4547
4548         if (!cpu_has_vmx_msr_bitmap())
4549                 return;
4550
4551         /*
4552          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4553          * have the write-low and read-high bitmap offsets the wrong way round.
4554          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4555          */
4556         if (msr <= 0x1fff) {
4557                 if (type & MSR_TYPE_R)
4558                         /* read-low */
4559                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4560
4561                 if (type & MSR_TYPE_W)
4562                         /* write-low */
4563                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4564
4565         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4566                 msr &= 0x1fff;
4567                 if (type & MSR_TYPE_R)
4568                         /* read-high */
4569                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4570
4571                 if (type & MSR_TYPE_W)
4572                         /* write-high */
4573                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4574
4575         }
4576 }
4577
4578 /*
4579  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4580  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4581  */
4582 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4583                                                unsigned long *msr_bitmap_nested,
4584                                                u32 msr, int type)
4585 {
4586         int f = sizeof(unsigned long);
4587
4588         if (!cpu_has_vmx_msr_bitmap()) {
4589                 WARN_ON(1);
4590                 return;
4591         }
4592
4593         /*
4594          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4595          * have the write-low and read-high bitmap offsets the wrong way round.
4596          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4597          */
4598         if (msr <= 0x1fff) {
4599                 if (type & MSR_TYPE_R &&
4600                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4601                         /* read-low */
4602                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4603
4604                 if (type & MSR_TYPE_W &&
4605                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4606                         /* write-low */
4607                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4608
4609         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4610                 msr &= 0x1fff;
4611                 if (type & MSR_TYPE_R &&
4612                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4613                         /* read-high */
4614                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4615
4616                 if (type & MSR_TYPE_W &&
4617                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4618                         /* write-high */
4619                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4620
4621         }
4622 }
4623
4624 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4625 {
4626         if (!longmode_only)
4627                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4628                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4629         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4630                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4631 }
4632
4633 static void vmx_disable_intercept_msr_read_x2apic(u32 msr, bool apicv_active)
4634 {
4635         if (apicv_active) {
4636                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4637                                 msr, MSR_TYPE_R);
4638                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4639                                 msr, MSR_TYPE_R);
4640         } else {
4641                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4642                                 msr, MSR_TYPE_R);
4643                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4644                                 msr, MSR_TYPE_R);
4645         }
4646 }
4647
4648 static void vmx_disable_intercept_msr_write_x2apic(u32 msr, bool apicv_active)
4649 {
4650         if (apicv_active) {
4651                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4652                                 msr, MSR_TYPE_W);
4653                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4654                                 msr, MSR_TYPE_W);
4655         } else {
4656                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4657                                 msr, MSR_TYPE_W);
4658                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4659                                 msr, MSR_TYPE_W);
4660         }
4661 }
4662
4663 static bool vmx_get_enable_apicv(void)
4664 {
4665         return enable_apicv;
4666 }
4667
4668 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4669 {
4670         struct vcpu_vmx *vmx = to_vmx(vcpu);
4671         int max_irr;
4672         void *vapic_page;
4673         u16 status;
4674
4675         if (vmx->nested.pi_desc &&
4676             vmx->nested.pi_pending) {
4677                 vmx->nested.pi_pending = false;
4678                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4679                         return 0;
4680
4681                 max_irr = find_last_bit(
4682                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4683
4684                 if (max_irr == 256)
4685                         return 0;
4686
4687                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4688                 if (!vapic_page) {
4689                         WARN_ON(1);
4690                         return -ENOMEM;
4691                 }
4692                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4693                 kunmap(vmx->nested.virtual_apic_page);
4694
4695                 status = vmcs_read16(GUEST_INTR_STATUS);
4696                 if ((u8)max_irr > ((u8)status & 0xff)) {
4697                         status &= ~0xff;
4698                         status |= (u8)max_irr;
4699                         vmcs_write16(GUEST_INTR_STATUS, status);
4700                 }
4701         }
4702         return 0;
4703 }
4704
4705 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4706 {
4707 #ifdef CONFIG_SMP
4708         if (vcpu->mode == IN_GUEST_MODE) {
4709                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4710
4711                 /*
4712                  * Currently, we don't support urgent interrupt,
4713                  * all interrupts are recognized as non-urgent
4714                  * interrupt, so we cannot post interrupts when
4715                  * 'SN' is set.
4716                  *
4717                  * If the vcpu is in guest mode, it means it is
4718                  * running instead of being scheduled out and
4719                  * waiting in the run queue, and that's the only
4720                  * case when 'SN' is set currently, warning if
4721                  * 'SN' is set.
4722                  */
4723                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4724
4725                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4726                                 POSTED_INTR_VECTOR);
4727                 return true;
4728         }
4729 #endif
4730         return false;
4731 }
4732
4733 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4734                                                 int vector)
4735 {
4736         struct vcpu_vmx *vmx = to_vmx(vcpu);
4737
4738         if (is_guest_mode(vcpu) &&
4739             vector == vmx->nested.posted_intr_nv) {
4740                 /* the PIR and ON have been set by L1. */
4741                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4742                 /*
4743                  * If a posted intr is not recognized by hardware,
4744                  * we will accomplish it in the next vmentry.
4745                  */
4746                 vmx->nested.pi_pending = true;
4747                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4748                 return 0;
4749         }
4750         return -1;
4751 }
4752 /*
4753  * Send interrupt to vcpu via posted interrupt way.
4754  * 1. If target vcpu is running(non-root mode), send posted interrupt
4755  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4756  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4757  * interrupt from PIR in next vmentry.
4758  */
4759 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4760 {
4761         struct vcpu_vmx *vmx = to_vmx(vcpu);
4762         int r;
4763
4764         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4765         if (!r)
4766                 return;
4767
4768         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4769                 return;
4770
4771         r = pi_test_and_set_on(&vmx->pi_desc);
4772         kvm_make_request(KVM_REQ_EVENT, vcpu);
4773         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4774                 kvm_vcpu_kick(vcpu);
4775 }
4776
4777 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4778 {
4779         struct vcpu_vmx *vmx = to_vmx(vcpu);
4780
4781         if (!pi_test_and_clear_on(&vmx->pi_desc))
4782                 return;
4783
4784         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4785 }
4786
4787 /*
4788  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4789  * will not change in the lifetime of the guest.
4790  * Note that host-state that does change is set elsewhere. E.g., host-state
4791  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4792  */
4793 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4794 {
4795         u32 low32, high32;
4796         unsigned long tmpl;
4797         struct desc_ptr dt;
4798         unsigned long cr4;
4799
4800         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4801         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4802
4803         /* Save the most likely value for this task's CR4 in the VMCS. */
4804         cr4 = cr4_read_shadow();
4805         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4806         vmx->host_state.vmcs_host_cr4 = cr4;
4807
4808         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4809 #ifdef CONFIG_X86_64
4810         /*
4811          * Load null selectors, so we can avoid reloading them in
4812          * __vmx_load_host_state(), in case userspace uses the null selectors
4813          * too (the expected case).
4814          */
4815         vmcs_write16(HOST_DS_SELECTOR, 0);
4816         vmcs_write16(HOST_ES_SELECTOR, 0);
4817 #else
4818         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4819         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4820 #endif
4821         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4822         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4823
4824         native_store_idt(&dt);
4825         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4826         vmx->host_idt_base = dt.address;
4827
4828         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4829
4830         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4831         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4832         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4833         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4834
4835         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4836                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4837                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4838         }
4839 }
4840
4841 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4842 {
4843         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4844         if (enable_ept)
4845                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4846         if (is_guest_mode(&vmx->vcpu))
4847                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4848                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4849         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4850 }
4851
4852 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4853 {
4854         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4855
4856         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4857                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4858         /* Enable the preemption timer dynamically */
4859         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4860         return pin_based_exec_ctrl;
4861 }
4862
4863 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4864 {
4865         struct vcpu_vmx *vmx = to_vmx(vcpu);
4866
4867         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4868         if (cpu_has_secondary_exec_ctrls()) {
4869                 if (kvm_vcpu_apicv_active(vcpu))
4870                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4871                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4872                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4873                 else
4874                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4875                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4876                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4877         }
4878
4879         if (cpu_has_vmx_msr_bitmap())
4880                 vmx_set_msr_bitmap(vcpu);
4881 }
4882
4883 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4884 {
4885         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4886
4887         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4888                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4889
4890         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4891                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4892 #ifdef CONFIG_X86_64
4893                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4894                                 CPU_BASED_CR8_LOAD_EXITING;
4895 #endif
4896         }
4897         if (!enable_ept)
4898                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4899                                 CPU_BASED_CR3_LOAD_EXITING  |
4900                                 CPU_BASED_INVLPG_EXITING;
4901         return exec_control;
4902 }
4903
4904 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4905 {
4906         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4907         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4908                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4909         if (vmx->vpid == 0)
4910                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4911         if (!enable_ept) {
4912                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4913                 enable_unrestricted_guest = 0;
4914                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4915                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4916         }
4917         if (!enable_unrestricted_guest)
4918                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4919         if (!ple_gap)
4920                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4921         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4922                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4923                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4924         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4925         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4926            (handle_vmptrld).
4927            We can NOT enable shadow_vmcs here because we don't have yet
4928            a current VMCS12
4929         */
4930         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4931
4932         if (!enable_pml)
4933                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4934
4935         return exec_control;
4936 }
4937
4938 static void ept_set_mmio_spte_mask(void)
4939 {
4940         /*
4941          * EPT Misconfigurations can be generated if the value of bits 2:0
4942          * of an EPT paging-structure entry is 110b (write/execute).
4943          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4944          * spte.
4945          */
4946         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4947 }
4948
4949 #define VMX_XSS_EXIT_BITMAP 0
4950 /*
4951  * Sets up the vmcs for emulated real mode.
4952  */
4953 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4954 {
4955 #ifdef CONFIG_X86_64
4956         unsigned long a;
4957 #endif
4958         int i;
4959
4960         /* I/O */
4961         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4962         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4963
4964         if (enable_shadow_vmcs) {
4965                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4966                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4967         }
4968         if (cpu_has_vmx_msr_bitmap())
4969                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4970
4971         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4972
4973         /* Control */
4974         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4975         vmx->hv_deadline_tsc = -1;
4976
4977         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4978
4979         if (cpu_has_secondary_exec_ctrls()) {
4980                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4981                                 vmx_secondary_exec_control(vmx));
4982         }
4983
4984         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4985                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4986                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4987                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4988                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4989
4990                 vmcs_write16(GUEST_INTR_STATUS, 0);
4991
4992                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4993                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4994         }
4995
4996         if (ple_gap) {
4997                 vmcs_write32(PLE_GAP, ple_gap);
4998                 vmx->ple_window = ple_window;
4999                 vmx->ple_window_dirty = true;
5000         }
5001
5002         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5003         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5004         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5005
5006         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5007         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5008         vmx_set_constant_host_state(vmx);
5009 #ifdef CONFIG_X86_64
5010         rdmsrl(MSR_FS_BASE, a);
5011         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5012         rdmsrl(MSR_GS_BASE, a);
5013         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5014 #else
5015         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5016         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5017 #endif
5018
5019         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5020         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5021         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5022         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5023         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5024
5025         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5026                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5027
5028         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5029                 u32 index = vmx_msr_index[i];
5030                 u32 data_low, data_high;
5031                 int j = vmx->nmsrs;
5032
5033                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5034                         continue;
5035                 if (wrmsr_safe(index, data_low, data_high) < 0)
5036                         continue;
5037                 vmx->guest_msrs[j].index = i;
5038                 vmx->guest_msrs[j].data = 0;
5039                 vmx->guest_msrs[j].mask = -1ull;
5040                 ++vmx->nmsrs;
5041         }
5042
5043
5044         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5045
5046         /* 22.2.1, 20.8.1 */
5047         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5048
5049         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5050         set_cr4_guest_host_mask(vmx);
5051
5052         if (vmx_xsaves_supported())
5053                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5054
5055         if (enable_pml) {
5056                 ASSERT(vmx->pml_pg);
5057                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5058                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5059         }
5060
5061         return 0;
5062 }
5063
5064 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5065 {
5066         struct vcpu_vmx *vmx = to_vmx(vcpu);
5067         struct msr_data apic_base_msr;
5068         u64 cr0;
5069
5070         vmx->rmode.vm86_active = 0;
5071
5072         vmx->soft_vnmi_blocked = 0;
5073
5074         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5075         kvm_set_cr8(vcpu, 0);
5076
5077         if (!init_event) {
5078                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5079                                      MSR_IA32_APICBASE_ENABLE;
5080                 if (kvm_vcpu_is_reset_bsp(vcpu))
5081                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5082                 apic_base_msr.host_initiated = true;
5083                 kvm_set_apic_base(vcpu, &apic_base_msr);
5084         }
5085
5086         vmx_segment_cache_clear(vmx);
5087
5088         seg_setup(VCPU_SREG_CS);
5089         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5090         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5091
5092         seg_setup(VCPU_SREG_DS);
5093         seg_setup(VCPU_SREG_ES);
5094         seg_setup(VCPU_SREG_FS);
5095         seg_setup(VCPU_SREG_GS);
5096         seg_setup(VCPU_SREG_SS);
5097
5098         vmcs_write16(GUEST_TR_SELECTOR, 0);
5099         vmcs_writel(GUEST_TR_BASE, 0);
5100         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5101         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5102
5103         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5104         vmcs_writel(GUEST_LDTR_BASE, 0);
5105         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5106         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5107
5108         if (!init_event) {
5109                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5110                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5111                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5112                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5113         }
5114
5115         vmcs_writel(GUEST_RFLAGS, 0x02);
5116         kvm_rip_write(vcpu, 0xfff0);
5117
5118         vmcs_writel(GUEST_GDTR_BASE, 0);
5119         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5120
5121         vmcs_writel(GUEST_IDTR_BASE, 0);
5122         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5123
5124         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5125         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5126         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5127
5128         setup_msrs(vmx);
5129
5130         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5131
5132         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5133                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5134                 if (cpu_need_tpr_shadow(vcpu))
5135                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5136                                      __pa(vcpu->arch.apic->regs));
5137                 vmcs_write32(TPR_THRESHOLD, 0);
5138         }
5139
5140         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5141
5142         if (kvm_vcpu_apicv_active(vcpu))
5143                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5144
5145         if (vmx->vpid != 0)
5146                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5147
5148         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5149         vmx->vcpu.arch.cr0 = cr0;
5150         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5151         vmx_set_cr4(vcpu, 0);
5152         vmx_set_efer(vcpu, 0);
5153         vmx_fpu_activate(vcpu);
5154         update_exception_bitmap(vcpu);
5155
5156         vpid_sync_context(vmx->vpid);
5157 }
5158
5159 /*
5160  * In nested virtualization, check if L1 asked to exit on external interrupts.
5161  * For most existing hypervisors, this will always return true.
5162  */
5163 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5164 {
5165         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5166                 PIN_BASED_EXT_INTR_MASK;
5167 }
5168
5169 /*
5170  * In nested virtualization, check if L1 has set
5171  * VM_EXIT_ACK_INTR_ON_EXIT
5172  */
5173 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5174 {
5175         return get_vmcs12(vcpu)->vm_exit_controls &
5176                 VM_EXIT_ACK_INTR_ON_EXIT;
5177 }
5178
5179 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5180 {
5181         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5182                 PIN_BASED_NMI_EXITING;
5183 }
5184
5185 static void enable_irq_window(struct kvm_vcpu *vcpu)
5186 {
5187         u32 cpu_based_vm_exec_control;
5188
5189         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5190         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5191         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5192 }
5193
5194 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5195 {
5196         u32 cpu_based_vm_exec_control;
5197
5198         if (!cpu_has_virtual_nmis() ||
5199             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5200                 enable_irq_window(vcpu);
5201                 return;
5202         }
5203
5204         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5205         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5206         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5207 }
5208
5209 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5210 {
5211         struct vcpu_vmx *vmx = to_vmx(vcpu);
5212         uint32_t intr;
5213         int irq = vcpu->arch.interrupt.nr;
5214
5215         trace_kvm_inj_virq(irq);
5216
5217         ++vcpu->stat.irq_injections;
5218         if (vmx->rmode.vm86_active) {
5219                 int inc_eip = 0;
5220                 if (vcpu->arch.interrupt.soft)
5221                         inc_eip = vcpu->arch.event_exit_inst_len;
5222                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5223                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5224                 return;
5225         }
5226         intr = irq | INTR_INFO_VALID_MASK;
5227         if (vcpu->arch.interrupt.soft) {
5228                 intr |= INTR_TYPE_SOFT_INTR;
5229                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5230                              vmx->vcpu.arch.event_exit_inst_len);
5231         } else
5232                 intr |= INTR_TYPE_EXT_INTR;
5233         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5234 }
5235
5236 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5237 {
5238         struct vcpu_vmx *vmx = to_vmx(vcpu);
5239
5240         if (!is_guest_mode(vcpu)) {
5241                 if (!cpu_has_virtual_nmis()) {
5242                         /*
5243                          * Tracking the NMI-blocked state in software is built upon
5244                          * finding the next open IRQ window. This, in turn, depends on
5245                          * well-behaving guests: They have to keep IRQs disabled at
5246                          * least as long as the NMI handler runs. Otherwise we may
5247                          * cause NMI nesting, maybe breaking the guest. But as this is
5248                          * highly unlikely, we can live with the residual risk.
5249                          */
5250                         vmx->soft_vnmi_blocked = 1;
5251                         vmx->vnmi_blocked_time = 0;
5252                 }
5253
5254                 ++vcpu->stat.nmi_injections;
5255                 vmx->nmi_known_unmasked = false;
5256         }
5257
5258         if (vmx->rmode.vm86_active) {
5259                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5260                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5261                 return;
5262         }
5263
5264         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5265                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5266 }
5267
5268 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5269 {
5270         if (!cpu_has_virtual_nmis())
5271                 return to_vmx(vcpu)->soft_vnmi_blocked;
5272         if (to_vmx(vcpu)->nmi_known_unmasked)
5273                 return false;
5274         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5275 }
5276
5277 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5278 {
5279         struct vcpu_vmx *vmx = to_vmx(vcpu);
5280
5281         if (!cpu_has_virtual_nmis()) {
5282                 if (vmx->soft_vnmi_blocked != masked) {
5283                         vmx->soft_vnmi_blocked = masked;
5284                         vmx->vnmi_blocked_time = 0;
5285                 }
5286         } else {
5287                 vmx->nmi_known_unmasked = !masked;
5288                 if (masked)
5289                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5290                                       GUEST_INTR_STATE_NMI);
5291                 else
5292                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5293                                         GUEST_INTR_STATE_NMI);
5294         }
5295 }
5296
5297 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5298 {
5299         if (to_vmx(vcpu)->nested.nested_run_pending)
5300                 return 0;
5301
5302         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5303                 return 0;
5304
5305         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5306                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5307                    | GUEST_INTR_STATE_NMI));
5308 }
5309
5310 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5311 {
5312         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5313                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5314                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5315                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5316 }
5317
5318 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5319 {
5320         int ret;
5321
5322         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5323                                     PAGE_SIZE * 3);
5324         if (ret)
5325                 return ret;
5326         kvm->arch.tss_addr = addr;
5327         return init_rmode_tss(kvm);
5328 }
5329
5330 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5331 {
5332         switch (vec) {
5333         case BP_VECTOR:
5334                 /*
5335                  * Update instruction length as we may reinject the exception
5336                  * from user space while in guest debugging mode.
5337                  */
5338                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5339                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5340                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5341                         return false;
5342                 /* fall through */
5343         case DB_VECTOR:
5344                 if (vcpu->guest_debug &
5345                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5346                         return false;
5347                 /* fall through */
5348         case DE_VECTOR:
5349         case OF_VECTOR:
5350         case BR_VECTOR:
5351         case UD_VECTOR:
5352         case DF_VECTOR:
5353         case SS_VECTOR:
5354         case GP_VECTOR:
5355         case MF_VECTOR:
5356                 return true;
5357         break;
5358         }
5359         return false;
5360 }
5361
5362 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5363                                   int vec, u32 err_code)
5364 {
5365         /*
5366          * Instruction with address size override prefix opcode 0x67
5367          * Cause the #SS fault with 0 error code in VM86 mode.
5368          */
5369         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5370                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5371                         if (vcpu->arch.halt_request) {
5372                                 vcpu->arch.halt_request = 0;
5373                                 return kvm_vcpu_halt(vcpu);
5374                         }
5375                         return 1;
5376                 }
5377                 return 0;
5378         }
5379
5380         /*
5381          * Forward all other exceptions that are valid in real mode.
5382          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5383          *        the required debugging infrastructure rework.
5384          */
5385         kvm_queue_exception(vcpu, vec);
5386         return 1;
5387 }
5388
5389 /*
5390  * Trigger machine check on the host. We assume all the MSRs are already set up
5391  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5392  * We pass a fake environment to the machine check handler because we want
5393  * the guest to be always treated like user space, no matter what context
5394  * it used internally.
5395  */
5396 static void kvm_machine_check(void)
5397 {
5398 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5399         struct pt_regs regs = {
5400                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5401                 .flags = X86_EFLAGS_IF,
5402         };
5403
5404         do_machine_check(&regs, 0);
5405 #endif
5406 }
5407
5408 static int handle_machine_check(struct kvm_vcpu *vcpu)
5409 {
5410         /* already handled by vcpu_run */
5411         return 1;
5412 }
5413
5414 static int handle_exception(struct kvm_vcpu *vcpu)
5415 {
5416         struct vcpu_vmx *vmx = to_vmx(vcpu);
5417         struct kvm_run *kvm_run = vcpu->run;
5418         u32 intr_info, ex_no, error_code;
5419         unsigned long cr2, rip, dr6;
5420         u32 vect_info;
5421         enum emulation_result er;
5422
5423         vect_info = vmx->idt_vectoring_info;
5424         intr_info = vmx->exit_intr_info;
5425
5426         if (is_machine_check(intr_info))
5427                 return handle_machine_check(vcpu);
5428
5429         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5430                 return 1;  /* already handled by vmx_vcpu_run() */
5431
5432         if (is_no_device(intr_info)) {
5433                 vmx_fpu_activate(vcpu);
5434                 return 1;
5435         }
5436
5437         if (is_invalid_opcode(intr_info)) {
5438                 if (is_guest_mode(vcpu)) {
5439                         kvm_queue_exception(vcpu, UD_VECTOR);
5440                         return 1;
5441                 }
5442                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5443                 if (er != EMULATE_DONE)
5444                         kvm_queue_exception(vcpu, UD_VECTOR);
5445                 return 1;
5446         }
5447
5448         error_code = 0;
5449         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5450                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5451
5452         /*
5453          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5454          * MMIO, it is better to report an internal error.
5455          * See the comments in vmx_handle_exit.
5456          */
5457         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5458             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5459                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5460                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5461                 vcpu->run->internal.ndata = 3;
5462                 vcpu->run->internal.data[0] = vect_info;
5463                 vcpu->run->internal.data[1] = intr_info;
5464                 vcpu->run->internal.data[2] = error_code;
5465                 return 0;
5466         }
5467
5468         if (is_page_fault(intr_info)) {
5469                 /* EPT won't cause page fault directly */
5470                 BUG_ON(enable_ept);
5471                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5472                 trace_kvm_page_fault(cr2, error_code);
5473
5474                 if (kvm_event_needs_reinjection(vcpu))
5475                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5476                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5477         }
5478
5479         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5480
5481         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5482                 return handle_rmode_exception(vcpu, ex_no, error_code);
5483
5484         switch (ex_no) {
5485         case AC_VECTOR:
5486                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5487                 return 1;
5488         case DB_VECTOR:
5489                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5490                 if (!(vcpu->guest_debug &
5491                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5492                         vcpu->arch.dr6 &= ~15;
5493                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5494                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5495                                 skip_emulated_instruction(vcpu);
5496
5497                         kvm_queue_exception(vcpu, DB_VECTOR);
5498                         return 1;
5499                 }
5500                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5501                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5502                 /* fall through */
5503         case BP_VECTOR:
5504                 /*
5505                  * Update instruction length as we may reinject #BP from
5506                  * user space while in guest debugging mode. Reading it for
5507                  * #DB as well causes no harm, it is not used in that case.
5508                  */
5509                 vmx->vcpu.arch.event_exit_inst_len =
5510                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5511                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5512                 rip = kvm_rip_read(vcpu);
5513                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5514                 kvm_run->debug.arch.exception = ex_no;
5515                 break;
5516         default:
5517                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5518                 kvm_run->ex.exception = ex_no;
5519                 kvm_run->ex.error_code = error_code;
5520                 break;
5521         }
5522         return 0;
5523 }
5524
5525 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5526 {
5527         ++vcpu->stat.irq_exits;
5528         return 1;
5529 }
5530
5531 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5532 {
5533         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5534         return 0;
5535 }
5536
5537 static int handle_io(struct kvm_vcpu *vcpu)
5538 {
5539         unsigned long exit_qualification;
5540         int size, in, string;
5541         unsigned port;
5542
5543         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5544         string = (exit_qualification & 16) != 0;
5545         in = (exit_qualification & 8) != 0;
5546
5547         ++vcpu->stat.io_exits;
5548
5549         if (string || in)
5550                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5551
5552         port = exit_qualification >> 16;
5553         size = (exit_qualification & 7) + 1;
5554         skip_emulated_instruction(vcpu);
5555
5556         return kvm_fast_pio_out(vcpu, size, port);
5557 }
5558
5559 static void
5560 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5561 {
5562         /*
5563          * Patch in the VMCALL instruction:
5564          */
5565         hypercall[0] = 0x0f;
5566         hypercall[1] = 0x01;
5567         hypercall[2] = 0xc1;
5568 }
5569
5570 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5571 {
5572         unsigned long always_on = VMXON_CR0_ALWAYSON;
5573         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5574
5575         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5576                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5577             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5578                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5579         return (val & always_on) == always_on;
5580 }
5581
5582 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5583 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5584 {
5585         if (is_guest_mode(vcpu)) {
5586                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5587                 unsigned long orig_val = val;
5588
5589                 /*
5590                  * We get here when L2 changed cr0 in a way that did not change
5591                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5592                  * but did change L0 shadowed bits. So we first calculate the
5593                  * effective cr0 value that L1 would like to write into the
5594                  * hardware. It consists of the L2-owned bits from the new
5595                  * value combined with the L1-owned bits from L1's guest_cr0.
5596                  */
5597                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5598                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5599
5600                 if (!nested_cr0_valid(vcpu, val))
5601                         return 1;
5602
5603                 if (kvm_set_cr0(vcpu, val))
5604                         return 1;
5605                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5606                 return 0;
5607         } else {
5608                 if (to_vmx(vcpu)->nested.vmxon &&
5609                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5610                         return 1;
5611                 return kvm_set_cr0(vcpu, val);
5612         }
5613 }
5614
5615 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5616 {
5617         if (is_guest_mode(vcpu)) {
5618                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5619                 unsigned long orig_val = val;
5620
5621                 /* analogously to handle_set_cr0 */
5622                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5623                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5624                 if (kvm_set_cr4(vcpu, val))
5625                         return 1;
5626                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5627                 return 0;
5628         } else
5629                 return kvm_set_cr4(vcpu, val);
5630 }
5631
5632 /* called to set cr0 as appropriate for clts instruction exit. */
5633 static void handle_clts(struct kvm_vcpu *vcpu)
5634 {
5635         if (is_guest_mode(vcpu)) {
5636                 /*
5637                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5638                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5639                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5640                  */
5641                 vmcs_writel(CR0_READ_SHADOW,
5642                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5643                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5644         } else
5645                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5646 }
5647
5648 static int handle_cr(struct kvm_vcpu *vcpu)
5649 {
5650         unsigned long exit_qualification, val;
5651         int cr;
5652         int reg;
5653         int err;
5654
5655         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5656         cr = exit_qualification & 15;
5657         reg = (exit_qualification >> 8) & 15;
5658         switch ((exit_qualification >> 4) & 3) {
5659         case 0: /* mov to cr */
5660                 val = kvm_register_readl(vcpu, reg);
5661                 trace_kvm_cr_write(cr, val);
5662                 switch (cr) {
5663                 case 0:
5664                         err = handle_set_cr0(vcpu, val);
5665                         kvm_complete_insn_gp(vcpu, err);
5666                         return 1;
5667                 case 3:
5668                         err = kvm_set_cr3(vcpu, val);
5669                         kvm_complete_insn_gp(vcpu, err);
5670                         return 1;
5671                 case 4:
5672                         err = handle_set_cr4(vcpu, val);
5673                         kvm_complete_insn_gp(vcpu, err);
5674                         return 1;
5675                 case 8: {
5676                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5677                                 u8 cr8 = (u8)val;
5678                                 err = kvm_set_cr8(vcpu, cr8);
5679                                 kvm_complete_insn_gp(vcpu, err);
5680                                 if (lapic_in_kernel(vcpu))
5681                                         return 1;
5682                                 if (cr8_prev <= cr8)
5683                                         return 1;
5684                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5685                                 return 0;
5686                         }
5687                 }
5688                 break;
5689         case 2: /* clts */
5690                 handle_clts(vcpu);
5691                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5692                 skip_emulated_instruction(vcpu);
5693                 vmx_fpu_activate(vcpu);
5694                 return 1;
5695         case 1: /*mov from cr*/
5696                 switch (cr) {
5697                 case 3:
5698                         val = kvm_read_cr3(vcpu);
5699                         kvm_register_write(vcpu, reg, val);
5700                         trace_kvm_cr_read(cr, val);
5701                         skip_emulated_instruction(vcpu);
5702                         return 1;
5703                 case 8:
5704                         val = kvm_get_cr8(vcpu);
5705                         kvm_register_write(vcpu, reg, val);
5706                         trace_kvm_cr_read(cr, val);
5707                         skip_emulated_instruction(vcpu);
5708                         return 1;
5709                 }
5710                 break;
5711         case 3: /* lmsw */
5712                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5713                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5714                 kvm_lmsw(vcpu, val);
5715
5716                 skip_emulated_instruction(vcpu);
5717                 return 1;
5718         default:
5719                 break;
5720         }
5721         vcpu->run->exit_reason = 0;
5722         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5723                (int)(exit_qualification >> 4) & 3, cr);
5724         return 0;
5725 }
5726
5727 static int handle_dr(struct kvm_vcpu *vcpu)
5728 {
5729         unsigned long exit_qualification;
5730         int dr, dr7, reg;
5731
5732         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5733         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5734
5735         /* First, if DR does not exist, trigger UD */
5736         if (!kvm_require_dr(vcpu, dr))
5737                 return 1;
5738
5739         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5740         if (!kvm_require_cpl(vcpu, 0))
5741                 return 1;
5742         dr7 = vmcs_readl(GUEST_DR7);
5743         if (dr7 & DR7_GD) {
5744                 /*
5745                  * As the vm-exit takes precedence over the debug trap, we
5746                  * need to emulate the latter, either for the host or the
5747                  * guest debugging itself.
5748                  */
5749                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5750                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5751                         vcpu->run->debug.arch.dr7 = dr7;
5752                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5753                         vcpu->run->debug.arch.exception = DB_VECTOR;
5754                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5755                         return 0;
5756                 } else {
5757                         vcpu->arch.dr6 &= ~15;
5758                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5759                         kvm_queue_exception(vcpu, DB_VECTOR);
5760                         return 1;
5761                 }
5762         }
5763
5764         if (vcpu->guest_debug == 0) {
5765                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5766                                 CPU_BASED_MOV_DR_EXITING);
5767
5768                 /*
5769                  * No more DR vmexits; force a reload of the debug registers
5770                  * and reenter on this instruction.  The next vmexit will
5771                  * retrieve the full state of the debug registers.
5772                  */
5773                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5774                 return 1;
5775         }
5776
5777         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5778         if (exit_qualification & TYPE_MOV_FROM_DR) {
5779                 unsigned long val;
5780
5781                 if (kvm_get_dr(vcpu, dr, &val))
5782                         return 1;
5783                 kvm_register_write(vcpu, reg, val);
5784         } else
5785                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5786                         return 1;
5787
5788         skip_emulated_instruction(vcpu);
5789         return 1;
5790 }
5791
5792 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5793 {
5794         return vcpu->arch.dr6;
5795 }
5796
5797 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5798 {
5799 }
5800
5801 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5802 {
5803         get_debugreg(vcpu->arch.db[0], 0);
5804         get_debugreg(vcpu->arch.db[1], 1);
5805         get_debugreg(vcpu->arch.db[2], 2);
5806         get_debugreg(vcpu->arch.db[3], 3);
5807         get_debugreg(vcpu->arch.dr6, 6);
5808         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5809
5810         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5811         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5812 }
5813
5814 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5815 {
5816         vmcs_writel(GUEST_DR7, val);
5817 }
5818
5819 static int handle_cpuid(struct kvm_vcpu *vcpu)
5820 {
5821         kvm_emulate_cpuid(vcpu);
5822         return 1;
5823 }
5824
5825 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5826 {
5827         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5828         struct msr_data msr_info;
5829
5830         msr_info.index = ecx;
5831         msr_info.host_initiated = false;
5832         if (vmx_get_msr(vcpu, &msr_info)) {
5833                 trace_kvm_msr_read_ex(ecx);
5834                 kvm_inject_gp(vcpu, 0);
5835                 return 1;
5836         }
5837
5838         trace_kvm_msr_read(ecx, msr_info.data);
5839
5840         /* FIXME: handling of bits 32:63 of rax, rdx */
5841         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5842         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5843         skip_emulated_instruction(vcpu);
5844         return 1;
5845 }
5846
5847 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5848 {
5849         struct msr_data msr;
5850         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5851         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5852                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5853
5854         msr.data = data;
5855         msr.index = ecx;
5856         msr.host_initiated = false;
5857         if (kvm_set_msr(vcpu, &msr) != 0) {
5858                 trace_kvm_msr_write_ex(ecx, data);
5859                 kvm_inject_gp(vcpu, 0);
5860                 return 1;
5861         }
5862
5863         trace_kvm_msr_write(ecx, data);
5864         skip_emulated_instruction(vcpu);
5865         return 1;
5866 }
5867
5868 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5869 {
5870         kvm_make_request(KVM_REQ_EVENT, vcpu);
5871         return 1;
5872 }
5873
5874 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5875 {
5876         u32 cpu_based_vm_exec_control;
5877
5878         /* clear pending irq */
5879         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5880         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5881         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5882
5883         kvm_make_request(KVM_REQ_EVENT, vcpu);
5884
5885         ++vcpu->stat.irq_window_exits;
5886         return 1;
5887 }
5888
5889 static int handle_halt(struct kvm_vcpu *vcpu)
5890 {
5891         return kvm_emulate_halt(vcpu);
5892 }
5893
5894 static int handle_vmcall(struct kvm_vcpu *vcpu)
5895 {
5896         return kvm_emulate_hypercall(vcpu);
5897 }
5898
5899 static int handle_invd(struct kvm_vcpu *vcpu)
5900 {
5901         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5902 }
5903
5904 static int handle_invlpg(struct kvm_vcpu *vcpu)
5905 {
5906         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5907
5908         kvm_mmu_invlpg(vcpu, exit_qualification);
5909         skip_emulated_instruction(vcpu);
5910         return 1;
5911 }
5912
5913 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5914 {
5915         int err;
5916
5917         err = kvm_rdpmc(vcpu);
5918         kvm_complete_insn_gp(vcpu, err);
5919
5920         return 1;
5921 }
5922
5923 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5924 {
5925         kvm_emulate_wbinvd(vcpu);
5926         return 1;
5927 }
5928
5929 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5930 {
5931         u64 new_bv = kvm_read_edx_eax(vcpu);
5932         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5933
5934         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5935                 skip_emulated_instruction(vcpu);
5936         return 1;
5937 }
5938
5939 static int handle_xsaves(struct kvm_vcpu *vcpu)
5940 {
5941         skip_emulated_instruction(vcpu);
5942         WARN(1, "this should never happen\n");
5943         return 1;
5944 }
5945
5946 static int handle_xrstors(struct kvm_vcpu *vcpu)
5947 {
5948         skip_emulated_instruction(vcpu);
5949         WARN(1, "this should never happen\n");
5950         return 1;
5951 }
5952
5953 static int handle_apic_access(struct kvm_vcpu *vcpu)
5954 {
5955         if (likely(fasteoi)) {
5956                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5957                 int access_type, offset;
5958
5959                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5960                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5961                 /*
5962                  * Sane guest uses MOV to write EOI, with written value
5963                  * not cared. So make a short-circuit here by avoiding
5964                  * heavy instruction emulation.
5965                  */
5966                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5967                     (offset == APIC_EOI)) {
5968                         kvm_lapic_set_eoi(vcpu);
5969                         skip_emulated_instruction(vcpu);
5970                         return 1;
5971                 }
5972         }
5973         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5974 }
5975
5976 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5977 {
5978         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5979         int vector = exit_qualification & 0xff;
5980
5981         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5982         kvm_apic_set_eoi_accelerated(vcpu, vector);
5983         return 1;
5984 }
5985
5986 static int handle_apic_write(struct kvm_vcpu *vcpu)
5987 {
5988         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5989         u32 offset = exit_qualification & 0xfff;
5990
5991         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5992         kvm_apic_write_nodecode(vcpu, offset);
5993         return 1;
5994 }
5995
5996 static int handle_task_switch(struct kvm_vcpu *vcpu)
5997 {
5998         struct vcpu_vmx *vmx = to_vmx(vcpu);
5999         unsigned long exit_qualification;
6000         bool has_error_code = false;
6001         u32 error_code = 0;
6002         u16 tss_selector;
6003         int reason, type, idt_v, idt_index;
6004
6005         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6006         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6007         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6008
6009         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6010
6011         reason = (u32)exit_qualification >> 30;
6012         if (reason == TASK_SWITCH_GATE && idt_v) {
6013                 switch (type) {
6014                 case INTR_TYPE_NMI_INTR:
6015                         vcpu->arch.nmi_injected = false;
6016                         vmx_set_nmi_mask(vcpu, true);
6017                         break;
6018                 case INTR_TYPE_EXT_INTR:
6019                 case INTR_TYPE_SOFT_INTR:
6020                         kvm_clear_interrupt_queue(vcpu);
6021                         break;
6022                 case INTR_TYPE_HARD_EXCEPTION:
6023                         if (vmx->idt_vectoring_info &
6024                             VECTORING_INFO_DELIVER_CODE_MASK) {
6025                                 has_error_code = true;
6026                                 error_code =
6027                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6028                         }
6029                         /* fall through */
6030                 case INTR_TYPE_SOFT_EXCEPTION:
6031                         kvm_clear_exception_queue(vcpu);
6032                         break;
6033                 default:
6034                         break;
6035                 }
6036         }
6037         tss_selector = exit_qualification;
6038
6039         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6040                        type != INTR_TYPE_EXT_INTR &&
6041                        type != INTR_TYPE_NMI_INTR))
6042                 skip_emulated_instruction(vcpu);
6043
6044         if (kvm_task_switch(vcpu, tss_selector,
6045                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6046                             has_error_code, error_code) == EMULATE_FAIL) {
6047                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6048                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6049                 vcpu->run->internal.ndata = 0;
6050                 return 0;
6051         }
6052
6053         /*
6054          * TODO: What about debug traps on tss switch?
6055          *       Are we supposed to inject them and update dr6?
6056          */
6057
6058         return 1;
6059 }
6060
6061 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6062 {
6063         unsigned long exit_qualification;
6064         gpa_t gpa;
6065         u32 error_code;
6066         int gla_validity;
6067
6068         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6069
6070         gla_validity = (exit_qualification >> 7) & 0x3;
6071         if (gla_validity == 0x2) {
6072                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6073                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6074                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6075                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6076                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6077                         (long unsigned int)exit_qualification);
6078                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6079                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6080                 return 0;
6081         }
6082
6083         /*
6084          * EPT violation happened while executing iret from NMI,
6085          * "blocked by NMI" bit has to be set before next VM entry.
6086          * There are errata that may cause this bit to not be set:
6087          * AAK134, BY25.
6088          */
6089         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6090                         cpu_has_virtual_nmis() &&
6091                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6092                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6093
6094         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6095         trace_kvm_page_fault(gpa, exit_qualification);
6096
6097         /* it is a read fault? */
6098         error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6099         /* it is a write fault? */
6100         error_code |= exit_qualification & PFERR_WRITE_MASK;
6101         /* It is a fetch fault? */
6102         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6103         /* ept page table is present? */
6104         error_code |= (exit_qualification & 0x38) != 0;
6105
6106         vcpu->arch.exit_qualification = exit_qualification;
6107
6108         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6109 }
6110
6111 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6112 {
6113         int ret;
6114         gpa_t gpa;
6115
6116         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6117         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6118                 skip_emulated_instruction(vcpu);
6119                 trace_kvm_fast_mmio(gpa);
6120                 return 1;
6121         }
6122
6123         ret = handle_mmio_page_fault(vcpu, gpa, true);
6124         if (likely(ret == RET_MMIO_PF_EMULATE))
6125                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6126                                               EMULATE_DONE;
6127
6128         if (unlikely(ret == RET_MMIO_PF_INVALID))
6129                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6130
6131         if (unlikely(ret == RET_MMIO_PF_RETRY))
6132                 return 1;
6133
6134         /* It is the real ept misconfig */
6135         WARN_ON(1);
6136
6137         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6138         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6139
6140         return 0;
6141 }
6142
6143 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6144 {
6145         u32 cpu_based_vm_exec_control;
6146
6147         /* clear pending NMI */
6148         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6149         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6150         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6151         ++vcpu->stat.nmi_window_exits;
6152         kvm_make_request(KVM_REQ_EVENT, vcpu);
6153
6154         return 1;
6155 }
6156
6157 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6158 {
6159         struct vcpu_vmx *vmx = to_vmx(vcpu);
6160         enum emulation_result err = EMULATE_DONE;
6161         int ret = 1;
6162         u32 cpu_exec_ctrl;
6163         bool intr_window_requested;
6164         unsigned count = 130;
6165
6166         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6167         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6168
6169         while (vmx->emulation_required && count-- != 0) {
6170                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6171                         return handle_interrupt_window(&vmx->vcpu);
6172
6173                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6174                         return 1;
6175
6176                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6177
6178                 if (err == EMULATE_USER_EXIT) {
6179                         ++vcpu->stat.mmio_exits;
6180                         ret = 0;
6181                         goto out;
6182                 }
6183
6184                 if (err != EMULATE_DONE) {
6185                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6186                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6187                         vcpu->run->internal.ndata = 0;
6188                         return 0;
6189                 }
6190
6191                 if (vcpu->arch.halt_request) {
6192                         vcpu->arch.halt_request = 0;
6193                         ret = kvm_vcpu_halt(vcpu);
6194                         goto out;
6195                 }
6196
6197                 if (signal_pending(current))
6198                         goto out;
6199                 if (need_resched())
6200                         schedule();
6201         }
6202
6203 out:
6204         return ret;
6205 }
6206
6207 static int __grow_ple_window(int val)
6208 {
6209         if (ple_window_grow < 1)
6210                 return ple_window;
6211
6212         val = min(val, ple_window_actual_max);
6213
6214         if (ple_window_grow < ple_window)
6215                 val *= ple_window_grow;
6216         else
6217                 val += ple_window_grow;
6218
6219         return val;
6220 }
6221
6222 static int __shrink_ple_window(int val, int modifier, int minimum)
6223 {
6224         if (modifier < 1)
6225                 return ple_window;
6226
6227         if (modifier < ple_window)
6228                 val /= modifier;
6229         else
6230                 val -= modifier;
6231
6232         return max(val, minimum);
6233 }
6234
6235 static void grow_ple_window(struct kvm_vcpu *vcpu)
6236 {
6237         struct vcpu_vmx *vmx = to_vmx(vcpu);
6238         int old = vmx->ple_window;
6239
6240         vmx->ple_window = __grow_ple_window(old);
6241
6242         if (vmx->ple_window != old)
6243                 vmx->ple_window_dirty = true;
6244
6245         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6246 }
6247
6248 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6249 {
6250         struct vcpu_vmx *vmx = to_vmx(vcpu);
6251         int old = vmx->ple_window;
6252
6253         vmx->ple_window = __shrink_ple_window(old,
6254                                               ple_window_shrink, ple_window);
6255
6256         if (vmx->ple_window != old)
6257                 vmx->ple_window_dirty = true;
6258
6259         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6260 }
6261
6262 /*
6263  * ple_window_actual_max is computed to be one grow_ple_window() below
6264  * ple_window_max. (See __grow_ple_window for the reason.)
6265  * This prevents overflows, because ple_window_max is int.
6266  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6267  * this process.
6268  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6269  */
6270 static void update_ple_window_actual_max(void)
6271 {
6272         ple_window_actual_max =
6273                         __shrink_ple_window(max(ple_window_max, ple_window),
6274                                             ple_window_grow, INT_MIN);
6275 }
6276
6277 /*
6278  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6279  */
6280 static void wakeup_handler(void)
6281 {
6282         struct kvm_vcpu *vcpu;
6283         int cpu = smp_processor_id();
6284
6285         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6286         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6287                         blocked_vcpu_list) {
6288                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6289
6290                 if (pi_test_on(pi_desc) == 1)
6291                         kvm_vcpu_kick(vcpu);
6292         }
6293         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6294 }
6295
6296 static __init int hardware_setup(void)
6297 {
6298         int r = -ENOMEM, i, msr;
6299
6300         rdmsrl_safe(MSR_EFER, &host_efer);
6301
6302         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6303                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6304
6305         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6306         if (!vmx_io_bitmap_a)
6307                 return r;
6308
6309         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6310         if (!vmx_io_bitmap_b)
6311                 goto out;
6312
6313         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6314         if (!vmx_msr_bitmap_legacy)
6315                 goto out1;
6316
6317         vmx_msr_bitmap_legacy_x2apic_apicv =
6318                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6319         if (!vmx_msr_bitmap_legacy_x2apic_apicv)
6320                 goto out2;
6321
6322         vmx_msr_bitmap_legacy_x2apic =
6323                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6324         if (!vmx_msr_bitmap_legacy_x2apic)
6325                 goto out3;
6326
6327         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6328         if (!vmx_msr_bitmap_longmode)
6329                 goto out4;
6330
6331         vmx_msr_bitmap_longmode_x2apic_apicv =
6332                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6333         if (!vmx_msr_bitmap_longmode_x2apic_apicv)
6334                 goto out5;
6335
6336         vmx_msr_bitmap_longmode_x2apic =
6337                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6338         if (!vmx_msr_bitmap_longmode_x2apic)
6339                 goto out6;
6340
6341         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6342         if (!vmx_vmread_bitmap)
6343                 goto out7;
6344
6345         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6346         if (!vmx_vmwrite_bitmap)
6347                 goto out8;
6348
6349         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6350         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6351
6352         /*
6353          * Allow direct access to the PC debug port (it is often used for I/O
6354          * delays, but the vmexits simply slow things down).
6355          */
6356         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6357         clear_bit(0x80, vmx_io_bitmap_a);
6358
6359         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6360
6361         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6362         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6363
6364         if (setup_vmcs_config(&vmcs_config) < 0) {
6365                 r = -EIO;
6366                 goto out9;
6367         }
6368
6369         if (boot_cpu_has(X86_FEATURE_NX))
6370                 kvm_enable_efer_bits(EFER_NX);
6371
6372         if (!cpu_has_vmx_vpid())
6373                 enable_vpid = 0;
6374         if (!cpu_has_vmx_shadow_vmcs())
6375                 enable_shadow_vmcs = 0;
6376         if (enable_shadow_vmcs)
6377                 init_vmcs_shadow_fields();
6378
6379         if (!cpu_has_vmx_ept() ||
6380             !cpu_has_vmx_ept_4levels()) {
6381                 enable_ept = 0;
6382                 enable_unrestricted_guest = 0;
6383                 enable_ept_ad_bits = 0;
6384         }
6385
6386         if (!cpu_has_vmx_ept_ad_bits())
6387                 enable_ept_ad_bits = 0;
6388
6389         if (!cpu_has_vmx_unrestricted_guest())
6390                 enable_unrestricted_guest = 0;
6391
6392         if (!cpu_has_vmx_flexpriority())
6393                 flexpriority_enabled = 0;
6394
6395         /*
6396          * set_apic_access_page_addr() is used to reload apic access
6397          * page upon invalidation.  No need to do anything if not
6398          * using the APIC_ACCESS_ADDR VMCS field.
6399          */
6400         if (!flexpriority_enabled)
6401                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6402
6403         if (!cpu_has_vmx_tpr_shadow())
6404                 kvm_x86_ops->update_cr8_intercept = NULL;
6405
6406         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6407                 kvm_disable_largepages();
6408
6409         if (!cpu_has_vmx_ple())
6410                 ple_gap = 0;
6411
6412         if (!cpu_has_vmx_apicv())
6413                 enable_apicv = 0;
6414
6415         if (cpu_has_vmx_tsc_scaling()) {
6416                 kvm_has_tsc_control = true;
6417                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6418                 kvm_tsc_scaling_ratio_frac_bits = 48;
6419         }
6420
6421         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6422         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6423         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6424         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6425         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6426         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6427         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6428
6429         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6430                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6431         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6432                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6433         memcpy(vmx_msr_bitmap_legacy_x2apic,
6434                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6435         memcpy(vmx_msr_bitmap_longmode_x2apic,
6436                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6437
6438         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6439
6440         /*
6441          * enable_apicv && kvm_vcpu_apicv_active()
6442          */
6443         for (msr = 0x800; msr <= 0x8ff; msr++) {
6444                 if (msr == 0x839 /* TMCCT */)
6445                         continue;
6446                 vmx_disable_intercept_msr_read_x2apic(msr, true);
6447         }
6448
6449         /* TPR */
6450         vmx_disable_intercept_msr_write_x2apic(0x808, true);
6451         /* EOI */
6452         vmx_disable_intercept_msr_write_x2apic(0x80b, true);
6453         /* SELF-IPI */
6454         vmx_disable_intercept_msr_write_x2apic(0x83f, true);
6455
6456         /*
6457          * (enable_apicv && !kvm_vcpu_apicv_active()) ||
6458          *      !enable_apicv
6459          */
6460         /* TPR */
6461         vmx_disable_intercept_msr_read_x2apic(0x808, false);
6462         vmx_disable_intercept_msr_write_x2apic(0x808, false);
6463
6464         if (enable_ept) {
6465                 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6466                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6467                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6468                         0ull, VMX_EPT_EXECUTABLE_MASK,
6469                         cpu_has_vmx_ept_execute_only() ?
6470                                       0ull : VMX_EPT_READABLE_MASK);
6471                 ept_set_mmio_spte_mask();
6472                 kvm_enable_tdp();
6473         } else
6474                 kvm_disable_tdp();
6475
6476         update_ple_window_actual_max();
6477
6478         /*
6479          * Only enable PML when hardware supports PML feature, and both EPT
6480          * and EPT A/D bit features are enabled -- PML depends on them to work.
6481          */
6482         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6483                 enable_pml = 0;
6484
6485         if (!enable_pml) {
6486                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6487                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6488                 kvm_x86_ops->flush_log_dirty = NULL;
6489                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6490         }
6491
6492         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6493                 u64 vmx_msr;
6494
6495                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6496                 cpu_preemption_timer_multi =
6497                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6498         } else {
6499                 kvm_x86_ops->set_hv_timer = NULL;
6500                 kvm_x86_ops->cancel_hv_timer = NULL;
6501         }
6502
6503         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6504
6505         kvm_mce_cap_supported |= MCG_LMCE_P;
6506
6507         return alloc_kvm_area();
6508
6509 out9:
6510         free_page((unsigned long)vmx_vmwrite_bitmap);
6511 out8:
6512         free_page((unsigned long)vmx_vmread_bitmap);
6513 out7:
6514         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6515 out6:
6516         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic_apicv);
6517 out5:
6518         free_page((unsigned long)vmx_msr_bitmap_longmode);
6519 out4:
6520         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6521 out3:
6522         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic_apicv);
6523 out2:
6524         free_page((unsigned long)vmx_msr_bitmap_legacy);
6525 out1:
6526         free_page((unsigned long)vmx_io_bitmap_b);
6527 out:
6528         free_page((unsigned long)vmx_io_bitmap_a);
6529
6530     return r;
6531 }
6532
6533 static __exit void hardware_unsetup(void)
6534 {
6535         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic_apicv);
6536         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6537         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic_apicv);
6538         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6539         free_page((unsigned long)vmx_msr_bitmap_legacy);
6540         free_page((unsigned long)vmx_msr_bitmap_longmode);
6541         free_page((unsigned long)vmx_io_bitmap_b);
6542         free_page((unsigned long)vmx_io_bitmap_a);
6543         free_page((unsigned long)vmx_vmwrite_bitmap);
6544         free_page((unsigned long)vmx_vmread_bitmap);
6545
6546         free_kvm_area();
6547 }
6548
6549 /*
6550  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6551  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6552  */
6553 static int handle_pause(struct kvm_vcpu *vcpu)
6554 {
6555         if (ple_gap)
6556                 grow_ple_window(vcpu);
6557
6558         skip_emulated_instruction(vcpu);
6559         kvm_vcpu_on_spin(vcpu);
6560
6561         return 1;
6562 }
6563
6564 static int handle_nop(struct kvm_vcpu *vcpu)
6565 {
6566         skip_emulated_instruction(vcpu);
6567         return 1;
6568 }
6569
6570 static int handle_mwait(struct kvm_vcpu *vcpu)
6571 {
6572         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6573         return handle_nop(vcpu);
6574 }
6575
6576 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6577 {
6578         return 1;
6579 }
6580
6581 static int handle_monitor(struct kvm_vcpu *vcpu)
6582 {
6583         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6584         return handle_nop(vcpu);
6585 }
6586
6587 /*
6588  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6589  * We could reuse a single VMCS for all the L2 guests, but we also want the
6590  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6591  * allows keeping them loaded on the processor, and in the future will allow
6592  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6593  * every entry if they never change.
6594  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6595  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6596  *
6597  * The following functions allocate and free a vmcs02 in this pool.
6598  */
6599
6600 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6601 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6602 {
6603         struct vmcs02_list *item;
6604         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6605                 if (item->vmptr == vmx->nested.current_vmptr) {
6606                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6607                         return &item->vmcs02;
6608                 }
6609
6610         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6611                 /* Recycle the least recently used VMCS. */
6612                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6613                                        struct vmcs02_list, list);
6614                 item->vmptr = vmx->nested.current_vmptr;
6615                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6616                 return &item->vmcs02;
6617         }
6618
6619         /* Create a new VMCS */
6620         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6621         if (!item)
6622                 return NULL;
6623         item->vmcs02.vmcs = alloc_vmcs();
6624         item->vmcs02.shadow_vmcs = NULL;
6625         if (!item->vmcs02.vmcs) {
6626                 kfree(item);
6627                 return NULL;
6628         }
6629         loaded_vmcs_init(&item->vmcs02);
6630         item->vmptr = vmx->nested.current_vmptr;
6631         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6632         vmx->nested.vmcs02_num++;
6633         return &item->vmcs02;
6634 }
6635
6636 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6637 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6638 {
6639         struct vmcs02_list *item;
6640         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6641                 if (item->vmptr == vmptr) {
6642                         free_loaded_vmcs(&item->vmcs02);
6643                         list_del(&item->list);
6644                         kfree(item);
6645                         vmx->nested.vmcs02_num--;
6646                         return;
6647                 }
6648 }
6649
6650 /*
6651  * Free all VMCSs saved for this vcpu, except the one pointed by
6652  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6653  * must be &vmx->vmcs01.
6654  */
6655 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6656 {
6657         struct vmcs02_list *item, *n;
6658
6659         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6660         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6661                 /*
6662                  * Something will leak if the above WARN triggers.  Better than
6663                  * a use-after-free.
6664                  */
6665                 if (vmx->loaded_vmcs == &item->vmcs02)
6666                         continue;
6667
6668                 free_loaded_vmcs(&item->vmcs02);
6669                 list_del(&item->list);
6670                 kfree(item);
6671                 vmx->nested.vmcs02_num--;
6672         }
6673 }
6674
6675 /*
6676  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6677  * set the success or error code of an emulated VMX instruction, as specified
6678  * by Vol 2B, VMX Instruction Reference, "Conventions".
6679  */
6680 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6681 {
6682         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6683                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6684                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6685 }
6686
6687 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6688 {
6689         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6690                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6691                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6692                         | X86_EFLAGS_CF);
6693 }
6694
6695 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6696                                         u32 vm_instruction_error)
6697 {
6698         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6699                 /*
6700                  * failValid writes the error number to the current VMCS, which
6701                  * can't be done there isn't a current VMCS.
6702                  */
6703                 nested_vmx_failInvalid(vcpu);
6704                 return;
6705         }
6706         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6707                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6708                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6709                         | X86_EFLAGS_ZF);
6710         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6711         /*
6712          * We don't need to force a shadow sync because
6713          * VM_INSTRUCTION_ERROR is not shadowed
6714          */
6715 }
6716
6717 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6718 {
6719         /* TODO: not to reset guest simply here. */
6720         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6721         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6722 }
6723
6724 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6725 {
6726         struct vcpu_vmx *vmx =
6727                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6728
6729         vmx->nested.preemption_timer_expired = true;
6730         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6731         kvm_vcpu_kick(&vmx->vcpu);
6732
6733         return HRTIMER_NORESTART;
6734 }
6735
6736 /*
6737  * Decode the memory-address operand of a vmx instruction, as recorded on an
6738  * exit caused by such an instruction (run by a guest hypervisor).
6739  * On success, returns 0. When the operand is invalid, returns 1 and throws
6740  * #UD or #GP.
6741  */
6742 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6743                                  unsigned long exit_qualification,
6744                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6745 {
6746         gva_t off;
6747         bool exn;
6748         struct kvm_segment s;
6749
6750         /*
6751          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6752          * Execution", on an exit, vmx_instruction_info holds most of the
6753          * addressing components of the operand. Only the displacement part
6754          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6755          * For how an actual address is calculated from all these components,
6756          * refer to Vol. 1, "Operand Addressing".
6757          */
6758         int  scaling = vmx_instruction_info & 3;
6759         int  addr_size = (vmx_instruction_info >> 7) & 7;
6760         bool is_reg = vmx_instruction_info & (1u << 10);
6761         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6762         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6763         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6764         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6765         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6766
6767         if (is_reg) {
6768                 kvm_queue_exception(vcpu, UD_VECTOR);
6769                 return 1;
6770         }
6771
6772         /* Addr = segment_base + offset */
6773         /* offset = base + [index * scale] + displacement */
6774         off = exit_qualification; /* holds the displacement */
6775         if (base_is_valid)
6776                 off += kvm_register_read(vcpu, base_reg);
6777         if (index_is_valid)
6778                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6779         vmx_get_segment(vcpu, &s, seg_reg);
6780         *ret = s.base + off;
6781
6782         if (addr_size == 1) /* 32 bit */
6783                 *ret &= 0xffffffff;
6784
6785         /* Checks for #GP/#SS exceptions. */
6786         exn = false;
6787         if (is_long_mode(vcpu)) {
6788                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6789                  * non-canonical form. This is the only check on the memory
6790                  * destination for long mode!
6791                  */
6792                 exn = is_noncanonical_address(*ret);
6793         } else if (is_protmode(vcpu)) {
6794                 /* Protected mode: apply checks for segment validity in the
6795                  * following order:
6796                  * - segment type check (#GP(0) may be thrown)
6797                  * - usability check (#GP(0)/#SS(0))
6798                  * - limit check (#GP(0)/#SS(0))
6799                  */
6800                 if (wr)
6801                         /* #GP(0) if the destination operand is located in a
6802                          * read-only data segment or any code segment.
6803                          */
6804                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6805                 else
6806                         /* #GP(0) if the source operand is located in an
6807                          * execute-only code segment
6808                          */
6809                         exn = ((s.type & 0xa) == 8);
6810                 if (exn) {
6811                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6812                         return 1;
6813                 }
6814                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6815                  */
6816                 exn = (s.unusable != 0);
6817                 /* Protected mode: #GP(0)/#SS(0) if the memory
6818                  * operand is outside the segment limit.
6819                  */
6820                 exn = exn || (off + sizeof(u64) > s.limit);
6821         }
6822         if (exn) {
6823                 kvm_queue_exception_e(vcpu,
6824                                       seg_reg == VCPU_SREG_SS ?
6825                                                 SS_VECTOR : GP_VECTOR,
6826                                       0);
6827                 return 1;
6828         }
6829
6830         return 0;
6831 }
6832
6833 /*
6834  * This function performs the various checks including
6835  * - if it's 4KB aligned
6836  * - No bits beyond the physical address width are set
6837  * - Returns 0 on success or else 1
6838  * (Intel SDM Section 30.3)
6839  */
6840 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6841                                   gpa_t *vmpointer)
6842 {
6843         gva_t gva;
6844         gpa_t vmptr;
6845         struct x86_exception e;
6846         struct page *page;
6847         struct vcpu_vmx *vmx = to_vmx(vcpu);
6848         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6849
6850         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6851                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6852                 return 1;
6853
6854         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6855                                 sizeof(vmptr), &e)) {
6856                 kvm_inject_page_fault(vcpu, &e);
6857                 return 1;
6858         }
6859
6860         switch (exit_reason) {
6861         case EXIT_REASON_VMON:
6862                 /*
6863                  * SDM 3: 24.11.5
6864                  * The first 4 bytes of VMXON region contain the supported
6865                  * VMCS revision identifier
6866                  *
6867                  * Note - IA32_VMX_BASIC[48] will never be 1
6868                  * for the nested case;
6869                  * which replaces physical address width with 32
6870                  *
6871                  */
6872                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6873                         nested_vmx_failInvalid(vcpu);
6874                         skip_emulated_instruction(vcpu);
6875                         return 1;
6876                 }
6877
6878                 page = nested_get_page(vcpu, vmptr);
6879                 if (page == NULL ||
6880                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6881                         nested_vmx_failInvalid(vcpu);
6882                         kunmap(page);
6883                         skip_emulated_instruction(vcpu);
6884                         return 1;
6885                 }
6886                 kunmap(page);
6887                 vmx->nested.vmxon_ptr = vmptr;
6888                 break;
6889         case EXIT_REASON_VMCLEAR:
6890                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6891                         nested_vmx_failValid(vcpu,
6892                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6893                         skip_emulated_instruction(vcpu);
6894                         return 1;
6895                 }
6896
6897                 if (vmptr == vmx->nested.vmxon_ptr) {
6898                         nested_vmx_failValid(vcpu,
6899                                              VMXERR_VMCLEAR_VMXON_POINTER);
6900                         skip_emulated_instruction(vcpu);
6901                         return 1;
6902                 }
6903                 break;
6904         case EXIT_REASON_VMPTRLD:
6905                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6906                         nested_vmx_failValid(vcpu,
6907                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6908                         skip_emulated_instruction(vcpu);
6909                         return 1;
6910                 }
6911
6912                 if (vmptr == vmx->nested.vmxon_ptr) {
6913                         nested_vmx_failValid(vcpu,
6914                                              VMXERR_VMCLEAR_VMXON_POINTER);
6915                         skip_emulated_instruction(vcpu);
6916                         return 1;
6917                 }
6918                 break;
6919         default:
6920                 return 1; /* shouldn't happen */
6921         }
6922
6923         if (vmpointer)
6924                 *vmpointer = vmptr;
6925         return 0;
6926 }
6927
6928 /*
6929  * Emulate the VMXON instruction.
6930  * Currently, we just remember that VMX is active, and do not save or even
6931  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6932  * do not currently need to store anything in that guest-allocated memory
6933  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6934  * argument is different from the VMXON pointer (which the spec says they do).
6935  */
6936 static int handle_vmon(struct kvm_vcpu *vcpu)
6937 {
6938         struct kvm_segment cs;
6939         struct vcpu_vmx *vmx = to_vmx(vcpu);
6940         struct vmcs *shadow_vmcs;
6941         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6942                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6943
6944         /* The Intel VMX Instruction Reference lists a bunch of bits that
6945          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6946          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6947          * Otherwise, we should fail with #UD. We test these now:
6948          */
6949         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6950             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6951             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6952                 kvm_queue_exception(vcpu, UD_VECTOR);
6953                 return 1;
6954         }
6955
6956         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6957         if (is_long_mode(vcpu) && !cs.l) {
6958                 kvm_queue_exception(vcpu, UD_VECTOR);
6959                 return 1;
6960         }
6961
6962         if (vmx_get_cpl(vcpu)) {
6963                 kvm_inject_gp(vcpu, 0);
6964                 return 1;
6965         }
6966
6967         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6968                 return 1;
6969
6970         if (vmx->nested.vmxon) {
6971                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6972                 skip_emulated_instruction(vcpu);
6973                 return 1;
6974         }
6975
6976         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6977                         != VMXON_NEEDED_FEATURES) {
6978                 kvm_inject_gp(vcpu, 0);
6979                 return 1;
6980         }
6981
6982         if (cpu_has_vmx_msr_bitmap()) {
6983                 vmx->nested.msr_bitmap =
6984                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6985                 if (!vmx->nested.msr_bitmap)
6986                         goto out_msr_bitmap;
6987         }
6988
6989         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6990         if (!vmx->nested.cached_vmcs12)
6991                 goto out_cached_vmcs12;
6992
6993         if (enable_shadow_vmcs) {
6994                 shadow_vmcs = alloc_vmcs();
6995                 if (!shadow_vmcs)
6996                         goto out_shadow_vmcs;
6997                 /* mark vmcs as shadow */
6998                 shadow_vmcs->revision_id |= (1u << 31);
6999                 /* init shadow vmcs */
7000                 vmcs_clear(shadow_vmcs);
7001                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7002         }
7003
7004         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7005         vmx->nested.vmcs02_num = 0;
7006
7007         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7008                      HRTIMER_MODE_REL_PINNED);
7009         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7010
7011         vmx->nested.vmxon = true;
7012
7013         skip_emulated_instruction(vcpu);
7014         nested_vmx_succeed(vcpu);
7015         return 1;
7016
7017 out_shadow_vmcs:
7018         kfree(vmx->nested.cached_vmcs12);
7019
7020 out_cached_vmcs12:
7021         free_page((unsigned long)vmx->nested.msr_bitmap);
7022
7023 out_msr_bitmap:
7024         return -ENOMEM;
7025 }
7026
7027 /*
7028  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7029  * for running VMX instructions (except VMXON, whose prerequisites are
7030  * slightly different). It also specifies what exception to inject otherwise.
7031  */
7032 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7033 {
7034         struct kvm_segment cs;
7035         struct vcpu_vmx *vmx = to_vmx(vcpu);
7036
7037         if (!vmx->nested.vmxon) {
7038                 kvm_queue_exception(vcpu, UD_VECTOR);
7039                 return 0;
7040         }
7041
7042         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7043         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7044             (is_long_mode(vcpu) && !cs.l)) {
7045                 kvm_queue_exception(vcpu, UD_VECTOR);
7046                 return 0;
7047         }
7048
7049         if (vmx_get_cpl(vcpu)) {
7050                 kvm_inject_gp(vcpu, 0);
7051                 return 0;
7052         }
7053
7054         return 1;
7055 }
7056
7057 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7058 {
7059         if (vmx->nested.current_vmptr == -1ull)
7060                 return;
7061
7062         /* current_vmptr and current_vmcs12 are always set/reset together */
7063         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7064                 return;
7065
7066         if (enable_shadow_vmcs) {
7067                 /* copy to memory all shadowed fields in case
7068                    they were modified */
7069                 copy_shadow_to_vmcs12(vmx);
7070                 vmx->nested.sync_shadow_vmcs = false;
7071                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7072                                 SECONDARY_EXEC_SHADOW_VMCS);
7073                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7074         }
7075         vmx->nested.posted_intr_nv = -1;
7076
7077         /* Flush VMCS12 to guest memory */
7078         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7079                VMCS12_SIZE);
7080
7081         kunmap(vmx->nested.current_vmcs12_page);
7082         nested_release_page(vmx->nested.current_vmcs12_page);
7083         vmx->nested.current_vmptr = -1ull;
7084         vmx->nested.current_vmcs12 = NULL;
7085 }
7086
7087 /*
7088  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7089  * just stops using VMX.
7090  */
7091 static void free_nested(struct vcpu_vmx *vmx)
7092 {
7093         if (!vmx->nested.vmxon)
7094                 return;
7095
7096         vmx->nested.vmxon = false;
7097         free_vpid(vmx->nested.vpid02);
7098         nested_release_vmcs12(vmx);
7099         if (vmx->nested.msr_bitmap) {
7100                 free_page((unsigned long)vmx->nested.msr_bitmap);
7101                 vmx->nested.msr_bitmap = NULL;
7102         }
7103         if (enable_shadow_vmcs) {
7104                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7105                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7106                 vmx->vmcs01.shadow_vmcs = NULL;
7107         }
7108         kfree(vmx->nested.cached_vmcs12);
7109         /* Unpin physical memory we referred to in current vmcs02 */
7110         if (vmx->nested.apic_access_page) {
7111                 nested_release_page(vmx->nested.apic_access_page);
7112                 vmx->nested.apic_access_page = NULL;
7113         }
7114         if (vmx->nested.virtual_apic_page) {
7115                 nested_release_page(vmx->nested.virtual_apic_page);
7116                 vmx->nested.virtual_apic_page = NULL;
7117         }
7118         if (vmx->nested.pi_desc_page) {
7119                 kunmap(vmx->nested.pi_desc_page);
7120                 nested_release_page(vmx->nested.pi_desc_page);
7121                 vmx->nested.pi_desc_page = NULL;
7122                 vmx->nested.pi_desc = NULL;
7123         }
7124
7125         nested_free_all_saved_vmcss(vmx);
7126 }
7127
7128 /* Emulate the VMXOFF instruction */
7129 static int handle_vmoff(struct kvm_vcpu *vcpu)
7130 {
7131         if (!nested_vmx_check_permission(vcpu))
7132                 return 1;
7133         free_nested(to_vmx(vcpu));
7134         skip_emulated_instruction(vcpu);
7135         nested_vmx_succeed(vcpu);
7136         return 1;
7137 }
7138
7139 /* Emulate the VMCLEAR instruction */
7140 static int handle_vmclear(struct kvm_vcpu *vcpu)
7141 {
7142         struct vcpu_vmx *vmx = to_vmx(vcpu);
7143         gpa_t vmptr;
7144         struct vmcs12 *vmcs12;
7145         struct page *page;
7146
7147         if (!nested_vmx_check_permission(vcpu))
7148                 return 1;
7149
7150         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7151                 return 1;
7152
7153         if (vmptr == vmx->nested.current_vmptr)
7154                 nested_release_vmcs12(vmx);
7155
7156         page = nested_get_page(vcpu, vmptr);
7157         if (page == NULL) {
7158                 /*
7159                  * For accurate processor emulation, VMCLEAR beyond available
7160                  * physical memory should do nothing at all. However, it is
7161                  * possible that a nested vmx bug, not a guest hypervisor bug,
7162                  * resulted in this case, so let's shut down before doing any
7163                  * more damage:
7164                  */
7165                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7166                 return 1;
7167         }
7168         vmcs12 = kmap(page);
7169         vmcs12->launch_state = 0;
7170         kunmap(page);
7171         nested_release_page(page);
7172
7173         nested_free_vmcs02(vmx, vmptr);
7174
7175         skip_emulated_instruction(vcpu);
7176         nested_vmx_succeed(vcpu);
7177         return 1;
7178 }
7179
7180 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7181
7182 /* Emulate the VMLAUNCH instruction */
7183 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7184 {
7185         return nested_vmx_run(vcpu, true);
7186 }
7187
7188 /* Emulate the VMRESUME instruction */
7189 static int handle_vmresume(struct kvm_vcpu *vcpu)
7190 {
7191
7192         return nested_vmx_run(vcpu, false);
7193 }
7194
7195 enum vmcs_field_type {
7196         VMCS_FIELD_TYPE_U16 = 0,
7197         VMCS_FIELD_TYPE_U64 = 1,
7198         VMCS_FIELD_TYPE_U32 = 2,
7199         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7200 };
7201
7202 static inline int vmcs_field_type(unsigned long field)
7203 {
7204         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7205                 return VMCS_FIELD_TYPE_U32;
7206         return (field >> 13) & 0x3 ;
7207 }
7208
7209 static inline int vmcs_field_readonly(unsigned long field)
7210 {
7211         return (((field >> 10) & 0x3) == 1);
7212 }
7213
7214 /*
7215  * Read a vmcs12 field. Since these can have varying lengths and we return
7216  * one type, we chose the biggest type (u64) and zero-extend the return value
7217  * to that size. Note that the caller, handle_vmread, might need to use only
7218  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7219  * 64-bit fields are to be returned).
7220  */
7221 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7222                                   unsigned long field, u64 *ret)
7223 {
7224         short offset = vmcs_field_to_offset(field);
7225         char *p;
7226
7227         if (offset < 0)
7228                 return offset;
7229
7230         p = ((char *)(get_vmcs12(vcpu))) + offset;
7231
7232         switch (vmcs_field_type(field)) {
7233         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7234                 *ret = *((natural_width *)p);
7235                 return 0;
7236         case VMCS_FIELD_TYPE_U16:
7237                 *ret = *((u16 *)p);
7238                 return 0;
7239         case VMCS_FIELD_TYPE_U32:
7240                 *ret = *((u32 *)p);
7241                 return 0;
7242         case VMCS_FIELD_TYPE_U64:
7243                 *ret = *((u64 *)p);
7244                 return 0;
7245         default:
7246                 WARN_ON(1);
7247                 return -ENOENT;
7248         }
7249 }
7250
7251
7252 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7253                                    unsigned long field, u64 field_value){
7254         short offset = vmcs_field_to_offset(field);
7255         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7256         if (offset < 0)
7257                 return offset;
7258
7259         switch (vmcs_field_type(field)) {
7260         case VMCS_FIELD_TYPE_U16:
7261                 *(u16 *)p = field_value;
7262                 return 0;
7263         case VMCS_FIELD_TYPE_U32:
7264                 *(u32 *)p = field_value;
7265                 return 0;
7266         case VMCS_FIELD_TYPE_U64:
7267                 *(u64 *)p = field_value;
7268                 return 0;
7269         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7270                 *(natural_width *)p = field_value;
7271                 return 0;
7272         default:
7273                 WARN_ON(1);
7274                 return -ENOENT;
7275         }
7276
7277 }
7278
7279 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7280 {
7281         int i;
7282         unsigned long field;
7283         u64 field_value;
7284         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7285         const unsigned long *fields = shadow_read_write_fields;
7286         const int num_fields = max_shadow_read_write_fields;
7287
7288         preempt_disable();
7289
7290         vmcs_load(shadow_vmcs);
7291
7292         for (i = 0; i < num_fields; i++) {
7293                 field = fields[i];
7294                 switch (vmcs_field_type(field)) {
7295                 case VMCS_FIELD_TYPE_U16:
7296                         field_value = vmcs_read16(field);
7297                         break;
7298                 case VMCS_FIELD_TYPE_U32:
7299                         field_value = vmcs_read32(field);
7300                         break;
7301                 case VMCS_FIELD_TYPE_U64:
7302                         field_value = vmcs_read64(field);
7303                         break;
7304                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7305                         field_value = vmcs_readl(field);
7306                         break;
7307                 default:
7308                         WARN_ON(1);
7309                         continue;
7310                 }
7311                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7312         }
7313
7314         vmcs_clear(shadow_vmcs);
7315         vmcs_load(vmx->loaded_vmcs->vmcs);
7316
7317         preempt_enable();
7318 }
7319
7320 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7321 {
7322         const unsigned long *fields[] = {
7323                 shadow_read_write_fields,
7324                 shadow_read_only_fields
7325         };
7326         const int max_fields[] = {
7327                 max_shadow_read_write_fields,
7328                 max_shadow_read_only_fields
7329         };
7330         int i, q;
7331         unsigned long field;
7332         u64 field_value = 0;
7333         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7334
7335         vmcs_load(shadow_vmcs);
7336
7337         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7338                 for (i = 0; i < max_fields[q]; i++) {
7339                         field = fields[q][i];
7340                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7341
7342                         switch (vmcs_field_type(field)) {
7343                         case VMCS_FIELD_TYPE_U16:
7344                                 vmcs_write16(field, (u16)field_value);
7345                                 break;
7346                         case VMCS_FIELD_TYPE_U32:
7347                                 vmcs_write32(field, (u32)field_value);
7348                                 break;
7349                         case VMCS_FIELD_TYPE_U64:
7350                                 vmcs_write64(field, (u64)field_value);
7351                                 break;
7352                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7353                                 vmcs_writel(field, (long)field_value);
7354                                 break;
7355                         default:
7356                                 WARN_ON(1);
7357                                 break;
7358                         }
7359                 }
7360         }
7361
7362         vmcs_clear(shadow_vmcs);
7363         vmcs_load(vmx->loaded_vmcs->vmcs);
7364 }
7365
7366 /*
7367  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7368  * used before) all generate the same failure when it is missing.
7369  */
7370 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7371 {
7372         struct vcpu_vmx *vmx = to_vmx(vcpu);
7373         if (vmx->nested.current_vmptr == -1ull) {
7374                 nested_vmx_failInvalid(vcpu);
7375                 skip_emulated_instruction(vcpu);
7376                 return 0;
7377         }
7378         return 1;
7379 }
7380
7381 static int handle_vmread(struct kvm_vcpu *vcpu)
7382 {
7383         unsigned long field;
7384         u64 field_value;
7385         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7386         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7387         gva_t gva = 0;
7388
7389         if (!nested_vmx_check_permission(vcpu) ||
7390             !nested_vmx_check_vmcs12(vcpu))
7391                 return 1;
7392
7393         /* Decode instruction info and find the field to read */
7394         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7395         /* Read the field, zero-extended to a u64 field_value */
7396         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7397                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7398                 skip_emulated_instruction(vcpu);
7399                 return 1;
7400         }
7401         /*
7402          * Now copy part of this value to register or memory, as requested.
7403          * Note that the number of bits actually copied is 32 or 64 depending
7404          * on the guest's mode (32 or 64 bit), not on the given field's length.
7405          */
7406         if (vmx_instruction_info & (1u << 10)) {
7407                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7408                         field_value);
7409         } else {
7410                 if (get_vmx_mem_address(vcpu, exit_qualification,
7411                                 vmx_instruction_info, true, &gva))
7412                         return 1;
7413                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7414                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7415                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7416         }
7417
7418         nested_vmx_succeed(vcpu);
7419         skip_emulated_instruction(vcpu);
7420         return 1;
7421 }
7422
7423
7424 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7425 {
7426         unsigned long field;
7427         gva_t gva;
7428         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7429         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7430         /* The value to write might be 32 or 64 bits, depending on L1's long
7431          * mode, and eventually we need to write that into a field of several
7432          * possible lengths. The code below first zero-extends the value to 64
7433          * bit (field_value), and then copies only the appropriate number of
7434          * bits into the vmcs12 field.
7435          */
7436         u64 field_value = 0;
7437         struct x86_exception e;
7438
7439         if (!nested_vmx_check_permission(vcpu) ||
7440             !nested_vmx_check_vmcs12(vcpu))
7441                 return 1;
7442
7443         if (vmx_instruction_info & (1u << 10))
7444                 field_value = kvm_register_readl(vcpu,
7445                         (((vmx_instruction_info) >> 3) & 0xf));
7446         else {
7447                 if (get_vmx_mem_address(vcpu, exit_qualification,
7448                                 vmx_instruction_info, false, &gva))
7449                         return 1;
7450                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7451                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7452                         kvm_inject_page_fault(vcpu, &e);
7453                         return 1;
7454                 }
7455         }
7456
7457
7458         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7459         if (vmcs_field_readonly(field)) {
7460                 nested_vmx_failValid(vcpu,
7461                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7462                 skip_emulated_instruction(vcpu);
7463                 return 1;
7464         }
7465
7466         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7467                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7468                 skip_emulated_instruction(vcpu);
7469                 return 1;
7470         }
7471
7472         nested_vmx_succeed(vcpu);
7473         skip_emulated_instruction(vcpu);
7474         return 1;
7475 }
7476
7477 /* Emulate the VMPTRLD instruction */
7478 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7479 {
7480         struct vcpu_vmx *vmx = to_vmx(vcpu);
7481         gpa_t vmptr;
7482
7483         if (!nested_vmx_check_permission(vcpu))
7484                 return 1;
7485
7486         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7487                 return 1;
7488
7489         if (vmx->nested.current_vmptr != vmptr) {
7490                 struct vmcs12 *new_vmcs12;
7491                 struct page *page;
7492                 page = nested_get_page(vcpu, vmptr);
7493                 if (page == NULL) {
7494                         nested_vmx_failInvalid(vcpu);
7495                         skip_emulated_instruction(vcpu);
7496                         return 1;
7497                 }
7498                 new_vmcs12 = kmap(page);
7499                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7500                         kunmap(page);
7501                         nested_release_page_clean(page);
7502                         nested_vmx_failValid(vcpu,
7503                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7504                         skip_emulated_instruction(vcpu);
7505                         return 1;
7506                 }
7507
7508                 nested_release_vmcs12(vmx);
7509                 vmx->nested.current_vmptr = vmptr;
7510                 vmx->nested.current_vmcs12 = new_vmcs12;
7511                 vmx->nested.current_vmcs12_page = page;
7512                 /*
7513                  * Load VMCS12 from guest memory since it is not already
7514                  * cached.
7515                  */
7516                 memcpy(vmx->nested.cached_vmcs12,
7517                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7518
7519                 if (enable_shadow_vmcs) {
7520                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7521                                       SECONDARY_EXEC_SHADOW_VMCS);
7522                         vmcs_write64(VMCS_LINK_POINTER,
7523                                      __pa(vmx->vmcs01.shadow_vmcs));
7524                         vmx->nested.sync_shadow_vmcs = true;
7525                 }
7526         }
7527
7528         nested_vmx_succeed(vcpu);
7529         skip_emulated_instruction(vcpu);
7530         return 1;
7531 }
7532
7533 /* Emulate the VMPTRST instruction */
7534 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7535 {
7536         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7537         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7538         gva_t vmcs_gva;
7539         struct x86_exception e;
7540
7541         if (!nested_vmx_check_permission(vcpu))
7542                 return 1;
7543
7544         if (get_vmx_mem_address(vcpu, exit_qualification,
7545                         vmx_instruction_info, true, &vmcs_gva))
7546                 return 1;
7547         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7548         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7549                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7550                                  sizeof(u64), &e)) {
7551                 kvm_inject_page_fault(vcpu, &e);
7552                 return 1;
7553         }
7554         nested_vmx_succeed(vcpu);
7555         skip_emulated_instruction(vcpu);
7556         return 1;
7557 }
7558
7559 /* Emulate the INVEPT instruction */
7560 static int handle_invept(struct kvm_vcpu *vcpu)
7561 {
7562         struct vcpu_vmx *vmx = to_vmx(vcpu);
7563         u32 vmx_instruction_info, types;
7564         unsigned long type;
7565         gva_t gva;
7566         struct x86_exception e;
7567         struct {
7568                 u64 eptp, gpa;
7569         } operand;
7570
7571         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7572               SECONDARY_EXEC_ENABLE_EPT) ||
7573             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7574                 kvm_queue_exception(vcpu, UD_VECTOR);
7575                 return 1;
7576         }
7577
7578         if (!nested_vmx_check_permission(vcpu))
7579                 return 1;
7580
7581         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7582                 kvm_queue_exception(vcpu, UD_VECTOR);
7583                 return 1;
7584         }
7585
7586         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7587         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7588
7589         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7590
7591         if (type >= 32 || !(types & (1 << type))) {
7592                 nested_vmx_failValid(vcpu,
7593                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7594                 skip_emulated_instruction(vcpu);
7595                 return 1;
7596         }
7597
7598         /* According to the Intel VMX instruction reference, the memory
7599          * operand is read even if it isn't needed (e.g., for type==global)
7600          */
7601         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7602                         vmx_instruction_info, false, &gva))
7603                 return 1;
7604         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7605                                 sizeof(operand), &e)) {
7606                 kvm_inject_page_fault(vcpu, &e);
7607                 return 1;
7608         }
7609
7610         switch (type) {
7611         case VMX_EPT_EXTENT_GLOBAL:
7612         /*
7613          * TODO: track mappings and invalidate
7614          * single context requests appropriately
7615          */
7616         case VMX_EPT_EXTENT_CONTEXT:
7617                 kvm_mmu_sync_roots(vcpu);
7618                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7619                 nested_vmx_succeed(vcpu);
7620                 break;
7621         default:
7622                 BUG_ON(1);
7623                 break;
7624         }
7625
7626         skip_emulated_instruction(vcpu);
7627         return 1;
7628 }
7629
7630 static int handle_invvpid(struct kvm_vcpu *vcpu)
7631 {
7632         struct vcpu_vmx *vmx = to_vmx(vcpu);
7633         u32 vmx_instruction_info;
7634         unsigned long type, types;
7635         gva_t gva;
7636         struct x86_exception e;
7637         int vpid;
7638
7639         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7640               SECONDARY_EXEC_ENABLE_VPID) ||
7641                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7642                 kvm_queue_exception(vcpu, UD_VECTOR);
7643                 return 1;
7644         }
7645
7646         if (!nested_vmx_check_permission(vcpu))
7647                 return 1;
7648
7649         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7650         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7651
7652         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7653
7654         if (type >= 32 || !(types & (1 << type))) {
7655                 nested_vmx_failValid(vcpu,
7656                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7657                 skip_emulated_instruction(vcpu);
7658                 return 1;
7659         }
7660
7661         /* according to the intel vmx instruction reference, the memory
7662          * operand is read even if it isn't needed (e.g., for type==global)
7663          */
7664         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7665                         vmx_instruction_info, false, &gva))
7666                 return 1;
7667         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7668                                 sizeof(u32), &e)) {
7669                 kvm_inject_page_fault(vcpu, &e);
7670                 return 1;
7671         }
7672
7673         switch (type) {
7674         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7675                 /*
7676                  * Old versions of KVM use the single-context version so we
7677                  * have to support it; just treat it the same as all-context.
7678                  */
7679         case VMX_VPID_EXTENT_ALL_CONTEXT:
7680                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7681                 nested_vmx_succeed(vcpu);
7682                 break;
7683         default:
7684                 /* Trap individual address invalidation invvpid calls */
7685                 BUG_ON(1);
7686                 break;
7687         }
7688
7689         skip_emulated_instruction(vcpu);
7690         return 1;
7691 }
7692
7693 static int handle_pml_full(struct kvm_vcpu *vcpu)
7694 {
7695         unsigned long exit_qualification;
7696
7697         trace_kvm_pml_full(vcpu->vcpu_id);
7698
7699         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7700
7701         /*
7702          * PML buffer FULL happened while executing iret from NMI,
7703          * "blocked by NMI" bit has to be set before next VM entry.
7704          */
7705         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7706                         cpu_has_virtual_nmis() &&
7707                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7708                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7709                                 GUEST_INTR_STATE_NMI);
7710
7711         /*
7712          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7713          * here.., and there's no userspace involvement needed for PML.
7714          */
7715         return 1;
7716 }
7717
7718 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7719 {
7720         kvm_lapic_expired_hv_timer(vcpu);
7721         return 1;
7722 }
7723
7724 /*
7725  * The exit handlers return 1 if the exit was handled fully and guest execution
7726  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7727  * to be done to userspace and return 0.
7728  */
7729 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7730         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7731         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7732         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7733         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7734         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7735         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7736         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7737         [EXIT_REASON_CPUID]                   = handle_cpuid,
7738         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7739         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7740         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7741         [EXIT_REASON_HLT]                     = handle_halt,
7742         [EXIT_REASON_INVD]                    = handle_invd,
7743         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7744         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7745         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7746         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7747         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7748         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7749         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7750         [EXIT_REASON_VMREAD]                  = handle_vmread,
7751         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7752         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7753         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7754         [EXIT_REASON_VMON]                    = handle_vmon,
7755         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7756         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7757         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7758         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7759         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7760         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7761         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7762         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7763         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7764         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7765         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7766         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7767         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7768         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7769         [EXIT_REASON_INVEPT]                  = handle_invept,
7770         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7771         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7772         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7773         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7774         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7775 };
7776
7777 static const int kvm_vmx_max_exit_handlers =
7778         ARRAY_SIZE(kvm_vmx_exit_handlers);
7779
7780 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7781                                        struct vmcs12 *vmcs12)
7782 {
7783         unsigned long exit_qualification;
7784         gpa_t bitmap, last_bitmap;
7785         unsigned int port;
7786         int size;
7787         u8 b;
7788
7789         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7790                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7791
7792         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7793
7794         port = exit_qualification >> 16;
7795         size = (exit_qualification & 7) + 1;
7796
7797         last_bitmap = (gpa_t)-1;
7798         b = -1;
7799
7800         while (size > 0) {
7801                 if (port < 0x8000)
7802                         bitmap = vmcs12->io_bitmap_a;
7803                 else if (port < 0x10000)
7804                         bitmap = vmcs12->io_bitmap_b;
7805                 else
7806                         return true;
7807                 bitmap += (port & 0x7fff) / 8;
7808
7809                 if (last_bitmap != bitmap)
7810                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7811                                 return true;
7812                 if (b & (1 << (port & 7)))
7813                         return true;
7814
7815                 port++;
7816                 size--;
7817                 last_bitmap = bitmap;
7818         }
7819
7820         return false;
7821 }
7822
7823 /*
7824  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7825  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7826  * disinterest in the current event (read or write a specific MSR) by using an
7827  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7828  */
7829 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7830         struct vmcs12 *vmcs12, u32 exit_reason)
7831 {
7832         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7833         gpa_t bitmap;
7834
7835         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7836                 return true;
7837
7838         /*
7839          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7840          * for the four combinations of read/write and low/high MSR numbers.
7841          * First we need to figure out which of the four to use:
7842          */
7843         bitmap = vmcs12->msr_bitmap;
7844         if (exit_reason == EXIT_REASON_MSR_WRITE)
7845                 bitmap += 2048;
7846         if (msr_index >= 0xc0000000) {
7847                 msr_index -= 0xc0000000;
7848                 bitmap += 1024;
7849         }
7850
7851         /* Then read the msr_index'th bit from this bitmap: */
7852         if (msr_index < 1024*8) {
7853                 unsigned char b;
7854                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7855                         return true;
7856                 return 1 & (b >> (msr_index & 7));
7857         } else
7858                 return true; /* let L1 handle the wrong parameter */
7859 }
7860
7861 /*
7862  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7863  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7864  * intercept (via guest_host_mask etc.) the current event.
7865  */
7866 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7867         struct vmcs12 *vmcs12)
7868 {
7869         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7870         int cr = exit_qualification & 15;
7871         int reg = (exit_qualification >> 8) & 15;
7872         unsigned long val = kvm_register_readl(vcpu, reg);
7873
7874         switch ((exit_qualification >> 4) & 3) {
7875         case 0: /* mov to cr */
7876                 switch (cr) {
7877                 case 0:
7878                         if (vmcs12->cr0_guest_host_mask &
7879                             (val ^ vmcs12->cr0_read_shadow))
7880                                 return true;
7881                         break;
7882                 case 3:
7883                         if ((vmcs12->cr3_target_count >= 1 &&
7884                                         vmcs12->cr3_target_value0 == val) ||
7885                                 (vmcs12->cr3_target_count >= 2 &&
7886                                         vmcs12->cr3_target_value1 == val) ||
7887                                 (vmcs12->cr3_target_count >= 3 &&
7888                                         vmcs12->cr3_target_value2 == val) ||
7889                                 (vmcs12->cr3_target_count >= 4 &&
7890                                         vmcs12->cr3_target_value3 == val))
7891                                 return false;
7892                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7893                                 return true;
7894                         break;
7895                 case 4:
7896                         if (vmcs12->cr4_guest_host_mask &
7897                             (vmcs12->cr4_read_shadow ^ val))
7898                                 return true;
7899                         break;
7900                 case 8:
7901                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7902                                 return true;
7903                         break;
7904                 }
7905                 break;
7906         case 2: /* clts */
7907                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7908                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7909                         return true;
7910                 break;
7911         case 1: /* mov from cr */
7912                 switch (cr) {
7913                 case 3:
7914                         if (vmcs12->cpu_based_vm_exec_control &
7915                             CPU_BASED_CR3_STORE_EXITING)
7916                                 return true;
7917                         break;
7918                 case 8:
7919                         if (vmcs12->cpu_based_vm_exec_control &
7920                             CPU_BASED_CR8_STORE_EXITING)
7921                                 return true;
7922                         break;
7923                 }
7924                 break;
7925         case 3: /* lmsw */
7926                 /*
7927                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7928                  * cr0. Other attempted changes are ignored, with no exit.
7929                  */
7930                 if (vmcs12->cr0_guest_host_mask & 0xe &
7931                     (val ^ vmcs12->cr0_read_shadow))
7932                         return true;
7933                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7934                     !(vmcs12->cr0_read_shadow & 0x1) &&
7935                     (val & 0x1))
7936                         return true;
7937                 break;
7938         }
7939         return false;
7940 }
7941
7942 /*
7943  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7944  * should handle it ourselves in L0 (and then continue L2). Only call this
7945  * when in is_guest_mode (L2).
7946  */
7947 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7948 {
7949         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7950         struct vcpu_vmx *vmx = to_vmx(vcpu);
7951         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7952         u32 exit_reason = vmx->exit_reason;
7953
7954         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7955                                 vmcs_readl(EXIT_QUALIFICATION),
7956                                 vmx->idt_vectoring_info,
7957                                 intr_info,
7958                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7959                                 KVM_ISA_VMX);
7960
7961         if (vmx->nested.nested_run_pending)
7962                 return false;
7963
7964         if (unlikely(vmx->fail)) {
7965                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7966                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7967                 return true;
7968         }
7969
7970         switch (exit_reason) {
7971         case EXIT_REASON_EXCEPTION_NMI:
7972                 if (!is_exception(intr_info))
7973                         return false;
7974                 else if (is_page_fault(intr_info))
7975                         return enable_ept;
7976                 else if (is_no_device(intr_info) &&
7977                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7978                         return false;
7979                 else if (is_debug(intr_info) &&
7980                          vcpu->guest_debug &
7981                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7982                         return false;
7983                 else if (is_breakpoint(intr_info) &&
7984                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7985                         return false;
7986                 return vmcs12->exception_bitmap &
7987                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7988         case EXIT_REASON_EXTERNAL_INTERRUPT:
7989                 return false;
7990         case EXIT_REASON_TRIPLE_FAULT:
7991                 return true;
7992         case EXIT_REASON_PENDING_INTERRUPT:
7993                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7994         case EXIT_REASON_NMI_WINDOW:
7995                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7996         case EXIT_REASON_TASK_SWITCH:
7997                 return true;
7998         case EXIT_REASON_CPUID:
7999                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
8000                         return false;
8001                 return true;
8002         case EXIT_REASON_HLT:
8003                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8004         case EXIT_REASON_INVD:
8005                 return true;
8006         case EXIT_REASON_INVLPG:
8007                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8008         case EXIT_REASON_RDPMC:
8009                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8010         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8011                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8012         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8013         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8014         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8015         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8016         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8017         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8018                 /*
8019                  * VMX instructions trap unconditionally. This allows L1 to
8020                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8021                  */
8022                 return true;
8023         case EXIT_REASON_CR_ACCESS:
8024                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8025         case EXIT_REASON_DR_ACCESS:
8026                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8027         case EXIT_REASON_IO_INSTRUCTION:
8028                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8029         case EXIT_REASON_MSR_READ:
8030         case EXIT_REASON_MSR_WRITE:
8031                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8032         case EXIT_REASON_INVALID_STATE:
8033                 return true;
8034         case EXIT_REASON_MWAIT_INSTRUCTION:
8035                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8036         case EXIT_REASON_MONITOR_TRAP_FLAG:
8037                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8038         case EXIT_REASON_MONITOR_INSTRUCTION:
8039                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8040         case EXIT_REASON_PAUSE_INSTRUCTION:
8041                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8042                         nested_cpu_has2(vmcs12,
8043                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8044         case EXIT_REASON_MCE_DURING_VMENTRY:
8045                 return false;
8046         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8047                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8048         case EXIT_REASON_APIC_ACCESS:
8049                 return nested_cpu_has2(vmcs12,
8050                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8051         case EXIT_REASON_APIC_WRITE:
8052         case EXIT_REASON_EOI_INDUCED:
8053                 /* apic_write and eoi_induced should exit unconditionally. */
8054                 return true;
8055         case EXIT_REASON_EPT_VIOLATION:
8056                 /*
8057                  * L0 always deals with the EPT violation. If nested EPT is
8058                  * used, and the nested mmu code discovers that the address is
8059                  * missing in the guest EPT table (EPT12), the EPT violation
8060                  * will be injected with nested_ept_inject_page_fault()
8061                  */
8062                 return false;
8063         case EXIT_REASON_EPT_MISCONFIG:
8064                 /*
8065                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8066                  * table (shadow on EPT) or a merged EPT table that L0 built
8067                  * (EPT on EPT). So any problems with the structure of the
8068                  * table is L0's fault.
8069                  */
8070                 return false;
8071         case EXIT_REASON_WBINVD:
8072                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8073         case EXIT_REASON_XSETBV:
8074                 return true;
8075         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8076                 /*
8077                  * This should never happen, since it is not possible to
8078                  * set XSS to a non-zero value---neither in L1 nor in L2.
8079                  * If if it were, XSS would have to be checked against
8080                  * the XSS exit bitmap in vmcs12.
8081                  */
8082                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8083         case EXIT_REASON_PREEMPTION_TIMER:
8084                 return false;
8085         default:
8086                 return true;
8087         }
8088 }
8089
8090 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8091 {
8092         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8093         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8094 }
8095
8096 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8097 {
8098         if (vmx->pml_pg) {
8099                 __free_page(vmx->pml_pg);
8100                 vmx->pml_pg = NULL;
8101         }
8102 }
8103
8104 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8105 {
8106         struct vcpu_vmx *vmx = to_vmx(vcpu);
8107         u64 *pml_buf;
8108         u16 pml_idx;
8109
8110         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8111
8112         /* Do nothing if PML buffer is empty */
8113         if (pml_idx == (PML_ENTITY_NUM - 1))
8114                 return;
8115
8116         /* PML index always points to next available PML buffer entity */
8117         if (pml_idx >= PML_ENTITY_NUM)
8118                 pml_idx = 0;
8119         else
8120                 pml_idx++;
8121
8122         pml_buf = page_address(vmx->pml_pg);
8123         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8124                 u64 gpa;
8125
8126                 gpa = pml_buf[pml_idx];
8127                 WARN_ON(gpa & (PAGE_SIZE - 1));
8128                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8129         }
8130
8131         /* reset PML index */
8132         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8133 }
8134
8135 /*
8136  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8137  * Called before reporting dirty_bitmap to userspace.
8138  */
8139 static void kvm_flush_pml_buffers(struct kvm *kvm)
8140 {
8141         int i;
8142         struct kvm_vcpu *vcpu;
8143         /*
8144          * We only need to kick vcpu out of guest mode here, as PML buffer
8145          * is flushed at beginning of all VMEXITs, and it's obvious that only
8146          * vcpus running in guest are possible to have unflushed GPAs in PML
8147          * buffer.
8148          */
8149         kvm_for_each_vcpu(i, vcpu, kvm)
8150                 kvm_vcpu_kick(vcpu);
8151 }
8152
8153 static void vmx_dump_sel(char *name, uint32_t sel)
8154 {
8155         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8156                name, vmcs_read32(sel),
8157                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8158                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8159                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8160 }
8161
8162 static void vmx_dump_dtsel(char *name, uint32_t limit)
8163 {
8164         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8165                name, vmcs_read32(limit),
8166                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8167 }
8168
8169 static void dump_vmcs(void)
8170 {
8171         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8172         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8173         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8174         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8175         u32 secondary_exec_control = 0;
8176         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8177         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8178         int i, n;
8179
8180         if (cpu_has_secondary_exec_ctrls())
8181                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8182
8183         pr_err("*** Guest State ***\n");
8184         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8185                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8186                vmcs_readl(CR0_GUEST_HOST_MASK));
8187         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8188                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8189         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8190         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8191             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8192         {
8193                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8194                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8195                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8196                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8197         }
8198         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8199                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8200         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8201                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8202         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8203                vmcs_readl(GUEST_SYSENTER_ESP),
8204                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8205         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8206         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8207         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8208         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8209         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8210         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8211         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8212         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8213         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8214         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8215         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8216             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8217                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8218                        efer, vmcs_read64(GUEST_IA32_PAT));
8219         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8220                vmcs_read64(GUEST_IA32_DEBUGCTL),
8221                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8222         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8223                 pr_err("PerfGlobCtl = 0x%016llx\n",
8224                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8225         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8226                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8227         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8228                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8229                vmcs_read32(GUEST_ACTIVITY_STATE));
8230         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8231                 pr_err("InterruptStatus = %04x\n",
8232                        vmcs_read16(GUEST_INTR_STATUS));
8233
8234         pr_err("*** Host State ***\n");
8235         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8236                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8237         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8238                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8239                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8240                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8241                vmcs_read16(HOST_TR_SELECTOR));
8242         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8243                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8244                vmcs_readl(HOST_TR_BASE));
8245         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8246                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8247         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8248                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8249                vmcs_readl(HOST_CR4));
8250         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8251                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8252                vmcs_read32(HOST_IA32_SYSENTER_CS),
8253                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8254         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8255                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8256                        vmcs_read64(HOST_IA32_EFER),
8257                        vmcs_read64(HOST_IA32_PAT));
8258         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8259                 pr_err("PerfGlobCtl = 0x%016llx\n",
8260                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8261
8262         pr_err("*** Control State ***\n");
8263         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8264                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8265         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8266         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8267                vmcs_read32(EXCEPTION_BITMAP),
8268                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8269                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8270         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8271                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8272                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8273                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8274         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8275                vmcs_read32(VM_EXIT_INTR_INFO),
8276                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8277                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8278         pr_err("        reason=%08x qualification=%016lx\n",
8279                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8280         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8281                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8282                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8283         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8284         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8285                 pr_err("TSC Multiplier = 0x%016llx\n",
8286                        vmcs_read64(TSC_MULTIPLIER));
8287         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8288                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8289         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8290                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8291         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8292                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8293         n = vmcs_read32(CR3_TARGET_COUNT);
8294         for (i = 0; i + 1 < n; i += 4)
8295                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8296                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8297                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8298         if (i < n)
8299                 pr_err("CR3 target%u=%016lx\n",
8300                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8301         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8302                 pr_err("PLE Gap=%08x Window=%08x\n",
8303                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8304         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8305                 pr_err("Virtual processor ID = 0x%04x\n",
8306                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8307 }
8308
8309 /*
8310  * The guest has exited.  See if we can fix it or if we need userspace
8311  * assistance.
8312  */
8313 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8314 {
8315         struct vcpu_vmx *vmx = to_vmx(vcpu);
8316         u32 exit_reason = vmx->exit_reason;
8317         u32 vectoring_info = vmx->idt_vectoring_info;
8318
8319         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8320
8321         /*
8322          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8323          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8324          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8325          * mode as if vcpus is in root mode, the PML buffer must has been
8326          * flushed already.
8327          */
8328         if (enable_pml)
8329                 vmx_flush_pml_buffer(vcpu);
8330
8331         /* If guest state is invalid, start emulating */
8332         if (vmx->emulation_required)
8333                 return handle_invalid_guest_state(vcpu);
8334
8335         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8336                 nested_vmx_vmexit(vcpu, exit_reason,
8337                                   vmcs_read32(VM_EXIT_INTR_INFO),
8338                                   vmcs_readl(EXIT_QUALIFICATION));
8339                 return 1;
8340         }
8341
8342         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8343                 dump_vmcs();
8344                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8345                 vcpu->run->fail_entry.hardware_entry_failure_reason
8346                         = exit_reason;
8347                 return 0;
8348         }
8349
8350         if (unlikely(vmx->fail)) {
8351                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8352                 vcpu->run->fail_entry.hardware_entry_failure_reason
8353                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8354                 return 0;
8355         }
8356
8357         /*
8358          * Note:
8359          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8360          * delivery event since it indicates guest is accessing MMIO.
8361          * The vm-exit can be triggered again after return to guest that
8362          * will cause infinite loop.
8363          */
8364         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8365                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8366                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8367                         exit_reason != EXIT_REASON_PML_FULL &&
8368                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8369                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8370                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8371                 vcpu->run->internal.ndata = 2;
8372                 vcpu->run->internal.data[0] = vectoring_info;
8373                 vcpu->run->internal.data[1] = exit_reason;
8374                 return 0;
8375         }
8376
8377         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8378             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8379                                         get_vmcs12(vcpu))))) {
8380                 if (vmx_interrupt_allowed(vcpu)) {
8381                         vmx->soft_vnmi_blocked = 0;
8382                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8383                            vcpu->arch.nmi_pending) {
8384                         /*
8385                          * This CPU don't support us in finding the end of an
8386                          * NMI-blocked window if the guest runs with IRQs
8387                          * disabled. So we pull the trigger after 1 s of
8388                          * futile waiting, but inform the user about this.
8389                          */
8390                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8391                                "state on VCPU %d after 1 s timeout\n",
8392                                __func__, vcpu->vcpu_id);
8393                         vmx->soft_vnmi_blocked = 0;
8394                 }
8395         }
8396
8397         if (exit_reason < kvm_vmx_max_exit_handlers
8398             && kvm_vmx_exit_handlers[exit_reason])
8399                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8400         else {
8401                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8402                 kvm_queue_exception(vcpu, UD_VECTOR);
8403                 return 1;
8404         }
8405 }
8406
8407 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8408 {
8409         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8410
8411         if (is_guest_mode(vcpu) &&
8412                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8413                 return;
8414
8415         if (irr == -1 || tpr < irr) {
8416                 vmcs_write32(TPR_THRESHOLD, 0);
8417                 return;
8418         }
8419
8420         vmcs_write32(TPR_THRESHOLD, irr);
8421 }
8422
8423 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8424 {
8425         u32 sec_exec_control;
8426
8427         /* Postpone execution until vmcs01 is the current VMCS. */
8428         if (is_guest_mode(vcpu)) {
8429                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8430                 return;
8431         }
8432
8433         if (!cpu_has_vmx_virtualize_x2apic_mode())
8434                 return;
8435
8436         if (!cpu_need_tpr_shadow(vcpu))
8437                 return;
8438
8439         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8440
8441         if (set) {
8442                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8443                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8444         } else {
8445                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8446                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8447         }
8448         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8449
8450         vmx_set_msr_bitmap(vcpu);
8451 }
8452
8453 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8454 {
8455         struct vcpu_vmx *vmx = to_vmx(vcpu);
8456
8457         /*
8458          * Currently we do not handle the nested case where L2 has an
8459          * APIC access page of its own; that page is still pinned.
8460          * Hence, we skip the case where the VCPU is in guest mode _and_
8461          * L1 prepared an APIC access page for L2.
8462          *
8463          * For the case where L1 and L2 share the same APIC access page
8464          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8465          * in the vmcs12), this function will only update either the vmcs01
8466          * or the vmcs02.  If the former, the vmcs02 will be updated by
8467          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8468          * the next L2->L1 exit.
8469          */
8470         if (!is_guest_mode(vcpu) ||
8471             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8472                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8473                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8474 }
8475
8476 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8477 {
8478         u16 status;
8479         u8 old;
8480
8481         if (max_isr == -1)
8482                 max_isr = 0;
8483
8484         status = vmcs_read16(GUEST_INTR_STATUS);
8485         old = status >> 8;
8486         if (max_isr != old) {
8487                 status &= 0xff;
8488                 status |= max_isr << 8;
8489                 vmcs_write16(GUEST_INTR_STATUS, status);
8490         }
8491 }
8492
8493 static void vmx_set_rvi(int vector)
8494 {
8495         u16 status;
8496         u8 old;
8497
8498         if (vector == -1)
8499                 vector = 0;
8500
8501         status = vmcs_read16(GUEST_INTR_STATUS);
8502         old = (u8)status & 0xff;
8503         if ((u8)vector != old) {
8504                 status &= ~0xff;
8505                 status |= (u8)vector;
8506                 vmcs_write16(GUEST_INTR_STATUS, status);
8507         }
8508 }
8509
8510 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8511 {
8512         if (!is_guest_mode(vcpu)) {
8513                 vmx_set_rvi(max_irr);
8514                 return;
8515         }
8516
8517         if (max_irr == -1)
8518                 return;
8519
8520         /*
8521          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8522          * handles it.
8523          */
8524         if (nested_exit_on_intr(vcpu))
8525                 return;
8526
8527         /*
8528          * Else, fall back to pre-APICv interrupt injection since L2
8529          * is run without virtual interrupt delivery.
8530          */
8531         if (!kvm_event_needs_reinjection(vcpu) &&
8532             vmx_interrupt_allowed(vcpu)) {
8533                 kvm_queue_interrupt(vcpu, max_irr, false);
8534                 vmx_inject_irq(vcpu);
8535         }
8536 }
8537
8538 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8539 {
8540         if (!kvm_vcpu_apicv_active(vcpu))
8541                 return;
8542
8543         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8544         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8545         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8546         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8547 }
8548
8549 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8550 {
8551         u32 exit_intr_info;
8552
8553         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8554               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8555                 return;
8556
8557         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8558         exit_intr_info = vmx->exit_intr_info;
8559
8560         /* Handle machine checks before interrupts are enabled */
8561         if (is_machine_check(exit_intr_info))
8562                 kvm_machine_check();
8563
8564         /* We need to handle NMIs before interrupts are enabled */
8565         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8566             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8567                 kvm_before_handle_nmi(&vmx->vcpu);
8568                 asm("int $2");
8569                 kvm_after_handle_nmi(&vmx->vcpu);
8570         }
8571 }
8572
8573 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8574 {
8575         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8576         register void *__sp asm(_ASM_SP);
8577
8578         /*
8579          * If external interrupt exists, IF bit is set in rflags/eflags on the
8580          * interrupt stack frame, and interrupt will be enabled on a return
8581          * from interrupt handler.
8582          */
8583         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8584                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8585                 unsigned int vector;
8586                 unsigned long entry;
8587                 gate_desc *desc;
8588                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8589 #ifdef CONFIG_X86_64
8590                 unsigned long tmp;
8591 #endif
8592
8593                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8594                 desc = (gate_desc *)vmx->host_idt_base + vector;
8595                 entry = gate_offset(*desc);
8596                 asm volatile(
8597 #ifdef CONFIG_X86_64
8598                         "mov %%" _ASM_SP ", %[sp]\n\t"
8599                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8600                         "push $%c[ss]\n\t"
8601                         "push %[sp]\n\t"
8602 #endif
8603                         "pushf\n\t"
8604                         __ASM_SIZE(push) " $%c[cs]\n\t"
8605                         "call *%[entry]\n\t"
8606                         :
8607 #ifdef CONFIG_X86_64
8608                         [sp]"=&r"(tmp),
8609 #endif
8610                         "+r"(__sp)
8611                         :
8612                         [entry]"r"(entry),
8613                         [ss]"i"(__KERNEL_DS),
8614                         [cs]"i"(__KERNEL_CS)
8615                         );
8616         }
8617 }
8618
8619 static bool vmx_has_high_real_mode_segbase(void)
8620 {
8621         return enable_unrestricted_guest || emulate_invalid_guest_state;
8622 }
8623
8624 static bool vmx_mpx_supported(void)
8625 {
8626         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8627                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8628 }
8629
8630 static bool vmx_xsaves_supported(void)
8631 {
8632         return vmcs_config.cpu_based_2nd_exec_ctrl &
8633                 SECONDARY_EXEC_XSAVES;
8634 }
8635
8636 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8637 {
8638         u32 exit_intr_info;
8639         bool unblock_nmi;
8640         u8 vector;
8641         bool idtv_info_valid;
8642
8643         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8644
8645         if (cpu_has_virtual_nmis()) {
8646                 if (vmx->nmi_known_unmasked)
8647                         return;
8648                 /*
8649                  * Can't use vmx->exit_intr_info since we're not sure what
8650                  * the exit reason is.
8651                  */
8652                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8653                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8654                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8655                 /*
8656                  * SDM 3: 27.7.1.2 (September 2008)
8657                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8658                  * a guest IRET fault.
8659                  * SDM 3: 23.2.2 (September 2008)
8660                  * Bit 12 is undefined in any of the following cases:
8661                  *  If the VM exit sets the valid bit in the IDT-vectoring
8662                  *   information field.
8663                  *  If the VM exit is due to a double fault.
8664                  */
8665                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8666                     vector != DF_VECTOR && !idtv_info_valid)
8667                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8668                                       GUEST_INTR_STATE_NMI);
8669                 else
8670                         vmx->nmi_known_unmasked =
8671                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8672                                   & GUEST_INTR_STATE_NMI);
8673         } else if (unlikely(vmx->soft_vnmi_blocked))
8674                 vmx->vnmi_blocked_time +=
8675                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8676 }
8677
8678 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8679                                       u32 idt_vectoring_info,
8680                                       int instr_len_field,
8681                                       int error_code_field)
8682 {
8683         u8 vector;
8684         int type;
8685         bool idtv_info_valid;
8686
8687         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8688
8689         vcpu->arch.nmi_injected = false;
8690         kvm_clear_exception_queue(vcpu);
8691         kvm_clear_interrupt_queue(vcpu);
8692
8693         if (!idtv_info_valid)
8694                 return;
8695
8696         kvm_make_request(KVM_REQ_EVENT, vcpu);
8697
8698         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8699         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8700
8701         switch (type) {
8702         case INTR_TYPE_NMI_INTR:
8703                 vcpu->arch.nmi_injected = true;
8704                 /*
8705                  * SDM 3: 27.7.1.2 (September 2008)
8706                  * Clear bit "block by NMI" before VM entry if a NMI
8707                  * delivery faulted.
8708                  */
8709                 vmx_set_nmi_mask(vcpu, false);
8710                 break;
8711         case INTR_TYPE_SOFT_EXCEPTION:
8712                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8713                 /* fall through */
8714         case INTR_TYPE_HARD_EXCEPTION:
8715                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8716                         u32 err = vmcs_read32(error_code_field);
8717                         kvm_requeue_exception_e(vcpu, vector, err);
8718                 } else
8719                         kvm_requeue_exception(vcpu, vector);
8720                 break;
8721         case INTR_TYPE_SOFT_INTR:
8722                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8723                 /* fall through */
8724         case INTR_TYPE_EXT_INTR:
8725                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8726                 break;
8727         default:
8728                 break;
8729         }
8730 }
8731
8732 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8733 {
8734         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8735                                   VM_EXIT_INSTRUCTION_LEN,
8736                                   IDT_VECTORING_ERROR_CODE);
8737 }
8738
8739 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8740 {
8741         __vmx_complete_interrupts(vcpu,
8742                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8743                                   VM_ENTRY_INSTRUCTION_LEN,
8744                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8745
8746         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8747 }
8748
8749 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8750 {
8751         int i, nr_msrs;
8752         struct perf_guest_switch_msr *msrs;
8753
8754         msrs = perf_guest_get_msrs(&nr_msrs);
8755
8756         if (!msrs)
8757                 return;
8758
8759         for (i = 0; i < nr_msrs; i++)
8760                 if (msrs[i].host == msrs[i].guest)
8761                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8762                 else
8763                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8764                                         msrs[i].host);
8765 }
8766
8767 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8768 {
8769         struct vcpu_vmx *vmx = to_vmx(vcpu);
8770         u64 tscl;
8771         u32 delta_tsc;
8772
8773         if (vmx->hv_deadline_tsc == -1)
8774                 return;
8775
8776         tscl = rdtsc();
8777         if (vmx->hv_deadline_tsc > tscl)
8778                 /* sure to be 32 bit only because checked on set_hv_timer */
8779                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8780                         cpu_preemption_timer_multi);
8781         else
8782                 delta_tsc = 0;
8783
8784         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8785 }
8786
8787 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8788 {
8789         struct vcpu_vmx *vmx = to_vmx(vcpu);
8790         unsigned long debugctlmsr, cr4;
8791
8792         /* Record the guest's net vcpu time for enforced NMI injections. */
8793         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8794                 vmx->entry_time = ktime_get();
8795
8796         /* Don't enter VMX if guest state is invalid, let the exit handler
8797            start emulation until we arrive back to a valid state */
8798         if (vmx->emulation_required)
8799                 return;
8800
8801         if (vmx->ple_window_dirty) {
8802                 vmx->ple_window_dirty = false;
8803                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8804         }
8805
8806         if (vmx->nested.sync_shadow_vmcs) {
8807                 copy_vmcs12_to_shadow(vmx);
8808                 vmx->nested.sync_shadow_vmcs = false;
8809         }
8810
8811         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8812                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8813         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8814                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8815
8816         cr4 = cr4_read_shadow();
8817         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8818                 vmcs_writel(HOST_CR4, cr4);
8819                 vmx->host_state.vmcs_host_cr4 = cr4;
8820         }
8821
8822         /* When single-stepping over STI and MOV SS, we must clear the
8823          * corresponding interruptibility bits in the guest state. Otherwise
8824          * vmentry fails as it then expects bit 14 (BS) in pending debug
8825          * exceptions being set, but that's not correct for the guest debugging
8826          * case. */
8827         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8828                 vmx_set_interrupt_shadow(vcpu, 0);
8829
8830         if (vmx->guest_pkru_valid)
8831                 __write_pkru(vmx->guest_pkru);
8832
8833         atomic_switch_perf_msrs(vmx);
8834         debugctlmsr = get_debugctlmsr();
8835
8836         vmx_arm_hv_timer(vcpu);
8837
8838         vmx->__launched = vmx->loaded_vmcs->launched;
8839         asm(
8840                 /* Store host registers */
8841                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8842                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8843                 "push %%" _ASM_CX " \n\t"
8844                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8845                 "je 1f \n\t"
8846                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8847                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8848                 "1: \n\t"
8849                 /* Reload cr2 if changed */
8850                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8851                 "mov %%cr2, %%" _ASM_DX " \n\t"
8852                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8853                 "je 2f \n\t"
8854                 "mov %%" _ASM_AX", %%cr2 \n\t"
8855                 "2: \n\t"
8856                 /* Check if vmlaunch of vmresume is needed */
8857                 "cmpl $0, %c[launched](%0) \n\t"
8858                 /* Load guest registers.  Don't clobber flags. */
8859                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8860                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8861                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8862                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8863                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8864                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8865 #ifdef CONFIG_X86_64
8866                 "mov %c[r8](%0),  %%r8  \n\t"
8867                 "mov %c[r9](%0),  %%r9  \n\t"
8868                 "mov %c[r10](%0), %%r10 \n\t"
8869                 "mov %c[r11](%0), %%r11 \n\t"
8870                 "mov %c[r12](%0), %%r12 \n\t"
8871                 "mov %c[r13](%0), %%r13 \n\t"
8872                 "mov %c[r14](%0), %%r14 \n\t"
8873                 "mov %c[r15](%0), %%r15 \n\t"
8874 #endif
8875                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8876
8877                 /* Enter guest mode */
8878                 "jne 1f \n\t"
8879                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8880                 "jmp 2f \n\t"
8881                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8882                 "2: "
8883                 /* Save guest registers, load host registers, keep flags */
8884                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8885                 "pop %0 \n\t"
8886                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8887                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8888                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8889                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8890                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8891                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8892                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8893 #ifdef CONFIG_X86_64
8894                 "mov %%r8,  %c[r8](%0) \n\t"
8895                 "mov %%r9,  %c[r9](%0) \n\t"
8896                 "mov %%r10, %c[r10](%0) \n\t"
8897                 "mov %%r11, %c[r11](%0) \n\t"
8898                 "mov %%r12, %c[r12](%0) \n\t"
8899                 "mov %%r13, %c[r13](%0) \n\t"
8900                 "mov %%r14, %c[r14](%0) \n\t"
8901                 "mov %%r15, %c[r15](%0) \n\t"
8902 #endif
8903                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8904                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8905
8906                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8907                 "setbe %c[fail](%0) \n\t"
8908                 ".pushsection .rodata \n\t"
8909                 ".global vmx_return \n\t"
8910                 "vmx_return: " _ASM_PTR " 2b \n\t"
8911                 ".popsection"
8912               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8913                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8914                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8915                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8916                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8917                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8918                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8919                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8920                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8921                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8922                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8923 #ifdef CONFIG_X86_64
8924                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8925                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8926                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8927                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8928                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8929                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8930                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8931                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8932 #endif
8933                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8934                 [wordsize]"i"(sizeof(ulong))
8935               : "cc", "memory"
8936 #ifdef CONFIG_X86_64
8937                 , "rax", "rbx", "rdi", "rsi"
8938                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8939 #else
8940                 , "eax", "ebx", "edi", "esi"
8941 #endif
8942               );
8943
8944         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8945         if (debugctlmsr)
8946                 update_debugctlmsr(debugctlmsr);
8947
8948 #ifndef CONFIG_X86_64
8949         /*
8950          * The sysexit path does not restore ds/es, so we must set them to
8951          * a reasonable value ourselves.
8952          *
8953          * We can't defer this to vmx_load_host_state() since that function
8954          * may be executed in interrupt context, which saves and restore segments
8955          * around it, nullifying its effect.
8956          */
8957         loadsegment(ds, __USER_DS);
8958         loadsegment(es, __USER_DS);
8959 #endif
8960
8961         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8962                                   | (1 << VCPU_EXREG_RFLAGS)
8963                                   | (1 << VCPU_EXREG_PDPTR)
8964                                   | (1 << VCPU_EXREG_SEGMENTS)
8965                                   | (1 << VCPU_EXREG_CR3));
8966         vcpu->arch.regs_dirty = 0;
8967
8968         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8969
8970         vmx->loaded_vmcs->launched = 1;
8971
8972         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8973
8974         /*
8975          * eager fpu is enabled if PKEY is supported and CR4 is switched
8976          * back on host, so it is safe to read guest PKRU from current
8977          * XSAVE.
8978          */
8979         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8980                 vmx->guest_pkru = __read_pkru();
8981                 if (vmx->guest_pkru != vmx->host_pkru) {
8982                         vmx->guest_pkru_valid = true;
8983                         __write_pkru(vmx->host_pkru);
8984                 } else
8985                         vmx->guest_pkru_valid = false;
8986         }
8987
8988         /*
8989          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8990          * we did not inject a still-pending event to L1 now because of
8991          * nested_run_pending, we need to re-enable this bit.
8992          */
8993         if (vmx->nested.nested_run_pending)
8994                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8995
8996         vmx->nested.nested_run_pending = 0;
8997
8998         vmx_complete_atomic_exit(vmx);
8999         vmx_recover_nmi_blocking(vmx);
9000         vmx_complete_interrupts(vmx);
9001 }
9002
9003 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9004 {
9005         struct vcpu_vmx *vmx = to_vmx(vcpu);
9006         int cpu;
9007
9008         if (vmx->loaded_vmcs == &vmx->vmcs01)
9009                 return;
9010
9011         cpu = get_cpu();
9012         vmx->loaded_vmcs = &vmx->vmcs01;
9013         vmx_vcpu_put(vcpu);
9014         vmx_vcpu_load(vcpu, cpu);
9015         vcpu->cpu = cpu;
9016         put_cpu();
9017 }
9018
9019 /*
9020  * Ensure that the current vmcs of the logical processor is the
9021  * vmcs01 of the vcpu before calling free_nested().
9022  */
9023 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9024 {
9025        struct vcpu_vmx *vmx = to_vmx(vcpu);
9026        int r;
9027
9028        r = vcpu_load(vcpu);
9029        BUG_ON(r);
9030        vmx_load_vmcs01(vcpu);
9031        free_nested(vmx);
9032        vcpu_put(vcpu);
9033 }
9034
9035 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9036 {
9037         struct vcpu_vmx *vmx = to_vmx(vcpu);
9038
9039         if (enable_pml)
9040                 vmx_destroy_pml_buffer(vmx);
9041         free_vpid(vmx->vpid);
9042         leave_guest_mode(vcpu);
9043         vmx_free_vcpu_nested(vcpu);
9044         free_loaded_vmcs(vmx->loaded_vmcs);
9045         kfree(vmx->guest_msrs);
9046         kvm_vcpu_uninit(vcpu);
9047         kmem_cache_free(kvm_vcpu_cache, vmx);
9048 }
9049
9050 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9051 {
9052         int err;
9053         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9054         int cpu;
9055
9056         if (!vmx)
9057                 return ERR_PTR(-ENOMEM);
9058
9059         vmx->vpid = allocate_vpid();
9060
9061         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9062         if (err)
9063                 goto free_vcpu;
9064
9065         err = -ENOMEM;
9066
9067         /*
9068          * If PML is turned on, failure on enabling PML just results in failure
9069          * of creating the vcpu, therefore we can simplify PML logic (by
9070          * avoiding dealing with cases, such as enabling PML partially on vcpus
9071          * for the guest, etc.
9072          */
9073         if (enable_pml) {
9074                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9075                 if (!vmx->pml_pg)
9076                         goto uninit_vcpu;
9077         }
9078
9079         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9080         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9081                      > PAGE_SIZE);
9082
9083         if (!vmx->guest_msrs)
9084                 goto free_pml;
9085
9086         vmx->loaded_vmcs = &vmx->vmcs01;
9087         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9088         vmx->loaded_vmcs->shadow_vmcs = NULL;
9089         if (!vmx->loaded_vmcs->vmcs)
9090                 goto free_msrs;
9091         if (!vmm_exclusive)
9092                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9093         loaded_vmcs_init(vmx->loaded_vmcs);
9094         if (!vmm_exclusive)
9095                 kvm_cpu_vmxoff();
9096
9097         cpu = get_cpu();
9098         vmx_vcpu_load(&vmx->vcpu, cpu);
9099         vmx->vcpu.cpu = cpu;
9100         err = vmx_vcpu_setup(vmx);
9101         vmx_vcpu_put(&vmx->vcpu);
9102         put_cpu();
9103         if (err)
9104                 goto free_vmcs;
9105         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9106                 err = alloc_apic_access_page(kvm);
9107                 if (err)
9108                         goto free_vmcs;
9109         }
9110
9111         if (enable_ept) {
9112                 if (!kvm->arch.ept_identity_map_addr)
9113                         kvm->arch.ept_identity_map_addr =
9114                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9115                 err = init_rmode_identity_map(kvm);
9116                 if (err)
9117                         goto free_vmcs;
9118         }
9119
9120         if (nested) {
9121                 nested_vmx_setup_ctls_msrs(vmx);
9122                 vmx->nested.vpid02 = allocate_vpid();
9123         }
9124
9125         vmx->nested.posted_intr_nv = -1;
9126         vmx->nested.current_vmptr = -1ull;
9127         vmx->nested.current_vmcs12 = NULL;
9128
9129         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9130
9131         return &vmx->vcpu;
9132
9133 free_vmcs:
9134         free_vpid(vmx->nested.vpid02);
9135         free_loaded_vmcs(vmx->loaded_vmcs);
9136 free_msrs:
9137         kfree(vmx->guest_msrs);
9138 free_pml:
9139         vmx_destroy_pml_buffer(vmx);
9140 uninit_vcpu:
9141         kvm_vcpu_uninit(&vmx->vcpu);
9142 free_vcpu:
9143         free_vpid(vmx->vpid);
9144         kmem_cache_free(kvm_vcpu_cache, vmx);
9145         return ERR_PTR(err);
9146 }
9147
9148 static void __init vmx_check_processor_compat(void *rtn)
9149 {
9150         struct vmcs_config vmcs_conf;
9151
9152         *(int *)rtn = 0;
9153         if (setup_vmcs_config(&vmcs_conf) < 0)
9154                 *(int *)rtn = -EIO;
9155         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9156                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9157                                 smp_processor_id());
9158                 *(int *)rtn = -EIO;
9159         }
9160 }
9161
9162 static int get_ept_level(void)
9163 {
9164         return VMX_EPT_DEFAULT_GAW + 1;
9165 }
9166
9167 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9168 {
9169         u8 cache;
9170         u64 ipat = 0;
9171
9172         /* For VT-d and EPT combination
9173          * 1. MMIO: always map as UC
9174          * 2. EPT with VT-d:
9175          *   a. VT-d without snooping control feature: can't guarantee the
9176          *      result, try to trust guest.
9177          *   b. VT-d with snooping control feature: snooping control feature of
9178          *      VT-d engine can guarantee the cache correctness. Just set it
9179          *      to WB to keep consistent with host. So the same as item 3.
9180          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9181          *    consistent with host MTRR
9182          */
9183         if (is_mmio) {
9184                 cache = MTRR_TYPE_UNCACHABLE;
9185                 goto exit;
9186         }
9187
9188         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9189                 ipat = VMX_EPT_IPAT_BIT;
9190                 cache = MTRR_TYPE_WRBACK;
9191                 goto exit;
9192         }
9193
9194         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9195                 ipat = VMX_EPT_IPAT_BIT;
9196                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9197                         cache = MTRR_TYPE_WRBACK;
9198                 else
9199                         cache = MTRR_TYPE_UNCACHABLE;
9200                 goto exit;
9201         }
9202
9203         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9204
9205 exit:
9206         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9207 }
9208
9209 static int vmx_get_lpage_level(void)
9210 {
9211         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9212                 return PT_DIRECTORY_LEVEL;
9213         else
9214                 /* For shadow and EPT supported 1GB page */
9215                 return PT_PDPE_LEVEL;
9216 }
9217
9218 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9219 {
9220         /*
9221          * These bits in the secondary execution controls field
9222          * are dynamic, the others are mostly based on the hypervisor
9223          * architecture and the guest's CPUID.  Do not touch the
9224          * dynamic bits.
9225          */
9226         u32 mask =
9227                 SECONDARY_EXEC_SHADOW_VMCS |
9228                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9229                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9230
9231         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9232
9233         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9234                      (new_ctl & ~mask) | (cur_ctl & mask));
9235 }
9236
9237 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9238 {
9239         struct kvm_cpuid_entry2 *best;
9240         struct vcpu_vmx *vmx = to_vmx(vcpu);
9241         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9242
9243         if (vmx_rdtscp_supported()) {
9244                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9245                 if (!rdtscp_enabled)
9246                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9247
9248                 if (nested) {
9249                         if (rdtscp_enabled)
9250                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9251                                         SECONDARY_EXEC_RDTSCP;
9252                         else
9253                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9254                                         ~SECONDARY_EXEC_RDTSCP;
9255                 }
9256         }
9257
9258         /* Exposing INVPCID only when PCID is exposed */
9259         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9260         if (vmx_invpcid_supported() &&
9261             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9262             !guest_cpuid_has_pcid(vcpu))) {
9263                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9264
9265                 if (best)
9266                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9267         }
9268
9269         if (cpu_has_secondary_exec_ctrls())
9270                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9271
9272         if (nested_vmx_allowed(vcpu))
9273                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9274                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9275         else
9276                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9277                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9278 }
9279
9280 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9281 {
9282         if (func == 1 && nested)
9283                 entry->ecx |= bit(X86_FEATURE_VMX);
9284 }
9285
9286 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9287                 struct x86_exception *fault)
9288 {
9289         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9290         u32 exit_reason;
9291
9292         if (fault->error_code & PFERR_RSVD_MASK)
9293                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9294         else
9295                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9296         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9297         vmcs12->guest_physical_address = fault->address;
9298 }
9299
9300 /* Callbacks for nested_ept_init_mmu_context: */
9301
9302 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9303 {
9304         /* return the page table to be shadowed - in our case, EPT12 */
9305         return get_vmcs12(vcpu)->ept_pointer;
9306 }
9307
9308 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9309 {
9310         WARN_ON(mmu_is_nested(vcpu));
9311         kvm_init_shadow_ept_mmu(vcpu,
9312                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9313                         VMX_EPT_EXECUTE_ONLY_BIT);
9314         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9315         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9316         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9317
9318         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9319 }
9320
9321 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9322 {
9323         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9324 }
9325
9326 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9327                                             u16 error_code)
9328 {
9329         bool inequality, bit;
9330
9331         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9332         inequality =
9333                 (error_code & vmcs12->page_fault_error_code_mask) !=
9334                  vmcs12->page_fault_error_code_match;
9335         return inequality ^ bit;
9336 }
9337
9338 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9339                 struct x86_exception *fault)
9340 {
9341         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9342
9343         WARN_ON(!is_guest_mode(vcpu));
9344
9345         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9346                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9347                                   vmcs_read32(VM_EXIT_INTR_INFO),
9348                                   vmcs_readl(EXIT_QUALIFICATION));
9349         else
9350                 kvm_inject_page_fault(vcpu, fault);
9351 }
9352
9353 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9354                                         struct vmcs12 *vmcs12)
9355 {
9356         struct vcpu_vmx *vmx = to_vmx(vcpu);
9357         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9358
9359         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9360                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9361                     vmcs12->apic_access_addr >> maxphyaddr)
9362                         return false;
9363
9364                 /*
9365                  * Translate L1 physical address to host physical
9366                  * address for vmcs02. Keep the page pinned, so this
9367                  * physical address remains valid. We keep a reference
9368                  * to it so we can release it later.
9369                  */
9370                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9371                         nested_release_page(vmx->nested.apic_access_page);
9372                 vmx->nested.apic_access_page =
9373                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9374         }
9375
9376         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9377                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9378                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9379                         return false;
9380
9381                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9382                         nested_release_page(vmx->nested.virtual_apic_page);
9383                 vmx->nested.virtual_apic_page =
9384                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9385
9386                 /*
9387                  * Failing the vm entry is _not_ what the processor does
9388                  * but it's basically the only possibility we have.
9389                  * We could still enter the guest if CR8 load exits are
9390                  * enabled, CR8 store exits are enabled, and virtualize APIC
9391                  * access is disabled; in this case the processor would never
9392                  * use the TPR shadow and we could simply clear the bit from
9393                  * the execution control.  But such a configuration is useless,
9394                  * so let's keep the code simple.
9395                  */
9396                 if (!vmx->nested.virtual_apic_page)
9397                         return false;
9398         }
9399
9400         if (nested_cpu_has_posted_intr(vmcs12)) {
9401                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9402                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9403                         return false;
9404
9405                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9406                         kunmap(vmx->nested.pi_desc_page);
9407                         nested_release_page(vmx->nested.pi_desc_page);
9408                 }
9409                 vmx->nested.pi_desc_page =
9410                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9411                 if (!vmx->nested.pi_desc_page)
9412                         return false;
9413
9414                 vmx->nested.pi_desc =
9415                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9416                 if (!vmx->nested.pi_desc) {
9417                         nested_release_page_clean(vmx->nested.pi_desc_page);
9418                         return false;
9419                 }
9420                 vmx->nested.pi_desc =
9421                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9422                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9423                         (PAGE_SIZE - 1)));
9424         }
9425
9426         return true;
9427 }
9428
9429 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9430 {
9431         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9432         struct vcpu_vmx *vmx = to_vmx(vcpu);
9433
9434         if (vcpu->arch.virtual_tsc_khz == 0)
9435                 return;
9436
9437         /* Make sure short timeouts reliably trigger an immediate vmexit.
9438          * hrtimer_start does not guarantee this. */
9439         if (preemption_timeout <= 1) {
9440                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9441                 return;
9442         }
9443
9444         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9445         preemption_timeout *= 1000000;
9446         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9447         hrtimer_start(&vmx->nested.preemption_timer,
9448                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9449 }
9450
9451 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9452                                                 struct vmcs12 *vmcs12)
9453 {
9454         int maxphyaddr;
9455         u64 addr;
9456
9457         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9458                 return 0;
9459
9460         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9461                 WARN_ON(1);
9462                 return -EINVAL;
9463         }
9464         maxphyaddr = cpuid_maxphyaddr(vcpu);
9465
9466         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9467            ((addr + PAGE_SIZE) >> maxphyaddr))
9468                 return -EINVAL;
9469
9470         return 0;
9471 }
9472
9473 /*
9474  * Merge L0's and L1's MSR bitmap, return false to indicate that
9475  * we do not use the hardware.
9476  */
9477 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9478                                                struct vmcs12 *vmcs12)
9479 {
9480         int msr;
9481         struct page *page;
9482         unsigned long *msr_bitmap_l1;
9483         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9484
9485         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9486         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9487                 return false;
9488
9489         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9490         if (!page) {
9491                 WARN_ON(1);
9492                 return false;
9493         }
9494         msr_bitmap_l1 = (unsigned long *)kmap(page);
9495         if (!msr_bitmap_l1) {
9496                 nested_release_page_clean(page);
9497                 WARN_ON(1);
9498                 return false;
9499         }
9500
9501         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9502
9503         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9504                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9505                         for (msr = 0x800; msr <= 0x8ff; msr++)
9506                                 nested_vmx_disable_intercept_for_msr(
9507                                         msr_bitmap_l1, msr_bitmap_l0,
9508                                         msr, MSR_TYPE_R);
9509
9510                 nested_vmx_disable_intercept_for_msr(
9511                                 msr_bitmap_l1, msr_bitmap_l0,
9512                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9513                                 MSR_TYPE_R | MSR_TYPE_W);
9514
9515                 if (nested_cpu_has_vid(vmcs12)) {
9516                         nested_vmx_disable_intercept_for_msr(
9517                                 msr_bitmap_l1, msr_bitmap_l0,
9518                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9519                                 MSR_TYPE_W);
9520                         nested_vmx_disable_intercept_for_msr(
9521                                 msr_bitmap_l1, msr_bitmap_l0,
9522                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9523                                 MSR_TYPE_W);
9524                 }
9525         }
9526         kunmap(page);
9527         nested_release_page_clean(page);
9528
9529         return true;
9530 }
9531
9532 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9533                                            struct vmcs12 *vmcs12)
9534 {
9535         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9536             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9537             !nested_cpu_has_vid(vmcs12) &&
9538             !nested_cpu_has_posted_intr(vmcs12))
9539                 return 0;
9540
9541         /*
9542          * If virtualize x2apic mode is enabled,
9543          * virtualize apic access must be disabled.
9544          */
9545         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9546             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9547                 return -EINVAL;
9548
9549         /*
9550          * If virtual interrupt delivery is enabled,
9551          * we must exit on external interrupts.
9552          */
9553         if (nested_cpu_has_vid(vmcs12) &&
9554            !nested_exit_on_intr(vcpu))
9555                 return -EINVAL;
9556
9557         /*
9558          * bits 15:8 should be zero in posted_intr_nv,
9559          * the descriptor address has been already checked
9560          * in nested_get_vmcs12_pages.
9561          */
9562         if (nested_cpu_has_posted_intr(vmcs12) &&
9563            (!nested_cpu_has_vid(vmcs12) ||
9564             !nested_exit_intr_ack_set(vcpu) ||
9565             vmcs12->posted_intr_nv & 0xff00))
9566                 return -EINVAL;
9567
9568         /* tpr shadow is needed by all apicv features. */
9569         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9570                 return -EINVAL;
9571
9572         return 0;
9573 }
9574
9575 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9576                                        unsigned long count_field,
9577                                        unsigned long addr_field)
9578 {
9579         int maxphyaddr;
9580         u64 count, addr;
9581
9582         if (vmcs12_read_any(vcpu, count_field, &count) ||
9583             vmcs12_read_any(vcpu, addr_field, &addr)) {
9584                 WARN_ON(1);
9585                 return -EINVAL;
9586         }
9587         if (count == 0)
9588                 return 0;
9589         maxphyaddr = cpuid_maxphyaddr(vcpu);
9590         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9591             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9592                 pr_debug_ratelimited(
9593                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9594                         addr_field, maxphyaddr, count, addr);
9595                 return -EINVAL;
9596         }
9597         return 0;
9598 }
9599
9600 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9601                                                 struct vmcs12 *vmcs12)
9602 {
9603         if (vmcs12->vm_exit_msr_load_count == 0 &&
9604             vmcs12->vm_exit_msr_store_count == 0 &&
9605             vmcs12->vm_entry_msr_load_count == 0)
9606                 return 0; /* Fast path */
9607         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9608                                         VM_EXIT_MSR_LOAD_ADDR) ||
9609             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9610                                         VM_EXIT_MSR_STORE_ADDR) ||
9611             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9612                                         VM_ENTRY_MSR_LOAD_ADDR))
9613                 return -EINVAL;
9614         return 0;
9615 }
9616
9617 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9618                                        struct vmx_msr_entry *e)
9619 {
9620         /* x2APIC MSR accesses are not allowed */
9621         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9622                 return -EINVAL;
9623         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9624             e->index == MSR_IA32_UCODE_REV)
9625                 return -EINVAL;
9626         if (e->reserved != 0)
9627                 return -EINVAL;
9628         return 0;
9629 }
9630
9631 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9632                                      struct vmx_msr_entry *e)
9633 {
9634         if (e->index == MSR_FS_BASE ||
9635             e->index == MSR_GS_BASE ||
9636             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9637             nested_vmx_msr_check_common(vcpu, e))
9638                 return -EINVAL;
9639         return 0;
9640 }
9641
9642 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9643                                       struct vmx_msr_entry *e)
9644 {
9645         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9646             nested_vmx_msr_check_common(vcpu, e))
9647                 return -EINVAL;
9648         return 0;
9649 }
9650
9651 /*
9652  * Load guest's/host's msr at nested entry/exit.
9653  * return 0 for success, entry index for failure.
9654  */
9655 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9656 {
9657         u32 i;
9658         struct vmx_msr_entry e;
9659         struct msr_data msr;
9660
9661         msr.host_initiated = false;
9662         for (i = 0; i < count; i++) {
9663                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9664                                         &e, sizeof(e))) {
9665                         pr_debug_ratelimited(
9666                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9667                                 __func__, i, gpa + i * sizeof(e));
9668                         goto fail;
9669                 }
9670                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9671                         pr_debug_ratelimited(
9672                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9673                                 __func__, i, e.index, e.reserved);
9674                         goto fail;
9675                 }
9676                 msr.index = e.index;
9677                 msr.data = e.value;
9678                 if (kvm_set_msr(vcpu, &msr)) {
9679                         pr_debug_ratelimited(
9680                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9681                                 __func__, i, e.index, e.value);
9682                         goto fail;
9683                 }
9684         }
9685         return 0;
9686 fail:
9687         return i + 1;
9688 }
9689
9690 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9691 {
9692         u32 i;
9693         struct vmx_msr_entry e;
9694
9695         for (i = 0; i < count; i++) {
9696                 struct msr_data msr_info;
9697                 if (kvm_vcpu_read_guest(vcpu,
9698                                         gpa + i * sizeof(e),
9699                                         &e, 2 * sizeof(u32))) {
9700                         pr_debug_ratelimited(
9701                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9702                                 __func__, i, gpa + i * sizeof(e));
9703                         return -EINVAL;
9704                 }
9705                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9706                         pr_debug_ratelimited(
9707                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9708                                 __func__, i, e.index, e.reserved);
9709                         return -EINVAL;
9710                 }
9711                 msr_info.host_initiated = false;
9712                 msr_info.index = e.index;
9713                 if (kvm_get_msr(vcpu, &msr_info)) {
9714                         pr_debug_ratelimited(
9715                                 "%s cannot read MSR (%u, 0x%x)\n",
9716                                 __func__, i, e.index);
9717                         return -EINVAL;
9718                 }
9719                 if (kvm_vcpu_write_guest(vcpu,
9720                                          gpa + i * sizeof(e) +
9721                                              offsetof(struct vmx_msr_entry, value),
9722                                          &msr_info.data, sizeof(msr_info.data))) {
9723                         pr_debug_ratelimited(
9724                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9725                                 __func__, i, e.index, msr_info.data);
9726                         return -EINVAL;
9727                 }
9728         }
9729         return 0;
9730 }
9731
9732 /*
9733  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9734  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9735  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9736  * guest in a way that will both be appropriate to L1's requests, and our
9737  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9738  * function also has additional necessary side-effects, like setting various
9739  * vcpu->arch fields.
9740  */
9741 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9742 {
9743         struct vcpu_vmx *vmx = to_vmx(vcpu);
9744         u32 exec_control;
9745
9746         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9747         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9748         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9749         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9750         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9751         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9752         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9753         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9754         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9755         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9756         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9757         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9758         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9759         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9760         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9761         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9762         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9763         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9764         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9765         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9766         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9767         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9768         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9769         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9770         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9771         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9772         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9773         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9774         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9775         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9776         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9777         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9778         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9779         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9780         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9781         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9782
9783         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9784                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9785                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9786         } else {
9787                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9788                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9789         }
9790         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9791                 vmcs12->vm_entry_intr_info_field);
9792         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9793                 vmcs12->vm_entry_exception_error_code);
9794         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9795                 vmcs12->vm_entry_instruction_len);
9796         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9797                 vmcs12->guest_interruptibility_info);
9798         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9799         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9800         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9801                 vmcs12->guest_pending_dbg_exceptions);
9802         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9803         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9804
9805         if (nested_cpu_has_xsaves(vmcs12))
9806                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9807         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9808
9809         exec_control = vmcs12->pin_based_vm_exec_control;
9810
9811         /* Preemption timer setting is only taken from vmcs01.  */
9812         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9813         exec_control |= vmcs_config.pin_based_exec_ctrl;
9814         if (vmx->hv_deadline_tsc == -1)
9815                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9816
9817         /* Posted interrupts setting is only taken from vmcs12.  */
9818         if (nested_cpu_has_posted_intr(vmcs12)) {
9819                 /*
9820                  * Note that we use L0's vector here and in
9821                  * vmx_deliver_nested_posted_interrupt.
9822                  */
9823                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9824                 vmx->nested.pi_pending = false;
9825                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9826                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9827                         page_to_phys(vmx->nested.pi_desc_page) +
9828                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9829                         (PAGE_SIZE - 1)));
9830         } else
9831                 exec_control &= ~PIN_BASED_POSTED_INTR;
9832
9833         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9834
9835         vmx->nested.preemption_timer_expired = false;
9836         if (nested_cpu_has_preemption_timer(vmcs12))
9837                 vmx_start_preemption_timer(vcpu);
9838
9839         /*
9840          * Whether page-faults are trapped is determined by a combination of
9841          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9842          * If enable_ept, L0 doesn't care about page faults and we should
9843          * set all of these to L1's desires. However, if !enable_ept, L0 does
9844          * care about (at least some) page faults, and because it is not easy
9845          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9846          * to exit on each and every L2 page fault. This is done by setting
9847          * MASK=MATCH=0 and (see below) EB.PF=1.
9848          * Note that below we don't need special code to set EB.PF beyond the
9849          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9850          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9851          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9852          *
9853          * A problem with this approach (when !enable_ept) is that L1 may be
9854          * injected with more page faults than it asked for. This could have
9855          * caused problems, but in practice existing hypervisors don't care.
9856          * To fix this, we will need to emulate the PFEC checking (on the L1
9857          * page tables), using walk_addr(), when injecting PFs to L1.
9858          */
9859         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9860                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9861         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9862                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9863
9864         if (cpu_has_secondary_exec_ctrls()) {
9865                 exec_control = vmx_secondary_exec_control(vmx);
9866
9867                 /* Take the following fields only from vmcs12 */
9868                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9869                                   SECONDARY_EXEC_RDTSCP |
9870                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9871                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9872                 if (nested_cpu_has(vmcs12,
9873                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9874                         exec_control |= vmcs12->secondary_vm_exec_control;
9875
9876                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9877                         /*
9878                          * If translation failed, no matter: This feature asks
9879                          * to exit when accessing the given address, and if it
9880                          * can never be accessed, this feature won't do
9881                          * anything anyway.
9882                          */
9883                         if (!vmx->nested.apic_access_page)
9884                                 exec_control &=
9885                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9886                         else
9887                                 vmcs_write64(APIC_ACCESS_ADDR,
9888                                   page_to_phys(vmx->nested.apic_access_page));
9889                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9890                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9891                         exec_control |=
9892                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9893                         kvm_vcpu_reload_apic_access_page(vcpu);
9894                 }
9895
9896                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9897                         vmcs_write64(EOI_EXIT_BITMAP0,
9898                                 vmcs12->eoi_exit_bitmap0);
9899                         vmcs_write64(EOI_EXIT_BITMAP1,
9900                                 vmcs12->eoi_exit_bitmap1);
9901                         vmcs_write64(EOI_EXIT_BITMAP2,
9902                                 vmcs12->eoi_exit_bitmap2);
9903                         vmcs_write64(EOI_EXIT_BITMAP3,
9904                                 vmcs12->eoi_exit_bitmap3);
9905                         vmcs_write16(GUEST_INTR_STATUS,
9906                                 vmcs12->guest_intr_status);
9907                 }
9908
9909                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9910         }
9911
9912
9913         /*
9914          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9915          * Some constant fields are set here by vmx_set_constant_host_state().
9916          * Other fields are different per CPU, and will be set later when
9917          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9918          */
9919         vmx_set_constant_host_state(vmx);
9920
9921         /*
9922          * Set the MSR load/store lists to match L0's settings.
9923          */
9924         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
9925         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
9926         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
9927         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
9928         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
9929
9930         /*
9931          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9932          * entry, but only if the current (host) sp changed from the value
9933          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9934          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9935          * here we just force the write to happen on entry.
9936          */
9937         vmx->host_rsp = 0;
9938
9939         exec_control = vmx_exec_control(vmx); /* L0's desires */
9940         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9941         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9942         exec_control &= ~CPU_BASED_TPR_SHADOW;
9943         exec_control |= vmcs12->cpu_based_vm_exec_control;
9944
9945         if (exec_control & CPU_BASED_TPR_SHADOW) {
9946                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9947                                 page_to_phys(vmx->nested.virtual_apic_page));
9948                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9949         }
9950
9951         if (cpu_has_vmx_msr_bitmap() &&
9952             exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9953             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9954                 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
9955         else
9956                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9957
9958         /*
9959          * Merging of IO bitmap not currently supported.
9960          * Rather, exit every time.
9961          */
9962         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9963         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9964
9965         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9966
9967         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9968          * bitwise-or of what L1 wants to trap for L2, and what we want to
9969          * trap. Note that CR0.TS also needs updating - we do this later.
9970          */
9971         update_exception_bitmap(vcpu);
9972         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9973         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9974
9975         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9976          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9977          * bits are further modified by vmx_set_efer() below.
9978          */
9979         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9980
9981         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9982          * emulated by vmx_set_efer(), below.
9983          */
9984         vm_entry_controls_init(vmx,
9985                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9986                         ~VM_ENTRY_IA32E_MODE) |
9987                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9988
9989         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9990                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9991                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9992         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9993                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9994
9995
9996         set_cr4_guest_host_mask(vmx);
9997
9998         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9999                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10000
10001         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10002                 vmcs_write64(TSC_OFFSET,
10003                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10004         else
10005                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10006         if (kvm_has_tsc_control)
10007                 decache_tsc_multiplier(vmx);
10008
10009         if (enable_vpid) {
10010                 /*
10011                  * There is no direct mapping between vpid02 and vpid12, the
10012                  * vpid02 is per-vCPU for L0 and reused while the value of
10013                  * vpid12 is changed w/ one invvpid during nested vmentry.
10014                  * The vpid12 is allocated by L1 for L2, so it will not
10015                  * influence global bitmap(for vpid01 and vpid02 allocation)
10016                  * even if spawn a lot of nested vCPUs.
10017                  */
10018                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10019                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10020                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10021                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10022                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10023                         }
10024                 } else {
10025                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10026                         vmx_flush_tlb(vcpu);
10027                 }
10028
10029         }
10030
10031         if (nested_cpu_has_ept(vmcs12)) {
10032                 kvm_mmu_unload(vcpu);
10033                 nested_ept_init_mmu_context(vcpu);
10034         }
10035
10036         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10037                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10038         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10039                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10040         else
10041                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10042         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10043         vmx_set_efer(vcpu, vcpu->arch.efer);
10044
10045         /*
10046          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10047          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10048          * The CR0_READ_SHADOW is what L2 should have expected to read given
10049          * the specifications by L1; It's not enough to take
10050          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10051          * have more bits than L1 expected.
10052          */
10053         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10054         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10055
10056         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10057         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10058
10059         /* shadow page tables on either EPT or shadow page tables */
10060         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10061         kvm_mmu_reset_context(vcpu);
10062
10063         if (!enable_ept)
10064                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10065
10066         /*
10067          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10068          */
10069         if (enable_ept) {
10070                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10071                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10072                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10073                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10074         }
10075
10076         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10077         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10078 }
10079
10080 /*
10081  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10082  * for running an L2 nested guest.
10083  */
10084 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10085 {
10086         struct vmcs12 *vmcs12;
10087         struct vcpu_vmx *vmx = to_vmx(vcpu);
10088         int cpu;
10089         struct loaded_vmcs *vmcs02;
10090         bool ia32e;
10091         u32 msr_entry_idx;
10092
10093         if (!nested_vmx_check_permission(vcpu) ||
10094             !nested_vmx_check_vmcs12(vcpu))
10095                 return 1;
10096
10097         skip_emulated_instruction(vcpu);
10098         vmcs12 = get_vmcs12(vcpu);
10099
10100         if (enable_shadow_vmcs)
10101                 copy_shadow_to_vmcs12(vmx);
10102
10103         /*
10104          * The nested entry process starts with enforcing various prerequisites
10105          * on vmcs12 as required by the Intel SDM, and act appropriately when
10106          * they fail: As the SDM explains, some conditions should cause the
10107          * instruction to fail, while others will cause the instruction to seem
10108          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10109          * To speed up the normal (success) code path, we should avoid checking
10110          * for misconfigurations which will anyway be caught by the processor
10111          * when using the merged vmcs02.
10112          */
10113         if (vmcs12->launch_state == launch) {
10114                 nested_vmx_failValid(vcpu,
10115                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10116                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10117                 return 1;
10118         }
10119
10120         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10121             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10122                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10123                 return 1;
10124         }
10125
10126         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10127                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10128                 return 1;
10129         }
10130
10131         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10132                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10133                 return 1;
10134         }
10135
10136         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10137                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10138                 return 1;
10139         }
10140
10141         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10142                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10143                 return 1;
10144         }
10145
10146         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10147                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
10148                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10149             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10150                                 vmx->nested.nested_vmx_secondary_ctls_low,
10151                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10152             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10153                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10154                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10155             !vmx_control_verify(vmcs12->vm_exit_controls,
10156                                 vmx->nested.nested_vmx_true_exit_ctls_low,
10157                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10158             !vmx_control_verify(vmcs12->vm_entry_controls,
10159                                 vmx->nested.nested_vmx_true_entry_ctls_low,
10160                                 vmx->nested.nested_vmx_entry_ctls_high))
10161         {
10162                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10163                 return 1;
10164         }
10165
10166         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10167             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10168                 nested_vmx_failValid(vcpu,
10169                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10170                 return 1;
10171         }
10172
10173         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10174             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10175                 nested_vmx_entry_failure(vcpu, vmcs12,
10176                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10177                 return 1;
10178         }
10179         if (vmcs12->vmcs_link_pointer != -1ull) {
10180                 nested_vmx_entry_failure(vcpu, vmcs12,
10181                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10182                 return 1;
10183         }
10184
10185         /*
10186          * If the load IA32_EFER VM-entry control is 1, the following checks
10187          * are performed on the field for the IA32_EFER MSR:
10188          * - Bits reserved in the IA32_EFER MSR must be 0.
10189          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10190          *   the IA-32e mode guest VM-exit control. It must also be identical
10191          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10192          *   CR0.PG) is 1.
10193          */
10194         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10195                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10196                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10197                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10198                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10199                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10200                         nested_vmx_entry_failure(vcpu, vmcs12,
10201                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10202                         return 1;
10203                 }
10204         }
10205
10206         /*
10207          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10208          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10209          * the values of the LMA and LME bits in the field must each be that of
10210          * the host address-space size VM-exit control.
10211          */
10212         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10213                 ia32e = (vmcs12->vm_exit_controls &
10214                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10215                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10216                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10217                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10218                         nested_vmx_entry_failure(vcpu, vmcs12,
10219                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10220                         return 1;
10221                 }
10222         }
10223
10224         /*
10225          * We're finally done with prerequisite checking, and can start with
10226          * the nested entry.
10227          */
10228
10229         vmcs02 = nested_get_current_vmcs02(vmx);
10230         if (!vmcs02)
10231                 return -ENOMEM;
10232
10233         enter_guest_mode(vcpu);
10234
10235         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10236                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10237
10238         cpu = get_cpu();
10239         vmx->loaded_vmcs = vmcs02;
10240         vmx_vcpu_put(vcpu);
10241         vmx_vcpu_load(vcpu, cpu);
10242         vcpu->cpu = cpu;
10243         put_cpu();
10244
10245         vmx_segment_cache_clear(vmx);
10246
10247         prepare_vmcs02(vcpu, vmcs12);
10248
10249         msr_entry_idx = nested_vmx_load_msr(vcpu,
10250                                             vmcs12->vm_entry_msr_load_addr,
10251                                             vmcs12->vm_entry_msr_load_count);
10252         if (msr_entry_idx) {
10253                 leave_guest_mode(vcpu);
10254                 vmx_load_vmcs01(vcpu);
10255                 nested_vmx_entry_failure(vcpu, vmcs12,
10256                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10257                 return 1;
10258         }
10259
10260         vmcs12->launch_state = 1;
10261
10262         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10263                 return kvm_vcpu_halt(vcpu);
10264
10265         vmx->nested.nested_run_pending = 1;
10266
10267         /*
10268          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10269          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10270          * returned as far as L1 is concerned. It will only return (and set
10271          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10272          */
10273         return 1;
10274 }
10275
10276 /*
10277  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10278  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10279  * This function returns the new value we should put in vmcs12.guest_cr0.
10280  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10281  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10282  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10283  *     didn't trap the bit, because if L1 did, so would L0).
10284  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10285  *     been modified by L2, and L1 knows it. So just leave the old value of
10286  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10287  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10288  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10289  *     changed these bits, and therefore they need to be updated, but L0
10290  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10291  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10292  */
10293 static inline unsigned long
10294 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10295 {
10296         return
10297         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10298         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10299         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10300                         vcpu->arch.cr0_guest_owned_bits));
10301 }
10302
10303 static inline unsigned long
10304 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10305 {
10306         return
10307         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10308         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10309         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10310                         vcpu->arch.cr4_guest_owned_bits));
10311 }
10312
10313 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10314                                        struct vmcs12 *vmcs12)
10315 {
10316         u32 idt_vectoring;
10317         unsigned int nr;
10318
10319         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10320                 nr = vcpu->arch.exception.nr;
10321                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10322
10323                 if (kvm_exception_is_soft(nr)) {
10324                         vmcs12->vm_exit_instruction_len =
10325                                 vcpu->arch.event_exit_inst_len;
10326                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10327                 } else
10328                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10329
10330                 if (vcpu->arch.exception.has_error_code) {
10331                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10332                         vmcs12->idt_vectoring_error_code =
10333                                 vcpu->arch.exception.error_code;
10334                 }
10335
10336                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10337         } else if (vcpu->arch.nmi_injected) {
10338                 vmcs12->idt_vectoring_info_field =
10339                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10340         } else if (vcpu->arch.interrupt.pending) {
10341                 nr = vcpu->arch.interrupt.nr;
10342                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10343
10344                 if (vcpu->arch.interrupt.soft) {
10345                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10346                         vmcs12->vm_entry_instruction_len =
10347                                 vcpu->arch.event_exit_inst_len;
10348                 } else
10349                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10350
10351                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10352         }
10353 }
10354
10355 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10356 {
10357         struct vcpu_vmx *vmx = to_vmx(vcpu);
10358
10359         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10360             vmx->nested.preemption_timer_expired) {
10361                 if (vmx->nested.nested_run_pending)
10362                         return -EBUSY;
10363                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10364                 return 0;
10365         }
10366
10367         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10368                 if (vmx->nested.nested_run_pending ||
10369                     vcpu->arch.interrupt.pending)
10370                         return -EBUSY;
10371                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10372                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10373                                   INTR_INFO_VALID_MASK, 0);
10374                 /*
10375                  * The NMI-triggered VM exit counts as injection:
10376                  * clear this one and block further NMIs.
10377                  */
10378                 vcpu->arch.nmi_pending = 0;
10379                 vmx_set_nmi_mask(vcpu, true);
10380                 return 0;
10381         }
10382
10383         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10384             nested_exit_on_intr(vcpu)) {
10385                 if (vmx->nested.nested_run_pending)
10386                         return -EBUSY;
10387                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10388                 return 0;
10389         }
10390
10391         return vmx_complete_nested_posted_interrupt(vcpu);
10392 }
10393
10394 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10395 {
10396         ktime_t remaining =
10397                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10398         u64 value;
10399
10400         if (ktime_to_ns(remaining) <= 0)
10401                 return 0;
10402
10403         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10404         do_div(value, 1000000);
10405         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10406 }
10407
10408 /*
10409  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10410  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10411  * and this function updates it to reflect the changes to the guest state while
10412  * L2 was running (and perhaps made some exits which were handled directly by L0
10413  * without going back to L1), and to reflect the exit reason.
10414  * Note that we do not have to copy here all VMCS fields, just those that
10415  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10416  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10417  * which already writes to vmcs12 directly.
10418  */
10419 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10420                            u32 exit_reason, u32 exit_intr_info,
10421                            unsigned long exit_qualification)
10422 {
10423         /* update guest state fields: */
10424         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10425         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10426
10427         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10428         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10429         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10430
10431         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10432         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10433         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10434         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10435         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10436         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10437         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10438         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10439         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10440         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10441         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10442         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10443         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10444         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10445         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10446         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10447         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10448         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10449         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10450         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10451         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10452         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10453         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10454         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10455         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10456         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10457         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10458         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10459         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10460         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10461         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10462         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10463         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10464         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10465         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10466         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10467
10468         vmcs12->guest_interruptibility_info =
10469                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10470         vmcs12->guest_pending_dbg_exceptions =
10471                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10472         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10473                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10474         else
10475                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10476
10477         if (nested_cpu_has_preemption_timer(vmcs12)) {
10478                 if (vmcs12->vm_exit_controls &
10479                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10480                         vmcs12->vmx_preemption_timer_value =
10481                                 vmx_get_preemption_timer_value(vcpu);
10482                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10483         }
10484
10485         /*
10486          * In some cases (usually, nested EPT), L2 is allowed to change its
10487          * own CR3 without exiting. If it has changed it, we must keep it.
10488          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10489          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10490          *
10491          * Additionally, restore L2's PDPTR to vmcs12.
10492          */
10493         if (enable_ept) {
10494                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10495                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10496                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10497                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10498                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10499         }
10500
10501         if (nested_cpu_has_ept(vmcs12))
10502                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10503
10504         if (nested_cpu_has_vid(vmcs12))
10505                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10506
10507         vmcs12->vm_entry_controls =
10508                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10509                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10510
10511         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10512                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10513                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10514         }
10515
10516         /* TODO: These cannot have changed unless we have MSR bitmaps and
10517          * the relevant bit asks not to trap the change */
10518         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10519                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10520         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10521                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10522         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10523         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10524         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10525         if (kvm_mpx_supported())
10526                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10527         if (nested_cpu_has_xsaves(vmcs12))
10528                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10529
10530         /* update exit information fields: */
10531
10532         vmcs12->vm_exit_reason = exit_reason;
10533         vmcs12->exit_qualification = exit_qualification;
10534
10535         vmcs12->vm_exit_intr_info = exit_intr_info;
10536         if ((vmcs12->vm_exit_intr_info &
10537              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10538             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10539                 vmcs12->vm_exit_intr_error_code =
10540                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10541         vmcs12->idt_vectoring_info_field = 0;
10542         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10543         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10544
10545         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10546                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10547                  * instead of reading the real value. */
10548                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10549
10550                 /*
10551                  * Transfer the event that L0 or L1 may wanted to inject into
10552                  * L2 to IDT_VECTORING_INFO_FIELD.
10553                  */
10554                 vmcs12_save_pending_event(vcpu, vmcs12);
10555         }
10556
10557         /*
10558          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10559          * preserved above and would only end up incorrectly in L1.
10560          */
10561         vcpu->arch.nmi_injected = false;
10562         kvm_clear_exception_queue(vcpu);
10563         kvm_clear_interrupt_queue(vcpu);
10564 }
10565
10566 /*
10567  * A part of what we need to when the nested L2 guest exits and we want to
10568  * run its L1 parent, is to reset L1's guest state to the host state specified
10569  * in vmcs12.
10570  * This function is to be called not only on normal nested exit, but also on
10571  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10572  * Failures During or After Loading Guest State").
10573  * This function should be called when the active VMCS is L1's (vmcs01).
10574  */
10575 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10576                                    struct vmcs12 *vmcs12)
10577 {
10578         struct kvm_segment seg;
10579
10580         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10581                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10582         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10583                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10584         else
10585                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10586         vmx_set_efer(vcpu, vcpu->arch.efer);
10587
10588         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10589         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10590         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10591         /*
10592          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10593          * actually changed, because it depends on the current state of
10594          * fpu_active (which may have changed).
10595          * Note that vmx_set_cr0 refers to efer set above.
10596          */
10597         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10598         /*
10599          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10600          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10601          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10602          */
10603         update_exception_bitmap(vcpu);
10604         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10605         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10606
10607         /*
10608          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10609          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10610          */
10611         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10612         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10613
10614         nested_ept_uninit_mmu_context(vcpu);
10615
10616         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10617         kvm_mmu_reset_context(vcpu);
10618
10619         if (!enable_ept)
10620                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10621
10622         if (enable_vpid) {
10623                 /*
10624                  * Trivially support vpid by letting L2s share their parent
10625                  * L1's vpid. TODO: move to a more elaborate solution, giving
10626                  * each L2 its own vpid and exposing the vpid feature to L1.
10627                  */
10628                 vmx_flush_tlb(vcpu);
10629         }
10630
10631
10632         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10633         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10634         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10635         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10636         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10637
10638         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10639         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10640                 vmcs_write64(GUEST_BNDCFGS, 0);
10641
10642         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10643                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10644                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10645         }
10646         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10647                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10648                         vmcs12->host_ia32_perf_global_ctrl);
10649
10650         /* Set L1 segment info according to Intel SDM
10651             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10652         seg = (struct kvm_segment) {
10653                 .base = 0,
10654                 .limit = 0xFFFFFFFF,
10655                 .selector = vmcs12->host_cs_selector,
10656                 .type = 11,
10657                 .present = 1,
10658                 .s = 1,
10659                 .g = 1
10660         };
10661         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10662                 seg.l = 1;
10663         else
10664                 seg.db = 1;
10665         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10666         seg = (struct kvm_segment) {
10667                 .base = 0,
10668                 .limit = 0xFFFFFFFF,
10669                 .type = 3,
10670                 .present = 1,
10671                 .s = 1,
10672                 .db = 1,
10673                 .g = 1
10674         };
10675         seg.selector = vmcs12->host_ds_selector;
10676         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10677         seg.selector = vmcs12->host_es_selector;
10678         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10679         seg.selector = vmcs12->host_ss_selector;
10680         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10681         seg.selector = vmcs12->host_fs_selector;
10682         seg.base = vmcs12->host_fs_base;
10683         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10684         seg.selector = vmcs12->host_gs_selector;
10685         seg.base = vmcs12->host_gs_base;
10686         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10687         seg = (struct kvm_segment) {
10688                 .base = vmcs12->host_tr_base,
10689                 .limit = 0x67,
10690                 .selector = vmcs12->host_tr_selector,
10691                 .type = 11,
10692                 .present = 1
10693         };
10694         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10695
10696         kvm_set_dr(vcpu, 7, 0x400);
10697         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10698
10699         if (cpu_has_vmx_msr_bitmap())
10700                 vmx_set_msr_bitmap(vcpu);
10701
10702         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10703                                 vmcs12->vm_exit_msr_load_count))
10704                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10705 }
10706
10707 /*
10708  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10709  * and modify vmcs12 to make it see what it would expect to see there if
10710  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10711  */
10712 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10713                               u32 exit_intr_info,
10714                               unsigned long exit_qualification)
10715 {
10716         struct vcpu_vmx *vmx = to_vmx(vcpu);
10717         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10718         u32 vm_inst_error = 0;
10719
10720         /* trying to cancel vmlaunch/vmresume is a bug */
10721         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10722
10723         leave_guest_mode(vcpu);
10724         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10725                        exit_qualification);
10726
10727         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10728                                  vmcs12->vm_exit_msr_store_count))
10729                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10730
10731         if (unlikely(vmx->fail))
10732                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10733
10734         vmx_load_vmcs01(vcpu);
10735
10736         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10737             && nested_exit_intr_ack_set(vcpu)) {
10738                 int irq = kvm_cpu_get_interrupt(vcpu);
10739                 WARN_ON(irq < 0);
10740                 vmcs12->vm_exit_intr_info = irq |
10741                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10742         }
10743
10744         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10745                                        vmcs12->exit_qualification,
10746                                        vmcs12->idt_vectoring_info_field,
10747                                        vmcs12->vm_exit_intr_info,
10748                                        vmcs12->vm_exit_intr_error_code,
10749                                        KVM_ISA_VMX);
10750
10751         vm_entry_controls_reset_shadow(vmx);
10752         vm_exit_controls_reset_shadow(vmx);
10753         vmx_segment_cache_clear(vmx);
10754
10755         /* if no vmcs02 cache requested, remove the one we used */
10756         if (VMCS02_POOL_SIZE == 0)
10757                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10758
10759         load_vmcs12_host_state(vcpu, vmcs12);
10760
10761         /* Update any VMCS fields that might have changed while L2 ran */
10762         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10763         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10764         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10765         if (vmx->hv_deadline_tsc == -1)
10766                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10767                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10768         else
10769                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10770                               PIN_BASED_VMX_PREEMPTION_TIMER);
10771         if (kvm_has_tsc_control)
10772                 decache_tsc_multiplier(vmx);
10773
10774         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10775                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10776                 vmx_set_virtual_x2apic_mode(vcpu,
10777                                 vcpu->arch.apic_base & X2APIC_ENABLE);
10778         }
10779
10780         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10781         vmx->host_rsp = 0;
10782
10783         /* Unpin physical memory we referred to in vmcs02 */
10784         if (vmx->nested.apic_access_page) {
10785                 nested_release_page(vmx->nested.apic_access_page);
10786                 vmx->nested.apic_access_page = NULL;
10787         }
10788         if (vmx->nested.virtual_apic_page) {
10789                 nested_release_page(vmx->nested.virtual_apic_page);
10790                 vmx->nested.virtual_apic_page = NULL;
10791         }
10792         if (vmx->nested.pi_desc_page) {
10793                 kunmap(vmx->nested.pi_desc_page);
10794                 nested_release_page(vmx->nested.pi_desc_page);
10795                 vmx->nested.pi_desc_page = NULL;
10796                 vmx->nested.pi_desc = NULL;
10797         }
10798
10799         /*
10800          * We are now running in L2, mmu_notifier will force to reload the
10801          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10802          */
10803         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
10804
10805         /*
10806          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10807          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10808          * success or failure flag accordingly.
10809          */
10810         if (unlikely(vmx->fail)) {
10811                 vmx->fail = 0;
10812                 nested_vmx_failValid(vcpu, vm_inst_error);
10813         } else
10814                 nested_vmx_succeed(vcpu);
10815         if (enable_shadow_vmcs)
10816                 vmx->nested.sync_shadow_vmcs = true;
10817
10818         /* in case we halted in L2 */
10819         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10820 }
10821
10822 /*
10823  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10824  */
10825 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10826 {
10827         if (is_guest_mode(vcpu))
10828                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10829         free_nested(to_vmx(vcpu));
10830 }
10831
10832 /*
10833  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10834  * 23.7 "VM-entry failures during or after loading guest state" (this also
10835  * lists the acceptable exit-reason and exit-qualification parameters).
10836  * It should only be called before L2 actually succeeded to run, and when
10837  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10838  */
10839 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10840                         struct vmcs12 *vmcs12,
10841                         u32 reason, unsigned long qualification)
10842 {
10843         load_vmcs12_host_state(vcpu, vmcs12);
10844         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10845         vmcs12->exit_qualification = qualification;
10846         nested_vmx_succeed(vcpu);
10847         if (enable_shadow_vmcs)
10848                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10849 }
10850
10851 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10852                                struct x86_instruction_info *info,
10853                                enum x86_intercept_stage stage)
10854 {
10855         return X86EMUL_CONTINUE;
10856 }
10857
10858 #ifdef CONFIG_X86_64
10859 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10860 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10861                                   u64 divisor, u64 *result)
10862 {
10863         u64 low = a << shift, high = a >> (64 - shift);
10864
10865         /* To avoid the overflow on divq */
10866         if (high >= divisor)
10867                 return 1;
10868
10869         /* Low hold the result, high hold rem which is discarded */
10870         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10871             "rm" (divisor), "0" (low), "1" (high));
10872         *result = low;
10873
10874         return 0;
10875 }
10876
10877 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10878 {
10879         struct vcpu_vmx *vmx = to_vmx(vcpu);
10880         u64 tscl = rdtsc();
10881         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10882         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10883
10884         /* Convert to host delta tsc if tsc scaling is enabled */
10885         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10886                         u64_shl_div_u64(delta_tsc,
10887                                 kvm_tsc_scaling_ratio_frac_bits,
10888                                 vcpu->arch.tsc_scaling_ratio,
10889                                 &delta_tsc))
10890                 return -ERANGE;
10891
10892         /*
10893          * If the delta tsc can't fit in the 32 bit after the multi shift,
10894          * we can't use the preemption timer.
10895          * It's possible that it fits on later vmentries, but checking
10896          * on every vmentry is costly so we just use an hrtimer.
10897          */
10898         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10899                 return -ERANGE;
10900
10901         vmx->hv_deadline_tsc = tscl + delta_tsc;
10902         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10903                         PIN_BASED_VMX_PREEMPTION_TIMER);
10904         return 0;
10905 }
10906
10907 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10908 {
10909         struct vcpu_vmx *vmx = to_vmx(vcpu);
10910         vmx->hv_deadline_tsc = -1;
10911         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10912                         PIN_BASED_VMX_PREEMPTION_TIMER);
10913 }
10914 #endif
10915
10916 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10917 {
10918         if (ple_gap)
10919                 shrink_ple_window(vcpu);
10920 }
10921
10922 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10923                                      struct kvm_memory_slot *slot)
10924 {
10925         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10926         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10927 }
10928
10929 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10930                                        struct kvm_memory_slot *slot)
10931 {
10932         kvm_mmu_slot_set_dirty(kvm, slot);
10933 }
10934
10935 static void vmx_flush_log_dirty(struct kvm *kvm)
10936 {
10937         kvm_flush_pml_buffers(kvm);
10938 }
10939
10940 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10941                                            struct kvm_memory_slot *memslot,
10942                                            gfn_t offset, unsigned long mask)
10943 {
10944         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10945 }
10946
10947 /*
10948  * This routine does the following things for vCPU which is going
10949  * to be blocked if VT-d PI is enabled.
10950  * - Store the vCPU to the wakeup list, so when interrupts happen
10951  *   we can find the right vCPU to wake up.
10952  * - Change the Posted-interrupt descriptor as below:
10953  *      'NDST' <-- vcpu->pre_pcpu
10954  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10955  * - If 'ON' is set during this process, which means at least one
10956  *   interrupt is posted for this vCPU, we cannot block it, in
10957  *   this case, return 1, otherwise, return 0.
10958  *
10959  */
10960 static int pi_pre_block(struct kvm_vcpu *vcpu)
10961 {
10962         unsigned long flags;
10963         unsigned int dest;
10964         struct pi_desc old, new;
10965         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10966
10967         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10968                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
10969                 !kvm_vcpu_apicv_active(vcpu))
10970                 return 0;
10971
10972         vcpu->pre_pcpu = vcpu->cpu;
10973         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10974                           vcpu->pre_pcpu), flags);
10975         list_add_tail(&vcpu->blocked_vcpu_list,
10976                       &per_cpu(blocked_vcpu_on_cpu,
10977                       vcpu->pre_pcpu));
10978         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10979                                vcpu->pre_pcpu), flags);
10980
10981         do {
10982                 old.control = new.control = pi_desc->control;
10983
10984                 /*
10985                  * We should not block the vCPU if
10986                  * an interrupt is posted for it.
10987                  */
10988                 if (pi_test_on(pi_desc) == 1) {
10989                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10990                                           vcpu->pre_pcpu), flags);
10991                         list_del(&vcpu->blocked_vcpu_list);
10992                         spin_unlock_irqrestore(
10993                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10994                                         vcpu->pre_pcpu), flags);
10995                         vcpu->pre_pcpu = -1;
10996
10997                         return 1;
10998                 }
10999
11000                 WARN((pi_desc->sn == 1),
11001                      "Warning: SN field of posted-interrupts "
11002                      "is set before blocking\n");
11003
11004                 /*
11005                  * Since vCPU can be preempted during this process,
11006                  * vcpu->cpu could be different with pre_pcpu, we
11007                  * need to set pre_pcpu as the destination of wakeup
11008                  * notification event, then we can find the right vCPU
11009                  * to wakeup in wakeup handler if interrupts happen
11010                  * when the vCPU is in blocked state.
11011                  */
11012                 dest = cpu_physical_id(vcpu->pre_pcpu);
11013
11014                 if (x2apic_enabled())
11015                         new.ndst = dest;
11016                 else
11017                         new.ndst = (dest << 8) & 0xFF00;
11018
11019                 /* set 'NV' to 'wakeup vector' */
11020                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11021         } while (cmpxchg(&pi_desc->control, old.control,
11022                         new.control) != old.control);
11023
11024         return 0;
11025 }
11026
11027 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11028 {
11029         if (pi_pre_block(vcpu))
11030                 return 1;
11031
11032         if (kvm_lapic_hv_timer_in_use(vcpu))
11033                 kvm_lapic_switch_to_sw_timer(vcpu);
11034
11035         return 0;
11036 }
11037
11038 static void pi_post_block(struct kvm_vcpu *vcpu)
11039 {
11040         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11041         struct pi_desc old, new;
11042         unsigned int dest;
11043         unsigned long flags;
11044
11045         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11046                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11047                 !kvm_vcpu_apicv_active(vcpu))
11048                 return;
11049
11050         do {
11051                 old.control = new.control = pi_desc->control;
11052
11053                 dest = cpu_physical_id(vcpu->cpu);
11054
11055                 if (x2apic_enabled())
11056                         new.ndst = dest;
11057                 else
11058                         new.ndst = (dest << 8) & 0xFF00;
11059
11060                 /* Allow posting non-urgent interrupts */
11061                 new.sn = 0;
11062
11063                 /* set 'NV' to 'notification vector' */
11064                 new.nv = POSTED_INTR_VECTOR;
11065         } while (cmpxchg(&pi_desc->control, old.control,
11066                         new.control) != old.control);
11067
11068         if(vcpu->pre_pcpu != -1) {
11069                 spin_lock_irqsave(
11070                         &per_cpu(blocked_vcpu_on_cpu_lock,
11071                         vcpu->pre_pcpu), flags);
11072                 list_del(&vcpu->blocked_vcpu_list);
11073                 spin_unlock_irqrestore(
11074                         &per_cpu(blocked_vcpu_on_cpu_lock,
11075                         vcpu->pre_pcpu), flags);
11076                 vcpu->pre_pcpu = -1;
11077         }
11078 }
11079
11080 static void vmx_post_block(struct kvm_vcpu *vcpu)
11081 {
11082         if (kvm_x86_ops->set_hv_timer)
11083                 kvm_lapic_switch_to_hv_timer(vcpu);
11084
11085         pi_post_block(vcpu);
11086 }
11087
11088 /*
11089  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11090  *
11091  * @kvm: kvm
11092  * @host_irq: host irq of the interrupt
11093  * @guest_irq: gsi of the interrupt
11094  * @set: set or unset PI
11095  * returns 0 on success, < 0 on failure
11096  */
11097 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11098                               uint32_t guest_irq, bool set)
11099 {
11100         struct kvm_kernel_irq_routing_entry *e;
11101         struct kvm_irq_routing_table *irq_rt;
11102         struct kvm_lapic_irq irq;
11103         struct kvm_vcpu *vcpu;
11104         struct vcpu_data vcpu_info;
11105         int idx, ret = -EINVAL;
11106
11107         if (!kvm_arch_has_assigned_device(kvm) ||
11108                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11109                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11110                 return 0;
11111
11112         idx = srcu_read_lock(&kvm->irq_srcu);
11113         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11114         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11115
11116         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11117                 if (e->type != KVM_IRQ_ROUTING_MSI)
11118                         continue;
11119                 /*
11120                  * VT-d PI cannot support posting multicast/broadcast
11121                  * interrupts to a vCPU, we still use interrupt remapping
11122                  * for these kind of interrupts.
11123                  *
11124                  * For lowest-priority interrupts, we only support
11125                  * those with single CPU as the destination, e.g. user
11126                  * configures the interrupts via /proc/irq or uses
11127                  * irqbalance to make the interrupts single-CPU.
11128                  *
11129                  * We will support full lowest-priority interrupt later.
11130                  */
11131
11132                 kvm_set_msi_irq(kvm, e, &irq);
11133                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11134                         /*
11135                          * Make sure the IRTE is in remapped mode if
11136                          * we don't handle it in posted mode.
11137                          */
11138                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11139                         if (ret < 0) {
11140                                 printk(KERN_INFO
11141                                    "failed to back to remapped mode, irq: %u\n",
11142                                    host_irq);
11143                                 goto out;
11144                         }
11145
11146                         continue;
11147                 }
11148
11149                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11150                 vcpu_info.vector = irq.vector;
11151
11152                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11153                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11154
11155                 if (set)
11156                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11157                 else {
11158                         /* suppress notification event before unposting */
11159                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11160                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11161                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11162                 }
11163
11164                 if (ret < 0) {
11165                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11166                                         __func__);
11167                         goto out;
11168                 }
11169         }
11170
11171         ret = 0;
11172 out:
11173         srcu_read_unlock(&kvm->irq_srcu, idx);
11174         return ret;
11175 }
11176
11177 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11178 {
11179         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11180                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11181                         FEATURE_CONTROL_LMCE;
11182         else
11183                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11184                         ~FEATURE_CONTROL_LMCE;
11185 }
11186
11187 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11188         .cpu_has_kvm_support = cpu_has_kvm_support,
11189         .disabled_by_bios = vmx_disabled_by_bios,
11190         .hardware_setup = hardware_setup,
11191         .hardware_unsetup = hardware_unsetup,
11192         .check_processor_compatibility = vmx_check_processor_compat,
11193         .hardware_enable = hardware_enable,
11194         .hardware_disable = hardware_disable,
11195         .cpu_has_accelerated_tpr = report_flexpriority,
11196         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11197
11198         .vcpu_create = vmx_create_vcpu,
11199         .vcpu_free = vmx_free_vcpu,
11200         .vcpu_reset = vmx_vcpu_reset,
11201
11202         .prepare_guest_switch = vmx_save_host_state,
11203         .vcpu_load = vmx_vcpu_load,
11204         .vcpu_put = vmx_vcpu_put,
11205
11206         .update_bp_intercept = update_exception_bitmap,
11207         .get_msr = vmx_get_msr,
11208         .set_msr = vmx_set_msr,
11209         .get_segment_base = vmx_get_segment_base,
11210         .get_segment = vmx_get_segment,
11211         .set_segment = vmx_set_segment,
11212         .get_cpl = vmx_get_cpl,
11213         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11214         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11215         .decache_cr3 = vmx_decache_cr3,
11216         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11217         .set_cr0 = vmx_set_cr0,
11218         .set_cr3 = vmx_set_cr3,
11219         .set_cr4 = vmx_set_cr4,
11220         .set_efer = vmx_set_efer,
11221         .get_idt = vmx_get_idt,
11222         .set_idt = vmx_set_idt,
11223         .get_gdt = vmx_get_gdt,
11224         .set_gdt = vmx_set_gdt,
11225         .get_dr6 = vmx_get_dr6,
11226         .set_dr6 = vmx_set_dr6,
11227         .set_dr7 = vmx_set_dr7,
11228         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11229         .cache_reg = vmx_cache_reg,
11230         .get_rflags = vmx_get_rflags,
11231         .set_rflags = vmx_set_rflags,
11232
11233         .get_pkru = vmx_get_pkru,
11234
11235         .fpu_activate = vmx_fpu_activate,
11236         .fpu_deactivate = vmx_fpu_deactivate,
11237
11238         .tlb_flush = vmx_flush_tlb,
11239
11240         .run = vmx_vcpu_run,
11241         .handle_exit = vmx_handle_exit,
11242         .skip_emulated_instruction = skip_emulated_instruction,
11243         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11244         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11245         .patch_hypercall = vmx_patch_hypercall,
11246         .set_irq = vmx_inject_irq,
11247         .set_nmi = vmx_inject_nmi,
11248         .queue_exception = vmx_queue_exception,
11249         .cancel_injection = vmx_cancel_injection,
11250         .interrupt_allowed = vmx_interrupt_allowed,
11251         .nmi_allowed = vmx_nmi_allowed,
11252         .get_nmi_mask = vmx_get_nmi_mask,
11253         .set_nmi_mask = vmx_set_nmi_mask,
11254         .enable_nmi_window = enable_nmi_window,
11255         .enable_irq_window = enable_irq_window,
11256         .update_cr8_intercept = update_cr8_intercept,
11257         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11258         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11259         .get_enable_apicv = vmx_get_enable_apicv,
11260         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11261         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11262         .hwapic_irr_update = vmx_hwapic_irr_update,
11263         .hwapic_isr_update = vmx_hwapic_isr_update,
11264         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11265         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11266
11267         .set_tss_addr = vmx_set_tss_addr,
11268         .get_tdp_level = get_ept_level,
11269         .get_mt_mask = vmx_get_mt_mask,
11270
11271         .get_exit_info = vmx_get_exit_info,
11272
11273         .get_lpage_level = vmx_get_lpage_level,
11274
11275         .cpuid_update = vmx_cpuid_update,
11276
11277         .rdtscp_supported = vmx_rdtscp_supported,
11278         .invpcid_supported = vmx_invpcid_supported,
11279
11280         .set_supported_cpuid = vmx_set_supported_cpuid,
11281
11282         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11283
11284         .write_tsc_offset = vmx_write_tsc_offset,
11285
11286         .set_tdp_cr3 = vmx_set_cr3,
11287
11288         .check_intercept = vmx_check_intercept,
11289         .handle_external_intr = vmx_handle_external_intr,
11290         .mpx_supported = vmx_mpx_supported,
11291         .xsaves_supported = vmx_xsaves_supported,
11292
11293         .check_nested_events = vmx_check_nested_events,
11294
11295         .sched_in = vmx_sched_in,
11296
11297         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11298         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11299         .flush_log_dirty = vmx_flush_log_dirty,
11300         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11301
11302         .pre_block = vmx_pre_block,
11303         .post_block = vmx_post_block,
11304
11305         .pmu_ops = &intel_pmu_ops,
11306
11307         .update_pi_irte = vmx_update_pi_irte,
11308
11309 #ifdef CONFIG_X86_64
11310         .set_hv_timer = vmx_set_hv_timer,
11311         .cancel_hv_timer = vmx_cancel_hv_timer,
11312 #endif
11313
11314         .setup_mce = vmx_setup_mce,
11315 };
11316
11317 static int __init vmx_init(void)
11318 {
11319         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11320                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11321         if (r)
11322                 return r;
11323
11324 #ifdef CONFIG_KEXEC_CORE
11325         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11326                            crash_vmclear_local_loaded_vmcss);
11327 #endif
11328
11329         return 0;
11330 }
11331
11332 static void __exit vmx_exit(void)
11333 {
11334 #ifdef CONFIG_KEXEC_CORE
11335         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11336         synchronize_rcu();
11337 #endif
11338
11339         kvm_exit();
11340 }
11341
11342 module_init(vmx_init)
11343 module_exit(vmx_exit)