arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly emulate_invalid_guest_state = 0;
  75 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  76
  77 static bool __read_mostly vmm_exclusive = 1;
  78 module_param(vmm_exclusive, bool, S_IRUGO);
  79
  80 static bool __read_mostly fasteoi = 1;
  81 module_param(fasteoi, bool, S_IRUGO);
  82
  83 /*
  84  * If nested=1, nested virtualization is supported, i.e., guests may use
  85  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  86  * use VMX instructions.
  87  */
  88 static bool __read_mostly nested = 0;
  89 module_param(nested, bool, S_IRUGO);
  90
  91 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  92         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  93 #define KVM_GUEST_CR0_MASK                                              \
  94         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  95 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  96         (X86_CR0_WP | X86_CR0_NE)
  97 #define KVM_VM_CR0_ALWAYS_ON                                            \
  98         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  99 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 100         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 101          | X86_CR4_OSXMMEXCPT)
 102
 103 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 104 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 105
 106 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 107
 108 /*
 109  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 110  * ple_gap:    upper bound on the amount of time between two successive
 111  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 112  *             According to test, this time is usually smaller than 128 cycles.
 113  * ple_window: upper bound on the amount of time a guest is allowed to execute
 114  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 115  *             less than 2^12 cycles
 116  * Time is measured based on a counter that runs at the same rate as the TSC,
 117  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 118  */
 119 #define KVM_VMX_DEFAULT_PLE_GAP    128
 120 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 121 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 122 module_param(ple_gap, int, S_IRUGO);
 123
 124 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 125 module_param(ple_window, int, S_IRUGO);
 126
 127 #define NR_AUTOLOAD_MSRS 8
 128 #define VMCS02_POOL_SIZE 1
 129
 130 struct vmcs {
 131         u32 revision_id;
 132         u32 abort;
 133         char data[0];
 134 };
 135
 136 /*
 137  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 138  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 139  * loaded on this CPU (so we can clear them if the CPU goes down).
 140  */
 141 struct loaded_vmcs {
 142         struct vmcs *vmcs;
 143         int cpu;
 144         int launched;
 145         struct list_head loaded_vmcss_on_cpu_link;
 146 };
 147
 148 struct shared_msr_entry {
 149         unsigned index;
 150         u64 data;
 151         u64 mask;
 152 };
 153
 154 /*
 155  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 156  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 157  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 158  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 159  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 160  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 161  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 162  * underlying hardware which will be used to run L2.
 163  * This structure is packed to ensure that its layout is identical across
 164  * machines (necessary for live migration).
 165  * If there are changes in this struct, VMCS12_REVISION must be changed.
 166  */
 167 typedef u64 natural_width;
 168 struct __packed vmcs12 {
 169         /* According to the Intel spec, a VMCS region must start with the
 170          * following two fields. Then follow implementation-specific data.
 171          */
 172         u32 revision_id;
 173         u32 abort;
 174
 175         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 176         u32 padding[7]; /* room for future expansion */
 177
 178         u64 io_bitmap_a;
 179         u64 io_bitmap_b;
 180         u64 msr_bitmap;
 181         u64 vm_exit_msr_store_addr;
 182         u64 vm_exit_msr_load_addr;
 183         u64 vm_entry_msr_load_addr;
 184         u64 tsc_offset;
 185         u64 virtual_apic_page_addr;
 186         u64 apic_access_addr;
 187         u64 ept_pointer;
 188         u64 guest_physical_address;
 189         u64 vmcs_link_pointer;
 190         u64 guest_ia32_debugctl;
 191         u64 guest_ia32_pat;
 192         u64 guest_ia32_efer;
 193         u64 guest_ia32_perf_global_ctrl;
 194         u64 guest_pdptr0;
 195         u64 guest_pdptr1;
 196         u64 guest_pdptr2;
 197         u64 guest_pdptr3;
 198         u64 host_ia32_pat;
 199         u64 host_ia32_efer;
 200         u64 host_ia32_perf_global_ctrl;
 201         u64 padding64[8]; /* room for future expansion */
 202         /*
 203          * To allow migration of L1 (complete with its L2 guests) between
 204          * machines of different natural widths (32 or 64 bit), we cannot have
 205          * unsigned long fields with no explict size. We use u64 (aliased
 206          * natural_width) instead. Luckily, x86 is little-endian.
 207          */
 208         natural_width cr0_guest_host_mask;
 209         natural_width cr4_guest_host_mask;
 210         natural_width cr0_read_shadow;
 211         natural_width cr4_read_shadow;
 212         natural_width cr3_target_value0;
 213         natural_width cr3_target_value1;
 214         natural_width cr3_target_value2;
 215         natural_width cr3_target_value3;
 216         natural_width exit_qualification;
 217         natural_width guest_linear_address;
 218         natural_width guest_cr0;
 219         natural_width guest_cr3;
 220         natural_width guest_cr4;
 221         natural_width guest_es_base;
 222         natural_width guest_cs_base;
 223         natural_width guest_ss_base;
 224         natural_width guest_ds_base;
 225         natural_width guest_fs_base;
 226         natural_width guest_gs_base;
 227         natural_width guest_ldtr_base;
 228         natural_width guest_tr_base;
 229         natural_width guest_gdtr_base;
 230         natural_width guest_idtr_base;
 231         natural_width guest_dr7;
 232         natural_width guest_rsp;
 233         natural_width guest_rip;
 234         natural_width guest_rflags;
 235         natural_width guest_pending_dbg_exceptions;
 236         natural_width guest_sysenter_esp;
 237         natural_width guest_sysenter_eip;
 238         natural_width host_cr0;
 239         natural_width host_cr3;
 240         natural_width host_cr4;
 241         natural_width host_fs_base;
 242         natural_width host_gs_base;
 243         natural_width host_tr_base;
 244         natural_width host_gdtr_base;
 245         natural_width host_idtr_base;
 246         natural_width host_ia32_sysenter_esp;
 247         natural_width host_ia32_sysenter_eip;
 248         natural_width host_rsp;
 249         natural_width host_rip;
 250         natural_width paddingl[8]; /* room for future expansion */
 251         u32 pin_based_vm_exec_control;
 252         u32 cpu_based_vm_exec_control;
 253         u32 exception_bitmap;
 254         u32 page_fault_error_code_mask;
 255         u32 page_fault_error_code_match;
 256         u32 cr3_target_count;
 257         u32 vm_exit_controls;
 258         u32 vm_exit_msr_store_count;
 259         u32 vm_exit_msr_load_count;
 260         u32 vm_entry_controls;
 261         u32 vm_entry_msr_load_count;
 262         u32 vm_entry_intr_info_field;
 263         u32 vm_entry_exception_error_code;
 264         u32 vm_entry_instruction_len;
 265         u32 tpr_threshold;
 266         u32 secondary_vm_exec_control;
 267         u32 vm_instruction_error;
 268         u32 vm_exit_reason;
 269         u32 vm_exit_intr_info;
 270         u32 vm_exit_intr_error_code;
 271         u32 idt_vectoring_info_field;
 272         u32 idt_vectoring_error_code;
 273         u32 vm_exit_instruction_len;
 274         u32 vmx_instruction_info;
 275         u32 guest_es_limit;
 276         u32 guest_cs_limit;
 277         u32 guest_ss_limit;
 278         u32 guest_ds_limit;
 279         u32 guest_fs_limit;
 280         u32 guest_gs_limit;
 281         u32 guest_ldtr_limit;
 282         u32 guest_tr_limit;
 283         u32 guest_gdtr_limit;
 284         u32 guest_idtr_limit;
 285         u32 guest_es_ar_bytes;
 286         u32 guest_cs_ar_bytes;
 287         u32 guest_ss_ar_bytes;
 288         u32 guest_ds_ar_bytes;
 289         u32 guest_fs_ar_bytes;
 290         u32 guest_gs_ar_bytes;
 291         u32 guest_ldtr_ar_bytes;
 292         u32 guest_tr_ar_bytes;
 293         u32 guest_interruptibility_info;
 294         u32 guest_activity_state;
 295         u32 guest_sysenter_cs;
 296         u32 host_ia32_sysenter_cs;
 297         u32 padding32[8]; /* room for future expansion */
 298         u16 virtual_processor_id;
 299         u16 guest_es_selector;
 300         u16 guest_cs_selector;
 301         u16 guest_ss_selector;
 302         u16 guest_ds_selector;
 303         u16 guest_fs_selector;
 304         u16 guest_gs_selector;
 305         u16 guest_ldtr_selector;
 306         u16 guest_tr_selector;
 307         u16 host_es_selector;
 308         u16 host_cs_selector;
 309         u16 host_ss_selector;
 310         u16 host_ds_selector;
 311         u16 host_fs_selector;
 312         u16 host_gs_selector;
 313         u16 host_tr_selector;
 314 };
 315
 316 /*
 317  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 318  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 319  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 320  */
 321 #define VMCS12_REVISION 0x11e57ed0
 322
 323 /*
 324  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 325  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 326  * current implementation, 4K are reserved to avoid future complications.
 327  */
 328 #define VMCS12_SIZE 0x1000
 329
 330 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 331 struct vmcs02_list {
 332         struct list_head list;
 333         gpa_t vmptr;
 334         struct loaded_vmcs vmcs02;
 335 };
 336
 337 /*
 338  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 339  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 340  */
 341 struct nested_vmx {
 342         /* Has the level1 guest done vmxon? */
 343         bool vmxon;
 344
 345         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 346         gpa_t current_vmptr;
 347         /* The host-usable pointer to the above */
 348         struct page *current_vmcs12_page;
 349         struct vmcs12 *current_vmcs12;
 350
 351         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 352         struct list_head vmcs02_pool;
 353         int vmcs02_num;
 354         u64 vmcs01_tsc_offset;
 355         /* L2 must run next, and mustn't decide to exit to L1. */
 356         bool nested_run_pending;
 357         /*
 358          * Guest pages referred to in vmcs02 with host-physical pointers, so
 359          * we must keep them pinned while L2 runs.
 360          */
 361         struct page *apic_access_page;
 362 };
 363
 364 struct vcpu_vmx {
 365         struct kvm_vcpu       vcpu;
 366         unsigned long         host_rsp;
 367         u8                    fail;
 368         u8                    cpl;
 369         bool                  nmi_known_unmasked;
 370         u32                   exit_intr_info;
 371         u32                   idt_vectoring_info;
 372         ulong                 rflags;
 373         struct shared_msr_entry *guest_msrs;
 374         int                   nmsrs;
 375         int                   save_nmsrs;
 376 #ifdef CONFIG_X86_64
 377         u64                   msr_host_kernel_gs_base;
 378         u64                   msr_guest_kernel_gs_base;
 379 #endif
 380         /*
 381          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 382          * non-nested (L1) guest, it always points to vmcs01. For a nested
 383          * guest (L2), it points to a different VMCS.
 384          */
 385         struct loaded_vmcs    vmcs01;
 386         struct loaded_vmcs   *loaded_vmcs;
 387         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 388         struct msr_autoload {
 389                 unsigned nr;
 390                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 391                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 392         } msr_autoload;
 393         struct {
 394                 int           loaded;
 395                 u16           fs_sel, gs_sel, ldt_sel;
 396 #ifdef CONFIG_X86_64
 397                 u16           ds_sel, es_sel;
 398 #endif
 399                 int           gs_ldt_reload_needed;
 400                 int           fs_reload_needed;
 401         } host_state;
 402         struct {
 403                 int vm86_active;
 404                 ulong save_rflags;
 405                 struct kvm_save_segment {
 406                         u16 selector;
 407                         unsigned long base;
 408                         u32 limit;
 409                         u32 ar;
 410                 } tr, es, ds, fs, gs;
 411         } rmode;
 412         struct {
 413                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 414                 struct kvm_save_segment seg[8];
 415         } segment_cache;
 416         int vpid;
 417         bool emulation_required;
 418
 419         /* Support for vnmi-less CPUs */
 420         int soft_vnmi_blocked;
 421         ktime_t entry_time;
 422         s64 vnmi_blocked_time;
 423         u32 exit_reason;
 424
 425         bool rdtscp_enabled;
 426
 427         /* Support for a guest hypervisor (nested VMX) */
 428         struct nested_vmx nested;
 429 };
 430
 431 enum segment_cache_field {
 432         SEG_FIELD_SEL = 0,
 433         SEG_FIELD_BASE = 1,
 434         SEG_FIELD_LIMIT = 2,
 435         SEG_FIELD_AR = 3,
 436
 437         SEG_FIELD_NR = 4
 438 };
 439
 440 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 441 {
 442         return container_of(vcpu, struct vcpu_vmx, vcpu);
 443 }
 444
 445 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 446 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 447 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 448                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 449
 450 static unsigned short vmcs_field_to_offset_table[] = {
 451         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 452         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 453         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 454         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 455         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 456         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 457         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 458         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 459         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 460         FIELD(HOST_ES_SELECTOR, host_es_selector),
 461         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 462         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 463         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 464         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 465         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 466         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 467         FIELD64(IO_BITMAP_A, io_bitmap_a),
 468         FIELD64(IO_BITMAP_B, io_bitmap_b),
 469         FIELD64(MSR_BITMAP, msr_bitmap),
 470         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 471         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 472         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 473         FIELD64(TSC_OFFSET, tsc_offset),
 474         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 475         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 476         FIELD64(EPT_POINTER, ept_pointer),
 477         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 478         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 479         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 480         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 481         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 482         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 483         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 484         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 485         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 486         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 487         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 488         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 489         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 490         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 491         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 492         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 493         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 494         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 495         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 496         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 497         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 498         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 499         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 500         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 501         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 502         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 503         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 504         FIELD(TPR_THRESHOLD, tpr_threshold),
 505         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 506         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 507         FIELD(VM_EXIT_REASON, vm_exit_reason),
 508         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 509         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 510         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 511         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 512         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 513         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 514         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 515         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 516         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 517         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 518         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 519         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 520         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 521         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 522         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 523         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 524         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 525         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 526         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 527         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 528         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 529         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 530         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 531         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 532         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 533         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 534         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 535         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 536         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 537         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 538         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 539         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 540         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 541         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 542         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 543         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 544         FIELD(EXIT_QUALIFICATION, exit_qualification),
 545         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 546         FIELD(GUEST_CR0, guest_cr0),
 547         FIELD(GUEST_CR3, guest_cr3),
 548         FIELD(GUEST_CR4, guest_cr4),
 549         FIELD(GUEST_ES_BASE, guest_es_base),
 550         FIELD(GUEST_CS_BASE, guest_cs_base),
 551         FIELD(GUEST_SS_BASE, guest_ss_base),
 552         FIELD(GUEST_DS_BASE, guest_ds_base),
 553         FIELD(GUEST_FS_BASE, guest_fs_base),
 554         FIELD(GUEST_GS_BASE, guest_gs_base),
 555         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 556         FIELD(GUEST_TR_BASE, guest_tr_base),
 557         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 558         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 559         FIELD(GUEST_DR7, guest_dr7),
 560         FIELD(GUEST_RSP, guest_rsp),
 561         FIELD(GUEST_RIP, guest_rip),
 562         FIELD(GUEST_RFLAGS, guest_rflags),
 563         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 564         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 565         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 566         FIELD(HOST_CR0, host_cr0),
 567         FIELD(HOST_CR3, host_cr3),
 568         FIELD(HOST_CR4, host_cr4),
 569         FIELD(HOST_FS_BASE, host_fs_base),
 570         FIELD(HOST_GS_BASE, host_gs_base),
 571         FIELD(HOST_TR_BASE, host_tr_base),
 572         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 573         FIELD(HOST_IDTR_BASE, host_idtr_base),
 574         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 575         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 576         FIELD(HOST_RSP, host_rsp),
 577         FIELD(HOST_RIP, host_rip),
 578 };
 579 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 580
 581 static inline short vmcs_field_to_offset(unsigned long field)
 582 {
 583         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 584                 return -1;
 585         return vmcs_field_to_offset_table[field];
 586 }
 587
 588 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 589 {
 590         return to_vmx(vcpu)->nested.current_vmcs12;
 591 }
 592
 593 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 594 {
 595         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 596         if (is_error_page(page)) {
 597                 kvm_release_page_clean(page);
 598                 return NULL;
 599         }
 600         return page;
 601 }
 602
 603 static void nested_release_page(struct page *page)
 604 {
 605         kvm_release_page_dirty(page);
 606 }
 607
 608 static void nested_release_page_clean(struct page *page)
 609 {
 610         kvm_release_page_clean(page);
 611 }
 612
 613 static u64 construct_eptp(unsigned long root_hpa);
 614 static void kvm_cpu_vmxon(u64 addr);
 615 static void kvm_cpu_vmxoff(void);
 616 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 617 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 618 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 619                             struct kvm_segment *var, int seg);
 620 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 621                             struct kvm_segment *var, int seg);
 622
 623 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 624 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 625 /*
 626  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 627  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 628  */
 629 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 630 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 631
 632 static unsigned long *vmx_io_bitmap_a;
 633 static unsigned long *vmx_io_bitmap_b;
 634 static unsigned long *vmx_msr_bitmap_legacy;
 635 static unsigned long *vmx_msr_bitmap_longmode;
 636
 637 static bool cpu_has_load_ia32_efer;
 638 static bool cpu_has_load_perf_global_ctrl;
 639
 640 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 641 static DEFINE_SPINLOCK(vmx_vpid_lock);
 642
 643 static struct vmcs_config {
 644         int size;
 645         int order;
 646         u32 revision_id;
 647         u32 pin_based_exec_ctrl;
 648         u32 cpu_based_exec_ctrl;
 649         u32 cpu_based_2nd_exec_ctrl;
 650         u32 vmexit_ctrl;
 651         u32 vmentry_ctrl;
 652 } vmcs_config;
 653
 654 static struct vmx_capability {
 655         u32 ept;
 656         u32 vpid;
 657 } vmx_capability;
 658
 659 #define VMX_SEGMENT_FIELD(seg)                                  \
 660         [VCPU_SREG_##seg] = {                                   \
 661                 .selector = GUEST_##seg##_SELECTOR,             \
 662                 .base = GUEST_##seg##_BASE,                     \
 663                 .limit = GUEST_##seg##_LIMIT,                   \
 664                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 665         }
 666
 667 static struct kvm_vmx_segment_field {
 668         unsigned selector;
 669         unsigned base;
 670         unsigned limit;
 671         unsigned ar_bytes;
 672 } kvm_vmx_segment_fields[] = {
 673         VMX_SEGMENT_FIELD(CS),
 674         VMX_SEGMENT_FIELD(DS),
 675         VMX_SEGMENT_FIELD(ES),
 676         VMX_SEGMENT_FIELD(FS),
 677         VMX_SEGMENT_FIELD(GS),
 678         VMX_SEGMENT_FIELD(SS),
 679         VMX_SEGMENT_FIELD(TR),
 680         VMX_SEGMENT_FIELD(LDTR),
 681 };
 682
 683 static u64 host_efer;
 684
 685 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 686
 687 /*
 688  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 689  * away by decrementing the array size.
 690  */
 691 static const u32 vmx_msr_index[] = {
 692 #ifdef CONFIG_X86_64
 693         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 694 #endif
 695         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 696 };
 697 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 698
 699 static inline bool is_page_fault(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_no_device(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 709                              INTR_INFO_VALID_MASK)) ==
 710                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 711 }
 712
 713 static inline bool is_invalid_opcode(u32 intr_info)
 714 {
 715         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 716                              INTR_INFO_VALID_MASK)) ==
 717                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 718 }
 719
 720 static inline bool is_external_interrupt(u32 intr_info)
 721 {
 722         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 723                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 724 }
 725
 726 static inline bool is_machine_check(u32 intr_info)
 727 {
 728         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 729                              INTR_INFO_VALID_MASK)) ==
 730                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 731 }
 732
 733 static inline bool cpu_has_vmx_msr_bitmap(void)
 734 {
 735         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 736 }
 737
 738 static inline bool cpu_has_vmx_tpr_shadow(void)
 739 {
 740         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 741 }
 742
 743 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 744 {
 745         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 746 }
 747
 748 static inline bool cpu_has_secondary_exec_ctrls(void)
 749 {
 750         return vmcs_config.cpu_based_exec_ctrl &
 751                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 752 }
 753
 754 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 755 {
 756         return vmcs_config.cpu_based_2nd_exec_ctrl &
 757                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 758 }
 759
 760 static inline bool cpu_has_vmx_flexpriority(void)
 761 {
 762         return cpu_has_vmx_tpr_shadow() &&
 763                 cpu_has_vmx_virtualize_apic_accesses();
 764 }
 765
 766 static inline bool cpu_has_vmx_ept_execute_only(void)
 767 {
 768         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 769 }
 770
 771 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 772 {
 773         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 774 }
 775
 776 static inline bool cpu_has_vmx_eptp_writeback(void)
 777 {
 778         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 779 }
 780
 781 static inline bool cpu_has_vmx_ept_2m_page(void)
 782 {
 783         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 784 }
 785
 786 static inline bool cpu_has_vmx_ept_1g_page(void)
 787 {
 788         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 789 }
 790
 791 static inline bool cpu_has_vmx_ept_4levels(void)
 792 {
 793         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 794 }
 795
 796 static inline bool cpu_has_vmx_invept_individual_addr(void)
 797 {
 798         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 799 }
 800
 801 static inline bool cpu_has_vmx_invept_context(void)
 802 {
 803         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 804 }
 805
 806 static inline bool cpu_has_vmx_invept_global(void)
 807 {
 808         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 809 }
 810
 811 static inline bool cpu_has_vmx_invvpid_single(void)
 812 {
 813         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 814 }
 815
 816 static inline bool cpu_has_vmx_invvpid_global(void)
 817 {
 818         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 819 }
 820
 821 static inline bool cpu_has_vmx_ept(void)
 822 {
 823         return vmcs_config.cpu_based_2nd_exec_ctrl &
 824                 SECONDARY_EXEC_ENABLE_EPT;
 825 }
 826
 827 static inline bool cpu_has_vmx_unrestricted_guest(void)
 828 {
 829         return vmcs_config.cpu_based_2nd_exec_ctrl &
 830                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 831 }
 832
 833 static inline bool cpu_has_vmx_ple(void)
 834 {
 835         return vmcs_config.cpu_based_2nd_exec_ctrl &
 836                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 837 }
 838
 839 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 840 {
 841         return flexpriority_enabled && irqchip_in_kernel(kvm);
 842 }
 843
 844 static inline bool cpu_has_vmx_vpid(void)
 845 {
 846         return vmcs_config.cpu_based_2nd_exec_ctrl &
 847                 SECONDARY_EXEC_ENABLE_VPID;
 848 }
 849
 850 static inline bool cpu_has_vmx_rdtscp(void)
 851 {
 852         return vmcs_config.cpu_based_2nd_exec_ctrl &
 853                 SECONDARY_EXEC_RDTSCP;
 854 }
 855
 856 static inline bool cpu_has_virtual_nmis(void)
 857 {
 858         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 859 }
 860
 861 static inline bool cpu_has_vmx_wbinvd_exit(void)
 862 {
 863         return vmcs_config.cpu_based_2nd_exec_ctrl &
 864                 SECONDARY_EXEC_WBINVD_EXITING;
 865 }
 866
 867 static inline bool report_flexpriority(void)
 868 {
 869         return flexpriority_enabled;
 870 }
 871
 872 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 873 {
 874         return vmcs12->cpu_based_vm_exec_control & bit;
 875 }
 876
 877 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 878 {
 879         return (vmcs12->cpu_based_vm_exec_control &
 880                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 881                 (vmcs12->secondary_vm_exec_control & bit);
 882 }
 883
 884 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 885         struct kvm_vcpu *vcpu)
 886 {
 887         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 888 }
 889
 890 static inline bool is_exception(u32 intr_info)
 891 {
 892         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 893                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 894 }
 895
 896 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 897 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 898                         struct vmcs12 *vmcs12,
 899                         u32 reason, unsigned long qualification);
 900
 901 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 902 {
 903         int i;
 904
 905         for (i = 0; i < vmx->nmsrs; ++i)
 906                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 907                         return i;
 908         return -1;
 909 }
 910
 911 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 912 {
 913     struct {
 914         u64 vpid : 16;
 915         u64 rsvd : 48;
 916         u64 gva;
 917     } operand = { vpid, 0, gva };
 918
 919     asm volatile (__ex(ASM_VMX_INVVPID)
 920                   /* CF==1 or ZF==1 --> rc = -1 */
 921                   "; ja 1f ; ud2 ; 1:"
 922                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 923 }
 924
 925 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 926 {
 927         struct {
 928                 u64 eptp, gpa;
 929         } operand = {eptp, gpa};
 930
 931         asm volatile (__ex(ASM_VMX_INVEPT)
 932                         /* CF==1 or ZF==1 --> rc = -1 */
 933                         "; ja 1f ; ud2 ; 1:\n"
 934                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 935 }
 936
 937 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 938 {
 939         int i;
 940
 941         i = __find_msr_index(vmx, msr);
 942         if (i >= 0)
 943                 return &vmx->guest_msrs[i];
 944         return NULL;
 945 }
 946
 947 static void vmcs_clear(struct vmcs *vmcs)
 948 {
 949         u64 phys_addr = __pa(vmcs);
 950         u8 error;
 951
 952         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 953                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 954                       : "cc", "memory");
 955         if (error)
 956                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 957                        vmcs, phys_addr);
 958 }
 959
 960 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 961 {
 962         vmcs_clear(loaded_vmcs->vmcs);
 963         loaded_vmcs->cpu = -1;
 964         loaded_vmcs->launched = 0;
 965 }
 966
 967 static void vmcs_load(struct vmcs *vmcs)
 968 {
 969         u64 phys_addr = __pa(vmcs);
 970         u8 error;
 971
 972         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 973                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 974                         : "cc", "memory");
 975         if (error)
 976                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 977                        vmcs, phys_addr);
 978 }
 979
 980 static void __loaded_vmcs_clear(void *arg)
 981 {
 982         struct loaded_vmcs *loaded_vmcs = arg;
 983         int cpu = raw_smp_processor_id();
 984
 985         if (loaded_vmcs->cpu != cpu)
 986                 return; /* vcpu migration can race with cpu offline */
 987         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 988                 per_cpu(current_vmcs, cpu) = NULL;
 989         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 990         loaded_vmcs_init(loaded_vmcs);
 991 }
 992
 993 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 994 {
 995         if (loaded_vmcs->cpu != -1)
 996                 smp_call_function_single(
 997                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 998 }
 999
1000 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1001 {
1002         if (vmx->vpid == 0)
1003                 return;
1004
1005         if (cpu_has_vmx_invvpid_single())
1006                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1007 }
1008
1009 static inline void vpid_sync_vcpu_global(void)
1010 {
1011         if (cpu_has_vmx_invvpid_global())
1012                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1013 }
1014
1015 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1016 {
1017         if (cpu_has_vmx_invvpid_single())
1018                 vpid_sync_vcpu_single(vmx);
1019         else
1020                 vpid_sync_vcpu_global();
1021 }
1022
1023 static inline void ept_sync_global(void)
1024 {
1025         if (cpu_has_vmx_invept_global())
1026                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1027 }
1028
1029 static inline void ept_sync_context(u64 eptp)
1030 {
1031         if (enable_ept) {
1032                 if (cpu_has_vmx_invept_context())
1033                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1034                 else
1035                         ept_sync_global();
1036         }
1037 }
1038
1039 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1040 {
1041         if (enable_ept) {
1042                 if (cpu_has_vmx_invept_individual_addr())
1043                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1044                                         eptp, gpa);
1045                 else
1046                         ept_sync_context(eptp);
1047         }
1048 }
1049
1050 static __always_inline unsigned long vmcs_readl(unsigned long field)
1051 {
1052         unsigned long value;
1053
1054         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1055                       : "=a"(value) : "d"(field) : "cc");
1056         return value;
1057 }
1058
1059 static __always_inline u16 vmcs_read16(unsigned long field)
1060 {
1061         return vmcs_readl(field);
1062 }
1063
1064 static __always_inline u32 vmcs_read32(unsigned long field)
1065 {
1066         return vmcs_readl(field);
1067 }
1068
1069 static __always_inline u64 vmcs_read64(unsigned long field)
1070 {
1071 #ifdef CONFIG_X86_64
1072         return vmcs_readl(field);
1073 #else
1074         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1075 #endif
1076 }
1077
1078 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1079 {
1080         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1081                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1082         dump_stack();
1083 }
1084
1085 static void vmcs_writel(unsigned long field, unsigned long value)
1086 {
1087         u8 error;
1088
1089         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1090                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1091         if (unlikely(error))
1092                 vmwrite_error(field, value);
1093 }
1094
1095 static void vmcs_write16(unsigned long field, u16 value)
1096 {
1097         vmcs_writel(field, value);
1098 }
1099
1100 static void vmcs_write32(unsigned long field, u32 value)
1101 {
1102         vmcs_writel(field, value);
1103 }
1104
1105 static void vmcs_write64(unsigned long field, u64 value)
1106 {
1107         vmcs_writel(field, value);
1108 #ifndef CONFIG_X86_64
1109         asm volatile ("");
1110         vmcs_writel(field+1, value >> 32);
1111 #endif
1112 }
1113
1114 static void vmcs_clear_bits(unsigned long field, u32 mask)
1115 {
1116         vmcs_writel(field, vmcs_readl(field) & ~mask);
1117 }
1118
1119 static void vmcs_set_bits(unsigned long field, u32 mask)
1120 {
1121         vmcs_writel(field, vmcs_readl(field) | mask);
1122 }
1123
1124 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1125 {
1126         vmx->segment_cache.bitmask = 0;
1127 }
1128
1129 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1130                                        unsigned field)
1131 {
1132         bool ret;
1133         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1134
1135         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1136                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1137                 vmx->segment_cache.bitmask = 0;
1138         }
1139         ret = vmx->segment_cache.bitmask & mask;
1140         vmx->segment_cache.bitmask |= mask;
1141         return ret;
1142 }
1143
1144 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1145 {
1146         u16 *p = &vmx->segment_cache.seg[seg].selector;
1147
1148         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1149                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1150         return *p;
1151 }
1152
1153 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1154 {
1155         ulong *p = &vmx->segment_cache.seg[seg].base;
1156
1157         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1158                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1159         return *p;
1160 }
1161
1162 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1163 {
1164         u32 *p = &vmx->segment_cache.seg[seg].limit;
1165
1166         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1167                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1168         return *p;
1169 }
1170
1171 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1172 {
1173         u32 *p = &vmx->segment_cache.seg[seg].ar;
1174
1175         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1176                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1177         return *p;
1178 }
1179
1180 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1181 {
1182         u32 eb;
1183
1184         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1185              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1186         if ((vcpu->guest_debug &
1187              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1188             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1189                 eb |= 1u << BP_VECTOR;
1190         if (to_vmx(vcpu)->rmode.vm86_active)
1191                 eb = ~0;
1192         if (enable_ept)
1193                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1194         if (vcpu->fpu_active)
1195                 eb &= ~(1u << NM_VECTOR);
1196
1197         /* When we are running a nested L2 guest and L1 specified for it a
1198          * certain exception bitmap, we must trap the same exceptions and pass
1199          * them to L1. When running L2, we will only handle the exceptions
1200          * specified above if L1 did not want them.
1201          */
1202         if (is_guest_mode(vcpu))
1203                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1204
1205         vmcs_write32(EXCEPTION_BITMAP, eb);
1206 }
1207
1208 static void clear_atomic_switch_msr_special(unsigned long entry,
1209                 unsigned long exit)
1210 {
1211         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1212         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1213 }
1214
1215 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1216 {
1217         unsigned i;
1218         struct msr_autoload *m = &vmx->msr_autoload;
1219
1220         switch (msr) {
1221         case MSR_EFER:
1222                 if (cpu_has_load_ia32_efer) {
1223                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1224                                         VM_EXIT_LOAD_IA32_EFER);
1225                         return;
1226                 }
1227                 break;
1228         case MSR_CORE_PERF_GLOBAL_CTRL:
1229                 if (cpu_has_load_perf_global_ctrl) {
1230                         clear_atomic_switch_msr_special(
1231                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1232                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1233                         return;
1234                 }
1235                 break;
1236         }
1237
1238         for (i = 0; i < m->nr; ++i)
1239                 if (m->guest[i].index == msr)
1240                         break;
1241
1242         if (i == m->nr)
1243                 return;
1244         --m->nr;
1245         m->guest[i] = m->guest[m->nr];
1246         m->host[i] = m->host[m->nr];
1247         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1248         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1249 }
1250
1251 static void add_atomic_switch_msr_special(unsigned long entry,
1252                 unsigned long exit, unsigned long guest_val_vmcs,
1253                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1254 {
1255         vmcs_write64(guest_val_vmcs, guest_val);
1256         vmcs_write64(host_val_vmcs, host_val);
1257         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1258         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1259 }
1260
1261 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1262                                   u64 guest_val, u64 host_val)
1263 {
1264         unsigned i;
1265         struct msr_autoload *m = &vmx->msr_autoload;
1266
1267         switch (msr) {
1268         case MSR_EFER:
1269                 if (cpu_has_load_ia32_efer) {
1270                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1271                                         VM_EXIT_LOAD_IA32_EFER,
1272                                         GUEST_IA32_EFER,
1273                                         HOST_IA32_EFER,
1274                                         guest_val, host_val);
1275                         return;
1276                 }
1277                 break;
1278         case MSR_CORE_PERF_GLOBAL_CTRL:
1279                 if (cpu_has_load_perf_global_ctrl) {
1280                         add_atomic_switch_msr_special(
1281                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1282                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1283                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1284                                         HOST_IA32_PERF_GLOBAL_CTRL,
1285                                         guest_val, host_val);
1286                         return;
1287                 }
1288                 break;
1289         }
1290
1291         for (i = 0; i < m->nr; ++i)
1292                 if (m->guest[i].index == msr)
1293                         break;
1294
1295         if (i == NR_AUTOLOAD_MSRS) {
1296                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1297                                 "Can't add msr %x\n", msr);
1298                 return;
1299         } else if (i == m->nr) {
1300                 ++m->nr;
1301                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1302                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1303         }
1304
1305         m->guest[i].index = msr;
1306         m->guest[i].value = guest_val;
1307         m->host[i].index = msr;
1308         m->host[i].value = host_val;
1309 }
1310
1311 static void reload_tss(void)
1312 {
1313         /*
1314          * VT restores TR but not its size.  Useless.
1315          */
1316         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1317         struct desc_struct *descs;
1318
1319         descs = (void *)gdt->address;
1320         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1321         load_TR_desc();
1322 }
1323
1324 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1325 {
1326         u64 guest_efer;
1327         u64 ignore_bits;
1328
1329         guest_efer = vmx->vcpu.arch.efer;
1330
1331         /*
1332          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1333          * outside long mode
1334          */
1335         ignore_bits = EFER_NX | EFER_SCE;
1336 #ifdef CONFIG_X86_64
1337         ignore_bits |= EFER_LMA | EFER_LME;
1338         /* SCE is meaningful only in long mode on Intel */
1339         if (guest_efer & EFER_LMA)
1340                 ignore_bits &= ~(u64)EFER_SCE;
1341 #endif
1342         guest_efer &= ~ignore_bits;
1343         guest_efer |= host_efer & ignore_bits;
1344         vmx->guest_msrs[efer_offset].data = guest_efer;
1345         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1346
1347         clear_atomic_switch_msr(vmx, MSR_EFER);
1348         /* On ept, can't emulate nx, and must switch nx atomically */
1349         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1350                 guest_efer = vmx->vcpu.arch.efer;
1351                 if (!(guest_efer & EFER_LMA))
1352                         guest_efer &= ~EFER_LME;
1353                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1354                 return false;
1355         }
1356
1357         return true;
1358 }
1359
1360 static unsigned long segment_base(u16 selector)
1361 {
1362         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1363         struct desc_struct *d;
1364         unsigned long table_base;
1365         unsigned long v;
1366
1367         if (!(selector & ~3))
1368                 return 0;
1369
1370         table_base = gdt->address;
1371
1372         if (selector & 4) {           /* from ldt */
1373                 u16 ldt_selector = kvm_read_ldt();
1374
1375                 if (!(ldt_selector & ~3))
1376                         return 0;
1377
1378                 table_base = segment_base(ldt_selector);
1379         }
1380         d = (struct desc_struct *)(table_base + (selector & ~7));
1381         v = get_desc_base(d);
1382 #ifdef CONFIG_X86_64
1383        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1384                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1385 #endif
1386         return v;
1387 }
1388
1389 static inline unsigned long kvm_read_tr_base(void)
1390 {
1391         u16 tr;
1392         asm("str %0" : "=g"(tr));
1393         return segment_base(tr);
1394 }
1395
1396 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1397 {
1398         struct vcpu_vmx *vmx = to_vmx(vcpu);
1399         int i;
1400
1401         if (vmx->host_state.loaded)
1402                 return;
1403
1404         vmx->host_state.loaded = 1;
1405         /*
1406          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1407          * allow segment selectors with cpl > 0 or ti == 1.
1408          */
1409         vmx->host_state.ldt_sel = kvm_read_ldt();
1410         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1411         savesegment(fs, vmx->host_state.fs_sel);
1412         if (!(vmx->host_state.fs_sel & 7)) {
1413                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1414                 vmx->host_state.fs_reload_needed = 0;
1415         } else {
1416                 vmcs_write16(HOST_FS_SELECTOR, 0);
1417                 vmx->host_state.fs_reload_needed = 1;
1418         }
1419         savesegment(gs, vmx->host_state.gs_sel);
1420         if (!(vmx->host_state.gs_sel & 7))
1421                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1422         else {
1423                 vmcs_write16(HOST_GS_SELECTOR, 0);
1424                 vmx->host_state.gs_ldt_reload_needed = 1;
1425         }
1426
1427 #ifdef CONFIG_X86_64
1428         savesegment(ds, vmx->host_state.ds_sel);
1429         savesegment(es, vmx->host_state.es_sel);
1430 #endif
1431
1432 #ifdef CONFIG_X86_64
1433         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1434         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1435 #else
1436         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1437         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1438 #endif
1439
1440 #ifdef CONFIG_X86_64
1441         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1442         if (is_long_mode(&vmx->vcpu))
1443                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1444 #endif
1445         for (i = 0; i < vmx->save_nmsrs; ++i)
1446                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1447                                    vmx->guest_msrs[i].data,
1448                                    vmx->guest_msrs[i].mask);
1449 }
1450
1451 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1452 {
1453         if (!vmx->host_state.loaded)
1454                 return;
1455
1456         ++vmx->vcpu.stat.host_state_reload;
1457         vmx->host_state.loaded = 0;
1458 #ifdef CONFIG_X86_64
1459         if (is_long_mode(&vmx->vcpu))
1460                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1461 #endif
1462         if (vmx->host_state.gs_ldt_reload_needed) {
1463                 kvm_load_ldt(vmx->host_state.ldt_sel);
1464 #ifdef CONFIG_X86_64
1465                 load_gs_index(vmx->host_state.gs_sel);
1466 #else
1467                 loadsegment(gs, vmx->host_state.gs_sel);
1468 #endif
1469         }
1470         if (vmx->host_state.fs_reload_needed)
1471                 loadsegment(fs, vmx->host_state.fs_sel);
1472 #ifdef CONFIG_X86_64
1473         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1474                 loadsegment(ds, vmx->host_state.ds_sel);
1475                 loadsegment(es, vmx->host_state.es_sel);
1476         }
1477 #endif
1478         reload_tss();
1479 #ifdef CONFIG_X86_64
1480         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1481 #endif
1482         if (user_has_fpu())
1483                 clts();
1484         load_gdt(&__get_cpu_var(host_gdt));
1485 }
1486
1487 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1488 {
1489         preempt_disable();
1490         __vmx_load_host_state(vmx);
1491         preempt_enable();
1492 }
1493
1494 /*
1495  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1496  * vcpu mutex is already taken.
1497  */
1498 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1499 {
1500         struct vcpu_vmx *vmx = to_vmx(vcpu);
1501         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1502
1503         if (!vmm_exclusive)
1504                 kvm_cpu_vmxon(phys_addr);
1505         else if (vmx->loaded_vmcs->cpu != cpu)
1506                 loaded_vmcs_clear(vmx->loaded_vmcs);
1507
1508         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1509                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1510                 vmcs_load(vmx->loaded_vmcs->vmcs);
1511         }
1512
1513         if (vmx->loaded_vmcs->cpu != cpu) {
1514                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1515                 unsigned long sysenter_esp;
1516
1517                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1518                 local_irq_disable();
1519                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1520                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1521                 local_irq_enable();
1522
1523                 /*
1524                  * Linux uses per-cpu TSS and GDT, so set these when switching
1525                  * processors.
1526                  */
1527                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1528                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1529
1530                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1531                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1532                 vmx->loaded_vmcs->cpu = cpu;
1533         }
1534 }
1535
1536 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1537 {
1538         __vmx_load_host_state(to_vmx(vcpu));
1539         if (!vmm_exclusive) {
1540                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1541                 vcpu->cpu = -1;
1542                 kvm_cpu_vmxoff();
1543         }
1544 }
1545
1546 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1547 {
1548         ulong cr0;
1549
1550         if (vcpu->fpu_active)
1551                 return;
1552         vcpu->fpu_active = 1;
1553         cr0 = vmcs_readl(GUEST_CR0);
1554         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1555         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1556         vmcs_writel(GUEST_CR0, cr0);
1557         update_exception_bitmap(vcpu);
1558         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1559         if (is_guest_mode(vcpu))
1560                 vcpu->arch.cr0_guest_owned_bits &=
1561                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1562         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1563 }
1564
1565 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1566
1567 /*
1568  * Return the cr0 value that a nested guest would read. This is a combination
1569  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1570  * its hypervisor (cr0_read_shadow).
1571  */
1572 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1573 {
1574         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1575                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1576 }
1577 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1578 {
1579         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1580                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1581 }
1582
1583 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1584 {
1585         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1586          * set this *before* calling this function.
1587          */
1588         vmx_decache_cr0_guest_bits(vcpu);
1589         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1590         update_exception_bitmap(vcpu);
1591         vcpu->arch.cr0_guest_owned_bits = 0;
1592         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1593         if (is_guest_mode(vcpu)) {
1594                 /*
1595                  * L1's specified read shadow might not contain the TS bit,
1596                  * so now that we turned on shadowing of this bit, we need to
1597                  * set this bit of the shadow. Like in nested_vmx_run we need
1598                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1599                  * up-to-date here because we just decached cr0.TS (and we'll
1600                  * only update vmcs12->guest_cr0 on nested exit).
1601                  */
1602                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1603                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1604                         (vcpu->arch.cr0 & X86_CR0_TS);
1605                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1606         } else
1607                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1608 }
1609
1610 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1611 {
1612         unsigned long rflags, save_rflags;
1613
1614         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1615                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1616                 rflags = vmcs_readl(GUEST_RFLAGS);
1617                 if (to_vmx(vcpu)->rmode.vm86_active) {
1618                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1619                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1620                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1621                 }
1622                 to_vmx(vcpu)->rflags = rflags;
1623         }
1624         return to_vmx(vcpu)->rflags;
1625 }
1626
1627 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1628 {
1629         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1630         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1631         to_vmx(vcpu)->rflags = rflags;
1632         if (to_vmx(vcpu)->rmode.vm86_active) {
1633                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1634                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1635         }
1636         vmcs_writel(GUEST_RFLAGS, rflags);
1637 }
1638
1639 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1640 {
1641         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1642         int ret = 0;
1643
1644         if (interruptibility & GUEST_INTR_STATE_STI)
1645                 ret |= KVM_X86_SHADOW_INT_STI;
1646         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1647                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1648
1649         return ret & mask;
1650 }
1651
1652 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1653 {
1654         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1655         u32 interruptibility = interruptibility_old;
1656
1657         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1658
1659         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1660                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1661         else if (mask & KVM_X86_SHADOW_INT_STI)
1662                 interruptibility |= GUEST_INTR_STATE_STI;
1663
1664         if ((interruptibility != interruptibility_old))
1665                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1666 }
1667
1668 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1669 {
1670         unsigned long rip;
1671
1672         rip = kvm_rip_read(vcpu);
1673         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1674         kvm_rip_write(vcpu, rip);
1675
1676         /* skipping an emulated instruction also counts */
1677         vmx_set_interrupt_shadow(vcpu, 0);
1678 }
1679
1680 /*
1681  * KVM wants to inject page-faults which it got to the guest. This function
1682  * checks whether in a nested guest, we need to inject them to L1 or L2.
1683  * This function assumes it is called with the exit reason in vmcs02 being
1684  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1685  * is running).
1686  */
1687 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1688 {
1689         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1690
1691         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1692         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1693                 return 0;
1694
1695         nested_vmx_vmexit(vcpu);
1696         return 1;
1697 }
1698
1699 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1700                                 bool has_error_code, u32 error_code,
1701                                 bool reinject)
1702 {
1703         struct vcpu_vmx *vmx = to_vmx(vcpu);
1704         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1705
1706         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1707                 nested_pf_handled(vcpu))
1708                 return;
1709
1710         if (has_error_code) {
1711                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1712                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1713         }
1714
1715         if (vmx->rmode.vm86_active) {
1716                 int inc_eip = 0;
1717                 if (kvm_exception_is_soft(nr))
1718                         inc_eip = vcpu->arch.event_exit_inst_len;
1719                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1720                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1721                 return;
1722         }
1723
1724         if (kvm_exception_is_soft(nr)) {
1725                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1726                              vmx->vcpu.arch.event_exit_inst_len);
1727                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1728         } else
1729                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1730
1731         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1732 }
1733
1734 static bool vmx_rdtscp_supported(void)
1735 {
1736         return cpu_has_vmx_rdtscp();
1737 }
1738
1739 /*
1740  * Swap MSR entry in host/guest MSR entry array.
1741  */
1742 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1743 {
1744         struct shared_msr_entry tmp;
1745
1746         tmp = vmx->guest_msrs[to];
1747         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1748         vmx->guest_msrs[from] = tmp;
1749 }
1750
1751 /*
1752  * Set up the vmcs to automatically save and restore system
1753  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1754  * mode, as fiddling with msrs is very expensive.
1755  */
1756 static void setup_msrs(struct vcpu_vmx *vmx)
1757 {
1758         int save_nmsrs, index;
1759         unsigned long *msr_bitmap;
1760
1761         save_nmsrs = 0;
1762 #ifdef CONFIG_X86_64
1763         if (is_long_mode(&vmx->vcpu)) {
1764                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1765                 if (index >= 0)
1766                         move_msr_up(vmx, index, save_nmsrs++);
1767                 index = __find_msr_index(vmx, MSR_LSTAR);
1768                 if (index >= 0)
1769                         move_msr_up(vmx, index, save_nmsrs++);
1770                 index = __find_msr_index(vmx, MSR_CSTAR);
1771                 if (index >= 0)
1772                         move_msr_up(vmx, index, save_nmsrs++);
1773                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1774                 if (index >= 0 && vmx->rdtscp_enabled)
1775                         move_msr_up(vmx, index, save_nmsrs++);
1776                 /*
1777                  * MSR_STAR is only needed on long mode guests, and only
1778                  * if efer.sce is enabled.
1779                  */
1780                 index = __find_msr_index(vmx, MSR_STAR);
1781                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1782                         move_msr_up(vmx, index, save_nmsrs++);
1783         }
1784 #endif
1785         index = __find_msr_index(vmx, MSR_EFER);
1786         if (index >= 0 && update_transition_efer(vmx, index))
1787                 move_msr_up(vmx, index, save_nmsrs++);
1788
1789         vmx->save_nmsrs = save_nmsrs;
1790
1791         if (cpu_has_vmx_msr_bitmap()) {
1792                 if (is_long_mode(&vmx->vcpu))
1793                         msr_bitmap = vmx_msr_bitmap_longmode;
1794                 else
1795                         msr_bitmap = vmx_msr_bitmap_legacy;
1796
1797                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1798         }
1799 }
1800
1801 /*
1802  * reads and returns guest's timestamp counter "register"
1803  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1804  */
1805 static u64 guest_read_tsc(void)
1806 {
1807         u64 host_tsc, tsc_offset;
1808
1809         rdtscll(host_tsc);
1810         tsc_offset = vmcs_read64(TSC_OFFSET);
1811         return host_tsc + tsc_offset;
1812 }
1813
1814 /*
1815  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1816  * counter, even if a nested guest (L2) is currently running.
1817  */
1818 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1819 {
1820         u64 host_tsc, tsc_offset;
1821
1822         rdtscll(host_tsc);
1823         tsc_offset = is_guest_mode(vcpu) ?
1824                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1825                 vmcs_read64(TSC_OFFSET);
1826         return host_tsc + tsc_offset;
1827 }
1828
1829 /*
1830  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1831  * software catchup for faster rates on slower CPUs.
1832  */
1833 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1834 {
1835         if (!scale)
1836                 return;
1837
1838         if (user_tsc_khz > tsc_khz) {
1839                 vcpu->arch.tsc_catchup = 1;
1840                 vcpu->arch.tsc_always_catchup = 1;
1841         } else
1842                 WARN(1, "user requested TSC rate below hardware speed\n");
1843 }
1844
1845 /*
1846  * writes 'offset' into guest's timestamp counter offset register
1847  */
1848 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1849 {
1850         if (is_guest_mode(vcpu)) {
1851                 /*
1852                  * We're here if L1 chose not to trap WRMSR to TSC. According
1853                  * to the spec, this should set L1's TSC; The offset that L1
1854                  * set for L2 remains unchanged, and still needs to be added
1855                  * to the newly set TSC to get L2's TSC.
1856                  */
1857                 struct vmcs12 *vmcs12;
1858                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1859                 /* recalculate vmcs02.TSC_OFFSET: */
1860                 vmcs12 = get_vmcs12(vcpu);
1861                 vmcs_write64(TSC_OFFSET, offset +
1862                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1863                          vmcs12->tsc_offset : 0));
1864         } else {
1865                 vmcs_write64(TSC_OFFSET, offset);
1866         }
1867 }
1868
1869 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1870 {
1871         u64 offset = vmcs_read64(TSC_OFFSET);
1872         vmcs_write64(TSC_OFFSET, offset + adjustment);
1873         if (is_guest_mode(vcpu)) {
1874                 /* Even when running L2, the adjustment needs to apply to L1 */
1875                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1876         }
1877 }
1878
1879 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1880 {
1881         return target_tsc - native_read_tsc();
1882 }
1883
1884 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1885 {
1886         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1887         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1888 }
1889
1890 /*
1891  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1892  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1893  * all guests if the "nested" module option is off, and can also be disabled
1894  * for a single guest by disabling its VMX cpuid bit.
1895  */
1896 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1897 {
1898         return nested && guest_cpuid_has_vmx(vcpu);
1899 }
1900
1901 /*
1902  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1903  * returned for the various VMX controls MSRs when nested VMX is enabled.
1904  * The same values should also be used to verify that vmcs12 control fields are
1905  * valid during nested entry from L1 to L2.
1906  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1907  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1908  * bit in the high half is on if the corresponding bit in the control field
1909  * may be on. See also vmx_control_verify().
1910  * TODO: allow these variables to be modified (downgraded) by module options
1911  * or other means.
1912  */
1913 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1914 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1915 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1916 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1917 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1918 static __init void nested_vmx_setup_ctls_msrs(void)
1919 {
1920         /*
1921          * Note that as a general rule, the high half of the MSRs (bits in
1922          * the control fields which may be 1) should be initialized by the
1923          * intersection of the underlying hardware's MSR (i.e., features which
1924          * can be supported) and the list of features we want to expose -
1925          * because they are known to be properly supported in our code.
1926          * Also, usually, the low half of the MSRs (bits which must be 1) can
1927          * be set to 0, meaning that L1 may turn off any of these bits. The
1928          * reason is that if one of these bits is necessary, it will appear
1929          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1930          * fields of vmcs01 and vmcs02, will turn these bits off - and
1931          * nested_vmx_exit_handled() will not pass related exits to L1.
1932          * These rules have exceptions below.
1933          */
1934
1935         /* pin-based controls */
1936         /*
1937          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1938          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1939          */
1940         nested_vmx_pinbased_ctls_low = 0x16 ;
1941         nested_vmx_pinbased_ctls_high = 0x16 |
1942                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1943                 PIN_BASED_VIRTUAL_NMIS;
1944
1945         /* exit controls */
1946         nested_vmx_exit_ctls_low = 0;
1947         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1948 #ifdef CONFIG_X86_64
1949         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1950 #else
1951         nested_vmx_exit_ctls_high = 0;
1952 #endif
1953
1954         /* entry controls */
1955         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1956                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1957         nested_vmx_entry_ctls_low = 0;
1958         nested_vmx_entry_ctls_high &=
1959                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1960
1961         /* cpu-based controls */
1962         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1963                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1964         nested_vmx_procbased_ctls_low = 0;
1965         nested_vmx_procbased_ctls_high &=
1966                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1967                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1968                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1969                 CPU_BASED_CR3_STORE_EXITING |
1970 #ifdef CONFIG_X86_64
1971                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1972 #endif
1973                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1974                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1975                 CPU_BASED_RDPMC_EXITING |
1976                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1977         /*
1978          * We can allow some features even when not supported by the
1979          * hardware. For example, L1 can specify an MSR bitmap - and we
1980          * can use it to avoid exits to L1 - even when L0 runs L2
1981          * without MSR bitmaps.
1982          */
1983         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1984
1985         /* secondary cpu-based controls */
1986         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1987                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1988         nested_vmx_secondary_ctls_low = 0;
1989         nested_vmx_secondary_ctls_high &=
1990                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1991 }
1992
1993 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1994 {
1995         /*
1996          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1997          */
1998         return ((control & high) | low) == control;
1999 }
2000
2001 static inline u64 vmx_control_msr(u32 low, u32 high)
2002 {
2003         return low | ((u64)high << 32);
2004 }
2005
2006 /*
2007  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2008  * also let it use VMX-specific MSRs.
2009  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2010  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2011  * like all other MSRs).
2012  */
2013 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2014 {
2015         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2016                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2017                 /*
2018                  * According to the spec, processors which do not support VMX
2019                  * should throw a #GP(0) when VMX capability MSRs are read.
2020                  */
2021                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2022                 return 1;
2023         }
2024
2025         switch (msr_index) {
2026         case MSR_IA32_FEATURE_CONTROL:
2027                 *pdata = 0;
2028                 break;
2029         case MSR_IA32_VMX_BASIC:
2030                 /*
2031                  * This MSR reports some information about VMX support. We
2032                  * should return information about the VMX we emulate for the
2033                  * guest, and the VMCS structure we give it - not about the
2034                  * VMX support of the underlying hardware.
2035                  */
2036                 *pdata = VMCS12_REVISION |
2037                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2038                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2039                 break;
2040         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2041         case MSR_IA32_VMX_PINBASED_CTLS:
2042                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2043                                         nested_vmx_pinbased_ctls_high);
2044                 break;
2045         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2046         case MSR_IA32_VMX_PROCBASED_CTLS:
2047                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2048                                         nested_vmx_procbased_ctls_high);
2049                 break;
2050         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2051         case MSR_IA32_VMX_EXIT_CTLS:
2052                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2053                                         nested_vmx_exit_ctls_high);
2054                 break;
2055         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2056         case MSR_IA32_VMX_ENTRY_CTLS:
2057                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2058                                         nested_vmx_entry_ctls_high);
2059                 break;
2060         case MSR_IA32_VMX_MISC:
2061                 *pdata = 0;
2062                 break;
2063         /*
2064          * These MSRs specify bits which the guest must keep fixed (on or off)
2065          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2066          * We picked the standard core2 setting.
2067          */
2068 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2069 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2070         case MSR_IA32_VMX_CR0_FIXED0:
2071                 *pdata = VMXON_CR0_ALWAYSON;
2072                 break;
2073         case MSR_IA32_VMX_CR0_FIXED1:
2074                 *pdata = -1ULL;
2075                 break;
2076         case MSR_IA32_VMX_CR4_FIXED0:
2077                 *pdata = VMXON_CR4_ALWAYSON;
2078                 break;
2079         case MSR_IA32_VMX_CR4_FIXED1:
2080                 *pdata = -1ULL;
2081                 break;
2082         case MSR_IA32_VMX_VMCS_ENUM:
2083                 *pdata = 0x1f;
2084                 break;
2085         case MSR_IA32_VMX_PROCBASED_CTLS2:
2086                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2087                                         nested_vmx_secondary_ctls_high);
2088                 break;
2089         case MSR_IA32_VMX_EPT_VPID_CAP:
2090                 /* Currently, no nested ept or nested vpid */
2091                 *pdata = 0;
2092                 break;
2093         default:
2094                 return 0;
2095         }
2096
2097         return 1;
2098 }
2099
2100 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2101 {
2102         if (!nested_vmx_allowed(vcpu))
2103                 return 0;
2104
2105         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2106                 /* TODO: the right thing. */
2107                 return 1;
2108         /*
2109          * No need to treat VMX capability MSRs specially: If we don't handle
2110          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2111          */
2112         return 0;
2113 }
2114
2115 /*
2116  * Reads an msr value (of 'msr_index') into 'pdata'.
2117  * Returns 0 on success, non-0 otherwise.
2118  * Assumes vcpu_load() was already called.
2119  */
2120 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2121 {
2122         u64 data;
2123         struct shared_msr_entry *msr;
2124
2125         if (!pdata) {
2126                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2127                 return -EINVAL;
2128         }
2129
2130         switch (msr_index) {
2131 #ifdef CONFIG_X86_64
2132         case MSR_FS_BASE:
2133                 data = vmcs_readl(GUEST_FS_BASE);
2134                 break;
2135         case MSR_GS_BASE:
2136                 data = vmcs_readl(GUEST_GS_BASE);
2137                 break;
2138         case MSR_KERNEL_GS_BASE:
2139                 vmx_load_host_state(to_vmx(vcpu));
2140                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2141                 break;
2142 #endif
2143         case MSR_EFER:
2144                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2145         case MSR_IA32_TSC:
2146                 data = guest_read_tsc();
2147                 break;
2148         case MSR_IA32_SYSENTER_CS:
2149                 data = vmcs_read32(GUEST_SYSENTER_CS);
2150                 break;
2151         case MSR_IA32_SYSENTER_EIP:
2152                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2153                 break;
2154         case MSR_IA32_SYSENTER_ESP:
2155                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2156                 break;
2157         case MSR_TSC_AUX:
2158                 if (!to_vmx(vcpu)->rdtscp_enabled)
2159                         return 1;
2160                 /* Otherwise falls through */
2161         default:
2162                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2163                         return 0;
2164                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2165                 if (msr) {
2166                         data = msr->data;
2167                         break;
2168                 }
2169                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2170         }
2171
2172         *pdata = data;
2173         return 0;
2174 }
2175
2176 /*
2177  * Writes msr value into into the appropriate "register".
2178  * Returns 0 on success, non-0 otherwise.
2179  * Assumes vcpu_load() was already called.
2180  */
2181 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2182 {
2183         struct vcpu_vmx *vmx = to_vmx(vcpu);
2184         struct shared_msr_entry *msr;
2185         int ret = 0;
2186
2187         switch (msr_index) {
2188         case MSR_EFER:
2189                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2190                 break;
2191 #ifdef CONFIG_X86_64
2192         case MSR_FS_BASE:
2193                 vmx_segment_cache_clear(vmx);
2194                 vmcs_writel(GUEST_FS_BASE, data);
2195                 break;
2196         case MSR_GS_BASE:
2197                 vmx_segment_cache_clear(vmx);
2198                 vmcs_writel(GUEST_GS_BASE, data);
2199                 break;
2200         case MSR_KERNEL_GS_BASE:
2201                 vmx_load_host_state(vmx);
2202                 vmx->msr_guest_kernel_gs_base = data;
2203                 break;
2204 #endif
2205         case MSR_IA32_SYSENTER_CS:
2206                 vmcs_write32(GUEST_SYSENTER_CS, data);
2207                 break;
2208         case MSR_IA32_SYSENTER_EIP:
2209                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2210                 break;
2211         case MSR_IA32_SYSENTER_ESP:
2212                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2213                 break;
2214         case MSR_IA32_TSC:
2215                 kvm_write_tsc(vcpu, data);
2216                 break;
2217         case MSR_IA32_CR_PAT:
2218                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2219                         vmcs_write64(GUEST_IA32_PAT, data);
2220                         vcpu->arch.pat = data;
2221                         break;
2222                 }
2223                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2224                 break;
2225         case MSR_TSC_AUX:
2226                 if (!vmx->rdtscp_enabled)
2227                         return 1;
2228                 /* Check reserved bit, higher 32 bits should be zero */
2229                 if ((data >> 32) != 0)
2230                         return 1;
2231                 /* Otherwise falls through */
2232         default:
2233                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2234                         break;
2235                 msr = find_msr_entry(vmx, msr_index);
2236                 if (msr) {
2237                         msr->data = data;
2238                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2239                                 preempt_disable();
2240                                 kvm_set_shared_msr(msr->index, msr->data,
2241                                                    msr->mask);
2242                                 preempt_enable();
2243                         }
2244                         break;
2245                 }
2246                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2247         }
2248
2249         return ret;
2250 }
2251
2252 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2253 {
2254         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2255         switch (reg) {
2256         case VCPU_REGS_RSP:
2257                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2258                 break;
2259         case VCPU_REGS_RIP:
2260                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2261                 break;
2262         case VCPU_EXREG_PDPTR:
2263                 if (enable_ept)
2264                         ept_save_pdptrs(vcpu);
2265                 break;
2266         default:
2267                 break;
2268         }
2269 }
2270
2271 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2272 {
2273         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2274                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2275         else
2276                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2277
2278         update_exception_bitmap(vcpu);
2279 }
2280
2281 static __init int cpu_has_kvm_support(void)
2282 {
2283         return cpu_has_vmx();
2284 }
2285
2286 static __init int vmx_disabled_by_bios(void)
2287 {
2288         u64 msr;
2289
2290         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2291         if (msr & FEATURE_CONTROL_LOCKED) {
2292                 /* launched w/ TXT and VMX disabled */
2293                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2294                         && tboot_enabled())
2295                         return 1;
2296                 /* launched w/o TXT and VMX only enabled w/ TXT */
2297                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2298                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2299                         && !tboot_enabled()) {
2300                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2301                                 "activate TXT before enabling KVM\n");
2302                         return 1;
2303                 }
2304                 /* launched w/o TXT and VMX disabled */
2305                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2306                         && !tboot_enabled())
2307                         return 1;
2308         }
2309
2310         return 0;
2311 }
2312
2313 static void kvm_cpu_vmxon(u64 addr)
2314 {
2315         asm volatile (ASM_VMX_VMXON_RAX
2316                         : : "a"(&addr), "m"(addr)
2317                         : "memory", "cc");
2318 }
2319
2320 static int hardware_enable(void *garbage)
2321 {
2322         int cpu = raw_smp_processor_id();
2323         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2324         u64 old, test_bits;
2325
2326         if (read_cr4() & X86_CR4_VMXE)
2327                 return -EBUSY;
2328
2329         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2330         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2331
2332         test_bits = FEATURE_CONTROL_LOCKED;
2333         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2334         if (tboot_enabled())
2335                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2336
2337         if ((old & test_bits) != test_bits) {
2338                 /* enable and lock */
2339                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2340         }
2341         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2342
2343         if (vmm_exclusive) {
2344                 kvm_cpu_vmxon(phys_addr);
2345                 ept_sync_global();
2346         }
2347
2348         store_gdt(&__get_cpu_var(host_gdt));
2349
2350         return 0;
2351 }
2352
2353 static void vmclear_local_loaded_vmcss(void)
2354 {
2355         int cpu = raw_smp_processor_id();
2356         struct loaded_vmcs *v, *n;
2357
2358         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2359                                  loaded_vmcss_on_cpu_link)
2360                 __loaded_vmcs_clear(v);
2361 }
2362
2363
2364 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2365  * tricks.
2366  */
2367 static void kvm_cpu_vmxoff(void)
2368 {
2369         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2370 }
2371
2372 static void hardware_disable(void *garbage)
2373 {
2374         if (vmm_exclusive) {
2375                 vmclear_local_loaded_vmcss();
2376                 kvm_cpu_vmxoff();
2377         }
2378         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2379 }
2380
2381 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2382                                       u32 msr, u32 *result)
2383 {
2384         u32 vmx_msr_low, vmx_msr_high;
2385         u32 ctl = ctl_min | ctl_opt;
2386
2387         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2388
2389         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2390         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2391
2392         /* Ensure minimum (required) set of control bits are supported. */
2393         if (ctl_min & ~ctl)
2394                 return -EIO;
2395
2396         *result = ctl;
2397         return 0;
2398 }
2399
2400 static __init bool allow_1_setting(u32 msr, u32 ctl)
2401 {
2402         u32 vmx_msr_low, vmx_msr_high;
2403
2404         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2405         return vmx_msr_high & ctl;
2406 }
2407
2408 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2409 {
2410         u32 vmx_msr_low, vmx_msr_high;
2411         u32 min, opt, min2, opt2;
2412         u32 _pin_based_exec_control = 0;
2413         u32 _cpu_based_exec_control = 0;
2414         u32 _cpu_based_2nd_exec_control = 0;
2415         u32 _vmexit_control = 0;
2416         u32 _vmentry_control = 0;
2417
2418         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2419         opt = PIN_BASED_VIRTUAL_NMIS;
2420         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2421                                 &_pin_based_exec_control) < 0)
2422                 return -EIO;
2423
2424         min = CPU_BASED_HLT_EXITING |
2425 #ifdef CONFIG_X86_64
2426               CPU_BASED_CR8_LOAD_EXITING |
2427               CPU_BASED_CR8_STORE_EXITING |
2428 #endif
2429               CPU_BASED_CR3_LOAD_EXITING |
2430               CPU_BASED_CR3_STORE_EXITING |
2431               CPU_BASED_USE_IO_BITMAPS |
2432               CPU_BASED_MOV_DR_EXITING |
2433               CPU_BASED_USE_TSC_OFFSETING |
2434               CPU_BASED_MWAIT_EXITING |
2435               CPU_BASED_MONITOR_EXITING |
2436               CPU_BASED_INVLPG_EXITING |
2437               CPU_BASED_RDPMC_EXITING;
2438
2439         opt = CPU_BASED_TPR_SHADOW |
2440               CPU_BASED_USE_MSR_BITMAPS |
2441               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2442         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2443                                 &_cpu_based_exec_control) < 0)
2444                 return -EIO;
2445 #ifdef CONFIG_X86_64
2446         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2447                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2448                                            ~CPU_BASED_CR8_STORE_EXITING;
2449 #endif
2450         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2451                 min2 = 0;
2452                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2453                         SECONDARY_EXEC_WBINVD_EXITING |
2454                         SECONDARY_EXEC_ENABLE_VPID |
2455                         SECONDARY_EXEC_ENABLE_EPT |
2456                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2457                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2458                         SECONDARY_EXEC_RDTSCP;
2459                 if (adjust_vmx_controls(min2, opt2,
2460                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2461                                         &_cpu_based_2nd_exec_control) < 0)
2462                         return -EIO;
2463         }
2464 #ifndef CONFIG_X86_64
2465         if (!(_cpu_based_2nd_exec_control &
2466                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2467                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2468 #endif
2469         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2470                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2471                    enabled */
2472                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2473                                              CPU_BASED_CR3_STORE_EXITING |
2474                                              CPU_BASED_INVLPG_EXITING);
2475                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2476                       vmx_capability.ept, vmx_capability.vpid);
2477         }
2478
2479         min = 0;
2480 #ifdef CONFIG_X86_64
2481         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2482 #endif
2483         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2484         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2485                                 &_vmexit_control) < 0)
2486                 return -EIO;
2487
2488         min = 0;
2489         opt = VM_ENTRY_LOAD_IA32_PAT;
2490         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2491                                 &_vmentry_control) < 0)
2492                 return -EIO;
2493
2494         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2495
2496         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2497         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2498                 return -EIO;
2499
2500 #ifdef CONFIG_X86_64
2501         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2502         if (vmx_msr_high & (1u<<16))
2503                 return -EIO;
2504 #endif
2505
2506         /* Require Write-Back (WB) memory type for VMCS accesses. */
2507         if (((vmx_msr_high >> 18) & 15) != 6)
2508                 return -EIO;
2509
2510         vmcs_conf->size = vmx_msr_high & 0x1fff;
2511         vmcs_conf->order = get_order(vmcs_config.size);
2512         vmcs_conf->revision_id = vmx_msr_low;
2513
2514         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2515         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2516         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2517         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2518         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2519
2520         cpu_has_load_ia32_efer =
2521                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2522                                 VM_ENTRY_LOAD_IA32_EFER)
2523                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2524                                    VM_EXIT_LOAD_IA32_EFER);
2525
2526         cpu_has_load_perf_global_ctrl =
2527                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2528                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2529                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2530                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2531
2532         /*
2533          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2534          * but due to arrata below it can't be used. Workaround is to use
2535          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2536          *
2537          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2538          *
2539          * AAK155             (model 26)
2540          * AAP115             (model 30)
2541          * AAT100             (model 37)
2542          * BC86,AAY89,BD102   (model 44)
2543          * BA97               (model 46)
2544          *
2545          */
2546         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2547                 switch (boot_cpu_data.x86_model) {
2548                 case 26:
2549                 case 30:
2550                 case 37:
2551                 case 44:
2552                 case 46:
2553                         cpu_has_load_perf_global_ctrl = false;
2554                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2555                                         "does not work properly. Using workaround\n");
2556                         break;
2557                 default:
2558                         break;
2559                 }
2560         }
2561
2562         return 0;
2563 }
2564
2565 static struct vmcs *alloc_vmcs_cpu(int cpu)
2566 {
2567         int node = cpu_to_node(cpu);
2568         struct page *pages;
2569         struct vmcs *vmcs;
2570
2571         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2572         if (!pages)
2573                 return NULL;
2574         vmcs = page_address(pages);
2575         memset(vmcs, 0, vmcs_config.size);
2576         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2577         return vmcs;
2578 }
2579
2580 static struct vmcs *alloc_vmcs(void)
2581 {
2582         return alloc_vmcs_cpu(raw_smp_processor_id());
2583 }
2584
2585 static void free_vmcs(struct vmcs *vmcs)
2586 {
2587         free_pages((unsigned long)vmcs, vmcs_config.order);
2588 }
2589
2590 /*
2591  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2592  */
2593 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2594 {
2595         if (!loaded_vmcs->vmcs)
2596                 return;
2597         loaded_vmcs_clear(loaded_vmcs);
2598         free_vmcs(loaded_vmcs->vmcs);
2599         loaded_vmcs->vmcs = NULL;
2600 }
2601
2602 static void free_kvm_area(void)
2603 {
2604         int cpu;
2605
2606         for_each_possible_cpu(cpu) {
2607                 free_vmcs(per_cpu(vmxarea, cpu));
2608                 per_cpu(vmxarea, cpu) = NULL;
2609         }
2610 }
2611
2612 static __init int alloc_kvm_area(void)
2613 {
2614         int cpu;
2615
2616         for_each_possible_cpu(cpu) {
2617                 struct vmcs *vmcs;
2618
2619                 vmcs = alloc_vmcs_cpu(cpu);
2620                 if (!vmcs) {
2621                         free_kvm_area();
2622                         return -ENOMEM;
2623                 }
2624
2625                 per_cpu(vmxarea, cpu) = vmcs;
2626         }
2627         return 0;
2628 }
2629
2630 static __init int hardware_setup(void)
2631 {
2632         if (setup_vmcs_config(&vmcs_config) < 0)
2633                 return -EIO;
2634
2635         if (boot_cpu_has(X86_FEATURE_NX))
2636                 kvm_enable_efer_bits(EFER_NX);
2637
2638         if (!cpu_has_vmx_vpid())
2639                 enable_vpid = 0;
2640
2641         if (!cpu_has_vmx_ept() ||
2642             !cpu_has_vmx_ept_4levels()) {
2643                 enable_ept = 0;
2644                 enable_unrestricted_guest = 0;
2645         }
2646
2647         if (!cpu_has_vmx_unrestricted_guest())
2648                 enable_unrestricted_guest = 0;
2649
2650         if (!cpu_has_vmx_flexpriority())
2651                 flexpriority_enabled = 0;
2652
2653         if (!cpu_has_vmx_tpr_shadow())
2654                 kvm_x86_ops->update_cr8_intercept = NULL;
2655
2656         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2657                 kvm_disable_largepages();
2658
2659         if (!cpu_has_vmx_ple())
2660                 ple_gap = 0;
2661
2662         if (nested)
2663                 nested_vmx_setup_ctls_msrs();
2664
2665         return alloc_kvm_area();
2666 }
2667
2668 static __exit void hardware_unsetup(void)
2669 {
2670         free_kvm_area();
2671 }
2672
2673 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2674 {
2675         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2676
2677         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2678                 vmcs_write16(sf->selector, save->selector);
2679                 vmcs_writel(sf->base, save->base);
2680                 vmcs_write32(sf->limit, save->limit);
2681                 vmcs_write32(sf->ar_bytes, save->ar);
2682         } else {
2683                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2684                         << AR_DPL_SHIFT;
2685                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2686         }
2687 }
2688
2689 static void enter_pmode(struct kvm_vcpu *vcpu)
2690 {
2691         unsigned long flags;
2692         struct vcpu_vmx *vmx = to_vmx(vcpu);
2693
2694         vmx->emulation_required = 1;
2695         vmx->rmode.vm86_active = 0;
2696
2697         vmx_segment_cache_clear(vmx);
2698
2699         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2700         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2701         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2702         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2703
2704         flags = vmcs_readl(GUEST_RFLAGS);
2705         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2706         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2707         vmcs_writel(GUEST_RFLAGS, flags);
2708
2709         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2710                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2711
2712         update_exception_bitmap(vcpu);
2713
2714         if (emulate_invalid_guest_state)
2715                 return;
2716
2717         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2718         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2719         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2720         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2721
2722         vmx_segment_cache_clear(vmx);
2723
2724         vmcs_write16(GUEST_SS_SELECTOR, 0);
2725         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2726
2727         vmcs_write16(GUEST_CS_SELECTOR,
2728                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2729         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2730 }
2731
2732 static gva_t rmode_tss_base(struct kvm *kvm)
2733 {
2734         if (!kvm->arch.tss_addr) {
2735                 struct kvm_memslots *slots;
2736                 struct kvm_memory_slot *slot;
2737                 gfn_t base_gfn;
2738
2739                 slots = kvm_memslots(kvm);
2740                 slot = id_to_memslot(slots, 0);
2741                 base_gfn = slot->base_gfn + slot->npages - 3;
2742
2743                 return base_gfn << PAGE_SHIFT;
2744         }
2745         return kvm->arch.tss_addr;
2746 }
2747
2748 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2749 {
2750         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2751
2752         save->selector = vmcs_read16(sf->selector);
2753         save->base = vmcs_readl(sf->base);
2754         save->limit = vmcs_read32(sf->limit);
2755         save->ar = vmcs_read32(sf->ar_bytes);
2756         vmcs_write16(sf->selector, save->base >> 4);
2757         vmcs_write32(sf->base, save->base & 0xffff0);
2758         vmcs_write32(sf->limit, 0xffff);
2759         vmcs_write32(sf->ar_bytes, 0xf3);
2760         if (save->base & 0xf)
2761                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2762                             " aligned when entering protected mode (seg=%d)",
2763                             seg);
2764 }
2765
2766 static void enter_rmode(struct kvm_vcpu *vcpu)
2767 {
2768         unsigned long flags;
2769         struct vcpu_vmx *vmx = to_vmx(vcpu);
2770         struct kvm_segment var;
2771
2772         if (enable_unrestricted_guest)
2773                 return;
2774
2775         vmx->emulation_required = 1;
2776         vmx->rmode.vm86_active = 1;
2777
2778         /*
2779          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2780          * vcpu. Call it here with phys address pointing 16M below 4G.
2781          */
2782         if (!vcpu->kvm->arch.tss_addr) {
2783                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2784                              "called before entering vcpu\n");
2785                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2786                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2787                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2788         }
2789
2790         vmx_segment_cache_clear(vmx);
2791
2792         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2793         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2794         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2795
2796         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2797         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2798
2799         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2800         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2801
2802         flags = vmcs_readl(GUEST_RFLAGS);
2803         vmx->rmode.save_rflags = flags;
2804
2805         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2806
2807         vmcs_writel(GUEST_RFLAGS, flags);
2808         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2809         update_exception_bitmap(vcpu);
2810
2811         if (emulate_invalid_guest_state)
2812                 goto continue_rmode;
2813
2814         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2815         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2816
2817         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2818         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2819
2820         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2821         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2822
2823         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2824         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2825
2826         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2827         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2828
2829         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2830         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2831
2832 continue_rmode:
2833         kvm_mmu_reset_context(vcpu);
2834 }
2835
2836 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2837 {
2838         struct vcpu_vmx *vmx = to_vmx(vcpu);
2839         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2840
2841         if (!msr)
2842                 return;
2843
2844         /*
2845          * Force kernel_gs_base reloading before EFER changes, as control
2846          * of this msr depends on is_long_mode().
2847          */
2848         vmx_load_host_state(to_vmx(vcpu));
2849         vcpu->arch.efer = efer;
2850         if (efer & EFER_LMA) {
2851                 vmcs_write32(VM_ENTRY_CONTROLS,
2852                              vmcs_read32(VM_ENTRY_CONTROLS) |
2853                              VM_ENTRY_IA32E_MODE);
2854                 msr->data = efer;
2855         } else {
2856                 vmcs_write32(VM_ENTRY_CONTROLS,
2857                              vmcs_read32(VM_ENTRY_CONTROLS) &
2858                              ~VM_ENTRY_IA32E_MODE);
2859
2860                 msr->data = efer & ~EFER_LME;
2861         }
2862         setup_msrs(vmx);
2863 }
2864
2865 #ifdef CONFIG_X86_64
2866
2867 static void enter_lmode(struct kvm_vcpu *vcpu)
2868 {
2869         u32 guest_tr_ar;
2870
2871         vmx_segment_cache_clear(to_vmx(vcpu));
2872
2873         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2874         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2875                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2876                                      __func__);
2877                 vmcs_write32(GUEST_TR_AR_BYTES,
2878                              (guest_tr_ar & ~AR_TYPE_MASK)
2879                              | AR_TYPE_BUSY_64_TSS);
2880         }
2881         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2882 }
2883
2884 static void exit_lmode(struct kvm_vcpu *vcpu)
2885 {
2886         vmcs_write32(VM_ENTRY_CONTROLS,
2887                      vmcs_read32(VM_ENTRY_CONTROLS)
2888                      & ~VM_ENTRY_IA32E_MODE);
2889         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2890 }
2891
2892 #endif
2893
2894 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2895 {
2896         vpid_sync_context(to_vmx(vcpu));
2897         if (enable_ept) {
2898                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2899                         return;
2900                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2901         }
2902 }
2903
2904 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2905 {
2906         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2907
2908         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2909         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2910 }
2911
2912 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2913 {
2914         if (enable_ept && is_paging(vcpu))
2915                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2916         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2917 }
2918
2919 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2920 {
2921         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2922
2923         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2924         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2925 }
2926
2927 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2928 {
2929         if (!test_bit(VCPU_EXREG_PDPTR,
2930                       (unsigned long *)&vcpu->arch.regs_dirty))
2931                 return;
2932
2933         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2934                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2935                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2936                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2937                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2938         }
2939 }
2940
2941 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2942 {
2943         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2944                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2945                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2946                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2947                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2948         }
2949
2950         __set_bit(VCPU_EXREG_PDPTR,
2951                   (unsigned long *)&vcpu->arch.regs_avail);
2952         __set_bit(VCPU_EXREG_PDPTR,
2953                   (unsigned long *)&vcpu->arch.regs_dirty);
2954 }
2955
2956 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2957
2958 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2959                                         unsigned long cr0,
2960                                         struct kvm_vcpu *vcpu)
2961 {
2962         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2963                 vmx_decache_cr3(vcpu);
2964         if (!(cr0 & X86_CR0_PG)) {
2965                 /* From paging/starting to nonpaging */
2966                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2967                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2968                              (CPU_BASED_CR3_LOAD_EXITING |
2969                               CPU_BASED_CR3_STORE_EXITING));
2970                 vcpu->arch.cr0 = cr0;
2971                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2972         } else if (!is_paging(vcpu)) {
2973                 /* From nonpaging to paging */
2974                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2975                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2976                              ~(CPU_BASED_CR3_LOAD_EXITING |
2977                                CPU_BASED_CR3_STORE_EXITING));
2978                 vcpu->arch.cr0 = cr0;
2979                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2980         }
2981
2982         if (!(cr0 & X86_CR0_WP))
2983                 *hw_cr0 &= ~X86_CR0_WP;
2984 }
2985
2986 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2987 {
2988         struct vcpu_vmx *vmx = to_vmx(vcpu);
2989         unsigned long hw_cr0;
2990
2991         if (enable_unrestricted_guest)
2992                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2993                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2994         else
2995                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2996
2997         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2998                 enter_pmode(vcpu);
2999
3000         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3001                 enter_rmode(vcpu);
3002
3003 #ifdef CONFIG_X86_64
3004         if (vcpu->arch.efer & EFER_LME) {
3005                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3006                         enter_lmode(vcpu);
3007                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3008                         exit_lmode(vcpu);
3009         }
3010 #endif
3011
3012         if (enable_ept)
3013                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3014
3015         if (!vcpu->fpu_active)
3016                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3017
3018         vmcs_writel(CR0_READ_SHADOW, cr0);
3019         vmcs_writel(GUEST_CR0, hw_cr0);
3020         vcpu->arch.cr0 = cr0;
3021         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3022 }
3023
3024 static u64 construct_eptp(unsigned long root_hpa)
3025 {
3026         u64 eptp;
3027
3028         /* TODO write the value reading from MSR */
3029         eptp = VMX_EPT_DEFAULT_MT |
3030                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3031         eptp |= (root_hpa & PAGE_MASK);
3032
3033         return eptp;
3034 }
3035
3036 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3037 {
3038         unsigned long guest_cr3;
3039         u64 eptp;
3040
3041         guest_cr3 = cr3;
3042         if (enable_ept) {
3043                 eptp = construct_eptp(cr3);
3044                 vmcs_write64(EPT_POINTER, eptp);
3045                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3046                         vcpu->kvm->arch.ept_identity_map_addr;
3047                 ept_load_pdptrs(vcpu);
3048         }
3049
3050         vmx_flush_tlb(vcpu);
3051         vmcs_writel(GUEST_CR3, guest_cr3);
3052 }
3053
3054 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3055 {
3056         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3057                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3058
3059         if (cr4 & X86_CR4_VMXE) {
3060                 /*
3061                  * To use VMXON (and later other VMX instructions), a guest
3062                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3063                  * So basically the check on whether to allow nested VMX
3064                  * is here.
3065                  */
3066                 if (!nested_vmx_allowed(vcpu))
3067                         return 1;
3068         } else if (to_vmx(vcpu)->nested.vmxon)
3069                 return 1;
3070
3071         vcpu->arch.cr4 = cr4;
3072         if (enable_ept) {
3073                 if (!is_paging(vcpu)) {
3074                         hw_cr4 &= ~X86_CR4_PAE;
3075                         hw_cr4 |= X86_CR4_PSE;
3076                 } else if (!(cr4 & X86_CR4_PAE)) {
3077                         hw_cr4 &= ~X86_CR4_PAE;
3078                 }
3079         }
3080
3081         vmcs_writel(CR4_READ_SHADOW, cr4);
3082         vmcs_writel(GUEST_CR4, hw_cr4);
3083         return 0;
3084 }
3085
3086 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3087                             struct kvm_segment *var, int seg)
3088 {
3089         struct vcpu_vmx *vmx = to_vmx(vcpu);
3090         struct kvm_save_segment *save;
3091         u32 ar;
3092
3093         if (vmx->rmode.vm86_active
3094             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3095                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3096                 || seg == VCPU_SREG_GS)
3097             && !emulate_invalid_guest_state) {
3098                 switch (seg) {
3099                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3100                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3101                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3102                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3103                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3104                 default: BUG();
3105                 }
3106                 var->selector = save->selector;
3107                 var->base = save->base;
3108                 var->limit = save->limit;
3109                 ar = save->ar;
3110                 if (seg == VCPU_SREG_TR
3111                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3112                         goto use_saved_rmode_seg;
3113         }
3114         var->base = vmx_read_guest_seg_base(vmx, seg);
3115         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3116         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3117         ar = vmx_read_guest_seg_ar(vmx, seg);
3118 use_saved_rmode_seg:
3119         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3120                 ar = 0;
3121         var->type = ar & 15;
3122         var->s = (ar >> 4) & 1;
3123         var->dpl = (ar >> 5) & 3;
3124         var->present = (ar >> 7) & 1;
3125         var->avl = (ar >> 12) & 1;
3126         var->l = (ar >> 13) & 1;
3127         var->db = (ar >> 14) & 1;
3128         var->g = (ar >> 15) & 1;
3129         var->unusable = (ar >> 16) & 1;
3130 }
3131
3132 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3133 {
3134         struct kvm_segment s;
3135
3136         if (to_vmx(vcpu)->rmode.vm86_active) {
3137                 vmx_get_segment(vcpu, &s, seg);
3138                 return s.base;
3139         }
3140         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3141 }
3142
3143 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3144 {
3145         if (!is_protmode(vcpu))
3146                 return 0;
3147
3148         if (!is_long_mode(vcpu)
3149             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3150                 return 3;
3151
3152         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3153 }
3154
3155 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3156 {
3157         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3158                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3159                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3160         }
3161         return to_vmx(vcpu)->cpl;
3162 }
3163
3164
3165 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3166 {
3167         u32 ar;
3168
3169         if (var->unusable)
3170                 ar = 1 << 16;
3171         else {
3172                 ar = var->type & 15;
3173                 ar |= (var->s & 1) << 4;
3174                 ar |= (var->dpl & 3) << 5;
3175                 ar |= (var->present & 1) << 7;
3176                 ar |= (var->avl & 1) << 12;
3177                 ar |= (var->l & 1) << 13;
3178                 ar |= (var->db & 1) << 14;
3179                 ar |= (var->g & 1) << 15;
3180         }
3181         if (ar == 0) /* a 0 value means unusable */
3182                 ar = AR_UNUSABLE_MASK;
3183
3184         return ar;
3185 }
3186
3187 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3188                             struct kvm_segment *var, int seg)
3189 {
3190         struct vcpu_vmx *vmx = to_vmx(vcpu);
3191         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3192         u32 ar;
3193
3194         vmx_segment_cache_clear(vmx);
3195
3196         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3197                 vmcs_write16(sf->selector, var->selector);
3198                 vmx->rmode.tr.selector = var->selector;
3199                 vmx->rmode.tr.base = var->base;
3200                 vmx->rmode.tr.limit = var->limit;
3201                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3202                 return;
3203         }
3204         vmcs_writel(sf->base, var->base);
3205         vmcs_write32(sf->limit, var->limit);
3206         vmcs_write16(sf->selector, var->selector);
3207         if (vmx->rmode.vm86_active && var->s) {
3208                 /*
3209                  * Hack real-mode segments into vm86 compatibility.
3210                  */
3211                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3212                         vmcs_writel(sf->base, 0xf0000);
3213                 ar = 0xf3;
3214         } else
3215                 ar = vmx_segment_access_rights(var);
3216
3217         /*
3218          *   Fix the "Accessed" bit in AR field of segment registers for older
3219          * qemu binaries.
3220          *   IA32 arch specifies that at the time of processor reset the
3221          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3222          * is setting it to 0 in the usedland code. This causes invalid guest
3223          * state vmexit when "unrestricted guest" mode is turned on.
3224          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3225          * tree. Newer qemu binaries with that qemu fix would not need this
3226          * kvm hack.
3227          */
3228         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3229                 ar |= 0x1; /* Accessed */
3230
3231         vmcs_write32(sf->ar_bytes, ar);
3232         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3233
3234         /*
3235          * Fix segments for real mode guest in hosts that don't have
3236          * "unrestricted_mode" or it was disabled.
3237          * This is done to allow migration of the guests from hosts with
3238          * unrestricted guest like Westmere to older host that don't have
3239          * unrestricted guest like Nehelem.
3240          */
3241         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3242                 switch (seg) {
3243                 case VCPU_SREG_CS:
3244                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3245                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3246                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3247                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3248                         vmcs_write16(GUEST_CS_SELECTOR,
3249                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3250                         break;
3251                 case VCPU_SREG_ES:
3252                         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3253                         break;
3254                 case VCPU_SREG_DS:
3255                         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3256                         break;
3257                 case VCPU_SREG_GS:
3258                         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3259                         break;
3260                 case VCPU_SREG_FS:
3261                         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3262                         break;
3263                 case VCPU_SREG_SS:
3264                         vmcs_write16(GUEST_SS_SELECTOR,
3265                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3266                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3267                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3268                         break;
3269                 }
3270         }
3271 }
3272
3273 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3274 {
3275         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3276
3277         *db = (ar >> 14) & 1;
3278         *l = (ar >> 13) & 1;
3279 }
3280
3281 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3282 {
3283         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3284         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3285 }
3286
3287 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3288 {
3289         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3290         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3291 }
3292
3293 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3294 {
3295         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3296         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3297 }
3298
3299 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3300 {
3301         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3302         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3303 }
3304
3305 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3306 {
3307         struct kvm_segment var;
3308         u32 ar;
3309
3310         vmx_get_segment(vcpu, &var, seg);
3311         ar = vmx_segment_access_rights(&var);
3312
3313         if (var.base != (var.selector << 4))
3314                 return false;
3315         if (var.limit != 0xffff)
3316                 return false;
3317         if (ar != 0xf3)
3318                 return false;
3319
3320         return true;
3321 }
3322
3323 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3324 {
3325         struct kvm_segment cs;
3326         unsigned int cs_rpl;
3327
3328         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3329         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3330
3331         if (cs.unusable)
3332                 return false;
3333         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3334                 return false;
3335         if (!cs.s)
3336                 return false;
3337         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3338                 if (cs.dpl > cs_rpl)
3339                         return false;
3340         } else {
3341                 if (cs.dpl != cs_rpl)
3342                         return false;
3343         }
3344         if (!cs.present)
3345                 return false;
3346
3347         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3348         return true;
3349 }
3350
3351 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3352 {
3353         struct kvm_segment ss;
3354         unsigned int ss_rpl;
3355
3356         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3357         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3358
3359         if (ss.unusable)
3360                 return true;
3361         if (ss.type != 3 && ss.type != 7)
3362                 return false;
3363         if (!ss.s)
3364                 return false;
3365         if (ss.dpl != ss_rpl) /* DPL != RPL */
3366                 return false;
3367         if (!ss.present)
3368                 return false;
3369
3370         return true;
3371 }
3372
3373 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3374 {
3375         struct kvm_segment var;
3376         unsigned int rpl;
3377
3378         vmx_get_segment(vcpu, &var, seg);
3379         rpl = var.selector & SELECTOR_RPL_MASK;
3380
3381         if (var.unusable)
3382                 return true;
3383         if (!var.s)
3384                 return false;
3385         if (!var.present)
3386                 return false;
3387         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3388                 if (var.dpl < rpl) /* DPL < RPL */
3389                         return false;
3390         }
3391
3392         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3393          * rights flags
3394          */
3395         return true;
3396 }
3397
3398 static bool tr_valid(struct kvm_vcpu *vcpu)
3399 {
3400         struct kvm_segment tr;
3401
3402         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3403
3404         if (tr.unusable)
3405                 return false;
3406         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3407                 return false;
3408         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3409                 return false;
3410         if (!tr.present)
3411                 return false;
3412
3413         return true;
3414 }
3415
3416 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3417 {
3418         struct kvm_segment ldtr;
3419
3420         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3421
3422         if (ldtr.unusable)
3423                 return true;
3424         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3425                 return false;
3426         if (ldtr.type != 2)
3427                 return false;
3428         if (!ldtr.present)
3429                 return false;
3430
3431         return true;
3432 }
3433
3434 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3435 {
3436         struct kvm_segment cs, ss;
3437
3438         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3439         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3440
3441         return ((cs.selector & SELECTOR_RPL_MASK) ==
3442                  (ss.selector & SELECTOR_RPL_MASK));
3443 }
3444
3445 /*
3446  * Check if guest state is valid. Returns true if valid, false if
3447  * not.
3448  * We assume that registers are always usable
3449  */
3450 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3451 {
3452         /* real mode guest state checks */
3453         if (!is_protmode(vcpu)) {
3454                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3455                         return false;
3456                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3457                         return false;
3458                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3459                         return false;
3460                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3461                         return false;
3462                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3463                         return false;
3464                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3465                         return false;
3466         } else {
3467         /* protected mode guest state checks */
3468                 if (!cs_ss_rpl_check(vcpu))
3469                         return false;
3470                 if (!code_segment_valid(vcpu))
3471                         return false;
3472                 if (!stack_segment_valid(vcpu))
3473                         return false;
3474                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3475                         return false;
3476                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3477                         return false;
3478                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3479                         return false;
3480                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3481                         return false;
3482                 if (!tr_valid(vcpu))
3483                         return false;
3484                 if (!ldtr_valid(vcpu))
3485                         return false;
3486         }
3487         /* TODO:
3488          * - Add checks on RIP
3489          * - Add checks on RFLAGS
3490          */
3491
3492         return true;
3493 }
3494
3495 static int init_rmode_tss(struct kvm *kvm)
3496 {
3497         gfn_t fn;
3498         u16 data = 0;
3499         int r, idx, ret = 0;
3500
3501         idx = srcu_read_lock(&kvm->srcu);
3502         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3503         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3504         if (r < 0)
3505                 goto out;
3506         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3507         r = kvm_write_guest_page(kvm, fn++, &data,
3508                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3509         if (r < 0)
3510                 goto out;
3511         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3512         if (r < 0)
3513                 goto out;
3514         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3515         if (r < 0)
3516                 goto out;
3517         data = ~0;
3518         r = kvm_write_guest_page(kvm, fn, &data,
3519                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3520                                  sizeof(u8));
3521         if (r < 0)
3522                 goto out;
3523
3524         ret = 1;
3525 out:
3526         srcu_read_unlock(&kvm->srcu, idx);
3527         return ret;
3528 }
3529
3530 static int init_rmode_identity_map(struct kvm *kvm)
3531 {
3532         int i, idx, r, ret;
3533         pfn_t identity_map_pfn;
3534         u32 tmp;
3535
3536         if (!enable_ept)
3537                 return 1;
3538         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3539                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3540                         "haven't been allocated!\n");
3541                 return 0;
3542         }
3543         if (likely(kvm->arch.ept_identity_pagetable_done))
3544                 return 1;
3545         ret = 0;
3546         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3547         idx = srcu_read_lock(&kvm->srcu);
3548         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3549         if (r < 0)
3550                 goto out;
3551         /* Set up identity-mapping pagetable for EPT in real mode */
3552         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3553                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3554                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3555                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3556                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3557                 if (r < 0)
3558                         goto out;
3559         }
3560         kvm->arch.ept_identity_pagetable_done = true;
3561         ret = 1;
3562 out:
3563         srcu_read_unlock(&kvm->srcu, idx);
3564         return ret;
3565 }
3566
3567 static void seg_setup(int seg)
3568 {
3569         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3570         unsigned int ar;
3571
3572         vmcs_write16(sf->selector, 0);
3573         vmcs_writel(sf->base, 0);
3574         vmcs_write32(sf->limit, 0xffff);
3575         if (enable_unrestricted_guest) {
3576                 ar = 0x93;
3577                 if (seg == VCPU_SREG_CS)
3578                         ar |= 0x08; /* code segment */
3579         } else
3580                 ar = 0xf3;
3581
3582         vmcs_write32(sf->ar_bytes, ar);
3583 }
3584
3585 static int alloc_apic_access_page(struct kvm *kvm)
3586 {
3587         struct kvm_userspace_memory_region kvm_userspace_mem;
3588         int r = 0;
3589
3590         mutex_lock(&kvm->slots_lock);
3591         if (kvm->arch.apic_access_page)
3592                 goto out;
3593         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3594         kvm_userspace_mem.flags = 0;
3595         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3596         kvm_userspace_mem.memory_size = PAGE_SIZE;
3597         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3598         if (r)
3599                 goto out;
3600
3601         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3602 out:
3603         mutex_unlock(&kvm->slots_lock);
3604         return r;
3605 }
3606
3607 static int alloc_identity_pagetable(struct kvm *kvm)
3608 {
3609         struct kvm_userspace_memory_region kvm_userspace_mem;
3610         int r = 0;
3611
3612         mutex_lock(&kvm->slots_lock);
3613         if (kvm->arch.ept_identity_pagetable)
3614                 goto out;
3615         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3616         kvm_userspace_mem.flags = 0;
3617         kvm_userspace_mem.guest_phys_addr =
3618                 kvm->arch.ept_identity_map_addr;
3619         kvm_userspace_mem.memory_size = PAGE_SIZE;
3620         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3621         if (r)
3622                 goto out;
3623
3624         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3625                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3626 out:
3627         mutex_unlock(&kvm->slots_lock);
3628         return r;
3629 }
3630
3631 static void allocate_vpid(struct vcpu_vmx *vmx)
3632 {
3633         int vpid;
3634
3635         vmx->vpid = 0;
3636         if (!enable_vpid)
3637                 return;
3638         spin_lock(&vmx_vpid_lock);
3639         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3640         if (vpid < VMX_NR_VPIDS) {
3641                 vmx->vpid = vpid;
3642                 __set_bit(vpid, vmx_vpid_bitmap);
3643         }
3644         spin_unlock(&vmx_vpid_lock);
3645 }
3646
3647 static void free_vpid(struct vcpu_vmx *vmx)
3648 {
3649         if (!enable_vpid)
3650                 return;
3651         spin_lock(&vmx_vpid_lock);
3652         if (vmx->vpid != 0)
3653                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3654         spin_unlock(&vmx_vpid_lock);
3655 }
3656
3657 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3658 {
3659         int f = sizeof(unsigned long);
3660
3661         if (!cpu_has_vmx_msr_bitmap())
3662                 return;
3663
3664         /*
3665          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3666          * have the write-low and read-high bitmap offsets the wrong way round.
3667          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3668          */
3669         if (msr <= 0x1fff) {
3670                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3671                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3672         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3673                 msr &= 0x1fff;
3674                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3675                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3676         }
3677 }
3678
3679 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3680 {
3681         if (!longmode_only)
3682                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3683         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3684 }
3685
3686 /*
3687  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3688  * will not change in the lifetime of the guest.
3689  * Note that host-state that does change is set elsewhere. E.g., host-state
3690  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3691  */
3692 static void vmx_set_constant_host_state(void)
3693 {
3694         u32 low32, high32;
3695         unsigned long tmpl;
3696         struct desc_ptr dt;
3697
3698         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3699         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3700         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3701
3702         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3703 #ifdef CONFIG_X86_64
3704         /*
3705          * Load null selectors, so we can avoid reloading them in
3706          * __vmx_load_host_state(), in case userspace uses the null selectors
3707          * too (the expected case).
3708          */
3709         vmcs_write16(HOST_DS_SELECTOR, 0);
3710         vmcs_write16(HOST_ES_SELECTOR, 0);
3711 #else
3712         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3713         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3714 #endif
3715         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3716         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3717
3718         native_store_idt(&dt);
3719         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3720
3721         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3722         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3723
3724         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3725         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3726         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3727         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3728
3729         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3730                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3731                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3732         }
3733 }
3734
3735 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3736 {
3737         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3738         if (enable_ept)
3739                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3740         if (is_guest_mode(&vmx->vcpu))
3741                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3742                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3743         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3744 }
3745
3746 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3747 {
3748         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3749         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3750                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3751 #ifdef CONFIG_X86_64
3752                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3753                                 CPU_BASED_CR8_LOAD_EXITING;
3754 #endif
3755         }
3756         if (!enable_ept)
3757                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3758                                 CPU_BASED_CR3_LOAD_EXITING  |
3759                                 CPU_BASED_INVLPG_EXITING;
3760         return exec_control;
3761 }
3762
3763 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3764 {
3765         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3766         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3767                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3768         if (vmx->vpid == 0)
3769                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3770         if (!enable_ept) {
3771                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3772                 enable_unrestricted_guest = 0;
3773         }
3774         if (!enable_unrestricted_guest)
3775                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3776         if (!ple_gap)
3777                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3778         return exec_control;
3779 }
3780
3781 static void ept_set_mmio_spte_mask(void)
3782 {
3783         /*
3784          * EPT Misconfigurations can be generated if the value of bits 2:0
3785          * of an EPT paging-structure entry is 110b (write/execute).
3786          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3787          * spte.
3788          */
3789         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3790 }
3791
3792 /*
3793  * Sets up the vmcs for emulated real mode.
3794  */
3795 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3796 {
3797 #ifdef CONFIG_X86_64
3798         unsigned long a;
3799 #endif
3800         int i;
3801
3802         /* I/O */
3803         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3804         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3805
3806         if (cpu_has_vmx_msr_bitmap())
3807                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3808
3809         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3810
3811         /* Control */
3812         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3813                 vmcs_config.pin_based_exec_ctrl);
3814
3815         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3816
3817         if (cpu_has_secondary_exec_ctrls()) {
3818                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3819                                 vmx_secondary_exec_control(vmx));
3820         }
3821
3822         if (ple_gap) {
3823                 vmcs_write32(PLE_GAP, ple_gap);
3824                 vmcs_write32(PLE_WINDOW, ple_window);
3825         }
3826
3827         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3828         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3829         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3830
3831         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3832         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3833         vmx_set_constant_host_state();
3834 #ifdef CONFIG_X86_64
3835         rdmsrl(MSR_FS_BASE, a);
3836         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3837         rdmsrl(MSR_GS_BASE, a);
3838         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3839 #else
3840         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3841         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3842 #endif
3843
3844         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3845         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3846         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3847         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3848         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3849
3850         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3851                 u32 msr_low, msr_high;
3852                 u64 host_pat;
3853                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3854                 host_pat = msr_low | ((u64) msr_high << 32);
3855                 /* Write the default value follow host pat */
3856                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3857                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3858                 vmx->vcpu.arch.pat = host_pat;
3859         }
3860
3861         for (i = 0; i < NR_VMX_MSR; ++i) {
3862                 u32 index = vmx_msr_index[i];
3863                 u32 data_low, data_high;
3864                 int j = vmx->nmsrs;
3865
3866                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3867                         continue;
3868                 if (wrmsr_safe(index, data_low, data_high) < 0)
3869                         continue;
3870                 vmx->guest_msrs[j].index = i;
3871                 vmx->guest_msrs[j].data = 0;
3872                 vmx->guest_msrs[j].mask = -1ull;
3873                 ++vmx->nmsrs;
3874         }
3875
3876         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3877
3878         /* 22.2.1, 20.8.1 */
3879         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3880
3881         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3882         set_cr4_guest_host_mask(vmx);
3883
3884         kvm_write_tsc(&vmx->vcpu, 0);
3885
3886         return 0;
3887 }
3888
3889 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3890 {
3891         struct vcpu_vmx *vmx = to_vmx(vcpu);
3892         u64 msr;
3893         int ret;
3894
3895         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3896
3897         vmx->rmode.vm86_active = 0;
3898
3899         vmx->soft_vnmi_blocked = 0;
3900
3901         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3902         kvm_set_cr8(&vmx->vcpu, 0);
3903         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3904         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3905                 msr |= MSR_IA32_APICBASE_BSP;
3906         kvm_set_apic_base(&vmx->vcpu, msr);
3907
3908         ret = fx_init(&vmx->vcpu);
3909         if (ret != 0)
3910                 goto out;
3911
3912         vmx_segment_cache_clear(vmx);
3913
3914         seg_setup(VCPU_SREG_CS);
3915         /*
3916          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3917          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3918          */
3919         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3920                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3921                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3922         } else {
3923                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3924                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3925         }
3926
3927         seg_setup(VCPU_SREG_DS);
3928         seg_setup(VCPU_SREG_ES);
3929         seg_setup(VCPU_SREG_FS);
3930         seg_setup(VCPU_SREG_GS);
3931         seg_setup(VCPU_SREG_SS);
3932
3933         vmcs_write16(GUEST_TR_SELECTOR, 0);
3934         vmcs_writel(GUEST_TR_BASE, 0);
3935         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3936         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3937
3938         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3939         vmcs_writel(GUEST_LDTR_BASE, 0);
3940         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3941         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3942
3943         vmcs_write32(GUEST_SYSENTER_CS, 0);
3944         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3945         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3946
3947         vmcs_writel(GUEST_RFLAGS, 0x02);
3948         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3949                 kvm_rip_write(vcpu, 0xfff0);
3950         else
3951                 kvm_rip_write(vcpu, 0);
3952         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3953
3954         vmcs_writel(GUEST_DR7, 0x400);
3955
3956         vmcs_writel(GUEST_GDTR_BASE, 0);
3957         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3958
3959         vmcs_writel(GUEST_IDTR_BASE, 0);
3960         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3961
3962         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3963         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3964         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3965
3966         /* Special registers */
3967         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3968
3969         setup_msrs(vmx);
3970
3971         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3972
3973         if (cpu_has_vmx_tpr_shadow()) {
3974                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3975                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3976                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3977                                      __pa(vmx->vcpu.arch.apic->regs));
3978                 vmcs_write32(TPR_THRESHOLD, 0);
3979         }
3980
3981         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3982                 vmcs_write64(APIC_ACCESS_ADDR,
3983                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3984
3985         if (vmx->vpid != 0)
3986                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3987
3988         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3989         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3990         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3991         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3992         vmx_set_cr4(&vmx->vcpu, 0);
3993         vmx_set_efer(&vmx->vcpu, 0);
3994         vmx_fpu_activate(&vmx->vcpu);
3995         update_exception_bitmap(&vmx->vcpu);
3996
3997         vpid_sync_context(vmx);
3998
3999         ret = 0;
4000
4001         /* HACK: Don't enable emulation on guest boot/reset */
4002         vmx->emulation_required = 0;
4003
4004 out:
4005         return ret;
4006 }
4007
4008 /*
4009  * In nested virtualization, check if L1 asked to exit on external interrupts.
4010  * For most existing hypervisors, this will always return true.
4011  */
4012 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4013 {
4014         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4015                 PIN_BASED_EXT_INTR_MASK;
4016 }
4017
4018 static void enable_irq_window(struct kvm_vcpu *vcpu)
4019 {
4020         u32 cpu_based_vm_exec_control;
4021         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4022                 /*
4023                  * We get here if vmx_interrupt_allowed() said we can't
4024                  * inject to L1 now because L2 must run. Ask L2 to exit
4025                  * right after entry, so we can inject to L1 more promptly.
4026                  */
4027                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4028                 return;
4029         }
4030
4031         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4032         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4033         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4034 }
4035
4036 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4037 {
4038         u32 cpu_based_vm_exec_control;
4039
4040         if (!cpu_has_virtual_nmis()) {
4041                 enable_irq_window(vcpu);
4042                 return;
4043         }
4044
4045         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4046                 enable_irq_window(vcpu);
4047                 return;
4048         }
4049         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4050         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4051         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4052 }
4053
4054 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4055 {
4056         struct vcpu_vmx *vmx = to_vmx(vcpu);
4057         uint32_t intr;
4058         int irq = vcpu->arch.interrupt.nr;
4059
4060         trace_kvm_inj_virq(irq);
4061
4062         ++vcpu->stat.irq_injections;
4063         if (vmx->rmode.vm86_active) {
4064                 int inc_eip = 0;
4065                 if (vcpu->arch.interrupt.soft)
4066                         inc_eip = vcpu->arch.event_exit_inst_len;
4067                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4068                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4069                 return;
4070         }
4071         intr = irq | INTR_INFO_VALID_MASK;
4072         if (vcpu->arch.interrupt.soft) {
4073                 intr |= INTR_TYPE_SOFT_INTR;
4074                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4075                              vmx->vcpu.arch.event_exit_inst_len);
4076         } else
4077                 intr |= INTR_TYPE_EXT_INTR;
4078         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4079 }
4080
4081 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4082 {
4083         struct vcpu_vmx *vmx = to_vmx(vcpu);
4084
4085         if (is_guest_mode(vcpu))
4086                 return;
4087
4088         if (!cpu_has_virtual_nmis()) {
4089                 /*
4090                  * Tracking the NMI-blocked state in software is built upon
4091                  * finding the next open IRQ window. This, in turn, depends on
4092                  * well-behaving guests: They have to keep IRQs disabled at
4093                  * least as long as the NMI handler runs. Otherwise we may
4094                  * cause NMI nesting, maybe breaking the guest. But as this is
4095                  * highly unlikely, we can live with the residual risk.
4096                  */
4097                 vmx->soft_vnmi_blocked = 1;
4098                 vmx->vnmi_blocked_time = 0;
4099         }
4100
4101         ++vcpu->stat.nmi_injections;
4102         vmx->nmi_known_unmasked = false;
4103         if (vmx->rmode.vm86_active) {
4104                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4105                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4106                 return;
4107         }
4108         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4109                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4110 }
4111
4112 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4113 {
4114         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4115                 return 0;
4116
4117         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4118                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4119                    | GUEST_INTR_STATE_NMI));
4120 }
4121
4122 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4123 {
4124         if (!cpu_has_virtual_nmis())
4125                 return to_vmx(vcpu)->soft_vnmi_blocked;
4126         if (to_vmx(vcpu)->nmi_known_unmasked)
4127                 return false;
4128         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4129 }
4130
4131 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4132 {
4133         struct vcpu_vmx *vmx = to_vmx(vcpu);
4134
4135         if (!cpu_has_virtual_nmis()) {
4136                 if (vmx->soft_vnmi_blocked != masked) {
4137                         vmx->soft_vnmi_blocked = masked;
4138                         vmx->vnmi_blocked_time = 0;
4139                 }
4140         } else {
4141                 vmx->nmi_known_unmasked = !masked;
4142                 if (masked)
4143                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4144                                       GUEST_INTR_STATE_NMI);
4145                 else
4146                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4147                                         GUEST_INTR_STATE_NMI);
4148         }
4149 }
4150
4151 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4152 {
4153         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4154                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4155                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4156                     (vmcs12->idt_vectoring_info_field &
4157                      VECTORING_INFO_VALID_MASK))
4158                         return 0;
4159                 nested_vmx_vmexit(vcpu);
4160                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4161                 vmcs12->vm_exit_intr_info = 0;
4162                 /* fall through to normal code, but now in L1, not L2 */
4163         }
4164
4165         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4166                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4167                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4168 }
4169
4170 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4171 {
4172         int ret;
4173         struct kvm_userspace_memory_region tss_mem = {
4174                 .slot = TSS_PRIVATE_MEMSLOT,
4175                 .guest_phys_addr = addr,
4176                 .memory_size = PAGE_SIZE * 3,
4177                 .flags = 0,
4178         };
4179
4180         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4181         if (ret)
4182                 return ret;
4183         kvm->arch.tss_addr = addr;
4184         if (!init_rmode_tss(kvm))
4185                 return  -ENOMEM;
4186
4187         return 0;
4188 }
4189
4190 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4191                                   int vec, u32 err_code)
4192 {
4193         /*
4194          * Instruction with address size override prefix opcode 0x67
4195          * Cause the #SS fault with 0 error code in VM86 mode.
4196          */
4197         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4198                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4199                         return 1;
4200         /*
4201          * Forward all other exceptions that are valid in real mode.
4202          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4203          *        the required debugging infrastructure rework.
4204          */
4205         switch (vec) {
4206         case DB_VECTOR:
4207                 if (vcpu->guest_debug &
4208                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4209                         return 0;
4210                 kvm_queue_exception(vcpu, vec);
4211                 return 1;
4212         case BP_VECTOR:
4213                 /*
4214                  * Update instruction length as we may reinject the exception
4215                  * from user space while in guest debugging mode.
4216                  */
4217                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4218                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4219                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4220                         return 0;
4221                 /* fall through */
4222         case DE_VECTOR:
4223         case OF_VECTOR:
4224         case BR_VECTOR:
4225         case UD_VECTOR:
4226         case DF_VECTOR:
4227         case SS_VECTOR:
4228         case GP_VECTOR:
4229         case MF_VECTOR:
4230                 kvm_queue_exception(vcpu, vec);
4231                 return 1;
4232         }
4233         return 0;
4234 }
4235
4236 /*
4237  * Trigger machine check on the host. We assume all the MSRs are already set up
4238  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4239  * We pass a fake environment to the machine check handler because we want
4240  * the guest to be always treated like user space, no matter what context
4241  * it used internally.
4242  */
4243 static void kvm_machine_check(void)
4244 {
4245 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4246         struct pt_regs regs = {
4247                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4248                 .flags = X86_EFLAGS_IF,
4249         };
4250
4251         do_machine_check(&regs, 0);
4252 #endif
4253 }
4254
4255 static int handle_machine_check(struct kvm_vcpu *vcpu)
4256 {
4257         /* already handled by vcpu_run */
4258         return 1;
4259 }
4260
4261 static int handle_exception(struct kvm_vcpu *vcpu)
4262 {
4263         struct vcpu_vmx *vmx = to_vmx(vcpu);
4264         struct kvm_run *kvm_run = vcpu->run;
4265         u32 intr_info, ex_no, error_code;
4266         unsigned long cr2, rip, dr6;
4267         u32 vect_info;
4268         enum emulation_result er;
4269
4270         vect_info = vmx->idt_vectoring_info;
4271         intr_info = vmx->exit_intr_info;
4272
4273         if (is_machine_check(intr_info))
4274                 return handle_machine_check(vcpu);
4275
4276         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4277             !is_page_fault(intr_info)) {
4278                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4279                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4280                 vcpu->run->internal.ndata = 2;
4281                 vcpu->run->internal.data[0] = vect_info;
4282                 vcpu->run->internal.data[1] = intr_info;
4283                 return 0;
4284         }
4285
4286         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4287                 return 1;  /* already handled by vmx_vcpu_run() */
4288
4289         if (is_no_device(intr_info)) {
4290                 vmx_fpu_activate(vcpu);
4291                 return 1;
4292         }
4293
4294         if (is_invalid_opcode(intr_info)) {
4295                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4296                 if (er != EMULATE_DONE)
4297                         kvm_queue_exception(vcpu, UD_VECTOR);
4298                 return 1;
4299         }
4300
4301         error_code = 0;
4302         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4303                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4304         if (is_page_fault(intr_info)) {
4305                 /* EPT won't cause page fault directly */
4306                 BUG_ON(enable_ept);
4307                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4308                 trace_kvm_page_fault(cr2, error_code);
4309
4310                 if (kvm_event_needs_reinjection(vcpu))
4311                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4312                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4313         }
4314
4315         if (vmx->rmode.vm86_active &&
4316             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4317                                                                 error_code)) {
4318                 if (vcpu->arch.halt_request) {
4319                         vcpu->arch.halt_request = 0;
4320                         return kvm_emulate_halt(vcpu);
4321                 }
4322                 return 1;
4323         }
4324
4325         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4326         switch (ex_no) {
4327         case DB_VECTOR:
4328                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4329                 if (!(vcpu->guest_debug &
4330                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4331                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4332                         kvm_queue_exception(vcpu, DB_VECTOR);
4333                         return 1;
4334                 }
4335                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4336                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4337                 /* fall through */
4338         case BP_VECTOR:
4339                 /*
4340                  * Update instruction length as we may reinject #BP from
4341                  * user space while in guest debugging mode. Reading it for
4342                  * #DB as well causes no harm, it is not used in that case.
4343                  */
4344                 vmx->vcpu.arch.event_exit_inst_len =
4345                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4346                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4347                 rip = kvm_rip_read(vcpu);
4348                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4349                 kvm_run->debug.arch.exception = ex_no;
4350                 break;
4351         default:
4352                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4353                 kvm_run->ex.exception = ex_no;
4354                 kvm_run->ex.error_code = error_code;
4355                 break;
4356         }
4357         return 0;
4358 }
4359
4360 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4361 {
4362         ++vcpu->stat.irq_exits;
4363         return 1;
4364 }
4365
4366 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4367 {
4368         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4369         return 0;
4370 }
4371
4372 static int handle_io(struct kvm_vcpu *vcpu)
4373 {
4374         unsigned long exit_qualification;
4375         int size, in, string;
4376         unsigned port;
4377
4378         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4379         string = (exit_qualification & 16) != 0;
4380         in = (exit_qualification & 8) != 0;
4381
4382         ++vcpu->stat.io_exits;
4383
4384         if (string || in)
4385                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4386
4387         port = exit_qualification >> 16;
4388         size = (exit_qualification & 7) + 1;
4389         skip_emulated_instruction(vcpu);
4390
4391         return kvm_fast_pio_out(vcpu, size, port);
4392 }
4393
4394 static void
4395 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4396 {
4397         /*
4398          * Patch in the VMCALL instruction:
4399          */
4400         hypercall[0] = 0x0f;
4401         hypercall[1] = 0x01;
4402         hypercall[2] = 0xc1;
4403 }
4404
4405 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4406 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4407 {
4408         if (to_vmx(vcpu)->nested.vmxon &&
4409             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4410                 return 1;
4411
4412         if (is_guest_mode(vcpu)) {
4413                 /*
4414                  * We get here when L2 changed cr0 in a way that did not change
4415                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4416                  * but did change L0 shadowed bits. This can currently happen
4417                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4418                  * loading) while pretending to allow the guest to change it.
4419                  */
4420                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4421                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4422                         return 1;
4423                 vmcs_writel(CR0_READ_SHADOW, val);
4424                 return 0;
4425         } else
4426                 return kvm_set_cr0(vcpu, val);
4427 }
4428
4429 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4430 {
4431         if (is_guest_mode(vcpu)) {
4432                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4433                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4434                         return 1;
4435                 vmcs_writel(CR4_READ_SHADOW, val);
4436                 return 0;
4437         } else
4438                 return kvm_set_cr4(vcpu, val);
4439 }
4440
4441 /* called to set cr0 as approriate for clts instruction exit. */
4442 static void handle_clts(struct kvm_vcpu *vcpu)
4443 {
4444         if (is_guest_mode(vcpu)) {
4445                 /*
4446                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4447                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4448                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4449                  */
4450                 vmcs_writel(CR0_READ_SHADOW,
4451                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4452                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4453         } else
4454                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4455 }
4456
4457 static int handle_cr(struct kvm_vcpu *vcpu)
4458 {
4459         unsigned long exit_qualification, val;
4460         int cr;
4461         int reg;
4462         int err;
4463
4464         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4465         cr = exit_qualification & 15;
4466         reg = (exit_qualification >> 8) & 15;
4467         switch ((exit_qualification >> 4) & 3) {
4468         case 0: /* mov to cr */
4469                 val = kvm_register_read(vcpu, reg);
4470                 trace_kvm_cr_write(cr, val);
4471                 switch (cr) {
4472                 case 0:
4473                         err = handle_set_cr0(vcpu, val);
4474                         kvm_complete_insn_gp(vcpu, err);
4475                         return 1;
4476                 case 3:
4477                         err = kvm_set_cr3(vcpu, val);
4478                         kvm_complete_insn_gp(vcpu, err);
4479                         return 1;
4480                 case 4:
4481                         err = handle_set_cr4(vcpu, val);
4482                         kvm_complete_insn_gp(vcpu, err);
4483                         return 1;
4484                 case 8: {
4485                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4486                                 u8 cr8 = kvm_register_read(vcpu, reg);
4487                                 err = kvm_set_cr8(vcpu, cr8);
4488                                 kvm_complete_insn_gp(vcpu, err);
4489                                 if (irqchip_in_kernel(vcpu->kvm))
4490                                         return 1;
4491                                 if (cr8_prev <= cr8)
4492                                         return 1;
4493                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4494                                 return 0;
4495                         }
4496                 };
4497                 break;
4498         case 2: /* clts */
4499                 handle_clts(vcpu);
4500                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4501                 skip_emulated_instruction(vcpu);
4502                 vmx_fpu_activate(vcpu);
4503                 return 1;
4504         case 1: /*mov from cr*/
4505                 switch (cr) {
4506                 case 3:
4507                         val = kvm_read_cr3(vcpu);
4508                         kvm_register_write(vcpu, reg, val);
4509                         trace_kvm_cr_read(cr, val);
4510                         skip_emulated_instruction(vcpu);
4511                         return 1;
4512                 case 8:
4513                         val = kvm_get_cr8(vcpu);
4514                         kvm_register_write(vcpu, reg, val);
4515                         trace_kvm_cr_read(cr, val);
4516                         skip_emulated_instruction(vcpu);
4517                         return 1;
4518                 }
4519                 break;
4520         case 3: /* lmsw */
4521                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4522                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4523                 kvm_lmsw(vcpu, val);
4524
4525                 skip_emulated_instruction(vcpu);
4526                 return 1;
4527         default:
4528                 break;
4529         }
4530         vcpu->run->exit_reason = 0;
4531         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4532                (int)(exit_qualification >> 4) & 3, cr);
4533         return 0;
4534 }
4535
4536 static int handle_dr(struct kvm_vcpu *vcpu)
4537 {
4538         unsigned long exit_qualification;
4539         int dr, reg;
4540
4541         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4542         if (!kvm_require_cpl(vcpu, 0))
4543                 return 1;
4544         dr = vmcs_readl(GUEST_DR7);
4545         if (dr & DR7_GD) {
4546                 /*
4547                  * As the vm-exit takes precedence over the debug trap, we
4548                  * need to emulate the latter, either for the host or the
4549                  * guest debugging itself.
4550                  */
4551                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4552                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4553                         vcpu->run->debug.arch.dr7 = dr;
4554                         vcpu->run->debug.arch.pc =
4555                                 vmcs_readl(GUEST_CS_BASE) +
4556                                 vmcs_readl(GUEST_RIP);
4557                         vcpu->run->debug.arch.exception = DB_VECTOR;
4558                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4559                         return 0;
4560                 } else {
4561                         vcpu->arch.dr7 &= ~DR7_GD;
4562                         vcpu->arch.dr6 |= DR6_BD;
4563                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4564                         kvm_queue_exception(vcpu, DB_VECTOR);
4565                         return 1;
4566                 }
4567         }
4568
4569         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4570         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4571         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4572         if (exit_qualification & TYPE_MOV_FROM_DR) {
4573                 unsigned long val;
4574                 if (!kvm_get_dr(vcpu, dr, &val))
4575                         kvm_register_write(vcpu, reg, val);
4576         } else
4577                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4578         skip_emulated_instruction(vcpu);
4579         return 1;
4580 }
4581
4582 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4583 {
4584         vmcs_writel(GUEST_DR7, val);
4585 }
4586
4587 static int handle_cpuid(struct kvm_vcpu *vcpu)
4588 {
4589         kvm_emulate_cpuid(vcpu);
4590         return 1;
4591 }
4592
4593 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4594 {
4595         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4596         u64 data;
4597
4598         if (vmx_get_msr(vcpu, ecx, &data)) {
4599                 trace_kvm_msr_read_ex(ecx);
4600                 kvm_inject_gp(vcpu, 0);
4601                 return 1;
4602         }
4603
4604         trace_kvm_msr_read(ecx, data);
4605
4606         /* FIXME: handling of bits 32:63 of rax, rdx */
4607         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4608         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4609         skip_emulated_instruction(vcpu);
4610         return 1;
4611 }
4612
4613 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4614 {
4615         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4616         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4617                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4618
4619         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4620                 trace_kvm_msr_write_ex(ecx, data);
4621                 kvm_inject_gp(vcpu, 0);
4622                 return 1;
4623         }
4624
4625         trace_kvm_msr_write(ecx, data);
4626         skip_emulated_instruction(vcpu);
4627         return 1;
4628 }
4629
4630 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4631 {
4632         kvm_make_request(KVM_REQ_EVENT, vcpu);
4633         return 1;
4634 }
4635
4636 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4637 {
4638         u32 cpu_based_vm_exec_control;
4639
4640         /* clear pending irq */
4641         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4642         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4643         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4644
4645         kvm_make_request(KVM_REQ_EVENT, vcpu);
4646
4647         ++vcpu->stat.irq_window_exits;
4648
4649         /*
4650          * If the user space waits to inject interrupts, exit as soon as
4651          * possible
4652          */
4653         if (!irqchip_in_kernel(vcpu->kvm) &&
4654             vcpu->run->request_interrupt_window &&
4655             !kvm_cpu_has_interrupt(vcpu)) {
4656                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4657                 return 0;
4658         }
4659         return 1;
4660 }
4661
4662 static int handle_halt(struct kvm_vcpu *vcpu)
4663 {
4664         skip_emulated_instruction(vcpu);
4665         return kvm_emulate_halt(vcpu);
4666 }
4667
4668 static int handle_vmcall(struct kvm_vcpu *vcpu)
4669 {
4670         skip_emulated_instruction(vcpu);
4671         kvm_emulate_hypercall(vcpu);
4672         return 1;
4673 }
4674
4675 static int handle_invd(struct kvm_vcpu *vcpu)
4676 {
4677         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4678 }
4679
4680 static int handle_invlpg(struct kvm_vcpu *vcpu)
4681 {
4682         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4683
4684         kvm_mmu_invlpg(vcpu, exit_qualification);
4685         skip_emulated_instruction(vcpu);
4686         return 1;
4687 }
4688
4689 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4690 {
4691         int err;
4692
4693         err = kvm_rdpmc(vcpu);
4694         kvm_complete_insn_gp(vcpu, err);
4695
4696         return 1;
4697 }
4698
4699 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4700 {
4701         skip_emulated_instruction(vcpu);
4702         kvm_emulate_wbinvd(vcpu);
4703         return 1;
4704 }
4705
4706 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4707 {
4708         u64 new_bv = kvm_read_edx_eax(vcpu);
4709         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4710
4711         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4712                 skip_emulated_instruction(vcpu);
4713         return 1;
4714 }
4715
4716 static int handle_apic_access(struct kvm_vcpu *vcpu)
4717 {
4718         if (likely(fasteoi)) {
4719                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4720                 int access_type, offset;
4721
4722                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4723                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4724                 /*
4725                  * Sane guest uses MOV to write EOI, with written value
4726                  * not cared. So make a short-circuit here by avoiding
4727                  * heavy instruction emulation.
4728                  */
4729                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4730                     (offset == APIC_EOI)) {
4731                         kvm_lapic_set_eoi(vcpu);
4732                         skip_emulated_instruction(vcpu);
4733                         return 1;
4734                 }
4735         }
4736         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4737 }
4738
4739 static int handle_task_switch(struct kvm_vcpu *vcpu)
4740 {
4741         struct vcpu_vmx *vmx = to_vmx(vcpu);
4742         unsigned long exit_qualification;
4743         bool has_error_code = false;
4744         u32 error_code = 0;
4745         u16 tss_selector;
4746         int reason, type, idt_v, idt_index;
4747
4748         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4749         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4750         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4751
4752         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4753
4754         reason = (u32)exit_qualification >> 30;
4755         if (reason == TASK_SWITCH_GATE && idt_v) {
4756                 switch (type) {
4757                 case INTR_TYPE_NMI_INTR:
4758                         vcpu->arch.nmi_injected = false;
4759                         vmx_set_nmi_mask(vcpu, true);
4760                         break;
4761                 case INTR_TYPE_EXT_INTR:
4762                 case INTR_TYPE_SOFT_INTR:
4763                         kvm_clear_interrupt_queue(vcpu);
4764                         break;
4765                 case INTR_TYPE_HARD_EXCEPTION:
4766                         if (vmx->idt_vectoring_info &
4767                             VECTORING_INFO_DELIVER_CODE_MASK) {
4768                                 has_error_code = true;
4769                                 error_code =
4770                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4771                         }
4772                         /* fall through */
4773                 case INTR_TYPE_SOFT_EXCEPTION:
4774                         kvm_clear_exception_queue(vcpu);
4775                         break;
4776                 default:
4777                         break;
4778                 }
4779         }
4780         tss_selector = exit_qualification;
4781
4782         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4783                        type != INTR_TYPE_EXT_INTR &&
4784                        type != INTR_TYPE_NMI_INTR))
4785                 skip_emulated_instruction(vcpu);
4786
4787         if (kvm_task_switch(vcpu, tss_selector,
4788                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4789                             has_error_code, error_code) == EMULATE_FAIL) {
4790                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4791                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4792                 vcpu->run->internal.ndata = 0;
4793                 return 0;
4794         }
4795
4796         /* clear all local breakpoint enable flags */
4797         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4798
4799         /*
4800          * TODO: What about debug traps on tss switch?
4801          *       Are we supposed to inject them and update dr6?
4802          */
4803
4804         return 1;
4805 }
4806
4807 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4808 {
4809         unsigned long exit_qualification;
4810         gpa_t gpa;
4811         int gla_validity;
4812
4813         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4814
4815         if (exit_qualification & (1 << 6)) {
4816                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4817                 return -EINVAL;
4818         }
4819
4820         gla_validity = (exit_qualification >> 7) & 0x3;
4821         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4822                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4823                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4824                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4825                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4826                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4827                         (long unsigned int)exit_qualification);
4828                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4829                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4830                 return 0;
4831         }
4832
4833         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4834         trace_kvm_page_fault(gpa, exit_qualification);
4835         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4836 }
4837
4838 static u64 ept_rsvd_mask(u64 spte, int level)
4839 {
4840         int i;
4841         u64 mask = 0;
4842
4843         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4844                 mask |= (1ULL << i);
4845
4846         if (level > 2)
4847                 /* bits 7:3 reserved */
4848                 mask |= 0xf8;
4849         else if (level == 2) {
4850                 if (spte & (1ULL << 7))
4851                         /* 2MB ref, bits 20:12 reserved */
4852                         mask |= 0x1ff000;
4853                 else
4854                         /* bits 6:3 reserved */
4855                         mask |= 0x78;
4856         }
4857
4858         return mask;
4859 }
4860
4861 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4862                                        int level)
4863 {
4864         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4865
4866         /* 010b (write-only) */
4867         WARN_ON((spte & 0x7) == 0x2);
4868
4869         /* 110b (write/execute) */
4870         WARN_ON((spte & 0x7) == 0x6);
4871
4872         /* 100b (execute-only) and value not supported by logical processor */
4873         if (!cpu_has_vmx_ept_execute_only())
4874                 WARN_ON((spte & 0x7) == 0x4);
4875
4876         /* not 000b */
4877         if ((spte & 0x7)) {
4878                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4879
4880                 if (rsvd_bits != 0) {
4881                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4882                                          __func__, rsvd_bits);
4883                         WARN_ON(1);
4884                 }
4885
4886                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4887                         u64 ept_mem_type = (spte & 0x38) >> 3;
4888
4889                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4890                             ept_mem_type == 7) {
4891                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4892                                                 __func__, ept_mem_type);
4893                                 WARN_ON(1);
4894                         }
4895                 }
4896         }
4897 }
4898
4899 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4900 {
4901         u64 sptes[4];
4902         int nr_sptes, i, ret;
4903         gpa_t gpa;
4904
4905         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4906
4907         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4908         if (likely(ret == 1))
4909                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4910                                               EMULATE_DONE;
4911         if (unlikely(!ret))
4912                 return 1;
4913
4914         /* It is the real ept misconfig */
4915         printk(KERN_ERR "EPT: Misconfiguration.\n");
4916         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4917
4918         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4919
4920         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4921                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4922
4923         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4924         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4925
4926         return 0;
4927 }
4928
4929 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4930 {
4931         u32 cpu_based_vm_exec_control;
4932
4933         /* clear pending NMI */
4934         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4935         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4936         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4937         ++vcpu->stat.nmi_window_exits;
4938         kvm_make_request(KVM_REQ_EVENT, vcpu);
4939
4940         return 1;
4941 }
4942
4943 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4944 {
4945         struct vcpu_vmx *vmx = to_vmx(vcpu);
4946         enum emulation_result err = EMULATE_DONE;
4947         int ret = 1;
4948         u32 cpu_exec_ctrl;
4949         bool intr_window_requested;
4950
4951         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4952         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4953
4954         while (!guest_state_valid(vcpu)) {
4955                 if (intr_window_requested
4956                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4957                         return handle_interrupt_window(&vmx->vcpu);
4958
4959                 err = emulate_instruction(vcpu, 0);
4960
4961                 if (err == EMULATE_DO_MMIO) {
4962                         ret = 0;
4963                         goto out;
4964                 }
4965
4966                 if (err != EMULATE_DONE)
4967                         return 0;
4968
4969                 if (signal_pending(current))
4970                         goto out;
4971                 if (need_resched())
4972                         schedule();
4973         }
4974
4975         vmx->emulation_required = 0;
4976 out:
4977         return ret;
4978 }
4979
4980 /*
4981  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4982  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4983  */
4984 static int handle_pause(struct kvm_vcpu *vcpu)
4985 {
4986         skip_emulated_instruction(vcpu);
4987         kvm_vcpu_on_spin(vcpu);
4988
4989         return 1;
4990 }
4991
4992 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4993 {
4994         kvm_queue_exception(vcpu, UD_VECTOR);
4995         return 1;
4996 }
4997
4998 /*
4999  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5000  * We could reuse a single VMCS for all the L2 guests, but we also want the
5001  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5002  * allows keeping them loaded on the processor, and in the future will allow
5003  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5004  * every entry if they never change.
5005  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5006  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5007  *
5008  * The following functions allocate and free a vmcs02 in this pool.
5009  */
5010
5011 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5012 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5013 {
5014         struct vmcs02_list *item;
5015         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5016                 if (item->vmptr == vmx->nested.current_vmptr) {
5017                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5018                         return &item->vmcs02;
5019                 }
5020
5021         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5022                 /* Recycle the least recently used VMCS. */
5023                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5024                         struct vmcs02_list, list);
5025                 item->vmptr = vmx->nested.current_vmptr;
5026                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5027                 return &item->vmcs02;
5028         }
5029
5030         /* Create a new VMCS */
5031         item = (struct vmcs02_list *)
5032                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5033         if (!item)
5034                 return NULL;
5035         item->vmcs02.vmcs = alloc_vmcs();
5036         if (!item->vmcs02.vmcs) {
5037                 kfree(item);
5038                 return NULL;
5039         }
5040         loaded_vmcs_init(&item->vmcs02);
5041         item->vmptr = vmx->nested.current_vmptr;
5042         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5043         vmx->nested.vmcs02_num++;
5044         return &item->vmcs02;
5045 }
5046
5047 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5048 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5049 {
5050         struct vmcs02_list *item;
5051         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5052                 if (item->vmptr == vmptr) {
5053                         free_loaded_vmcs(&item->vmcs02);
5054                         list_del(&item->list);
5055                         kfree(item);
5056                         vmx->nested.vmcs02_num--;
5057                         return;
5058                 }
5059 }
5060
5061 /*
5062  * Free all VMCSs saved for this vcpu, except the one pointed by
5063  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5064  * currently used, if running L2), and vmcs01 when running L2.
5065  */
5066 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5067 {
5068         struct vmcs02_list *item, *n;
5069         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5070                 if (vmx->loaded_vmcs != &item->vmcs02)
5071                         free_loaded_vmcs(&item->vmcs02);
5072                 list_del(&item->list);
5073                 kfree(item);
5074         }
5075         vmx->nested.vmcs02_num = 0;
5076
5077         if (vmx->loaded_vmcs != &vmx->vmcs01)
5078                 free_loaded_vmcs(&vmx->vmcs01);
5079 }
5080
5081 /*
5082  * Emulate the VMXON instruction.
5083  * Currently, we just remember that VMX is active, and do not save or even
5084  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5085  * do not currently need to store anything in that guest-allocated memory
5086  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5087  * argument is different from the VMXON pointer (which the spec says they do).
5088  */
5089 static int handle_vmon(struct kvm_vcpu *vcpu)
5090 {
5091         struct kvm_segment cs;
5092         struct vcpu_vmx *vmx = to_vmx(vcpu);
5093
5094         /* The Intel VMX Instruction Reference lists a bunch of bits that
5095          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5096          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5097          * Otherwise, we should fail with #UD. We test these now:
5098          */
5099         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5100             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5101             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5102                 kvm_queue_exception(vcpu, UD_VECTOR);
5103                 return 1;
5104         }
5105
5106         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5107         if (is_long_mode(vcpu) && !cs.l) {
5108                 kvm_queue_exception(vcpu, UD_VECTOR);
5109                 return 1;
5110         }
5111
5112         if (vmx_get_cpl(vcpu)) {
5113                 kvm_inject_gp(vcpu, 0);
5114                 return 1;
5115         }
5116
5117         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5118         vmx->nested.vmcs02_num = 0;
5119
5120         vmx->nested.vmxon = true;
5121
5122         skip_emulated_instruction(vcpu);
5123         return 1;
5124 }
5125
5126 /*
5127  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5128  * for running VMX instructions (except VMXON, whose prerequisites are
5129  * slightly different). It also specifies what exception to inject otherwise.
5130  */
5131 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5132 {
5133         struct kvm_segment cs;
5134         struct vcpu_vmx *vmx = to_vmx(vcpu);
5135
5136         if (!vmx->nested.vmxon) {
5137                 kvm_queue_exception(vcpu, UD_VECTOR);
5138                 return 0;
5139         }
5140
5141         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5142         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5143             (is_long_mode(vcpu) && !cs.l)) {
5144                 kvm_queue_exception(vcpu, UD_VECTOR);
5145                 return 0;
5146         }
5147
5148         if (vmx_get_cpl(vcpu)) {
5149                 kvm_inject_gp(vcpu, 0);
5150                 return 0;
5151         }
5152
5153         return 1;
5154 }
5155
5156 /*
5157  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5158  * just stops using VMX.
5159  */
5160 static void free_nested(struct vcpu_vmx *vmx)
5161 {
5162         if (!vmx->nested.vmxon)
5163                 return;
5164         vmx->nested.vmxon = false;
5165         if (vmx->nested.current_vmptr != -1ull) {
5166                 kunmap(vmx->nested.current_vmcs12_page);
5167                 nested_release_page(vmx->nested.current_vmcs12_page);
5168                 vmx->nested.current_vmptr = -1ull;
5169                 vmx->nested.current_vmcs12 = NULL;
5170         }
5171         /* Unpin physical memory we referred to in current vmcs02 */
5172         if (vmx->nested.apic_access_page) {
5173                 nested_release_page(vmx->nested.apic_access_page);
5174                 vmx->nested.apic_access_page = 0;
5175         }
5176
5177         nested_free_all_saved_vmcss(vmx);
5178 }
5179
5180 /* Emulate the VMXOFF instruction */
5181 static int handle_vmoff(struct kvm_vcpu *vcpu)
5182 {
5183         if (!nested_vmx_check_permission(vcpu))
5184                 return 1;
5185         free_nested(to_vmx(vcpu));
5186         skip_emulated_instruction(vcpu);
5187         return 1;
5188 }
5189
5190 /*
5191  * Decode the memory-address operand of a vmx instruction, as recorded on an
5192  * exit caused by such an instruction (run by a guest hypervisor).
5193  * On success, returns 0. When the operand is invalid, returns 1 and throws
5194  * #UD or #GP.
5195  */
5196 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5197                                  unsigned long exit_qualification,
5198                                  u32 vmx_instruction_info, gva_t *ret)
5199 {
5200         /*
5201          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5202          * Execution", on an exit, vmx_instruction_info holds most of the
5203          * addressing components of the operand. Only the displacement part
5204          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5205          * For how an actual address is calculated from all these components,
5206          * refer to Vol. 1, "Operand Addressing".
5207          */
5208         int  scaling = vmx_instruction_info & 3;
5209         int  addr_size = (vmx_instruction_info >> 7) & 7;
5210         bool is_reg = vmx_instruction_info & (1u << 10);
5211         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5212         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5213         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5214         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5215         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5216
5217         if (is_reg) {
5218                 kvm_queue_exception(vcpu, UD_VECTOR);
5219                 return 1;
5220         }
5221
5222         /* Addr = segment_base + offset */
5223         /* offset = base + [index * scale] + displacement */
5224         *ret = vmx_get_segment_base(vcpu, seg_reg);
5225         if (base_is_valid)
5226                 *ret += kvm_register_read(vcpu, base_reg);
5227         if (index_is_valid)
5228                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5229         *ret += exit_qualification; /* holds the displacement */
5230
5231         if (addr_size == 1) /* 32 bit */
5232                 *ret &= 0xffffffff;
5233
5234         /*
5235          * TODO: throw #GP (and return 1) in various cases that the VM*
5236          * instructions require it - e.g., offset beyond segment limit,
5237          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5238          * address, and so on. Currently these are not checked.
5239          */
5240         return 0;
5241 }
5242
5243 /*
5244  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5245  * set the success or error code of an emulated VMX instruction, as specified
5246  * by Vol 2B, VMX Instruction Reference, "Conventions".
5247  */
5248 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5249 {
5250         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5251                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5252                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5253 }
5254
5255 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5256 {
5257         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5258                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5259                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5260                         | X86_EFLAGS_CF);
5261 }
5262
5263 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5264                                         u32 vm_instruction_error)
5265 {
5266         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5267                 /*
5268                  * failValid writes the error number to the current VMCS, which
5269                  * can't be done there isn't a current VMCS.
5270                  */
5271                 nested_vmx_failInvalid(vcpu);
5272                 return;
5273         }
5274         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5275                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5276                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5277                         | X86_EFLAGS_ZF);
5278         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5279 }
5280
5281 /* Emulate the VMCLEAR instruction */
5282 static int handle_vmclear(struct kvm_vcpu *vcpu)
5283 {
5284         struct vcpu_vmx *vmx = to_vmx(vcpu);
5285         gva_t gva;
5286         gpa_t vmptr;
5287         struct vmcs12 *vmcs12;
5288         struct page *page;
5289         struct x86_exception e;
5290
5291         if (!nested_vmx_check_permission(vcpu))
5292                 return 1;
5293
5294         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5295                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5296                 return 1;
5297
5298         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5299                                 sizeof(vmptr), &e)) {
5300                 kvm_inject_page_fault(vcpu, &e);
5301                 return 1;
5302         }
5303
5304         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5305                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5306                 skip_emulated_instruction(vcpu);
5307                 return 1;
5308         }
5309
5310         if (vmptr == vmx->nested.current_vmptr) {
5311                 kunmap(vmx->nested.current_vmcs12_page);
5312                 nested_release_page(vmx->nested.current_vmcs12_page);
5313                 vmx->nested.current_vmptr = -1ull;
5314                 vmx->nested.current_vmcs12 = NULL;
5315         }
5316
5317         page = nested_get_page(vcpu, vmptr);
5318         if (page == NULL) {
5319                 /*
5320                  * For accurate processor emulation, VMCLEAR beyond available
5321                  * physical memory should do nothing at all. However, it is
5322                  * possible that a nested vmx bug, not a guest hypervisor bug,
5323                  * resulted in this case, so let's shut down before doing any
5324                  * more damage:
5325                  */
5326                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5327                 return 1;
5328         }
5329         vmcs12 = kmap(page);
5330         vmcs12->launch_state = 0;
5331         kunmap(page);
5332         nested_release_page(page);
5333
5334         nested_free_vmcs02(vmx, vmptr);
5335
5336         skip_emulated_instruction(vcpu);
5337         nested_vmx_succeed(vcpu);
5338         return 1;
5339 }
5340
5341 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5342
5343 /* Emulate the VMLAUNCH instruction */
5344 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5345 {
5346         return nested_vmx_run(vcpu, true);
5347 }
5348
5349 /* Emulate the VMRESUME instruction */
5350 static int handle_vmresume(struct kvm_vcpu *vcpu)
5351 {
5352
5353         return nested_vmx_run(vcpu, false);
5354 }
5355
5356 enum vmcs_field_type {
5357         VMCS_FIELD_TYPE_U16 = 0,
5358         VMCS_FIELD_TYPE_U64 = 1,
5359         VMCS_FIELD_TYPE_U32 = 2,
5360         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5361 };
5362
5363 static inline int vmcs_field_type(unsigned long field)
5364 {
5365         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5366                 return VMCS_FIELD_TYPE_U32;
5367         return (field >> 13) & 0x3 ;
5368 }
5369
5370 static inline int vmcs_field_readonly(unsigned long field)
5371 {
5372         return (((field >> 10) & 0x3) == 1);
5373 }
5374
5375 /*
5376  * Read a vmcs12 field. Since these can have varying lengths and we return
5377  * one type, we chose the biggest type (u64) and zero-extend the return value
5378  * to that size. Note that the caller, handle_vmread, might need to use only
5379  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5380  * 64-bit fields are to be returned).
5381  */
5382 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5383                                         unsigned long field, u64 *ret)
5384 {
5385         short offset = vmcs_field_to_offset(field);
5386         char *p;
5387
5388         if (offset < 0)
5389                 return 0;
5390
5391         p = ((char *)(get_vmcs12(vcpu))) + offset;
5392
5393         switch (vmcs_field_type(field)) {
5394         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5395                 *ret = *((natural_width *)p);
5396                 return 1;
5397         case VMCS_FIELD_TYPE_U16:
5398                 *ret = *((u16 *)p);
5399                 return 1;
5400         case VMCS_FIELD_TYPE_U32:
5401                 *ret = *((u32 *)p);
5402                 return 1;
5403         case VMCS_FIELD_TYPE_U64:
5404                 *ret = *((u64 *)p);
5405                 return 1;
5406         default:
5407                 return 0; /* can never happen. */
5408         }
5409 }
5410
5411 /*
5412  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5413  * used before) all generate the same failure when it is missing.
5414  */
5415 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5416 {
5417         struct vcpu_vmx *vmx = to_vmx(vcpu);
5418         if (vmx->nested.current_vmptr == -1ull) {
5419                 nested_vmx_failInvalid(vcpu);
5420                 skip_emulated_instruction(vcpu);
5421                 return 0;
5422         }
5423         return 1;
5424 }
5425
5426 static int handle_vmread(struct kvm_vcpu *vcpu)
5427 {
5428         unsigned long field;
5429         u64 field_value;
5430         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5431         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5432         gva_t gva = 0;
5433
5434         if (!nested_vmx_check_permission(vcpu) ||
5435             !nested_vmx_check_vmcs12(vcpu))
5436                 return 1;
5437
5438         /* Decode instruction info and find the field to read */
5439         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5440         /* Read the field, zero-extended to a u64 field_value */
5441         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5442                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5443                 skip_emulated_instruction(vcpu);
5444                 return 1;
5445         }
5446         /*
5447          * Now copy part of this value to register or memory, as requested.
5448          * Note that the number of bits actually copied is 32 or 64 depending
5449          * on the guest's mode (32 or 64 bit), not on the given field's length.
5450          */
5451         if (vmx_instruction_info & (1u << 10)) {
5452                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5453                         field_value);
5454         } else {
5455                 if (get_vmx_mem_address(vcpu, exit_qualification,
5456                                 vmx_instruction_info, &gva))
5457                         return 1;
5458                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5459                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5460                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5461         }
5462
5463         nested_vmx_succeed(vcpu);
5464         skip_emulated_instruction(vcpu);
5465         return 1;
5466 }
5467
5468
5469 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5470 {
5471         unsigned long field;
5472         gva_t gva;
5473         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5474         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5475         char *p;
5476         short offset;
5477         /* The value to write might be 32 or 64 bits, depending on L1's long
5478          * mode, and eventually we need to write that into a field of several
5479          * possible lengths. The code below first zero-extends the value to 64
5480          * bit (field_value), and then copies only the approriate number of
5481          * bits into the vmcs12 field.
5482          */
5483         u64 field_value = 0;
5484         struct x86_exception e;
5485
5486         if (!nested_vmx_check_permission(vcpu) ||
5487             !nested_vmx_check_vmcs12(vcpu))
5488                 return 1;
5489
5490         if (vmx_instruction_info & (1u << 10))
5491                 field_value = kvm_register_read(vcpu,
5492                         (((vmx_instruction_info) >> 3) & 0xf));
5493         else {
5494                 if (get_vmx_mem_address(vcpu, exit_qualification,
5495                                 vmx_instruction_info, &gva))
5496                         return 1;
5497                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5498                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5499                         kvm_inject_page_fault(vcpu, &e);
5500                         return 1;
5501                 }
5502         }
5503
5504
5505         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5506         if (vmcs_field_readonly(field)) {
5507                 nested_vmx_failValid(vcpu,
5508                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5509                 skip_emulated_instruction(vcpu);
5510                 return 1;
5511         }
5512
5513         offset = vmcs_field_to_offset(field);
5514         if (offset < 0) {
5515                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5516                 skip_emulated_instruction(vcpu);
5517                 return 1;
5518         }
5519         p = ((char *) get_vmcs12(vcpu)) + offset;
5520
5521         switch (vmcs_field_type(field)) {
5522         case VMCS_FIELD_TYPE_U16:
5523                 *(u16 *)p = field_value;
5524                 break;
5525         case VMCS_FIELD_TYPE_U32:
5526                 *(u32 *)p = field_value;
5527                 break;
5528         case VMCS_FIELD_TYPE_U64:
5529                 *(u64 *)p = field_value;
5530                 break;
5531         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5532                 *(natural_width *)p = field_value;
5533                 break;
5534         default:
5535                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5536                 skip_emulated_instruction(vcpu);
5537                 return 1;
5538         }
5539
5540         nested_vmx_succeed(vcpu);
5541         skip_emulated_instruction(vcpu);
5542         return 1;
5543 }
5544
5545 /* Emulate the VMPTRLD instruction */
5546 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5547 {
5548         struct vcpu_vmx *vmx = to_vmx(vcpu);
5549         gva_t gva;
5550         gpa_t vmptr;
5551         struct x86_exception e;
5552
5553         if (!nested_vmx_check_permission(vcpu))
5554                 return 1;
5555
5556         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5557                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5558                 return 1;
5559
5560         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5561                                 sizeof(vmptr), &e)) {
5562                 kvm_inject_page_fault(vcpu, &e);
5563                 return 1;
5564         }
5565
5566         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5567                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5568                 skip_emulated_instruction(vcpu);
5569                 return 1;
5570         }
5571
5572         if (vmx->nested.current_vmptr != vmptr) {
5573                 struct vmcs12 *new_vmcs12;
5574                 struct page *page;
5575                 page = nested_get_page(vcpu, vmptr);
5576                 if (page == NULL) {
5577                         nested_vmx_failInvalid(vcpu);
5578                         skip_emulated_instruction(vcpu);
5579                         return 1;
5580                 }
5581                 new_vmcs12 = kmap(page);
5582                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5583                         kunmap(page);
5584                         nested_release_page_clean(page);
5585                         nested_vmx_failValid(vcpu,
5586                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5587                         skip_emulated_instruction(vcpu);
5588                         return 1;
5589                 }
5590                 if (vmx->nested.current_vmptr != -1ull) {
5591                         kunmap(vmx->nested.current_vmcs12_page);
5592                         nested_release_page(vmx->nested.current_vmcs12_page);
5593                 }
5594
5595                 vmx->nested.current_vmptr = vmptr;
5596                 vmx->nested.current_vmcs12 = new_vmcs12;
5597                 vmx->nested.current_vmcs12_page = page;
5598         }
5599
5600         nested_vmx_succeed(vcpu);
5601         skip_emulated_instruction(vcpu);
5602         return 1;
5603 }
5604
5605 /* Emulate the VMPTRST instruction */
5606 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5607 {
5608         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5609         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5610         gva_t vmcs_gva;
5611         struct x86_exception e;
5612
5613         if (!nested_vmx_check_permission(vcpu))
5614                 return 1;
5615
5616         if (get_vmx_mem_address(vcpu, exit_qualification,
5617                         vmx_instruction_info, &vmcs_gva))
5618                 return 1;
5619         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5620         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5621                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5622                                  sizeof(u64), &e)) {
5623                 kvm_inject_page_fault(vcpu, &e);
5624                 return 1;
5625         }
5626         nested_vmx_succeed(vcpu);
5627         skip_emulated_instruction(vcpu);
5628         return 1;
5629 }
5630
5631 /*
5632  * The exit handlers return 1 if the exit was handled fully and guest execution
5633  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5634  * to be done to userspace and return 0.
5635  */
5636 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5637         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5638         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5639         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5640         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5641         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5642         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5643         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5644         [EXIT_REASON_CPUID]                   = handle_cpuid,
5645         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5646         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5647         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5648         [EXIT_REASON_HLT]                     = handle_halt,
5649         [EXIT_REASON_INVD]                    = handle_invd,
5650         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5651         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5652         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5653         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5654         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5655         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5656         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5657         [EXIT_REASON_VMREAD]                  = handle_vmread,
5658         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5659         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5660         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5661         [EXIT_REASON_VMON]                    = handle_vmon,
5662         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5663         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5664         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5665         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5666         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5667         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5668         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5669         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5670         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5671         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5672         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5673 };
5674
5675 static const int kvm_vmx_max_exit_handlers =
5676         ARRAY_SIZE(kvm_vmx_exit_handlers);
5677
5678 /*
5679  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5680  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5681  * disinterest in the current event (read or write a specific MSR) by using an
5682  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5683  */
5684 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5685         struct vmcs12 *vmcs12, u32 exit_reason)
5686 {
5687         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5688         gpa_t bitmap;
5689
5690         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5691                 return 1;
5692
5693         /*
5694          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5695          * for the four combinations of read/write and low/high MSR numbers.
5696          * First we need to figure out which of the four to use:
5697          */
5698         bitmap = vmcs12->msr_bitmap;
5699         if (exit_reason == EXIT_REASON_MSR_WRITE)
5700                 bitmap += 2048;
5701         if (msr_index >= 0xc0000000) {
5702                 msr_index -= 0xc0000000;
5703                 bitmap += 1024;
5704         }
5705
5706         /* Then read the msr_index'th bit from this bitmap: */
5707         if (msr_index < 1024*8) {
5708                 unsigned char b;
5709                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5710                 return 1 & (b >> (msr_index & 7));
5711         } else
5712                 return 1; /* let L1 handle the wrong parameter */
5713 }
5714
5715 /*
5716  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5717  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5718  * intercept (via guest_host_mask etc.) the current event.
5719  */
5720 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5721         struct vmcs12 *vmcs12)
5722 {
5723         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5724         int cr = exit_qualification & 15;
5725         int reg = (exit_qualification >> 8) & 15;
5726         unsigned long val = kvm_register_read(vcpu, reg);
5727
5728         switch ((exit_qualification >> 4) & 3) {
5729         case 0: /* mov to cr */
5730                 switch (cr) {
5731                 case 0:
5732                         if (vmcs12->cr0_guest_host_mask &
5733                             (val ^ vmcs12->cr0_read_shadow))
5734                                 return 1;
5735                         break;
5736                 case 3:
5737                         if ((vmcs12->cr3_target_count >= 1 &&
5738                                         vmcs12->cr3_target_value0 == val) ||
5739                                 (vmcs12->cr3_target_count >= 2 &&
5740                                         vmcs12->cr3_target_value1 == val) ||
5741                                 (vmcs12->cr3_target_count >= 3 &&
5742                                         vmcs12->cr3_target_value2 == val) ||
5743                                 (vmcs12->cr3_target_count >= 4 &&
5744                                         vmcs12->cr3_target_value3 == val))
5745                                 return 0;
5746                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5747                                 return 1;
5748                         break;
5749                 case 4:
5750                         if (vmcs12->cr4_guest_host_mask &
5751                             (vmcs12->cr4_read_shadow ^ val))
5752                                 return 1;
5753                         break;
5754                 case 8:
5755                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5756                                 return 1;
5757                         break;
5758                 }
5759                 break;
5760         case 2: /* clts */
5761                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5762                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5763                         return 1;
5764                 break;
5765         case 1: /* mov from cr */
5766                 switch (cr) {
5767                 case 3:
5768                         if (vmcs12->cpu_based_vm_exec_control &
5769                             CPU_BASED_CR3_STORE_EXITING)
5770                                 return 1;
5771                         break;
5772                 case 8:
5773                         if (vmcs12->cpu_based_vm_exec_control &
5774                             CPU_BASED_CR8_STORE_EXITING)
5775                                 return 1;
5776                         break;
5777                 }
5778                 break;
5779         case 3: /* lmsw */
5780                 /*
5781                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5782                  * cr0. Other attempted changes are ignored, with no exit.
5783                  */
5784                 if (vmcs12->cr0_guest_host_mask & 0xe &
5785                     (val ^ vmcs12->cr0_read_shadow))
5786                         return 1;
5787                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5788                     !(vmcs12->cr0_read_shadow & 0x1) &&
5789                     (val & 0x1))
5790                         return 1;
5791                 break;
5792         }
5793         return 0;
5794 }
5795
5796 /*
5797  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5798  * should handle it ourselves in L0 (and then continue L2). Only call this
5799  * when in is_guest_mode (L2).
5800  */
5801 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5802 {
5803         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5804         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5805         struct vcpu_vmx *vmx = to_vmx(vcpu);
5806         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5807
5808         if (vmx->nested.nested_run_pending)
5809                 return 0;
5810
5811         if (unlikely(vmx->fail)) {
5812                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5813                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5814                 return 1;
5815         }
5816
5817         switch (exit_reason) {
5818         case EXIT_REASON_EXCEPTION_NMI:
5819                 if (!is_exception(intr_info))
5820                         return 0;
5821                 else if (is_page_fault(intr_info))
5822                         return enable_ept;
5823                 return vmcs12->exception_bitmap &
5824                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5825         case EXIT_REASON_EXTERNAL_INTERRUPT:
5826                 return 0;
5827         case EXIT_REASON_TRIPLE_FAULT:
5828                 return 1;
5829         case EXIT_REASON_PENDING_INTERRUPT:
5830         case EXIT_REASON_NMI_WINDOW:
5831                 /*
5832                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5833                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5834                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5835                  * Same for NMI Window Exiting.
5836                  */
5837                 return 1;
5838         case EXIT_REASON_TASK_SWITCH:
5839                 return 1;
5840         case EXIT_REASON_CPUID:
5841                 return 1;
5842         case EXIT_REASON_HLT:
5843                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5844         case EXIT_REASON_INVD:
5845                 return 1;
5846         case EXIT_REASON_INVLPG:
5847                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5848         case EXIT_REASON_RDPMC:
5849                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5850         case EXIT_REASON_RDTSC:
5851                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5852         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5853         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5854         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5855         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5856         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5857                 /*
5858                  * VMX instructions trap unconditionally. This allows L1 to
5859                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5860                  */
5861                 return 1;
5862         case EXIT_REASON_CR_ACCESS:
5863                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5864         case EXIT_REASON_DR_ACCESS:
5865                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5866         case EXIT_REASON_IO_INSTRUCTION:
5867                 /* TODO: support IO bitmaps */
5868                 return 1;
5869         case EXIT_REASON_MSR_READ:
5870         case EXIT_REASON_MSR_WRITE:
5871                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5872         case EXIT_REASON_INVALID_STATE:
5873                 return 1;
5874         case EXIT_REASON_MWAIT_INSTRUCTION:
5875                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5876         case EXIT_REASON_MONITOR_INSTRUCTION:
5877                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5878         case EXIT_REASON_PAUSE_INSTRUCTION:
5879                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5880                         nested_cpu_has2(vmcs12,
5881                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5882         case EXIT_REASON_MCE_DURING_VMENTRY:
5883                 return 0;
5884         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5885                 return 1;
5886         case EXIT_REASON_APIC_ACCESS:
5887                 return nested_cpu_has2(vmcs12,
5888                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5889         case EXIT_REASON_EPT_VIOLATION:
5890         case EXIT_REASON_EPT_MISCONFIG:
5891                 return 0;
5892         case EXIT_REASON_WBINVD:
5893                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5894         case EXIT_REASON_XSETBV:
5895                 return 1;
5896         default:
5897                 return 1;
5898         }
5899 }
5900
5901 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5902 {
5903         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5904         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5905 }
5906
5907 /*
5908  * The guest has exited.  See if we can fix it or if we need userspace
5909  * assistance.
5910  */
5911 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5912 {
5913         struct vcpu_vmx *vmx = to_vmx(vcpu);
5914         u32 exit_reason = vmx->exit_reason;
5915         u32 vectoring_info = vmx->idt_vectoring_info;
5916
5917         /* If guest state is invalid, start emulating */
5918         if (vmx->emulation_required && emulate_invalid_guest_state)
5919                 return handle_invalid_guest_state(vcpu);
5920
5921         /*
5922          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5923          * we did not inject a still-pending event to L1 now because of
5924          * nested_run_pending, we need to re-enable this bit.
5925          */
5926         if (vmx->nested.nested_run_pending)
5927                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5928
5929         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5930             exit_reason == EXIT_REASON_VMRESUME))
5931                 vmx->nested.nested_run_pending = 1;
5932         else
5933                 vmx->nested.nested_run_pending = 0;
5934
5935         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5936                 nested_vmx_vmexit(vcpu);
5937                 return 1;
5938         }
5939
5940         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5941                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5942                 vcpu->run->fail_entry.hardware_entry_failure_reason
5943                         = exit_reason;
5944                 return 0;
5945         }
5946
5947         if (unlikely(vmx->fail)) {
5948                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5949                 vcpu->run->fail_entry.hardware_entry_failure_reason
5950                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5951                 return 0;
5952         }
5953
5954         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5955                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5956                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5957                         exit_reason != EXIT_REASON_TASK_SWITCH))
5958                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5959                        "(0x%x) and exit reason is 0x%x\n",
5960                        __func__, vectoring_info, exit_reason);
5961
5962         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5963             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5964                                         get_vmcs12(vcpu), vcpu)))) {
5965                 if (vmx_interrupt_allowed(vcpu)) {
5966                         vmx->soft_vnmi_blocked = 0;
5967                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5968                            vcpu->arch.nmi_pending) {
5969                         /*
5970                          * This CPU don't support us in finding the end of an
5971                          * NMI-blocked window if the guest runs with IRQs
5972                          * disabled. So we pull the trigger after 1 s of
5973                          * futile waiting, but inform the user about this.
5974                          */
5975                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5976                                "state on VCPU %d after 1 s timeout\n",
5977                                __func__, vcpu->vcpu_id);
5978                         vmx->soft_vnmi_blocked = 0;
5979                 }
5980         }
5981
5982         if (exit_reason < kvm_vmx_max_exit_handlers
5983             && kvm_vmx_exit_handlers[exit_reason])
5984                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5985         else {
5986                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5987                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5988         }
5989         return 0;
5990 }
5991
5992 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5993 {
5994         if (irr == -1 || tpr < irr) {
5995                 vmcs_write32(TPR_THRESHOLD, 0);
5996                 return;
5997         }
5998
5999         vmcs_write32(TPR_THRESHOLD, irr);
6000 }
6001
6002 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6003 {
6004         u32 exit_intr_info;
6005
6006         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6007               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6008                 return;
6009
6010         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6011         exit_intr_info = vmx->exit_intr_info;
6012
6013         /* Handle machine checks before interrupts are enabled */
6014         if (is_machine_check(exit_intr_info))
6015                 kvm_machine_check();
6016
6017         /* We need to handle NMIs before interrupts are enabled */
6018         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6019             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6020                 kvm_before_handle_nmi(&vmx->vcpu);
6021                 asm("int $2");
6022                 kvm_after_handle_nmi(&vmx->vcpu);
6023         }
6024 }
6025
6026 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6027 {
6028         u32 exit_intr_info;
6029         bool unblock_nmi;
6030         u8 vector;
6031         bool idtv_info_valid;
6032
6033         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6034
6035         if (cpu_has_virtual_nmis()) {
6036                 if (vmx->nmi_known_unmasked)
6037                         return;
6038                 /*
6039                  * Can't use vmx->exit_intr_info since we're not sure what
6040                  * the exit reason is.
6041                  */
6042                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6043                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6044                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6045                 /*
6046                  * SDM 3: 27.7.1.2 (September 2008)
6047                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6048                  * a guest IRET fault.
6049                  * SDM 3: 23.2.2 (September 2008)
6050                  * Bit 12 is undefined in any of the following cases:
6051                  *  If the VM exit sets the valid bit in the IDT-vectoring
6052                  *   information field.
6053                  *  If the VM exit is due to a double fault.
6054                  */
6055                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6056                     vector != DF_VECTOR && !idtv_info_valid)
6057                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6058                                       GUEST_INTR_STATE_NMI);
6059                 else
6060                         vmx->nmi_known_unmasked =
6061                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6062                                   & GUEST_INTR_STATE_NMI);
6063         } else if (unlikely(vmx->soft_vnmi_blocked))
6064                 vmx->vnmi_blocked_time +=
6065                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6066 }
6067
6068 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6069                                       u32 idt_vectoring_info,
6070                                       int instr_len_field,
6071                                       int error_code_field)
6072 {
6073         u8 vector;
6074         int type;
6075         bool idtv_info_valid;
6076
6077         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6078
6079         vmx->vcpu.arch.nmi_injected = false;
6080         kvm_clear_exception_queue(&vmx->vcpu);
6081         kvm_clear_interrupt_queue(&vmx->vcpu);
6082
6083         if (!idtv_info_valid)
6084                 return;
6085
6086         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6087
6088         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6089         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6090
6091         switch (type) {
6092         case INTR_TYPE_NMI_INTR:
6093                 vmx->vcpu.arch.nmi_injected = true;
6094                 /*
6095                  * SDM 3: 27.7.1.2 (September 2008)
6096                  * Clear bit "block by NMI" before VM entry if a NMI
6097                  * delivery faulted.
6098                  */
6099                 vmx_set_nmi_mask(&vmx->vcpu, false);
6100                 break;
6101         case INTR_TYPE_SOFT_EXCEPTION:
6102                 vmx->vcpu.arch.event_exit_inst_len =
6103                         vmcs_read32(instr_len_field);
6104                 /* fall through */
6105         case INTR_TYPE_HARD_EXCEPTION:
6106                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6107                         u32 err = vmcs_read32(error_code_field);
6108                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6109                 } else
6110                         kvm_queue_exception(&vmx->vcpu, vector);
6111                 break;
6112         case INTR_TYPE_SOFT_INTR:
6113                 vmx->vcpu.arch.event_exit_inst_len =
6114                         vmcs_read32(instr_len_field);
6115                 /* fall through */
6116         case INTR_TYPE_EXT_INTR:
6117                 kvm_queue_interrupt(&vmx->vcpu, vector,
6118                         type == INTR_TYPE_SOFT_INTR);
6119                 break;
6120         default:
6121                 break;
6122         }
6123 }
6124
6125 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6126 {
6127         if (is_guest_mode(&vmx->vcpu))
6128                 return;
6129         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6130                                   VM_EXIT_INSTRUCTION_LEN,
6131                                   IDT_VECTORING_ERROR_CODE);
6132 }
6133
6134 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6135 {
6136         if (is_guest_mode(vcpu))
6137                 return;
6138         __vmx_complete_interrupts(to_vmx(vcpu),
6139                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6140                                   VM_ENTRY_INSTRUCTION_LEN,
6141                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6142
6143         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6144 }
6145
6146 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6147 {
6148         int i, nr_msrs;
6149         struct perf_guest_switch_msr *msrs;
6150
6151         msrs = perf_guest_get_msrs(&nr_msrs);
6152
6153         if (!msrs)
6154                 return;
6155
6156         for (i = 0; i < nr_msrs; i++)
6157                 if (msrs[i].host == msrs[i].guest)
6158                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6159                 else
6160                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6161                                         msrs[i].host);
6162 }
6163
6164 #ifdef CONFIG_X86_64
6165 #define R "r"
6166 #define Q "q"
6167 #else
6168 #define R "e"
6169 #define Q "l"
6170 #endif
6171
6172 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6173 {
6174         struct vcpu_vmx *vmx = to_vmx(vcpu);
6175
6176         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6177                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6178                 if (vmcs12->idt_vectoring_info_field &
6179                                 VECTORING_INFO_VALID_MASK) {
6180                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6181                                 vmcs12->idt_vectoring_info_field);
6182                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6183                                 vmcs12->vm_exit_instruction_len);
6184                         if (vmcs12->idt_vectoring_info_field &
6185                                         VECTORING_INFO_DELIVER_CODE_MASK)
6186                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6187                                         vmcs12->idt_vectoring_error_code);
6188                 }
6189         }
6190
6191         /* Record the guest's net vcpu time for enforced NMI injections. */
6192         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6193                 vmx->entry_time = ktime_get();
6194
6195         /* Don't enter VMX if guest state is invalid, let the exit handler
6196            start emulation until we arrive back to a valid state */
6197         if (vmx->emulation_required && emulate_invalid_guest_state)
6198                 return;
6199
6200         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6201                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6202         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6203                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6204
6205         /* When single-stepping over STI and MOV SS, we must clear the
6206          * corresponding interruptibility bits in the guest state. Otherwise
6207          * vmentry fails as it then expects bit 14 (BS) in pending debug
6208          * exceptions being set, but that's not correct for the guest debugging
6209          * case. */
6210         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6211                 vmx_set_interrupt_shadow(vcpu, 0);
6212
6213         atomic_switch_perf_msrs(vmx);
6214
6215         vmx->__launched = vmx->loaded_vmcs->launched;
6216         asm(
6217                 /* Store host registers */
6218                 "push %%"R"dx; push %%"R"bp;"
6219                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6220                 "push %%"R"cx \n\t"
6221                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6222                 "je 1f \n\t"
6223                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6224                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6225                 "1: \n\t"
6226                 /* Reload cr2 if changed */
6227                 "mov %c[cr2](%0), %%"R"ax \n\t"
6228                 "mov %%cr2, %%"R"dx \n\t"
6229                 "cmp %%"R"ax, %%"R"dx \n\t"
6230                 "je 2f \n\t"
6231                 "mov %%"R"ax, %%cr2 \n\t"
6232                 "2: \n\t"
6233                 /* Check if vmlaunch of vmresume is needed */
6234                 "cmpl $0, %c[launched](%0) \n\t"
6235                 /* Load guest registers.  Don't clobber flags. */
6236                 "mov %c[rax](%0), %%"R"ax \n\t"
6237                 "mov %c[rbx](%0), %%"R"bx \n\t"
6238                 "mov %c[rdx](%0), %%"R"dx \n\t"
6239                 "mov %c[rsi](%0), %%"R"si \n\t"
6240                 "mov %c[rdi](%0), %%"R"di \n\t"
6241                 "mov %c[rbp](%0), %%"R"bp \n\t"
6242 #ifdef CONFIG_X86_64
6243                 "mov %c[r8](%0),  %%r8  \n\t"
6244                 "mov %c[r9](%0),  %%r9  \n\t"
6245                 "mov %c[r10](%0), %%r10 \n\t"
6246                 "mov %c[r11](%0), %%r11 \n\t"
6247                 "mov %c[r12](%0), %%r12 \n\t"
6248                 "mov %c[r13](%0), %%r13 \n\t"
6249                 "mov %c[r14](%0), %%r14 \n\t"
6250                 "mov %c[r15](%0), %%r15 \n\t"
6251 #endif
6252                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6253
6254                 /* Enter guest mode */
6255                 "jne .Llaunched \n\t"
6256                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6257                 "jmp .Lkvm_vmx_return \n\t"
6258                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6259                 ".Lkvm_vmx_return: "
6260                 /* Save guest registers, load host registers, keep flags */
6261                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6262                 "pop %0 \n\t"
6263                 "mov %%"R"ax, %c[rax](%0) \n\t"
6264                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6265                 "pop"Q" %c[rcx](%0) \n\t"
6266                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6267                 "mov %%"R"si, %c[rsi](%0) \n\t"
6268                 "mov %%"R"di, %c[rdi](%0) \n\t"
6269                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6270 #ifdef CONFIG_X86_64
6271                 "mov %%r8,  %c[r8](%0) \n\t"
6272                 "mov %%r9,  %c[r9](%0) \n\t"
6273                 "mov %%r10, %c[r10](%0) \n\t"
6274                 "mov %%r11, %c[r11](%0) \n\t"
6275                 "mov %%r12, %c[r12](%0) \n\t"
6276                 "mov %%r13, %c[r13](%0) \n\t"
6277                 "mov %%r14, %c[r14](%0) \n\t"
6278                 "mov %%r15, %c[r15](%0) \n\t"
6279 #endif
6280                 "mov %%cr2, %%"R"ax   \n\t"
6281                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6282
6283                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6284                 "setbe %c[fail](%0) \n\t"
6285               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6286                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6287                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6288                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6289                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6290                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6291                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6292                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6293                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6294                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6295                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6296 #ifdef CONFIG_X86_64
6297                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6298                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6299                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6300                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6301                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6302                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6303                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6304                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6305 #endif
6306                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6307                 [wordsize]"i"(sizeof(ulong))
6308               : "cc", "memory"
6309                 , R"ax", R"bx", R"di", R"si"
6310 #ifdef CONFIG_X86_64
6311                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6312 #endif
6313               );
6314
6315 #ifndef CONFIG_X86_64
6316         /*
6317          * The sysexit path does not restore ds/es, so we must set them to
6318          * a reasonable value ourselves.
6319          *
6320          * We can't defer this to vmx_load_host_state() since that function
6321          * may be executed in interrupt context, which saves and restore segments
6322          * around it, nullifying its effect.
6323          */
6324         loadsegment(ds, __USER_DS);
6325         loadsegment(es, __USER_DS);
6326 #endif
6327
6328         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6329                                   | (1 << VCPU_EXREG_RFLAGS)
6330                                   | (1 << VCPU_EXREG_CPL)
6331                                   | (1 << VCPU_EXREG_PDPTR)
6332                                   | (1 << VCPU_EXREG_SEGMENTS)
6333                                   | (1 << VCPU_EXREG_CR3));
6334         vcpu->arch.regs_dirty = 0;
6335
6336         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6337
6338         if (is_guest_mode(vcpu)) {
6339                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6340                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6341                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6342                         vmcs12->idt_vectoring_error_code =
6343                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6344                         vmcs12->vm_exit_instruction_len =
6345                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6346                 }
6347         }
6348
6349         vmx->loaded_vmcs->launched = 1;
6350
6351         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6352         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6353
6354         vmx_complete_atomic_exit(vmx);
6355         vmx_recover_nmi_blocking(vmx);
6356         vmx_complete_interrupts(vmx);
6357 }
6358
6359 #undef R
6360 #undef Q
6361
6362 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6363 {
6364         struct vcpu_vmx *vmx = to_vmx(vcpu);
6365
6366         free_vpid(vmx);
6367         free_nested(vmx);
6368         free_loaded_vmcs(vmx->loaded_vmcs);
6369         kfree(vmx->guest_msrs);
6370         kvm_vcpu_uninit(vcpu);
6371         kmem_cache_free(kvm_vcpu_cache, vmx);
6372 }
6373
6374 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6375 {
6376         int err;
6377         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6378         int cpu;
6379
6380         if (!vmx)
6381                 return ERR_PTR(-ENOMEM);
6382
6383         allocate_vpid(vmx);
6384
6385         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6386         if (err)
6387                 goto free_vcpu;
6388
6389         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6390         err = -ENOMEM;
6391         if (!vmx->guest_msrs) {
6392                 goto uninit_vcpu;
6393         }
6394
6395         vmx->loaded_vmcs = &vmx->vmcs01;
6396         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6397         if (!vmx->loaded_vmcs->vmcs)
6398                 goto free_msrs;
6399         if (!vmm_exclusive)
6400                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6401         loaded_vmcs_init(vmx->loaded_vmcs);
6402         if (!vmm_exclusive)
6403                 kvm_cpu_vmxoff();
6404
6405         cpu = get_cpu();
6406         vmx_vcpu_load(&vmx->vcpu, cpu);
6407         vmx->vcpu.cpu = cpu;
6408         err = vmx_vcpu_setup(vmx);
6409         vmx_vcpu_put(&vmx->vcpu);
6410         put_cpu();
6411         if (err)
6412                 goto free_vmcs;
6413         if (vm_need_virtualize_apic_accesses(kvm))
6414                 err = alloc_apic_access_page(kvm);
6415                 if (err)
6416                         goto free_vmcs;
6417
6418         if (enable_ept) {
6419                 if (!kvm->arch.ept_identity_map_addr)
6420                         kvm->arch.ept_identity_map_addr =
6421                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6422                 err = -ENOMEM;
6423                 if (alloc_identity_pagetable(kvm) != 0)
6424                         goto free_vmcs;
6425                 if (!init_rmode_identity_map(kvm))
6426                         goto free_vmcs;
6427         }
6428
6429         vmx->nested.current_vmptr = -1ull;
6430         vmx->nested.current_vmcs12 = NULL;
6431
6432         return &vmx->vcpu;
6433
6434 free_vmcs:
6435         free_loaded_vmcs(vmx->loaded_vmcs);
6436 free_msrs:
6437         kfree(vmx->guest_msrs);
6438 uninit_vcpu:
6439         kvm_vcpu_uninit(&vmx->vcpu);
6440 free_vcpu:
6441         free_vpid(vmx);
6442         kmem_cache_free(kvm_vcpu_cache, vmx);
6443         return ERR_PTR(err);
6444 }
6445
6446 static void __init vmx_check_processor_compat(void *rtn)
6447 {
6448         struct vmcs_config vmcs_conf;
6449
6450         *(int *)rtn = 0;
6451         if (setup_vmcs_config(&vmcs_conf) < 0)
6452                 *(int *)rtn = -EIO;
6453         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6454                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6455                                 smp_processor_id());
6456                 *(int *)rtn = -EIO;
6457         }
6458 }
6459
6460 static int get_ept_level(void)
6461 {
6462         return VMX_EPT_DEFAULT_GAW + 1;
6463 }
6464
6465 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6466 {
6467         u64 ret;
6468
6469         /* For VT-d and EPT combination
6470          * 1. MMIO: always map as UC
6471          * 2. EPT with VT-d:
6472          *   a. VT-d without snooping control feature: can't guarantee the
6473          *      result, try to trust guest.
6474          *   b. VT-d with snooping control feature: snooping control feature of
6475          *      VT-d engine can guarantee the cache correctness. Just set it
6476          *      to WB to keep consistent with host. So the same as item 3.
6477          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6478          *    consistent with host MTRR
6479          */
6480         if (is_mmio)
6481                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6482         else if (vcpu->kvm->arch.iommu_domain &&
6483                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6484                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6485                       VMX_EPT_MT_EPTE_SHIFT;
6486         else
6487                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6488                         | VMX_EPT_IPAT_BIT;
6489
6490         return ret;
6491 }
6492
6493 static int vmx_get_lpage_level(void)
6494 {
6495         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6496                 return PT_DIRECTORY_LEVEL;
6497         else
6498                 /* For shadow and EPT supported 1GB page */
6499                 return PT_PDPE_LEVEL;
6500 }
6501
6502 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6503 {
6504         struct kvm_cpuid_entry2 *best;
6505         struct vcpu_vmx *vmx = to_vmx(vcpu);
6506         u32 exec_control;
6507
6508         vmx->rdtscp_enabled = false;
6509         if (vmx_rdtscp_supported()) {
6510                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6511                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6512                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6513                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6514                                 vmx->rdtscp_enabled = true;
6515                         else {
6516                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6517                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6518                                                 exec_control);
6519                         }
6520                 }
6521         }
6522 }
6523
6524 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6525 {
6526         if (func == 1 && nested)
6527                 entry->ecx |= bit(X86_FEATURE_VMX);
6528 }
6529
6530 /*
6531  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6532  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6533  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6534  * guest in a way that will both be appropriate to L1's requests, and our
6535  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6536  * function also has additional necessary side-effects, like setting various
6537  * vcpu->arch fields.
6538  */
6539 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6540 {
6541         struct vcpu_vmx *vmx = to_vmx(vcpu);
6542         u32 exec_control;
6543
6544         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6545         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6546         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6547         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6548         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6549         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6550         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6551         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6552         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6553         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6554         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6555         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6556         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6557         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6558         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6559         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6560         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6561         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6562         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6563         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6564         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6565         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6566         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6567         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6568         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6569         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6570         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6571         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6572         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6573         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6574         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6575         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6576         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6577         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6578         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6579         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6580
6581         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6582         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6583                 vmcs12->vm_entry_intr_info_field);
6584         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6585                 vmcs12->vm_entry_exception_error_code);
6586         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6587                 vmcs12->vm_entry_instruction_len);
6588         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6589                 vmcs12->guest_interruptibility_info);
6590         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6591         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6592         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6593         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6594         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6595                 vmcs12->guest_pending_dbg_exceptions);
6596         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6597         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6598
6599         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6600
6601         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6602                 (vmcs_config.pin_based_exec_ctrl |
6603                  vmcs12->pin_based_vm_exec_control));
6604
6605         /*
6606          * Whether page-faults are trapped is determined by a combination of
6607          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6608          * If enable_ept, L0 doesn't care about page faults and we should
6609          * set all of these to L1's desires. However, if !enable_ept, L0 does
6610          * care about (at least some) page faults, and because it is not easy
6611          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6612          * to exit on each and every L2 page fault. This is done by setting
6613          * MASK=MATCH=0 and (see below) EB.PF=1.
6614          * Note that below we don't need special code to set EB.PF beyond the
6615          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6616          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6617          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6618          *
6619          * A problem with this approach (when !enable_ept) is that L1 may be
6620          * injected with more page faults than it asked for. This could have
6621          * caused problems, but in practice existing hypervisors don't care.
6622          * To fix this, we will need to emulate the PFEC checking (on the L1
6623          * page tables), using walk_addr(), when injecting PFs to L1.
6624          */
6625         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6626                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6627         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6628                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6629
6630         if (cpu_has_secondary_exec_ctrls()) {
6631                 u32 exec_control = vmx_secondary_exec_control(vmx);
6632                 if (!vmx->rdtscp_enabled)
6633                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6634                 /* Take the following fields only from vmcs12 */
6635                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6636                 if (nested_cpu_has(vmcs12,
6637                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6638                         exec_control |= vmcs12->secondary_vm_exec_control;
6639
6640                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6641                         /*
6642                          * Translate L1 physical address to host physical
6643                          * address for vmcs02. Keep the page pinned, so this
6644                          * physical address remains valid. We keep a reference
6645                          * to it so we can release it later.
6646                          */
6647                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6648                                 nested_release_page(vmx->nested.apic_access_page);
6649                         vmx->nested.apic_access_page =
6650                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6651                         /*
6652                          * If translation failed, no matter: This feature asks
6653                          * to exit when accessing the given address, and if it
6654                          * can never be accessed, this feature won't do
6655                          * anything anyway.
6656                          */
6657                         if (!vmx->nested.apic_access_page)
6658                                 exec_control &=
6659                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6660                         else
6661                                 vmcs_write64(APIC_ACCESS_ADDR,
6662                                   page_to_phys(vmx->nested.apic_access_page));
6663                 }
6664
6665                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6666         }
6667
6668
6669         /*
6670          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6671          * Some constant fields are set here by vmx_set_constant_host_state().
6672          * Other fields are different per CPU, and will be set later when
6673          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6674          */
6675         vmx_set_constant_host_state();
6676
6677         /*
6678          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6679          * entry, but only if the current (host) sp changed from the value
6680          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6681          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6682          * here we just force the write to happen on entry.
6683          */
6684         vmx->host_rsp = 0;
6685
6686         exec_control = vmx_exec_control(vmx); /* L0's desires */
6687         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6688         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6689         exec_control &= ~CPU_BASED_TPR_SHADOW;
6690         exec_control |= vmcs12->cpu_based_vm_exec_control;
6691         /*
6692          * Merging of IO and MSR bitmaps not currently supported.
6693          * Rather, exit every time.
6694          */
6695         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6696         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6697         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6698
6699         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6700
6701         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6702          * bitwise-or of what L1 wants to trap for L2, and what we want to
6703          * trap. Note that CR0.TS also needs updating - we do this later.
6704          */
6705         update_exception_bitmap(vcpu);
6706         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6707         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6708
6709         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6710         vmcs_write32(VM_EXIT_CONTROLS,
6711                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6712         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6713                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6714
6715         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6716                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6717         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6718                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6719
6720
6721         set_cr4_guest_host_mask(vmx);
6722
6723         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6724                 vmcs_write64(TSC_OFFSET,
6725                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6726         else
6727                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6728
6729         if (enable_vpid) {
6730                 /*
6731                  * Trivially support vpid by letting L2s share their parent
6732                  * L1's vpid. TODO: move to a more elaborate solution, giving
6733                  * each L2 its own vpid and exposing the vpid feature to L1.
6734                  */
6735                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6736                 vmx_flush_tlb(vcpu);
6737         }
6738
6739         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6740                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6741         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6742                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6743         else
6744                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6745         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6746         vmx_set_efer(vcpu, vcpu->arch.efer);
6747
6748         /*
6749          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6750          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6751          * The CR0_READ_SHADOW is what L2 should have expected to read given
6752          * the specifications by L1; It's not enough to take
6753          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6754          * have more bits than L1 expected.
6755          */
6756         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6757         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6758
6759         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6760         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6761
6762         /* shadow page tables on either EPT or shadow page tables */
6763         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6764         kvm_mmu_reset_context(vcpu);
6765
6766         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6767         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6768 }
6769
6770 /*
6771  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6772  * for running an L2 nested guest.
6773  */
6774 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6775 {
6776         struct vmcs12 *vmcs12;
6777         struct vcpu_vmx *vmx = to_vmx(vcpu);
6778         int cpu;
6779         struct loaded_vmcs *vmcs02;
6780
6781         if (!nested_vmx_check_permission(vcpu) ||
6782             !nested_vmx_check_vmcs12(vcpu))
6783                 return 1;
6784
6785         skip_emulated_instruction(vcpu);
6786         vmcs12 = get_vmcs12(vcpu);
6787
6788         /*
6789          * The nested entry process starts with enforcing various prerequisites
6790          * on vmcs12 as required by the Intel SDM, and act appropriately when
6791          * they fail: As the SDM explains, some conditions should cause the
6792          * instruction to fail, while others will cause the instruction to seem
6793          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6794          * To speed up the normal (success) code path, we should avoid checking
6795          * for misconfigurations which will anyway be caught by the processor
6796          * when using the merged vmcs02.
6797          */
6798         if (vmcs12->launch_state == launch) {
6799                 nested_vmx_failValid(vcpu,
6800                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6801                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6802                 return 1;
6803         }
6804
6805         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6806                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6807                 /*TODO: Also verify bits beyond physical address width are 0*/
6808                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6809                 return 1;
6810         }
6811
6812         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6813                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6814                 /*TODO: Also verify bits beyond physical address width are 0*/
6815                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6816                 return 1;
6817         }
6818
6819         if (vmcs12->vm_entry_msr_load_count > 0 ||
6820             vmcs12->vm_exit_msr_load_count > 0 ||
6821             vmcs12->vm_exit_msr_store_count > 0) {
6822                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6823                                     __func__);
6824                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6825                 return 1;
6826         }
6827
6828         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6829               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6830             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6831               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6832             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6833               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6834             !vmx_control_verify(vmcs12->vm_exit_controls,
6835               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6836             !vmx_control_verify(vmcs12->vm_entry_controls,
6837               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6838         {
6839                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6840                 return 1;
6841         }
6842
6843         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6844             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6845                 nested_vmx_failValid(vcpu,
6846                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6847                 return 1;
6848         }
6849
6850         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6851             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6852                 nested_vmx_entry_failure(vcpu, vmcs12,
6853                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6854                 return 1;
6855         }
6856         if (vmcs12->vmcs_link_pointer != -1ull) {
6857                 nested_vmx_entry_failure(vcpu, vmcs12,
6858                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6859                 return 1;
6860         }
6861
6862         /*
6863          * We're finally done with prerequisite checking, and can start with
6864          * the nested entry.
6865          */
6866
6867         vmcs02 = nested_get_current_vmcs02(vmx);
6868         if (!vmcs02)
6869                 return -ENOMEM;
6870
6871         enter_guest_mode(vcpu);
6872
6873         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6874
6875         cpu = get_cpu();
6876         vmx->loaded_vmcs = vmcs02;
6877         vmx_vcpu_put(vcpu);
6878         vmx_vcpu_load(vcpu, cpu);
6879         vcpu->cpu = cpu;
6880         put_cpu();
6881
6882         vmcs12->launch_state = 1;
6883
6884         prepare_vmcs02(vcpu, vmcs12);
6885
6886         /*
6887          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6888          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6889          * returned as far as L1 is concerned. It will only return (and set
6890          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6891          */
6892         return 1;
6893 }
6894
6895 /*
6896  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6897  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6898  * This function returns the new value we should put in vmcs12.guest_cr0.
6899  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6900  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6901  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6902  *     didn't trap the bit, because if L1 did, so would L0).
6903  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6904  *     been modified by L2, and L1 knows it. So just leave the old value of
6905  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6906  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6907  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6908  *     changed these bits, and therefore they need to be updated, but L0
6909  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6910  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6911  */
6912 static inline unsigned long
6913 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6914 {
6915         return
6916         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6917         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6918         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6919                         vcpu->arch.cr0_guest_owned_bits));
6920 }
6921
6922 static inline unsigned long
6923 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6924 {
6925         return
6926         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6927         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6928         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6929                         vcpu->arch.cr4_guest_owned_bits));
6930 }
6931
6932 /*
6933  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6934  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6935  * and this function updates it to reflect the changes to the guest state while
6936  * L2 was running (and perhaps made some exits which were handled directly by L0
6937  * without going back to L1), and to reflect the exit reason.
6938  * Note that we do not have to copy here all VMCS fields, just those that
6939  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6940  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6941  * which already writes to vmcs12 directly.
6942  */
6943 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6944 {
6945         /* update guest state fields: */
6946         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6947         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6948
6949         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6950         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6951         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6952         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6953
6954         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6955         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6956         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6957         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6958         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6959         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6960         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6961         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6962         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6963         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6964         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6965         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6966         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6967         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6968         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6969         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6970         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6971         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6972         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6973         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6974         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6975         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6976         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6977         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6978         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6979         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6980         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6981         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6982         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6983         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6984         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6985         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6986         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6987         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6988         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6989         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6990
6991         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6992         vmcs12->guest_interruptibility_info =
6993                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6994         vmcs12->guest_pending_dbg_exceptions =
6995                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6996
6997         /* TODO: These cannot have changed unless we have MSR bitmaps and
6998          * the relevant bit asks not to trap the change */
6999         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7000         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7001                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7002         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7003         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7004         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7005
7006         /* update exit information fields: */
7007
7008         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
7009         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7010
7011         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7012         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7013         vmcs12->idt_vectoring_info_field =
7014                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7015         vmcs12->idt_vectoring_error_code =
7016                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7017         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7018         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7019
7020         /* clear vm-entry fields which are to be cleared on exit */
7021         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7022                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7023 }
7024
7025 /*
7026  * A part of what we need to when the nested L2 guest exits and we want to
7027  * run its L1 parent, is to reset L1's guest state to the host state specified
7028  * in vmcs12.
7029  * This function is to be called not only on normal nested exit, but also on
7030  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7031  * Failures During or After Loading Guest State").
7032  * This function should be called when the active VMCS is L1's (vmcs01).
7033  */
7034 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7035 {
7036         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7037                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7038         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7039                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7040         else
7041                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7042         vmx_set_efer(vcpu, vcpu->arch.efer);
7043
7044         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7045         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7046         /*
7047          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7048          * actually changed, because it depends on the current state of
7049          * fpu_active (which may have changed).
7050          * Note that vmx_set_cr0 refers to efer set above.
7051          */
7052         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7053         /*
7054          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7055          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7056          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7057          */
7058         update_exception_bitmap(vcpu);
7059         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7060         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7061
7062         /*
7063          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7064          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7065          */
7066         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7067         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7068
7069         /* shadow page tables on either EPT or shadow page tables */
7070         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7071         kvm_mmu_reset_context(vcpu);
7072
7073         if (enable_vpid) {
7074                 /*
7075                  * Trivially support vpid by letting L2s share their parent
7076                  * L1's vpid. TODO: move to a more elaborate solution, giving
7077                  * each L2 its own vpid and exposing the vpid feature to L1.
7078                  */
7079                 vmx_flush_tlb(vcpu);
7080         }
7081
7082
7083         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7084         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7085         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7086         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7087         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7088         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7089         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7090         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7091         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7092         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7093         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7094         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7095         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7096         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7097         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7098
7099         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7100                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7101         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7102                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7103                         vmcs12->host_ia32_perf_global_ctrl);
7104 }
7105
7106 /*
7107  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7108  * and modify vmcs12 to make it see what it would expect to see there if
7109  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7110  */
7111 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7112 {
7113         struct vcpu_vmx *vmx = to_vmx(vcpu);
7114         int cpu;
7115         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7116
7117         leave_guest_mode(vcpu);
7118         prepare_vmcs12(vcpu, vmcs12);
7119
7120         cpu = get_cpu();
7121         vmx->loaded_vmcs = &vmx->vmcs01;
7122         vmx_vcpu_put(vcpu);
7123         vmx_vcpu_load(vcpu, cpu);
7124         vcpu->cpu = cpu;
7125         put_cpu();
7126
7127         /* if no vmcs02 cache requested, remove the one we used */
7128         if (VMCS02_POOL_SIZE == 0)
7129                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7130
7131         load_vmcs12_host_state(vcpu, vmcs12);
7132
7133         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7134         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7135
7136         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7137         vmx->host_rsp = 0;
7138
7139         /* Unpin physical memory we referred to in vmcs02 */
7140         if (vmx->nested.apic_access_page) {
7141                 nested_release_page(vmx->nested.apic_access_page);
7142                 vmx->nested.apic_access_page = 0;
7143         }
7144
7145         /*
7146          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7147          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7148          * success or failure flag accordingly.
7149          */
7150         if (unlikely(vmx->fail)) {
7151                 vmx->fail = 0;
7152                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7153         } else
7154                 nested_vmx_succeed(vcpu);
7155 }
7156
7157 /*
7158  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7159  * 23.7 "VM-entry failures during or after loading guest state" (this also
7160  * lists the acceptable exit-reason and exit-qualification parameters).
7161  * It should only be called before L2 actually succeeded to run, and when
7162  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7163  */
7164 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7165                         struct vmcs12 *vmcs12,
7166                         u32 reason, unsigned long qualification)
7167 {
7168         load_vmcs12_host_state(vcpu, vmcs12);
7169         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7170         vmcs12->exit_qualification = qualification;
7171         nested_vmx_succeed(vcpu);
7172 }
7173
7174 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7175                                struct x86_instruction_info *info,
7176                                enum x86_intercept_stage stage)
7177 {
7178         return X86EMUL_CONTINUE;
7179 }
7180
7181 static struct kvm_x86_ops vmx_x86_ops = {
7182         .cpu_has_kvm_support = cpu_has_kvm_support,
7183         .disabled_by_bios = vmx_disabled_by_bios,
7184         .hardware_setup = hardware_setup,
7185         .hardware_unsetup = hardware_unsetup,
7186         .check_processor_compatibility = vmx_check_processor_compat,
7187         .hardware_enable = hardware_enable,
7188         .hardware_disable = hardware_disable,
7189         .cpu_has_accelerated_tpr = report_flexpriority,
7190
7191         .vcpu_create = vmx_create_vcpu,
7192         .vcpu_free = vmx_free_vcpu,
7193         .vcpu_reset = vmx_vcpu_reset,
7194
7195         .prepare_guest_switch = vmx_save_host_state,
7196         .vcpu_load = vmx_vcpu_load,
7197         .vcpu_put = vmx_vcpu_put,
7198
7199         .set_guest_debug = set_guest_debug,
7200         .get_msr = vmx_get_msr,
7201         .set_msr = vmx_set_msr,
7202         .get_segment_base = vmx_get_segment_base,
7203         .get_segment = vmx_get_segment,
7204         .set_segment = vmx_set_segment,
7205         .get_cpl = vmx_get_cpl,
7206         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7207         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7208         .decache_cr3 = vmx_decache_cr3,
7209         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7210         .set_cr0 = vmx_set_cr0,
7211         .set_cr3 = vmx_set_cr3,
7212         .set_cr4 = vmx_set_cr4,
7213         .set_efer = vmx_set_efer,
7214         .get_idt = vmx_get_idt,
7215         .set_idt = vmx_set_idt,
7216         .get_gdt = vmx_get_gdt,
7217         .set_gdt = vmx_set_gdt,
7218         .set_dr7 = vmx_set_dr7,
7219         .cache_reg = vmx_cache_reg,
7220         .get_rflags = vmx_get_rflags,
7221         .set_rflags = vmx_set_rflags,
7222         .fpu_activate = vmx_fpu_activate,
7223         .fpu_deactivate = vmx_fpu_deactivate,
7224
7225         .tlb_flush = vmx_flush_tlb,
7226
7227         .run = vmx_vcpu_run,
7228         .handle_exit = vmx_handle_exit,
7229         .skip_emulated_instruction = skip_emulated_instruction,
7230         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7231         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7232         .patch_hypercall = vmx_patch_hypercall,
7233         .set_irq = vmx_inject_irq,
7234         .set_nmi = vmx_inject_nmi,
7235         .queue_exception = vmx_queue_exception,
7236         .cancel_injection = vmx_cancel_injection,
7237         .interrupt_allowed = vmx_interrupt_allowed,
7238         .nmi_allowed = vmx_nmi_allowed,
7239         .get_nmi_mask = vmx_get_nmi_mask,
7240         .set_nmi_mask = vmx_set_nmi_mask,
7241         .enable_nmi_window = enable_nmi_window,
7242         .enable_irq_window = enable_irq_window,
7243         .update_cr8_intercept = update_cr8_intercept,
7244
7245         .set_tss_addr = vmx_set_tss_addr,
7246         .get_tdp_level = get_ept_level,
7247         .get_mt_mask = vmx_get_mt_mask,
7248
7249         .get_exit_info = vmx_get_exit_info,
7250
7251         .get_lpage_level = vmx_get_lpage_level,
7252
7253         .cpuid_update = vmx_cpuid_update,
7254
7255         .rdtscp_supported = vmx_rdtscp_supported,
7256
7257         .set_supported_cpuid = vmx_set_supported_cpuid,
7258
7259         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7260
7261         .set_tsc_khz = vmx_set_tsc_khz,
7262         .write_tsc_offset = vmx_write_tsc_offset,
7263         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7264         .compute_tsc_offset = vmx_compute_tsc_offset,
7265         .read_l1_tsc = vmx_read_l1_tsc,
7266
7267         .set_tdp_cr3 = vmx_set_cr3,
7268
7269         .check_intercept = vmx_check_intercept,
7270 };
7271
7272 static int __init vmx_init(void)
7273 {
7274         int r, i;
7275
7276         rdmsrl_safe(MSR_EFER, &host_efer);
7277
7278         for (i = 0; i < NR_VMX_MSR; ++i)
7279                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7280
7281         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7282         if (!vmx_io_bitmap_a)
7283                 return -ENOMEM;
7284
7285         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7286         if (!vmx_io_bitmap_b) {
7287                 r = -ENOMEM;
7288                 goto out;
7289         }
7290
7291         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7292         if (!vmx_msr_bitmap_legacy) {
7293                 r = -ENOMEM;
7294                 goto out1;
7295         }
7296
7297         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7298         if (!vmx_msr_bitmap_longmode) {
7299                 r = -ENOMEM;
7300                 goto out2;
7301         }
7302
7303         /*
7304          * Allow direct access to the PC debug port (it is often used for I/O
7305          * delays, but the vmexits simply slow things down).
7306          */
7307         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7308         clear_bit(0x80, vmx_io_bitmap_a);
7309
7310         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7311
7312         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7313         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7314
7315         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7316
7317         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7318                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7319         if (r)
7320                 goto out3;
7321
7322         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7323         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7324         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7325         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7326         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7327         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7328
7329         if (enable_ept) {
7330                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7331                                 VMX_EPT_EXECUTABLE_MASK);
7332                 ept_set_mmio_spte_mask();
7333                 kvm_enable_tdp();
7334         } else
7335                 kvm_disable_tdp();
7336
7337         return 0;
7338
7339 out3:
7340         free_page((unsigned long)vmx_msr_bitmap_longmode);
7341 out2:
7342         free_page((unsigned long)vmx_msr_bitmap_legacy);
7343 out1:
7344         free_page((unsigned long)vmx_io_bitmap_b);
7345 out:
7346         free_page((unsigned long)vmx_io_bitmap_a);
7347         return r;
7348 }
7349
7350 static void __exit vmx_exit(void)
7351 {
7352         free_page((unsigned long)vmx_msr_bitmap_legacy);
7353         free_page((unsigned long)vmx_msr_bitmap_longmode);
7354         free_page((unsigned long)vmx_io_bitmap_b);
7355         free_page((unsigned long)vmx_io_bitmap_a);
7356
7357         kvm_exit();
7358 }
7359
7360 module_init(vmx_init)
7361 module_exit(vmx_exit)