arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_invvpid(void)
1243 {
1244         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1245 }
1246
1247 static inline bool cpu_has_vmx_ept(void)
1248 {
1249         return vmcs_config.cpu_based_2nd_exec_ctrl &
1250                 SECONDARY_EXEC_ENABLE_EPT;
1251 }
1252
1253 static inline bool cpu_has_vmx_unrestricted_guest(void)
1254 {
1255         return vmcs_config.cpu_based_2nd_exec_ctrl &
1256                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1257 }
1258
1259 static inline bool cpu_has_vmx_ple(void)
1260 {
1261         return vmcs_config.cpu_based_2nd_exec_ctrl &
1262                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1263 }
1264
1265 static inline bool cpu_has_vmx_basic_inout(void)
1266 {
1267         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1268 }
1269
1270 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1271 {
1272         return flexpriority_enabled && lapic_in_kernel(vcpu);
1273 }
1274
1275 static inline bool cpu_has_vmx_vpid(void)
1276 {
1277         return vmcs_config.cpu_based_2nd_exec_ctrl &
1278                 SECONDARY_EXEC_ENABLE_VPID;
1279 }
1280
1281 static inline bool cpu_has_vmx_rdtscp(void)
1282 {
1283         return vmcs_config.cpu_based_2nd_exec_ctrl &
1284                 SECONDARY_EXEC_RDTSCP;
1285 }
1286
1287 static inline bool cpu_has_vmx_invpcid(void)
1288 {
1289         return vmcs_config.cpu_based_2nd_exec_ctrl &
1290                 SECONDARY_EXEC_ENABLE_INVPCID;
1291 }
1292
1293 static inline bool cpu_has_virtual_nmis(void)
1294 {
1295         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1296 }
1297
1298 static inline bool cpu_has_vmx_wbinvd_exit(void)
1299 {
1300         return vmcs_config.cpu_based_2nd_exec_ctrl &
1301                 SECONDARY_EXEC_WBINVD_EXITING;
1302 }
1303
1304 static inline bool cpu_has_vmx_shadow_vmcs(void)
1305 {
1306         u64 vmx_msr;
1307         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1308         /* check if the cpu supports writing r/o exit information fields */
1309         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1310                 return false;
1311
1312         return vmcs_config.cpu_based_2nd_exec_ctrl &
1313                 SECONDARY_EXEC_SHADOW_VMCS;
1314 }
1315
1316 static inline bool cpu_has_vmx_pml(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1319 }
1320
1321 static inline bool cpu_has_vmx_tsc_scaling(void)
1322 {
1323         return vmcs_config.cpu_based_2nd_exec_ctrl &
1324                 SECONDARY_EXEC_TSC_SCALING;
1325 }
1326
1327 static inline bool report_flexpriority(void)
1328 {
1329         return flexpriority_enabled;
1330 }
1331
1332 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return vmcs12->cpu_based_vm_exec_control & bit;
1335 }
1336
1337 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1338 {
1339         return (vmcs12->cpu_based_vm_exec_control &
1340                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1341                 (vmcs12->secondary_vm_exec_control & bit);
1342 }
1343
1344 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1347 }
1348
1349 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1350 {
1351         return vmcs12->pin_based_vm_exec_control &
1352                 PIN_BASED_VMX_PREEMPTION_TIMER;
1353 }
1354
1355 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1358 }
1359
1360 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1361 {
1362         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1363                 vmx_xsaves_supported();
1364 }
1365
1366 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1369 }
1370
1371 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1374 }
1375
1376 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1379 }
1380
1381 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1382 {
1383         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1384 }
1385
1386 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1387 {
1388         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1389 }
1390
1391 static inline bool is_nmi(u32 intr_info)
1392 {
1393         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1394                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1395 }
1396
1397 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1398                               u32 exit_intr_info,
1399                               unsigned long exit_qualification);
1400 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1401                         struct vmcs12 *vmcs12,
1402                         u32 reason, unsigned long qualification);
1403
1404 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1405 {
1406         int i;
1407
1408         for (i = 0; i < vmx->nmsrs; ++i)
1409                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1410                         return i;
1411         return -1;
1412 }
1413
1414 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1415 {
1416     struct {
1417         u64 vpid : 16;
1418         u64 rsvd : 48;
1419         u64 gva;
1420     } operand = { vpid, 0, gva };
1421
1422     asm volatile (__ex(ASM_VMX_INVVPID)
1423                   /* CF==1 or ZF==1 --> rc = -1 */
1424                   "; ja 1f ; ud2 ; 1:"
1425                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1426 }
1427
1428 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1429 {
1430         struct {
1431                 u64 eptp, gpa;
1432         } operand = {eptp, gpa};
1433
1434         asm volatile (__ex(ASM_VMX_INVEPT)
1435                         /* CF==1 or ZF==1 --> rc = -1 */
1436                         "; ja 1f ; ud2 ; 1:\n"
1437                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1438 }
1439
1440 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1441 {
1442         int i;
1443
1444         i = __find_msr_index(vmx, msr);
1445         if (i >= 0)
1446                 return &vmx->guest_msrs[i];
1447         return NULL;
1448 }
1449
1450 static void vmcs_clear(struct vmcs *vmcs)
1451 {
1452         u64 phys_addr = __pa(vmcs);
1453         u8 error;
1454
1455         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1456                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1457                       : "cc", "memory");
1458         if (error)
1459                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1460                        vmcs, phys_addr);
1461 }
1462
1463 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1464 {
1465         vmcs_clear(loaded_vmcs->vmcs);
1466         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1467                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1468         loaded_vmcs->cpu = -1;
1469         loaded_vmcs->launched = 0;
1470 }
1471
1472 static void vmcs_load(struct vmcs *vmcs)
1473 {
1474         u64 phys_addr = __pa(vmcs);
1475         u8 error;
1476
1477         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1478                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1479                         : "cc", "memory");
1480         if (error)
1481                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1482                        vmcs, phys_addr);
1483 }
1484
1485 #ifdef CONFIG_KEXEC_CORE
1486 /*
1487  * This bitmap is used to indicate whether the vmclear
1488  * operation is enabled on all cpus. All disabled by
1489  * default.
1490  */
1491 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1492
1493 static inline void crash_enable_local_vmclear(int cpu)
1494 {
1495         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline void crash_disable_local_vmclear(int cpu)
1499 {
1500         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static inline int crash_local_vmclear_enabled(int cpu)
1504 {
1505         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1506 }
1507
1508 static void crash_vmclear_local_loaded_vmcss(void)
1509 {
1510         int cpu = raw_smp_processor_id();
1511         struct loaded_vmcs *v;
1512
1513         if (!crash_local_vmclear_enabled(cpu))
1514                 return;
1515
1516         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1517                             loaded_vmcss_on_cpu_link)
1518                 vmcs_clear(v->vmcs);
1519 }
1520 #else
1521 static inline void crash_enable_local_vmclear(int cpu) { }
1522 static inline void crash_disable_local_vmclear(int cpu) { }
1523 #endif /* CONFIG_KEXEC_CORE */
1524
1525 static void __loaded_vmcs_clear(void *arg)
1526 {
1527         struct loaded_vmcs *loaded_vmcs = arg;
1528         int cpu = raw_smp_processor_id();
1529
1530         if (loaded_vmcs->cpu != cpu)
1531                 return; /* vcpu migration can race with cpu offline */
1532         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1533                 per_cpu(current_vmcs, cpu) = NULL;
1534         crash_disable_local_vmclear(cpu);
1535         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1536
1537         /*
1538          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1539          * is before setting loaded_vmcs->vcpu to -1 which is done in
1540          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1541          * then adds the vmcs into percpu list before it is deleted.
1542          */
1543         smp_wmb();
1544
1545         loaded_vmcs_init(loaded_vmcs);
1546         crash_enable_local_vmclear(cpu);
1547 }
1548
1549 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1550 {
1551         int cpu = loaded_vmcs->cpu;
1552
1553         if (cpu != -1)
1554                 smp_call_function_single(cpu,
1555                          __loaded_vmcs_clear, loaded_vmcs, 1);
1556 }
1557
1558 static inline void vpid_sync_vcpu_single(int vpid)
1559 {
1560         if (vpid == 0)
1561                 return;
1562
1563         if (cpu_has_vmx_invvpid_single())
1564                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1565 }
1566
1567 static inline void vpid_sync_vcpu_global(void)
1568 {
1569         if (cpu_has_vmx_invvpid_global())
1570                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1571 }
1572
1573 static inline void vpid_sync_context(int vpid)
1574 {
1575         if (cpu_has_vmx_invvpid_single())
1576                 vpid_sync_vcpu_single(vpid);
1577         else
1578                 vpid_sync_vcpu_global();
1579 }
1580
1581 static inline void ept_sync_global(void)
1582 {
1583         if (cpu_has_vmx_invept_global())
1584                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1585 }
1586
1587 static inline void ept_sync_context(u64 eptp)
1588 {
1589         if (enable_ept) {
1590                 if (cpu_has_vmx_invept_context())
1591                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1592                 else
1593                         ept_sync_global();
1594         }
1595 }
1596
1597 static __always_inline void vmcs_check16(unsigned long field)
1598 {
1599         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1600                          "16-bit accessor invalid for 64-bit field");
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1602                          "16-bit accessor invalid for 64-bit high field");
1603         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1604                          "16-bit accessor invalid for 32-bit high field");
1605         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1606                          "16-bit accessor invalid for natural width field");
1607 }
1608
1609 static __always_inline void vmcs_check32(unsigned long field)
1610 {
1611         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1612                          "32-bit accessor invalid for 16-bit field");
1613         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1614                          "32-bit accessor invalid for natural width field");
1615 }
1616
1617 static __always_inline void vmcs_check64(unsigned long field)
1618 {
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1620                          "64-bit accessor invalid for 16-bit field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1622                          "64-bit accessor invalid for 64-bit high field");
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1624                          "64-bit accessor invalid for 32-bit field");
1625         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1626                          "64-bit accessor invalid for natural width field");
1627 }
1628
1629 static __always_inline void vmcs_checkl(unsigned long field)
1630 {
1631         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1632                          "Natural width accessor invalid for 16-bit field");
1633         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1634                          "Natural width accessor invalid for 64-bit field");
1635         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1636                          "Natural width accessor invalid for 64-bit high field");
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1638                          "Natural width accessor invalid for 32-bit field");
1639 }
1640
1641 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1642 {
1643         unsigned long value;
1644
1645         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1646                       : "=a"(value) : "d"(field) : "cc");
1647         return value;
1648 }
1649
1650 static __always_inline u16 vmcs_read16(unsigned long field)
1651 {
1652         vmcs_check16(field);
1653         return __vmcs_readl(field);
1654 }
1655
1656 static __always_inline u32 vmcs_read32(unsigned long field)
1657 {
1658         vmcs_check32(field);
1659         return __vmcs_readl(field);
1660 }
1661
1662 static __always_inline u64 vmcs_read64(unsigned long field)
1663 {
1664         vmcs_check64(field);
1665 #ifdef CONFIG_X86_64
1666         return __vmcs_readl(field);
1667 #else
1668         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1669 #endif
1670 }
1671
1672 static __always_inline unsigned long vmcs_readl(unsigned long field)
1673 {
1674         vmcs_checkl(field);
1675         return __vmcs_readl(field);
1676 }
1677
1678 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1679 {
1680         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1681                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1682         dump_stack();
1683 }
1684
1685 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1686 {
1687         u8 error;
1688
1689         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1690                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1691         if (unlikely(error))
1692                 vmwrite_error(field, value);
1693 }
1694
1695 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1696 {
1697         vmcs_check16(field);
1698         __vmcs_writel(field, value);
1699 }
1700
1701 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1702 {
1703         vmcs_check32(field);
1704         __vmcs_writel(field, value);
1705 }
1706
1707 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1708 {
1709         vmcs_check64(field);
1710         __vmcs_writel(field, value);
1711 #ifndef CONFIG_X86_64
1712         asm volatile ("");
1713         __vmcs_writel(field+1, value >> 32);
1714 #endif
1715 }
1716
1717 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1718 {
1719         vmcs_checkl(field);
1720         __vmcs_writel(field, value);
1721 }
1722
1723 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1724 {
1725         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1726                          "vmcs_clear_bits does not support 64-bit fields");
1727         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1728 }
1729
1730 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1731 {
1732         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1733                          "vmcs_set_bits does not support 64-bit fields");
1734         __vmcs_writel(field, __vmcs_readl(field) | mask);
1735 }
1736
1737 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1738 {
1739         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1740 }
1741
1742 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1743 {
1744         vmcs_write32(VM_ENTRY_CONTROLS, val);
1745         vmx->vm_entry_controls_shadow = val;
1746 }
1747
1748 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1749 {
1750         if (vmx->vm_entry_controls_shadow != val)
1751                 vm_entry_controls_init(vmx, val);
1752 }
1753
1754 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1755 {
1756         return vmx->vm_entry_controls_shadow;
1757 }
1758
1759
1760 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1763 }
1764
1765 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1766 {
1767         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1768 }
1769
1770 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1771 {
1772         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1773 }
1774
1775 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1776 {
1777         vmcs_write32(VM_EXIT_CONTROLS, val);
1778         vmx->vm_exit_controls_shadow = val;
1779 }
1780
1781 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1782 {
1783         if (vmx->vm_exit_controls_shadow != val)
1784                 vm_exit_controls_init(vmx, val);
1785 }
1786
1787 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1788 {
1789         return vmx->vm_exit_controls_shadow;
1790 }
1791
1792
1793 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1796 }
1797
1798 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1799 {
1800         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1801 }
1802
1803 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1804 {
1805         vmx->segment_cache.bitmask = 0;
1806 }
1807
1808 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1809                                        unsigned field)
1810 {
1811         bool ret;
1812         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1813
1814         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1815                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1816                 vmx->segment_cache.bitmask = 0;
1817         }
1818         ret = vmx->segment_cache.bitmask & mask;
1819         vmx->segment_cache.bitmask |= mask;
1820         return ret;
1821 }
1822
1823 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1824 {
1825         u16 *p = &vmx->segment_cache.seg[seg].selector;
1826
1827         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1828                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1829         return *p;
1830 }
1831
1832 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1833 {
1834         ulong *p = &vmx->segment_cache.seg[seg].base;
1835
1836         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1837                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1838         return *p;
1839 }
1840
1841 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1842 {
1843         u32 *p = &vmx->segment_cache.seg[seg].limit;
1844
1845         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1846                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1847         return *p;
1848 }
1849
1850 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1851 {
1852         u32 *p = &vmx->segment_cache.seg[seg].ar;
1853
1854         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1855                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1856         return *p;
1857 }
1858
1859 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1860 {
1861         u32 eb;
1862
1863         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1864              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1865         if ((vcpu->guest_debug &
1866              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1867             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1868                 eb |= 1u << BP_VECTOR;
1869         if (to_vmx(vcpu)->rmode.vm86_active)
1870                 eb = ~0;
1871         if (enable_ept)
1872                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1873
1874         /* When we are running a nested L2 guest and L1 specified for it a
1875          * certain exception bitmap, we must trap the same exceptions and pass
1876          * them to L1. When running L2, we will only handle the exceptions
1877          * specified above if L1 did not want them.
1878          */
1879         if (is_guest_mode(vcpu))
1880                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1881
1882         vmcs_write32(EXCEPTION_BITMAP, eb);
1883 }
1884
1885 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1886                 unsigned long entry, unsigned long exit)
1887 {
1888         vm_entry_controls_clearbit(vmx, entry);
1889         vm_exit_controls_clearbit(vmx, exit);
1890 }
1891
1892 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1893 {
1894         unsigned i;
1895         struct msr_autoload *m = &vmx->msr_autoload;
1896
1897         switch (msr) {
1898         case MSR_EFER:
1899                 if (cpu_has_load_ia32_efer) {
1900                         clear_atomic_switch_msr_special(vmx,
1901                                         VM_ENTRY_LOAD_IA32_EFER,
1902                                         VM_EXIT_LOAD_IA32_EFER);
1903                         return;
1904                 }
1905                 break;
1906         case MSR_CORE_PERF_GLOBAL_CTRL:
1907                 if (cpu_has_load_perf_global_ctrl) {
1908                         clear_atomic_switch_msr_special(vmx,
1909                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1910                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1911                         return;
1912                 }
1913                 break;
1914         }
1915
1916         for (i = 0; i < m->nr; ++i)
1917                 if (m->guest[i].index == msr)
1918                         break;
1919
1920         if (i == m->nr)
1921                 return;
1922         --m->nr;
1923         m->guest[i] = m->guest[m->nr];
1924         m->host[i] = m->host[m->nr];
1925         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1926         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1927 }
1928
1929 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1930                 unsigned long entry, unsigned long exit,
1931                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1932                 u64 guest_val, u64 host_val)
1933 {
1934         vmcs_write64(guest_val_vmcs, guest_val);
1935         vmcs_write64(host_val_vmcs, host_val);
1936         vm_entry_controls_setbit(vmx, entry);
1937         vm_exit_controls_setbit(vmx, exit);
1938 }
1939
1940 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1941                                   u64 guest_val, u64 host_val)
1942 {
1943         unsigned i;
1944         struct msr_autoload *m = &vmx->msr_autoload;
1945
1946         switch (msr) {
1947         case MSR_EFER:
1948                 if (cpu_has_load_ia32_efer) {
1949                         add_atomic_switch_msr_special(vmx,
1950                                         VM_ENTRY_LOAD_IA32_EFER,
1951                                         VM_EXIT_LOAD_IA32_EFER,
1952                                         GUEST_IA32_EFER,
1953                                         HOST_IA32_EFER,
1954                                         guest_val, host_val);
1955                         return;
1956                 }
1957                 break;
1958         case MSR_CORE_PERF_GLOBAL_CTRL:
1959                 if (cpu_has_load_perf_global_ctrl) {
1960                         add_atomic_switch_msr_special(vmx,
1961                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1962                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1963                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1964                                         HOST_IA32_PERF_GLOBAL_CTRL,
1965                                         guest_val, host_val);
1966                         return;
1967                 }
1968                 break;
1969         case MSR_IA32_PEBS_ENABLE:
1970                 /* PEBS needs a quiescent period after being disabled (to write
1971                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1972                  * provide that period, so a CPU could write host's record into
1973                  * guest's memory.
1974                  */
1975                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1976         }
1977
1978         for (i = 0; i < m->nr; ++i)
1979                 if (m->guest[i].index == msr)
1980                         break;
1981
1982         if (i == NR_AUTOLOAD_MSRS) {
1983                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1984                                 "Can't add msr %x\n", msr);
1985                 return;
1986         } else if (i == m->nr) {
1987                 ++m->nr;
1988                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1989                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1990         }
1991
1992         m->guest[i].index = msr;
1993         m->guest[i].value = guest_val;
1994         m->host[i].index = msr;
1995         m->host[i].value = host_val;
1996 }
1997
1998 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1999 {
2000         u64 guest_efer = vmx->vcpu.arch.efer;
2001         u64 ignore_bits = 0;
2002
2003         if (!enable_ept) {
2004                 /*
2005                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2006                  * host CPUID is more efficient than testing guest CPUID
2007                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2008                  */
2009                 if (boot_cpu_has(X86_FEATURE_SMEP))
2010                         guest_efer |= EFER_NX;
2011                 else if (!(guest_efer & EFER_NX))
2012                         ignore_bits |= EFER_NX;
2013         }
2014
2015         /*
2016          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2017          */
2018         ignore_bits |= EFER_SCE;
2019 #ifdef CONFIG_X86_64
2020         ignore_bits |= EFER_LMA | EFER_LME;
2021         /* SCE is meaningful only in long mode on Intel */
2022         if (guest_efer & EFER_LMA)
2023                 ignore_bits &= ~(u64)EFER_SCE;
2024 #endif
2025
2026         clear_atomic_switch_msr(vmx, MSR_EFER);
2027
2028         /*
2029          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2030          * On CPUs that support "load IA32_EFER", always switch EFER
2031          * atomically, since it's faster than switching it manually.
2032          */
2033         if (cpu_has_load_ia32_efer ||
2034             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2035                 if (!(guest_efer & EFER_LMA))
2036                         guest_efer &= ~EFER_LME;
2037                 if (guest_efer != host_efer)
2038                         add_atomic_switch_msr(vmx, MSR_EFER,
2039                                               guest_efer, host_efer);
2040                 return false;
2041         } else {
2042                 guest_efer &= ~ignore_bits;
2043                 guest_efer |= host_efer & ignore_bits;
2044
2045                 vmx->guest_msrs[efer_offset].data = guest_efer;
2046                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2047
2048                 return true;
2049         }
2050 }
2051
2052 #ifdef CONFIG_X86_32
2053 /*
2054  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2055  * VMCS rather than the segment table.  KVM uses this helper to figure
2056  * out the current bases to poke them into the VMCS before entry.
2057  */
2058 static unsigned long segment_base(u16 selector)
2059 {
2060         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2061         struct desc_struct *table;
2062         unsigned long v;
2063
2064         if (!(selector & ~SEGMENT_RPL_MASK))
2065                 return 0;
2066
2067         table = (struct desc_struct *)gdt->address;
2068
2069         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2070                 u16 ldt_selector = kvm_read_ldt();
2071
2072                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2073                         return 0;
2074
2075                 table = (struct desc_struct *)segment_base(ldt_selector);
2076         }
2077         v = get_desc_base(&table[selector >> 3]);
2078         return v;
2079 }
2080 #endif
2081
2082 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2083 {
2084         struct vcpu_vmx *vmx = to_vmx(vcpu);
2085         int i;
2086
2087         if (vmx->host_state.loaded)
2088                 return;
2089
2090         vmx->host_state.loaded = 1;
2091         /*
2092          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2093          * allow segment selectors with cpl > 0 or ti == 1.
2094          */
2095         vmx->host_state.ldt_sel = kvm_read_ldt();
2096         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2097         savesegment(fs, vmx->host_state.fs_sel);
2098         if (!(vmx->host_state.fs_sel & 7)) {
2099                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2100                 vmx->host_state.fs_reload_needed = 0;
2101         } else {
2102                 vmcs_write16(HOST_FS_SELECTOR, 0);
2103                 vmx->host_state.fs_reload_needed = 1;
2104         }
2105         savesegment(gs, vmx->host_state.gs_sel);
2106         if (!(vmx->host_state.gs_sel & 7))
2107                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2108         else {
2109                 vmcs_write16(HOST_GS_SELECTOR, 0);
2110                 vmx->host_state.gs_ldt_reload_needed = 1;
2111         }
2112
2113 #ifdef CONFIG_X86_64
2114         savesegment(ds, vmx->host_state.ds_sel);
2115         savesegment(es, vmx->host_state.es_sel);
2116 #endif
2117
2118 #ifdef CONFIG_X86_64
2119         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2120         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2121 #else
2122         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2123         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2124 #endif
2125
2126 #ifdef CONFIG_X86_64
2127         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2128         if (is_long_mode(&vmx->vcpu))
2129                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2130 #endif
2131         if (boot_cpu_has(X86_FEATURE_MPX))
2132                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2133         for (i = 0; i < vmx->save_nmsrs; ++i)
2134                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2135                                    vmx->guest_msrs[i].data,
2136                                    vmx->guest_msrs[i].mask);
2137 }
2138
2139 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2140 {
2141         if (!vmx->host_state.loaded)
2142                 return;
2143
2144         ++vmx->vcpu.stat.host_state_reload;
2145         vmx->host_state.loaded = 0;
2146 #ifdef CONFIG_X86_64
2147         if (is_long_mode(&vmx->vcpu))
2148                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2149 #endif
2150         if (vmx->host_state.gs_ldt_reload_needed) {
2151                 kvm_load_ldt(vmx->host_state.ldt_sel);
2152 #ifdef CONFIG_X86_64
2153                 load_gs_index(vmx->host_state.gs_sel);
2154 #else
2155                 loadsegment(gs, vmx->host_state.gs_sel);
2156 #endif
2157         }
2158         if (vmx->host_state.fs_reload_needed)
2159                 loadsegment(fs, vmx->host_state.fs_sel);
2160 #ifdef CONFIG_X86_64
2161         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2162                 loadsegment(ds, vmx->host_state.ds_sel);
2163                 loadsegment(es, vmx->host_state.es_sel);
2164         }
2165 #endif
2166         invalidate_tss_limit();
2167 #ifdef CONFIG_X86_64
2168         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2169 #endif
2170         if (vmx->host_state.msr_host_bndcfgs)
2171                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2172         load_gdt(this_cpu_ptr(&host_gdt));
2173 }
2174
2175 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2176 {
2177         preempt_disable();
2178         __vmx_load_host_state(vmx);
2179         preempt_enable();
2180 }
2181
2182 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2183 {
2184         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2185         struct pi_desc old, new;
2186         unsigned int dest;
2187
2188         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2189                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2190                 !kvm_vcpu_apicv_active(vcpu))
2191                 return;
2192
2193         do {
2194                 old.control = new.control = pi_desc->control;
2195
2196                 /*
2197                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2198                  * are two possible cases:
2199                  * 1. After running 'pre_block', context switch
2200                  *    happened. For this case, 'sn' was set in
2201                  *    vmx_vcpu_put(), so we need to clear it here.
2202                  * 2. After running 'pre_block', we were blocked,
2203                  *    and woken up by some other guy. For this case,
2204                  *    we don't need to do anything, 'pi_post_block'
2205                  *    will do everything for us. However, we cannot
2206                  *    check whether it is case #1 or case #2 here
2207                  *    (maybe, not needed), so we also clear sn here,
2208                  *    I think it is not a big deal.
2209                  */
2210                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2211                         if (vcpu->cpu != cpu) {
2212                                 dest = cpu_physical_id(cpu);
2213
2214                                 if (x2apic_enabled())
2215                                         new.ndst = dest;
2216                                 else
2217                                         new.ndst = (dest << 8) & 0xFF00;
2218                         }
2219
2220                         /* set 'NV' to 'notification vector' */
2221                         new.nv = POSTED_INTR_VECTOR;
2222                 }
2223
2224                 /* Allow posting non-urgent interrupts */
2225                 new.sn = 0;
2226         } while (cmpxchg(&pi_desc->control, old.control,
2227                         new.control) != old.control);
2228 }
2229
2230 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2231 {
2232         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2233         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2234 }
2235
2236 /*
2237  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2238  * vcpu mutex is already taken.
2239  */
2240 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2241 {
2242         struct vcpu_vmx *vmx = to_vmx(vcpu);
2243         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2244         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2245
2246         if (!vmm_exclusive)
2247                 kvm_cpu_vmxon(phys_addr);
2248         else if (!already_loaded)
2249                 loaded_vmcs_clear(vmx->loaded_vmcs);
2250
2251         if (!already_loaded) {
2252                 local_irq_disable();
2253                 crash_disable_local_vmclear(cpu);
2254
2255                 /*
2256                  * Read loaded_vmcs->cpu should be before fetching
2257                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2258                  * See the comments in __loaded_vmcs_clear().
2259                  */
2260                 smp_rmb();
2261
2262                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2263                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2264                 crash_enable_local_vmclear(cpu);
2265                 local_irq_enable();
2266         }
2267
2268         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2269                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2270                 vmcs_load(vmx->loaded_vmcs->vmcs);
2271         }
2272
2273         if (!already_loaded) {
2274                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2275                 unsigned long sysenter_esp;
2276
2277                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2278
2279                 /*
2280                  * Linux uses per-cpu TSS and GDT, so set these when switching
2281                  * processors.  See 22.2.4.
2282                  */
2283                 vmcs_writel(HOST_TR_BASE,
2284                             (unsigned long)this_cpu_ptr(&cpu_tss));
2285                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2286
2287                 /*
2288                  * VM exits change the host TR limit to 0x67 after a VM
2289                  * exit.  This is okay, since 0x67 covers everything except
2290                  * the IO bitmap and have have code to handle the IO bitmap
2291                  * being lost after a VM exit.
2292                  */
2293                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2294
2295                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2296                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2297
2298                 vmx->loaded_vmcs->cpu = cpu;
2299         }
2300
2301         /* Setup TSC multiplier */
2302         if (kvm_has_tsc_control &&
2303             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2304                 decache_tsc_multiplier(vmx);
2305
2306         vmx_vcpu_pi_load(vcpu, cpu);
2307         vmx->host_pkru = read_pkru();
2308 }
2309
2310 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2311 {
2312         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2313
2314         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2315                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2316                 !kvm_vcpu_apicv_active(vcpu))
2317                 return;
2318
2319         /* Set SN when the vCPU is preempted */
2320         if (vcpu->preempted)
2321                 pi_set_sn(pi_desc);
2322 }
2323
2324 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2325 {
2326         vmx_vcpu_pi_put(vcpu);
2327
2328         __vmx_load_host_state(to_vmx(vcpu));
2329         if (!vmm_exclusive) {
2330                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2331                 vcpu->cpu = -1;
2332                 kvm_cpu_vmxoff();
2333         }
2334 }
2335
2336 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2337
2338 /*
2339  * Return the cr0 value that a nested guest would read. This is a combination
2340  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2341  * its hypervisor (cr0_read_shadow).
2342  */
2343 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2344 {
2345         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2346                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2347 }
2348 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2349 {
2350         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2351                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2352 }
2353
2354 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2355 {
2356         unsigned long rflags, save_rflags;
2357
2358         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2359                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2360                 rflags = vmcs_readl(GUEST_RFLAGS);
2361                 if (to_vmx(vcpu)->rmode.vm86_active) {
2362                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2363                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2364                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2365                 }
2366                 to_vmx(vcpu)->rflags = rflags;
2367         }
2368         return to_vmx(vcpu)->rflags;
2369 }
2370
2371 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2372 {
2373         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2374         to_vmx(vcpu)->rflags = rflags;
2375         if (to_vmx(vcpu)->rmode.vm86_active) {
2376                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2377                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2378         }
2379         vmcs_writel(GUEST_RFLAGS, rflags);
2380 }
2381
2382 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2383 {
2384         return to_vmx(vcpu)->guest_pkru;
2385 }
2386
2387 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2388 {
2389         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2390         int ret = 0;
2391
2392         if (interruptibility & GUEST_INTR_STATE_STI)
2393                 ret |= KVM_X86_SHADOW_INT_STI;
2394         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2395                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2396
2397         return ret;
2398 }
2399
2400 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2401 {
2402         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2403         u32 interruptibility = interruptibility_old;
2404
2405         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2406
2407         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2408                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2409         else if (mask & KVM_X86_SHADOW_INT_STI)
2410                 interruptibility |= GUEST_INTR_STATE_STI;
2411
2412         if ((interruptibility != interruptibility_old))
2413                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2414 }
2415
2416 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2417 {
2418         unsigned long rip;
2419
2420         rip = kvm_rip_read(vcpu);
2421         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2422         kvm_rip_write(vcpu, rip);
2423
2424         /* skipping an emulated instruction also counts */
2425         vmx_set_interrupt_shadow(vcpu, 0);
2426 }
2427
2428 /*
2429  * KVM wants to inject page-faults which it got to the guest. This function
2430  * checks whether in a nested guest, we need to inject them to L1 or L2.
2431  */
2432 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2433 {
2434         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2435
2436         if (!(vmcs12->exception_bitmap & (1u << nr)))
2437                 return 0;
2438
2439         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2440                           vmcs_read32(VM_EXIT_INTR_INFO),
2441                           vmcs_readl(EXIT_QUALIFICATION));
2442         return 1;
2443 }
2444
2445 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2446                                 bool has_error_code, u32 error_code,
2447                                 bool reinject)
2448 {
2449         struct vcpu_vmx *vmx = to_vmx(vcpu);
2450         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2451
2452         if (!reinject && is_guest_mode(vcpu) &&
2453             nested_vmx_check_exception(vcpu, nr))
2454                 return;
2455
2456         if (has_error_code) {
2457                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2458                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2459         }
2460
2461         if (vmx->rmode.vm86_active) {
2462                 int inc_eip = 0;
2463                 if (kvm_exception_is_soft(nr))
2464                         inc_eip = vcpu->arch.event_exit_inst_len;
2465                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2466                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2467                 return;
2468         }
2469
2470         if (kvm_exception_is_soft(nr)) {
2471                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2472                              vmx->vcpu.arch.event_exit_inst_len);
2473                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2474         } else
2475                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2476
2477         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2478 }
2479
2480 static bool vmx_rdtscp_supported(void)
2481 {
2482         return cpu_has_vmx_rdtscp();
2483 }
2484
2485 static bool vmx_invpcid_supported(void)
2486 {
2487         return cpu_has_vmx_invpcid() && enable_ept;
2488 }
2489
2490 /*
2491  * Swap MSR entry in host/guest MSR entry array.
2492  */
2493 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2494 {
2495         struct shared_msr_entry tmp;
2496
2497         tmp = vmx->guest_msrs[to];
2498         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2499         vmx->guest_msrs[from] = tmp;
2500 }
2501
2502 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2503 {
2504         unsigned long *msr_bitmap;
2505
2506         if (is_guest_mode(vcpu))
2507                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2508         else if (cpu_has_secondary_exec_ctrls() &&
2509                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2510                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2511                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2512                         if (is_long_mode(vcpu))
2513                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2514                         else
2515                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2516                 } else {
2517                         if (is_long_mode(vcpu))
2518                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2519                         else
2520                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2521                 }
2522         } else {
2523                 if (is_long_mode(vcpu))
2524                         msr_bitmap = vmx_msr_bitmap_longmode;
2525                 else
2526                         msr_bitmap = vmx_msr_bitmap_legacy;
2527         }
2528
2529         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2530 }
2531
2532 /*
2533  * Set up the vmcs to automatically save and restore system
2534  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2535  * mode, as fiddling with msrs is very expensive.
2536  */
2537 static void setup_msrs(struct vcpu_vmx *vmx)
2538 {
2539         int save_nmsrs, index;
2540
2541         save_nmsrs = 0;
2542 #ifdef CONFIG_X86_64
2543         if (is_long_mode(&vmx->vcpu)) {
2544                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2545                 if (index >= 0)
2546                         move_msr_up(vmx, index, save_nmsrs++);
2547                 index = __find_msr_index(vmx, MSR_LSTAR);
2548                 if (index >= 0)
2549                         move_msr_up(vmx, index, save_nmsrs++);
2550                 index = __find_msr_index(vmx, MSR_CSTAR);
2551                 if (index >= 0)
2552                         move_msr_up(vmx, index, save_nmsrs++);
2553                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2554                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2555                         move_msr_up(vmx, index, save_nmsrs++);
2556                 /*
2557                  * MSR_STAR is only needed on long mode guests, and only
2558                  * if efer.sce is enabled.
2559                  */
2560                 index = __find_msr_index(vmx, MSR_STAR);
2561                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2562                         move_msr_up(vmx, index, save_nmsrs++);
2563         }
2564 #endif
2565         index = __find_msr_index(vmx, MSR_EFER);
2566         if (index >= 0 && update_transition_efer(vmx, index))
2567                 move_msr_up(vmx, index, save_nmsrs++);
2568
2569         vmx->save_nmsrs = save_nmsrs;
2570
2571         if (cpu_has_vmx_msr_bitmap())
2572                 vmx_set_msr_bitmap(&vmx->vcpu);
2573 }
2574
2575 /*
2576  * reads and returns guest's timestamp counter "register"
2577  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2578  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2579  */
2580 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2581 {
2582         u64 host_tsc, tsc_offset;
2583
2584         host_tsc = rdtsc();
2585         tsc_offset = vmcs_read64(TSC_OFFSET);
2586         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2587 }
2588
2589 /*
2590  * writes 'offset' into guest's timestamp counter offset register
2591  */
2592 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2593 {
2594         if (is_guest_mode(vcpu)) {
2595                 /*
2596                  * We're here if L1 chose not to trap WRMSR to TSC. According
2597                  * to the spec, this should set L1's TSC; The offset that L1
2598                  * set for L2 remains unchanged, and still needs to be added
2599                  * to the newly set TSC to get L2's TSC.
2600                  */
2601                 struct vmcs12 *vmcs12;
2602                 /* recalculate vmcs02.TSC_OFFSET: */
2603                 vmcs12 = get_vmcs12(vcpu);
2604                 vmcs_write64(TSC_OFFSET, offset +
2605                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2606                          vmcs12->tsc_offset : 0));
2607         } else {
2608                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2609                                            vmcs_read64(TSC_OFFSET), offset);
2610                 vmcs_write64(TSC_OFFSET, offset);
2611         }
2612 }
2613
2614 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2615 {
2616         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2617         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2618 }
2619
2620 /*
2621  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2622  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2623  * all guests if the "nested" module option is off, and can also be disabled
2624  * for a single guest by disabling its VMX cpuid bit.
2625  */
2626 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2627 {
2628         return nested && guest_cpuid_has_vmx(vcpu);
2629 }
2630
2631 /*
2632  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2633  * returned for the various VMX controls MSRs when nested VMX is enabled.
2634  * The same values should also be used to verify that vmcs12 control fields are
2635  * valid during nested entry from L1 to L2.
2636  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2637  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2638  * bit in the high half is on if the corresponding bit in the control field
2639  * may be on. See also vmx_control_verify().
2640  */
2641 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2642 {
2643         /*
2644          * Note that as a general rule, the high half of the MSRs (bits in
2645          * the control fields which may be 1) should be initialized by the
2646          * intersection of the underlying hardware's MSR (i.e., features which
2647          * can be supported) and the list of features we want to expose -
2648          * because they are known to be properly supported in our code.
2649          * Also, usually, the low half of the MSRs (bits which must be 1) can
2650          * be set to 0, meaning that L1 may turn off any of these bits. The
2651          * reason is that if one of these bits is necessary, it will appear
2652          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2653          * fields of vmcs01 and vmcs02, will turn these bits off - and
2654          * nested_vmx_exit_handled() will not pass related exits to L1.
2655          * These rules have exceptions below.
2656          */
2657
2658         /* pin-based controls */
2659         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2660                 vmx->nested.nested_vmx_pinbased_ctls_low,
2661                 vmx->nested.nested_vmx_pinbased_ctls_high);
2662         vmx->nested.nested_vmx_pinbased_ctls_low |=
2663                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2664         vmx->nested.nested_vmx_pinbased_ctls_high &=
2665                 PIN_BASED_EXT_INTR_MASK |
2666                 PIN_BASED_NMI_EXITING |
2667                 PIN_BASED_VIRTUAL_NMIS;
2668         vmx->nested.nested_vmx_pinbased_ctls_high |=
2669                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2670                 PIN_BASED_VMX_PREEMPTION_TIMER;
2671         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2672                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2673                         PIN_BASED_POSTED_INTR;
2674
2675         /* exit controls */
2676         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2677                 vmx->nested.nested_vmx_exit_ctls_low,
2678                 vmx->nested.nested_vmx_exit_ctls_high);
2679         vmx->nested.nested_vmx_exit_ctls_low =
2680                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2681
2682         vmx->nested.nested_vmx_exit_ctls_high &=
2683 #ifdef CONFIG_X86_64
2684                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2685 #endif
2686                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2687         vmx->nested.nested_vmx_exit_ctls_high |=
2688                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2689                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2690                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2691
2692         if (kvm_mpx_supported())
2693                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2694
2695         /* We support free control of debug control saving. */
2696         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2697
2698         /* entry controls */
2699         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2700                 vmx->nested.nested_vmx_entry_ctls_low,
2701                 vmx->nested.nested_vmx_entry_ctls_high);
2702         vmx->nested.nested_vmx_entry_ctls_low =
2703                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2704         vmx->nested.nested_vmx_entry_ctls_high &=
2705 #ifdef CONFIG_X86_64
2706                 VM_ENTRY_IA32E_MODE |
2707 #endif
2708                 VM_ENTRY_LOAD_IA32_PAT;
2709         vmx->nested.nested_vmx_entry_ctls_high |=
2710                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2711         if (kvm_mpx_supported())
2712                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2713
2714         /* We support free control of debug control loading. */
2715         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2716
2717         /* cpu-based controls */
2718         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2719                 vmx->nested.nested_vmx_procbased_ctls_low,
2720                 vmx->nested.nested_vmx_procbased_ctls_high);
2721         vmx->nested.nested_vmx_procbased_ctls_low =
2722                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2723         vmx->nested.nested_vmx_procbased_ctls_high &=
2724                 CPU_BASED_VIRTUAL_INTR_PENDING |
2725                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2726                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2727                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2728                 CPU_BASED_CR3_STORE_EXITING |
2729 #ifdef CONFIG_X86_64
2730                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2731 #endif
2732                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2733                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2734                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2735                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2736                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2737         /*
2738          * We can allow some features even when not supported by the
2739          * hardware. For example, L1 can specify an MSR bitmap - and we
2740          * can use it to avoid exits to L1 - even when L0 runs L2
2741          * without MSR bitmaps.
2742          */
2743         vmx->nested.nested_vmx_procbased_ctls_high |=
2744                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2745                 CPU_BASED_USE_MSR_BITMAPS;
2746
2747         /* We support free control of CR3 access interception. */
2748         vmx->nested.nested_vmx_procbased_ctls_low &=
2749                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2750
2751         /* secondary cpu-based controls */
2752         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2753                 vmx->nested.nested_vmx_secondary_ctls_low,
2754                 vmx->nested.nested_vmx_secondary_ctls_high);
2755         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2756         vmx->nested.nested_vmx_secondary_ctls_high &=
2757                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2758                 SECONDARY_EXEC_RDTSCP |
2759                 SECONDARY_EXEC_DESC |
2760                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2761                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2762                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2763                 SECONDARY_EXEC_WBINVD_EXITING |
2764                 SECONDARY_EXEC_XSAVES;
2765
2766         if (enable_ept) {
2767                 /* nested EPT: emulate EPT also to L1 */
2768                 vmx->nested.nested_vmx_secondary_ctls_high |=
2769                         SECONDARY_EXEC_ENABLE_EPT;
2770                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2771                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2772                          VMX_EPT_INVEPT_BIT;
2773                 if (cpu_has_vmx_ept_execute_only())
2774                         vmx->nested.nested_vmx_ept_caps |=
2775                                 VMX_EPT_EXECUTE_ONLY_BIT;
2776                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2777                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2778                         VMX_EPT_EXTENT_CONTEXT_BIT;
2779         } else
2780                 vmx->nested.nested_vmx_ept_caps = 0;
2781
2782         /*
2783          * Old versions of KVM use the single-context version without
2784          * checking for support, so declare that it is supported even
2785          * though it is treated as global context.  The alternative is
2786          * not failing the single-context invvpid, and it is worse.
2787          */
2788         if (enable_vpid) {
2789                 vmx->nested.nested_vmx_secondary_ctls_high |=
2790                         SECONDARY_EXEC_ENABLE_VPID;
2791                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2792                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2793         } else
2794                 vmx->nested.nested_vmx_vpid_caps = 0;
2795
2796         if (enable_unrestricted_guest)
2797                 vmx->nested.nested_vmx_secondary_ctls_high |=
2798                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2799
2800         /* miscellaneous data */
2801         rdmsr(MSR_IA32_VMX_MISC,
2802                 vmx->nested.nested_vmx_misc_low,
2803                 vmx->nested.nested_vmx_misc_high);
2804         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2805         vmx->nested.nested_vmx_misc_low |=
2806                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2807                 VMX_MISC_ACTIVITY_HLT;
2808         vmx->nested.nested_vmx_misc_high = 0;
2809
2810         /*
2811          * This MSR reports some information about VMX support. We
2812          * should return information about the VMX we emulate for the
2813          * guest, and the VMCS structure we give it - not about the
2814          * VMX support of the underlying hardware.
2815          */
2816         vmx->nested.nested_vmx_basic =
2817                 VMCS12_REVISION |
2818                 VMX_BASIC_TRUE_CTLS |
2819                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2820                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2821
2822         if (cpu_has_vmx_basic_inout())
2823                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2824
2825         /*
2826          * These MSRs specify bits which the guest must keep fixed on
2827          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2828          * We picked the standard core2 setting.
2829          */
2830 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2831 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2832         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2833         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2834
2835         /* These MSRs specify bits which the guest must keep fixed off. */
2836         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2837         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2838
2839         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2840         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2841 }
2842
2843 /*
2844  * if fixed0[i] == 1: val[i] must be 1
2845  * if fixed1[i] == 0: val[i] must be 0
2846  */
2847 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2848 {
2849         return ((val & fixed1) | fixed0) == val;
2850 }
2851
2852 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2853 {
2854         return fixed_bits_valid(control, low, high);
2855 }
2856
2857 static inline u64 vmx_control_msr(u32 low, u32 high)
2858 {
2859         return low | ((u64)high << 32);
2860 }
2861
2862 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2863 {
2864         superset &= mask;
2865         subset &= mask;
2866
2867         return (superset | subset) == superset;
2868 }
2869
2870 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2871 {
2872         const u64 feature_and_reserved =
2873                 /* feature (except bit 48; see below) */
2874                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2875                 /* reserved */
2876                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2877         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2878
2879         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2880                 return -EINVAL;
2881
2882         /*
2883          * KVM does not emulate a version of VMX that constrains physical
2884          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2885          */
2886         if (data & BIT_ULL(48))
2887                 return -EINVAL;
2888
2889         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2890             vmx_basic_vmcs_revision_id(data))
2891                 return -EINVAL;
2892
2893         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2894                 return -EINVAL;
2895
2896         vmx->nested.nested_vmx_basic = data;
2897         return 0;
2898 }
2899
2900 static int
2901 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2902 {
2903         u64 supported;
2904         u32 *lowp, *highp;
2905
2906         switch (msr_index) {
2907         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2908                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2909                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2910                 break;
2911         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2912                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2913                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2914                 break;
2915         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2916                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2917                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2918                 break;
2919         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2920                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2921                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2922                 break;
2923         case MSR_IA32_VMX_PROCBASED_CTLS2:
2924                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2925                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2926                 break;
2927         default:
2928                 BUG();
2929         }
2930
2931         supported = vmx_control_msr(*lowp, *highp);
2932
2933         /* Check must-be-1 bits are still 1. */
2934         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2935                 return -EINVAL;
2936
2937         /* Check must-be-0 bits are still 0. */
2938         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2939                 return -EINVAL;
2940
2941         *lowp = data;
2942         *highp = data >> 32;
2943         return 0;
2944 }
2945
2946 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2947 {
2948         const u64 feature_and_reserved_bits =
2949                 /* feature */
2950                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2951                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2952                 /* reserved */
2953                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2954         u64 vmx_misc;
2955
2956         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2957                                    vmx->nested.nested_vmx_misc_high);
2958
2959         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2960                 return -EINVAL;
2961
2962         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2963              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2964             vmx_misc_preemption_timer_rate(data) !=
2965             vmx_misc_preemption_timer_rate(vmx_misc))
2966                 return -EINVAL;
2967
2968         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2969                 return -EINVAL;
2970
2971         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2972                 return -EINVAL;
2973
2974         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2975                 return -EINVAL;
2976
2977         vmx->nested.nested_vmx_misc_low = data;
2978         vmx->nested.nested_vmx_misc_high = data >> 32;
2979         return 0;
2980 }
2981
2982 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2983 {
2984         u64 vmx_ept_vpid_cap;
2985
2986         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2987                                            vmx->nested.nested_vmx_vpid_caps);
2988
2989         /* Every bit is either reserved or a feature bit. */
2990         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2991                 return -EINVAL;
2992
2993         vmx->nested.nested_vmx_ept_caps = data;
2994         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2995         return 0;
2996 }
2997
2998 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2999 {
3000         u64 *msr;
3001
3002         switch (msr_index) {
3003         case MSR_IA32_VMX_CR0_FIXED0:
3004                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3005                 break;
3006         case MSR_IA32_VMX_CR4_FIXED0:
3007                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3008                 break;
3009         default:
3010                 BUG();
3011         }
3012
3013         /*
3014          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3015          * must be 1 in the restored value.
3016          */
3017         if (!is_bitwise_subset(data, *msr, -1ULL))
3018                 return -EINVAL;
3019
3020         *msr = data;
3021         return 0;
3022 }
3023
3024 /*
3025  * Called when userspace is restoring VMX MSRs.
3026  *
3027  * Returns 0 on success, non-0 otherwise.
3028  */
3029 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3030 {
3031         struct vcpu_vmx *vmx = to_vmx(vcpu);
3032
3033         switch (msr_index) {
3034         case MSR_IA32_VMX_BASIC:
3035                 return vmx_restore_vmx_basic(vmx, data);
3036         case MSR_IA32_VMX_PINBASED_CTLS:
3037         case MSR_IA32_VMX_PROCBASED_CTLS:
3038         case MSR_IA32_VMX_EXIT_CTLS:
3039         case MSR_IA32_VMX_ENTRY_CTLS:
3040                 /*
3041                  * The "non-true" VMX capability MSRs are generated from the
3042                  * "true" MSRs, so we do not support restoring them directly.
3043                  *
3044                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3045                  * should restore the "true" MSRs with the must-be-1 bits
3046                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3047                  * DEFAULT SETTINGS".
3048                  */
3049                 return -EINVAL;
3050         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3051         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3052         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3053         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3054         case MSR_IA32_VMX_PROCBASED_CTLS2:
3055                 return vmx_restore_control_msr(vmx, msr_index, data);
3056         case MSR_IA32_VMX_MISC:
3057                 return vmx_restore_vmx_misc(vmx, data);
3058         case MSR_IA32_VMX_CR0_FIXED0:
3059         case MSR_IA32_VMX_CR4_FIXED0:
3060                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3061         case MSR_IA32_VMX_CR0_FIXED1:
3062         case MSR_IA32_VMX_CR4_FIXED1:
3063                 /*
3064                  * These MSRs are generated based on the vCPU's CPUID, so we
3065                  * do not support restoring them directly.
3066                  */
3067                 return -EINVAL;
3068         case MSR_IA32_VMX_EPT_VPID_CAP:
3069                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3070         case MSR_IA32_VMX_VMCS_ENUM:
3071                 vmx->nested.nested_vmx_vmcs_enum = data;
3072                 return 0;
3073         default:
3074                 /*
3075                  * The rest of the VMX capability MSRs do not support restore.
3076                  */
3077                 return -EINVAL;
3078         }
3079 }
3080
3081 /* Returns 0 on success, non-0 otherwise. */
3082 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3083 {
3084         struct vcpu_vmx *vmx = to_vmx(vcpu);
3085
3086         switch (msr_index) {
3087         case MSR_IA32_VMX_BASIC:
3088                 *pdata = vmx->nested.nested_vmx_basic;
3089                 break;
3090         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3091         case MSR_IA32_VMX_PINBASED_CTLS:
3092                 *pdata = vmx_control_msr(
3093                         vmx->nested.nested_vmx_pinbased_ctls_low,
3094                         vmx->nested.nested_vmx_pinbased_ctls_high);
3095                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3096                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3097                 break;
3098         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3099         case MSR_IA32_VMX_PROCBASED_CTLS:
3100                 *pdata = vmx_control_msr(
3101                         vmx->nested.nested_vmx_procbased_ctls_low,
3102                         vmx->nested.nested_vmx_procbased_ctls_high);
3103                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3104                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3105                 break;
3106         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3107         case MSR_IA32_VMX_EXIT_CTLS:
3108                 *pdata = vmx_control_msr(
3109                         vmx->nested.nested_vmx_exit_ctls_low,
3110                         vmx->nested.nested_vmx_exit_ctls_high);
3111                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3112                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3113                 break;
3114         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3115         case MSR_IA32_VMX_ENTRY_CTLS:
3116                 *pdata = vmx_control_msr(
3117                         vmx->nested.nested_vmx_entry_ctls_low,
3118                         vmx->nested.nested_vmx_entry_ctls_high);
3119                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3120                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3121                 break;
3122         case MSR_IA32_VMX_MISC:
3123                 *pdata = vmx_control_msr(
3124                         vmx->nested.nested_vmx_misc_low,
3125                         vmx->nested.nested_vmx_misc_high);
3126                 break;
3127         case MSR_IA32_VMX_CR0_FIXED0:
3128                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3129                 break;
3130         case MSR_IA32_VMX_CR0_FIXED1:
3131                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3132                 break;
3133         case MSR_IA32_VMX_CR4_FIXED0:
3134                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3135                 break;
3136         case MSR_IA32_VMX_CR4_FIXED1:
3137                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3138                 break;
3139         case MSR_IA32_VMX_VMCS_ENUM:
3140                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3141                 break;
3142         case MSR_IA32_VMX_PROCBASED_CTLS2:
3143                 *pdata = vmx_control_msr(
3144                         vmx->nested.nested_vmx_secondary_ctls_low,
3145                         vmx->nested.nested_vmx_secondary_ctls_high);
3146                 break;
3147         case MSR_IA32_VMX_EPT_VPID_CAP:
3148                 *pdata = vmx->nested.nested_vmx_ept_caps |
3149                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3150                 break;
3151         default:
3152                 return 1;
3153         }
3154
3155         return 0;
3156 }
3157
3158 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3159                                                  uint64_t val)
3160 {
3161         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3162
3163         return !(val & ~valid_bits);
3164 }
3165
3166 /*
3167  * Reads an msr value (of 'msr_index') into 'pdata'.
3168  * Returns 0 on success, non-0 otherwise.
3169  * Assumes vcpu_load() was already called.
3170  */
3171 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3172 {
3173         struct shared_msr_entry *msr;
3174
3175         switch (msr_info->index) {
3176 #ifdef CONFIG_X86_64
3177         case MSR_FS_BASE:
3178                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3179                 break;
3180         case MSR_GS_BASE:
3181                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3182                 break;
3183         case MSR_KERNEL_GS_BASE:
3184                 vmx_load_host_state(to_vmx(vcpu));
3185                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3186                 break;
3187 #endif
3188         case MSR_EFER:
3189                 return kvm_get_msr_common(vcpu, msr_info);
3190         case MSR_IA32_TSC:
3191                 msr_info->data = guest_read_tsc(vcpu);
3192                 break;
3193         case MSR_IA32_SYSENTER_CS:
3194                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3195                 break;
3196         case MSR_IA32_SYSENTER_EIP:
3197                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3198                 break;
3199         case MSR_IA32_SYSENTER_ESP:
3200                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3201                 break;
3202         case MSR_IA32_BNDCFGS:
3203                 if (!kvm_mpx_supported())
3204                         return 1;
3205                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3206                 break;
3207         case MSR_IA32_MCG_EXT_CTL:
3208                 if (!msr_info->host_initiated &&
3209                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3210                       FEATURE_CONTROL_LMCE))
3211                         return 1;
3212                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3213                 break;
3214         case MSR_IA32_FEATURE_CONTROL:
3215                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3216                 break;
3217         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3218                 if (!nested_vmx_allowed(vcpu))
3219                         return 1;
3220                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3221         case MSR_IA32_XSS:
3222                 if (!vmx_xsaves_supported())
3223                         return 1;
3224                 msr_info->data = vcpu->arch.ia32_xss;
3225                 break;
3226         case MSR_TSC_AUX:
3227                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3228                         return 1;
3229                 /* Otherwise falls through */
3230         default:
3231                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3232                 if (msr) {
3233                         msr_info->data = msr->data;
3234                         break;
3235                 }
3236                 return kvm_get_msr_common(vcpu, msr_info);
3237         }
3238
3239         return 0;
3240 }
3241
3242 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3243
3244 /*
3245  * Writes msr value into into the appropriate "register".
3246  * Returns 0 on success, non-0 otherwise.
3247  * Assumes vcpu_load() was already called.
3248  */
3249 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3250 {
3251         struct vcpu_vmx *vmx = to_vmx(vcpu);
3252         struct shared_msr_entry *msr;
3253         int ret = 0;
3254         u32 msr_index = msr_info->index;
3255         u64 data = msr_info->data;
3256
3257         switch (msr_index) {
3258         case MSR_EFER:
3259                 ret = kvm_set_msr_common(vcpu, msr_info);
3260                 break;
3261 #ifdef CONFIG_X86_64
3262         case MSR_FS_BASE:
3263                 vmx_segment_cache_clear(vmx);
3264                 vmcs_writel(GUEST_FS_BASE, data);
3265                 break;
3266         case MSR_GS_BASE:
3267                 vmx_segment_cache_clear(vmx);
3268                 vmcs_writel(GUEST_GS_BASE, data);
3269                 break;
3270         case MSR_KERNEL_GS_BASE:
3271                 vmx_load_host_state(vmx);
3272                 vmx->msr_guest_kernel_gs_base = data;
3273                 break;
3274 #endif
3275         case MSR_IA32_SYSENTER_CS:
3276                 vmcs_write32(GUEST_SYSENTER_CS, data);
3277                 break;
3278         case MSR_IA32_SYSENTER_EIP:
3279                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3280                 break;
3281         case MSR_IA32_SYSENTER_ESP:
3282                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3283                 break;
3284         case MSR_IA32_BNDCFGS:
3285                 if (!kvm_mpx_supported())
3286                         return 1;
3287                 vmcs_write64(GUEST_BNDCFGS, data);
3288                 break;
3289         case MSR_IA32_TSC:
3290                 kvm_write_tsc(vcpu, msr_info);
3291                 break;
3292         case MSR_IA32_CR_PAT:
3293                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3294                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3295                                 return 1;
3296                         vmcs_write64(GUEST_IA32_PAT, data);
3297                         vcpu->arch.pat = data;
3298                         break;
3299                 }
3300                 ret = kvm_set_msr_common(vcpu, msr_info);
3301                 break;
3302         case MSR_IA32_TSC_ADJUST:
3303                 ret = kvm_set_msr_common(vcpu, msr_info);
3304                 break;
3305         case MSR_IA32_MCG_EXT_CTL:
3306                 if ((!msr_info->host_initiated &&
3307                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3308                        FEATURE_CONTROL_LMCE)) ||
3309                     (data & ~MCG_EXT_CTL_LMCE_EN))
3310                         return 1;
3311                 vcpu->arch.mcg_ext_ctl = data;
3312                 break;
3313         case MSR_IA32_FEATURE_CONTROL:
3314                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3315                     (to_vmx(vcpu)->msr_ia32_feature_control &
3316                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3317                         return 1;
3318                 vmx->msr_ia32_feature_control = data;
3319                 if (msr_info->host_initiated && data == 0)
3320                         vmx_leave_nested(vcpu);
3321                 break;
3322         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3323                 if (!msr_info->host_initiated)
3324                         return 1; /* they are read-only */
3325                 if (!nested_vmx_allowed(vcpu))
3326                         return 1;
3327                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3328         case MSR_IA32_XSS:
3329                 if (!vmx_xsaves_supported())
3330                         return 1;
3331                 /*
3332                  * The only supported bit as of Skylake is bit 8, but
3333                  * it is not supported on KVM.
3334                  */
3335                 if (data != 0)
3336                         return 1;
3337                 vcpu->arch.ia32_xss = data;
3338                 if (vcpu->arch.ia32_xss != host_xss)
3339                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3340                                 vcpu->arch.ia32_xss, host_xss);
3341                 else
3342                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3343                 break;
3344         case MSR_TSC_AUX:
3345                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3346                         return 1;
3347                 /* Check reserved bit, higher 32 bits should be zero */
3348                 if ((data >> 32) != 0)
3349                         return 1;
3350                 /* Otherwise falls through */
3351         default:
3352                 msr = find_msr_entry(vmx, msr_index);
3353                 if (msr) {
3354                         u64 old_msr_data = msr->data;
3355                         msr->data = data;
3356                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3357                                 preempt_disable();
3358                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3359                                                          msr->mask);
3360                                 preempt_enable();
3361                                 if (ret)
3362                                         msr->data = old_msr_data;
3363                         }
3364                         break;
3365                 }
3366                 ret = kvm_set_msr_common(vcpu, msr_info);
3367         }
3368
3369         return ret;
3370 }
3371
3372 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3373 {
3374         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3375         switch (reg) {
3376         case VCPU_REGS_RSP:
3377                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3378                 break;
3379         case VCPU_REGS_RIP:
3380                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3381                 break;
3382         case VCPU_EXREG_PDPTR:
3383                 if (enable_ept)
3384                         ept_save_pdptrs(vcpu);
3385                 break;
3386         default:
3387                 break;
3388         }
3389 }
3390
3391 static __init int cpu_has_kvm_support(void)
3392 {
3393         return cpu_has_vmx();
3394 }
3395
3396 static __init int vmx_disabled_by_bios(void)
3397 {
3398         u64 msr;
3399
3400         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3401         if (msr & FEATURE_CONTROL_LOCKED) {
3402                 /* launched w/ TXT and VMX disabled */
3403                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3404                         && tboot_enabled())
3405                         return 1;
3406                 /* launched w/o TXT and VMX only enabled w/ TXT */
3407                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3408                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3409                         && !tboot_enabled()) {
3410                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3411                                 "activate TXT before enabling KVM\n");
3412                         return 1;
3413                 }
3414                 /* launched w/o TXT and VMX disabled */
3415                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3416                         && !tboot_enabled())
3417                         return 1;
3418         }
3419
3420         return 0;
3421 }
3422
3423 static void kvm_cpu_vmxon(u64 addr)
3424 {
3425         intel_pt_handle_vmx(1);
3426
3427         asm volatile (ASM_VMX_VMXON_RAX
3428                         : : "a"(&addr), "m"(addr)
3429                         : "memory", "cc");
3430 }
3431
3432 static int hardware_enable(void)
3433 {
3434         int cpu = raw_smp_processor_id();
3435         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3436         u64 old, test_bits;
3437
3438         if (cr4_read_shadow() & X86_CR4_VMXE)
3439                 return -EBUSY;
3440
3441         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3442         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3443         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3444
3445         /*
3446          * Now we can enable the vmclear operation in kdump
3447          * since the loaded_vmcss_on_cpu list on this cpu
3448          * has been initialized.
3449          *
3450          * Though the cpu is not in VMX operation now, there
3451          * is no problem to enable the vmclear operation
3452          * for the loaded_vmcss_on_cpu list is empty!
3453          */
3454         crash_enable_local_vmclear(cpu);
3455
3456         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3457
3458         test_bits = FEATURE_CONTROL_LOCKED;
3459         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3460         if (tboot_enabled())
3461                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3462
3463         if ((old & test_bits) != test_bits) {
3464                 /* enable and lock */
3465                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3466         }
3467         cr4_set_bits(X86_CR4_VMXE);
3468
3469         if (vmm_exclusive) {
3470                 kvm_cpu_vmxon(phys_addr);
3471                 ept_sync_global();
3472         }
3473
3474         native_store_gdt(this_cpu_ptr(&host_gdt));
3475
3476         return 0;
3477 }
3478
3479 static void vmclear_local_loaded_vmcss(void)
3480 {
3481         int cpu = raw_smp_processor_id();
3482         struct loaded_vmcs *v, *n;
3483
3484         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3485                                  loaded_vmcss_on_cpu_link)
3486                 __loaded_vmcs_clear(v);
3487 }
3488
3489
3490 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3491  * tricks.
3492  */
3493 static void kvm_cpu_vmxoff(void)
3494 {
3495         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3496
3497         intel_pt_handle_vmx(0);
3498 }
3499
3500 static void hardware_disable(void)
3501 {
3502         if (vmm_exclusive) {
3503                 vmclear_local_loaded_vmcss();
3504                 kvm_cpu_vmxoff();
3505         }
3506         cr4_clear_bits(X86_CR4_VMXE);
3507 }
3508
3509 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3510                                       u32 msr, u32 *result)
3511 {
3512         u32 vmx_msr_low, vmx_msr_high;
3513         u32 ctl = ctl_min | ctl_opt;
3514
3515         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3516
3517         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3518         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3519
3520         /* Ensure minimum (required) set of control bits are supported. */
3521         if (ctl_min & ~ctl)
3522                 return -EIO;
3523
3524         *result = ctl;
3525         return 0;
3526 }
3527
3528 static __init bool allow_1_setting(u32 msr, u32 ctl)
3529 {
3530         u32 vmx_msr_low, vmx_msr_high;
3531
3532         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3533         return vmx_msr_high & ctl;
3534 }
3535
3536 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3537 {
3538         u32 vmx_msr_low, vmx_msr_high;
3539         u32 min, opt, min2, opt2;
3540         u32 _pin_based_exec_control = 0;
3541         u32 _cpu_based_exec_control = 0;
3542         u32 _cpu_based_2nd_exec_control = 0;
3543         u32 _vmexit_control = 0;
3544         u32 _vmentry_control = 0;
3545
3546         min = CPU_BASED_HLT_EXITING |
3547 #ifdef CONFIG_X86_64
3548               CPU_BASED_CR8_LOAD_EXITING |
3549               CPU_BASED_CR8_STORE_EXITING |
3550 #endif
3551               CPU_BASED_CR3_LOAD_EXITING |
3552               CPU_BASED_CR3_STORE_EXITING |
3553               CPU_BASED_USE_IO_BITMAPS |
3554               CPU_BASED_MOV_DR_EXITING |
3555               CPU_BASED_USE_TSC_OFFSETING |
3556               CPU_BASED_MWAIT_EXITING |
3557               CPU_BASED_MONITOR_EXITING |
3558               CPU_BASED_INVLPG_EXITING |
3559               CPU_BASED_RDPMC_EXITING;
3560
3561         opt = CPU_BASED_TPR_SHADOW |
3562               CPU_BASED_USE_MSR_BITMAPS |
3563               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3564         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3565                                 &_cpu_based_exec_control) < 0)
3566                 return -EIO;
3567 #ifdef CONFIG_X86_64
3568         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3569                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3570                                            ~CPU_BASED_CR8_STORE_EXITING;
3571 #endif
3572         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3573                 min2 = 0;
3574                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3575                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3576                         SECONDARY_EXEC_WBINVD_EXITING |
3577                         SECONDARY_EXEC_ENABLE_VPID |
3578                         SECONDARY_EXEC_ENABLE_EPT |
3579                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3580                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3581                         SECONDARY_EXEC_RDTSCP |
3582                         SECONDARY_EXEC_ENABLE_INVPCID |
3583                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3584                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3585                         SECONDARY_EXEC_SHADOW_VMCS |
3586                         SECONDARY_EXEC_XSAVES |
3587                         SECONDARY_EXEC_ENABLE_PML |
3588                         SECONDARY_EXEC_TSC_SCALING;
3589                 if (adjust_vmx_controls(min2, opt2,
3590                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3591                                         &_cpu_based_2nd_exec_control) < 0)
3592                         return -EIO;
3593         }
3594 #ifndef CONFIG_X86_64
3595         if (!(_cpu_based_2nd_exec_control &
3596                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3597                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3598 #endif
3599
3600         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3601                 _cpu_based_2nd_exec_control &= ~(
3602                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3603                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3604                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3605
3606         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3607                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3608                    enabled */
3609                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3610                                              CPU_BASED_CR3_STORE_EXITING |
3611                                              CPU_BASED_INVLPG_EXITING);
3612                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3613                       vmx_capability.ept, vmx_capability.vpid);
3614         }
3615
3616         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3617 #ifdef CONFIG_X86_64
3618         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3619 #endif
3620         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3621                 VM_EXIT_CLEAR_BNDCFGS;
3622         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3623                                 &_vmexit_control) < 0)
3624                 return -EIO;
3625
3626         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3627         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3628                  PIN_BASED_VMX_PREEMPTION_TIMER;
3629         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3630                                 &_pin_based_exec_control) < 0)
3631                 return -EIO;
3632
3633         if (cpu_has_broken_vmx_preemption_timer())
3634                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3635         if (!(_cpu_based_2nd_exec_control &
3636                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3637                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3638
3639         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3640         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3641         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3642                                 &_vmentry_control) < 0)
3643                 return -EIO;
3644
3645         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3646
3647         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3648         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3649                 return -EIO;
3650
3651 #ifdef CONFIG_X86_64
3652         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3653         if (vmx_msr_high & (1u<<16))
3654                 return -EIO;
3655 #endif
3656
3657         /* Require Write-Back (WB) memory type for VMCS accesses. */
3658         if (((vmx_msr_high >> 18) & 15) != 6)
3659                 return -EIO;
3660
3661         vmcs_conf->size = vmx_msr_high & 0x1fff;
3662         vmcs_conf->order = get_order(vmcs_conf->size);
3663         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3664         vmcs_conf->revision_id = vmx_msr_low;
3665
3666         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3667         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3668         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3669         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3670         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3671
3672         cpu_has_load_ia32_efer =
3673                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3674                                 VM_ENTRY_LOAD_IA32_EFER)
3675                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3676                                    VM_EXIT_LOAD_IA32_EFER);
3677
3678         cpu_has_load_perf_global_ctrl =
3679                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3680                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3681                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3682                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3683
3684         /*
3685          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3686          * but due to errata below it can't be used. Workaround is to use
3687          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3688          *
3689          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3690          *
3691          * AAK155             (model 26)
3692          * AAP115             (model 30)
3693          * AAT100             (model 37)
3694          * BC86,AAY89,BD102   (model 44)
3695          * BA97               (model 46)
3696          *
3697          */
3698         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3699                 switch (boot_cpu_data.x86_model) {
3700                 case 26:
3701                 case 30:
3702                 case 37:
3703                 case 44:
3704                 case 46:
3705                         cpu_has_load_perf_global_ctrl = false;
3706                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3707                                         "does not work properly. Using workaround\n");
3708                         break;
3709                 default:
3710                         break;
3711                 }
3712         }
3713
3714         if (boot_cpu_has(X86_FEATURE_XSAVES))
3715                 rdmsrl(MSR_IA32_XSS, host_xss);
3716
3717         return 0;
3718 }
3719
3720 static struct vmcs *alloc_vmcs_cpu(int cpu)
3721 {
3722         int node = cpu_to_node(cpu);
3723         struct page *pages;
3724         struct vmcs *vmcs;
3725
3726         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3727         if (!pages)
3728                 return NULL;
3729         vmcs = page_address(pages);
3730         memset(vmcs, 0, vmcs_config.size);
3731         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3732         return vmcs;
3733 }
3734
3735 static struct vmcs *alloc_vmcs(void)
3736 {
3737         return alloc_vmcs_cpu(raw_smp_processor_id());
3738 }
3739
3740 static void free_vmcs(struct vmcs *vmcs)
3741 {
3742         free_pages((unsigned long)vmcs, vmcs_config.order);
3743 }
3744
3745 /*
3746  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3747  */
3748 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3749 {
3750         if (!loaded_vmcs->vmcs)
3751                 return;
3752         loaded_vmcs_clear(loaded_vmcs);
3753         free_vmcs(loaded_vmcs->vmcs);
3754         loaded_vmcs->vmcs = NULL;
3755         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3756 }
3757
3758 static void free_kvm_area(void)
3759 {
3760         int cpu;
3761
3762         for_each_possible_cpu(cpu) {
3763                 free_vmcs(per_cpu(vmxarea, cpu));
3764                 per_cpu(vmxarea, cpu) = NULL;
3765         }
3766 }
3767
3768 static void init_vmcs_shadow_fields(void)
3769 {
3770         int i, j;
3771
3772         /* No checks for read only fields yet */
3773
3774         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3775                 switch (shadow_read_write_fields[i]) {
3776                 case GUEST_BNDCFGS:
3777                         if (!kvm_mpx_supported())
3778                                 continue;
3779                         break;
3780                 default:
3781                         break;
3782                 }
3783
3784                 if (j < i)
3785                         shadow_read_write_fields[j] =
3786                                 shadow_read_write_fields[i];
3787                 j++;
3788         }
3789         max_shadow_read_write_fields = j;
3790
3791         /* shadowed fields guest access without vmexit */
3792         for (i = 0; i < max_shadow_read_write_fields; i++) {
3793                 clear_bit(shadow_read_write_fields[i],
3794                           vmx_vmwrite_bitmap);
3795                 clear_bit(shadow_read_write_fields[i],
3796                           vmx_vmread_bitmap);
3797         }
3798         for (i = 0; i < max_shadow_read_only_fields; i++)
3799                 clear_bit(shadow_read_only_fields[i],
3800                           vmx_vmread_bitmap);
3801 }
3802
3803 static __init int alloc_kvm_area(void)
3804 {
3805         int cpu;
3806
3807         for_each_possible_cpu(cpu) {
3808                 struct vmcs *vmcs;
3809
3810                 vmcs = alloc_vmcs_cpu(cpu);
3811                 if (!vmcs) {
3812                         free_kvm_area();
3813                         return -ENOMEM;
3814                 }
3815
3816                 per_cpu(vmxarea, cpu) = vmcs;
3817         }
3818         return 0;
3819 }
3820
3821 static bool emulation_required(struct kvm_vcpu *vcpu)
3822 {
3823         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3824 }
3825
3826 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3827                 struct kvm_segment *save)
3828 {
3829         if (!emulate_invalid_guest_state) {
3830                 /*
3831                  * CS and SS RPL should be equal during guest entry according
3832                  * to VMX spec, but in reality it is not always so. Since vcpu
3833                  * is in the middle of the transition from real mode to
3834                  * protected mode it is safe to assume that RPL 0 is a good
3835                  * default value.
3836                  */
3837                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3838                         save->selector &= ~SEGMENT_RPL_MASK;
3839                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3840                 save->s = 1;
3841         }
3842         vmx_set_segment(vcpu, save, seg);
3843 }
3844
3845 static void enter_pmode(struct kvm_vcpu *vcpu)
3846 {
3847         unsigned long flags;
3848         struct vcpu_vmx *vmx = to_vmx(vcpu);
3849
3850         /*
3851          * Update real mode segment cache. It may be not up-to-date if sement
3852          * register was written while vcpu was in a guest mode.
3853          */
3854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3855         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3856         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3857         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3858         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3859         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3860
3861         vmx->rmode.vm86_active = 0;
3862
3863         vmx_segment_cache_clear(vmx);
3864
3865         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3866
3867         flags = vmcs_readl(GUEST_RFLAGS);
3868         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3869         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3870         vmcs_writel(GUEST_RFLAGS, flags);
3871
3872         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3873                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3874
3875         update_exception_bitmap(vcpu);
3876
3877         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3878         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3879         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3880         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3881         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3882         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3883 }
3884
3885 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3886 {
3887         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3888         struct kvm_segment var = *save;
3889
3890         var.dpl = 0x3;
3891         if (seg == VCPU_SREG_CS)
3892                 var.type = 0x3;
3893
3894         if (!emulate_invalid_guest_state) {
3895                 var.selector = var.base >> 4;
3896                 var.base = var.base & 0xffff0;
3897                 var.limit = 0xffff;
3898                 var.g = 0;
3899                 var.db = 0;
3900                 var.present = 1;
3901                 var.s = 1;
3902                 var.l = 0;
3903                 var.unusable = 0;
3904                 var.type = 0x3;
3905                 var.avl = 0;
3906                 if (save->base & 0xf)
3907                         printk_once(KERN_WARNING "kvm: segment base is not "
3908                                         "paragraph aligned when entering "
3909                                         "protected mode (seg=%d)", seg);
3910         }
3911
3912         vmcs_write16(sf->selector, var.selector);
3913         vmcs_writel(sf->base, var.base);
3914         vmcs_write32(sf->limit, var.limit);
3915         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3916 }
3917
3918 static void enter_rmode(struct kvm_vcpu *vcpu)
3919 {
3920         unsigned long flags;
3921         struct vcpu_vmx *vmx = to_vmx(vcpu);
3922
3923         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3924         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3925         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3926         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3927         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3928         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3929         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3930
3931         vmx->rmode.vm86_active = 1;
3932
3933         /*
3934          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3935          * vcpu. Warn the user that an update is overdue.
3936          */
3937         if (!vcpu->kvm->arch.tss_addr)
3938                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3939                              "called before entering vcpu\n");
3940
3941         vmx_segment_cache_clear(vmx);
3942
3943         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3944         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3945         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3946
3947         flags = vmcs_readl(GUEST_RFLAGS);
3948         vmx->rmode.save_rflags = flags;
3949
3950         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3951
3952         vmcs_writel(GUEST_RFLAGS, flags);
3953         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3954         update_exception_bitmap(vcpu);
3955
3956         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3957         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3958         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3959         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3960         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3961         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3962
3963         kvm_mmu_reset_context(vcpu);
3964 }
3965
3966 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3967 {
3968         struct vcpu_vmx *vmx = to_vmx(vcpu);
3969         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3970
3971         if (!msr)
3972                 return;
3973
3974         /*
3975          * Force kernel_gs_base reloading before EFER changes, as control
3976          * of this msr depends on is_long_mode().
3977          */
3978         vmx_load_host_state(to_vmx(vcpu));
3979         vcpu->arch.efer = efer;
3980         if (efer & EFER_LMA) {
3981                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3982                 msr->data = efer;
3983         } else {
3984                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3985
3986                 msr->data = efer & ~EFER_LME;
3987         }
3988         setup_msrs(vmx);
3989 }
3990
3991 #ifdef CONFIG_X86_64
3992
3993 static void enter_lmode(struct kvm_vcpu *vcpu)
3994 {
3995         u32 guest_tr_ar;
3996
3997         vmx_segment_cache_clear(to_vmx(vcpu));
3998
3999         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4000         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4001                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4002                                      __func__);
4003                 vmcs_write32(GUEST_TR_AR_BYTES,
4004                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4005                              | VMX_AR_TYPE_BUSY_64_TSS);
4006         }
4007         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4008 }
4009
4010 static void exit_lmode(struct kvm_vcpu *vcpu)
4011 {
4012         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4013         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4014 }
4015
4016 #endif
4017
4018 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4019 {
4020         if (enable_ept) {
4021                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4022                         return;
4023                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4024         } else {
4025                 vpid_sync_context(vpid);
4026         }
4027 }
4028
4029 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4030 {
4031         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4032 }
4033
4034 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4035 {
4036         if (enable_ept)
4037                 vmx_flush_tlb(vcpu);
4038 }
4039
4040 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4041 {
4042         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4043
4044         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4045         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4046 }
4047
4048 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4049 {
4050         if (enable_ept && is_paging(vcpu))
4051                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4052         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4053 }
4054
4055 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4056 {
4057         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4058
4059         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4060         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4061 }
4062
4063 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4064 {
4065         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4066
4067         if (!test_bit(VCPU_EXREG_PDPTR,
4068                       (unsigned long *)&vcpu->arch.regs_dirty))
4069                 return;
4070
4071         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4072                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4073                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4074                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4075                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4076         }
4077 }
4078
4079 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4080 {
4081         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4082
4083         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4084                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4085                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4086                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4087                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4088         }
4089
4090         __set_bit(VCPU_EXREG_PDPTR,
4091                   (unsigned long *)&vcpu->arch.regs_avail);
4092         __set_bit(VCPU_EXREG_PDPTR,
4093                   (unsigned long *)&vcpu->arch.regs_dirty);
4094 }
4095
4096 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4097 {
4098         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4099         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4100         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4101
4102         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4103                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4104             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4105                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4106
4107         return fixed_bits_valid(val, fixed0, fixed1);
4108 }
4109
4110 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4111 {
4112         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4113         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4114
4115         return fixed_bits_valid(val, fixed0, fixed1);
4116 }
4117
4118 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4119 {
4120         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4121         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4122
4123         return fixed_bits_valid(val, fixed0, fixed1);
4124 }
4125
4126 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4127 #define nested_guest_cr4_valid  nested_cr4_valid
4128 #define nested_host_cr4_valid   nested_cr4_valid
4129
4130 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4131
4132 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4133                                         unsigned long cr0,
4134                                         struct kvm_vcpu *vcpu)
4135 {
4136         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4137                 vmx_decache_cr3(vcpu);
4138         if (!(cr0 & X86_CR0_PG)) {
4139                 /* From paging/starting to nonpaging */
4140                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4141                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4142                              (CPU_BASED_CR3_LOAD_EXITING |
4143                               CPU_BASED_CR3_STORE_EXITING));
4144                 vcpu->arch.cr0 = cr0;
4145                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4146         } else if (!is_paging(vcpu)) {
4147                 /* From nonpaging to paging */
4148                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4149                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4150                              ~(CPU_BASED_CR3_LOAD_EXITING |
4151                                CPU_BASED_CR3_STORE_EXITING));
4152                 vcpu->arch.cr0 = cr0;
4153                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4154         }
4155
4156         if (!(cr0 & X86_CR0_WP))
4157                 *hw_cr0 &= ~X86_CR0_WP;
4158 }
4159
4160 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4161 {
4162         struct vcpu_vmx *vmx = to_vmx(vcpu);
4163         unsigned long hw_cr0;
4164
4165         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4166         if (enable_unrestricted_guest)
4167                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4168         else {
4169                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4170
4171                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4172                         enter_pmode(vcpu);
4173
4174                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4175                         enter_rmode(vcpu);
4176         }
4177
4178 #ifdef CONFIG_X86_64
4179         if (vcpu->arch.efer & EFER_LME) {
4180                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4181                         enter_lmode(vcpu);
4182                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4183                         exit_lmode(vcpu);
4184         }
4185 #endif
4186
4187         if (enable_ept)
4188                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4189
4190         vmcs_writel(CR0_READ_SHADOW, cr0);
4191         vmcs_writel(GUEST_CR0, hw_cr0);
4192         vcpu->arch.cr0 = cr0;
4193
4194         /* depends on vcpu->arch.cr0 to be set to a new value */
4195         vmx->emulation_required = emulation_required(vcpu);
4196 }
4197
4198 static u64 construct_eptp(unsigned long root_hpa)
4199 {
4200         u64 eptp;
4201
4202         /* TODO write the value reading from MSR */
4203         eptp = VMX_EPT_DEFAULT_MT |
4204                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4205         if (enable_ept_ad_bits)
4206                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4207         eptp |= (root_hpa & PAGE_MASK);
4208
4209         return eptp;
4210 }
4211
4212 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4213 {
4214         unsigned long guest_cr3;
4215         u64 eptp;
4216
4217         guest_cr3 = cr3;
4218         if (enable_ept) {
4219                 eptp = construct_eptp(cr3);
4220                 vmcs_write64(EPT_POINTER, eptp);
4221                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4222                         guest_cr3 = kvm_read_cr3(vcpu);
4223                 else
4224                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4225                 ept_load_pdptrs(vcpu);
4226         }
4227
4228         vmx_flush_tlb(vcpu);
4229         vmcs_writel(GUEST_CR3, guest_cr3);
4230 }
4231
4232 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4233 {
4234         /*
4235          * Pass through host's Machine Check Enable value to hw_cr4, which
4236          * is in force while we are in guest mode.  Do not let guests control
4237          * this bit, even if host CR4.MCE == 0.
4238          */
4239         unsigned long hw_cr4 =
4240                 (cr4_read_shadow() & X86_CR4_MCE) |
4241                 (cr4 & ~X86_CR4_MCE) |
4242                 (to_vmx(vcpu)->rmode.vm86_active ?
4243                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4244
4245         if (cr4 & X86_CR4_VMXE) {
4246                 /*
4247                  * To use VMXON (and later other VMX instructions), a guest
4248                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4249                  * So basically the check on whether to allow nested VMX
4250                  * is here.
4251                  */
4252                 if (!nested_vmx_allowed(vcpu))
4253                         return 1;
4254         }
4255
4256         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4257                 return 1;
4258
4259         vcpu->arch.cr4 = cr4;
4260         if (enable_ept) {
4261                 if (!is_paging(vcpu)) {
4262                         hw_cr4 &= ~X86_CR4_PAE;
4263                         hw_cr4 |= X86_CR4_PSE;
4264                 } else if (!(cr4 & X86_CR4_PAE)) {
4265                         hw_cr4 &= ~X86_CR4_PAE;
4266                 }
4267         }
4268
4269         if (!enable_unrestricted_guest && !is_paging(vcpu))
4270                 /*
4271                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4272                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4273                  * to be manually disabled when guest switches to non-paging
4274                  * mode.
4275                  *
4276                  * If !enable_unrestricted_guest, the CPU is always running
4277                  * with CR0.PG=1 and CR4 needs to be modified.
4278                  * If enable_unrestricted_guest, the CPU automatically
4279                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4280                  */
4281                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4282
4283         vmcs_writel(CR4_READ_SHADOW, cr4);
4284         vmcs_writel(GUEST_CR4, hw_cr4);
4285         return 0;
4286 }
4287
4288 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4289                             struct kvm_segment *var, int seg)
4290 {
4291         struct vcpu_vmx *vmx = to_vmx(vcpu);
4292         u32 ar;
4293
4294         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4295                 *var = vmx->rmode.segs[seg];
4296                 if (seg == VCPU_SREG_TR
4297                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4298                         return;
4299                 var->base = vmx_read_guest_seg_base(vmx, seg);
4300                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4301                 return;
4302         }
4303         var->base = vmx_read_guest_seg_base(vmx, seg);
4304         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4305         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4306         ar = vmx_read_guest_seg_ar(vmx, seg);
4307         var->unusable = (ar >> 16) & 1;
4308         var->type = ar & 15;
4309         var->s = (ar >> 4) & 1;
4310         var->dpl = (ar >> 5) & 3;
4311         /*
4312          * Some userspaces do not preserve unusable property. Since usable
4313          * segment has to be present according to VMX spec we can use present
4314          * property to amend userspace bug by making unusable segment always
4315          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4316          * segment as unusable.
4317          */
4318         var->present = !var->unusable;
4319         var->avl = (ar >> 12) & 1;
4320         var->l = (ar >> 13) & 1;
4321         var->db = (ar >> 14) & 1;
4322         var->g = (ar >> 15) & 1;
4323 }
4324
4325 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4326 {
4327         struct kvm_segment s;
4328
4329         if (to_vmx(vcpu)->rmode.vm86_active) {
4330                 vmx_get_segment(vcpu, &s, seg);
4331                 return s.base;
4332         }
4333         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4334 }
4335
4336 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4337 {
4338         struct vcpu_vmx *vmx = to_vmx(vcpu);
4339
4340         if (unlikely(vmx->rmode.vm86_active))
4341                 return 0;
4342         else {
4343                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4344                 return VMX_AR_DPL(ar);
4345         }
4346 }
4347
4348 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4349 {
4350         u32 ar;
4351
4352         if (var->unusable || !var->present)
4353                 ar = 1 << 16;
4354         else {
4355                 ar = var->type & 15;
4356                 ar |= (var->s & 1) << 4;
4357                 ar |= (var->dpl & 3) << 5;
4358                 ar |= (var->present & 1) << 7;
4359                 ar |= (var->avl & 1) << 12;
4360                 ar |= (var->l & 1) << 13;
4361                 ar |= (var->db & 1) << 14;
4362                 ar |= (var->g & 1) << 15;
4363         }
4364
4365         return ar;
4366 }
4367
4368 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4369                             struct kvm_segment *var, int seg)
4370 {
4371         struct vcpu_vmx *vmx = to_vmx(vcpu);
4372         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4373
4374         vmx_segment_cache_clear(vmx);
4375
4376         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4377                 vmx->rmode.segs[seg] = *var;
4378                 if (seg == VCPU_SREG_TR)
4379                         vmcs_write16(sf->selector, var->selector);
4380                 else if (var->s)
4381                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4382                 goto out;
4383         }
4384
4385         vmcs_writel(sf->base, var->base);
4386         vmcs_write32(sf->limit, var->limit);
4387         vmcs_write16(sf->selector, var->selector);
4388
4389         /*
4390          *   Fix the "Accessed" bit in AR field of segment registers for older
4391          * qemu binaries.
4392          *   IA32 arch specifies that at the time of processor reset the
4393          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4394          * is setting it to 0 in the userland code. This causes invalid guest
4395          * state vmexit when "unrestricted guest" mode is turned on.
4396          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4397          * tree. Newer qemu binaries with that qemu fix would not need this
4398          * kvm hack.
4399          */
4400         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4401                 var->type |= 0x1; /* Accessed */
4402
4403         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4404
4405 out:
4406         vmx->emulation_required = emulation_required(vcpu);
4407 }
4408
4409 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4410 {
4411         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4412
4413         *db = (ar >> 14) & 1;
4414         *l = (ar >> 13) & 1;
4415 }
4416
4417 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4418 {
4419         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4420         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4421 }
4422
4423 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4424 {
4425         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4426         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4427 }
4428
4429 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4430 {
4431         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4432         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4433 }
4434
4435 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4436 {
4437         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4438         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4439 }
4440
4441 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4442 {
4443         struct kvm_segment var;
4444         u32 ar;
4445
4446         vmx_get_segment(vcpu, &var, seg);
4447         var.dpl = 0x3;
4448         if (seg == VCPU_SREG_CS)
4449                 var.type = 0x3;
4450         ar = vmx_segment_access_rights(&var);
4451
4452         if (var.base != (var.selector << 4))
4453                 return false;
4454         if (var.limit != 0xffff)
4455                 return false;
4456         if (ar != 0xf3)
4457                 return false;
4458
4459         return true;
4460 }
4461
4462 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4463 {
4464         struct kvm_segment cs;
4465         unsigned int cs_rpl;
4466
4467         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4468         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4469
4470         if (cs.unusable)
4471                 return false;
4472         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4473                 return false;
4474         if (!cs.s)
4475                 return false;
4476         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4477                 if (cs.dpl > cs_rpl)
4478                         return false;
4479         } else {
4480                 if (cs.dpl != cs_rpl)
4481                         return false;
4482         }
4483         if (!cs.present)
4484                 return false;
4485
4486         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4487         return true;
4488 }
4489
4490 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4491 {
4492         struct kvm_segment ss;
4493         unsigned int ss_rpl;
4494
4495         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4496         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4497
4498         if (ss.unusable)
4499                 return true;
4500         if (ss.type != 3 && ss.type != 7)
4501                 return false;
4502         if (!ss.s)
4503                 return false;
4504         if (ss.dpl != ss_rpl) /* DPL != RPL */
4505                 return false;
4506         if (!ss.present)
4507                 return false;
4508
4509         return true;
4510 }
4511
4512 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4513 {
4514         struct kvm_segment var;
4515         unsigned int rpl;
4516
4517         vmx_get_segment(vcpu, &var, seg);
4518         rpl = var.selector & SEGMENT_RPL_MASK;
4519
4520         if (var.unusable)
4521                 return true;
4522         if (!var.s)
4523                 return false;
4524         if (!var.present)
4525                 return false;
4526         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4527                 if (var.dpl < rpl) /* DPL < RPL */
4528                         return false;
4529         }
4530
4531         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4532          * rights flags
4533          */
4534         return true;
4535 }
4536
4537 static bool tr_valid(struct kvm_vcpu *vcpu)
4538 {
4539         struct kvm_segment tr;
4540
4541         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4542
4543         if (tr.unusable)
4544                 return false;
4545         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4546                 return false;
4547         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4548                 return false;
4549         if (!tr.present)
4550                 return false;
4551
4552         return true;
4553 }
4554
4555 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4556 {
4557         struct kvm_segment ldtr;
4558
4559         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4560
4561         if (ldtr.unusable)
4562                 return true;
4563         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4564                 return false;
4565         if (ldtr.type != 2)
4566                 return false;
4567         if (!ldtr.present)
4568                 return false;
4569
4570         return true;
4571 }
4572
4573 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4574 {
4575         struct kvm_segment cs, ss;
4576
4577         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4578         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4579
4580         return ((cs.selector & SEGMENT_RPL_MASK) ==
4581                  (ss.selector & SEGMENT_RPL_MASK));
4582 }
4583
4584 /*
4585  * Check if guest state is valid. Returns true if valid, false if
4586  * not.
4587  * We assume that registers are always usable
4588  */
4589 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4590 {
4591         if (enable_unrestricted_guest)
4592                 return true;
4593
4594         /* real mode guest state checks */
4595         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4596                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4597                         return false;
4598                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4599                         return false;
4600                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4601                         return false;
4602                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4603                         return false;
4604                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4605                         return false;
4606                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4607                         return false;
4608         } else {
4609         /* protected mode guest state checks */
4610                 if (!cs_ss_rpl_check(vcpu))
4611                         return false;
4612                 if (!code_segment_valid(vcpu))
4613                         return false;
4614                 if (!stack_segment_valid(vcpu))
4615                         return false;
4616                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4617                         return false;
4618                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4619                         return false;
4620                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4621                         return false;
4622                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4623                         return false;
4624                 if (!tr_valid(vcpu))
4625                         return false;
4626                 if (!ldtr_valid(vcpu))
4627                         return false;
4628         }
4629         /* TODO:
4630          * - Add checks on RIP
4631          * - Add checks on RFLAGS
4632          */
4633
4634         return true;
4635 }
4636
4637 static int init_rmode_tss(struct kvm *kvm)
4638 {
4639         gfn_t fn;
4640         u16 data = 0;
4641         int idx, r;
4642
4643         idx = srcu_read_lock(&kvm->srcu);
4644         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4645         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4646         if (r < 0)
4647                 goto out;
4648         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4649         r = kvm_write_guest_page(kvm, fn++, &data,
4650                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4651         if (r < 0)
4652                 goto out;
4653         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4654         if (r < 0)
4655                 goto out;
4656         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4657         if (r < 0)
4658                 goto out;
4659         data = ~0;
4660         r = kvm_write_guest_page(kvm, fn, &data,
4661                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4662                                  sizeof(u8));
4663 out:
4664         srcu_read_unlock(&kvm->srcu, idx);
4665         return r;
4666 }
4667
4668 static int init_rmode_identity_map(struct kvm *kvm)
4669 {
4670         int i, idx, r = 0;
4671         kvm_pfn_t identity_map_pfn;
4672         u32 tmp;
4673
4674         if (!enable_ept)
4675                 return 0;
4676
4677         /* Protect kvm->arch.ept_identity_pagetable_done. */
4678         mutex_lock(&kvm->slots_lock);
4679
4680         if (likely(kvm->arch.ept_identity_pagetable_done))
4681                 goto out2;
4682
4683         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4684
4685         r = alloc_identity_pagetable(kvm);
4686         if (r < 0)
4687                 goto out2;
4688
4689         idx = srcu_read_lock(&kvm->srcu);
4690         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4691         if (r < 0)
4692                 goto out;
4693         /* Set up identity-mapping pagetable for EPT in real mode */
4694         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4695                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4696                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4697                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4698                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4699                 if (r < 0)
4700                         goto out;
4701         }
4702         kvm->arch.ept_identity_pagetable_done = true;
4703
4704 out:
4705         srcu_read_unlock(&kvm->srcu, idx);
4706
4707 out2:
4708         mutex_unlock(&kvm->slots_lock);
4709         return r;
4710 }
4711
4712 static void seg_setup(int seg)
4713 {
4714         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4715         unsigned int ar;
4716
4717         vmcs_write16(sf->selector, 0);
4718         vmcs_writel(sf->base, 0);
4719         vmcs_write32(sf->limit, 0xffff);
4720         ar = 0x93;
4721         if (seg == VCPU_SREG_CS)
4722                 ar |= 0x08; /* code segment */
4723
4724         vmcs_write32(sf->ar_bytes, ar);
4725 }
4726
4727 static int alloc_apic_access_page(struct kvm *kvm)
4728 {
4729         struct page *page;
4730         int r = 0;
4731
4732         mutex_lock(&kvm->slots_lock);
4733         if (kvm->arch.apic_access_page_done)
4734                 goto out;
4735         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4736                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4737         if (r)
4738                 goto out;
4739
4740         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4741         if (is_error_page(page)) {
4742                 r = -EFAULT;
4743                 goto out;
4744         }
4745
4746         /*
4747          * Do not pin the page in memory, so that memory hot-unplug
4748          * is able to migrate it.
4749          */
4750         put_page(page);
4751         kvm->arch.apic_access_page_done = true;
4752 out:
4753         mutex_unlock(&kvm->slots_lock);
4754         return r;
4755 }
4756
4757 static int alloc_identity_pagetable(struct kvm *kvm)
4758 {
4759         /* Called with kvm->slots_lock held. */
4760
4761         int r = 0;
4762
4763         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4764
4765         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4766                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4767
4768         return r;
4769 }
4770
4771 static int allocate_vpid(void)
4772 {
4773         int vpid;
4774
4775         if (!enable_vpid)
4776                 return 0;
4777         spin_lock(&vmx_vpid_lock);
4778         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4779         if (vpid < VMX_NR_VPIDS)
4780                 __set_bit(vpid, vmx_vpid_bitmap);
4781         else
4782                 vpid = 0;
4783         spin_unlock(&vmx_vpid_lock);
4784         return vpid;
4785 }
4786
4787 static void free_vpid(int vpid)
4788 {
4789         if (!enable_vpid || vpid == 0)
4790                 return;
4791         spin_lock(&vmx_vpid_lock);
4792         __clear_bit(vpid, vmx_vpid_bitmap);
4793         spin_unlock(&vmx_vpid_lock);
4794 }
4795
4796 #define MSR_TYPE_R      1
4797 #define MSR_TYPE_W      2
4798 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4799                                                 u32 msr, int type)
4800 {
4801         int f = sizeof(unsigned long);
4802
4803         if (!cpu_has_vmx_msr_bitmap())
4804                 return;
4805
4806         /*
4807          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4808          * have the write-low and read-high bitmap offsets the wrong way round.
4809          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4810          */
4811         if (msr <= 0x1fff) {
4812                 if (type & MSR_TYPE_R)
4813                         /* read-low */
4814                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4815
4816                 if (type & MSR_TYPE_W)
4817                         /* write-low */
4818                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4819
4820         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4821                 msr &= 0x1fff;
4822                 if (type & MSR_TYPE_R)
4823                         /* read-high */
4824                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4825
4826                 if (type & MSR_TYPE_W)
4827                         /* write-high */
4828                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4829
4830         }
4831 }
4832
4833 /*
4834  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4835  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4836  */
4837 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4838                                                unsigned long *msr_bitmap_nested,
4839                                                u32 msr, int type)
4840 {
4841         int f = sizeof(unsigned long);
4842
4843         if (!cpu_has_vmx_msr_bitmap()) {
4844                 WARN_ON(1);
4845                 return;
4846         }
4847
4848         /*
4849          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4850          * have the write-low and read-high bitmap offsets the wrong way round.
4851          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4852          */
4853         if (msr <= 0x1fff) {
4854                 if (type & MSR_TYPE_R &&
4855                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4856                         /* read-low */
4857                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4858
4859                 if (type & MSR_TYPE_W &&
4860                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4861                         /* write-low */
4862                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4863
4864         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4865                 msr &= 0x1fff;
4866                 if (type & MSR_TYPE_R &&
4867                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4868                         /* read-high */
4869                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4870
4871                 if (type & MSR_TYPE_W &&
4872                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4873                         /* write-high */
4874                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4875
4876         }
4877 }
4878
4879 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4880 {
4881         if (!longmode_only)
4882                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4883                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4884         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4885                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4886 }
4887
4888 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4889 {
4890         if (apicv_active) {
4891                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4892                                 msr, type);
4893                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4894                                 msr, type);
4895         } else {
4896                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4897                                 msr, type);
4898                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4899                                 msr, type);
4900         }
4901 }
4902
4903 static bool vmx_get_enable_apicv(void)
4904 {
4905         return enable_apicv;
4906 }
4907
4908 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4909 {
4910         struct vcpu_vmx *vmx = to_vmx(vcpu);
4911         int max_irr;
4912         void *vapic_page;
4913         u16 status;
4914
4915         if (vmx->nested.pi_desc &&
4916             vmx->nested.pi_pending) {
4917                 vmx->nested.pi_pending = false;
4918                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4919                         return;
4920
4921                 max_irr = find_last_bit(
4922                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4923
4924                 if (max_irr == 256)
4925                         return;
4926
4927                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4928                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4929                 kunmap(vmx->nested.virtual_apic_page);
4930
4931                 status = vmcs_read16(GUEST_INTR_STATUS);
4932                 if ((u8)max_irr > ((u8)status & 0xff)) {
4933                         status &= ~0xff;
4934                         status |= (u8)max_irr;
4935                         vmcs_write16(GUEST_INTR_STATUS, status);
4936                 }
4937         }
4938 }
4939
4940 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4941 {
4942 #ifdef CONFIG_SMP
4943         if (vcpu->mode == IN_GUEST_MODE) {
4944                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4945
4946                 /*
4947                  * Currently, we don't support urgent interrupt,
4948                  * all interrupts are recognized as non-urgent
4949                  * interrupt, so we cannot post interrupts when
4950                  * 'SN' is set.
4951                  *
4952                  * If the vcpu is in guest mode, it means it is
4953                  * running instead of being scheduled out and
4954                  * waiting in the run queue, and that's the only
4955                  * case when 'SN' is set currently, warning if
4956                  * 'SN' is set.
4957                  */
4958                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4959
4960                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4961                                 POSTED_INTR_VECTOR);
4962                 return true;
4963         }
4964 #endif
4965         return false;
4966 }
4967
4968 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4969                                                 int vector)
4970 {
4971         struct vcpu_vmx *vmx = to_vmx(vcpu);
4972
4973         if (is_guest_mode(vcpu) &&
4974             vector == vmx->nested.posted_intr_nv) {
4975                 /* the PIR and ON have been set by L1. */
4976                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4977                 /*
4978                  * If a posted intr is not recognized by hardware,
4979                  * we will accomplish it in the next vmentry.
4980                  */
4981                 vmx->nested.pi_pending = true;
4982                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4983                 return 0;
4984         }
4985         return -1;
4986 }
4987 /*
4988  * Send interrupt to vcpu via posted interrupt way.
4989  * 1. If target vcpu is running(non-root mode), send posted interrupt
4990  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4991  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4992  * interrupt from PIR in next vmentry.
4993  */
4994 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4995 {
4996         struct vcpu_vmx *vmx = to_vmx(vcpu);
4997         int r;
4998
4999         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5000         if (!r)
5001                 return;
5002
5003         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5004                 return;
5005
5006         /* If a previous notification has sent the IPI, nothing to do.  */
5007         if (pi_test_and_set_on(&vmx->pi_desc))
5008                 return;
5009
5010         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5011                 kvm_vcpu_kick(vcpu);
5012 }
5013
5014 /*
5015  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5016  * will not change in the lifetime of the guest.
5017  * Note that host-state that does change is set elsewhere. E.g., host-state
5018  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5019  */
5020 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5021 {
5022         u32 low32, high32;
5023         unsigned long tmpl;
5024         struct desc_ptr dt;
5025         unsigned long cr0, cr4;
5026
5027         cr0 = read_cr0();
5028         WARN_ON(cr0 & X86_CR0_TS);
5029         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5030         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5031
5032         /* Save the most likely value for this task's CR4 in the VMCS. */
5033         cr4 = cr4_read_shadow();
5034         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5035         vmx->host_state.vmcs_host_cr4 = cr4;
5036
5037         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5038 #ifdef CONFIG_X86_64
5039         /*
5040          * Load null selectors, so we can avoid reloading them in
5041          * __vmx_load_host_state(), in case userspace uses the null selectors
5042          * too (the expected case).
5043          */
5044         vmcs_write16(HOST_DS_SELECTOR, 0);
5045         vmcs_write16(HOST_ES_SELECTOR, 0);
5046 #else
5047         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5048         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5049 #endif
5050         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5051         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5052
5053         native_store_idt(&dt);
5054         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5055         vmx->host_idt_base = dt.address;
5056
5057         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5058
5059         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5060         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5061         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5062         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5063
5064         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5065                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5066                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5067         }
5068 }
5069
5070 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5071 {
5072         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5073         if (enable_ept)
5074                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5075         if (is_guest_mode(&vmx->vcpu))
5076                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5077                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5078         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5079 }
5080
5081 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5082 {
5083         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5084
5085         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5086                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5087         /* Enable the preemption timer dynamically */
5088         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5089         return pin_based_exec_ctrl;
5090 }
5091
5092 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5093 {
5094         struct vcpu_vmx *vmx = to_vmx(vcpu);
5095
5096         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5097         if (cpu_has_secondary_exec_ctrls()) {
5098                 if (kvm_vcpu_apicv_active(vcpu))
5099                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5100                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5101                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5102                 else
5103                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5104                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5105                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5106         }
5107
5108         if (cpu_has_vmx_msr_bitmap())
5109                 vmx_set_msr_bitmap(vcpu);
5110 }
5111
5112 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5113 {
5114         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5115
5116         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5117                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5118
5119         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5120                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5121 #ifdef CONFIG_X86_64
5122                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5123                                 CPU_BASED_CR8_LOAD_EXITING;
5124 #endif
5125         }
5126         if (!enable_ept)
5127                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5128                                 CPU_BASED_CR3_LOAD_EXITING  |
5129                                 CPU_BASED_INVLPG_EXITING;
5130         return exec_control;
5131 }
5132
5133 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5134 {
5135         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5136         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5137                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5138         if (vmx->vpid == 0)
5139                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5140         if (!enable_ept) {
5141                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5142                 enable_unrestricted_guest = 0;
5143                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5144                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5145         }
5146         if (!enable_unrestricted_guest)
5147                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5148         if (!ple_gap)
5149                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5150         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5151                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5152                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5153         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5154         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5155            (handle_vmptrld).
5156            We can NOT enable shadow_vmcs here because we don't have yet
5157            a current VMCS12
5158         */
5159         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5160
5161         if (!enable_pml)
5162                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5163
5164         return exec_control;
5165 }
5166
5167 static void ept_set_mmio_spte_mask(void)
5168 {
5169         /*
5170          * EPT Misconfigurations can be generated if the value of bits 2:0
5171          * of an EPT paging-structure entry is 110b (write/execute).
5172          */
5173         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5174 }
5175
5176 #define VMX_XSS_EXIT_BITMAP 0
5177 /*
5178  * Sets up the vmcs for emulated real mode.
5179  */
5180 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5181 {
5182 #ifdef CONFIG_X86_64
5183         unsigned long a;
5184 #endif
5185         int i;
5186
5187         /* I/O */
5188         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5189         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5190
5191         if (enable_shadow_vmcs) {
5192                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5193                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5194         }
5195         if (cpu_has_vmx_msr_bitmap())
5196                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5197
5198         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5199
5200         /* Control */
5201         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5202         vmx->hv_deadline_tsc = -1;
5203
5204         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5205
5206         if (cpu_has_secondary_exec_ctrls()) {
5207                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5208                                 vmx_secondary_exec_control(vmx));
5209         }
5210
5211         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5212                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5213                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5214                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5215                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5216
5217                 vmcs_write16(GUEST_INTR_STATUS, 0);
5218
5219                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5220                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5221         }
5222
5223         if (ple_gap) {
5224                 vmcs_write32(PLE_GAP, ple_gap);
5225                 vmx->ple_window = ple_window;
5226                 vmx->ple_window_dirty = true;
5227         }
5228
5229         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5230         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5231         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5232
5233         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5234         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5235         vmx_set_constant_host_state(vmx);
5236 #ifdef CONFIG_X86_64
5237         rdmsrl(MSR_FS_BASE, a);
5238         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5239         rdmsrl(MSR_GS_BASE, a);
5240         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5241 #else
5242         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5243         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5244 #endif
5245
5246         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5247         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5248         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5249         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5250         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5251
5252         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5253                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5254
5255         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5256                 u32 index = vmx_msr_index[i];
5257                 u32 data_low, data_high;
5258                 int j = vmx->nmsrs;
5259
5260                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5261                         continue;
5262                 if (wrmsr_safe(index, data_low, data_high) < 0)
5263                         continue;
5264                 vmx->guest_msrs[j].index = i;
5265                 vmx->guest_msrs[j].data = 0;
5266                 vmx->guest_msrs[j].mask = -1ull;
5267                 ++vmx->nmsrs;
5268         }
5269
5270
5271         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5272
5273         /* 22.2.1, 20.8.1 */
5274         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5275
5276         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5277         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5278
5279         set_cr4_guest_host_mask(vmx);
5280
5281         if (vmx_xsaves_supported())
5282                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5283
5284         if (enable_pml) {
5285                 ASSERT(vmx->pml_pg);
5286                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5287                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5288         }
5289
5290         return 0;
5291 }
5292
5293 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5294 {
5295         struct vcpu_vmx *vmx = to_vmx(vcpu);
5296         struct msr_data apic_base_msr;
5297         u64 cr0;
5298
5299         vmx->rmode.vm86_active = 0;
5300
5301         vmx->soft_vnmi_blocked = 0;
5302
5303         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5304         kvm_set_cr8(vcpu, 0);
5305
5306         if (!init_event) {
5307                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5308                                      MSR_IA32_APICBASE_ENABLE;
5309                 if (kvm_vcpu_is_reset_bsp(vcpu))
5310                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5311                 apic_base_msr.host_initiated = true;
5312                 kvm_set_apic_base(vcpu, &apic_base_msr);
5313         }
5314
5315         vmx_segment_cache_clear(vmx);
5316
5317         seg_setup(VCPU_SREG_CS);
5318         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5319         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5320
5321         seg_setup(VCPU_SREG_DS);
5322         seg_setup(VCPU_SREG_ES);
5323         seg_setup(VCPU_SREG_FS);
5324         seg_setup(VCPU_SREG_GS);
5325         seg_setup(VCPU_SREG_SS);
5326
5327         vmcs_write16(GUEST_TR_SELECTOR, 0);
5328         vmcs_writel(GUEST_TR_BASE, 0);
5329         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5330         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5331
5332         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5333         vmcs_writel(GUEST_LDTR_BASE, 0);
5334         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5335         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5336
5337         if (!init_event) {
5338                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5339                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5340                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5341                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5342         }
5343
5344         vmcs_writel(GUEST_RFLAGS, 0x02);
5345         kvm_rip_write(vcpu, 0xfff0);
5346
5347         vmcs_writel(GUEST_GDTR_BASE, 0);
5348         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5349
5350         vmcs_writel(GUEST_IDTR_BASE, 0);
5351         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5352
5353         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5354         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5355         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5356
5357         setup_msrs(vmx);
5358
5359         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5360
5361         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5362                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5363                 if (cpu_need_tpr_shadow(vcpu))
5364                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5365                                      __pa(vcpu->arch.apic->regs));
5366                 vmcs_write32(TPR_THRESHOLD, 0);
5367         }
5368
5369         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5370
5371         if (kvm_vcpu_apicv_active(vcpu))
5372                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5373
5374         if (vmx->vpid != 0)
5375                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5376
5377         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5378         vmx->vcpu.arch.cr0 = cr0;
5379         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5380         vmx_set_cr4(vcpu, 0);
5381         vmx_set_efer(vcpu, 0);
5382
5383         update_exception_bitmap(vcpu);
5384
5385         vpid_sync_context(vmx->vpid);
5386 }
5387
5388 /*
5389  * In nested virtualization, check if L1 asked to exit on external interrupts.
5390  * For most existing hypervisors, this will always return true.
5391  */
5392 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5393 {
5394         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5395                 PIN_BASED_EXT_INTR_MASK;
5396 }
5397
5398 /*
5399  * In nested virtualization, check if L1 has set
5400  * VM_EXIT_ACK_INTR_ON_EXIT
5401  */
5402 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5403 {
5404         return get_vmcs12(vcpu)->vm_exit_controls &
5405                 VM_EXIT_ACK_INTR_ON_EXIT;
5406 }
5407
5408 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5409 {
5410         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5411                 PIN_BASED_NMI_EXITING;
5412 }
5413
5414 static void enable_irq_window(struct kvm_vcpu *vcpu)
5415 {
5416         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5417                       CPU_BASED_VIRTUAL_INTR_PENDING);
5418 }
5419
5420 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5421 {
5422         if (!cpu_has_virtual_nmis() ||
5423             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5424                 enable_irq_window(vcpu);
5425                 return;
5426         }
5427
5428         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5429                       CPU_BASED_VIRTUAL_NMI_PENDING);
5430 }
5431
5432 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5433 {
5434         struct vcpu_vmx *vmx = to_vmx(vcpu);
5435         uint32_t intr;
5436         int irq = vcpu->arch.interrupt.nr;
5437
5438         trace_kvm_inj_virq(irq);
5439
5440         ++vcpu->stat.irq_injections;
5441         if (vmx->rmode.vm86_active) {
5442                 int inc_eip = 0;
5443                 if (vcpu->arch.interrupt.soft)
5444                         inc_eip = vcpu->arch.event_exit_inst_len;
5445                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5446                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5447                 return;
5448         }
5449         intr = irq | INTR_INFO_VALID_MASK;
5450         if (vcpu->arch.interrupt.soft) {
5451                 intr |= INTR_TYPE_SOFT_INTR;
5452                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5453                              vmx->vcpu.arch.event_exit_inst_len);
5454         } else
5455                 intr |= INTR_TYPE_EXT_INTR;
5456         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5457 }
5458
5459 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5460 {
5461         struct vcpu_vmx *vmx = to_vmx(vcpu);
5462
5463         if (!is_guest_mode(vcpu)) {
5464                 if (!cpu_has_virtual_nmis()) {
5465                         /*
5466                          * Tracking the NMI-blocked state in software is built upon
5467                          * finding the next open IRQ window. This, in turn, depends on
5468                          * well-behaving guests: They have to keep IRQs disabled at
5469                          * least as long as the NMI handler runs. Otherwise we may
5470                          * cause NMI nesting, maybe breaking the guest. But as this is
5471                          * highly unlikely, we can live with the residual risk.
5472                          */
5473                         vmx->soft_vnmi_blocked = 1;
5474                         vmx->vnmi_blocked_time = 0;
5475                 }
5476
5477                 ++vcpu->stat.nmi_injections;
5478                 vmx->nmi_known_unmasked = false;
5479         }
5480
5481         if (vmx->rmode.vm86_active) {
5482                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5483                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5484                 return;
5485         }
5486
5487         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5488                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5489 }
5490
5491 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5492 {
5493         if (!cpu_has_virtual_nmis())
5494                 return to_vmx(vcpu)->soft_vnmi_blocked;
5495         if (to_vmx(vcpu)->nmi_known_unmasked)
5496                 return false;
5497         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5498 }
5499
5500 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5501 {
5502         struct vcpu_vmx *vmx = to_vmx(vcpu);
5503
5504         if (!cpu_has_virtual_nmis()) {
5505                 if (vmx->soft_vnmi_blocked != masked) {
5506                         vmx->soft_vnmi_blocked = masked;
5507                         vmx->vnmi_blocked_time = 0;
5508                 }
5509         } else {
5510                 vmx->nmi_known_unmasked = !masked;
5511                 if (masked)
5512                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5513                                       GUEST_INTR_STATE_NMI);
5514                 else
5515                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5516                                         GUEST_INTR_STATE_NMI);
5517         }
5518 }
5519
5520 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5521 {
5522         if (to_vmx(vcpu)->nested.nested_run_pending)
5523                 return 0;
5524
5525         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5526                 return 0;
5527
5528         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5529                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5530                    | GUEST_INTR_STATE_NMI));
5531 }
5532
5533 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5534 {
5535         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5536                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5537                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5538                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5539 }
5540
5541 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5542 {
5543         int ret;
5544
5545         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5546                                     PAGE_SIZE * 3);
5547         if (ret)
5548                 return ret;
5549         kvm->arch.tss_addr = addr;
5550         return init_rmode_tss(kvm);
5551 }
5552
5553 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5554 {
5555         switch (vec) {
5556         case BP_VECTOR:
5557                 /*
5558                  * Update instruction length as we may reinject the exception
5559                  * from user space while in guest debugging mode.
5560                  */
5561                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5562                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5563                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5564                         return false;
5565                 /* fall through */
5566         case DB_VECTOR:
5567                 if (vcpu->guest_debug &
5568                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5569                         return false;
5570                 /* fall through */
5571         case DE_VECTOR:
5572         case OF_VECTOR:
5573         case BR_VECTOR:
5574         case UD_VECTOR:
5575         case DF_VECTOR:
5576         case SS_VECTOR:
5577         case GP_VECTOR:
5578         case MF_VECTOR:
5579                 return true;
5580         break;
5581         }
5582         return false;
5583 }
5584
5585 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5586                                   int vec, u32 err_code)
5587 {
5588         /*
5589          * Instruction with address size override prefix opcode 0x67
5590          * Cause the #SS fault with 0 error code in VM86 mode.
5591          */
5592         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5593                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5594                         if (vcpu->arch.halt_request) {
5595                                 vcpu->arch.halt_request = 0;
5596                                 return kvm_vcpu_halt(vcpu);
5597                         }
5598                         return 1;
5599                 }
5600                 return 0;
5601         }
5602
5603         /*
5604          * Forward all other exceptions that are valid in real mode.
5605          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5606          *        the required debugging infrastructure rework.
5607          */
5608         kvm_queue_exception(vcpu, vec);
5609         return 1;
5610 }
5611
5612 /*
5613  * Trigger machine check on the host. We assume all the MSRs are already set up
5614  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5615  * We pass a fake environment to the machine check handler because we want
5616  * the guest to be always treated like user space, no matter what context
5617  * it used internally.
5618  */
5619 static void kvm_machine_check(void)
5620 {
5621 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5622         struct pt_regs regs = {
5623                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5624                 .flags = X86_EFLAGS_IF,
5625         };
5626
5627         do_machine_check(&regs, 0);
5628 #endif
5629 }
5630
5631 static int handle_machine_check(struct kvm_vcpu *vcpu)
5632 {
5633         /* already handled by vcpu_run */
5634         return 1;
5635 }
5636
5637 static int handle_exception(struct kvm_vcpu *vcpu)
5638 {
5639         struct vcpu_vmx *vmx = to_vmx(vcpu);
5640         struct kvm_run *kvm_run = vcpu->run;
5641         u32 intr_info, ex_no, error_code;
5642         unsigned long cr2, rip, dr6;
5643         u32 vect_info;
5644         enum emulation_result er;
5645
5646         vect_info = vmx->idt_vectoring_info;
5647         intr_info = vmx->exit_intr_info;
5648
5649         if (is_machine_check(intr_info))
5650                 return handle_machine_check(vcpu);
5651
5652         if (is_nmi(intr_info))
5653                 return 1;  /* already handled by vmx_vcpu_run() */
5654
5655         if (is_invalid_opcode(intr_info)) {
5656                 if (is_guest_mode(vcpu)) {
5657                         kvm_queue_exception(vcpu, UD_VECTOR);
5658                         return 1;
5659                 }
5660                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5661                 if (er != EMULATE_DONE)
5662                         kvm_queue_exception(vcpu, UD_VECTOR);
5663                 return 1;
5664         }
5665
5666         error_code = 0;
5667         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5668                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5669
5670         /*
5671          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5672          * MMIO, it is better to report an internal error.
5673          * See the comments in vmx_handle_exit.
5674          */
5675         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5676             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5677                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5678                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5679                 vcpu->run->internal.ndata = 3;
5680                 vcpu->run->internal.data[0] = vect_info;
5681                 vcpu->run->internal.data[1] = intr_info;
5682                 vcpu->run->internal.data[2] = error_code;
5683                 return 0;
5684         }
5685
5686         if (is_page_fault(intr_info)) {
5687                 /* EPT won't cause page fault directly */
5688                 BUG_ON(enable_ept);
5689                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5690                 trace_kvm_page_fault(cr2, error_code);
5691
5692                 if (kvm_event_needs_reinjection(vcpu))
5693                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5694                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5695         }
5696
5697         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5698
5699         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5700                 return handle_rmode_exception(vcpu, ex_no, error_code);
5701
5702         switch (ex_no) {
5703         case AC_VECTOR:
5704                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5705                 return 1;
5706         case DB_VECTOR:
5707                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5708                 if (!(vcpu->guest_debug &
5709                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5710                         vcpu->arch.dr6 &= ~15;
5711                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5712                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5713                                 skip_emulated_instruction(vcpu);
5714
5715                         kvm_queue_exception(vcpu, DB_VECTOR);
5716                         return 1;
5717                 }
5718                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5719                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5720                 /* fall through */
5721         case BP_VECTOR:
5722                 /*
5723                  * Update instruction length as we may reinject #BP from
5724                  * user space while in guest debugging mode. Reading it for
5725                  * #DB as well causes no harm, it is not used in that case.
5726                  */
5727                 vmx->vcpu.arch.event_exit_inst_len =
5728                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5729                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5730                 rip = kvm_rip_read(vcpu);
5731                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5732                 kvm_run->debug.arch.exception = ex_no;
5733                 break;
5734         default:
5735                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5736                 kvm_run->ex.exception = ex_no;
5737                 kvm_run->ex.error_code = error_code;
5738                 break;
5739         }
5740         return 0;
5741 }
5742
5743 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5744 {
5745         ++vcpu->stat.irq_exits;
5746         return 1;
5747 }
5748
5749 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5750 {
5751         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5752         return 0;
5753 }
5754
5755 static int handle_io(struct kvm_vcpu *vcpu)
5756 {
5757         unsigned long exit_qualification;
5758         int size, in, string, ret;
5759         unsigned port;
5760
5761         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5762         string = (exit_qualification & 16) != 0;
5763         in = (exit_qualification & 8) != 0;
5764
5765         ++vcpu->stat.io_exits;
5766
5767         if (string || in)
5768                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5769
5770         port = exit_qualification >> 16;
5771         size = (exit_qualification & 7) + 1;
5772
5773         ret = kvm_skip_emulated_instruction(vcpu);
5774
5775         /*
5776          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5777          * KVM_EXIT_DEBUG here.
5778          */
5779         return kvm_fast_pio_out(vcpu, size, port) && ret;
5780 }
5781
5782 static void
5783 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5784 {
5785         /*
5786          * Patch in the VMCALL instruction:
5787          */
5788         hypercall[0] = 0x0f;
5789         hypercall[1] = 0x01;
5790         hypercall[2] = 0xc1;
5791 }
5792
5793 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5794 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5795 {
5796         if (is_guest_mode(vcpu)) {
5797                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5798                 unsigned long orig_val = val;
5799
5800                 /*
5801                  * We get here when L2 changed cr0 in a way that did not change
5802                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5803                  * but did change L0 shadowed bits. So we first calculate the
5804                  * effective cr0 value that L1 would like to write into the
5805                  * hardware. It consists of the L2-owned bits from the new
5806                  * value combined with the L1-owned bits from L1's guest_cr0.
5807                  */
5808                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5809                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5810
5811                 if (!nested_guest_cr0_valid(vcpu, val))
5812                         return 1;
5813
5814                 if (kvm_set_cr0(vcpu, val))
5815                         return 1;
5816                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5817                 return 0;
5818         } else {
5819                 if (to_vmx(vcpu)->nested.vmxon &&
5820                     !nested_host_cr0_valid(vcpu, val))
5821                         return 1;
5822
5823                 return kvm_set_cr0(vcpu, val);
5824         }
5825 }
5826
5827 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5828 {
5829         if (is_guest_mode(vcpu)) {
5830                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5831                 unsigned long orig_val = val;
5832
5833                 /* analogously to handle_set_cr0 */
5834                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5835                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5836                 if (kvm_set_cr4(vcpu, val))
5837                         return 1;
5838                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5839                 return 0;
5840         } else
5841                 return kvm_set_cr4(vcpu, val);
5842 }
5843
5844 static int handle_cr(struct kvm_vcpu *vcpu)
5845 {
5846         unsigned long exit_qualification, val;
5847         int cr;
5848         int reg;
5849         int err;
5850         int ret;
5851
5852         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5853         cr = exit_qualification & 15;
5854         reg = (exit_qualification >> 8) & 15;
5855         switch ((exit_qualification >> 4) & 3) {
5856         case 0: /* mov to cr */
5857                 val = kvm_register_readl(vcpu, reg);
5858                 trace_kvm_cr_write(cr, val);
5859                 switch (cr) {
5860                 case 0:
5861                         err = handle_set_cr0(vcpu, val);
5862                         return kvm_complete_insn_gp(vcpu, err);
5863                 case 3:
5864                         err = kvm_set_cr3(vcpu, val);
5865                         return kvm_complete_insn_gp(vcpu, err);
5866                 case 4:
5867                         err = handle_set_cr4(vcpu, val);
5868                         return kvm_complete_insn_gp(vcpu, err);
5869                 case 8: {
5870                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5871                                 u8 cr8 = (u8)val;
5872                                 err = kvm_set_cr8(vcpu, cr8);
5873                                 ret = kvm_complete_insn_gp(vcpu, err);
5874                                 if (lapic_in_kernel(vcpu))
5875                                         return ret;
5876                                 if (cr8_prev <= cr8)
5877                                         return ret;
5878                                 /*
5879                                  * TODO: we might be squashing a
5880                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5881                                  * KVM_EXIT_DEBUG here.
5882                                  */
5883                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5884                                 return 0;
5885                         }
5886                 }
5887                 break;
5888         case 2: /* clts */
5889                 WARN_ONCE(1, "Guest should always own CR0.TS");
5890                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5891                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5892                 return kvm_skip_emulated_instruction(vcpu);
5893         case 1: /*mov from cr*/
5894                 switch (cr) {
5895                 case 3:
5896                         val = kvm_read_cr3(vcpu);
5897                         kvm_register_write(vcpu, reg, val);
5898                         trace_kvm_cr_read(cr, val);
5899                         return kvm_skip_emulated_instruction(vcpu);
5900                 case 8:
5901                         val = kvm_get_cr8(vcpu);
5902                         kvm_register_write(vcpu, reg, val);
5903                         trace_kvm_cr_read(cr, val);
5904                         return kvm_skip_emulated_instruction(vcpu);
5905                 }
5906                 break;
5907         case 3: /* lmsw */
5908                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5909                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5910                 kvm_lmsw(vcpu, val);
5911
5912                 return kvm_skip_emulated_instruction(vcpu);
5913         default:
5914                 break;
5915         }
5916         vcpu->run->exit_reason = 0;
5917         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5918                (int)(exit_qualification >> 4) & 3, cr);
5919         return 0;
5920 }
5921
5922 static int handle_dr(struct kvm_vcpu *vcpu)
5923 {
5924         unsigned long exit_qualification;
5925         int dr, dr7, reg;
5926
5927         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5928         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5929
5930         /* First, if DR does not exist, trigger UD */
5931         if (!kvm_require_dr(vcpu, dr))
5932                 return 1;
5933
5934         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5935         if (!kvm_require_cpl(vcpu, 0))
5936                 return 1;
5937         dr7 = vmcs_readl(GUEST_DR7);
5938         if (dr7 & DR7_GD) {
5939                 /*
5940                  * As the vm-exit takes precedence over the debug trap, we
5941                  * need to emulate the latter, either for the host or the
5942                  * guest debugging itself.
5943                  */
5944                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5945                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5946                         vcpu->run->debug.arch.dr7 = dr7;
5947                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5948                         vcpu->run->debug.arch.exception = DB_VECTOR;
5949                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5950                         return 0;
5951                 } else {
5952                         vcpu->arch.dr6 &= ~15;
5953                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5954                         kvm_queue_exception(vcpu, DB_VECTOR);
5955                         return 1;
5956                 }
5957         }
5958
5959         if (vcpu->guest_debug == 0) {
5960                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5961                                 CPU_BASED_MOV_DR_EXITING);
5962
5963                 /*
5964                  * No more DR vmexits; force a reload of the debug registers
5965                  * and reenter on this instruction.  The next vmexit will
5966                  * retrieve the full state of the debug registers.
5967                  */
5968                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5969                 return 1;
5970         }
5971
5972         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5973         if (exit_qualification & TYPE_MOV_FROM_DR) {
5974                 unsigned long val;
5975
5976                 if (kvm_get_dr(vcpu, dr, &val))
5977                         return 1;
5978                 kvm_register_write(vcpu, reg, val);
5979         } else
5980                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5981                         return 1;
5982
5983         return kvm_skip_emulated_instruction(vcpu);
5984 }
5985
5986 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5987 {
5988         return vcpu->arch.dr6;
5989 }
5990
5991 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5992 {
5993 }
5994
5995 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5996 {
5997         get_debugreg(vcpu->arch.db[0], 0);
5998         get_debugreg(vcpu->arch.db[1], 1);
5999         get_debugreg(vcpu->arch.db[2], 2);
6000         get_debugreg(vcpu->arch.db[3], 3);
6001         get_debugreg(vcpu->arch.dr6, 6);
6002         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6003
6004         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6005         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6006 }
6007
6008 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6009 {
6010         vmcs_writel(GUEST_DR7, val);
6011 }
6012
6013 static int handle_cpuid(struct kvm_vcpu *vcpu)
6014 {
6015         return kvm_emulate_cpuid(vcpu);
6016 }
6017
6018 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6019 {
6020         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6021         struct msr_data msr_info;
6022
6023         msr_info.index = ecx;
6024         msr_info.host_initiated = false;
6025         if (vmx_get_msr(vcpu, &msr_info)) {
6026                 trace_kvm_msr_read_ex(ecx);
6027                 kvm_inject_gp(vcpu, 0);
6028                 return 1;
6029         }
6030
6031         trace_kvm_msr_read(ecx, msr_info.data);
6032
6033         /* FIXME: handling of bits 32:63 of rax, rdx */
6034         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6035         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6036         return kvm_skip_emulated_instruction(vcpu);
6037 }
6038
6039 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6040 {
6041         struct msr_data msr;
6042         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6043         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6044                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6045
6046         msr.data = data;
6047         msr.index = ecx;
6048         msr.host_initiated = false;
6049         if (kvm_set_msr(vcpu, &msr) != 0) {
6050                 trace_kvm_msr_write_ex(ecx, data);
6051                 kvm_inject_gp(vcpu, 0);
6052                 return 1;
6053         }
6054
6055         trace_kvm_msr_write(ecx, data);
6056         return kvm_skip_emulated_instruction(vcpu);
6057 }
6058
6059 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6060 {
6061         kvm_apic_update_ppr(vcpu);
6062         return 1;
6063 }
6064
6065 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6066 {
6067         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6068                         CPU_BASED_VIRTUAL_INTR_PENDING);
6069
6070         kvm_make_request(KVM_REQ_EVENT, vcpu);
6071
6072         ++vcpu->stat.irq_window_exits;
6073         return 1;
6074 }
6075
6076 static int handle_halt(struct kvm_vcpu *vcpu)
6077 {
6078         return kvm_emulate_halt(vcpu);
6079 }
6080
6081 static int handle_vmcall(struct kvm_vcpu *vcpu)
6082 {
6083         return kvm_emulate_hypercall(vcpu);
6084 }
6085
6086 static int handle_invd(struct kvm_vcpu *vcpu)
6087 {
6088         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6089 }
6090
6091 static int handle_invlpg(struct kvm_vcpu *vcpu)
6092 {
6093         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6094
6095         kvm_mmu_invlpg(vcpu, exit_qualification);
6096         return kvm_skip_emulated_instruction(vcpu);
6097 }
6098
6099 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6100 {
6101         int err;
6102
6103         err = kvm_rdpmc(vcpu);
6104         return kvm_complete_insn_gp(vcpu, err);
6105 }
6106
6107 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6108 {
6109         return kvm_emulate_wbinvd(vcpu);
6110 }
6111
6112 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6113 {
6114         u64 new_bv = kvm_read_edx_eax(vcpu);
6115         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6116
6117         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6118                 return kvm_skip_emulated_instruction(vcpu);
6119         return 1;
6120 }
6121
6122 static int handle_xsaves(struct kvm_vcpu *vcpu)
6123 {
6124         kvm_skip_emulated_instruction(vcpu);
6125         WARN(1, "this should never happen\n");
6126         return 1;
6127 }
6128
6129 static int handle_xrstors(struct kvm_vcpu *vcpu)
6130 {
6131         kvm_skip_emulated_instruction(vcpu);
6132         WARN(1, "this should never happen\n");
6133         return 1;
6134 }
6135
6136 static int handle_apic_access(struct kvm_vcpu *vcpu)
6137 {
6138         if (likely(fasteoi)) {
6139                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6140                 int access_type, offset;
6141
6142                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6143                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6144                 /*
6145                  * Sane guest uses MOV to write EOI, with written value
6146                  * not cared. So make a short-circuit here by avoiding
6147                  * heavy instruction emulation.
6148                  */
6149                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6150                     (offset == APIC_EOI)) {
6151                         kvm_lapic_set_eoi(vcpu);
6152                         return kvm_skip_emulated_instruction(vcpu);
6153                 }
6154         }
6155         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6156 }
6157
6158 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6159 {
6160         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6161         int vector = exit_qualification & 0xff;
6162
6163         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6164         kvm_apic_set_eoi_accelerated(vcpu, vector);
6165         return 1;
6166 }
6167
6168 static int handle_apic_write(struct kvm_vcpu *vcpu)
6169 {
6170         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6171         u32 offset = exit_qualification & 0xfff;
6172
6173         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6174         kvm_apic_write_nodecode(vcpu, offset);
6175         return 1;
6176 }
6177
6178 static int handle_task_switch(struct kvm_vcpu *vcpu)
6179 {
6180         struct vcpu_vmx *vmx = to_vmx(vcpu);
6181         unsigned long exit_qualification;
6182         bool has_error_code = false;
6183         u32 error_code = 0;
6184         u16 tss_selector;
6185         int reason, type, idt_v, idt_index;
6186
6187         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6188         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6189         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6190
6191         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6192
6193         reason = (u32)exit_qualification >> 30;
6194         if (reason == TASK_SWITCH_GATE && idt_v) {
6195                 switch (type) {
6196                 case INTR_TYPE_NMI_INTR:
6197                         vcpu->arch.nmi_injected = false;
6198                         vmx_set_nmi_mask(vcpu, true);
6199                         break;
6200                 case INTR_TYPE_EXT_INTR:
6201                 case INTR_TYPE_SOFT_INTR:
6202                         kvm_clear_interrupt_queue(vcpu);
6203                         break;
6204                 case INTR_TYPE_HARD_EXCEPTION:
6205                         if (vmx->idt_vectoring_info &
6206                             VECTORING_INFO_DELIVER_CODE_MASK) {
6207                                 has_error_code = true;
6208                                 error_code =
6209                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6210                         }
6211                         /* fall through */
6212                 case INTR_TYPE_SOFT_EXCEPTION:
6213                         kvm_clear_exception_queue(vcpu);
6214                         break;
6215                 default:
6216                         break;
6217                 }
6218         }
6219         tss_selector = exit_qualification;
6220
6221         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6222                        type != INTR_TYPE_EXT_INTR &&
6223                        type != INTR_TYPE_NMI_INTR))
6224                 skip_emulated_instruction(vcpu);
6225
6226         if (kvm_task_switch(vcpu, tss_selector,
6227                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6228                             has_error_code, error_code) == EMULATE_FAIL) {
6229                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6230                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6231                 vcpu->run->internal.ndata = 0;
6232                 return 0;
6233         }
6234
6235         /*
6236          * TODO: What about debug traps on tss switch?
6237          *       Are we supposed to inject them and update dr6?
6238          */
6239
6240         return 1;
6241 }
6242
6243 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6244 {
6245         unsigned long exit_qualification;
6246         gpa_t gpa;
6247         u32 error_code;
6248         int gla_validity;
6249
6250         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6251
6252         gla_validity = (exit_qualification >> 7) & 0x3;
6253         if (gla_validity == 0x2) {
6254                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6255                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6256                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6257                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6258                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6259                         (long unsigned int)exit_qualification);
6260                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6261                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6262                 return 0;
6263         }
6264
6265         /*
6266          * EPT violation happened while executing iret from NMI,
6267          * "blocked by NMI" bit has to be set before next VM entry.
6268          * There are errata that may cause this bit to not be set:
6269          * AAK134, BY25.
6270          */
6271         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6272                         cpu_has_virtual_nmis() &&
6273                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6274                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6275
6276         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6277         trace_kvm_page_fault(gpa, exit_qualification);
6278
6279         /* Is it a read fault? */
6280         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6281                      ? PFERR_USER_MASK : 0;
6282         /* Is it a write fault? */
6283         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6284                       ? PFERR_WRITE_MASK : 0;
6285         /* Is it a fetch fault? */
6286         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6287                       ? PFERR_FETCH_MASK : 0;
6288         /* ept page table entry is present? */
6289         error_code |= (exit_qualification &
6290                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6291                         EPT_VIOLATION_EXECUTABLE))
6292                       ? PFERR_PRESENT_MASK : 0;
6293
6294         vcpu->arch.gpa_available = true;
6295         vcpu->arch.exit_qualification = exit_qualification;
6296
6297         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6298 }
6299
6300 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6301 {
6302         int ret;
6303         gpa_t gpa;
6304
6305         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6306         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6307                 trace_kvm_fast_mmio(gpa);
6308                 return kvm_skip_emulated_instruction(vcpu);
6309         }
6310
6311         ret = handle_mmio_page_fault(vcpu, gpa, true);
6312         vcpu->arch.gpa_available = true;
6313         if (likely(ret == RET_MMIO_PF_EMULATE))
6314                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6315                                               EMULATE_DONE;
6316
6317         if (unlikely(ret == RET_MMIO_PF_INVALID))
6318                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6319
6320         if (unlikely(ret == RET_MMIO_PF_RETRY))
6321                 return 1;
6322
6323         /* It is the real ept misconfig */
6324         WARN_ON(1);
6325
6326         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6327         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6328
6329         return 0;
6330 }
6331
6332 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6333 {
6334         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6335                         CPU_BASED_VIRTUAL_NMI_PENDING);
6336         ++vcpu->stat.nmi_window_exits;
6337         kvm_make_request(KVM_REQ_EVENT, vcpu);
6338
6339         return 1;
6340 }
6341
6342 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6343 {
6344         struct vcpu_vmx *vmx = to_vmx(vcpu);
6345         enum emulation_result err = EMULATE_DONE;
6346         int ret = 1;
6347         u32 cpu_exec_ctrl;
6348         bool intr_window_requested;
6349         unsigned count = 130;
6350
6351         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6352         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6353
6354         while (vmx->emulation_required && count-- != 0) {
6355                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6356                         return handle_interrupt_window(&vmx->vcpu);
6357
6358                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6359                         return 1;
6360
6361                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6362
6363                 if (err == EMULATE_USER_EXIT) {
6364                         ++vcpu->stat.mmio_exits;
6365                         ret = 0;
6366                         goto out;
6367                 }
6368
6369                 if (err != EMULATE_DONE) {
6370                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6371                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6372                         vcpu->run->internal.ndata = 0;
6373                         return 0;
6374                 }
6375
6376                 if (vcpu->arch.halt_request) {
6377                         vcpu->arch.halt_request = 0;
6378                         ret = kvm_vcpu_halt(vcpu);
6379                         goto out;
6380                 }
6381
6382                 if (signal_pending(current))
6383                         goto out;
6384                 if (need_resched())
6385                         schedule();
6386         }
6387
6388 out:
6389         return ret;
6390 }
6391
6392 static int __grow_ple_window(int val)
6393 {
6394         if (ple_window_grow < 1)
6395                 return ple_window;
6396
6397         val = min(val, ple_window_actual_max);
6398
6399         if (ple_window_grow < ple_window)
6400                 val *= ple_window_grow;
6401         else
6402                 val += ple_window_grow;
6403
6404         return val;
6405 }
6406
6407 static int __shrink_ple_window(int val, int modifier, int minimum)
6408 {
6409         if (modifier < 1)
6410                 return ple_window;
6411
6412         if (modifier < ple_window)
6413                 val /= modifier;
6414         else
6415                 val -= modifier;
6416
6417         return max(val, minimum);
6418 }
6419
6420 static void grow_ple_window(struct kvm_vcpu *vcpu)
6421 {
6422         struct vcpu_vmx *vmx = to_vmx(vcpu);
6423         int old = vmx->ple_window;
6424
6425         vmx->ple_window = __grow_ple_window(old);
6426
6427         if (vmx->ple_window != old)
6428                 vmx->ple_window_dirty = true;
6429
6430         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6431 }
6432
6433 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6434 {
6435         struct vcpu_vmx *vmx = to_vmx(vcpu);
6436         int old = vmx->ple_window;
6437
6438         vmx->ple_window = __shrink_ple_window(old,
6439                                               ple_window_shrink, ple_window);
6440
6441         if (vmx->ple_window != old)
6442                 vmx->ple_window_dirty = true;
6443
6444         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6445 }
6446
6447 /*
6448  * ple_window_actual_max is computed to be one grow_ple_window() below
6449  * ple_window_max. (See __grow_ple_window for the reason.)
6450  * This prevents overflows, because ple_window_max is int.
6451  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6452  * this process.
6453  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6454  */
6455 static void update_ple_window_actual_max(void)
6456 {
6457         ple_window_actual_max =
6458                         __shrink_ple_window(max(ple_window_max, ple_window),
6459                                             ple_window_grow, INT_MIN);
6460 }
6461
6462 /*
6463  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6464  */
6465 static void wakeup_handler(void)
6466 {
6467         struct kvm_vcpu *vcpu;
6468         int cpu = smp_processor_id();
6469
6470         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6471         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6472                         blocked_vcpu_list) {
6473                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6474
6475                 if (pi_test_on(pi_desc) == 1)
6476                         kvm_vcpu_kick(vcpu);
6477         }
6478         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6479 }
6480
6481 void vmx_enable_tdp(void)
6482 {
6483         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6484                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6485                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6486                 0ull, VMX_EPT_EXECUTABLE_MASK,
6487                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6488                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6489
6490         ept_set_mmio_spte_mask();
6491         kvm_enable_tdp();
6492 }
6493
6494 static __init int hardware_setup(void)
6495 {
6496         int r = -ENOMEM, i, msr;
6497
6498         rdmsrl_safe(MSR_EFER, &host_efer);
6499
6500         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6501                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6502
6503         for (i = 0; i < VMX_BITMAP_NR; i++) {
6504                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6505                 if (!vmx_bitmap[i])
6506                         goto out;
6507         }
6508
6509         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6510         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6511         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6512
6513         /*
6514          * Allow direct access to the PC debug port (it is often used for I/O
6515          * delays, but the vmexits simply slow things down).
6516          */
6517         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6518         clear_bit(0x80, vmx_io_bitmap_a);
6519
6520         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6521
6522         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6523         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6524
6525         if (setup_vmcs_config(&vmcs_config) < 0) {
6526                 r = -EIO;
6527                 goto out;
6528         }
6529
6530         if (boot_cpu_has(X86_FEATURE_NX))
6531                 kvm_enable_efer_bits(EFER_NX);
6532
6533         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6534                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6535                 enable_vpid = 0;
6536
6537         if (!cpu_has_vmx_shadow_vmcs())
6538                 enable_shadow_vmcs = 0;
6539         if (enable_shadow_vmcs)
6540                 init_vmcs_shadow_fields();
6541
6542         if (!cpu_has_vmx_ept() ||
6543             !cpu_has_vmx_ept_4levels()) {
6544                 enable_ept = 0;
6545                 enable_unrestricted_guest = 0;
6546                 enable_ept_ad_bits = 0;
6547         }
6548
6549         if (!cpu_has_vmx_ept_ad_bits())
6550                 enable_ept_ad_bits = 0;
6551
6552         if (!cpu_has_vmx_unrestricted_guest())
6553                 enable_unrestricted_guest = 0;
6554
6555         if (!cpu_has_vmx_flexpriority())
6556                 flexpriority_enabled = 0;
6557
6558         /*
6559          * set_apic_access_page_addr() is used to reload apic access
6560          * page upon invalidation.  No need to do anything if not
6561          * using the APIC_ACCESS_ADDR VMCS field.
6562          */
6563         if (!flexpriority_enabled)
6564                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6565
6566         if (!cpu_has_vmx_tpr_shadow())
6567                 kvm_x86_ops->update_cr8_intercept = NULL;
6568
6569         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6570                 kvm_disable_largepages();
6571
6572         if (!cpu_has_vmx_ple())
6573                 ple_gap = 0;
6574
6575         if (!cpu_has_vmx_apicv()) {
6576                 enable_apicv = 0;
6577                 kvm_x86_ops->sync_pir_to_irr = NULL;
6578         }
6579
6580         if (cpu_has_vmx_tsc_scaling()) {
6581                 kvm_has_tsc_control = true;
6582                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6583                 kvm_tsc_scaling_ratio_frac_bits = 48;
6584         }
6585
6586         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6587         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6588         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6589         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6590         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6591         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6592         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6593
6594         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6595                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6596         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6597                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6598         memcpy(vmx_msr_bitmap_legacy_x2apic,
6599                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6600         memcpy(vmx_msr_bitmap_longmode_x2apic,
6601                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6602
6603         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6604
6605         for (msr = 0x800; msr <= 0x8ff; msr++) {
6606                 if (msr == 0x839 /* TMCCT */)
6607                         continue;
6608                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6609         }
6610
6611         /*
6612          * TPR reads and writes can be virtualized even if virtual interrupt
6613          * delivery is not in use.
6614          */
6615         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6616         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6617
6618         /* EOI */
6619         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6620         /* SELF-IPI */
6621         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6622
6623         if (enable_ept)
6624                 vmx_enable_tdp();
6625         else
6626                 kvm_disable_tdp();
6627
6628         update_ple_window_actual_max();
6629
6630         /*
6631          * Only enable PML when hardware supports PML feature, and both EPT
6632          * and EPT A/D bit features are enabled -- PML depends on them to work.
6633          */
6634         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6635                 enable_pml = 0;
6636
6637         if (!enable_pml) {
6638                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6639                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6640                 kvm_x86_ops->flush_log_dirty = NULL;
6641                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6642         }
6643
6644         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6645                 u64 vmx_msr;
6646
6647                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6648                 cpu_preemption_timer_multi =
6649                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6650         } else {
6651                 kvm_x86_ops->set_hv_timer = NULL;
6652                 kvm_x86_ops->cancel_hv_timer = NULL;
6653         }
6654
6655         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6656
6657         kvm_mce_cap_supported |= MCG_LMCE_P;
6658
6659         return alloc_kvm_area();
6660
6661 out:
6662         for (i = 0; i < VMX_BITMAP_NR; i++)
6663                 free_page((unsigned long)vmx_bitmap[i]);
6664
6665     return r;
6666 }
6667
6668 static __exit void hardware_unsetup(void)
6669 {
6670         int i;
6671
6672         for (i = 0; i < VMX_BITMAP_NR; i++)
6673                 free_page((unsigned long)vmx_bitmap[i]);
6674
6675         free_kvm_area();
6676 }
6677
6678 /*
6679  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6680  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6681  */
6682 static int handle_pause(struct kvm_vcpu *vcpu)
6683 {
6684         if (ple_gap)
6685                 grow_ple_window(vcpu);
6686
6687         kvm_vcpu_on_spin(vcpu);
6688         return kvm_skip_emulated_instruction(vcpu);
6689 }
6690
6691 static int handle_nop(struct kvm_vcpu *vcpu)
6692 {
6693         return kvm_skip_emulated_instruction(vcpu);
6694 }
6695
6696 static int handle_mwait(struct kvm_vcpu *vcpu)
6697 {
6698         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6699         return handle_nop(vcpu);
6700 }
6701
6702 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6703 {
6704         return 1;
6705 }
6706
6707 static int handle_monitor(struct kvm_vcpu *vcpu)
6708 {
6709         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6710         return handle_nop(vcpu);
6711 }
6712
6713 /*
6714  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6715  * We could reuse a single VMCS for all the L2 guests, but we also want the
6716  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6717  * allows keeping them loaded on the processor, and in the future will allow
6718  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6719  * every entry if they never change.
6720  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6721  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6722  *
6723  * The following functions allocate and free a vmcs02 in this pool.
6724  */
6725
6726 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6727 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6728 {
6729         struct vmcs02_list *item;
6730         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6731                 if (item->vmptr == vmx->nested.current_vmptr) {
6732                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6733                         return &item->vmcs02;
6734                 }
6735
6736         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6737                 /* Recycle the least recently used VMCS. */
6738                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6739                                        struct vmcs02_list, list);
6740                 item->vmptr = vmx->nested.current_vmptr;
6741                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6742                 return &item->vmcs02;
6743         }
6744
6745         /* Create a new VMCS */
6746         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6747         if (!item)
6748                 return NULL;
6749         item->vmcs02.vmcs = alloc_vmcs();
6750         item->vmcs02.shadow_vmcs = NULL;
6751         if (!item->vmcs02.vmcs) {
6752                 kfree(item);
6753                 return NULL;
6754         }
6755         loaded_vmcs_init(&item->vmcs02);
6756         item->vmptr = vmx->nested.current_vmptr;
6757         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6758         vmx->nested.vmcs02_num++;
6759         return &item->vmcs02;
6760 }
6761
6762 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6763 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6764 {
6765         struct vmcs02_list *item;
6766         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6767                 if (item->vmptr == vmptr) {
6768                         free_loaded_vmcs(&item->vmcs02);
6769                         list_del(&item->list);
6770                         kfree(item);
6771                         vmx->nested.vmcs02_num--;
6772                         return;
6773                 }
6774 }
6775
6776 /*
6777  * Free all VMCSs saved for this vcpu, except the one pointed by
6778  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6779  * must be &vmx->vmcs01.
6780  */
6781 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6782 {
6783         struct vmcs02_list *item, *n;
6784
6785         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6786         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6787                 /*
6788                  * Something will leak if the above WARN triggers.  Better than
6789                  * a use-after-free.
6790                  */
6791                 if (vmx->loaded_vmcs == &item->vmcs02)
6792                         continue;
6793
6794                 free_loaded_vmcs(&item->vmcs02);
6795                 list_del(&item->list);
6796                 kfree(item);
6797                 vmx->nested.vmcs02_num--;
6798         }
6799 }
6800
6801 /*
6802  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6803  * set the success or error code of an emulated VMX instruction, as specified
6804  * by Vol 2B, VMX Instruction Reference, "Conventions".
6805  */
6806 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6807 {
6808         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6809                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6810                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6811 }
6812
6813 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6814 {
6815         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6816                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6817                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6818                         | X86_EFLAGS_CF);
6819 }
6820
6821 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6822                                         u32 vm_instruction_error)
6823 {
6824         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6825                 /*
6826                  * failValid writes the error number to the current VMCS, which
6827                  * can't be done there isn't a current VMCS.
6828                  */
6829                 nested_vmx_failInvalid(vcpu);
6830                 return;
6831         }
6832         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6833                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6834                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6835                         | X86_EFLAGS_ZF);
6836         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6837         /*
6838          * We don't need to force a shadow sync because
6839          * VM_INSTRUCTION_ERROR is not shadowed
6840          */
6841 }
6842
6843 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6844 {
6845         /* TODO: not to reset guest simply here. */
6846         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6847         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6848 }
6849
6850 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6851 {
6852         struct vcpu_vmx *vmx =
6853                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6854
6855         vmx->nested.preemption_timer_expired = true;
6856         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6857         kvm_vcpu_kick(&vmx->vcpu);
6858
6859         return HRTIMER_NORESTART;
6860 }
6861
6862 /*
6863  * Decode the memory-address operand of a vmx instruction, as recorded on an
6864  * exit caused by such an instruction (run by a guest hypervisor).
6865  * On success, returns 0. When the operand is invalid, returns 1 and throws
6866  * #UD or #GP.
6867  */
6868 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6869                                  unsigned long exit_qualification,
6870                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6871 {
6872         gva_t off;
6873         bool exn;
6874         struct kvm_segment s;
6875
6876         /*
6877          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6878          * Execution", on an exit, vmx_instruction_info holds most of the
6879          * addressing components of the operand. Only the displacement part
6880          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6881          * For how an actual address is calculated from all these components,
6882          * refer to Vol. 1, "Operand Addressing".
6883          */
6884         int  scaling = vmx_instruction_info & 3;
6885         int  addr_size = (vmx_instruction_info >> 7) & 7;
6886         bool is_reg = vmx_instruction_info & (1u << 10);
6887         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6888         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6889         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6890         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6891         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6892
6893         if (is_reg) {
6894                 kvm_queue_exception(vcpu, UD_VECTOR);
6895                 return 1;
6896         }
6897
6898         /* Addr = segment_base + offset */
6899         /* offset = base + [index * scale] + displacement */
6900         off = exit_qualification; /* holds the displacement */
6901         if (base_is_valid)
6902                 off += kvm_register_read(vcpu, base_reg);
6903         if (index_is_valid)
6904                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6905         vmx_get_segment(vcpu, &s, seg_reg);
6906         *ret = s.base + off;
6907
6908         if (addr_size == 1) /* 32 bit */
6909                 *ret &= 0xffffffff;
6910
6911         /* Checks for #GP/#SS exceptions. */
6912         exn = false;
6913         if (is_long_mode(vcpu)) {
6914                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6915                  * non-canonical form. This is the only check on the memory
6916                  * destination for long mode!
6917                  */
6918                 exn = is_noncanonical_address(*ret);
6919         } else if (is_protmode(vcpu)) {
6920                 /* Protected mode: apply checks for segment validity in the
6921                  * following order:
6922                  * - segment type check (#GP(0) may be thrown)
6923                  * - usability check (#GP(0)/#SS(0))
6924                  * - limit check (#GP(0)/#SS(0))
6925                  */
6926                 if (wr)
6927                         /* #GP(0) if the destination operand is located in a
6928                          * read-only data segment or any code segment.
6929                          */
6930                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6931                 else
6932                         /* #GP(0) if the source operand is located in an
6933                          * execute-only code segment
6934                          */
6935                         exn = ((s.type & 0xa) == 8);
6936                 if (exn) {
6937                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6938                         return 1;
6939                 }
6940                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6941                  */
6942                 exn = (s.unusable != 0);
6943                 /* Protected mode: #GP(0)/#SS(0) if the memory
6944                  * operand is outside the segment limit.
6945                  */
6946                 exn = exn || (off + sizeof(u64) > s.limit);
6947         }
6948         if (exn) {
6949                 kvm_queue_exception_e(vcpu,
6950                                       seg_reg == VCPU_SREG_SS ?
6951                                                 SS_VECTOR : GP_VECTOR,
6952                                       0);
6953                 return 1;
6954         }
6955
6956         return 0;
6957 }
6958
6959 /*
6960  * This function performs the various checks including
6961  * - if it's 4KB aligned
6962  * - No bits beyond the physical address width are set
6963  * - Returns 0 on success or else 1
6964  * (Intel SDM Section 30.3)
6965  */
6966 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6967                                   gpa_t *vmpointer)
6968 {
6969         gva_t gva;
6970         gpa_t vmptr;
6971         struct x86_exception e;
6972         struct page *page;
6973         struct vcpu_vmx *vmx = to_vmx(vcpu);
6974         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6975
6976         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6977                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6978                 return 1;
6979
6980         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6981                                 sizeof(vmptr), &e)) {
6982                 kvm_inject_page_fault(vcpu, &e);
6983                 return 1;
6984         }
6985
6986         switch (exit_reason) {
6987         case EXIT_REASON_VMON:
6988                 /*
6989                  * SDM 3: 24.11.5
6990                  * The first 4 bytes of VMXON region contain the supported
6991                  * VMCS revision identifier
6992                  *
6993                  * Note - IA32_VMX_BASIC[48] will never be 1
6994                  * for the nested case;
6995                  * which replaces physical address width with 32
6996                  *
6997                  */
6998                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6999                         nested_vmx_failInvalid(vcpu);
7000                         return kvm_skip_emulated_instruction(vcpu);
7001                 }
7002
7003                 page = nested_get_page(vcpu, vmptr);
7004                 if (page == NULL) {
7005                         nested_vmx_failInvalid(vcpu);
7006                         return kvm_skip_emulated_instruction(vcpu);
7007                 }
7008                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7009                         kunmap(page);
7010                         nested_release_page_clean(page);
7011                         nested_vmx_failInvalid(vcpu);
7012                         return kvm_skip_emulated_instruction(vcpu);
7013                 }
7014                 kunmap(page);
7015                 nested_release_page_clean(page);
7016                 vmx->nested.vmxon_ptr = vmptr;
7017                 break;
7018         case EXIT_REASON_VMCLEAR:
7019                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7020                         nested_vmx_failValid(vcpu,
7021                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7022                         return kvm_skip_emulated_instruction(vcpu);
7023                 }
7024
7025                 if (vmptr == vmx->nested.vmxon_ptr) {
7026                         nested_vmx_failValid(vcpu,
7027                                              VMXERR_VMCLEAR_VMXON_POINTER);
7028                         return kvm_skip_emulated_instruction(vcpu);
7029                 }
7030                 break;
7031         case EXIT_REASON_VMPTRLD:
7032                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7033                         nested_vmx_failValid(vcpu,
7034                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7035                         return kvm_skip_emulated_instruction(vcpu);
7036                 }
7037
7038                 if (vmptr == vmx->nested.vmxon_ptr) {
7039                         nested_vmx_failValid(vcpu,
7040                                              VMXERR_VMPTRLD_VMXON_POINTER);
7041                         return kvm_skip_emulated_instruction(vcpu);
7042                 }
7043                 break;
7044         default:
7045                 return 1; /* shouldn't happen */
7046         }
7047
7048         if (vmpointer)
7049                 *vmpointer = vmptr;
7050         return 0;
7051 }
7052
7053 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7054 {
7055         struct vcpu_vmx *vmx = to_vmx(vcpu);
7056         struct vmcs *shadow_vmcs;
7057
7058         if (cpu_has_vmx_msr_bitmap()) {
7059                 vmx->nested.msr_bitmap =
7060                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7061                 if (!vmx->nested.msr_bitmap)
7062                         goto out_msr_bitmap;
7063         }
7064
7065         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7066         if (!vmx->nested.cached_vmcs12)
7067                 goto out_cached_vmcs12;
7068
7069         if (enable_shadow_vmcs) {
7070                 shadow_vmcs = alloc_vmcs();
7071                 if (!shadow_vmcs)
7072                         goto out_shadow_vmcs;
7073                 /* mark vmcs as shadow */
7074                 shadow_vmcs->revision_id |= (1u << 31);
7075                 /* init shadow vmcs */
7076                 vmcs_clear(shadow_vmcs);
7077                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7078         }
7079
7080         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7081         vmx->nested.vmcs02_num = 0;
7082
7083         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7084                      HRTIMER_MODE_REL_PINNED);
7085         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7086
7087         vmx->nested.vmxon = true;
7088         return 0;
7089
7090 out_shadow_vmcs:
7091         kfree(vmx->nested.cached_vmcs12);
7092
7093 out_cached_vmcs12:
7094         free_page((unsigned long)vmx->nested.msr_bitmap);
7095
7096 out_msr_bitmap:
7097         return -ENOMEM;
7098 }
7099
7100 /*
7101  * Emulate the VMXON instruction.
7102  * Currently, we just remember that VMX is active, and do not save or even
7103  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7104  * do not currently need to store anything in that guest-allocated memory
7105  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7106  * argument is different from the VMXON pointer (which the spec says they do).
7107  */
7108 static int handle_vmon(struct kvm_vcpu *vcpu)
7109 {
7110         int ret;
7111         struct kvm_segment cs;
7112         struct vcpu_vmx *vmx = to_vmx(vcpu);
7113         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7114                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7115
7116         /* The Intel VMX Instruction Reference lists a bunch of bits that
7117          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7118          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7119          * Otherwise, we should fail with #UD. We test these now:
7120          */
7121         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7122             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7123             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7124                 kvm_queue_exception(vcpu, UD_VECTOR);
7125                 return 1;
7126         }
7127
7128         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7129         if (is_long_mode(vcpu) && !cs.l) {
7130                 kvm_queue_exception(vcpu, UD_VECTOR);
7131                 return 1;
7132         }
7133
7134         if (vmx_get_cpl(vcpu)) {
7135                 kvm_inject_gp(vcpu, 0);
7136                 return 1;
7137         }
7138
7139         if (vmx->nested.vmxon) {
7140                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7141                 return kvm_skip_emulated_instruction(vcpu);
7142         }
7143
7144         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7145                         != VMXON_NEEDED_FEATURES) {
7146                 kvm_inject_gp(vcpu, 0);
7147                 return 1;
7148         }
7149
7150         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7151                 return 1;
7152
7153         ret = enter_vmx_operation(vcpu);
7154         if (ret)
7155                 return ret;
7156
7157         nested_vmx_succeed(vcpu);
7158         return kvm_skip_emulated_instruction(vcpu);
7159 }
7160
7161 /*
7162  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7163  * for running VMX instructions (except VMXON, whose prerequisites are
7164  * slightly different). It also specifies what exception to inject otherwise.
7165  */
7166 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7167 {
7168         struct kvm_segment cs;
7169         struct vcpu_vmx *vmx = to_vmx(vcpu);
7170
7171         if (!vmx->nested.vmxon) {
7172                 kvm_queue_exception(vcpu, UD_VECTOR);
7173                 return 0;
7174         }
7175
7176         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7177         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7178             (is_long_mode(vcpu) && !cs.l)) {
7179                 kvm_queue_exception(vcpu, UD_VECTOR);
7180                 return 0;
7181         }
7182
7183         if (vmx_get_cpl(vcpu)) {
7184                 kvm_inject_gp(vcpu, 0);
7185                 return 0;
7186         }
7187
7188         return 1;
7189 }
7190
7191 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7192 {
7193         if (vmx->nested.current_vmptr == -1ull)
7194                 return;
7195
7196         /* current_vmptr and current_vmcs12 are always set/reset together */
7197         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7198                 return;
7199
7200         if (enable_shadow_vmcs) {
7201                 /* copy to memory all shadowed fields in case
7202                    they were modified */
7203                 copy_shadow_to_vmcs12(vmx);
7204                 vmx->nested.sync_shadow_vmcs = false;
7205                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7206                                 SECONDARY_EXEC_SHADOW_VMCS);
7207                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7208         }
7209         vmx->nested.posted_intr_nv = -1;
7210
7211         /* Flush VMCS12 to guest memory */
7212         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7213                VMCS12_SIZE);
7214
7215         kunmap(vmx->nested.current_vmcs12_page);
7216         nested_release_page(vmx->nested.current_vmcs12_page);
7217         vmx->nested.current_vmptr = -1ull;
7218         vmx->nested.current_vmcs12 = NULL;
7219 }
7220
7221 /*
7222  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7223  * just stops using VMX.
7224  */
7225 static void free_nested(struct vcpu_vmx *vmx)
7226 {
7227         if (!vmx->nested.vmxon)
7228                 return;
7229
7230         vmx->nested.vmxon = false;
7231         free_vpid(vmx->nested.vpid02);
7232         nested_release_vmcs12(vmx);
7233         if (vmx->nested.msr_bitmap) {
7234                 free_page((unsigned long)vmx->nested.msr_bitmap);
7235                 vmx->nested.msr_bitmap = NULL;
7236         }
7237         if (enable_shadow_vmcs) {
7238                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7239                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7240                 vmx->vmcs01.shadow_vmcs = NULL;
7241         }
7242         kfree(vmx->nested.cached_vmcs12);
7243         /* Unpin physical memory we referred to in current vmcs02 */
7244         if (vmx->nested.apic_access_page) {
7245                 nested_release_page(vmx->nested.apic_access_page);
7246                 vmx->nested.apic_access_page = NULL;
7247         }
7248         if (vmx->nested.virtual_apic_page) {
7249                 nested_release_page(vmx->nested.virtual_apic_page);
7250                 vmx->nested.virtual_apic_page = NULL;
7251         }
7252         if (vmx->nested.pi_desc_page) {
7253                 kunmap(vmx->nested.pi_desc_page);
7254                 nested_release_page(vmx->nested.pi_desc_page);
7255                 vmx->nested.pi_desc_page = NULL;
7256                 vmx->nested.pi_desc = NULL;
7257         }
7258
7259         nested_free_all_saved_vmcss(vmx);
7260 }
7261
7262 /* Emulate the VMXOFF instruction */
7263 static int handle_vmoff(struct kvm_vcpu *vcpu)
7264 {
7265         if (!nested_vmx_check_permission(vcpu))
7266                 return 1;
7267         free_nested(to_vmx(vcpu));
7268         nested_vmx_succeed(vcpu);
7269         return kvm_skip_emulated_instruction(vcpu);
7270 }
7271
7272 /* Emulate the VMCLEAR instruction */
7273 static int handle_vmclear(struct kvm_vcpu *vcpu)
7274 {
7275         struct vcpu_vmx *vmx = to_vmx(vcpu);
7276         u32 zero = 0;
7277         gpa_t vmptr;
7278
7279         if (!nested_vmx_check_permission(vcpu))
7280                 return 1;
7281
7282         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7283                 return 1;
7284
7285         if (vmptr == vmx->nested.current_vmptr)
7286                 nested_release_vmcs12(vmx);
7287
7288         kvm_vcpu_write_guest(vcpu,
7289                         vmptr + offsetof(struct vmcs12, launch_state),
7290                         &zero, sizeof(zero));
7291
7292         nested_free_vmcs02(vmx, vmptr);
7293
7294         nested_vmx_succeed(vcpu);
7295         return kvm_skip_emulated_instruction(vcpu);
7296 }
7297
7298 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7299
7300 /* Emulate the VMLAUNCH instruction */
7301 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7302 {
7303         return nested_vmx_run(vcpu, true);
7304 }
7305
7306 /* Emulate the VMRESUME instruction */
7307 static int handle_vmresume(struct kvm_vcpu *vcpu)
7308 {
7309
7310         return nested_vmx_run(vcpu, false);
7311 }
7312
7313 enum vmcs_field_type {
7314         VMCS_FIELD_TYPE_U16 = 0,
7315         VMCS_FIELD_TYPE_U64 = 1,
7316         VMCS_FIELD_TYPE_U32 = 2,
7317         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7318 };
7319
7320 static inline int vmcs_field_type(unsigned long field)
7321 {
7322         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7323                 return VMCS_FIELD_TYPE_U32;
7324         return (field >> 13) & 0x3 ;
7325 }
7326
7327 static inline int vmcs_field_readonly(unsigned long field)
7328 {
7329         return (((field >> 10) & 0x3) == 1);
7330 }
7331
7332 /*
7333  * Read a vmcs12 field. Since these can have varying lengths and we return
7334  * one type, we chose the biggest type (u64) and zero-extend the return value
7335  * to that size. Note that the caller, handle_vmread, might need to use only
7336  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7337  * 64-bit fields are to be returned).
7338  */
7339 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7340                                   unsigned long field, u64 *ret)
7341 {
7342         short offset = vmcs_field_to_offset(field);
7343         char *p;
7344
7345         if (offset < 0)
7346                 return offset;
7347
7348         p = ((char *)(get_vmcs12(vcpu))) + offset;
7349
7350         switch (vmcs_field_type(field)) {
7351         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7352                 *ret = *((natural_width *)p);
7353                 return 0;
7354         case VMCS_FIELD_TYPE_U16:
7355                 *ret = *((u16 *)p);
7356                 return 0;
7357         case VMCS_FIELD_TYPE_U32:
7358                 *ret = *((u32 *)p);
7359                 return 0;
7360         case VMCS_FIELD_TYPE_U64:
7361                 *ret = *((u64 *)p);
7362                 return 0;
7363         default:
7364                 WARN_ON(1);
7365                 return -ENOENT;
7366         }
7367 }
7368
7369
7370 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7371                                    unsigned long field, u64 field_value){
7372         short offset = vmcs_field_to_offset(field);
7373         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7374         if (offset < 0)
7375                 return offset;
7376
7377         switch (vmcs_field_type(field)) {
7378         case VMCS_FIELD_TYPE_U16:
7379                 *(u16 *)p = field_value;
7380                 return 0;
7381         case VMCS_FIELD_TYPE_U32:
7382                 *(u32 *)p = field_value;
7383                 return 0;
7384         case VMCS_FIELD_TYPE_U64:
7385                 *(u64 *)p = field_value;
7386                 return 0;
7387         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7388                 *(natural_width *)p = field_value;
7389                 return 0;
7390         default:
7391                 WARN_ON(1);
7392                 return -ENOENT;
7393         }
7394
7395 }
7396
7397 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7398 {
7399         int i;
7400         unsigned long field;
7401         u64 field_value;
7402         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7403         const unsigned long *fields = shadow_read_write_fields;
7404         const int num_fields = max_shadow_read_write_fields;
7405
7406         preempt_disable();
7407
7408         vmcs_load(shadow_vmcs);
7409
7410         for (i = 0; i < num_fields; i++) {
7411                 field = fields[i];
7412                 switch (vmcs_field_type(field)) {
7413                 case VMCS_FIELD_TYPE_U16:
7414                         field_value = vmcs_read16(field);
7415                         break;
7416                 case VMCS_FIELD_TYPE_U32:
7417                         field_value = vmcs_read32(field);
7418                         break;
7419                 case VMCS_FIELD_TYPE_U64:
7420                         field_value = vmcs_read64(field);
7421                         break;
7422                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7423                         field_value = vmcs_readl(field);
7424                         break;
7425                 default:
7426                         WARN_ON(1);
7427                         continue;
7428                 }
7429                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7430         }
7431
7432         vmcs_clear(shadow_vmcs);
7433         vmcs_load(vmx->loaded_vmcs->vmcs);
7434
7435         preempt_enable();
7436 }
7437
7438 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7439 {
7440         const unsigned long *fields[] = {
7441                 shadow_read_write_fields,
7442                 shadow_read_only_fields
7443         };
7444         const int max_fields[] = {
7445                 max_shadow_read_write_fields,
7446                 max_shadow_read_only_fields
7447         };
7448         int i, q;
7449         unsigned long field;
7450         u64 field_value = 0;
7451         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7452
7453         vmcs_load(shadow_vmcs);
7454
7455         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7456                 for (i = 0; i < max_fields[q]; i++) {
7457                         field = fields[q][i];
7458                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7459
7460                         switch (vmcs_field_type(field)) {
7461                         case VMCS_FIELD_TYPE_U16:
7462                                 vmcs_write16(field, (u16)field_value);
7463                                 break;
7464                         case VMCS_FIELD_TYPE_U32:
7465                                 vmcs_write32(field, (u32)field_value);
7466                                 break;
7467                         case VMCS_FIELD_TYPE_U64:
7468                                 vmcs_write64(field, (u64)field_value);
7469                                 break;
7470                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7471                                 vmcs_writel(field, (long)field_value);
7472                                 break;
7473                         default:
7474                                 WARN_ON(1);
7475                                 break;
7476                         }
7477                 }
7478         }
7479
7480         vmcs_clear(shadow_vmcs);
7481         vmcs_load(vmx->loaded_vmcs->vmcs);
7482 }
7483
7484 /*
7485  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7486  * used before) all generate the same failure when it is missing.
7487  */
7488 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7489 {
7490         struct vcpu_vmx *vmx = to_vmx(vcpu);
7491         if (vmx->nested.current_vmptr == -1ull) {
7492                 nested_vmx_failInvalid(vcpu);
7493                 return 0;
7494         }
7495         return 1;
7496 }
7497
7498 static int handle_vmread(struct kvm_vcpu *vcpu)
7499 {
7500         unsigned long field;
7501         u64 field_value;
7502         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7503         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7504         gva_t gva = 0;
7505
7506         if (!nested_vmx_check_permission(vcpu))
7507                 return 1;
7508
7509         if (!nested_vmx_check_vmcs12(vcpu))
7510                 return kvm_skip_emulated_instruction(vcpu);
7511
7512         /* Decode instruction info and find the field to read */
7513         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7514         /* Read the field, zero-extended to a u64 field_value */
7515         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7516                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7517                 return kvm_skip_emulated_instruction(vcpu);
7518         }
7519         /*
7520          * Now copy part of this value to register or memory, as requested.
7521          * Note that the number of bits actually copied is 32 or 64 depending
7522          * on the guest's mode (32 or 64 bit), not on the given field's length.
7523          */
7524         if (vmx_instruction_info & (1u << 10)) {
7525                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7526                         field_value);
7527         } else {
7528                 if (get_vmx_mem_address(vcpu, exit_qualification,
7529                                 vmx_instruction_info, true, &gva))
7530                         return 1;
7531                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7532                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7533                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7534         }
7535
7536         nested_vmx_succeed(vcpu);
7537         return kvm_skip_emulated_instruction(vcpu);
7538 }
7539
7540
7541 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7542 {
7543         unsigned long field;
7544         gva_t gva;
7545         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7546         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7547         /* The value to write might be 32 or 64 bits, depending on L1's long
7548          * mode, and eventually we need to write that into a field of several
7549          * possible lengths. The code below first zero-extends the value to 64
7550          * bit (field_value), and then copies only the appropriate number of
7551          * bits into the vmcs12 field.
7552          */
7553         u64 field_value = 0;
7554         struct x86_exception e;
7555
7556         if (!nested_vmx_check_permission(vcpu))
7557                 return 1;
7558
7559         if (!nested_vmx_check_vmcs12(vcpu))
7560                 return kvm_skip_emulated_instruction(vcpu);
7561
7562         if (vmx_instruction_info & (1u << 10))
7563                 field_value = kvm_register_readl(vcpu,
7564                         (((vmx_instruction_info) >> 3) & 0xf));
7565         else {
7566                 if (get_vmx_mem_address(vcpu, exit_qualification,
7567                                 vmx_instruction_info, false, &gva))
7568                         return 1;
7569                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7570                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7571                         kvm_inject_page_fault(vcpu, &e);
7572                         return 1;
7573                 }
7574         }
7575
7576
7577         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7578         if (vmcs_field_readonly(field)) {
7579                 nested_vmx_failValid(vcpu,
7580                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7581                 return kvm_skip_emulated_instruction(vcpu);
7582         }
7583
7584         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7585                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7586                 return kvm_skip_emulated_instruction(vcpu);
7587         }
7588
7589         nested_vmx_succeed(vcpu);
7590         return kvm_skip_emulated_instruction(vcpu);
7591 }
7592
7593 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7594 {
7595         vmx->nested.current_vmptr = vmptr;
7596         if (enable_shadow_vmcs) {
7597                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7598                               SECONDARY_EXEC_SHADOW_VMCS);
7599                 vmcs_write64(VMCS_LINK_POINTER,
7600                              __pa(vmx->vmcs01.shadow_vmcs));
7601                 vmx->nested.sync_shadow_vmcs = true;
7602         }
7603 }
7604
7605 /* Emulate the VMPTRLD instruction */
7606 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7607 {
7608         struct vcpu_vmx *vmx = to_vmx(vcpu);
7609         gpa_t vmptr;
7610
7611         if (!nested_vmx_check_permission(vcpu))
7612                 return 1;
7613
7614         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7615                 return 1;
7616
7617         if (vmx->nested.current_vmptr != vmptr) {
7618                 struct vmcs12 *new_vmcs12;
7619                 struct page *page;
7620                 page = nested_get_page(vcpu, vmptr);
7621                 if (page == NULL) {
7622                         nested_vmx_failInvalid(vcpu);
7623                         return kvm_skip_emulated_instruction(vcpu);
7624                 }
7625                 new_vmcs12 = kmap(page);
7626                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7627                         kunmap(page);
7628                         nested_release_page_clean(page);
7629                         nested_vmx_failValid(vcpu,
7630                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7631                         return kvm_skip_emulated_instruction(vcpu);
7632                 }
7633
7634                 nested_release_vmcs12(vmx);
7635                 vmx->nested.current_vmcs12 = new_vmcs12;
7636                 vmx->nested.current_vmcs12_page = page;
7637                 /*
7638                  * Load VMCS12 from guest memory since it is not already
7639                  * cached.
7640                  */
7641                 memcpy(vmx->nested.cached_vmcs12,
7642                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7643                 set_current_vmptr(vmx, vmptr);
7644         }
7645
7646         nested_vmx_succeed(vcpu);
7647         return kvm_skip_emulated_instruction(vcpu);
7648 }
7649
7650 /* Emulate the VMPTRST instruction */
7651 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7652 {
7653         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7654         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7655         gva_t vmcs_gva;
7656         struct x86_exception e;
7657
7658         if (!nested_vmx_check_permission(vcpu))
7659                 return 1;
7660
7661         if (get_vmx_mem_address(vcpu, exit_qualification,
7662                         vmx_instruction_info, true, &vmcs_gva))
7663                 return 1;
7664         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7665         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7666                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7667                                  sizeof(u64), &e)) {
7668                 kvm_inject_page_fault(vcpu, &e);
7669                 return 1;
7670         }
7671         nested_vmx_succeed(vcpu);
7672         return kvm_skip_emulated_instruction(vcpu);
7673 }
7674
7675 /* Emulate the INVEPT instruction */
7676 static int handle_invept(struct kvm_vcpu *vcpu)
7677 {
7678         struct vcpu_vmx *vmx = to_vmx(vcpu);
7679         u32 vmx_instruction_info, types;
7680         unsigned long type;
7681         gva_t gva;
7682         struct x86_exception e;
7683         struct {
7684                 u64 eptp, gpa;
7685         } operand;
7686
7687         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7688               SECONDARY_EXEC_ENABLE_EPT) ||
7689             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7690                 kvm_queue_exception(vcpu, UD_VECTOR);
7691                 return 1;
7692         }
7693
7694         if (!nested_vmx_check_permission(vcpu))
7695                 return 1;
7696
7697         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7698                 kvm_queue_exception(vcpu, UD_VECTOR);
7699                 return 1;
7700         }
7701
7702         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7703         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7704
7705         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7706
7707         if (type >= 32 || !(types & (1 << type))) {
7708                 nested_vmx_failValid(vcpu,
7709                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7710                 return kvm_skip_emulated_instruction(vcpu);
7711         }
7712
7713         /* According to the Intel VMX instruction reference, the memory
7714          * operand is read even if it isn't needed (e.g., for type==global)
7715          */
7716         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7717                         vmx_instruction_info, false, &gva))
7718                 return 1;
7719         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7720                                 sizeof(operand), &e)) {
7721                 kvm_inject_page_fault(vcpu, &e);
7722                 return 1;
7723         }
7724
7725         switch (type) {
7726         case VMX_EPT_EXTENT_GLOBAL:
7727         /*
7728          * TODO: track mappings and invalidate
7729          * single context requests appropriately
7730          */
7731         case VMX_EPT_EXTENT_CONTEXT:
7732                 kvm_mmu_sync_roots(vcpu);
7733                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7734                 nested_vmx_succeed(vcpu);
7735                 break;
7736         default:
7737                 BUG_ON(1);
7738                 break;
7739         }
7740
7741         return kvm_skip_emulated_instruction(vcpu);
7742 }
7743
7744 static int handle_invvpid(struct kvm_vcpu *vcpu)
7745 {
7746         struct vcpu_vmx *vmx = to_vmx(vcpu);
7747         u32 vmx_instruction_info;
7748         unsigned long type, types;
7749         gva_t gva;
7750         struct x86_exception e;
7751         int vpid;
7752
7753         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7754               SECONDARY_EXEC_ENABLE_VPID) ||
7755                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7756                 kvm_queue_exception(vcpu, UD_VECTOR);
7757                 return 1;
7758         }
7759
7760         if (!nested_vmx_check_permission(vcpu))
7761                 return 1;
7762
7763         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7764         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7765
7766         types = (vmx->nested.nested_vmx_vpid_caps &
7767                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7768
7769         if (type >= 32 || !(types & (1 << type))) {
7770                 nested_vmx_failValid(vcpu,
7771                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7772                 return kvm_skip_emulated_instruction(vcpu);
7773         }
7774
7775         /* according to the intel vmx instruction reference, the memory
7776          * operand is read even if it isn't needed (e.g., for type==global)
7777          */
7778         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7779                         vmx_instruction_info, false, &gva))
7780                 return 1;
7781         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7782                                 sizeof(u32), &e)) {
7783                 kvm_inject_page_fault(vcpu, &e);
7784                 return 1;
7785         }
7786
7787         switch (type) {
7788         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7789         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7790         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7791                 if (!vpid) {
7792                         nested_vmx_failValid(vcpu,
7793                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7794                         return kvm_skip_emulated_instruction(vcpu);
7795                 }
7796                 break;
7797         case VMX_VPID_EXTENT_ALL_CONTEXT:
7798                 break;
7799         default:
7800                 WARN_ON_ONCE(1);
7801                 return kvm_skip_emulated_instruction(vcpu);
7802         }
7803
7804         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7805         nested_vmx_succeed(vcpu);
7806
7807         return kvm_skip_emulated_instruction(vcpu);
7808 }
7809
7810 static int handle_pml_full(struct kvm_vcpu *vcpu)
7811 {
7812         unsigned long exit_qualification;
7813
7814         trace_kvm_pml_full(vcpu->vcpu_id);
7815
7816         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7817
7818         /*
7819          * PML buffer FULL happened while executing iret from NMI,
7820          * "blocked by NMI" bit has to be set before next VM entry.
7821          */
7822         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7823                         cpu_has_virtual_nmis() &&
7824                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7825                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7826                                 GUEST_INTR_STATE_NMI);
7827
7828         /*
7829          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7830          * here.., and there's no userspace involvement needed for PML.
7831          */
7832         return 1;
7833 }
7834
7835 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7836 {
7837         kvm_lapic_expired_hv_timer(vcpu);
7838         return 1;
7839 }
7840
7841 /*
7842  * The exit handlers return 1 if the exit was handled fully and guest execution
7843  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7844  * to be done to userspace and return 0.
7845  */
7846 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7847         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7848         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7849         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7850         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7851         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7852         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7853         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7854         [EXIT_REASON_CPUID]                   = handle_cpuid,
7855         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7856         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7857         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7858         [EXIT_REASON_HLT]                     = handle_halt,
7859         [EXIT_REASON_INVD]                    = handle_invd,
7860         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7861         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7862         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7863         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7864         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7865         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7866         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7867         [EXIT_REASON_VMREAD]                  = handle_vmread,
7868         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7869         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7870         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7871         [EXIT_REASON_VMON]                    = handle_vmon,
7872         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7873         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7874         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7875         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7876         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7877         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7878         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7879         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7880         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7881         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7882         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7883         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7884         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7885         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7886         [EXIT_REASON_INVEPT]                  = handle_invept,
7887         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7888         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7889         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7890         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7891         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7892 };
7893
7894 static const int kvm_vmx_max_exit_handlers =
7895         ARRAY_SIZE(kvm_vmx_exit_handlers);
7896
7897 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7898                                        struct vmcs12 *vmcs12)
7899 {
7900         unsigned long exit_qualification;
7901         gpa_t bitmap, last_bitmap;
7902         unsigned int port;
7903         int size;
7904         u8 b;
7905
7906         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7907                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7908
7909         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7910
7911         port = exit_qualification >> 16;
7912         size = (exit_qualification & 7) + 1;
7913
7914         last_bitmap = (gpa_t)-1;
7915         b = -1;
7916
7917         while (size > 0) {
7918                 if (port < 0x8000)
7919                         bitmap = vmcs12->io_bitmap_a;
7920                 else if (port < 0x10000)
7921                         bitmap = vmcs12->io_bitmap_b;
7922                 else
7923                         return true;
7924                 bitmap += (port & 0x7fff) / 8;
7925
7926                 if (last_bitmap != bitmap)
7927                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7928                                 return true;
7929                 if (b & (1 << (port & 7)))
7930                         return true;
7931
7932                 port++;
7933                 size--;
7934                 last_bitmap = bitmap;
7935         }
7936
7937         return false;
7938 }
7939
7940 /*
7941  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7942  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7943  * disinterest in the current event (read or write a specific MSR) by using an
7944  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7945  */
7946 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7947         struct vmcs12 *vmcs12, u32 exit_reason)
7948 {
7949         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7950         gpa_t bitmap;
7951
7952         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7953                 return true;
7954
7955         /*
7956          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7957          * for the four combinations of read/write and low/high MSR numbers.
7958          * First we need to figure out which of the four to use:
7959          */
7960         bitmap = vmcs12->msr_bitmap;
7961         if (exit_reason == EXIT_REASON_MSR_WRITE)
7962                 bitmap += 2048;
7963         if (msr_index >= 0xc0000000) {
7964                 msr_index -= 0xc0000000;
7965                 bitmap += 1024;
7966         }
7967
7968         /* Then read the msr_index'th bit from this bitmap: */
7969         if (msr_index < 1024*8) {
7970                 unsigned char b;
7971                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7972                         return true;
7973                 return 1 & (b >> (msr_index & 7));
7974         } else
7975                 return true; /* let L1 handle the wrong parameter */
7976 }
7977
7978 /*
7979  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7980  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7981  * intercept (via guest_host_mask etc.) the current event.
7982  */
7983 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7984         struct vmcs12 *vmcs12)
7985 {
7986         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7987         int cr = exit_qualification & 15;
7988         int reg = (exit_qualification >> 8) & 15;
7989         unsigned long val = kvm_register_readl(vcpu, reg);
7990
7991         switch ((exit_qualification >> 4) & 3) {
7992         case 0: /* mov to cr */
7993                 switch (cr) {
7994                 case 0:
7995                         if (vmcs12->cr0_guest_host_mask &
7996                             (val ^ vmcs12->cr0_read_shadow))
7997                                 return true;
7998                         break;
7999                 case 3:
8000                         if ((vmcs12->cr3_target_count >= 1 &&
8001                                         vmcs12->cr3_target_value0 == val) ||
8002                                 (vmcs12->cr3_target_count >= 2 &&
8003                                         vmcs12->cr3_target_value1 == val) ||
8004                                 (vmcs12->cr3_target_count >= 3 &&
8005                                         vmcs12->cr3_target_value2 == val) ||
8006                                 (vmcs12->cr3_target_count >= 4 &&
8007                                         vmcs12->cr3_target_value3 == val))
8008                                 return false;
8009                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8010                                 return true;
8011                         break;
8012                 case 4:
8013                         if (vmcs12->cr4_guest_host_mask &
8014                             (vmcs12->cr4_read_shadow ^ val))
8015                                 return true;
8016                         break;
8017                 case 8:
8018                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8019                                 return true;
8020                         break;
8021                 }
8022                 break;
8023         case 2: /* clts */
8024                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8025                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8026                         return true;
8027                 break;
8028         case 1: /* mov from cr */
8029                 switch (cr) {
8030                 case 3:
8031                         if (vmcs12->cpu_based_vm_exec_control &
8032                             CPU_BASED_CR3_STORE_EXITING)
8033                                 return true;
8034                         break;
8035                 case 8:
8036                         if (vmcs12->cpu_based_vm_exec_control &
8037                             CPU_BASED_CR8_STORE_EXITING)
8038                                 return true;
8039                         break;
8040                 }
8041                 break;
8042         case 3: /* lmsw */
8043                 /*
8044                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8045                  * cr0. Other attempted changes are ignored, with no exit.
8046                  */
8047                 if (vmcs12->cr0_guest_host_mask & 0xe &
8048                     (val ^ vmcs12->cr0_read_shadow))
8049                         return true;
8050                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8051                     !(vmcs12->cr0_read_shadow & 0x1) &&
8052                     (val & 0x1))
8053                         return true;
8054                 break;
8055         }
8056         return false;
8057 }
8058
8059 /*
8060  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8061  * should handle it ourselves in L0 (and then continue L2). Only call this
8062  * when in is_guest_mode (L2).
8063  */
8064 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8065 {
8066         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8067         struct vcpu_vmx *vmx = to_vmx(vcpu);
8068         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8069         u32 exit_reason = vmx->exit_reason;
8070
8071         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8072                                 vmcs_readl(EXIT_QUALIFICATION),
8073                                 vmx->idt_vectoring_info,
8074                                 intr_info,
8075                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8076                                 KVM_ISA_VMX);
8077
8078         if (vmx->nested.nested_run_pending)
8079                 return false;
8080
8081         if (unlikely(vmx->fail)) {
8082                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8083                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8084                 return true;
8085         }
8086
8087         switch (exit_reason) {
8088         case EXIT_REASON_EXCEPTION_NMI:
8089                 if (is_nmi(intr_info))
8090                         return false;
8091                 else if (is_page_fault(intr_info))
8092                         return enable_ept;
8093                 else if (is_no_device(intr_info) &&
8094                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8095                         return false;
8096                 else if (is_debug(intr_info) &&
8097                          vcpu->guest_debug &
8098                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8099                         return false;
8100                 else if (is_breakpoint(intr_info) &&
8101                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8102                         return false;
8103                 return vmcs12->exception_bitmap &
8104                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8105         case EXIT_REASON_EXTERNAL_INTERRUPT:
8106                 return false;
8107         case EXIT_REASON_TRIPLE_FAULT:
8108                 return true;
8109         case EXIT_REASON_PENDING_INTERRUPT:
8110                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8111         case EXIT_REASON_NMI_WINDOW:
8112                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8113         case EXIT_REASON_TASK_SWITCH:
8114                 return true;
8115         case EXIT_REASON_CPUID:
8116                 return true;
8117         case EXIT_REASON_HLT:
8118                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8119         case EXIT_REASON_INVD:
8120                 return true;
8121         case EXIT_REASON_INVLPG:
8122                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8123         case EXIT_REASON_RDPMC:
8124                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8125         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8126                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8127         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8128         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8129         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8130         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8131         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8132         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8133                 /*
8134                  * VMX instructions trap unconditionally. This allows L1 to
8135                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8136                  */
8137                 return true;
8138         case EXIT_REASON_CR_ACCESS:
8139                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8140         case EXIT_REASON_DR_ACCESS:
8141                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8142         case EXIT_REASON_IO_INSTRUCTION:
8143                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8144         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8145                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8146         case EXIT_REASON_MSR_READ:
8147         case EXIT_REASON_MSR_WRITE:
8148                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8149         case EXIT_REASON_INVALID_STATE:
8150                 return true;
8151         case EXIT_REASON_MWAIT_INSTRUCTION:
8152                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8153         case EXIT_REASON_MONITOR_TRAP_FLAG:
8154                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8155         case EXIT_REASON_MONITOR_INSTRUCTION:
8156                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8157         case EXIT_REASON_PAUSE_INSTRUCTION:
8158                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8159                         nested_cpu_has2(vmcs12,
8160                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8161         case EXIT_REASON_MCE_DURING_VMENTRY:
8162                 return false;
8163         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8164                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8165         case EXIT_REASON_APIC_ACCESS:
8166                 return nested_cpu_has2(vmcs12,
8167                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8168         case EXIT_REASON_APIC_WRITE:
8169         case EXIT_REASON_EOI_INDUCED:
8170                 /* apic_write and eoi_induced should exit unconditionally. */
8171                 return true;
8172         case EXIT_REASON_EPT_VIOLATION:
8173                 /*
8174                  * L0 always deals with the EPT violation. If nested EPT is
8175                  * used, and the nested mmu code discovers that the address is
8176                  * missing in the guest EPT table (EPT12), the EPT violation
8177                  * will be injected with nested_ept_inject_page_fault()
8178                  */
8179                 return false;
8180         case EXIT_REASON_EPT_MISCONFIG:
8181                 /*
8182                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8183                  * table (shadow on EPT) or a merged EPT table that L0 built
8184                  * (EPT on EPT). So any problems with the structure of the
8185                  * table is L0's fault.
8186                  */
8187                 return false;
8188         case EXIT_REASON_WBINVD:
8189                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8190         case EXIT_REASON_XSETBV:
8191                 return true;
8192         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8193                 /*
8194                  * This should never happen, since it is not possible to
8195                  * set XSS to a non-zero value---neither in L1 nor in L2.
8196                  * If if it were, XSS would have to be checked against
8197                  * the XSS exit bitmap in vmcs12.
8198                  */
8199                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8200         case EXIT_REASON_PREEMPTION_TIMER:
8201                 return false;
8202         default:
8203                 return true;
8204         }
8205 }
8206
8207 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8208 {
8209         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8210         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8211 }
8212
8213 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8214 {
8215         if (vmx->pml_pg) {
8216                 __free_page(vmx->pml_pg);
8217                 vmx->pml_pg = NULL;
8218         }
8219 }
8220
8221 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8222 {
8223         struct vcpu_vmx *vmx = to_vmx(vcpu);
8224         u64 *pml_buf;
8225         u16 pml_idx;
8226
8227         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8228
8229         /* Do nothing if PML buffer is empty */
8230         if (pml_idx == (PML_ENTITY_NUM - 1))
8231                 return;
8232
8233         /* PML index always points to next available PML buffer entity */
8234         if (pml_idx >= PML_ENTITY_NUM)
8235                 pml_idx = 0;
8236         else
8237                 pml_idx++;
8238
8239         pml_buf = page_address(vmx->pml_pg);
8240         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8241                 u64 gpa;
8242
8243                 gpa = pml_buf[pml_idx];
8244                 WARN_ON(gpa & (PAGE_SIZE - 1));
8245                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8246         }
8247
8248         /* reset PML index */
8249         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8250 }
8251
8252 /*
8253  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8254  * Called before reporting dirty_bitmap to userspace.
8255  */
8256 static void kvm_flush_pml_buffers(struct kvm *kvm)
8257 {
8258         int i;
8259         struct kvm_vcpu *vcpu;
8260         /*
8261          * We only need to kick vcpu out of guest mode here, as PML buffer
8262          * is flushed at beginning of all VMEXITs, and it's obvious that only
8263          * vcpus running in guest are possible to have unflushed GPAs in PML
8264          * buffer.
8265          */
8266         kvm_for_each_vcpu(i, vcpu, kvm)
8267                 kvm_vcpu_kick(vcpu);
8268 }
8269
8270 static void vmx_dump_sel(char *name, uint32_t sel)
8271 {
8272         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8273                name, vmcs_read16(sel),
8274                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8275                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8276                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8277 }
8278
8279 static void vmx_dump_dtsel(char *name, uint32_t limit)
8280 {
8281         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8282                name, vmcs_read32(limit),
8283                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8284 }
8285
8286 static void dump_vmcs(void)
8287 {
8288         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8289         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8290         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8291         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8292         u32 secondary_exec_control = 0;
8293         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8294         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8295         int i, n;
8296
8297         if (cpu_has_secondary_exec_ctrls())
8298                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8299
8300         pr_err("*** Guest State ***\n");
8301         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8302                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8303                vmcs_readl(CR0_GUEST_HOST_MASK));
8304         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8305                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8306         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8307         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8308             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8309         {
8310                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8311                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8312                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8313                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8314         }
8315         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8316                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8317         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8318                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8319         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8320                vmcs_readl(GUEST_SYSENTER_ESP),
8321                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8322         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8323         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8324         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8325         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8326         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8327         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8328         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8329         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8330         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8331         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8332         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8333             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8334                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8335                        efer, vmcs_read64(GUEST_IA32_PAT));
8336         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8337                vmcs_read64(GUEST_IA32_DEBUGCTL),
8338                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8339         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8340                 pr_err("PerfGlobCtl = 0x%016llx\n",
8341                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8342         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8343                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8344         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8345                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8346                vmcs_read32(GUEST_ACTIVITY_STATE));
8347         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8348                 pr_err("InterruptStatus = %04x\n",
8349                        vmcs_read16(GUEST_INTR_STATUS));
8350
8351         pr_err("*** Host State ***\n");
8352         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8353                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8354         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8355                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8356                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8357                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8358                vmcs_read16(HOST_TR_SELECTOR));
8359         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8360                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8361                vmcs_readl(HOST_TR_BASE));
8362         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8363                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8364         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8365                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8366                vmcs_readl(HOST_CR4));
8367         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8368                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8369                vmcs_read32(HOST_IA32_SYSENTER_CS),
8370                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8371         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8372                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8373                        vmcs_read64(HOST_IA32_EFER),
8374                        vmcs_read64(HOST_IA32_PAT));
8375         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8376                 pr_err("PerfGlobCtl = 0x%016llx\n",
8377                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8378
8379         pr_err("*** Control State ***\n");
8380         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8381                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8382         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8383         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8384                vmcs_read32(EXCEPTION_BITMAP),
8385                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8386                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8387         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8388                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8389                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8390                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8391         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8392                vmcs_read32(VM_EXIT_INTR_INFO),
8393                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8394                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8395         pr_err("        reason=%08x qualification=%016lx\n",
8396                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8397         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8398                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8399                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8400         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8401         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8402                 pr_err("TSC Multiplier = 0x%016llx\n",
8403                        vmcs_read64(TSC_MULTIPLIER));
8404         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8405                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8406         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8407                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8408         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8409                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8410         n = vmcs_read32(CR3_TARGET_COUNT);
8411         for (i = 0; i + 1 < n; i += 4)
8412                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8413                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8414                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8415         if (i < n)
8416                 pr_err("CR3 target%u=%016lx\n",
8417                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8418         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8419                 pr_err("PLE Gap=%08x Window=%08x\n",
8420                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8421         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8422                 pr_err("Virtual processor ID = 0x%04x\n",
8423                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8424 }
8425
8426 /*
8427  * The guest has exited.  See if we can fix it or if we need userspace
8428  * assistance.
8429  */
8430 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8431 {
8432         struct vcpu_vmx *vmx = to_vmx(vcpu);
8433         u32 exit_reason = vmx->exit_reason;
8434         u32 vectoring_info = vmx->idt_vectoring_info;
8435
8436         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8437         vcpu->arch.gpa_available = false;
8438
8439         /*
8440          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8441          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8442          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8443          * mode as if vcpus is in root mode, the PML buffer must has been
8444          * flushed already.
8445          */
8446         if (enable_pml)
8447                 vmx_flush_pml_buffer(vcpu);
8448
8449         /* If guest state is invalid, start emulating */
8450         if (vmx->emulation_required)
8451                 return handle_invalid_guest_state(vcpu);
8452
8453         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8454                 nested_vmx_vmexit(vcpu, exit_reason,
8455                                   vmcs_read32(VM_EXIT_INTR_INFO),
8456                                   vmcs_readl(EXIT_QUALIFICATION));
8457                 return 1;
8458         }
8459
8460         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8461                 dump_vmcs();
8462                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8463                 vcpu->run->fail_entry.hardware_entry_failure_reason
8464                         = exit_reason;
8465                 return 0;
8466         }
8467
8468         if (unlikely(vmx->fail)) {
8469                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8470                 vcpu->run->fail_entry.hardware_entry_failure_reason
8471                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8472                 return 0;
8473         }
8474
8475         /*
8476          * Note:
8477          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8478          * delivery event since it indicates guest is accessing MMIO.
8479          * The vm-exit can be triggered again after return to guest that
8480          * will cause infinite loop.
8481          */
8482         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8483                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8484                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8485                         exit_reason != EXIT_REASON_PML_FULL &&
8486                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8487                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8488                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8489                 vcpu->run->internal.ndata = 2;
8490                 vcpu->run->internal.data[0] = vectoring_info;
8491                 vcpu->run->internal.data[1] = exit_reason;
8492                 return 0;
8493         }
8494
8495         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8496             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8497                                         get_vmcs12(vcpu))))) {
8498                 if (vmx_interrupt_allowed(vcpu)) {
8499                         vmx->soft_vnmi_blocked = 0;
8500                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8501                            vcpu->arch.nmi_pending) {
8502                         /*
8503                          * This CPU don't support us in finding the end of an
8504                          * NMI-blocked window if the guest runs with IRQs
8505                          * disabled. So we pull the trigger after 1 s of
8506                          * futile waiting, but inform the user about this.
8507                          */
8508                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8509                                "state on VCPU %d after 1 s timeout\n",
8510                                __func__, vcpu->vcpu_id);
8511                         vmx->soft_vnmi_blocked = 0;
8512                 }
8513         }
8514
8515         if (exit_reason < kvm_vmx_max_exit_handlers
8516             && kvm_vmx_exit_handlers[exit_reason])
8517                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8518         else {
8519                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8520                                 exit_reason);
8521                 kvm_queue_exception(vcpu, UD_VECTOR);
8522                 return 1;
8523         }
8524 }
8525
8526 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8527 {
8528         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8529
8530         if (is_guest_mode(vcpu) &&
8531                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8532                 return;
8533
8534         if (irr == -1 || tpr < irr) {
8535                 vmcs_write32(TPR_THRESHOLD, 0);
8536                 return;
8537         }
8538
8539         vmcs_write32(TPR_THRESHOLD, irr);
8540 }
8541
8542 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8543 {
8544         u32 sec_exec_control;
8545
8546         /* Postpone execution until vmcs01 is the current VMCS. */
8547         if (is_guest_mode(vcpu)) {
8548                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8549                 return;
8550         }
8551
8552         if (!cpu_has_vmx_virtualize_x2apic_mode())
8553                 return;
8554
8555         if (!cpu_need_tpr_shadow(vcpu))
8556                 return;
8557
8558         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8559
8560         if (set) {
8561                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8562                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8563         } else {
8564                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8565                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8566                 vmx_flush_tlb_ept_only(vcpu);
8567         }
8568         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8569
8570         vmx_set_msr_bitmap(vcpu);
8571 }
8572
8573 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8574 {
8575         struct vcpu_vmx *vmx = to_vmx(vcpu);
8576
8577         /*
8578          * Currently we do not handle the nested case where L2 has an
8579          * APIC access page of its own; that page is still pinned.
8580          * Hence, we skip the case where the VCPU is in guest mode _and_
8581          * L1 prepared an APIC access page for L2.
8582          *
8583          * For the case where L1 and L2 share the same APIC access page
8584          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8585          * in the vmcs12), this function will only update either the vmcs01
8586          * or the vmcs02.  If the former, the vmcs02 will be updated by
8587          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8588          * the next L2->L1 exit.
8589          */
8590         if (!is_guest_mode(vcpu) ||
8591             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8592                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8593                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8594                 vmx_flush_tlb_ept_only(vcpu);
8595         }
8596 }
8597
8598 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8599 {
8600         u16 status;
8601         u8 old;
8602
8603         if (max_isr == -1)
8604                 max_isr = 0;
8605
8606         status = vmcs_read16(GUEST_INTR_STATUS);
8607         old = status >> 8;
8608         if (max_isr != old) {
8609                 status &= 0xff;
8610                 status |= max_isr << 8;
8611                 vmcs_write16(GUEST_INTR_STATUS, status);
8612         }
8613 }
8614
8615 static void vmx_set_rvi(int vector)
8616 {
8617         u16 status;
8618         u8 old;
8619
8620         if (vector == -1)
8621                 vector = 0;
8622
8623         status = vmcs_read16(GUEST_INTR_STATUS);
8624         old = (u8)status & 0xff;
8625         if ((u8)vector != old) {
8626                 status &= ~0xff;
8627                 status |= (u8)vector;
8628                 vmcs_write16(GUEST_INTR_STATUS, status);
8629         }
8630 }
8631
8632 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8633 {
8634         if (!is_guest_mode(vcpu)) {
8635                 vmx_set_rvi(max_irr);
8636                 return;
8637         }
8638
8639         if (max_irr == -1)
8640                 return;
8641
8642         /*
8643          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8644          * handles it.
8645          */
8646         if (nested_exit_on_intr(vcpu))
8647                 return;
8648
8649         /*
8650          * Else, fall back to pre-APICv interrupt injection since L2
8651          * is run without virtual interrupt delivery.
8652          */
8653         if (!kvm_event_needs_reinjection(vcpu) &&
8654             vmx_interrupt_allowed(vcpu)) {
8655                 kvm_queue_interrupt(vcpu, max_irr, false);
8656                 vmx_inject_irq(vcpu);
8657         }
8658 }
8659
8660 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8661 {
8662         struct vcpu_vmx *vmx = to_vmx(vcpu);
8663         int max_irr;
8664
8665         WARN_ON(!vcpu->arch.apicv_active);
8666         if (pi_test_on(&vmx->pi_desc)) {
8667                 pi_clear_on(&vmx->pi_desc);
8668                 /*
8669                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8670                  * But on x86 this is just a compiler barrier anyway.
8671                  */
8672                 smp_mb__after_atomic();
8673                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8674         } else {
8675                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8676         }
8677         vmx_hwapic_irr_update(vcpu, max_irr);
8678         return max_irr;
8679 }
8680
8681 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8682 {
8683         if (!kvm_vcpu_apicv_active(vcpu))
8684                 return;
8685
8686         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8687         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8688         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8689         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8690 }
8691
8692 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8693 {
8694         struct vcpu_vmx *vmx = to_vmx(vcpu);
8695
8696         pi_clear_on(&vmx->pi_desc);
8697         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8698 }
8699
8700 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8701 {
8702         u32 exit_intr_info;
8703
8704         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8705               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8706                 return;
8707
8708         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8709         exit_intr_info = vmx->exit_intr_info;
8710
8711         /* Handle machine checks before interrupts are enabled */
8712         if (is_machine_check(exit_intr_info))
8713                 kvm_machine_check();
8714
8715         /* We need to handle NMIs before interrupts are enabled */
8716         if (is_nmi(exit_intr_info)) {
8717                 kvm_before_handle_nmi(&vmx->vcpu);
8718                 asm("int $2");
8719                 kvm_after_handle_nmi(&vmx->vcpu);
8720         }
8721 }
8722
8723 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8724 {
8725         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8726         register void *__sp asm(_ASM_SP);
8727
8728         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8729                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8730                 unsigned int vector;
8731                 unsigned long entry;
8732                 gate_desc *desc;
8733                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8734 #ifdef CONFIG_X86_64
8735                 unsigned long tmp;
8736 #endif
8737
8738                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8739                 desc = (gate_desc *)vmx->host_idt_base + vector;
8740                 entry = gate_offset(*desc);
8741                 asm volatile(
8742 #ifdef CONFIG_X86_64
8743                         "mov %%" _ASM_SP ", %[sp]\n\t"
8744                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8745                         "push $%c[ss]\n\t"
8746                         "push %[sp]\n\t"
8747 #endif
8748                         "pushf\n\t"
8749                         __ASM_SIZE(push) " $%c[cs]\n\t"
8750                         "call *%[entry]\n\t"
8751                         :
8752 #ifdef CONFIG_X86_64
8753                         [sp]"=&r"(tmp),
8754 #endif
8755                         "+r"(__sp)
8756                         :
8757                         [entry]"r"(entry),
8758                         [ss]"i"(__KERNEL_DS),
8759                         [cs]"i"(__KERNEL_CS)
8760                         );
8761         }
8762 }
8763
8764 static bool vmx_has_high_real_mode_segbase(void)
8765 {
8766         return enable_unrestricted_guest || emulate_invalid_guest_state;
8767 }
8768
8769 static bool vmx_mpx_supported(void)
8770 {
8771         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8772                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8773 }
8774
8775 static bool vmx_xsaves_supported(void)
8776 {
8777         return vmcs_config.cpu_based_2nd_exec_ctrl &
8778                 SECONDARY_EXEC_XSAVES;
8779 }
8780
8781 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8782 {
8783         u32 exit_intr_info;
8784         bool unblock_nmi;
8785         u8 vector;
8786         bool idtv_info_valid;
8787
8788         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8789
8790         if (cpu_has_virtual_nmis()) {
8791                 if (vmx->nmi_known_unmasked)
8792                         return;
8793                 /*
8794                  * Can't use vmx->exit_intr_info since we're not sure what
8795                  * the exit reason is.
8796                  */
8797                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8798                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8799                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8800                 /*
8801                  * SDM 3: 27.7.1.2 (September 2008)
8802                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8803                  * a guest IRET fault.
8804                  * SDM 3: 23.2.2 (September 2008)
8805                  * Bit 12 is undefined in any of the following cases:
8806                  *  If the VM exit sets the valid bit in the IDT-vectoring
8807                  *   information field.
8808                  *  If the VM exit is due to a double fault.
8809                  */
8810                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8811                     vector != DF_VECTOR && !idtv_info_valid)
8812                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8813                                       GUEST_INTR_STATE_NMI);
8814                 else
8815                         vmx->nmi_known_unmasked =
8816                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8817                                   & GUEST_INTR_STATE_NMI);
8818         } else if (unlikely(vmx->soft_vnmi_blocked))
8819                 vmx->vnmi_blocked_time +=
8820                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8821 }
8822
8823 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8824                                       u32 idt_vectoring_info,
8825                                       int instr_len_field,
8826                                       int error_code_field)
8827 {
8828         u8 vector;
8829         int type;
8830         bool idtv_info_valid;
8831
8832         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8833
8834         vcpu->arch.nmi_injected = false;
8835         kvm_clear_exception_queue(vcpu);
8836         kvm_clear_interrupt_queue(vcpu);
8837
8838         if (!idtv_info_valid)
8839                 return;
8840
8841         kvm_make_request(KVM_REQ_EVENT, vcpu);
8842
8843         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8844         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8845
8846         switch (type) {
8847         case INTR_TYPE_NMI_INTR:
8848                 vcpu->arch.nmi_injected = true;
8849                 /*
8850                  * SDM 3: 27.7.1.2 (September 2008)
8851                  * Clear bit "block by NMI" before VM entry if a NMI
8852                  * delivery faulted.
8853                  */
8854                 vmx_set_nmi_mask(vcpu, false);
8855                 break;
8856         case INTR_TYPE_SOFT_EXCEPTION:
8857                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8858                 /* fall through */
8859         case INTR_TYPE_HARD_EXCEPTION:
8860                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8861                         u32 err = vmcs_read32(error_code_field);
8862                         kvm_requeue_exception_e(vcpu, vector, err);
8863                 } else
8864                         kvm_requeue_exception(vcpu, vector);
8865                 break;
8866         case INTR_TYPE_SOFT_INTR:
8867                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8868                 /* fall through */
8869         case INTR_TYPE_EXT_INTR:
8870                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8871                 break;
8872         default:
8873                 break;
8874         }
8875 }
8876
8877 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8878 {
8879         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8880                                   VM_EXIT_INSTRUCTION_LEN,
8881                                   IDT_VECTORING_ERROR_CODE);
8882 }
8883
8884 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8885 {
8886         __vmx_complete_interrupts(vcpu,
8887                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8888                                   VM_ENTRY_INSTRUCTION_LEN,
8889                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8890
8891         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8892 }
8893
8894 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8895 {
8896         int i, nr_msrs;
8897         struct perf_guest_switch_msr *msrs;
8898
8899         msrs = perf_guest_get_msrs(&nr_msrs);
8900
8901         if (!msrs)
8902                 return;
8903
8904         for (i = 0; i < nr_msrs; i++)
8905                 if (msrs[i].host == msrs[i].guest)
8906                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8907                 else
8908                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8909                                         msrs[i].host);
8910 }
8911
8912 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8913 {
8914         struct vcpu_vmx *vmx = to_vmx(vcpu);
8915         u64 tscl;
8916         u32 delta_tsc;
8917
8918         if (vmx->hv_deadline_tsc == -1)
8919                 return;
8920
8921         tscl = rdtsc();
8922         if (vmx->hv_deadline_tsc > tscl)
8923                 /* sure to be 32 bit only because checked on set_hv_timer */
8924                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8925                         cpu_preemption_timer_multi);
8926         else
8927                 delta_tsc = 0;
8928
8929         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8930 }
8931
8932 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8933 {
8934         struct vcpu_vmx *vmx = to_vmx(vcpu);
8935         unsigned long debugctlmsr, cr4;
8936
8937         /* Record the guest's net vcpu time for enforced NMI injections. */
8938         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8939                 vmx->entry_time = ktime_get();
8940
8941         /* Don't enter VMX if guest state is invalid, let the exit handler
8942            start emulation until we arrive back to a valid state */
8943         if (vmx->emulation_required)
8944                 return;
8945
8946         if (vmx->ple_window_dirty) {
8947                 vmx->ple_window_dirty = false;
8948                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8949         }
8950
8951         if (vmx->nested.sync_shadow_vmcs) {
8952                 copy_vmcs12_to_shadow(vmx);
8953                 vmx->nested.sync_shadow_vmcs = false;
8954         }
8955
8956         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8957                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8958         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8959                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8960
8961         cr4 = cr4_read_shadow();
8962         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8963                 vmcs_writel(HOST_CR4, cr4);
8964                 vmx->host_state.vmcs_host_cr4 = cr4;
8965         }
8966
8967         /* When single-stepping over STI and MOV SS, we must clear the
8968          * corresponding interruptibility bits in the guest state. Otherwise
8969          * vmentry fails as it then expects bit 14 (BS) in pending debug
8970          * exceptions being set, but that's not correct for the guest debugging
8971          * case. */
8972         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8973                 vmx_set_interrupt_shadow(vcpu, 0);
8974
8975         if (vmx->guest_pkru_valid)
8976                 __write_pkru(vmx->guest_pkru);
8977
8978         atomic_switch_perf_msrs(vmx);
8979         debugctlmsr = get_debugctlmsr();
8980
8981         vmx_arm_hv_timer(vcpu);
8982
8983         vmx->__launched = vmx->loaded_vmcs->launched;
8984         asm(
8985                 /* Store host registers */
8986                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8987                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8988                 "push %%" _ASM_CX " \n\t"
8989                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8990                 "je 1f \n\t"
8991                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8992                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8993                 "1: \n\t"
8994                 /* Reload cr2 if changed */
8995                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8996                 "mov %%cr2, %%" _ASM_DX " \n\t"
8997                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8998                 "je 2f \n\t"
8999                 "mov %%" _ASM_AX", %%cr2 \n\t"
9000                 "2: \n\t"
9001                 /* Check if vmlaunch of vmresume is needed */
9002                 "cmpl $0, %c[launched](%0) \n\t"
9003                 /* Load guest registers.  Don't clobber flags. */
9004                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9005                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9006                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9007                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9008                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9009                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9010 #ifdef CONFIG_X86_64
9011                 "mov %c[r8](%0),  %%r8  \n\t"
9012                 "mov %c[r9](%0),  %%r9  \n\t"
9013                 "mov %c[r10](%0), %%r10 \n\t"
9014                 "mov %c[r11](%0), %%r11 \n\t"
9015                 "mov %c[r12](%0), %%r12 \n\t"
9016                 "mov %c[r13](%0), %%r13 \n\t"
9017                 "mov %c[r14](%0), %%r14 \n\t"
9018                 "mov %c[r15](%0), %%r15 \n\t"
9019 #endif
9020                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9021
9022                 /* Enter guest mode */
9023                 "jne 1f \n\t"
9024                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9025                 "jmp 2f \n\t"
9026                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9027                 "2: "
9028                 /* Save guest registers, load host registers, keep flags */
9029                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9030                 "pop %0 \n\t"
9031                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9032                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9033                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9034                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9035                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9036                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9037                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9038 #ifdef CONFIG_X86_64
9039                 "mov %%r8,  %c[r8](%0) \n\t"
9040                 "mov %%r9,  %c[r9](%0) \n\t"
9041                 "mov %%r10, %c[r10](%0) \n\t"
9042                 "mov %%r11, %c[r11](%0) \n\t"
9043                 "mov %%r12, %c[r12](%0) \n\t"
9044                 "mov %%r13, %c[r13](%0) \n\t"
9045                 "mov %%r14, %c[r14](%0) \n\t"
9046                 "mov %%r15, %c[r15](%0) \n\t"
9047 #endif
9048                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9049                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9050
9051                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9052                 "setbe %c[fail](%0) \n\t"
9053                 ".pushsection .rodata \n\t"
9054                 ".global vmx_return \n\t"
9055                 "vmx_return: " _ASM_PTR " 2b \n\t"
9056                 ".popsection"
9057               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9058                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9059                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9060                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9061                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9062                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9063                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9064                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9065                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9066                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9067                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9068 #ifdef CONFIG_X86_64
9069                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9070                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9071                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9072                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9073                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9074                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9075                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9076                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9077 #endif
9078                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9079                 [wordsize]"i"(sizeof(ulong))
9080               : "cc", "memory"
9081 #ifdef CONFIG_X86_64
9082                 , "rax", "rbx", "rdi", "rsi"
9083                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9084 #else
9085                 , "eax", "ebx", "edi", "esi"
9086 #endif
9087               );
9088
9089         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9090         if (debugctlmsr)
9091                 update_debugctlmsr(debugctlmsr);
9092
9093 #ifndef CONFIG_X86_64
9094         /*
9095          * The sysexit path does not restore ds/es, so we must set them to
9096          * a reasonable value ourselves.
9097          *
9098          * We can't defer this to vmx_load_host_state() since that function
9099          * may be executed in interrupt context, which saves and restore segments
9100          * around it, nullifying its effect.
9101          */
9102         loadsegment(ds, __USER_DS);
9103         loadsegment(es, __USER_DS);
9104 #endif
9105
9106         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9107                                   | (1 << VCPU_EXREG_RFLAGS)
9108                                   | (1 << VCPU_EXREG_PDPTR)
9109                                   | (1 << VCPU_EXREG_SEGMENTS)
9110                                   | (1 << VCPU_EXREG_CR3));
9111         vcpu->arch.regs_dirty = 0;
9112
9113         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9114
9115         vmx->loaded_vmcs->launched = 1;
9116
9117         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9118
9119         /*
9120          * eager fpu is enabled if PKEY is supported and CR4 is switched
9121          * back on host, so it is safe to read guest PKRU from current
9122          * XSAVE.
9123          */
9124         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9125                 vmx->guest_pkru = __read_pkru();
9126                 if (vmx->guest_pkru != vmx->host_pkru) {
9127                         vmx->guest_pkru_valid = true;
9128                         __write_pkru(vmx->host_pkru);
9129                 } else
9130                         vmx->guest_pkru_valid = false;
9131         }
9132
9133         /*
9134          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9135          * we did not inject a still-pending event to L1 now because of
9136          * nested_run_pending, we need to re-enable this bit.
9137          */
9138         if (vmx->nested.nested_run_pending)
9139                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9140
9141         vmx->nested.nested_run_pending = 0;
9142
9143         vmx_complete_atomic_exit(vmx);
9144         vmx_recover_nmi_blocking(vmx);
9145         vmx_complete_interrupts(vmx);
9146 }
9147
9148 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9149 {
9150         struct vcpu_vmx *vmx = to_vmx(vcpu);
9151         int cpu;
9152
9153         if (vmx->loaded_vmcs == vmcs)
9154                 return;
9155
9156         cpu = get_cpu();
9157         vmx->loaded_vmcs = vmcs;
9158         vmx_vcpu_put(vcpu);
9159         vmx_vcpu_load(vcpu, cpu);
9160         vcpu->cpu = cpu;
9161         put_cpu();
9162 }
9163
9164 /*
9165  * Ensure that the current vmcs of the logical processor is the
9166  * vmcs01 of the vcpu before calling free_nested().
9167  */
9168 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9169 {
9170        struct vcpu_vmx *vmx = to_vmx(vcpu);
9171        int r;
9172
9173        r = vcpu_load(vcpu);
9174        BUG_ON(r);
9175        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9176        free_nested(vmx);
9177        vcpu_put(vcpu);
9178 }
9179
9180 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9181 {
9182         struct vcpu_vmx *vmx = to_vmx(vcpu);
9183
9184         if (enable_pml)
9185                 vmx_destroy_pml_buffer(vmx);
9186         free_vpid(vmx->vpid);
9187         leave_guest_mode(vcpu);
9188         vmx_free_vcpu_nested(vcpu);
9189         free_loaded_vmcs(vmx->loaded_vmcs);
9190         kfree(vmx->guest_msrs);
9191         kvm_vcpu_uninit(vcpu);
9192         kmem_cache_free(kvm_vcpu_cache, vmx);
9193 }
9194
9195 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9196 {
9197         int err;
9198         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9199         int cpu;
9200
9201         if (!vmx)
9202                 return ERR_PTR(-ENOMEM);
9203
9204         vmx->vpid = allocate_vpid();
9205
9206         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9207         if (err)
9208                 goto free_vcpu;
9209
9210         err = -ENOMEM;
9211
9212         /*
9213          * If PML is turned on, failure on enabling PML just results in failure
9214          * of creating the vcpu, therefore we can simplify PML logic (by
9215          * avoiding dealing with cases, such as enabling PML partially on vcpus
9216          * for the guest, etc.
9217          */
9218         if (enable_pml) {
9219                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9220                 if (!vmx->pml_pg)
9221                         goto uninit_vcpu;
9222         }
9223
9224         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9225         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9226                      > PAGE_SIZE);
9227
9228         if (!vmx->guest_msrs)
9229                 goto free_pml;
9230
9231         vmx->loaded_vmcs = &vmx->vmcs01;
9232         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9233         vmx->loaded_vmcs->shadow_vmcs = NULL;
9234         if (!vmx->loaded_vmcs->vmcs)
9235                 goto free_msrs;
9236         if (!vmm_exclusive)
9237                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9238         loaded_vmcs_init(vmx->loaded_vmcs);
9239         if (!vmm_exclusive)
9240                 kvm_cpu_vmxoff();
9241
9242         cpu = get_cpu();
9243         vmx_vcpu_load(&vmx->vcpu, cpu);
9244         vmx->vcpu.cpu = cpu;
9245         err = vmx_vcpu_setup(vmx);
9246         vmx_vcpu_put(&vmx->vcpu);
9247         put_cpu();
9248         if (err)
9249                 goto free_vmcs;
9250         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9251                 err = alloc_apic_access_page(kvm);
9252                 if (err)
9253                         goto free_vmcs;
9254         }
9255
9256         if (enable_ept) {
9257                 if (!kvm->arch.ept_identity_map_addr)
9258                         kvm->arch.ept_identity_map_addr =
9259                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9260                 err = init_rmode_identity_map(kvm);
9261                 if (err)
9262                         goto free_vmcs;
9263         }
9264
9265         if (nested) {
9266                 nested_vmx_setup_ctls_msrs(vmx);
9267                 vmx->nested.vpid02 = allocate_vpid();
9268         }
9269
9270         vmx->nested.posted_intr_nv = -1;
9271         vmx->nested.current_vmptr = -1ull;
9272         vmx->nested.current_vmcs12 = NULL;
9273
9274         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9275
9276         return &vmx->vcpu;
9277
9278 free_vmcs:
9279         free_vpid(vmx->nested.vpid02);
9280         free_loaded_vmcs(vmx->loaded_vmcs);
9281 free_msrs:
9282         kfree(vmx->guest_msrs);
9283 free_pml:
9284         vmx_destroy_pml_buffer(vmx);
9285 uninit_vcpu:
9286         kvm_vcpu_uninit(&vmx->vcpu);
9287 free_vcpu:
9288         free_vpid(vmx->vpid);
9289         kmem_cache_free(kvm_vcpu_cache, vmx);
9290         return ERR_PTR(err);
9291 }
9292
9293 static void __init vmx_check_processor_compat(void *rtn)
9294 {
9295         struct vmcs_config vmcs_conf;
9296
9297         *(int *)rtn = 0;
9298         if (setup_vmcs_config(&vmcs_conf) < 0)
9299                 *(int *)rtn = -EIO;
9300         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9301                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9302                                 smp_processor_id());
9303                 *(int *)rtn = -EIO;
9304         }
9305 }
9306
9307 static int get_ept_level(void)
9308 {
9309         return VMX_EPT_DEFAULT_GAW + 1;
9310 }
9311
9312 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9313 {
9314         u8 cache;
9315         u64 ipat = 0;
9316
9317         /* For VT-d and EPT combination
9318          * 1. MMIO: always map as UC
9319          * 2. EPT with VT-d:
9320          *   a. VT-d without snooping control feature: can't guarantee the
9321          *      result, try to trust guest.
9322          *   b. VT-d with snooping control feature: snooping control feature of
9323          *      VT-d engine can guarantee the cache correctness. Just set it
9324          *      to WB to keep consistent with host. So the same as item 3.
9325          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9326          *    consistent with host MTRR
9327          */
9328         if (is_mmio) {
9329                 cache = MTRR_TYPE_UNCACHABLE;
9330                 goto exit;
9331         }
9332
9333         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9334                 ipat = VMX_EPT_IPAT_BIT;
9335                 cache = MTRR_TYPE_WRBACK;
9336                 goto exit;
9337         }
9338
9339         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9340                 ipat = VMX_EPT_IPAT_BIT;
9341                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9342                         cache = MTRR_TYPE_WRBACK;
9343                 else
9344                         cache = MTRR_TYPE_UNCACHABLE;
9345                 goto exit;
9346         }
9347
9348         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9349
9350 exit:
9351         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9352 }
9353
9354 static int vmx_get_lpage_level(void)
9355 {
9356         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9357                 return PT_DIRECTORY_LEVEL;
9358         else
9359                 /* For shadow and EPT supported 1GB page */
9360                 return PT_PDPE_LEVEL;
9361 }
9362
9363 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9364 {
9365         /*
9366          * These bits in the secondary execution controls field
9367          * are dynamic, the others are mostly based on the hypervisor
9368          * architecture and the guest's CPUID.  Do not touch the
9369          * dynamic bits.
9370          */
9371         u32 mask =
9372                 SECONDARY_EXEC_SHADOW_VMCS |
9373                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9374                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9375
9376         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9377
9378         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9379                      (new_ctl & ~mask) | (cur_ctl & mask));
9380 }
9381
9382 /*
9383  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9384  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9385  */
9386 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9387 {
9388         struct vcpu_vmx *vmx = to_vmx(vcpu);
9389         struct kvm_cpuid_entry2 *entry;
9390
9391         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9392         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9393
9394 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9395         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9396                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9397 } while (0)
9398
9399         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9400         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9401         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9402         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9403         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9404         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9405         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9406         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9407         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9408         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9409         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9410         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9411         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9412         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9413         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9414
9415         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9416         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9417         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9418         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9419         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9420         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9421         cr4_fixed1_update(bit(11),            ecx, bit(2));
9422
9423 #undef cr4_fixed1_update
9424 }
9425
9426 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9427 {
9428         struct kvm_cpuid_entry2 *best;
9429         struct vcpu_vmx *vmx = to_vmx(vcpu);
9430         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9431
9432         if (vmx_rdtscp_supported()) {
9433                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9434                 if (!rdtscp_enabled)
9435                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9436
9437                 if (nested) {
9438                         if (rdtscp_enabled)
9439                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9440                                         SECONDARY_EXEC_RDTSCP;
9441                         else
9442                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9443                                         ~SECONDARY_EXEC_RDTSCP;
9444                 }
9445         }
9446
9447         /* Exposing INVPCID only when PCID is exposed */
9448         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9449         if (vmx_invpcid_supported() &&
9450             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9451             !guest_cpuid_has_pcid(vcpu))) {
9452                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9453
9454                 if (best)
9455                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9456         }
9457
9458         if (cpu_has_secondary_exec_ctrls())
9459                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9460
9461         if (nested_vmx_allowed(vcpu))
9462                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9463                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9464         else
9465                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9466                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9467
9468         if (nested_vmx_allowed(vcpu))
9469                 nested_vmx_cr_fixed1_bits_update(vcpu);
9470 }
9471
9472 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9473 {
9474         if (func == 1 && nested)
9475                 entry->ecx |= bit(X86_FEATURE_VMX);
9476 }
9477
9478 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9479                 struct x86_exception *fault)
9480 {
9481         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9482         u32 exit_reason;
9483
9484         if (fault->error_code & PFERR_RSVD_MASK)
9485                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9486         else
9487                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9488         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9489         vmcs12->guest_physical_address = fault->address;
9490 }
9491
9492 /* Callbacks for nested_ept_init_mmu_context: */
9493
9494 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9495 {
9496         /* return the page table to be shadowed - in our case, EPT12 */
9497         return get_vmcs12(vcpu)->ept_pointer;
9498 }
9499
9500 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9501 {
9502         WARN_ON(mmu_is_nested(vcpu));
9503         kvm_init_shadow_ept_mmu(vcpu,
9504                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9505                         VMX_EPT_EXECUTE_ONLY_BIT);
9506         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9507         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9508         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9509
9510         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9511 }
9512
9513 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9514 {
9515         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9516 }
9517
9518 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9519                                             u16 error_code)
9520 {
9521         bool inequality, bit;
9522
9523         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9524         inequality =
9525                 (error_code & vmcs12->page_fault_error_code_mask) !=
9526                  vmcs12->page_fault_error_code_match;
9527         return inequality ^ bit;
9528 }
9529
9530 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9531                 struct x86_exception *fault)
9532 {
9533         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9534
9535         WARN_ON(!is_guest_mode(vcpu));
9536
9537         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9538                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9539                                   vmcs_read32(VM_EXIT_INTR_INFO),
9540                                   vmcs_readl(EXIT_QUALIFICATION));
9541         else
9542                 kvm_inject_page_fault(vcpu, fault);
9543 }
9544
9545 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9546                                                struct vmcs12 *vmcs12);
9547
9548 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9549                                         struct vmcs12 *vmcs12)
9550 {
9551         struct vcpu_vmx *vmx = to_vmx(vcpu);
9552         u64 hpa;
9553
9554         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9555                 /*
9556                  * Translate L1 physical address to host physical
9557                  * address for vmcs02. Keep the page pinned, so this
9558                  * physical address remains valid. We keep a reference
9559                  * to it so we can release it later.
9560                  */
9561                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9562                         nested_release_page(vmx->nested.apic_access_page);
9563                 vmx->nested.apic_access_page =
9564                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9565                 /*
9566                  * If translation failed, no matter: This feature asks
9567                  * to exit when accessing the given address, and if it
9568                  * can never be accessed, this feature won't do
9569                  * anything anyway.
9570                  */
9571                 if (vmx->nested.apic_access_page) {
9572                         hpa = page_to_phys(vmx->nested.apic_access_page);
9573                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9574                 } else {
9575                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9576                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9577                 }
9578         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9579                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9580                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9581                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9582                 kvm_vcpu_reload_apic_access_page(vcpu);
9583         }
9584
9585         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9586                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9587                         nested_release_page(vmx->nested.virtual_apic_page);
9588                 vmx->nested.virtual_apic_page =
9589                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9590
9591                 /*
9592                  * If translation failed, VM entry will fail because
9593                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9594                  * Failing the vm entry is _not_ what the processor
9595                  * does but it's basically the only possibility we
9596                  * have.  We could still enter the guest if CR8 load
9597                  * exits are enabled, CR8 store exits are enabled, and
9598                  * virtualize APIC access is disabled; in this case
9599                  * the processor would never use the TPR shadow and we
9600                  * could simply clear the bit from the execution
9601                  * control.  But such a configuration is useless, so
9602                  * let's keep the code simple.
9603                  */
9604                 if (vmx->nested.virtual_apic_page) {
9605                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9606                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9607                 }
9608         }
9609
9610         if (nested_cpu_has_posted_intr(vmcs12)) {
9611                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9612                         kunmap(vmx->nested.pi_desc_page);
9613                         nested_release_page(vmx->nested.pi_desc_page);
9614                 }
9615                 vmx->nested.pi_desc_page =
9616                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9617                 vmx->nested.pi_desc =
9618                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9619                 if (!vmx->nested.pi_desc) {
9620                         nested_release_page_clean(vmx->nested.pi_desc_page);
9621                         return;
9622                 }
9623                 vmx->nested.pi_desc =
9624                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9625                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9626                         (PAGE_SIZE - 1)));
9627                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9628                         page_to_phys(vmx->nested.pi_desc_page) +
9629                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9630                         (PAGE_SIZE - 1)));
9631         }
9632         if (cpu_has_vmx_msr_bitmap() &&
9633             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9634             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9635                 ;
9636         else
9637                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9638                                 CPU_BASED_USE_MSR_BITMAPS);
9639 }
9640
9641 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9642 {
9643         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9644         struct vcpu_vmx *vmx = to_vmx(vcpu);
9645
9646         if (vcpu->arch.virtual_tsc_khz == 0)
9647                 return;
9648
9649         /* Make sure short timeouts reliably trigger an immediate vmexit.
9650          * hrtimer_start does not guarantee this. */
9651         if (preemption_timeout <= 1) {
9652                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9653                 return;
9654         }
9655
9656         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9657         preemption_timeout *= 1000000;
9658         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9659         hrtimer_start(&vmx->nested.preemption_timer,
9660                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9661 }
9662
9663 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9664                                                 struct vmcs12 *vmcs12)
9665 {
9666         int maxphyaddr;
9667         u64 addr;
9668
9669         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9670                 return 0;
9671
9672         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9673                 WARN_ON(1);
9674                 return -EINVAL;
9675         }
9676         maxphyaddr = cpuid_maxphyaddr(vcpu);
9677
9678         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9679            ((addr + PAGE_SIZE) >> maxphyaddr))
9680                 return -EINVAL;
9681
9682         return 0;
9683 }
9684
9685 /*
9686  * Merge L0's and L1's MSR bitmap, return false to indicate that
9687  * we do not use the hardware.
9688  */
9689 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9690                                                struct vmcs12 *vmcs12)
9691 {
9692         int msr;
9693         struct page *page;
9694         unsigned long *msr_bitmap_l1;
9695         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9696
9697         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9698         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9699                 return false;
9700
9701         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9702         if (!page)
9703                 return false;
9704         msr_bitmap_l1 = (unsigned long *)kmap(page);
9705
9706         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9707
9708         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9709                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9710                         for (msr = 0x800; msr <= 0x8ff; msr++)
9711                                 nested_vmx_disable_intercept_for_msr(
9712                                         msr_bitmap_l1, msr_bitmap_l0,
9713                                         msr, MSR_TYPE_R);
9714
9715                 nested_vmx_disable_intercept_for_msr(
9716                                 msr_bitmap_l1, msr_bitmap_l0,
9717                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9718                                 MSR_TYPE_R | MSR_TYPE_W);
9719
9720                 if (nested_cpu_has_vid(vmcs12)) {
9721                         nested_vmx_disable_intercept_for_msr(
9722                                 msr_bitmap_l1, msr_bitmap_l0,
9723                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9724                                 MSR_TYPE_W);
9725                         nested_vmx_disable_intercept_for_msr(
9726                                 msr_bitmap_l1, msr_bitmap_l0,
9727                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9728                                 MSR_TYPE_W);
9729                 }
9730         }
9731         kunmap(page);
9732         nested_release_page_clean(page);
9733
9734         return true;
9735 }
9736
9737 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9738                                            struct vmcs12 *vmcs12)
9739 {
9740         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9741             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9742             !nested_cpu_has_vid(vmcs12) &&
9743             !nested_cpu_has_posted_intr(vmcs12))
9744                 return 0;
9745
9746         /*
9747          * If virtualize x2apic mode is enabled,
9748          * virtualize apic access must be disabled.
9749          */
9750         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9751             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9752                 return -EINVAL;
9753
9754         /*
9755          * If virtual interrupt delivery is enabled,
9756          * we must exit on external interrupts.
9757          */
9758         if (nested_cpu_has_vid(vmcs12) &&
9759            !nested_exit_on_intr(vcpu))
9760                 return -EINVAL;
9761
9762         /*
9763          * bits 15:8 should be zero in posted_intr_nv,
9764          * the descriptor address has been already checked
9765          * in nested_get_vmcs12_pages.
9766          */
9767         if (nested_cpu_has_posted_intr(vmcs12) &&
9768            (!nested_cpu_has_vid(vmcs12) ||
9769             !nested_exit_intr_ack_set(vcpu) ||
9770             vmcs12->posted_intr_nv & 0xff00))
9771                 return -EINVAL;
9772
9773         /* tpr shadow is needed by all apicv features. */
9774         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9775                 return -EINVAL;
9776
9777         return 0;
9778 }
9779
9780 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9781                                        unsigned long count_field,
9782                                        unsigned long addr_field)
9783 {
9784         int maxphyaddr;
9785         u64 count, addr;
9786
9787         if (vmcs12_read_any(vcpu, count_field, &count) ||
9788             vmcs12_read_any(vcpu, addr_field, &addr)) {
9789                 WARN_ON(1);
9790                 return -EINVAL;
9791         }
9792         if (count == 0)
9793                 return 0;
9794         maxphyaddr = cpuid_maxphyaddr(vcpu);
9795         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9796             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9797                 pr_debug_ratelimited(
9798                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9799                         addr_field, maxphyaddr, count, addr);
9800                 return -EINVAL;
9801         }
9802         return 0;
9803 }
9804
9805 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9806                                                 struct vmcs12 *vmcs12)
9807 {
9808         if (vmcs12->vm_exit_msr_load_count == 0 &&
9809             vmcs12->vm_exit_msr_store_count == 0 &&
9810             vmcs12->vm_entry_msr_load_count == 0)
9811                 return 0; /* Fast path */
9812         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9813                                         VM_EXIT_MSR_LOAD_ADDR) ||
9814             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9815                                         VM_EXIT_MSR_STORE_ADDR) ||
9816             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9817                                         VM_ENTRY_MSR_LOAD_ADDR))
9818                 return -EINVAL;
9819         return 0;
9820 }
9821
9822 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9823                                        struct vmx_msr_entry *e)
9824 {
9825         /* x2APIC MSR accesses are not allowed */
9826         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9827                 return -EINVAL;
9828         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9829             e->index == MSR_IA32_UCODE_REV)
9830                 return -EINVAL;
9831         if (e->reserved != 0)
9832                 return -EINVAL;
9833         return 0;
9834 }
9835
9836 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9837                                      struct vmx_msr_entry *e)
9838 {
9839         if (e->index == MSR_FS_BASE ||
9840             e->index == MSR_GS_BASE ||
9841             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9842             nested_vmx_msr_check_common(vcpu, e))
9843                 return -EINVAL;
9844         return 0;
9845 }
9846
9847 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9848                                       struct vmx_msr_entry *e)
9849 {
9850         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9851             nested_vmx_msr_check_common(vcpu, e))
9852                 return -EINVAL;
9853         return 0;
9854 }
9855
9856 /*
9857  * Load guest's/host's msr at nested entry/exit.
9858  * return 0 for success, entry index for failure.
9859  */
9860 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9861 {
9862         u32 i;
9863         struct vmx_msr_entry e;
9864         struct msr_data msr;
9865
9866         msr.host_initiated = false;
9867         for (i = 0; i < count; i++) {
9868                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9869                                         &e, sizeof(e))) {
9870                         pr_debug_ratelimited(
9871                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9872                                 __func__, i, gpa + i * sizeof(e));
9873                         goto fail;
9874                 }
9875                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9876                         pr_debug_ratelimited(
9877                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9878                                 __func__, i, e.index, e.reserved);
9879                         goto fail;
9880                 }
9881                 msr.index = e.index;
9882                 msr.data = e.value;
9883                 if (kvm_set_msr(vcpu, &msr)) {
9884                         pr_debug_ratelimited(
9885                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9886                                 __func__, i, e.index, e.value);
9887                         goto fail;
9888                 }
9889         }
9890         return 0;
9891 fail:
9892         return i + 1;
9893 }
9894
9895 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9896 {
9897         u32 i;
9898         struct vmx_msr_entry e;
9899
9900         for (i = 0; i < count; i++) {
9901                 struct msr_data msr_info;
9902                 if (kvm_vcpu_read_guest(vcpu,
9903                                         gpa + i * sizeof(e),
9904                                         &e, 2 * sizeof(u32))) {
9905                         pr_debug_ratelimited(
9906                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9907                                 __func__, i, gpa + i * sizeof(e));
9908                         return -EINVAL;
9909                 }
9910                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9911                         pr_debug_ratelimited(
9912                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9913                                 __func__, i, e.index, e.reserved);
9914                         return -EINVAL;
9915                 }
9916                 msr_info.host_initiated = false;
9917                 msr_info.index = e.index;
9918                 if (kvm_get_msr(vcpu, &msr_info)) {
9919                         pr_debug_ratelimited(
9920                                 "%s cannot read MSR (%u, 0x%x)\n",
9921                                 __func__, i, e.index);
9922                         return -EINVAL;
9923                 }
9924                 if (kvm_vcpu_write_guest(vcpu,
9925                                          gpa + i * sizeof(e) +
9926                                              offsetof(struct vmx_msr_entry, value),
9927                                          &msr_info.data, sizeof(msr_info.data))) {
9928                         pr_debug_ratelimited(
9929                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9930                                 __func__, i, e.index, msr_info.data);
9931                         return -EINVAL;
9932                 }
9933         }
9934         return 0;
9935 }
9936
9937 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9938 {
9939         unsigned long invalid_mask;
9940
9941         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9942         return (val & invalid_mask) == 0;
9943 }
9944
9945 /*
9946  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9947  * emulating VM entry into a guest with EPT enabled.
9948  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9949  * is assigned to entry_failure_code on failure.
9950  */
9951 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9952                                u32 *entry_failure_code)
9953 {
9954         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9955                 if (!nested_cr3_valid(vcpu, cr3)) {
9956                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9957                         return 1;
9958                 }
9959
9960                 /*
9961                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9962                  * must not be dereferenced.
9963                  */
9964                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9965                     !nested_ept) {
9966                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9967                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9968                                 return 1;
9969                         }
9970                 }
9971
9972                 vcpu->arch.cr3 = cr3;
9973                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9974         }
9975
9976         kvm_mmu_reset_context(vcpu);
9977         return 0;
9978 }
9979
9980 /*
9981  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9982  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9983  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9984  * guest in a way that will both be appropriate to L1's requests, and our
9985  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9986  * function also has additional necessary side-effects, like setting various
9987  * vcpu->arch fields.
9988  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9989  * is assigned to entry_failure_code on failure.
9990  */
9991 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9992                           bool from_vmentry, u32 *entry_failure_code)
9993 {
9994         struct vcpu_vmx *vmx = to_vmx(vcpu);
9995         u32 exec_control;
9996
9997         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9998         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9999         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10000         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10001         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10002         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10003         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10004         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10005         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10006         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10007         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10008         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10009         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10010         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10011         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10012         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10013         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10014         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10015         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10016         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10017         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10018         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10019         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10020         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10021         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10022         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10023         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10024         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10025         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10026         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10027         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10028         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10029         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10030         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10031         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10032         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10033
10034         if (from_vmentry &&
10035             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10036                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10037                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10038         } else {
10039                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10040                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10041         }
10042         if (from_vmentry) {
10043                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10044                              vmcs12->vm_entry_intr_info_field);
10045                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10046                              vmcs12->vm_entry_exception_error_code);
10047                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10048                              vmcs12->vm_entry_instruction_len);
10049                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10050                              vmcs12->guest_interruptibility_info);
10051         } else {
10052                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10053         }
10054         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10055         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10056         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10057                 vmcs12->guest_pending_dbg_exceptions);
10058         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10059         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10060
10061         if (nested_cpu_has_xsaves(vmcs12))
10062                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10063         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10064
10065         exec_control = vmcs12->pin_based_vm_exec_control;
10066
10067         /* Preemption timer setting is only taken from vmcs01.  */
10068         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10069         exec_control |= vmcs_config.pin_based_exec_ctrl;
10070         if (vmx->hv_deadline_tsc == -1)
10071                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10072
10073         /* Posted interrupts setting is only taken from vmcs12.  */
10074         if (nested_cpu_has_posted_intr(vmcs12)) {
10075                 /*
10076                  * Note that we use L0's vector here and in
10077                  * vmx_deliver_nested_posted_interrupt.
10078                  */
10079                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10080                 vmx->nested.pi_pending = false;
10081                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10082         } else {
10083                 exec_control &= ~PIN_BASED_POSTED_INTR;
10084         }
10085
10086         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10087
10088         vmx->nested.preemption_timer_expired = false;
10089         if (nested_cpu_has_preemption_timer(vmcs12))
10090                 vmx_start_preemption_timer(vcpu);
10091
10092         /*
10093          * Whether page-faults are trapped is determined by a combination of
10094          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10095          * If enable_ept, L0 doesn't care about page faults and we should
10096          * set all of these to L1's desires. However, if !enable_ept, L0 does
10097          * care about (at least some) page faults, and because it is not easy
10098          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10099          * to exit on each and every L2 page fault. This is done by setting
10100          * MASK=MATCH=0 and (see below) EB.PF=1.
10101          * Note that below we don't need special code to set EB.PF beyond the
10102          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10103          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10104          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10105          *
10106          * A problem with this approach (when !enable_ept) is that L1 may be
10107          * injected with more page faults than it asked for. This could have
10108          * caused problems, but in practice existing hypervisors don't care.
10109          * To fix this, we will need to emulate the PFEC checking (on the L1
10110          * page tables), using walk_addr(), when injecting PFs to L1.
10111          */
10112         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10113                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10114         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10115                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10116
10117         if (cpu_has_secondary_exec_ctrls()) {
10118                 exec_control = vmx_secondary_exec_control(vmx);
10119
10120                 /* Take the following fields only from vmcs12 */
10121                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10122                                   SECONDARY_EXEC_RDTSCP |
10123                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10124                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10125                 if (nested_cpu_has(vmcs12,
10126                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10127                         exec_control |= vmcs12->secondary_vm_exec_control;
10128
10129                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10130                         vmcs_write64(EOI_EXIT_BITMAP0,
10131                                 vmcs12->eoi_exit_bitmap0);
10132                         vmcs_write64(EOI_EXIT_BITMAP1,
10133                                 vmcs12->eoi_exit_bitmap1);
10134                         vmcs_write64(EOI_EXIT_BITMAP2,
10135                                 vmcs12->eoi_exit_bitmap2);
10136                         vmcs_write64(EOI_EXIT_BITMAP3,
10137                                 vmcs12->eoi_exit_bitmap3);
10138                         vmcs_write16(GUEST_INTR_STATUS,
10139                                 vmcs12->guest_intr_status);
10140                 }
10141
10142                 /*
10143                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10144                  * nested_get_vmcs12_pages will either fix it up or
10145                  * remove the VM execution control.
10146                  */
10147                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10148                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10149
10150                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10151         }
10152
10153
10154         /*
10155          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10156          * Some constant fields are set here by vmx_set_constant_host_state().
10157          * Other fields are different per CPU, and will be set later when
10158          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10159          */
10160         vmx_set_constant_host_state(vmx);
10161
10162         /*
10163          * Set the MSR load/store lists to match L0's settings.
10164          */
10165         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10166         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10167         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10168         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10169         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10170
10171         /*
10172          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10173          * entry, but only if the current (host) sp changed from the value
10174          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10175          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10176          * here we just force the write to happen on entry.
10177          */
10178         vmx->host_rsp = 0;
10179
10180         exec_control = vmx_exec_control(vmx); /* L0's desires */
10181         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10182         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10183         exec_control &= ~CPU_BASED_TPR_SHADOW;
10184         exec_control |= vmcs12->cpu_based_vm_exec_control;
10185
10186         /*
10187          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10188          * nested_get_vmcs12_pages can't fix it up, the illegal value
10189          * will result in a VM entry failure.
10190          */
10191         if (exec_control & CPU_BASED_TPR_SHADOW) {
10192                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10193                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10194         }
10195
10196         /*
10197          * Merging of IO bitmap not currently supported.
10198          * Rather, exit every time.
10199          */
10200         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10201         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10202
10203         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10204
10205         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10206          * bitwise-or of what L1 wants to trap for L2, and what we want to
10207          * trap. Note that CR0.TS also needs updating - we do this later.
10208          */
10209         update_exception_bitmap(vcpu);
10210         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10211         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10212
10213         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10214          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10215          * bits are further modified by vmx_set_efer() below.
10216          */
10217         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10218
10219         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10220          * emulated by vmx_set_efer(), below.
10221          */
10222         vm_entry_controls_init(vmx,
10223                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10224                         ~VM_ENTRY_IA32E_MODE) |
10225                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10226
10227         if (from_vmentry &&
10228             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10229                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10230                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10231         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10232                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10233         }
10234
10235         set_cr4_guest_host_mask(vmx);
10236
10237         if (from_vmentry &&
10238             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10239                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10240
10241         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10242                 vmcs_write64(TSC_OFFSET,
10243                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10244         else
10245                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10246         if (kvm_has_tsc_control)
10247                 decache_tsc_multiplier(vmx);
10248
10249         if (enable_vpid) {
10250                 /*
10251                  * There is no direct mapping between vpid02 and vpid12, the
10252                  * vpid02 is per-vCPU for L0 and reused while the value of
10253                  * vpid12 is changed w/ one invvpid during nested vmentry.
10254                  * The vpid12 is allocated by L1 for L2, so it will not
10255                  * influence global bitmap(for vpid01 and vpid02 allocation)
10256                  * even if spawn a lot of nested vCPUs.
10257                  */
10258                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10259                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10260                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10261                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10262                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10263                         }
10264                 } else {
10265                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10266                         vmx_flush_tlb(vcpu);
10267                 }
10268
10269         }
10270
10271         if (nested_cpu_has_ept(vmcs12)) {
10272                 kvm_mmu_unload(vcpu);
10273                 nested_ept_init_mmu_context(vcpu);
10274         } else if (nested_cpu_has2(vmcs12,
10275                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10276                 vmx_flush_tlb_ept_only(vcpu);
10277         }
10278
10279         /*
10280          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10281          * bits which we consider mandatory enabled.
10282          * The CR0_READ_SHADOW is what L2 should have expected to read given
10283          * the specifications by L1; It's not enough to take
10284          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10285          * have more bits than L1 expected.
10286          */
10287         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10288         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10289
10290         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10291         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10292
10293         if (from_vmentry &&
10294             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10295                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10296         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10297                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10298         else
10299                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10300         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10301         vmx_set_efer(vcpu, vcpu->arch.efer);
10302
10303         /* Shadow page tables on either EPT or shadow page tables. */
10304         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10305                                 entry_failure_code))
10306                 return 1;
10307
10308         if (!enable_ept)
10309                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10310
10311         /*
10312          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10313          */
10314         if (enable_ept) {
10315                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10316                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10317                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10318                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10319         }
10320
10321         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10322         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10323         return 0;
10324 }
10325
10326 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10327 {
10328         struct vcpu_vmx *vmx = to_vmx(vcpu);
10329
10330         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10331             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10332                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10333
10334         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10335                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10336
10337         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10338                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10339
10340         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10341                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10342
10343         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10344                                 vmx->nested.nested_vmx_procbased_ctls_low,
10345                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10346             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10347                                 vmx->nested.nested_vmx_secondary_ctls_low,
10348                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10349             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10350                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10351                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10352             !vmx_control_verify(vmcs12->vm_exit_controls,
10353                                 vmx->nested.nested_vmx_exit_ctls_low,
10354                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10355             !vmx_control_verify(vmcs12->vm_entry_controls,
10356                                 vmx->nested.nested_vmx_entry_ctls_low,
10357                                 vmx->nested.nested_vmx_entry_ctls_high))
10358                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10359
10360         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10361             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10362             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10363                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10364
10365         return 0;
10366 }
10367
10368 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10369                                   u32 *exit_qual)
10370 {
10371         bool ia32e;
10372
10373         *exit_qual = ENTRY_FAIL_DEFAULT;
10374
10375         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10376             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10377                 return 1;
10378
10379         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10380             vmcs12->vmcs_link_pointer != -1ull) {
10381                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10382                 return 1;
10383         }
10384
10385         /*
10386          * If the load IA32_EFER VM-entry control is 1, the following checks
10387          * are performed on the field for the IA32_EFER MSR:
10388          * - Bits reserved in the IA32_EFER MSR must be 0.
10389          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10390          *   the IA-32e mode guest VM-exit control. It must also be identical
10391          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10392          *   CR0.PG) is 1.
10393          */
10394         if (to_vmx(vcpu)->nested.nested_run_pending &&
10395             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10396                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10397                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10398                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10399                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10400                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10401                         return 1;
10402         }
10403
10404         /*
10405          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10406          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10407          * the values of the LMA and LME bits in the field must each be that of
10408          * the host address-space size VM-exit control.
10409          */
10410         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10411                 ia32e = (vmcs12->vm_exit_controls &
10412                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10413                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10414                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10415                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10416                         return 1;
10417         }
10418
10419         return 0;
10420 }
10421
10422 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10423 {
10424         struct vcpu_vmx *vmx = to_vmx(vcpu);
10425         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10426         struct loaded_vmcs *vmcs02;
10427         u32 msr_entry_idx;
10428         u32 exit_qual;
10429
10430         vmcs02 = nested_get_current_vmcs02(vmx);
10431         if (!vmcs02)
10432                 return -ENOMEM;
10433
10434         enter_guest_mode(vcpu);
10435
10436         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10437                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10438
10439         vmx_switch_vmcs(vcpu, vmcs02);
10440         vmx_segment_cache_clear(vmx);
10441
10442         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10443                 leave_guest_mode(vcpu);
10444                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10445                 nested_vmx_entry_failure(vcpu, vmcs12,
10446                                          EXIT_REASON_INVALID_STATE, exit_qual);
10447                 return 1;
10448         }
10449
10450         nested_get_vmcs12_pages(vcpu, vmcs12);
10451
10452         msr_entry_idx = nested_vmx_load_msr(vcpu,
10453                                             vmcs12->vm_entry_msr_load_addr,
10454                                             vmcs12->vm_entry_msr_load_count);
10455         if (msr_entry_idx) {
10456                 leave_guest_mode(vcpu);
10457                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10458                 nested_vmx_entry_failure(vcpu, vmcs12,
10459                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10460                 return 1;
10461         }
10462
10463         vmcs12->launch_state = 1;
10464
10465         /*
10466          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10467          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10468          * returned as far as L1 is concerned. It will only return (and set
10469          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10470          */
10471         return 0;
10472 }
10473
10474 /*
10475  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10476  * for running an L2 nested guest.
10477  */
10478 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10479 {
10480         struct vmcs12 *vmcs12;
10481         struct vcpu_vmx *vmx = to_vmx(vcpu);
10482         u32 exit_qual;
10483         int ret;
10484
10485         if (!nested_vmx_check_permission(vcpu))
10486                 return 1;
10487
10488         if (!nested_vmx_check_vmcs12(vcpu))
10489                 goto out;
10490
10491         vmcs12 = get_vmcs12(vcpu);
10492
10493         if (enable_shadow_vmcs)
10494                 copy_shadow_to_vmcs12(vmx);
10495
10496         /*
10497          * The nested entry process starts with enforcing various prerequisites
10498          * on vmcs12 as required by the Intel SDM, and act appropriately when
10499          * they fail: As the SDM explains, some conditions should cause the
10500          * instruction to fail, while others will cause the instruction to seem
10501          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10502          * To speed up the normal (success) code path, we should avoid checking
10503          * for misconfigurations which will anyway be caught by the processor
10504          * when using the merged vmcs02.
10505          */
10506         if (vmcs12->launch_state == launch) {
10507                 nested_vmx_failValid(vcpu,
10508                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10509                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10510                 goto out;
10511         }
10512
10513         ret = check_vmentry_prereqs(vcpu, vmcs12);
10514         if (ret) {
10515                 nested_vmx_failValid(vcpu, ret);
10516                 goto out;
10517         }
10518
10519         /*
10520          * After this point, the trap flag no longer triggers a singlestep trap
10521          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10522          * This is not 100% correct; for performance reasons, we delegate most
10523          * of the checks on host state to the processor.  If those fail,
10524          * the singlestep trap is missed.
10525          */
10526         skip_emulated_instruction(vcpu);
10527
10528         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10529         if (ret) {
10530                 nested_vmx_entry_failure(vcpu, vmcs12,
10531                                          EXIT_REASON_INVALID_STATE, exit_qual);
10532                 return 1;
10533         }
10534
10535         /*
10536          * We're finally done with prerequisite checking, and can start with
10537          * the nested entry.
10538          */
10539
10540         ret = enter_vmx_non_root_mode(vcpu, true);
10541         if (ret)
10542                 return ret;
10543
10544         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10545                 return kvm_vcpu_halt(vcpu);
10546
10547         vmx->nested.nested_run_pending = 1;
10548
10549         return 1;
10550
10551 out:
10552         return kvm_skip_emulated_instruction(vcpu);
10553 }
10554
10555 /*
10556  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10557  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10558  * This function returns the new value we should put in vmcs12.guest_cr0.
10559  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10560  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10561  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10562  *     didn't trap the bit, because if L1 did, so would L0).
10563  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10564  *     been modified by L2, and L1 knows it. So just leave the old value of
10565  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10566  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10567  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10568  *     changed these bits, and therefore they need to be updated, but L0
10569  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10570  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10571  */
10572 static inline unsigned long
10573 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10574 {
10575         return
10576         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10577         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10578         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10579                         vcpu->arch.cr0_guest_owned_bits));
10580 }
10581
10582 static inline unsigned long
10583 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10584 {
10585         return
10586         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10587         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10588         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10589                         vcpu->arch.cr4_guest_owned_bits));
10590 }
10591
10592 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10593                                        struct vmcs12 *vmcs12)
10594 {
10595         u32 idt_vectoring;
10596         unsigned int nr;
10597
10598         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10599                 nr = vcpu->arch.exception.nr;
10600                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10601
10602                 if (kvm_exception_is_soft(nr)) {
10603                         vmcs12->vm_exit_instruction_len =
10604                                 vcpu->arch.event_exit_inst_len;
10605                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10606                 } else
10607                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10608
10609                 if (vcpu->arch.exception.has_error_code) {
10610                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10611                         vmcs12->idt_vectoring_error_code =
10612                                 vcpu->arch.exception.error_code;
10613                 }
10614
10615                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10616         } else if (vcpu->arch.nmi_injected) {
10617                 vmcs12->idt_vectoring_info_field =
10618                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10619         } else if (vcpu->arch.interrupt.pending) {
10620                 nr = vcpu->arch.interrupt.nr;
10621                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10622
10623                 if (vcpu->arch.interrupt.soft) {
10624                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10625                         vmcs12->vm_entry_instruction_len =
10626                                 vcpu->arch.event_exit_inst_len;
10627                 } else
10628                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10629
10630                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10631         }
10632 }
10633
10634 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10635 {
10636         struct vcpu_vmx *vmx = to_vmx(vcpu);
10637
10638         if (vcpu->arch.exception.pending ||
10639                 vcpu->arch.nmi_injected ||
10640                 vcpu->arch.interrupt.pending)
10641                 return -EBUSY;
10642
10643         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10644             vmx->nested.preemption_timer_expired) {
10645                 if (vmx->nested.nested_run_pending)
10646                         return -EBUSY;
10647                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10648                 return 0;
10649         }
10650
10651         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10652                 if (vmx->nested.nested_run_pending)
10653                         return -EBUSY;
10654                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10655                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10656                                   INTR_INFO_VALID_MASK, 0);
10657                 /*
10658                  * The NMI-triggered VM exit counts as injection:
10659                  * clear this one and block further NMIs.
10660                  */
10661                 vcpu->arch.nmi_pending = 0;
10662                 vmx_set_nmi_mask(vcpu, true);
10663                 return 0;
10664         }
10665
10666         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10667             nested_exit_on_intr(vcpu)) {
10668                 if (vmx->nested.nested_run_pending)
10669                         return -EBUSY;
10670                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10671                 return 0;
10672         }
10673
10674         vmx_complete_nested_posted_interrupt(vcpu);
10675         return 0;
10676 }
10677
10678 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10679 {
10680         ktime_t remaining =
10681                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10682         u64 value;
10683
10684         if (ktime_to_ns(remaining) <= 0)
10685                 return 0;
10686
10687         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10688         do_div(value, 1000000);
10689         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10690 }
10691
10692 /*
10693  * Update the guest state fields of vmcs12 to reflect changes that
10694  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10695  * VM-entry controls is also updated, since this is really a guest
10696  * state bit.)
10697  */
10698 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10699 {
10700         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10701         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10702
10703         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10704         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10705         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10706
10707         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10708         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10709         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10710         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10711         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10712         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10713         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10714         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10715         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10716         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10717         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10718         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10719         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10720         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10721         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10722         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10723         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10724         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10725         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10726         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10727         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10728         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10729         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10730         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10731         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10732         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10733         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10734         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10735         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10736         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10737         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10738         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10739         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10740         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10741         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10742         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10743
10744         vmcs12->guest_interruptibility_info =
10745                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10746         vmcs12->guest_pending_dbg_exceptions =
10747                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10748         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10749                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10750         else
10751                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10752
10753         if (nested_cpu_has_preemption_timer(vmcs12)) {
10754                 if (vmcs12->vm_exit_controls &
10755                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10756                         vmcs12->vmx_preemption_timer_value =
10757                                 vmx_get_preemption_timer_value(vcpu);
10758                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10759         }
10760
10761         /*
10762          * In some cases (usually, nested EPT), L2 is allowed to change its
10763          * own CR3 without exiting. If it has changed it, we must keep it.
10764          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10765          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10766          *
10767          * Additionally, restore L2's PDPTR to vmcs12.
10768          */
10769         if (enable_ept) {
10770                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10771                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10772                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10773                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10774                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10775         }
10776
10777         if (nested_cpu_has_ept(vmcs12))
10778                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10779
10780         if (nested_cpu_has_vid(vmcs12))
10781                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10782
10783         vmcs12->vm_entry_controls =
10784                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10785                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10786
10787         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10788                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10789                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10790         }
10791
10792         /* TODO: These cannot have changed unless we have MSR bitmaps and
10793          * the relevant bit asks not to trap the change */
10794         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10795                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10796         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10797                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10798         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10799         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10800         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10801         if (kvm_mpx_supported())
10802                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10803         if (nested_cpu_has_xsaves(vmcs12))
10804                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10805 }
10806
10807 /*
10808  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10809  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10810  * and this function updates it to reflect the changes to the guest state while
10811  * L2 was running (and perhaps made some exits which were handled directly by L0
10812  * without going back to L1), and to reflect the exit reason.
10813  * Note that we do not have to copy here all VMCS fields, just those that
10814  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10815  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10816  * which already writes to vmcs12 directly.
10817  */
10818 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10819                            u32 exit_reason, u32 exit_intr_info,
10820                            unsigned long exit_qualification)
10821 {
10822         /* update guest state fields: */
10823         sync_vmcs12(vcpu, vmcs12);
10824
10825         /* update exit information fields: */
10826
10827         vmcs12->vm_exit_reason = exit_reason;
10828         vmcs12->exit_qualification = exit_qualification;
10829
10830         vmcs12->vm_exit_intr_info = exit_intr_info;
10831         if ((vmcs12->vm_exit_intr_info &
10832              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10833             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10834                 vmcs12->vm_exit_intr_error_code =
10835                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10836         vmcs12->idt_vectoring_info_field = 0;
10837         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10838         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10839
10840         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10841                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10842                  * instead of reading the real value. */
10843                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10844
10845                 /*
10846                  * Transfer the event that L0 or L1 may wanted to inject into
10847                  * L2 to IDT_VECTORING_INFO_FIELD.
10848                  */
10849                 vmcs12_save_pending_event(vcpu, vmcs12);
10850         }
10851
10852         /*
10853          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10854          * preserved above and would only end up incorrectly in L1.
10855          */
10856         vcpu->arch.nmi_injected = false;
10857         kvm_clear_exception_queue(vcpu);
10858         kvm_clear_interrupt_queue(vcpu);
10859 }
10860
10861 /*
10862  * A part of what we need to when the nested L2 guest exits and we want to
10863  * run its L1 parent, is to reset L1's guest state to the host state specified
10864  * in vmcs12.
10865  * This function is to be called not only on normal nested exit, but also on
10866  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10867  * Failures During or After Loading Guest State").
10868  * This function should be called when the active VMCS is L1's (vmcs01).
10869  */
10870 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10871                                    struct vmcs12 *vmcs12)
10872 {
10873         struct kvm_segment seg;
10874         u32 entry_failure_code;
10875
10876         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10877                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10878         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10879                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10880         else
10881                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10882         vmx_set_efer(vcpu, vcpu->arch.efer);
10883
10884         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10885         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10886         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10887         /*
10888          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10889          * actually changed, because vmx_set_cr0 refers to efer set above.
10890          *
10891          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10892          * (KVM doesn't change it);
10893          */
10894         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10895         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10896
10897         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10898         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10899         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10900
10901         nested_ept_uninit_mmu_context(vcpu);
10902
10903         /*
10904          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10905          * couldn't have changed.
10906          */
10907         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10908                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10909
10910         if (!enable_ept)
10911                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10912
10913         if (enable_vpid) {
10914                 /*
10915                  * Trivially support vpid by letting L2s share their parent
10916                  * L1's vpid. TODO: move to a more elaborate solution, giving
10917                  * each L2 its own vpid and exposing the vpid feature to L1.
10918                  */
10919                 vmx_flush_tlb(vcpu);
10920         }
10921
10922
10923         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10924         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10925         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10926         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10927         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10928
10929         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10930         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10931                 vmcs_write64(GUEST_BNDCFGS, 0);
10932
10933         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10934                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10935                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10936         }
10937         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10938                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10939                         vmcs12->host_ia32_perf_global_ctrl);
10940
10941         /* Set L1 segment info according to Intel SDM
10942             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10943         seg = (struct kvm_segment) {
10944                 .base = 0,
10945                 .limit = 0xFFFFFFFF,
10946                 .selector = vmcs12->host_cs_selector,
10947                 .type = 11,
10948                 .present = 1,
10949                 .s = 1,
10950                 .g = 1
10951         };
10952         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10953                 seg.l = 1;
10954         else
10955                 seg.db = 1;
10956         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10957         seg = (struct kvm_segment) {
10958                 .base = 0,
10959                 .limit = 0xFFFFFFFF,
10960                 .type = 3,
10961                 .present = 1,
10962                 .s = 1,
10963                 .db = 1,
10964                 .g = 1
10965         };
10966         seg.selector = vmcs12->host_ds_selector;
10967         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10968         seg.selector = vmcs12->host_es_selector;
10969         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10970         seg.selector = vmcs12->host_ss_selector;
10971         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10972         seg.selector = vmcs12->host_fs_selector;
10973         seg.base = vmcs12->host_fs_base;
10974         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10975         seg.selector = vmcs12->host_gs_selector;
10976         seg.base = vmcs12->host_gs_base;
10977         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10978         seg = (struct kvm_segment) {
10979                 .base = vmcs12->host_tr_base,
10980                 .limit = 0x67,
10981                 .selector = vmcs12->host_tr_selector,
10982                 .type = 11,
10983                 .present = 1
10984         };
10985         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10986
10987         kvm_set_dr(vcpu, 7, 0x400);
10988         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10989
10990         if (cpu_has_vmx_msr_bitmap())
10991                 vmx_set_msr_bitmap(vcpu);
10992
10993         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10994                                 vmcs12->vm_exit_msr_load_count))
10995                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10996 }
10997
10998 /*
10999  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11000  * and modify vmcs12 to make it see what it would expect to see there if
11001  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11002  */
11003 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11004                               u32 exit_intr_info,
11005                               unsigned long exit_qualification)
11006 {
11007         struct vcpu_vmx *vmx = to_vmx(vcpu);
11008         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11009         u32 vm_inst_error = 0;
11010
11011         /* trying to cancel vmlaunch/vmresume is a bug */
11012         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11013
11014         leave_guest_mode(vcpu);
11015         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11016                        exit_qualification);
11017
11018         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11019                                  vmcs12->vm_exit_msr_store_count))
11020                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11021
11022         if (unlikely(vmx->fail))
11023                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11024
11025         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11026
11027         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11028             && nested_exit_intr_ack_set(vcpu)) {
11029                 int irq = kvm_cpu_get_interrupt(vcpu);
11030                 WARN_ON(irq < 0);
11031                 vmcs12->vm_exit_intr_info = irq |
11032                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11033         }
11034
11035         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11036                                        vmcs12->exit_qualification,
11037                                        vmcs12->idt_vectoring_info_field,
11038                                        vmcs12->vm_exit_intr_info,
11039                                        vmcs12->vm_exit_intr_error_code,
11040                                        KVM_ISA_VMX);
11041
11042         vm_entry_controls_reset_shadow(vmx);
11043         vm_exit_controls_reset_shadow(vmx);
11044         vmx_segment_cache_clear(vmx);
11045
11046         /* if no vmcs02 cache requested, remove the one we used */
11047         if (VMCS02_POOL_SIZE == 0)
11048                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11049
11050         load_vmcs12_host_state(vcpu, vmcs12);
11051
11052         /* Update any VMCS fields that might have changed while L2 ran */
11053         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11054         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11055         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11056         if (vmx->hv_deadline_tsc == -1)
11057                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11058                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11059         else
11060                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11061                               PIN_BASED_VMX_PREEMPTION_TIMER);
11062         if (kvm_has_tsc_control)
11063                 decache_tsc_multiplier(vmx);
11064
11065         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11066                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11067                 vmx_set_virtual_x2apic_mode(vcpu,
11068                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11069         } else if (!nested_cpu_has_ept(vmcs12) &&
11070                    nested_cpu_has2(vmcs12,
11071                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11072                 vmx_flush_tlb_ept_only(vcpu);
11073         }
11074
11075         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11076         vmx->host_rsp = 0;
11077
11078         /* Unpin physical memory we referred to in vmcs02 */
11079         if (vmx->nested.apic_access_page) {
11080                 nested_release_page(vmx->nested.apic_access_page);
11081                 vmx->nested.apic_access_page = NULL;
11082         }
11083         if (vmx->nested.virtual_apic_page) {
11084                 nested_release_page(vmx->nested.virtual_apic_page);
11085                 vmx->nested.virtual_apic_page = NULL;
11086         }
11087         if (vmx->nested.pi_desc_page) {
11088                 kunmap(vmx->nested.pi_desc_page);
11089                 nested_release_page(vmx->nested.pi_desc_page);
11090                 vmx->nested.pi_desc_page = NULL;
11091                 vmx->nested.pi_desc = NULL;
11092         }
11093
11094         /*
11095          * We are now running in L2, mmu_notifier will force to reload the
11096          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11097          */
11098         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11099
11100         /*
11101          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11102          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11103          * success or failure flag accordingly.
11104          */
11105         if (unlikely(vmx->fail)) {
11106                 vmx->fail = 0;
11107                 nested_vmx_failValid(vcpu, vm_inst_error);
11108         } else
11109                 nested_vmx_succeed(vcpu);
11110         if (enable_shadow_vmcs)
11111                 vmx->nested.sync_shadow_vmcs = true;
11112
11113         /* in case we halted in L2 */
11114         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11115 }
11116
11117 /*
11118  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11119  */
11120 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11121 {
11122         if (is_guest_mode(vcpu)) {
11123                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11124                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11125         }
11126         free_nested(to_vmx(vcpu));
11127 }
11128
11129 /*
11130  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11131  * 23.7 "VM-entry failures during or after loading guest state" (this also
11132  * lists the acceptable exit-reason and exit-qualification parameters).
11133  * It should only be called before L2 actually succeeded to run, and when
11134  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11135  */
11136 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11137                         struct vmcs12 *vmcs12,
11138                         u32 reason, unsigned long qualification)
11139 {
11140         load_vmcs12_host_state(vcpu, vmcs12);
11141         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11142         vmcs12->exit_qualification = qualification;
11143         nested_vmx_succeed(vcpu);
11144         if (enable_shadow_vmcs)
11145                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11146 }
11147
11148 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11149                                struct x86_instruction_info *info,
11150                                enum x86_intercept_stage stage)
11151 {
11152         return X86EMUL_CONTINUE;
11153 }
11154
11155 #ifdef CONFIG_X86_64
11156 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11157 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11158                                   u64 divisor, u64 *result)
11159 {
11160         u64 low = a << shift, high = a >> (64 - shift);
11161
11162         /* To avoid the overflow on divq */
11163         if (high >= divisor)
11164                 return 1;
11165
11166         /* Low hold the result, high hold rem which is discarded */
11167         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11168             "rm" (divisor), "0" (low), "1" (high));
11169         *result = low;
11170
11171         return 0;
11172 }
11173
11174 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11175 {
11176         struct vcpu_vmx *vmx = to_vmx(vcpu);
11177         u64 tscl = rdtsc();
11178         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11179         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11180
11181         /* Convert to host delta tsc if tsc scaling is enabled */
11182         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11183                         u64_shl_div_u64(delta_tsc,
11184                                 kvm_tsc_scaling_ratio_frac_bits,
11185                                 vcpu->arch.tsc_scaling_ratio,
11186                                 &delta_tsc))
11187                 return -ERANGE;
11188
11189         /*
11190          * If the delta tsc can't fit in the 32 bit after the multi shift,
11191          * we can't use the preemption timer.
11192          * It's possible that it fits on later vmentries, but checking
11193          * on every vmentry is costly so we just use an hrtimer.
11194          */
11195         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11196                 return -ERANGE;
11197
11198         vmx->hv_deadline_tsc = tscl + delta_tsc;
11199         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11200                         PIN_BASED_VMX_PREEMPTION_TIMER);
11201         return 0;
11202 }
11203
11204 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11205 {
11206         struct vcpu_vmx *vmx = to_vmx(vcpu);
11207         vmx->hv_deadline_tsc = -1;
11208         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11209                         PIN_BASED_VMX_PREEMPTION_TIMER);
11210 }
11211 #endif
11212
11213 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11214 {
11215         if (ple_gap)
11216                 shrink_ple_window(vcpu);
11217 }
11218
11219 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11220                                      struct kvm_memory_slot *slot)
11221 {
11222         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11223         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11224 }
11225
11226 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11227                                        struct kvm_memory_slot *slot)
11228 {
11229         kvm_mmu_slot_set_dirty(kvm, slot);
11230 }
11231
11232 static void vmx_flush_log_dirty(struct kvm *kvm)
11233 {
11234         kvm_flush_pml_buffers(kvm);
11235 }
11236
11237 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11238                                            struct kvm_memory_slot *memslot,
11239                                            gfn_t offset, unsigned long mask)
11240 {
11241         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11242 }
11243
11244 /*
11245  * This routine does the following things for vCPU which is going
11246  * to be blocked if VT-d PI is enabled.
11247  * - Store the vCPU to the wakeup list, so when interrupts happen
11248  *   we can find the right vCPU to wake up.
11249  * - Change the Posted-interrupt descriptor as below:
11250  *      'NDST' <-- vcpu->pre_pcpu
11251  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11252  * - If 'ON' is set during this process, which means at least one
11253  *   interrupt is posted for this vCPU, we cannot block it, in
11254  *   this case, return 1, otherwise, return 0.
11255  *
11256  */
11257 static int pi_pre_block(struct kvm_vcpu *vcpu)
11258 {
11259         unsigned long flags;
11260         unsigned int dest;
11261         struct pi_desc old, new;
11262         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11263
11264         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11265                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11266                 !kvm_vcpu_apicv_active(vcpu))
11267                 return 0;
11268
11269         vcpu->pre_pcpu = vcpu->cpu;
11270         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11271                           vcpu->pre_pcpu), flags);
11272         list_add_tail(&vcpu->blocked_vcpu_list,
11273                       &per_cpu(blocked_vcpu_on_cpu,
11274                       vcpu->pre_pcpu));
11275         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11276                                vcpu->pre_pcpu), flags);
11277
11278         do {
11279                 old.control = new.control = pi_desc->control;
11280
11281                 /*
11282                  * We should not block the vCPU if
11283                  * an interrupt is posted for it.
11284                  */
11285                 if (pi_test_on(pi_desc) == 1) {
11286                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11287                                           vcpu->pre_pcpu), flags);
11288                         list_del(&vcpu->blocked_vcpu_list);
11289                         spin_unlock_irqrestore(
11290                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11291                                         vcpu->pre_pcpu), flags);
11292                         vcpu->pre_pcpu = -1;
11293
11294                         return 1;
11295                 }
11296
11297                 WARN((pi_desc->sn == 1),
11298                      "Warning: SN field of posted-interrupts "
11299                      "is set before blocking\n");
11300
11301                 /*
11302                  * Since vCPU can be preempted during this process,
11303                  * vcpu->cpu could be different with pre_pcpu, we
11304                  * need to set pre_pcpu as the destination of wakeup
11305                  * notification event, then we can find the right vCPU
11306                  * to wakeup in wakeup handler if interrupts happen
11307                  * when the vCPU is in blocked state.
11308                  */
11309                 dest = cpu_physical_id(vcpu->pre_pcpu);
11310
11311                 if (x2apic_enabled())
11312                         new.ndst = dest;
11313                 else
11314                         new.ndst = (dest << 8) & 0xFF00;
11315
11316                 /* set 'NV' to 'wakeup vector' */
11317                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11318         } while (cmpxchg(&pi_desc->control, old.control,
11319                         new.control) != old.control);
11320
11321         return 0;
11322 }
11323
11324 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11325 {
11326         if (pi_pre_block(vcpu))
11327                 return 1;
11328
11329         if (kvm_lapic_hv_timer_in_use(vcpu))
11330                 kvm_lapic_switch_to_sw_timer(vcpu);
11331
11332         return 0;
11333 }
11334
11335 static void pi_post_block(struct kvm_vcpu *vcpu)
11336 {
11337         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11338         struct pi_desc old, new;
11339         unsigned int dest;
11340         unsigned long flags;
11341
11342         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11343                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11344                 !kvm_vcpu_apicv_active(vcpu))
11345                 return;
11346
11347         do {
11348                 old.control = new.control = pi_desc->control;
11349
11350                 dest = cpu_physical_id(vcpu->cpu);
11351
11352                 if (x2apic_enabled())
11353                         new.ndst = dest;
11354                 else
11355                         new.ndst = (dest << 8) & 0xFF00;
11356
11357                 /* Allow posting non-urgent interrupts */
11358                 new.sn = 0;
11359
11360                 /* set 'NV' to 'notification vector' */
11361                 new.nv = POSTED_INTR_VECTOR;
11362         } while (cmpxchg(&pi_desc->control, old.control,
11363                         new.control) != old.control);
11364
11365         if(vcpu->pre_pcpu != -1) {
11366                 spin_lock_irqsave(
11367                         &per_cpu(blocked_vcpu_on_cpu_lock,
11368                         vcpu->pre_pcpu), flags);
11369                 list_del(&vcpu->blocked_vcpu_list);
11370                 spin_unlock_irqrestore(
11371                         &per_cpu(blocked_vcpu_on_cpu_lock,
11372                         vcpu->pre_pcpu), flags);
11373                 vcpu->pre_pcpu = -1;
11374         }
11375 }
11376
11377 static void vmx_post_block(struct kvm_vcpu *vcpu)
11378 {
11379         if (kvm_x86_ops->set_hv_timer)
11380                 kvm_lapic_switch_to_hv_timer(vcpu);
11381
11382         pi_post_block(vcpu);
11383 }
11384
11385 /*
11386  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11387  *
11388  * @kvm: kvm
11389  * @host_irq: host irq of the interrupt
11390  * @guest_irq: gsi of the interrupt
11391  * @set: set or unset PI
11392  * returns 0 on success, < 0 on failure
11393  */
11394 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11395                               uint32_t guest_irq, bool set)
11396 {
11397         struct kvm_kernel_irq_routing_entry *e;
11398         struct kvm_irq_routing_table *irq_rt;
11399         struct kvm_lapic_irq irq;
11400         struct kvm_vcpu *vcpu;
11401         struct vcpu_data vcpu_info;
11402         int idx, ret = -EINVAL;
11403
11404         if (!kvm_arch_has_assigned_device(kvm) ||
11405                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11406                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11407                 return 0;
11408
11409         idx = srcu_read_lock(&kvm->irq_srcu);
11410         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11411         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11412
11413         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11414                 if (e->type != KVM_IRQ_ROUTING_MSI)
11415                         continue;
11416                 /*
11417                  * VT-d PI cannot support posting multicast/broadcast
11418                  * interrupts to a vCPU, we still use interrupt remapping
11419                  * for these kind of interrupts.
11420                  *
11421                  * For lowest-priority interrupts, we only support
11422                  * those with single CPU as the destination, e.g. user
11423                  * configures the interrupts via /proc/irq or uses
11424                  * irqbalance to make the interrupts single-CPU.
11425                  *
11426                  * We will support full lowest-priority interrupt later.
11427                  */
11428
11429                 kvm_set_msi_irq(kvm, e, &irq);
11430                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11431                         /*
11432                          * Make sure the IRTE is in remapped mode if
11433                          * we don't handle it in posted mode.
11434                          */
11435                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11436                         if (ret < 0) {
11437                                 printk(KERN_INFO
11438                                    "failed to back to remapped mode, irq: %u\n",
11439                                    host_irq);
11440                                 goto out;
11441                         }
11442
11443                         continue;
11444                 }
11445
11446                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11447                 vcpu_info.vector = irq.vector;
11448
11449                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11450                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11451
11452                 if (set)
11453                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11454                 else {
11455                         /* suppress notification event before unposting */
11456                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11457                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11458                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11459                 }
11460
11461                 if (ret < 0) {
11462                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11463                                         __func__);
11464                         goto out;
11465                 }
11466         }
11467
11468         ret = 0;
11469 out:
11470         srcu_read_unlock(&kvm->irq_srcu, idx);
11471         return ret;
11472 }
11473
11474 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11475 {
11476         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11477                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11478                         FEATURE_CONTROL_LMCE;
11479         else
11480                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11481                         ~FEATURE_CONTROL_LMCE;
11482 }
11483
11484 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11485         .cpu_has_kvm_support = cpu_has_kvm_support,
11486         .disabled_by_bios = vmx_disabled_by_bios,
11487         .hardware_setup = hardware_setup,
11488         .hardware_unsetup = hardware_unsetup,
11489         .check_processor_compatibility = vmx_check_processor_compat,
11490         .hardware_enable = hardware_enable,
11491         .hardware_disable = hardware_disable,
11492         .cpu_has_accelerated_tpr = report_flexpriority,
11493         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11494
11495         .vcpu_create = vmx_create_vcpu,
11496         .vcpu_free = vmx_free_vcpu,
11497         .vcpu_reset = vmx_vcpu_reset,
11498
11499         .prepare_guest_switch = vmx_save_host_state,
11500         .vcpu_load = vmx_vcpu_load,
11501         .vcpu_put = vmx_vcpu_put,
11502
11503         .update_bp_intercept = update_exception_bitmap,
11504         .get_msr = vmx_get_msr,
11505         .set_msr = vmx_set_msr,
11506         .get_segment_base = vmx_get_segment_base,
11507         .get_segment = vmx_get_segment,
11508         .set_segment = vmx_set_segment,
11509         .get_cpl = vmx_get_cpl,
11510         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11511         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11512         .decache_cr3 = vmx_decache_cr3,
11513         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11514         .set_cr0 = vmx_set_cr0,
11515         .set_cr3 = vmx_set_cr3,
11516         .set_cr4 = vmx_set_cr4,
11517         .set_efer = vmx_set_efer,
11518         .get_idt = vmx_get_idt,
11519         .set_idt = vmx_set_idt,
11520         .get_gdt = vmx_get_gdt,
11521         .set_gdt = vmx_set_gdt,
11522         .get_dr6 = vmx_get_dr6,
11523         .set_dr6 = vmx_set_dr6,
11524         .set_dr7 = vmx_set_dr7,
11525         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11526         .cache_reg = vmx_cache_reg,
11527         .get_rflags = vmx_get_rflags,
11528         .set_rflags = vmx_set_rflags,
11529
11530         .get_pkru = vmx_get_pkru,
11531
11532         .tlb_flush = vmx_flush_tlb,
11533
11534         .run = vmx_vcpu_run,
11535         .handle_exit = vmx_handle_exit,
11536         .skip_emulated_instruction = skip_emulated_instruction,
11537         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11538         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11539         .patch_hypercall = vmx_patch_hypercall,
11540         .set_irq = vmx_inject_irq,
11541         .set_nmi = vmx_inject_nmi,
11542         .queue_exception = vmx_queue_exception,
11543         .cancel_injection = vmx_cancel_injection,
11544         .interrupt_allowed = vmx_interrupt_allowed,
11545         .nmi_allowed = vmx_nmi_allowed,
11546         .get_nmi_mask = vmx_get_nmi_mask,
11547         .set_nmi_mask = vmx_set_nmi_mask,
11548         .enable_nmi_window = enable_nmi_window,
11549         .enable_irq_window = enable_irq_window,
11550         .update_cr8_intercept = update_cr8_intercept,
11551         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11552         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11553         .get_enable_apicv = vmx_get_enable_apicv,
11554         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11555         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11556         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11557         .hwapic_irr_update = vmx_hwapic_irr_update,
11558         .hwapic_isr_update = vmx_hwapic_isr_update,
11559         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11560         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11561
11562         .set_tss_addr = vmx_set_tss_addr,
11563         .get_tdp_level = get_ept_level,
11564         .get_mt_mask = vmx_get_mt_mask,
11565
11566         .get_exit_info = vmx_get_exit_info,
11567
11568         .get_lpage_level = vmx_get_lpage_level,
11569
11570         .cpuid_update = vmx_cpuid_update,
11571
11572         .rdtscp_supported = vmx_rdtscp_supported,
11573         .invpcid_supported = vmx_invpcid_supported,
11574
11575         .set_supported_cpuid = vmx_set_supported_cpuid,
11576
11577         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11578
11579         .write_tsc_offset = vmx_write_tsc_offset,
11580
11581         .set_tdp_cr3 = vmx_set_cr3,
11582
11583         .check_intercept = vmx_check_intercept,
11584         .handle_external_intr = vmx_handle_external_intr,
11585         .mpx_supported = vmx_mpx_supported,
11586         .xsaves_supported = vmx_xsaves_supported,
11587
11588         .check_nested_events = vmx_check_nested_events,
11589
11590         .sched_in = vmx_sched_in,
11591
11592         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11593         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11594         .flush_log_dirty = vmx_flush_log_dirty,
11595         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11596
11597         .pre_block = vmx_pre_block,
11598         .post_block = vmx_post_block,
11599
11600         .pmu_ops = &intel_pmu_ops,
11601
11602         .update_pi_irte = vmx_update_pi_irte,
11603
11604 #ifdef CONFIG_X86_64
11605         .set_hv_timer = vmx_set_hv_timer,
11606         .cancel_hv_timer = vmx_cancel_hv_timer,
11607 #endif
11608
11609         .setup_mce = vmx_setup_mce,
11610 };
11611
11612 static int __init vmx_init(void)
11613 {
11614         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11615                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11616         if (r)
11617                 return r;
11618
11619 #ifdef CONFIG_KEXEC_CORE
11620         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11621                            crash_vmclear_local_loaded_vmcss);
11622 #endif
11623
11624         return 0;
11625 }
11626
11627 static void __exit vmx_exit(void)
11628 {
11629 #ifdef CONFIG_KEXEC_CORE
11630         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11631         synchronize_rcu();
11632 #endif
11633
11634         kvm_exit();
11635 }
11636
11637 module_init(vmx_init)
11638 module_exit(vmx_exit)