arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599 };
 600
 601 enum segment_cache_field {
 602         SEG_FIELD_SEL = 0,
 603         SEG_FIELD_BASE = 1,
 604         SEG_FIELD_LIMIT = 2,
 605         SEG_FIELD_AR = 3,
 606
 607         SEG_FIELD_NR = 4
 608 };
 609
 610 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 611 {
 612         return container_of(vcpu, struct vcpu_vmx, vcpu);
 613 }
 614
 615 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 616 {
 617         return &(to_vmx(vcpu)->pi_desc);
 618 }
 619
 620 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 621 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 622 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 623                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 624
 625
 626 static unsigned long shadow_read_only_fields[] = {
 627         /*
 628          * We do NOT shadow fields that are modified when L0
 629          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 630          * VMXON...) executed by L1.
 631          * For example, VM_INSTRUCTION_ERROR is read
 632          * by L1 if a vmx instruction fails (part of the error path).
 633          * Note the code assumes this logic. If for some reason
 634          * we start shadowing these fields then we need to
 635          * force a shadow sync when L0 emulates vmx instructions
 636          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 637          * by nested_vmx_failValid)
 638          */
 639         VM_EXIT_REASON,
 640         VM_EXIT_INTR_INFO,
 641         VM_EXIT_INSTRUCTION_LEN,
 642         IDT_VECTORING_INFO_FIELD,
 643         IDT_VECTORING_ERROR_CODE,
 644         VM_EXIT_INTR_ERROR_CODE,
 645         EXIT_QUALIFICATION,
 646         GUEST_LINEAR_ADDRESS,
 647         GUEST_PHYSICAL_ADDRESS
 648 };
 649 static int max_shadow_read_only_fields =
 650         ARRAY_SIZE(shadow_read_only_fields);
 651
 652 static unsigned long shadow_read_write_fields[] = {
 653         TPR_THRESHOLD,
 654         GUEST_RIP,
 655         GUEST_RSP,
 656         GUEST_CR0,
 657         GUEST_CR3,
 658         GUEST_CR4,
 659         GUEST_INTERRUPTIBILITY_INFO,
 660         GUEST_RFLAGS,
 661         GUEST_CS_SELECTOR,
 662         GUEST_CS_AR_BYTES,
 663         GUEST_CS_LIMIT,
 664         GUEST_CS_BASE,
 665         GUEST_ES_BASE,
 666         GUEST_BNDCFGS,
 667         CR0_GUEST_HOST_MASK,
 668         CR0_READ_SHADOW,
 669         CR4_READ_SHADOW,
 670         TSC_OFFSET,
 671         EXCEPTION_BITMAP,
 672         CPU_BASED_VM_EXEC_CONTROL,
 673         VM_ENTRY_EXCEPTION_ERROR_CODE,
 674         VM_ENTRY_INTR_INFO_FIELD,
 675         VM_ENTRY_INSTRUCTION_LEN,
 676         VM_ENTRY_EXCEPTION_ERROR_CODE,
 677         HOST_FS_BASE,
 678         HOST_GS_BASE,
 679         HOST_FS_SELECTOR,
 680         HOST_GS_SELECTOR
 681 };
 682 static int max_shadow_read_write_fields =
 683         ARRAY_SIZE(shadow_read_write_fields);
 684
 685 static const unsigned short vmcs_field_to_offset_table[] = {
 686         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 687         FIELD(POSTED_INTR_NV, posted_intr_nv),
 688         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 689         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 690         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 691         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 692         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 693         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 694         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 695         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 696         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 697         FIELD(HOST_ES_SELECTOR, host_es_selector),
 698         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 699         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 700         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 701         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 702         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 703         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 704         FIELD64(IO_BITMAP_A, io_bitmap_a),
 705         FIELD64(IO_BITMAP_B, io_bitmap_b),
 706         FIELD64(MSR_BITMAP, msr_bitmap),
 707         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 708         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 709         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 710         FIELD64(TSC_OFFSET, tsc_offset),
 711         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 712         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 713         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 714         FIELD64(EPT_POINTER, ept_pointer),
 715         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 716         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 717         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 718         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 719         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 720         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 721         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 722         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 723         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 724         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 725         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 726         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 727         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 728         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 729         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 730         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 731         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 732         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 733         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 734         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 735         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 736         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 737         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 738         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 739         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 740         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 741         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 742         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 743         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 744         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 745         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 746         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 747         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 748         FIELD(TPR_THRESHOLD, tpr_threshold),
 749         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 750         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 751         FIELD(VM_EXIT_REASON, vm_exit_reason),
 752         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 753         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 754         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 755         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 756         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 757         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 758         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 759         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 760         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 761         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 762         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 763         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 764         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 765         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 766         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 767         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 768         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 769         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 770         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 771         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 772         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 773         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 774         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 775         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 776         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 777         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 778         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 779         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 780         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 781         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 782         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 783         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 784         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 785         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 786         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 787         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 788         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 789         FIELD(EXIT_QUALIFICATION, exit_qualification),
 790         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 791         FIELD(GUEST_CR0, guest_cr0),
 792         FIELD(GUEST_CR3, guest_cr3),
 793         FIELD(GUEST_CR4, guest_cr4),
 794         FIELD(GUEST_ES_BASE, guest_es_base),
 795         FIELD(GUEST_CS_BASE, guest_cs_base),
 796         FIELD(GUEST_SS_BASE, guest_ss_base),
 797         FIELD(GUEST_DS_BASE, guest_ds_base),
 798         FIELD(GUEST_FS_BASE, guest_fs_base),
 799         FIELD(GUEST_GS_BASE, guest_gs_base),
 800         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 801         FIELD(GUEST_TR_BASE, guest_tr_base),
 802         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 803         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 804         FIELD(GUEST_DR7, guest_dr7),
 805         FIELD(GUEST_RSP, guest_rsp),
 806         FIELD(GUEST_RIP, guest_rip),
 807         FIELD(GUEST_RFLAGS, guest_rflags),
 808         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 809         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 810         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 811         FIELD(HOST_CR0, host_cr0),
 812         FIELD(HOST_CR3, host_cr3),
 813         FIELD(HOST_CR4, host_cr4),
 814         FIELD(HOST_FS_BASE, host_fs_base),
 815         FIELD(HOST_GS_BASE, host_gs_base),
 816         FIELD(HOST_TR_BASE, host_tr_base),
 817         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 818         FIELD(HOST_IDTR_BASE, host_idtr_base),
 819         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 820         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 821         FIELD(HOST_RSP, host_rsp),
 822         FIELD(HOST_RIP, host_rip),
 823 };
 824
 825 static inline short vmcs_field_to_offset(unsigned long field)
 826 {
 827         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 828
 829         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 830             vmcs_field_to_offset_table[field] == 0)
 831                 return -ENOENT;
 832
 833         return vmcs_field_to_offset_table[field];
 834 }
 835
 836 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 837 {
 838         return to_vmx(vcpu)->nested.current_vmcs12;
 839 }
 840
 841 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 842 {
 843         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 844         if (is_error_page(page))
 845                 return NULL;
 846
 847         return page;
 848 }
 849
 850 static void nested_release_page(struct page *page)
 851 {
 852         kvm_release_page_dirty(page);
 853 }
 854
 855 static void nested_release_page_clean(struct page *page)
 856 {
 857         kvm_release_page_clean(page);
 858 }
 859
 860 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 861 static u64 construct_eptp(unsigned long root_hpa);
 862 static void kvm_cpu_vmxon(u64 addr);
 863 static void kvm_cpu_vmxoff(void);
 864 static bool vmx_mpx_supported(void);
 865 static bool vmx_xsaves_supported(void);
 866 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 867 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 868                             struct kvm_segment *var, int seg);
 869 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 872 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 873 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 874 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 875 static int alloc_identity_pagetable(struct kvm *kvm);
 876
 877 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 878 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 879 /*
 880  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 881  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 882  */
 883 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 884 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 885
 886 /*
 887  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 888  * can find which vCPU should be waken up.
 889  */
 890 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 891 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 892
 893 static unsigned long *vmx_io_bitmap_a;
 894 static unsigned long *vmx_io_bitmap_b;
 895 static unsigned long *vmx_msr_bitmap_legacy;
 896 static unsigned long *vmx_msr_bitmap_longmode;
 897 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 898 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 899 static unsigned long *vmx_msr_bitmap_nested;
 900 static unsigned long *vmx_vmread_bitmap;
 901 static unsigned long *vmx_vmwrite_bitmap;
 902
 903 static bool cpu_has_load_ia32_efer;
 904 static bool cpu_has_load_perf_global_ctrl;
 905
 906 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 907 static DEFINE_SPINLOCK(vmx_vpid_lock);
 908
 909 static struct vmcs_config {
 910         int size;
 911         int order;
 912         u32 revision_id;
 913         u32 pin_based_exec_ctrl;
 914         u32 cpu_based_exec_ctrl;
 915         u32 cpu_based_2nd_exec_ctrl;
 916         u32 vmexit_ctrl;
 917         u32 vmentry_ctrl;
 918 } vmcs_config;
 919
 920 static struct vmx_capability {
 921         u32 ept;
 922         u32 vpid;
 923 } vmx_capability;
 924
 925 #define VMX_SEGMENT_FIELD(seg)                                  \
 926         [VCPU_SREG_##seg] = {                                   \
 927                 .selector = GUEST_##seg##_SELECTOR,             \
 928                 .base = GUEST_##seg##_BASE,                     \
 929                 .limit = GUEST_##seg##_LIMIT,                   \
 930                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 931         }
 932
 933 static const struct kvm_vmx_segment_field {
 934         unsigned selector;
 935         unsigned base;
 936         unsigned limit;
 937         unsigned ar_bytes;
 938 } kvm_vmx_segment_fields[] = {
 939         VMX_SEGMENT_FIELD(CS),
 940         VMX_SEGMENT_FIELD(DS),
 941         VMX_SEGMENT_FIELD(ES),
 942         VMX_SEGMENT_FIELD(FS),
 943         VMX_SEGMENT_FIELD(GS),
 944         VMX_SEGMENT_FIELD(SS),
 945         VMX_SEGMENT_FIELD(TR),
 946         VMX_SEGMENT_FIELD(LDTR),
 947 };
 948
 949 static u64 host_efer;
 950
 951 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 952
 953 /*
 954  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 955  * away by decrementing the array size.
 956  */
 957 static const u32 vmx_msr_index[] = {
 958 #ifdef CONFIG_X86_64
 959         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 960 #endif
 961         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 962 };
 963
 964 static inline bool is_page_fault(u32 intr_info)
 965 {
 966         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 967                              INTR_INFO_VALID_MASK)) ==
 968                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 969 }
 970
 971 static inline bool is_no_device(u32 intr_info)
 972 {
 973         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 974                              INTR_INFO_VALID_MASK)) ==
 975                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 976 }
 977
 978 static inline bool is_invalid_opcode(u32 intr_info)
 979 {
 980         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 981                              INTR_INFO_VALID_MASK)) ==
 982                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 983 }
 984
 985 static inline bool is_external_interrupt(u32 intr_info)
 986 {
 987         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 988                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 989 }
 990
 991 static inline bool is_machine_check(u32 intr_info)
 992 {
 993         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 994                              INTR_INFO_VALID_MASK)) ==
 995                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 996 }
 997
 998 static inline bool cpu_has_vmx_msr_bitmap(void)
 999 {
1000         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1001 }
1002
1003 static inline bool cpu_has_vmx_tpr_shadow(void)
1004 {
1005         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1006 }
1007
1008 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1009 {
1010         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1011 }
1012
1013 static inline bool cpu_has_secondary_exec_ctrls(void)
1014 {
1015         return vmcs_config.cpu_based_exec_ctrl &
1016                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1017 }
1018
1019 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1020 {
1021         return vmcs_config.cpu_based_2nd_exec_ctrl &
1022                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1023 }
1024
1025 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1026 {
1027         return vmcs_config.cpu_based_2nd_exec_ctrl &
1028                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1029 }
1030
1031 static inline bool cpu_has_vmx_apic_register_virt(void)
1032 {
1033         return vmcs_config.cpu_based_2nd_exec_ctrl &
1034                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1035 }
1036
1037 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1038 {
1039         return vmcs_config.cpu_based_2nd_exec_ctrl &
1040                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1041 }
1042
1043 static inline bool cpu_has_vmx_posted_intr(void)
1044 {
1045         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1046                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1047 }
1048
1049 static inline bool cpu_has_vmx_apicv(void)
1050 {
1051         return cpu_has_vmx_apic_register_virt() &&
1052                 cpu_has_vmx_virtual_intr_delivery() &&
1053                 cpu_has_vmx_posted_intr();
1054 }
1055
1056 static inline bool cpu_has_vmx_flexpriority(void)
1057 {
1058         return cpu_has_vmx_tpr_shadow() &&
1059                 cpu_has_vmx_virtualize_apic_accesses();
1060 }
1061
1062 static inline bool cpu_has_vmx_ept_execute_only(void)
1063 {
1064         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1065 }
1066
1067 static inline bool cpu_has_vmx_ept_2m_page(void)
1068 {
1069         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1070 }
1071
1072 static inline bool cpu_has_vmx_ept_1g_page(void)
1073 {
1074         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1075 }
1076
1077 static inline bool cpu_has_vmx_ept_4levels(void)
1078 {
1079         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1080 }
1081
1082 static inline bool cpu_has_vmx_ept_ad_bits(void)
1083 {
1084         return vmx_capability.ept & VMX_EPT_AD_BIT;
1085 }
1086
1087 static inline bool cpu_has_vmx_invept_context(void)
1088 {
1089         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1090 }
1091
1092 static inline bool cpu_has_vmx_invept_global(void)
1093 {
1094         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1095 }
1096
1097 static inline bool cpu_has_vmx_invvpid_single(void)
1098 {
1099         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1100 }
1101
1102 static inline bool cpu_has_vmx_invvpid_global(void)
1103 {
1104         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1105 }
1106
1107 static inline bool cpu_has_vmx_ept(void)
1108 {
1109         return vmcs_config.cpu_based_2nd_exec_ctrl &
1110                 SECONDARY_EXEC_ENABLE_EPT;
1111 }
1112
1113 static inline bool cpu_has_vmx_unrestricted_guest(void)
1114 {
1115         return vmcs_config.cpu_based_2nd_exec_ctrl &
1116                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1117 }
1118
1119 static inline bool cpu_has_vmx_ple(void)
1120 {
1121         return vmcs_config.cpu_based_2nd_exec_ctrl &
1122                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1123 }
1124
1125 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1126 {
1127         return flexpriority_enabled && lapic_in_kernel(vcpu);
1128 }
1129
1130 static inline bool cpu_has_vmx_vpid(void)
1131 {
1132         return vmcs_config.cpu_based_2nd_exec_ctrl &
1133                 SECONDARY_EXEC_ENABLE_VPID;
1134 }
1135
1136 static inline bool cpu_has_vmx_rdtscp(void)
1137 {
1138         return vmcs_config.cpu_based_2nd_exec_ctrl &
1139                 SECONDARY_EXEC_RDTSCP;
1140 }
1141
1142 static inline bool cpu_has_vmx_invpcid(void)
1143 {
1144         return vmcs_config.cpu_based_2nd_exec_ctrl &
1145                 SECONDARY_EXEC_ENABLE_INVPCID;
1146 }
1147
1148 static inline bool cpu_has_virtual_nmis(void)
1149 {
1150         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1151 }
1152
1153 static inline bool cpu_has_vmx_wbinvd_exit(void)
1154 {
1155         return vmcs_config.cpu_based_2nd_exec_ctrl &
1156                 SECONDARY_EXEC_WBINVD_EXITING;
1157 }
1158
1159 static inline bool cpu_has_vmx_shadow_vmcs(void)
1160 {
1161         u64 vmx_msr;
1162         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1163         /* check if the cpu supports writing r/o exit information fields */
1164         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1165                 return false;
1166
1167         return vmcs_config.cpu_based_2nd_exec_ctrl &
1168                 SECONDARY_EXEC_SHADOW_VMCS;
1169 }
1170
1171 static inline bool cpu_has_vmx_pml(void)
1172 {
1173         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1174 }
1175
1176 static inline bool cpu_has_vmx_tsc_scaling(void)
1177 {
1178         return vmcs_config.cpu_based_2nd_exec_ctrl &
1179                 SECONDARY_EXEC_TSC_SCALING;
1180 }
1181
1182 static inline bool report_flexpriority(void)
1183 {
1184         return flexpriority_enabled;
1185 }
1186
1187 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1188 {
1189         return vmcs12->cpu_based_vm_exec_control & bit;
1190 }
1191
1192 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1193 {
1194         return (vmcs12->cpu_based_vm_exec_control &
1195                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1196                 (vmcs12->secondary_vm_exec_control & bit);
1197 }
1198
1199 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1200 {
1201         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1202 }
1203
1204 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1205 {
1206         return vmcs12->pin_based_vm_exec_control &
1207                 PIN_BASED_VMX_PREEMPTION_TIMER;
1208 }
1209
1210 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1211 {
1212         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1213 }
1214
1215 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1216 {
1217         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1218                 vmx_xsaves_supported();
1219 }
1220
1221 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1222 {
1223         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1224 }
1225
1226 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1227 {
1228         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1229 }
1230
1231 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1232 {
1233         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1234 }
1235
1236 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1237 {
1238         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1239 }
1240
1241 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1242 {
1243         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1244 }
1245
1246 static inline bool is_exception(u32 intr_info)
1247 {
1248         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1249                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1250 }
1251
1252 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1253                               u32 exit_intr_info,
1254                               unsigned long exit_qualification);
1255 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1256                         struct vmcs12 *vmcs12,
1257                         u32 reason, unsigned long qualification);
1258
1259 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1260 {
1261         int i;
1262
1263         for (i = 0; i < vmx->nmsrs; ++i)
1264                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1265                         return i;
1266         return -1;
1267 }
1268
1269 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1270 {
1271     struct {
1272         u64 vpid : 16;
1273         u64 rsvd : 48;
1274         u64 gva;
1275     } operand = { vpid, 0, gva };
1276
1277     asm volatile (__ex(ASM_VMX_INVVPID)
1278                   /* CF==1 or ZF==1 --> rc = -1 */
1279                   "; ja 1f ; ud2 ; 1:"
1280                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1281 }
1282
1283 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1284 {
1285         struct {
1286                 u64 eptp, gpa;
1287         } operand = {eptp, gpa};
1288
1289         asm volatile (__ex(ASM_VMX_INVEPT)
1290                         /* CF==1 or ZF==1 --> rc = -1 */
1291                         "; ja 1f ; ud2 ; 1:\n"
1292                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1293 }
1294
1295 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1296 {
1297         int i;
1298
1299         i = __find_msr_index(vmx, msr);
1300         if (i >= 0)
1301                 return &vmx->guest_msrs[i];
1302         return NULL;
1303 }
1304
1305 static void vmcs_clear(struct vmcs *vmcs)
1306 {
1307         u64 phys_addr = __pa(vmcs);
1308         u8 error;
1309
1310         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1311                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1312                       : "cc", "memory");
1313         if (error)
1314                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1315                        vmcs, phys_addr);
1316 }
1317
1318 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1319 {
1320         vmcs_clear(loaded_vmcs->vmcs);
1321         loaded_vmcs->cpu = -1;
1322         loaded_vmcs->launched = 0;
1323 }
1324
1325 static void vmcs_load(struct vmcs *vmcs)
1326 {
1327         u64 phys_addr = __pa(vmcs);
1328         u8 error;
1329
1330         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1331                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1332                         : "cc", "memory");
1333         if (error)
1334                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1335                        vmcs, phys_addr);
1336 }
1337
1338 #ifdef CONFIG_KEXEC_CORE
1339 /*
1340  * This bitmap is used to indicate whether the vmclear
1341  * operation is enabled on all cpus. All disabled by
1342  * default.
1343  */
1344 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1345
1346 static inline void crash_enable_local_vmclear(int cpu)
1347 {
1348         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1349 }
1350
1351 static inline void crash_disable_local_vmclear(int cpu)
1352 {
1353         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1354 }
1355
1356 static inline int crash_local_vmclear_enabled(int cpu)
1357 {
1358         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1359 }
1360
1361 static void crash_vmclear_local_loaded_vmcss(void)
1362 {
1363         int cpu = raw_smp_processor_id();
1364         struct loaded_vmcs *v;
1365
1366         if (!crash_local_vmclear_enabled(cpu))
1367                 return;
1368
1369         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1370                             loaded_vmcss_on_cpu_link)
1371                 vmcs_clear(v->vmcs);
1372 }
1373 #else
1374 static inline void crash_enable_local_vmclear(int cpu) { }
1375 static inline void crash_disable_local_vmclear(int cpu) { }
1376 #endif /* CONFIG_KEXEC_CORE */
1377
1378 static void __loaded_vmcs_clear(void *arg)
1379 {
1380         struct loaded_vmcs *loaded_vmcs = arg;
1381         int cpu = raw_smp_processor_id();
1382
1383         if (loaded_vmcs->cpu != cpu)
1384                 return; /* vcpu migration can race with cpu offline */
1385         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1386                 per_cpu(current_vmcs, cpu) = NULL;
1387         crash_disable_local_vmclear(cpu);
1388         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1389
1390         /*
1391          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1392          * is before setting loaded_vmcs->vcpu to -1 which is done in
1393          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1394          * then adds the vmcs into percpu list before it is deleted.
1395          */
1396         smp_wmb();
1397
1398         loaded_vmcs_init(loaded_vmcs);
1399         crash_enable_local_vmclear(cpu);
1400 }
1401
1402 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1403 {
1404         int cpu = loaded_vmcs->cpu;
1405
1406         if (cpu != -1)
1407                 smp_call_function_single(cpu,
1408                          __loaded_vmcs_clear, loaded_vmcs, 1);
1409 }
1410
1411 static inline void vpid_sync_vcpu_single(int vpid)
1412 {
1413         if (vpid == 0)
1414                 return;
1415
1416         if (cpu_has_vmx_invvpid_single())
1417                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1418 }
1419
1420 static inline void vpid_sync_vcpu_global(void)
1421 {
1422         if (cpu_has_vmx_invvpid_global())
1423                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1424 }
1425
1426 static inline void vpid_sync_context(int vpid)
1427 {
1428         if (cpu_has_vmx_invvpid_single())
1429                 vpid_sync_vcpu_single(vpid);
1430         else
1431                 vpid_sync_vcpu_global();
1432 }
1433
1434 static inline void ept_sync_global(void)
1435 {
1436         if (cpu_has_vmx_invept_global())
1437                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1438 }
1439
1440 static inline void ept_sync_context(u64 eptp)
1441 {
1442         if (enable_ept) {
1443                 if (cpu_has_vmx_invept_context())
1444                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1445                 else
1446                         ept_sync_global();
1447         }
1448 }
1449
1450 static __always_inline unsigned long vmcs_readl(unsigned long field)
1451 {
1452         unsigned long value;
1453
1454         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1455                       : "=a"(value) : "d"(field) : "cc");
1456         return value;
1457 }
1458
1459 static __always_inline u16 vmcs_read16(unsigned long field)
1460 {
1461         return vmcs_readl(field);
1462 }
1463
1464 static __always_inline u32 vmcs_read32(unsigned long field)
1465 {
1466         return vmcs_readl(field);
1467 }
1468
1469 static __always_inline u64 vmcs_read64(unsigned long field)
1470 {
1471 #ifdef CONFIG_X86_64
1472         return vmcs_readl(field);
1473 #else
1474         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1475 #endif
1476 }
1477
1478 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1479 {
1480         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1481                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1482         dump_stack();
1483 }
1484
1485 static void vmcs_writel(unsigned long field, unsigned long value)
1486 {
1487         u8 error;
1488
1489         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1490                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1491         if (unlikely(error))
1492                 vmwrite_error(field, value);
1493 }
1494
1495 static void vmcs_write16(unsigned long field, u16 value)
1496 {
1497         vmcs_writel(field, value);
1498 }
1499
1500 static void vmcs_write32(unsigned long field, u32 value)
1501 {
1502         vmcs_writel(field, value);
1503 }
1504
1505 static void vmcs_write64(unsigned long field, u64 value)
1506 {
1507         vmcs_writel(field, value);
1508 #ifndef CONFIG_X86_64
1509         asm volatile ("");
1510         vmcs_writel(field+1, value >> 32);
1511 #endif
1512 }
1513
1514 static void vmcs_clear_bits(unsigned long field, u32 mask)
1515 {
1516         vmcs_writel(field, vmcs_readl(field) & ~mask);
1517 }
1518
1519 static void vmcs_set_bits(unsigned long field, u32 mask)
1520 {
1521         vmcs_writel(field, vmcs_readl(field) | mask);
1522 }
1523
1524 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1525 {
1526         vmcs_write32(VM_ENTRY_CONTROLS, val);
1527         vmx->vm_entry_controls_shadow = val;
1528 }
1529
1530 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1531 {
1532         if (vmx->vm_entry_controls_shadow != val)
1533                 vm_entry_controls_init(vmx, val);
1534 }
1535
1536 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1537 {
1538         return vmx->vm_entry_controls_shadow;
1539 }
1540
1541
1542 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1543 {
1544         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1545 }
1546
1547 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1548 {
1549         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1550 }
1551
1552 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1553 {
1554         vmcs_write32(VM_EXIT_CONTROLS, val);
1555         vmx->vm_exit_controls_shadow = val;
1556 }
1557
1558 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1559 {
1560         if (vmx->vm_exit_controls_shadow != val)
1561                 vm_exit_controls_init(vmx, val);
1562 }
1563
1564 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1565 {
1566         return vmx->vm_exit_controls_shadow;
1567 }
1568
1569
1570 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1571 {
1572         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1573 }
1574
1575 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1576 {
1577         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1578 }
1579
1580 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1581 {
1582         vmx->segment_cache.bitmask = 0;
1583 }
1584
1585 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1586                                        unsigned field)
1587 {
1588         bool ret;
1589         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1590
1591         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1592                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1593                 vmx->segment_cache.bitmask = 0;
1594         }
1595         ret = vmx->segment_cache.bitmask & mask;
1596         vmx->segment_cache.bitmask |= mask;
1597         return ret;
1598 }
1599
1600 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1601 {
1602         u16 *p = &vmx->segment_cache.seg[seg].selector;
1603
1604         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1605                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1606         return *p;
1607 }
1608
1609 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1610 {
1611         ulong *p = &vmx->segment_cache.seg[seg].base;
1612
1613         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1614                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1615         return *p;
1616 }
1617
1618 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1619 {
1620         u32 *p = &vmx->segment_cache.seg[seg].limit;
1621
1622         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1623                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1624         return *p;
1625 }
1626
1627 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1628 {
1629         u32 *p = &vmx->segment_cache.seg[seg].ar;
1630
1631         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1632                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1633         return *p;
1634 }
1635
1636 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1637 {
1638         u32 eb;
1639
1640         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1641              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1642         if ((vcpu->guest_debug &
1643              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1644             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1645                 eb |= 1u << BP_VECTOR;
1646         if (to_vmx(vcpu)->rmode.vm86_active)
1647                 eb = ~0;
1648         if (enable_ept)
1649                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1650         if (vcpu->fpu_active)
1651                 eb &= ~(1u << NM_VECTOR);
1652
1653         /* When we are running a nested L2 guest and L1 specified for it a
1654          * certain exception bitmap, we must trap the same exceptions and pass
1655          * them to L1. When running L2, we will only handle the exceptions
1656          * specified above if L1 did not want them.
1657          */
1658         if (is_guest_mode(vcpu))
1659                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1660
1661         vmcs_write32(EXCEPTION_BITMAP, eb);
1662 }
1663
1664 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1665                 unsigned long entry, unsigned long exit)
1666 {
1667         vm_entry_controls_clearbit(vmx, entry);
1668         vm_exit_controls_clearbit(vmx, exit);
1669 }
1670
1671 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1672 {
1673         unsigned i;
1674         struct msr_autoload *m = &vmx->msr_autoload;
1675
1676         switch (msr) {
1677         case MSR_EFER:
1678                 if (cpu_has_load_ia32_efer) {
1679                         clear_atomic_switch_msr_special(vmx,
1680                                         VM_ENTRY_LOAD_IA32_EFER,
1681                                         VM_EXIT_LOAD_IA32_EFER);
1682                         return;
1683                 }
1684                 break;
1685         case MSR_CORE_PERF_GLOBAL_CTRL:
1686                 if (cpu_has_load_perf_global_ctrl) {
1687                         clear_atomic_switch_msr_special(vmx,
1688                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1689                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1690                         return;
1691                 }
1692                 break;
1693         }
1694
1695         for (i = 0; i < m->nr; ++i)
1696                 if (m->guest[i].index == msr)
1697                         break;
1698
1699         if (i == m->nr)
1700                 return;
1701         --m->nr;
1702         m->guest[i] = m->guest[m->nr];
1703         m->host[i] = m->host[m->nr];
1704         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1705         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1706 }
1707
1708 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1709                 unsigned long entry, unsigned long exit,
1710                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1711                 u64 guest_val, u64 host_val)
1712 {
1713         vmcs_write64(guest_val_vmcs, guest_val);
1714         vmcs_write64(host_val_vmcs, host_val);
1715         vm_entry_controls_setbit(vmx, entry);
1716         vm_exit_controls_setbit(vmx, exit);
1717 }
1718
1719 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1720                                   u64 guest_val, u64 host_val)
1721 {
1722         unsigned i;
1723         struct msr_autoload *m = &vmx->msr_autoload;
1724
1725         switch (msr) {
1726         case MSR_EFER:
1727                 if (cpu_has_load_ia32_efer) {
1728                         add_atomic_switch_msr_special(vmx,
1729                                         VM_ENTRY_LOAD_IA32_EFER,
1730                                         VM_EXIT_LOAD_IA32_EFER,
1731                                         GUEST_IA32_EFER,
1732                                         HOST_IA32_EFER,
1733                                         guest_val, host_val);
1734                         return;
1735                 }
1736                 break;
1737         case MSR_CORE_PERF_GLOBAL_CTRL:
1738                 if (cpu_has_load_perf_global_ctrl) {
1739                         add_atomic_switch_msr_special(vmx,
1740                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1741                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1742                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1743                                         HOST_IA32_PERF_GLOBAL_CTRL,
1744                                         guest_val, host_val);
1745                         return;
1746                 }
1747                 break;
1748         }
1749
1750         for (i = 0; i < m->nr; ++i)
1751                 if (m->guest[i].index == msr)
1752                         break;
1753
1754         if (i == NR_AUTOLOAD_MSRS) {
1755                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1756                                 "Can't add msr %x\n", msr);
1757                 return;
1758         } else if (i == m->nr) {
1759                 ++m->nr;
1760                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1761                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1762         }
1763
1764         m->guest[i].index = msr;
1765         m->guest[i].value = guest_val;
1766         m->host[i].index = msr;
1767         m->host[i].value = host_val;
1768 }
1769
1770 static void reload_tss(void)
1771 {
1772         /*
1773          * VT restores TR but not its size.  Useless.
1774          */
1775         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1776         struct desc_struct *descs;
1777
1778         descs = (void *)gdt->address;
1779         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1780         load_TR_desc();
1781 }
1782
1783 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1784 {
1785         u64 guest_efer;
1786         u64 ignore_bits;
1787
1788         guest_efer = vmx->vcpu.arch.efer;
1789
1790         /*
1791          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1792          * outside long mode
1793          */
1794         ignore_bits = EFER_NX | EFER_SCE;
1795 #ifdef CONFIG_X86_64
1796         ignore_bits |= EFER_LMA | EFER_LME;
1797         /* SCE is meaningful only in long mode on Intel */
1798         if (guest_efer & EFER_LMA)
1799                 ignore_bits &= ~(u64)EFER_SCE;
1800 #endif
1801         guest_efer &= ~ignore_bits;
1802         guest_efer |= host_efer & ignore_bits;
1803         vmx->guest_msrs[efer_offset].data = guest_efer;
1804         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1805
1806         clear_atomic_switch_msr(vmx, MSR_EFER);
1807
1808         /*
1809          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1810          * On CPUs that support "load IA32_EFER", always switch EFER
1811          * atomically, since it's faster than switching it manually.
1812          */
1813         if (cpu_has_load_ia32_efer ||
1814             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1815                 guest_efer = vmx->vcpu.arch.efer;
1816                 if (!(guest_efer & EFER_LMA))
1817                         guest_efer &= ~EFER_LME;
1818                 if (guest_efer != host_efer)
1819                         add_atomic_switch_msr(vmx, MSR_EFER,
1820                                               guest_efer, host_efer);
1821                 return false;
1822         }
1823
1824         return true;
1825 }
1826
1827 static unsigned long segment_base(u16 selector)
1828 {
1829         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1830         struct desc_struct *d;
1831         unsigned long table_base;
1832         unsigned long v;
1833
1834         if (!(selector & ~3))
1835                 return 0;
1836
1837         table_base = gdt->address;
1838
1839         if (selector & 4) {           /* from ldt */
1840                 u16 ldt_selector = kvm_read_ldt();
1841
1842                 if (!(ldt_selector & ~3))
1843                         return 0;
1844
1845                 table_base = segment_base(ldt_selector);
1846         }
1847         d = (struct desc_struct *)(table_base + (selector & ~7));
1848         v = get_desc_base(d);
1849 #ifdef CONFIG_X86_64
1850        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1851                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1852 #endif
1853         return v;
1854 }
1855
1856 static inline unsigned long kvm_read_tr_base(void)
1857 {
1858         u16 tr;
1859         asm("str %0" : "=g"(tr));
1860         return segment_base(tr);
1861 }
1862
1863 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1864 {
1865         struct vcpu_vmx *vmx = to_vmx(vcpu);
1866         int i;
1867
1868         if (vmx->host_state.loaded)
1869                 return;
1870
1871         vmx->host_state.loaded = 1;
1872         /*
1873          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1874          * allow segment selectors with cpl > 0 or ti == 1.
1875          */
1876         vmx->host_state.ldt_sel = kvm_read_ldt();
1877         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1878         savesegment(fs, vmx->host_state.fs_sel);
1879         if (!(vmx->host_state.fs_sel & 7)) {
1880                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1881                 vmx->host_state.fs_reload_needed = 0;
1882         } else {
1883                 vmcs_write16(HOST_FS_SELECTOR, 0);
1884                 vmx->host_state.fs_reload_needed = 1;
1885         }
1886         savesegment(gs, vmx->host_state.gs_sel);
1887         if (!(vmx->host_state.gs_sel & 7))
1888                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1889         else {
1890                 vmcs_write16(HOST_GS_SELECTOR, 0);
1891                 vmx->host_state.gs_ldt_reload_needed = 1;
1892         }
1893
1894 #ifdef CONFIG_X86_64
1895         savesegment(ds, vmx->host_state.ds_sel);
1896         savesegment(es, vmx->host_state.es_sel);
1897 #endif
1898
1899 #ifdef CONFIG_X86_64
1900         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1901         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1902 #else
1903         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1904         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1905 #endif
1906
1907 #ifdef CONFIG_X86_64
1908         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1909         if (is_long_mode(&vmx->vcpu))
1910                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1911 #endif
1912         if (boot_cpu_has(X86_FEATURE_MPX))
1913                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1914         for (i = 0; i < vmx->save_nmsrs; ++i)
1915                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1916                                    vmx->guest_msrs[i].data,
1917                                    vmx->guest_msrs[i].mask);
1918 }
1919
1920 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1921 {
1922         if (!vmx->host_state.loaded)
1923                 return;
1924
1925         ++vmx->vcpu.stat.host_state_reload;
1926         vmx->host_state.loaded = 0;
1927 #ifdef CONFIG_X86_64
1928         if (is_long_mode(&vmx->vcpu))
1929                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1930 #endif
1931         if (vmx->host_state.gs_ldt_reload_needed) {
1932                 kvm_load_ldt(vmx->host_state.ldt_sel);
1933 #ifdef CONFIG_X86_64
1934                 load_gs_index(vmx->host_state.gs_sel);
1935 #else
1936                 loadsegment(gs, vmx->host_state.gs_sel);
1937 #endif
1938         }
1939         if (vmx->host_state.fs_reload_needed)
1940                 loadsegment(fs, vmx->host_state.fs_sel);
1941 #ifdef CONFIG_X86_64
1942         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1943                 loadsegment(ds, vmx->host_state.ds_sel);
1944                 loadsegment(es, vmx->host_state.es_sel);
1945         }
1946 #endif
1947         reload_tss();
1948 #ifdef CONFIG_X86_64
1949         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1950 #endif
1951         if (vmx->host_state.msr_host_bndcfgs)
1952                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1953         /*
1954          * If the FPU is not active (through the host task or
1955          * the guest vcpu), then restore the cr0.TS bit.
1956          */
1957         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1958                 stts();
1959         load_gdt(this_cpu_ptr(&host_gdt));
1960 }
1961
1962 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1963 {
1964         preempt_disable();
1965         __vmx_load_host_state(vmx);
1966         preempt_enable();
1967 }
1968
1969 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1970 {
1971         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1972         struct pi_desc old, new;
1973         unsigned int dest;
1974
1975         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1976                 !irq_remapping_cap(IRQ_POSTING_CAP))
1977                 return;
1978
1979         do {
1980                 old.control = new.control = pi_desc->control;
1981
1982                 /*
1983                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1984                  * are two possible cases:
1985                  * 1. After running 'pre_block', context switch
1986                  *    happened. For this case, 'sn' was set in
1987                  *    vmx_vcpu_put(), so we need to clear it here.
1988                  * 2. After running 'pre_block', we were blocked,
1989                  *    and woken up by some other guy. For this case,
1990                  *    we don't need to do anything, 'pi_post_block'
1991                  *    will do everything for us. However, we cannot
1992                  *    check whether it is case #1 or case #2 here
1993                  *    (maybe, not needed), so we also clear sn here,
1994                  *    I think it is not a big deal.
1995                  */
1996                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1997                         if (vcpu->cpu != cpu) {
1998                                 dest = cpu_physical_id(cpu);
1999
2000                                 if (x2apic_enabled())
2001                                         new.ndst = dest;
2002                                 else
2003                                         new.ndst = (dest << 8) & 0xFF00;
2004                         }
2005
2006                         /* set 'NV' to 'notification vector' */
2007                         new.nv = POSTED_INTR_VECTOR;
2008                 }
2009
2010                 /* Allow posting non-urgent interrupts */
2011                 new.sn = 0;
2012         } while (cmpxchg(&pi_desc->control, old.control,
2013                         new.control) != old.control);
2014 }
2015 /*
2016  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2017  * vcpu mutex is already taken.
2018  */
2019 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2020 {
2021         struct vcpu_vmx *vmx = to_vmx(vcpu);
2022         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2023
2024         if (!vmm_exclusive)
2025                 kvm_cpu_vmxon(phys_addr);
2026         else if (vmx->loaded_vmcs->cpu != cpu)
2027                 loaded_vmcs_clear(vmx->loaded_vmcs);
2028
2029         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2030                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2031                 vmcs_load(vmx->loaded_vmcs->vmcs);
2032         }
2033
2034         if (vmx->loaded_vmcs->cpu != cpu) {
2035                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2036                 unsigned long sysenter_esp;
2037
2038                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2039                 local_irq_disable();
2040                 crash_disable_local_vmclear(cpu);
2041
2042                 /*
2043                  * Read loaded_vmcs->cpu should be before fetching
2044                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2045                  * See the comments in __loaded_vmcs_clear().
2046                  */
2047                 smp_rmb();
2048
2049                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2050                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2051                 crash_enable_local_vmclear(cpu);
2052                 local_irq_enable();
2053
2054                 /*
2055                  * Linux uses per-cpu TSS and GDT, so set these when switching
2056                  * processors.
2057                  */
2058                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2059                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2060
2061                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2062                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2063
2064                 /* Setup TSC multiplier */
2065                 if (cpu_has_vmx_tsc_scaling())
2066                         vmcs_write64(TSC_MULTIPLIER,
2067                                      vcpu->arch.tsc_scaling_ratio);
2068
2069                 vmx->loaded_vmcs->cpu = cpu;
2070         }
2071
2072         vmx_vcpu_pi_load(vcpu, cpu);
2073 }
2074
2075 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2076 {
2077         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2078
2079         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2080                 !irq_remapping_cap(IRQ_POSTING_CAP))
2081                 return;
2082
2083         /* Set SN when the vCPU is preempted */
2084         if (vcpu->preempted)
2085                 pi_set_sn(pi_desc);
2086 }
2087
2088 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2089 {
2090         vmx_vcpu_pi_put(vcpu);
2091
2092         __vmx_load_host_state(to_vmx(vcpu));
2093         if (!vmm_exclusive) {
2094                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2095                 vcpu->cpu = -1;
2096                 kvm_cpu_vmxoff();
2097         }
2098 }
2099
2100 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2101 {
2102         ulong cr0;
2103
2104         if (vcpu->fpu_active)
2105                 return;
2106         vcpu->fpu_active = 1;
2107         cr0 = vmcs_readl(GUEST_CR0);
2108         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2109         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2110         vmcs_writel(GUEST_CR0, cr0);
2111         update_exception_bitmap(vcpu);
2112         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2113         if (is_guest_mode(vcpu))
2114                 vcpu->arch.cr0_guest_owned_bits &=
2115                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2116         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2117 }
2118
2119 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2120
2121 /*
2122  * Return the cr0 value that a nested guest would read. This is a combination
2123  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2124  * its hypervisor (cr0_read_shadow).
2125  */
2126 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2127 {
2128         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2129                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2130 }
2131 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2132 {
2133         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2134                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2135 }
2136
2137 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2138 {
2139         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2140          * set this *before* calling this function.
2141          */
2142         vmx_decache_cr0_guest_bits(vcpu);
2143         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2144         update_exception_bitmap(vcpu);
2145         vcpu->arch.cr0_guest_owned_bits = 0;
2146         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2147         if (is_guest_mode(vcpu)) {
2148                 /*
2149                  * L1's specified read shadow might not contain the TS bit,
2150                  * so now that we turned on shadowing of this bit, we need to
2151                  * set this bit of the shadow. Like in nested_vmx_run we need
2152                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2153                  * up-to-date here because we just decached cr0.TS (and we'll
2154                  * only update vmcs12->guest_cr0 on nested exit).
2155                  */
2156                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2157                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2158                         (vcpu->arch.cr0 & X86_CR0_TS);
2159                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2160         } else
2161                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2162 }
2163
2164 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2165 {
2166         unsigned long rflags, save_rflags;
2167
2168         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2169                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2170                 rflags = vmcs_readl(GUEST_RFLAGS);
2171                 if (to_vmx(vcpu)->rmode.vm86_active) {
2172                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2173                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2174                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2175                 }
2176                 to_vmx(vcpu)->rflags = rflags;
2177         }
2178         return to_vmx(vcpu)->rflags;
2179 }
2180
2181 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2182 {
2183         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2184         to_vmx(vcpu)->rflags = rflags;
2185         if (to_vmx(vcpu)->rmode.vm86_active) {
2186                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2187                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2188         }
2189         vmcs_writel(GUEST_RFLAGS, rflags);
2190 }
2191
2192 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2193 {
2194         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2195         int ret = 0;
2196
2197         if (interruptibility & GUEST_INTR_STATE_STI)
2198                 ret |= KVM_X86_SHADOW_INT_STI;
2199         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2200                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2201
2202         return ret;
2203 }
2204
2205 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2206 {
2207         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2208         u32 interruptibility = interruptibility_old;
2209
2210         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2211
2212         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2213                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2214         else if (mask & KVM_X86_SHADOW_INT_STI)
2215                 interruptibility |= GUEST_INTR_STATE_STI;
2216
2217         if ((interruptibility != interruptibility_old))
2218                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2219 }
2220
2221 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2222 {
2223         unsigned long rip;
2224
2225         rip = kvm_rip_read(vcpu);
2226         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2227         kvm_rip_write(vcpu, rip);
2228
2229         /* skipping an emulated instruction also counts */
2230         vmx_set_interrupt_shadow(vcpu, 0);
2231 }
2232
2233 /*
2234  * KVM wants to inject page-faults which it got to the guest. This function
2235  * checks whether in a nested guest, we need to inject them to L1 or L2.
2236  */
2237 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2238 {
2239         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2240
2241         if (!(vmcs12->exception_bitmap & (1u << nr)))
2242                 return 0;
2243
2244         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2245                           vmcs_read32(VM_EXIT_INTR_INFO),
2246                           vmcs_readl(EXIT_QUALIFICATION));
2247         return 1;
2248 }
2249
2250 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2251                                 bool has_error_code, u32 error_code,
2252                                 bool reinject)
2253 {
2254         struct vcpu_vmx *vmx = to_vmx(vcpu);
2255         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2256
2257         if (!reinject && is_guest_mode(vcpu) &&
2258             nested_vmx_check_exception(vcpu, nr))
2259                 return;
2260
2261         if (has_error_code) {
2262                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2263                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2264         }
2265
2266         if (vmx->rmode.vm86_active) {
2267                 int inc_eip = 0;
2268                 if (kvm_exception_is_soft(nr))
2269                         inc_eip = vcpu->arch.event_exit_inst_len;
2270                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2271                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2272                 return;
2273         }
2274
2275         if (kvm_exception_is_soft(nr)) {
2276                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2277                              vmx->vcpu.arch.event_exit_inst_len);
2278                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2279         } else
2280                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2281
2282         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2283 }
2284
2285 static bool vmx_rdtscp_supported(void)
2286 {
2287         return cpu_has_vmx_rdtscp();
2288 }
2289
2290 static bool vmx_invpcid_supported(void)
2291 {
2292         return cpu_has_vmx_invpcid() && enable_ept;
2293 }
2294
2295 /*
2296  * Swap MSR entry in host/guest MSR entry array.
2297  */
2298 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2299 {
2300         struct shared_msr_entry tmp;
2301
2302         tmp = vmx->guest_msrs[to];
2303         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2304         vmx->guest_msrs[from] = tmp;
2305 }
2306
2307 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2308 {
2309         unsigned long *msr_bitmap;
2310
2311         if (is_guest_mode(vcpu))
2312                 msr_bitmap = vmx_msr_bitmap_nested;
2313         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2314                 if (is_long_mode(vcpu))
2315                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2316                 else
2317                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2318         } else {
2319                 if (is_long_mode(vcpu))
2320                         msr_bitmap = vmx_msr_bitmap_longmode;
2321                 else
2322                         msr_bitmap = vmx_msr_bitmap_legacy;
2323         }
2324
2325         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2326 }
2327
2328 /*
2329  * Set up the vmcs to automatically save and restore system
2330  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2331  * mode, as fiddling with msrs is very expensive.
2332  */
2333 static void setup_msrs(struct vcpu_vmx *vmx)
2334 {
2335         int save_nmsrs, index;
2336
2337         save_nmsrs = 0;
2338 #ifdef CONFIG_X86_64
2339         if (is_long_mode(&vmx->vcpu)) {
2340                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2341                 if (index >= 0)
2342                         move_msr_up(vmx, index, save_nmsrs++);
2343                 index = __find_msr_index(vmx, MSR_LSTAR);
2344                 if (index >= 0)
2345                         move_msr_up(vmx, index, save_nmsrs++);
2346                 index = __find_msr_index(vmx, MSR_CSTAR);
2347                 if (index >= 0)
2348                         move_msr_up(vmx, index, save_nmsrs++);
2349                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2350                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2351                         move_msr_up(vmx, index, save_nmsrs++);
2352                 /*
2353                  * MSR_STAR is only needed on long mode guests, and only
2354                  * if efer.sce is enabled.
2355                  */
2356                 index = __find_msr_index(vmx, MSR_STAR);
2357                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2358                         move_msr_up(vmx, index, save_nmsrs++);
2359         }
2360 #endif
2361         index = __find_msr_index(vmx, MSR_EFER);
2362         if (index >= 0 && update_transition_efer(vmx, index))
2363                 move_msr_up(vmx, index, save_nmsrs++);
2364
2365         vmx->save_nmsrs = save_nmsrs;
2366
2367         if (cpu_has_vmx_msr_bitmap())
2368                 vmx_set_msr_bitmap(&vmx->vcpu);
2369 }
2370
2371 /*
2372  * reads and returns guest's timestamp counter "register"
2373  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2374  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2375  */
2376 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2377 {
2378         u64 host_tsc, tsc_offset;
2379
2380         host_tsc = rdtsc();
2381         tsc_offset = vmcs_read64(TSC_OFFSET);
2382         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2383 }
2384
2385 /*
2386  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2387  * counter, even if a nested guest (L2) is currently running.
2388  */
2389 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2390 {
2391         u64 tsc_offset;
2392
2393         tsc_offset = is_guest_mode(vcpu) ?
2394                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2395                 vmcs_read64(TSC_OFFSET);
2396         return host_tsc + tsc_offset;
2397 }
2398
2399 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2400 {
2401         return vmcs_read64(TSC_OFFSET);
2402 }
2403
2404 /*
2405  * writes 'offset' into guest's timestamp counter offset register
2406  */
2407 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2408 {
2409         if (is_guest_mode(vcpu)) {
2410                 /*
2411                  * We're here if L1 chose not to trap WRMSR to TSC. According
2412                  * to the spec, this should set L1's TSC; The offset that L1
2413                  * set for L2 remains unchanged, and still needs to be added
2414                  * to the newly set TSC to get L2's TSC.
2415                  */
2416                 struct vmcs12 *vmcs12;
2417                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2418                 /* recalculate vmcs02.TSC_OFFSET: */
2419                 vmcs12 = get_vmcs12(vcpu);
2420                 vmcs_write64(TSC_OFFSET, offset +
2421                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2422                          vmcs12->tsc_offset : 0));
2423         } else {
2424                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2425                                            vmcs_read64(TSC_OFFSET), offset);
2426                 vmcs_write64(TSC_OFFSET, offset);
2427         }
2428 }
2429
2430 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2431 {
2432         u64 offset = vmcs_read64(TSC_OFFSET);
2433
2434         vmcs_write64(TSC_OFFSET, offset + adjustment);
2435         if (is_guest_mode(vcpu)) {
2436                 /* Even when running L2, the adjustment needs to apply to L1 */
2437                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2438         } else
2439                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2440                                            offset + adjustment);
2441 }
2442
2443 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2444 {
2445         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2446         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2447 }
2448
2449 /*
2450  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2451  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2452  * all guests if the "nested" module option is off, and can also be disabled
2453  * for a single guest by disabling its VMX cpuid bit.
2454  */
2455 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2456 {
2457         return nested && guest_cpuid_has_vmx(vcpu);
2458 }
2459
2460 /*
2461  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2462  * returned for the various VMX controls MSRs when nested VMX is enabled.
2463  * The same values should also be used to verify that vmcs12 control fields are
2464  * valid during nested entry from L1 to L2.
2465  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2466  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2467  * bit in the high half is on if the corresponding bit in the control field
2468  * may be on. See also vmx_control_verify().
2469  */
2470 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2471 {
2472         /*
2473          * Note that as a general rule, the high half of the MSRs (bits in
2474          * the control fields which may be 1) should be initialized by the
2475          * intersection of the underlying hardware's MSR (i.e., features which
2476          * can be supported) and the list of features we want to expose -
2477          * because they are known to be properly supported in our code.
2478          * Also, usually, the low half of the MSRs (bits which must be 1) can
2479          * be set to 0, meaning that L1 may turn off any of these bits. The
2480          * reason is that if one of these bits is necessary, it will appear
2481          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2482          * fields of vmcs01 and vmcs02, will turn these bits off - and
2483          * nested_vmx_exit_handled() will not pass related exits to L1.
2484          * These rules have exceptions below.
2485          */
2486
2487         /* pin-based controls */
2488         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2489                 vmx->nested.nested_vmx_pinbased_ctls_low,
2490                 vmx->nested.nested_vmx_pinbased_ctls_high);
2491         vmx->nested.nested_vmx_pinbased_ctls_low |=
2492                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2493         vmx->nested.nested_vmx_pinbased_ctls_high &=
2494                 PIN_BASED_EXT_INTR_MASK |
2495                 PIN_BASED_NMI_EXITING |
2496                 PIN_BASED_VIRTUAL_NMIS;
2497         vmx->nested.nested_vmx_pinbased_ctls_high |=
2498                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2499                 PIN_BASED_VMX_PREEMPTION_TIMER;
2500         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2501                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2502                         PIN_BASED_POSTED_INTR;
2503
2504         /* exit controls */
2505         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2506                 vmx->nested.nested_vmx_exit_ctls_low,
2507                 vmx->nested.nested_vmx_exit_ctls_high);
2508         vmx->nested.nested_vmx_exit_ctls_low =
2509                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2510
2511         vmx->nested.nested_vmx_exit_ctls_high &=
2512 #ifdef CONFIG_X86_64
2513                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2514 #endif
2515                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2516         vmx->nested.nested_vmx_exit_ctls_high |=
2517                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2518                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2519                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2520
2521         if (vmx_mpx_supported())
2522                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2523
2524         /* We support free control of debug control saving. */
2525         vmx->nested.nested_vmx_true_exit_ctls_low =
2526                 vmx->nested.nested_vmx_exit_ctls_low &
2527                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2528
2529         /* entry controls */
2530         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2531                 vmx->nested.nested_vmx_entry_ctls_low,
2532                 vmx->nested.nested_vmx_entry_ctls_high);
2533         vmx->nested.nested_vmx_entry_ctls_low =
2534                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2535         vmx->nested.nested_vmx_entry_ctls_high &=
2536 #ifdef CONFIG_X86_64
2537                 VM_ENTRY_IA32E_MODE |
2538 #endif
2539                 VM_ENTRY_LOAD_IA32_PAT;
2540         vmx->nested.nested_vmx_entry_ctls_high |=
2541                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2542         if (vmx_mpx_supported())
2543                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2544
2545         /* We support free control of debug control loading. */
2546         vmx->nested.nested_vmx_true_entry_ctls_low =
2547                 vmx->nested.nested_vmx_entry_ctls_low &
2548                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2549
2550         /* cpu-based controls */
2551         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2552                 vmx->nested.nested_vmx_procbased_ctls_low,
2553                 vmx->nested.nested_vmx_procbased_ctls_high);
2554         vmx->nested.nested_vmx_procbased_ctls_low =
2555                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2556         vmx->nested.nested_vmx_procbased_ctls_high &=
2557                 CPU_BASED_VIRTUAL_INTR_PENDING |
2558                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2559                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2560                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2561                 CPU_BASED_CR3_STORE_EXITING |
2562 #ifdef CONFIG_X86_64
2563                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2564 #endif
2565                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2566                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2567                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2568                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2569                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2570         /*
2571          * We can allow some features even when not supported by the
2572          * hardware. For example, L1 can specify an MSR bitmap - and we
2573          * can use it to avoid exits to L1 - even when L0 runs L2
2574          * without MSR bitmaps.
2575          */
2576         vmx->nested.nested_vmx_procbased_ctls_high |=
2577                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2578                 CPU_BASED_USE_MSR_BITMAPS;
2579
2580         /* We support free control of CR3 access interception. */
2581         vmx->nested.nested_vmx_true_procbased_ctls_low =
2582                 vmx->nested.nested_vmx_procbased_ctls_low &
2583                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2584
2585         /* secondary cpu-based controls */
2586         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2587                 vmx->nested.nested_vmx_secondary_ctls_low,
2588                 vmx->nested.nested_vmx_secondary_ctls_high);
2589         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2590         vmx->nested.nested_vmx_secondary_ctls_high &=
2591                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2592                 SECONDARY_EXEC_RDTSCP |
2593                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2594                 SECONDARY_EXEC_ENABLE_VPID |
2595                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2596                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2597                 SECONDARY_EXEC_WBINVD_EXITING |
2598                 SECONDARY_EXEC_XSAVES |
2599                 SECONDARY_EXEC_PCOMMIT;
2600
2601         if (enable_ept) {
2602                 /* nested EPT: emulate EPT also to L1 */
2603                 vmx->nested.nested_vmx_secondary_ctls_high |=
2604                         SECONDARY_EXEC_ENABLE_EPT;
2605                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2606                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2607                          VMX_EPT_INVEPT_BIT;
2608                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2609                 /*
2610                  * For nested guests, we don't do anything specific
2611                  * for single context invalidation. Hence, only advertise
2612                  * support for global context invalidation.
2613                  */
2614                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2615         } else
2616                 vmx->nested.nested_vmx_ept_caps = 0;
2617
2618         if (enable_vpid)
2619                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2620                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2621         else
2622                 vmx->nested.nested_vmx_vpid_caps = 0;
2623
2624         if (enable_unrestricted_guest)
2625                 vmx->nested.nested_vmx_secondary_ctls_high |=
2626                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2627
2628         /* miscellaneous data */
2629         rdmsr(MSR_IA32_VMX_MISC,
2630                 vmx->nested.nested_vmx_misc_low,
2631                 vmx->nested.nested_vmx_misc_high);
2632         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2633         vmx->nested.nested_vmx_misc_low |=
2634                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2635                 VMX_MISC_ACTIVITY_HLT;
2636         vmx->nested.nested_vmx_misc_high = 0;
2637 }
2638
2639 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2640 {
2641         /*
2642          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2643          */
2644         return ((control & high) | low) == control;
2645 }
2646
2647 static inline u64 vmx_control_msr(u32 low, u32 high)
2648 {
2649         return low | ((u64)high << 32);
2650 }
2651
2652 /* Returns 0 on success, non-0 otherwise. */
2653 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2654 {
2655         struct vcpu_vmx *vmx = to_vmx(vcpu);
2656
2657         switch (msr_index) {
2658         case MSR_IA32_VMX_BASIC:
2659                 /*
2660                  * This MSR reports some information about VMX support. We
2661                  * should return information about the VMX we emulate for the
2662                  * guest, and the VMCS structure we give it - not about the
2663                  * VMX support of the underlying hardware.
2664                  */
2665                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2666                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2667                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2668                 break;
2669         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2670         case MSR_IA32_VMX_PINBASED_CTLS:
2671                 *pdata = vmx_control_msr(
2672                         vmx->nested.nested_vmx_pinbased_ctls_low,
2673                         vmx->nested.nested_vmx_pinbased_ctls_high);
2674                 break;
2675         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2676                 *pdata = vmx_control_msr(
2677                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2678                         vmx->nested.nested_vmx_procbased_ctls_high);
2679                 break;
2680         case MSR_IA32_VMX_PROCBASED_CTLS:
2681                 *pdata = vmx_control_msr(
2682                         vmx->nested.nested_vmx_procbased_ctls_low,
2683                         vmx->nested.nested_vmx_procbased_ctls_high);
2684                 break;
2685         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2686                 *pdata = vmx_control_msr(
2687                         vmx->nested.nested_vmx_true_exit_ctls_low,
2688                         vmx->nested.nested_vmx_exit_ctls_high);
2689                 break;
2690         case MSR_IA32_VMX_EXIT_CTLS:
2691                 *pdata = vmx_control_msr(
2692                         vmx->nested.nested_vmx_exit_ctls_low,
2693                         vmx->nested.nested_vmx_exit_ctls_high);
2694                 break;
2695         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2696                 *pdata = vmx_control_msr(
2697                         vmx->nested.nested_vmx_true_entry_ctls_low,
2698                         vmx->nested.nested_vmx_entry_ctls_high);
2699                 break;
2700         case MSR_IA32_VMX_ENTRY_CTLS:
2701                 *pdata = vmx_control_msr(
2702                         vmx->nested.nested_vmx_entry_ctls_low,
2703                         vmx->nested.nested_vmx_entry_ctls_high);
2704                 break;
2705         case MSR_IA32_VMX_MISC:
2706                 *pdata = vmx_control_msr(
2707                         vmx->nested.nested_vmx_misc_low,
2708                         vmx->nested.nested_vmx_misc_high);
2709                 break;
2710         /*
2711          * These MSRs specify bits which the guest must keep fixed (on or off)
2712          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2713          * We picked the standard core2 setting.
2714          */
2715 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2716 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2717         case MSR_IA32_VMX_CR0_FIXED0:
2718                 *pdata = VMXON_CR0_ALWAYSON;
2719                 break;
2720         case MSR_IA32_VMX_CR0_FIXED1:
2721                 *pdata = -1ULL;
2722                 break;
2723         case MSR_IA32_VMX_CR4_FIXED0:
2724                 *pdata = VMXON_CR4_ALWAYSON;
2725                 break;
2726         case MSR_IA32_VMX_CR4_FIXED1:
2727                 *pdata = -1ULL;
2728                 break;
2729         case MSR_IA32_VMX_VMCS_ENUM:
2730                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2731                 break;
2732         case MSR_IA32_VMX_PROCBASED_CTLS2:
2733                 *pdata = vmx_control_msr(
2734                         vmx->nested.nested_vmx_secondary_ctls_low,
2735                         vmx->nested.nested_vmx_secondary_ctls_high);
2736                 break;
2737         case MSR_IA32_VMX_EPT_VPID_CAP:
2738                 /* Currently, no nested vpid support */
2739                 *pdata = vmx->nested.nested_vmx_ept_caps |
2740                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2741                 break;
2742         default:
2743                 return 1;
2744         }
2745
2746         return 0;
2747 }
2748
2749 /*
2750  * Reads an msr value (of 'msr_index') into 'pdata'.
2751  * Returns 0 on success, non-0 otherwise.
2752  * Assumes vcpu_load() was already called.
2753  */
2754 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2755 {
2756         struct shared_msr_entry *msr;
2757
2758         switch (msr_info->index) {
2759 #ifdef CONFIG_X86_64
2760         case MSR_FS_BASE:
2761                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2762                 break;
2763         case MSR_GS_BASE:
2764                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2765                 break;
2766         case MSR_KERNEL_GS_BASE:
2767                 vmx_load_host_state(to_vmx(vcpu));
2768                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2769                 break;
2770 #endif
2771         case MSR_EFER:
2772                 return kvm_get_msr_common(vcpu, msr_info);
2773         case MSR_IA32_TSC:
2774                 msr_info->data = guest_read_tsc(vcpu);
2775                 break;
2776         case MSR_IA32_SYSENTER_CS:
2777                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2778                 break;
2779         case MSR_IA32_SYSENTER_EIP:
2780                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2781                 break;
2782         case MSR_IA32_SYSENTER_ESP:
2783                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2784                 break;
2785         case MSR_IA32_BNDCFGS:
2786                 if (!vmx_mpx_supported())
2787                         return 1;
2788                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2789                 break;
2790         case MSR_IA32_FEATURE_CONTROL:
2791                 if (!nested_vmx_allowed(vcpu))
2792                         return 1;
2793                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2794                 break;
2795         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2796                 if (!nested_vmx_allowed(vcpu))
2797                         return 1;
2798                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2799         case MSR_IA32_XSS:
2800                 if (!vmx_xsaves_supported())
2801                         return 1;
2802                 msr_info->data = vcpu->arch.ia32_xss;
2803                 break;
2804         case MSR_TSC_AUX:
2805                 if (!guest_cpuid_has_rdtscp(vcpu))
2806                         return 1;
2807                 /* Otherwise falls through */
2808         default:
2809                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2810                 if (msr) {
2811                         msr_info->data = msr->data;
2812                         break;
2813                 }
2814                 return kvm_get_msr_common(vcpu, msr_info);
2815         }
2816
2817         return 0;
2818 }
2819
2820 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2821
2822 /*
2823  * Writes msr value into into the appropriate "register".
2824  * Returns 0 on success, non-0 otherwise.
2825  * Assumes vcpu_load() was already called.
2826  */
2827 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2828 {
2829         struct vcpu_vmx *vmx = to_vmx(vcpu);
2830         struct shared_msr_entry *msr;
2831         int ret = 0;
2832         u32 msr_index = msr_info->index;
2833         u64 data = msr_info->data;
2834
2835         switch (msr_index) {
2836         case MSR_EFER:
2837                 ret = kvm_set_msr_common(vcpu, msr_info);
2838                 break;
2839 #ifdef CONFIG_X86_64
2840         case MSR_FS_BASE:
2841                 vmx_segment_cache_clear(vmx);
2842                 vmcs_writel(GUEST_FS_BASE, data);
2843                 break;
2844         case MSR_GS_BASE:
2845                 vmx_segment_cache_clear(vmx);
2846                 vmcs_writel(GUEST_GS_BASE, data);
2847                 break;
2848         case MSR_KERNEL_GS_BASE:
2849                 vmx_load_host_state(vmx);
2850                 vmx->msr_guest_kernel_gs_base = data;
2851                 break;
2852 #endif
2853         case MSR_IA32_SYSENTER_CS:
2854                 vmcs_write32(GUEST_SYSENTER_CS, data);
2855                 break;
2856         case MSR_IA32_SYSENTER_EIP:
2857                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2858                 break;
2859         case MSR_IA32_SYSENTER_ESP:
2860                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2861                 break;
2862         case MSR_IA32_BNDCFGS:
2863                 if (!vmx_mpx_supported())
2864                         return 1;
2865                 vmcs_write64(GUEST_BNDCFGS, data);
2866                 break;
2867         case MSR_IA32_TSC:
2868                 kvm_write_tsc(vcpu, msr_info);
2869                 break;
2870         case MSR_IA32_CR_PAT:
2871                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2872                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2873                                 return 1;
2874                         vmcs_write64(GUEST_IA32_PAT, data);
2875                         vcpu->arch.pat = data;
2876                         break;
2877                 }
2878                 ret = kvm_set_msr_common(vcpu, msr_info);
2879                 break;
2880         case MSR_IA32_TSC_ADJUST:
2881                 ret = kvm_set_msr_common(vcpu, msr_info);
2882                 break;
2883         case MSR_IA32_FEATURE_CONTROL:
2884                 if (!nested_vmx_allowed(vcpu) ||
2885                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2886                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2887                         return 1;
2888                 vmx->nested.msr_ia32_feature_control = data;
2889                 if (msr_info->host_initiated && data == 0)
2890                         vmx_leave_nested(vcpu);
2891                 break;
2892         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2893                 return 1; /* they are read-only */
2894         case MSR_IA32_XSS:
2895                 if (!vmx_xsaves_supported())
2896                         return 1;
2897                 /*
2898                  * The only supported bit as of Skylake is bit 8, but
2899                  * it is not supported on KVM.
2900                  */
2901                 if (data != 0)
2902                         return 1;
2903                 vcpu->arch.ia32_xss = data;
2904                 if (vcpu->arch.ia32_xss != host_xss)
2905                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2906                                 vcpu->arch.ia32_xss, host_xss);
2907                 else
2908                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2909                 break;
2910         case MSR_TSC_AUX:
2911                 if (!guest_cpuid_has_rdtscp(vcpu))
2912                         return 1;
2913                 /* Check reserved bit, higher 32 bits should be zero */
2914                 if ((data >> 32) != 0)
2915                         return 1;
2916                 /* Otherwise falls through */
2917         default:
2918                 msr = find_msr_entry(vmx, msr_index);
2919                 if (msr) {
2920                         u64 old_msr_data = msr->data;
2921                         msr->data = data;
2922                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2923                                 preempt_disable();
2924                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2925                                                          msr->mask);
2926                                 preempt_enable();
2927                                 if (ret)
2928                                         msr->data = old_msr_data;
2929                         }
2930                         break;
2931                 }
2932                 ret = kvm_set_msr_common(vcpu, msr_info);
2933         }
2934
2935         return ret;
2936 }
2937
2938 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2939 {
2940         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2941         switch (reg) {
2942         case VCPU_REGS_RSP:
2943                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2944                 break;
2945         case VCPU_REGS_RIP:
2946                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2947                 break;
2948         case VCPU_EXREG_PDPTR:
2949                 if (enable_ept)
2950                         ept_save_pdptrs(vcpu);
2951                 break;
2952         default:
2953                 break;
2954         }
2955 }
2956
2957 static __init int cpu_has_kvm_support(void)
2958 {
2959         return cpu_has_vmx();
2960 }
2961
2962 static __init int vmx_disabled_by_bios(void)
2963 {
2964         u64 msr;
2965
2966         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2967         if (msr & FEATURE_CONTROL_LOCKED) {
2968                 /* launched w/ TXT and VMX disabled */
2969                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2970                         && tboot_enabled())
2971                         return 1;
2972                 /* launched w/o TXT and VMX only enabled w/ TXT */
2973                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2974                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2975                         && !tboot_enabled()) {
2976                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2977                                 "activate TXT before enabling KVM\n");
2978                         return 1;
2979                 }
2980                 /* launched w/o TXT and VMX disabled */
2981                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2982                         && !tboot_enabled())
2983                         return 1;
2984         }
2985
2986         return 0;
2987 }
2988
2989 static void kvm_cpu_vmxon(u64 addr)
2990 {
2991         asm volatile (ASM_VMX_VMXON_RAX
2992                         : : "a"(&addr), "m"(addr)
2993                         : "memory", "cc");
2994 }
2995
2996 static int hardware_enable(void)
2997 {
2998         int cpu = raw_smp_processor_id();
2999         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3000         u64 old, test_bits;
3001
3002         if (cr4_read_shadow() & X86_CR4_VMXE)
3003                 return -EBUSY;
3004
3005         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3006         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3007         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3008
3009         /*
3010          * Now we can enable the vmclear operation in kdump
3011          * since the loaded_vmcss_on_cpu list on this cpu
3012          * has been initialized.
3013          *
3014          * Though the cpu is not in VMX operation now, there
3015          * is no problem to enable the vmclear operation
3016          * for the loaded_vmcss_on_cpu list is empty!
3017          */
3018         crash_enable_local_vmclear(cpu);
3019
3020         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3021
3022         test_bits = FEATURE_CONTROL_LOCKED;
3023         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3024         if (tboot_enabled())
3025                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3026
3027         if ((old & test_bits) != test_bits) {
3028                 /* enable and lock */
3029                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3030         }
3031         cr4_set_bits(X86_CR4_VMXE);
3032
3033         if (vmm_exclusive) {
3034                 kvm_cpu_vmxon(phys_addr);
3035                 ept_sync_global();
3036         }
3037
3038         native_store_gdt(this_cpu_ptr(&host_gdt));
3039
3040         return 0;
3041 }
3042
3043 static void vmclear_local_loaded_vmcss(void)
3044 {
3045         int cpu = raw_smp_processor_id();
3046         struct loaded_vmcs *v, *n;
3047
3048         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3049                                  loaded_vmcss_on_cpu_link)
3050                 __loaded_vmcs_clear(v);
3051 }
3052
3053
3054 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3055  * tricks.
3056  */
3057 static void kvm_cpu_vmxoff(void)
3058 {
3059         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3060 }
3061
3062 static void hardware_disable(void)
3063 {
3064         if (vmm_exclusive) {
3065                 vmclear_local_loaded_vmcss();
3066                 kvm_cpu_vmxoff();
3067         }
3068         cr4_clear_bits(X86_CR4_VMXE);
3069 }
3070
3071 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3072                                       u32 msr, u32 *result)
3073 {
3074         u32 vmx_msr_low, vmx_msr_high;
3075         u32 ctl = ctl_min | ctl_opt;
3076
3077         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3078
3079         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3080         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3081
3082         /* Ensure minimum (required) set of control bits are supported. */
3083         if (ctl_min & ~ctl)
3084                 return -EIO;
3085
3086         *result = ctl;
3087         return 0;
3088 }
3089
3090 static __init bool allow_1_setting(u32 msr, u32 ctl)
3091 {
3092         u32 vmx_msr_low, vmx_msr_high;
3093
3094         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3095         return vmx_msr_high & ctl;
3096 }
3097
3098 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3099 {
3100         u32 vmx_msr_low, vmx_msr_high;
3101         u32 min, opt, min2, opt2;
3102         u32 _pin_based_exec_control = 0;
3103         u32 _cpu_based_exec_control = 0;
3104         u32 _cpu_based_2nd_exec_control = 0;
3105         u32 _vmexit_control = 0;
3106         u32 _vmentry_control = 0;
3107
3108         min = CPU_BASED_HLT_EXITING |
3109 #ifdef CONFIG_X86_64
3110               CPU_BASED_CR8_LOAD_EXITING |
3111               CPU_BASED_CR8_STORE_EXITING |
3112 #endif
3113               CPU_BASED_CR3_LOAD_EXITING |
3114               CPU_BASED_CR3_STORE_EXITING |
3115               CPU_BASED_USE_IO_BITMAPS |
3116               CPU_BASED_MOV_DR_EXITING |
3117               CPU_BASED_USE_TSC_OFFSETING |
3118               CPU_BASED_MWAIT_EXITING |
3119               CPU_BASED_MONITOR_EXITING |
3120               CPU_BASED_INVLPG_EXITING |
3121               CPU_BASED_RDPMC_EXITING;
3122
3123         opt = CPU_BASED_TPR_SHADOW |
3124               CPU_BASED_USE_MSR_BITMAPS |
3125               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3126         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3127                                 &_cpu_based_exec_control) < 0)
3128                 return -EIO;
3129 #ifdef CONFIG_X86_64
3130         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3131                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3132                                            ~CPU_BASED_CR8_STORE_EXITING;
3133 #endif
3134         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3135                 min2 = 0;
3136                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3137                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3138                         SECONDARY_EXEC_WBINVD_EXITING |
3139                         SECONDARY_EXEC_ENABLE_VPID |
3140                         SECONDARY_EXEC_ENABLE_EPT |
3141                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3142                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3143                         SECONDARY_EXEC_RDTSCP |
3144                         SECONDARY_EXEC_ENABLE_INVPCID |
3145                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3146                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3147                         SECONDARY_EXEC_SHADOW_VMCS |
3148                         SECONDARY_EXEC_XSAVES |
3149                         SECONDARY_EXEC_ENABLE_PML |
3150                         SECONDARY_EXEC_PCOMMIT |
3151                         SECONDARY_EXEC_TSC_SCALING;
3152                 if (adjust_vmx_controls(min2, opt2,
3153                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3154                                         &_cpu_based_2nd_exec_control) < 0)
3155                         return -EIO;
3156         }
3157 #ifndef CONFIG_X86_64
3158         if (!(_cpu_based_2nd_exec_control &
3159                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3160                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3161 #endif
3162
3163         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3164                 _cpu_based_2nd_exec_control &= ~(
3165                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3166                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3167                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3168
3169         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3170                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3171                    enabled */
3172                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3173                                              CPU_BASED_CR3_STORE_EXITING |
3174                                              CPU_BASED_INVLPG_EXITING);
3175                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3176                       vmx_capability.ept, vmx_capability.vpid);
3177         }
3178
3179         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3180 #ifdef CONFIG_X86_64
3181         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3182 #endif
3183         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3184                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3185         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3186                                 &_vmexit_control) < 0)
3187                 return -EIO;
3188
3189         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3190         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3191         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3192                                 &_pin_based_exec_control) < 0)
3193                 return -EIO;
3194
3195         if (!(_cpu_based_2nd_exec_control &
3196                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3197                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3198                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3199
3200         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3201         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3202         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3203                                 &_vmentry_control) < 0)
3204                 return -EIO;
3205
3206         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3207
3208         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3209         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3210                 return -EIO;
3211
3212 #ifdef CONFIG_X86_64
3213         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3214         if (vmx_msr_high & (1u<<16))
3215                 return -EIO;
3216 #endif
3217
3218         /* Require Write-Back (WB) memory type for VMCS accesses. */
3219         if (((vmx_msr_high >> 18) & 15) != 6)
3220                 return -EIO;
3221
3222         vmcs_conf->size = vmx_msr_high & 0x1fff;
3223         vmcs_conf->order = get_order(vmcs_config.size);
3224         vmcs_conf->revision_id = vmx_msr_low;
3225
3226         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3227         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3228         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3229         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3230         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3231
3232         cpu_has_load_ia32_efer =
3233                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3234                                 VM_ENTRY_LOAD_IA32_EFER)
3235                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3236                                    VM_EXIT_LOAD_IA32_EFER);
3237
3238         cpu_has_load_perf_global_ctrl =
3239                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3240                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3241                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3242                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3243
3244         /*
3245          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3246          * but due to arrata below it can't be used. Workaround is to use
3247          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3248          *
3249          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3250          *
3251          * AAK155             (model 26)
3252          * AAP115             (model 30)
3253          * AAT100             (model 37)
3254          * BC86,AAY89,BD102   (model 44)
3255          * BA97               (model 46)
3256          *
3257          */
3258         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3259                 switch (boot_cpu_data.x86_model) {
3260                 case 26:
3261                 case 30:
3262                 case 37:
3263                 case 44:
3264                 case 46:
3265                         cpu_has_load_perf_global_ctrl = false;
3266                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3267                                         "does not work properly. Using workaround\n");
3268                         break;
3269                 default:
3270                         break;
3271                 }
3272         }
3273
3274         if (cpu_has_xsaves)
3275                 rdmsrl(MSR_IA32_XSS, host_xss);
3276
3277         return 0;
3278 }
3279
3280 static struct vmcs *alloc_vmcs_cpu(int cpu)
3281 {
3282         int node = cpu_to_node(cpu);
3283         struct page *pages;
3284         struct vmcs *vmcs;
3285
3286         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3287         if (!pages)
3288                 return NULL;
3289         vmcs = page_address(pages);
3290         memset(vmcs, 0, vmcs_config.size);
3291         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3292         return vmcs;
3293 }
3294
3295 static struct vmcs *alloc_vmcs(void)
3296 {
3297         return alloc_vmcs_cpu(raw_smp_processor_id());
3298 }
3299
3300 static void free_vmcs(struct vmcs *vmcs)
3301 {
3302         free_pages((unsigned long)vmcs, vmcs_config.order);
3303 }
3304
3305 /*
3306  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3307  */
3308 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3309 {
3310         if (!loaded_vmcs->vmcs)
3311                 return;
3312         loaded_vmcs_clear(loaded_vmcs);
3313         free_vmcs(loaded_vmcs->vmcs);
3314         loaded_vmcs->vmcs = NULL;
3315 }
3316
3317 static void free_kvm_area(void)
3318 {
3319         int cpu;
3320
3321         for_each_possible_cpu(cpu) {
3322                 free_vmcs(per_cpu(vmxarea, cpu));
3323                 per_cpu(vmxarea, cpu) = NULL;
3324         }
3325 }
3326
3327 static void init_vmcs_shadow_fields(void)
3328 {
3329         int i, j;
3330
3331         /* No checks for read only fields yet */
3332
3333         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3334                 switch (shadow_read_write_fields[i]) {
3335                 case GUEST_BNDCFGS:
3336                         if (!vmx_mpx_supported())
3337                                 continue;
3338                         break;
3339                 default:
3340                         break;
3341                 }
3342
3343                 if (j < i)
3344                         shadow_read_write_fields[j] =
3345                                 shadow_read_write_fields[i];
3346                 j++;
3347         }
3348         max_shadow_read_write_fields = j;
3349
3350         /* shadowed fields guest access without vmexit */
3351         for (i = 0; i < max_shadow_read_write_fields; i++) {
3352                 clear_bit(shadow_read_write_fields[i],
3353                           vmx_vmwrite_bitmap);
3354                 clear_bit(shadow_read_write_fields[i],
3355                           vmx_vmread_bitmap);
3356         }
3357         for (i = 0; i < max_shadow_read_only_fields; i++)
3358                 clear_bit(shadow_read_only_fields[i],
3359                           vmx_vmread_bitmap);
3360 }
3361
3362 static __init int alloc_kvm_area(void)
3363 {
3364         int cpu;
3365
3366         for_each_possible_cpu(cpu) {
3367                 struct vmcs *vmcs;
3368
3369                 vmcs = alloc_vmcs_cpu(cpu);
3370                 if (!vmcs) {
3371                         free_kvm_area();
3372                         return -ENOMEM;
3373                 }
3374
3375                 per_cpu(vmxarea, cpu) = vmcs;
3376         }
3377         return 0;
3378 }
3379
3380 static bool emulation_required(struct kvm_vcpu *vcpu)
3381 {
3382         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3383 }
3384
3385 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3386                 struct kvm_segment *save)
3387 {
3388         if (!emulate_invalid_guest_state) {
3389                 /*
3390                  * CS and SS RPL should be equal during guest entry according
3391                  * to VMX spec, but in reality it is not always so. Since vcpu
3392                  * is in the middle of the transition from real mode to
3393                  * protected mode it is safe to assume that RPL 0 is a good
3394                  * default value.
3395                  */
3396                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3397                         save->selector &= ~SEGMENT_RPL_MASK;
3398                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3399                 save->s = 1;
3400         }
3401         vmx_set_segment(vcpu, save, seg);
3402 }
3403
3404 static void enter_pmode(struct kvm_vcpu *vcpu)
3405 {
3406         unsigned long flags;
3407         struct vcpu_vmx *vmx = to_vmx(vcpu);
3408
3409         /*
3410          * Update real mode segment cache. It may be not up-to-date if sement
3411          * register was written while vcpu was in a guest mode.
3412          */
3413         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3414         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3415         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3416         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3417         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3418         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3419
3420         vmx->rmode.vm86_active = 0;
3421
3422         vmx_segment_cache_clear(vmx);
3423
3424         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3425
3426         flags = vmcs_readl(GUEST_RFLAGS);
3427         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3428         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3429         vmcs_writel(GUEST_RFLAGS, flags);
3430
3431         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3432                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3433
3434         update_exception_bitmap(vcpu);
3435
3436         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3437         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3438         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3439         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3440         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3441         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3442 }
3443
3444 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3445 {
3446         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3447         struct kvm_segment var = *save;
3448
3449         var.dpl = 0x3;
3450         if (seg == VCPU_SREG_CS)
3451                 var.type = 0x3;
3452
3453         if (!emulate_invalid_guest_state) {
3454                 var.selector = var.base >> 4;
3455                 var.base = var.base & 0xffff0;
3456                 var.limit = 0xffff;
3457                 var.g = 0;
3458                 var.db = 0;
3459                 var.present = 1;
3460                 var.s = 1;
3461                 var.l = 0;
3462                 var.unusable = 0;
3463                 var.type = 0x3;
3464                 var.avl = 0;
3465                 if (save->base & 0xf)
3466                         printk_once(KERN_WARNING "kvm: segment base is not "
3467                                         "paragraph aligned when entering "
3468                                         "protected mode (seg=%d)", seg);
3469         }
3470
3471         vmcs_write16(sf->selector, var.selector);
3472         vmcs_write32(sf->base, var.base);
3473         vmcs_write32(sf->limit, var.limit);
3474         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3475 }
3476
3477 static void enter_rmode(struct kvm_vcpu *vcpu)
3478 {
3479         unsigned long flags;
3480         struct vcpu_vmx *vmx = to_vmx(vcpu);
3481
3482         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3483         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3484         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3485         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3486         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3487         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3488         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3489
3490         vmx->rmode.vm86_active = 1;
3491
3492         /*
3493          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3494          * vcpu. Warn the user that an update is overdue.
3495          */
3496         if (!vcpu->kvm->arch.tss_addr)
3497                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3498                              "called before entering vcpu\n");
3499
3500         vmx_segment_cache_clear(vmx);
3501
3502         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3503         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3504         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3505
3506         flags = vmcs_readl(GUEST_RFLAGS);
3507         vmx->rmode.save_rflags = flags;
3508
3509         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3510
3511         vmcs_writel(GUEST_RFLAGS, flags);
3512         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3513         update_exception_bitmap(vcpu);
3514
3515         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3516         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3517         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3518         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3519         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3520         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3521
3522         kvm_mmu_reset_context(vcpu);
3523 }
3524
3525 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3526 {
3527         struct vcpu_vmx *vmx = to_vmx(vcpu);
3528         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3529
3530         if (!msr)
3531                 return;
3532
3533         /*
3534          * Force kernel_gs_base reloading before EFER changes, as control
3535          * of this msr depends on is_long_mode().
3536          */
3537         vmx_load_host_state(to_vmx(vcpu));
3538         vcpu->arch.efer = efer;
3539         if (efer & EFER_LMA) {
3540                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3541                 msr->data = efer;
3542         } else {
3543                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3544
3545                 msr->data = efer & ~EFER_LME;
3546         }
3547         setup_msrs(vmx);
3548 }
3549
3550 #ifdef CONFIG_X86_64
3551
3552 static void enter_lmode(struct kvm_vcpu *vcpu)
3553 {
3554         u32 guest_tr_ar;
3555
3556         vmx_segment_cache_clear(to_vmx(vcpu));
3557
3558         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3559         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3560                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3561                                      __func__);
3562                 vmcs_write32(GUEST_TR_AR_BYTES,
3563                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3564                              | VMX_AR_TYPE_BUSY_64_TSS);
3565         }
3566         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3567 }
3568
3569 static void exit_lmode(struct kvm_vcpu *vcpu)
3570 {
3571         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3572         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3573 }
3574
3575 #endif
3576
3577 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3578 {
3579         vpid_sync_context(vpid);
3580         if (enable_ept) {
3581                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3582                         return;
3583                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3584         }
3585 }
3586
3587 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3588 {
3589         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3590 }
3591
3592 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3593 {
3594         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3595
3596         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3597         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3598 }
3599
3600 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3601 {
3602         if (enable_ept && is_paging(vcpu))
3603                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3604         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3605 }
3606
3607 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3608 {
3609         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3610
3611         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3612         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3613 }
3614
3615 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3616 {
3617         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3618
3619         if (!test_bit(VCPU_EXREG_PDPTR,
3620                       (unsigned long *)&vcpu->arch.regs_dirty))
3621                 return;
3622
3623         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3624                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3625                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3626                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3627                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3628         }
3629 }
3630
3631 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3632 {
3633         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3634
3635         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3636                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3637                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3638                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3639                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3640         }
3641
3642         __set_bit(VCPU_EXREG_PDPTR,
3643                   (unsigned long *)&vcpu->arch.regs_avail);
3644         __set_bit(VCPU_EXREG_PDPTR,
3645                   (unsigned long *)&vcpu->arch.regs_dirty);
3646 }
3647
3648 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3649
3650 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3651                                         unsigned long cr0,
3652                                         struct kvm_vcpu *vcpu)
3653 {
3654         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3655                 vmx_decache_cr3(vcpu);
3656         if (!(cr0 & X86_CR0_PG)) {
3657                 /* From paging/starting to nonpaging */
3658                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3659                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3660                              (CPU_BASED_CR3_LOAD_EXITING |
3661                               CPU_BASED_CR3_STORE_EXITING));
3662                 vcpu->arch.cr0 = cr0;
3663                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3664         } else if (!is_paging(vcpu)) {
3665                 /* From nonpaging to paging */
3666                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3667                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3668                              ~(CPU_BASED_CR3_LOAD_EXITING |
3669                                CPU_BASED_CR3_STORE_EXITING));
3670                 vcpu->arch.cr0 = cr0;
3671                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3672         }
3673
3674         if (!(cr0 & X86_CR0_WP))
3675                 *hw_cr0 &= ~X86_CR0_WP;
3676 }
3677
3678 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3679 {
3680         struct vcpu_vmx *vmx = to_vmx(vcpu);
3681         unsigned long hw_cr0;
3682
3683         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3684         if (enable_unrestricted_guest)
3685                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3686         else {
3687                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3688
3689                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3690                         enter_pmode(vcpu);
3691
3692                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3693                         enter_rmode(vcpu);
3694         }
3695
3696 #ifdef CONFIG_X86_64
3697         if (vcpu->arch.efer & EFER_LME) {
3698                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3699                         enter_lmode(vcpu);
3700                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3701                         exit_lmode(vcpu);
3702         }
3703 #endif
3704
3705         if (enable_ept)
3706                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3707
3708         if (!vcpu->fpu_active)
3709                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3710
3711         vmcs_writel(CR0_READ_SHADOW, cr0);
3712         vmcs_writel(GUEST_CR0, hw_cr0);
3713         vcpu->arch.cr0 = cr0;
3714
3715         /* depends on vcpu->arch.cr0 to be set to a new value */
3716         vmx->emulation_required = emulation_required(vcpu);
3717 }
3718
3719 static u64 construct_eptp(unsigned long root_hpa)
3720 {
3721         u64 eptp;
3722
3723         /* TODO write the value reading from MSR */
3724         eptp = VMX_EPT_DEFAULT_MT |
3725                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3726         if (enable_ept_ad_bits)
3727                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3728         eptp |= (root_hpa & PAGE_MASK);
3729
3730         return eptp;
3731 }
3732
3733 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3734 {
3735         unsigned long guest_cr3;
3736         u64 eptp;
3737
3738         guest_cr3 = cr3;
3739         if (enable_ept) {
3740                 eptp = construct_eptp(cr3);
3741                 vmcs_write64(EPT_POINTER, eptp);
3742                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3743                         guest_cr3 = kvm_read_cr3(vcpu);
3744                 else
3745                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3746                 ept_load_pdptrs(vcpu);
3747         }
3748
3749         vmx_flush_tlb(vcpu);
3750         vmcs_writel(GUEST_CR3, guest_cr3);
3751 }
3752
3753 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3754 {
3755         /*
3756          * Pass through host's Machine Check Enable value to hw_cr4, which
3757          * is in force while we are in guest mode.  Do not let guests control
3758          * this bit, even if host CR4.MCE == 0.
3759          */
3760         unsigned long hw_cr4 =
3761                 (cr4_read_shadow() & X86_CR4_MCE) |
3762                 (cr4 & ~X86_CR4_MCE) |
3763                 (to_vmx(vcpu)->rmode.vm86_active ?
3764                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3765
3766         if (cr4 & X86_CR4_VMXE) {
3767                 /*
3768                  * To use VMXON (and later other VMX instructions), a guest
3769                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3770                  * So basically the check on whether to allow nested VMX
3771                  * is here.
3772                  */
3773                 if (!nested_vmx_allowed(vcpu))
3774                         return 1;
3775         }
3776         if (to_vmx(vcpu)->nested.vmxon &&
3777             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3778                 return 1;
3779
3780         vcpu->arch.cr4 = cr4;
3781         if (enable_ept) {
3782                 if (!is_paging(vcpu)) {
3783                         hw_cr4 &= ~X86_CR4_PAE;
3784                         hw_cr4 |= X86_CR4_PSE;
3785                 } else if (!(cr4 & X86_CR4_PAE)) {
3786                         hw_cr4 &= ~X86_CR4_PAE;
3787                 }
3788         }
3789
3790         if (!enable_unrestricted_guest && !is_paging(vcpu))
3791                 /*
3792                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3793                  * hardware.  However KVM always uses paging mode without
3794                  * unrestricted guest.
3795                  * To emulate this behavior, SMEP/SMAP needs to be manually
3796                  * disabled when guest switches to non-paging mode.
3797                  */
3798                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3799
3800         vmcs_writel(CR4_READ_SHADOW, cr4);
3801         vmcs_writel(GUEST_CR4, hw_cr4);
3802         return 0;
3803 }
3804
3805 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3806                             struct kvm_segment *var, int seg)
3807 {
3808         struct vcpu_vmx *vmx = to_vmx(vcpu);
3809         u32 ar;
3810
3811         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3812                 *var = vmx->rmode.segs[seg];
3813                 if (seg == VCPU_SREG_TR
3814                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3815                         return;
3816                 var->base = vmx_read_guest_seg_base(vmx, seg);
3817                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3818                 return;
3819         }
3820         var->base = vmx_read_guest_seg_base(vmx, seg);
3821         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3822         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3823         ar = vmx_read_guest_seg_ar(vmx, seg);
3824         var->unusable = (ar >> 16) & 1;
3825         var->type = ar & 15;
3826         var->s = (ar >> 4) & 1;
3827         var->dpl = (ar >> 5) & 3;
3828         /*
3829          * Some userspaces do not preserve unusable property. Since usable
3830          * segment has to be present according to VMX spec we can use present
3831          * property to amend userspace bug by making unusable segment always
3832          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3833          * segment as unusable.
3834          */
3835         var->present = !var->unusable;
3836         var->avl = (ar >> 12) & 1;
3837         var->l = (ar >> 13) & 1;
3838         var->db = (ar >> 14) & 1;
3839         var->g = (ar >> 15) & 1;
3840 }
3841
3842 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3843 {
3844         struct kvm_segment s;
3845
3846         if (to_vmx(vcpu)->rmode.vm86_active) {
3847                 vmx_get_segment(vcpu, &s, seg);
3848                 return s.base;
3849         }
3850         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3851 }
3852
3853 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3854 {
3855         struct vcpu_vmx *vmx = to_vmx(vcpu);
3856
3857         if (unlikely(vmx->rmode.vm86_active))
3858                 return 0;
3859         else {
3860                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3861                 return VMX_AR_DPL(ar);
3862         }
3863 }
3864
3865 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3866 {
3867         u32 ar;
3868
3869         if (var->unusable || !var->present)
3870                 ar = 1 << 16;
3871         else {
3872                 ar = var->type & 15;
3873                 ar |= (var->s & 1) << 4;
3874                 ar |= (var->dpl & 3) << 5;
3875                 ar |= (var->present & 1) << 7;
3876                 ar |= (var->avl & 1) << 12;
3877                 ar |= (var->l & 1) << 13;
3878                 ar |= (var->db & 1) << 14;
3879                 ar |= (var->g & 1) << 15;
3880         }
3881
3882         return ar;
3883 }
3884
3885 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3886                             struct kvm_segment *var, int seg)
3887 {
3888         struct vcpu_vmx *vmx = to_vmx(vcpu);
3889         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3890
3891         vmx_segment_cache_clear(vmx);
3892
3893         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3894                 vmx->rmode.segs[seg] = *var;
3895                 if (seg == VCPU_SREG_TR)
3896                         vmcs_write16(sf->selector, var->selector);
3897                 else if (var->s)
3898                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3899                 goto out;
3900         }
3901
3902         vmcs_writel(sf->base, var->base);
3903         vmcs_write32(sf->limit, var->limit);
3904         vmcs_write16(sf->selector, var->selector);
3905
3906         /*
3907          *   Fix the "Accessed" bit in AR field of segment registers for older
3908          * qemu binaries.
3909          *   IA32 arch specifies that at the time of processor reset the
3910          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3911          * is setting it to 0 in the userland code. This causes invalid guest
3912          * state vmexit when "unrestricted guest" mode is turned on.
3913          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3914          * tree. Newer qemu binaries with that qemu fix would not need this
3915          * kvm hack.
3916          */
3917         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3918                 var->type |= 0x1; /* Accessed */
3919
3920         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3921
3922 out:
3923         vmx->emulation_required = emulation_required(vcpu);
3924 }
3925
3926 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3927 {
3928         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3929
3930         *db = (ar >> 14) & 1;
3931         *l = (ar >> 13) & 1;
3932 }
3933
3934 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3935 {
3936         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3937         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3938 }
3939
3940 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3941 {
3942         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3943         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3944 }
3945
3946 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3947 {
3948         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3949         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3950 }
3951
3952 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3953 {
3954         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3955         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3956 }
3957
3958 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3959 {
3960         struct kvm_segment var;
3961         u32 ar;
3962
3963         vmx_get_segment(vcpu, &var, seg);
3964         var.dpl = 0x3;
3965         if (seg == VCPU_SREG_CS)
3966                 var.type = 0x3;
3967         ar = vmx_segment_access_rights(&var);
3968
3969         if (var.base != (var.selector << 4))
3970                 return false;
3971         if (var.limit != 0xffff)
3972                 return false;
3973         if (ar != 0xf3)
3974                 return false;
3975
3976         return true;
3977 }
3978
3979 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3980 {
3981         struct kvm_segment cs;
3982         unsigned int cs_rpl;
3983
3984         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3985         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3986
3987         if (cs.unusable)
3988                 return false;
3989         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3990                 return false;
3991         if (!cs.s)
3992                 return false;
3993         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3994                 if (cs.dpl > cs_rpl)
3995                         return false;
3996         } else {
3997                 if (cs.dpl != cs_rpl)
3998                         return false;
3999         }
4000         if (!cs.present)
4001                 return false;
4002
4003         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4004         return true;
4005 }
4006
4007 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4008 {
4009         struct kvm_segment ss;
4010         unsigned int ss_rpl;
4011
4012         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4013         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4014
4015         if (ss.unusable)
4016                 return true;
4017         if (ss.type != 3 && ss.type != 7)
4018                 return false;
4019         if (!ss.s)
4020                 return false;
4021         if (ss.dpl != ss_rpl) /* DPL != RPL */
4022                 return false;
4023         if (!ss.present)
4024                 return false;
4025
4026         return true;
4027 }
4028
4029 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4030 {
4031         struct kvm_segment var;
4032         unsigned int rpl;
4033
4034         vmx_get_segment(vcpu, &var, seg);
4035         rpl = var.selector & SEGMENT_RPL_MASK;
4036
4037         if (var.unusable)
4038                 return true;
4039         if (!var.s)
4040                 return false;
4041         if (!var.present)
4042                 return false;
4043         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4044                 if (var.dpl < rpl) /* DPL < RPL */
4045                         return false;
4046         }
4047
4048         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4049          * rights flags
4050          */
4051         return true;
4052 }
4053
4054 static bool tr_valid(struct kvm_vcpu *vcpu)
4055 {
4056         struct kvm_segment tr;
4057
4058         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4059
4060         if (tr.unusable)
4061                 return false;
4062         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4063                 return false;
4064         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4065                 return false;
4066         if (!tr.present)
4067                 return false;
4068
4069         return true;
4070 }
4071
4072 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4073 {
4074         struct kvm_segment ldtr;
4075
4076         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4077
4078         if (ldtr.unusable)
4079                 return true;
4080         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4081                 return false;
4082         if (ldtr.type != 2)
4083                 return false;
4084         if (!ldtr.present)
4085                 return false;
4086
4087         return true;
4088 }
4089
4090 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4091 {
4092         struct kvm_segment cs, ss;
4093
4094         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4095         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4096
4097         return ((cs.selector & SEGMENT_RPL_MASK) ==
4098                  (ss.selector & SEGMENT_RPL_MASK));
4099 }
4100
4101 /*
4102  * Check if guest state is valid. Returns true if valid, false if
4103  * not.
4104  * We assume that registers are always usable
4105  */
4106 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4107 {
4108         if (enable_unrestricted_guest)
4109                 return true;
4110
4111         /* real mode guest state checks */
4112         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4113                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4114                         return false;
4115                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4116                         return false;
4117                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4118                         return false;
4119                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4120                         return false;
4121                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4122                         return false;
4123                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4124                         return false;
4125         } else {
4126         /* protected mode guest state checks */
4127                 if (!cs_ss_rpl_check(vcpu))
4128                         return false;
4129                 if (!code_segment_valid(vcpu))
4130                         return false;
4131                 if (!stack_segment_valid(vcpu))
4132                         return false;
4133                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4134                         return false;
4135                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4136                         return false;
4137                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4138                         return false;
4139                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4140                         return false;
4141                 if (!tr_valid(vcpu))
4142                         return false;
4143                 if (!ldtr_valid(vcpu))
4144                         return false;
4145         }
4146         /* TODO:
4147          * - Add checks on RIP
4148          * - Add checks on RFLAGS
4149          */
4150
4151         return true;
4152 }
4153
4154 static int init_rmode_tss(struct kvm *kvm)
4155 {
4156         gfn_t fn;
4157         u16 data = 0;
4158         int idx, r;
4159
4160         idx = srcu_read_lock(&kvm->srcu);
4161         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4162         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4163         if (r < 0)
4164                 goto out;
4165         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4166         r = kvm_write_guest_page(kvm, fn++, &data,
4167                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4168         if (r < 0)
4169                 goto out;
4170         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4171         if (r < 0)
4172                 goto out;
4173         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4174         if (r < 0)
4175                 goto out;
4176         data = ~0;
4177         r = kvm_write_guest_page(kvm, fn, &data,
4178                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4179                                  sizeof(u8));
4180 out:
4181         srcu_read_unlock(&kvm->srcu, idx);
4182         return r;
4183 }
4184
4185 static int init_rmode_identity_map(struct kvm *kvm)
4186 {
4187         int i, idx, r = 0;
4188         pfn_t identity_map_pfn;
4189         u32 tmp;
4190
4191         if (!enable_ept)
4192                 return 0;
4193
4194         /* Protect kvm->arch.ept_identity_pagetable_done. */
4195         mutex_lock(&kvm->slots_lock);
4196
4197         if (likely(kvm->arch.ept_identity_pagetable_done))
4198                 goto out2;
4199
4200         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4201
4202         r = alloc_identity_pagetable(kvm);
4203         if (r < 0)
4204                 goto out2;
4205
4206         idx = srcu_read_lock(&kvm->srcu);
4207         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4208         if (r < 0)
4209                 goto out;
4210         /* Set up identity-mapping pagetable for EPT in real mode */
4211         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4212                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4213                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4214                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4215                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4216                 if (r < 0)
4217                         goto out;
4218         }
4219         kvm->arch.ept_identity_pagetable_done = true;
4220
4221 out:
4222         srcu_read_unlock(&kvm->srcu, idx);
4223
4224 out2:
4225         mutex_unlock(&kvm->slots_lock);
4226         return r;
4227 }
4228
4229 static void seg_setup(int seg)
4230 {
4231         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4232         unsigned int ar;
4233
4234         vmcs_write16(sf->selector, 0);
4235         vmcs_writel(sf->base, 0);
4236         vmcs_write32(sf->limit, 0xffff);
4237         ar = 0x93;
4238         if (seg == VCPU_SREG_CS)
4239                 ar |= 0x08; /* code segment */
4240
4241         vmcs_write32(sf->ar_bytes, ar);
4242 }
4243
4244 static int alloc_apic_access_page(struct kvm *kvm)
4245 {
4246         struct page *page;
4247         int r = 0;
4248
4249         mutex_lock(&kvm->slots_lock);
4250         if (kvm->arch.apic_access_page_done)
4251                 goto out;
4252         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4253                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4254         if (r)
4255                 goto out;
4256
4257         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4258         if (is_error_page(page)) {
4259                 r = -EFAULT;
4260                 goto out;
4261         }
4262
4263         /*
4264          * Do not pin the page in memory, so that memory hot-unplug
4265          * is able to migrate it.
4266          */
4267         put_page(page);
4268         kvm->arch.apic_access_page_done = true;
4269 out:
4270         mutex_unlock(&kvm->slots_lock);
4271         return r;
4272 }
4273
4274 static int alloc_identity_pagetable(struct kvm *kvm)
4275 {
4276         /* Called with kvm->slots_lock held. */
4277
4278         int r = 0;
4279
4280         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4281
4282         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4283                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4284
4285         return r;
4286 }
4287
4288 static int allocate_vpid(void)
4289 {
4290         int vpid;
4291
4292         if (!enable_vpid)
4293                 return 0;
4294         spin_lock(&vmx_vpid_lock);
4295         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4296         if (vpid < VMX_NR_VPIDS)
4297                 __set_bit(vpid, vmx_vpid_bitmap);
4298         else
4299                 vpid = 0;
4300         spin_unlock(&vmx_vpid_lock);
4301         return vpid;
4302 }
4303
4304 static void free_vpid(int vpid)
4305 {
4306         if (!enable_vpid || vpid == 0)
4307                 return;
4308         spin_lock(&vmx_vpid_lock);
4309         __clear_bit(vpid, vmx_vpid_bitmap);
4310         spin_unlock(&vmx_vpid_lock);
4311 }
4312
4313 #define MSR_TYPE_R      1
4314 #define MSR_TYPE_W      2
4315 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4316                                                 u32 msr, int type)
4317 {
4318         int f = sizeof(unsigned long);
4319
4320         if (!cpu_has_vmx_msr_bitmap())
4321                 return;
4322
4323         /*
4324          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4325          * have the write-low and read-high bitmap offsets the wrong way round.
4326          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4327          */
4328         if (msr <= 0x1fff) {
4329                 if (type & MSR_TYPE_R)
4330                         /* read-low */
4331                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4332
4333                 if (type & MSR_TYPE_W)
4334                         /* write-low */
4335                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4336
4337         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4338                 msr &= 0x1fff;
4339                 if (type & MSR_TYPE_R)
4340                         /* read-high */
4341                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4342
4343                 if (type & MSR_TYPE_W)
4344                         /* write-high */
4345                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4346
4347         }
4348 }
4349
4350 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4351                                                 u32 msr, int type)
4352 {
4353         int f = sizeof(unsigned long);
4354
4355         if (!cpu_has_vmx_msr_bitmap())
4356                 return;
4357
4358         /*
4359          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4360          * have the write-low and read-high bitmap offsets the wrong way round.
4361          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4362          */
4363         if (msr <= 0x1fff) {
4364                 if (type & MSR_TYPE_R)
4365                         /* read-low */
4366                         __set_bit(msr, msr_bitmap + 0x000 / f);
4367
4368                 if (type & MSR_TYPE_W)
4369                         /* write-low */
4370                         __set_bit(msr, msr_bitmap + 0x800 / f);
4371
4372         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4373                 msr &= 0x1fff;
4374                 if (type & MSR_TYPE_R)
4375                         /* read-high */
4376                         __set_bit(msr, msr_bitmap + 0x400 / f);
4377
4378                 if (type & MSR_TYPE_W)
4379                         /* write-high */
4380                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4381
4382         }
4383 }
4384
4385 /*
4386  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4387  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4388  */
4389 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4390                                                unsigned long *msr_bitmap_nested,
4391                                                u32 msr, int type)
4392 {
4393         int f = sizeof(unsigned long);
4394
4395         if (!cpu_has_vmx_msr_bitmap()) {
4396                 WARN_ON(1);
4397                 return;
4398         }
4399
4400         /*
4401          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4402          * have the write-low and read-high bitmap offsets the wrong way round.
4403          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4404          */
4405         if (msr <= 0x1fff) {
4406                 if (type & MSR_TYPE_R &&
4407                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4408                         /* read-low */
4409                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4410
4411                 if (type & MSR_TYPE_W &&
4412                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4413                         /* write-low */
4414                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4415
4416         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4417                 msr &= 0x1fff;
4418                 if (type & MSR_TYPE_R &&
4419                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4420                         /* read-high */
4421                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4422
4423                 if (type & MSR_TYPE_W &&
4424                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4425                         /* write-high */
4426                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4427
4428         }
4429 }
4430
4431 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4432 {
4433         if (!longmode_only)
4434                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4435                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4436         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4437                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4438 }
4439
4440 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4441 {
4442         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4443                         msr, MSR_TYPE_R);
4444         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4445                         msr, MSR_TYPE_R);
4446 }
4447
4448 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4449 {
4450         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4451                         msr, MSR_TYPE_R);
4452         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4453                         msr, MSR_TYPE_R);
4454 }
4455
4456 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4457 {
4458         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4459                         msr, MSR_TYPE_W);
4460         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4461                         msr, MSR_TYPE_W);
4462 }
4463
4464 static bool vmx_get_enable_apicv(void)
4465 {
4466         return enable_apicv;
4467 }
4468
4469 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4470 {
4471         struct vcpu_vmx *vmx = to_vmx(vcpu);
4472         int max_irr;
4473         void *vapic_page;
4474         u16 status;
4475
4476         if (vmx->nested.pi_desc &&
4477             vmx->nested.pi_pending) {
4478                 vmx->nested.pi_pending = false;
4479                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4480                         return 0;
4481
4482                 max_irr = find_last_bit(
4483                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4484
4485                 if (max_irr == 256)
4486                         return 0;
4487
4488                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4489                 if (!vapic_page) {
4490                         WARN_ON(1);
4491                         return -ENOMEM;
4492                 }
4493                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4494                 kunmap(vmx->nested.virtual_apic_page);
4495
4496                 status = vmcs_read16(GUEST_INTR_STATUS);
4497                 if ((u8)max_irr > ((u8)status & 0xff)) {
4498                         status &= ~0xff;
4499                         status |= (u8)max_irr;
4500                         vmcs_write16(GUEST_INTR_STATUS, status);
4501                 }
4502         }
4503         return 0;
4504 }
4505
4506 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4507 {
4508 #ifdef CONFIG_SMP
4509         if (vcpu->mode == IN_GUEST_MODE) {
4510                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4511
4512                 /*
4513                  * Currently, we don't support urgent interrupt,
4514                  * all interrupts are recognized as non-urgent
4515                  * interrupt, so we cannot post interrupts when
4516                  * 'SN' is set.
4517                  *
4518                  * If the vcpu is in guest mode, it means it is
4519                  * running instead of being scheduled out and
4520                  * waiting in the run queue, and that's the only
4521                  * case when 'SN' is set currently, warning if
4522                  * 'SN' is set.
4523                  */
4524                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4525
4526                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4527                                 POSTED_INTR_VECTOR);
4528                 return true;
4529         }
4530 #endif
4531         return false;
4532 }
4533
4534 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4535                                                 int vector)
4536 {
4537         struct vcpu_vmx *vmx = to_vmx(vcpu);
4538
4539         if (is_guest_mode(vcpu) &&
4540             vector == vmx->nested.posted_intr_nv) {
4541                 /* the PIR and ON have been set by L1. */
4542                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4543                 /*
4544                  * If a posted intr is not recognized by hardware,
4545                  * we will accomplish it in the next vmentry.
4546                  */
4547                 vmx->nested.pi_pending = true;
4548                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4549                 return 0;
4550         }
4551         return -1;
4552 }
4553 /*
4554  * Send interrupt to vcpu via posted interrupt way.
4555  * 1. If target vcpu is running(non-root mode), send posted interrupt
4556  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4557  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4558  * interrupt from PIR in next vmentry.
4559  */
4560 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4561 {
4562         struct vcpu_vmx *vmx = to_vmx(vcpu);
4563         int r;
4564
4565         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4566         if (!r)
4567                 return;
4568
4569         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4570                 return;
4571
4572         r = pi_test_and_set_on(&vmx->pi_desc);
4573         kvm_make_request(KVM_REQ_EVENT, vcpu);
4574         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4575                 kvm_vcpu_kick(vcpu);
4576 }
4577
4578 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4579 {
4580         struct vcpu_vmx *vmx = to_vmx(vcpu);
4581
4582         if (!pi_test_and_clear_on(&vmx->pi_desc))
4583                 return;
4584
4585         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4586 }
4587
4588 /*
4589  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4590  * will not change in the lifetime of the guest.
4591  * Note that host-state that does change is set elsewhere. E.g., host-state
4592  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4593  */
4594 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4595 {
4596         u32 low32, high32;
4597         unsigned long tmpl;
4598         struct desc_ptr dt;
4599         unsigned long cr4;
4600
4601         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4602         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4603
4604         /* Save the most likely value for this task's CR4 in the VMCS. */
4605         cr4 = cr4_read_shadow();
4606         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4607         vmx->host_state.vmcs_host_cr4 = cr4;
4608
4609         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4610 #ifdef CONFIG_X86_64
4611         /*
4612          * Load null selectors, so we can avoid reloading them in
4613          * __vmx_load_host_state(), in case userspace uses the null selectors
4614          * too (the expected case).
4615          */
4616         vmcs_write16(HOST_DS_SELECTOR, 0);
4617         vmcs_write16(HOST_ES_SELECTOR, 0);
4618 #else
4619         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4620         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4621 #endif
4622         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4623         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4624
4625         native_store_idt(&dt);
4626         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4627         vmx->host_idt_base = dt.address;
4628
4629         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4630
4631         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4632         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4633         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4634         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4635
4636         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4637                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4638                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4639         }
4640 }
4641
4642 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4643 {
4644         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4645         if (enable_ept)
4646                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4647         if (is_guest_mode(&vmx->vcpu))
4648                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4649                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4650         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4651 }
4652
4653 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4654 {
4655         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4656
4657         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4658                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4659         return pin_based_exec_ctrl;
4660 }
4661
4662 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4663 {
4664         struct vcpu_vmx *vmx = to_vmx(vcpu);
4665
4666         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4667 }
4668
4669 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4670 {
4671         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4672
4673         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4674                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4675
4676         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4677                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4678 #ifdef CONFIG_X86_64
4679                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4680                                 CPU_BASED_CR8_LOAD_EXITING;
4681 #endif
4682         }
4683         if (!enable_ept)
4684                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4685                                 CPU_BASED_CR3_LOAD_EXITING  |
4686                                 CPU_BASED_INVLPG_EXITING;
4687         return exec_control;
4688 }
4689
4690 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4691 {
4692         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4693         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4694                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4695         if (vmx->vpid == 0)
4696                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4697         if (!enable_ept) {
4698                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4699                 enable_unrestricted_guest = 0;
4700                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4701                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4702         }
4703         if (!enable_unrestricted_guest)
4704                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4705         if (!ple_gap)
4706                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4707         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4708                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4709                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4710         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4711         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4712            (handle_vmptrld).
4713            We can NOT enable shadow_vmcs here because we don't have yet
4714            a current VMCS12
4715         */
4716         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4717
4718         if (!enable_pml)
4719                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4720
4721         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4722         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4723
4724         return exec_control;
4725 }
4726
4727 static void ept_set_mmio_spte_mask(void)
4728 {
4729         /*
4730          * EPT Misconfigurations can be generated if the value of bits 2:0
4731          * of an EPT paging-structure entry is 110b (write/execute).
4732          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4733          * spte.
4734          */
4735         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4736 }
4737
4738 #define VMX_XSS_EXIT_BITMAP 0
4739 /*
4740  * Sets up the vmcs for emulated real mode.
4741  */
4742 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4743 {
4744 #ifdef CONFIG_X86_64
4745         unsigned long a;
4746 #endif
4747         int i;
4748
4749         /* I/O */
4750         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4751         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4752
4753         if (enable_shadow_vmcs) {
4754                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4755                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4756         }
4757         if (cpu_has_vmx_msr_bitmap())
4758                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4759
4760         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4761
4762         /* Control */
4763         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4764
4765         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4766
4767         if (cpu_has_secondary_exec_ctrls())
4768                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4769                                 vmx_secondary_exec_control(vmx));
4770
4771         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4772                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4773                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4774                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4775                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4776
4777                 vmcs_write16(GUEST_INTR_STATUS, 0);
4778
4779                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4780                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4781         }
4782
4783         if (ple_gap) {
4784                 vmcs_write32(PLE_GAP, ple_gap);
4785                 vmx->ple_window = ple_window;
4786                 vmx->ple_window_dirty = true;
4787         }
4788
4789         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4790         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4791         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4792
4793         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4794         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4795         vmx_set_constant_host_state(vmx);
4796 #ifdef CONFIG_X86_64
4797         rdmsrl(MSR_FS_BASE, a);
4798         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4799         rdmsrl(MSR_GS_BASE, a);
4800         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4801 #else
4802         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4803         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4804 #endif
4805
4806         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4807         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4808         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4809         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4810         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4811
4812         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4813                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4814
4815         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4816                 u32 index = vmx_msr_index[i];
4817                 u32 data_low, data_high;
4818                 int j = vmx->nmsrs;
4819
4820                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4821                         continue;
4822                 if (wrmsr_safe(index, data_low, data_high) < 0)
4823                         continue;
4824                 vmx->guest_msrs[j].index = i;
4825                 vmx->guest_msrs[j].data = 0;
4826                 vmx->guest_msrs[j].mask = -1ull;
4827                 ++vmx->nmsrs;
4828         }
4829
4830
4831         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4832
4833         /* 22.2.1, 20.8.1 */
4834         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4835
4836         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4837         set_cr4_guest_host_mask(vmx);
4838
4839         if (vmx_xsaves_supported())
4840                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4841
4842         return 0;
4843 }
4844
4845 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4846 {
4847         struct vcpu_vmx *vmx = to_vmx(vcpu);
4848         struct msr_data apic_base_msr;
4849         u64 cr0;
4850
4851         vmx->rmode.vm86_active = 0;
4852
4853         vmx->soft_vnmi_blocked = 0;
4854
4855         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4856         kvm_set_cr8(vcpu, 0);
4857
4858         if (!init_event) {
4859                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4860                                      MSR_IA32_APICBASE_ENABLE;
4861                 if (kvm_vcpu_is_reset_bsp(vcpu))
4862                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4863                 apic_base_msr.host_initiated = true;
4864                 kvm_set_apic_base(vcpu, &apic_base_msr);
4865         }
4866
4867         vmx_segment_cache_clear(vmx);
4868
4869         seg_setup(VCPU_SREG_CS);
4870         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4871         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4872
4873         seg_setup(VCPU_SREG_DS);
4874         seg_setup(VCPU_SREG_ES);
4875         seg_setup(VCPU_SREG_FS);
4876         seg_setup(VCPU_SREG_GS);
4877         seg_setup(VCPU_SREG_SS);
4878
4879         vmcs_write16(GUEST_TR_SELECTOR, 0);
4880         vmcs_writel(GUEST_TR_BASE, 0);
4881         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4882         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4883
4884         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4885         vmcs_writel(GUEST_LDTR_BASE, 0);
4886         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4887         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4888
4889         if (!init_event) {
4890                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4891                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4892                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4893                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4894         }
4895
4896         vmcs_writel(GUEST_RFLAGS, 0x02);
4897         kvm_rip_write(vcpu, 0xfff0);
4898
4899         vmcs_writel(GUEST_GDTR_BASE, 0);
4900         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4901
4902         vmcs_writel(GUEST_IDTR_BASE, 0);
4903         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4904
4905         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4906         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4907         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4908
4909         setup_msrs(vmx);
4910
4911         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4912
4913         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4914                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4915                 if (cpu_need_tpr_shadow(vcpu))
4916                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4917                                      __pa(vcpu->arch.apic->regs));
4918                 vmcs_write32(TPR_THRESHOLD, 0);
4919         }
4920
4921         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4922
4923         if (kvm_vcpu_apicv_active(vcpu))
4924                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4925
4926         if (vmx->vpid != 0)
4927                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4928
4929         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4930         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4931         vmx->vcpu.arch.cr0 = cr0;
4932         vmx_set_cr4(vcpu, 0);
4933         vmx_set_efer(vcpu, 0);
4934         vmx_fpu_activate(vcpu);
4935         update_exception_bitmap(vcpu);
4936
4937         vpid_sync_context(vmx->vpid);
4938 }
4939
4940 /*
4941  * In nested virtualization, check if L1 asked to exit on external interrupts.
4942  * For most existing hypervisors, this will always return true.
4943  */
4944 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4945 {
4946         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4947                 PIN_BASED_EXT_INTR_MASK;
4948 }
4949
4950 /*
4951  * In nested virtualization, check if L1 has set
4952  * VM_EXIT_ACK_INTR_ON_EXIT
4953  */
4954 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4955 {
4956         return get_vmcs12(vcpu)->vm_exit_controls &
4957                 VM_EXIT_ACK_INTR_ON_EXIT;
4958 }
4959
4960 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4961 {
4962         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4963                 PIN_BASED_NMI_EXITING;
4964 }
4965
4966 static void enable_irq_window(struct kvm_vcpu *vcpu)
4967 {
4968         u32 cpu_based_vm_exec_control;
4969
4970         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4971         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4972         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4973 }
4974
4975 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4976 {
4977         u32 cpu_based_vm_exec_control;
4978
4979         if (!cpu_has_virtual_nmis() ||
4980             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4981                 enable_irq_window(vcpu);
4982                 return;
4983         }
4984
4985         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4986         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4987         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4988 }
4989
4990 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4991 {
4992         struct vcpu_vmx *vmx = to_vmx(vcpu);
4993         uint32_t intr;
4994         int irq = vcpu->arch.interrupt.nr;
4995
4996         trace_kvm_inj_virq(irq);
4997
4998         ++vcpu->stat.irq_injections;
4999         if (vmx->rmode.vm86_active) {
5000                 int inc_eip = 0;
5001                 if (vcpu->arch.interrupt.soft)
5002                         inc_eip = vcpu->arch.event_exit_inst_len;
5003                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5004                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5005                 return;
5006         }
5007         intr = irq | INTR_INFO_VALID_MASK;
5008         if (vcpu->arch.interrupt.soft) {
5009                 intr |= INTR_TYPE_SOFT_INTR;
5010                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5011                              vmx->vcpu.arch.event_exit_inst_len);
5012         } else
5013                 intr |= INTR_TYPE_EXT_INTR;
5014         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5015 }
5016
5017 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5018 {
5019         struct vcpu_vmx *vmx = to_vmx(vcpu);
5020
5021         if (is_guest_mode(vcpu))
5022                 return;
5023
5024         if (!cpu_has_virtual_nmis()) {
5025                 /*
5026                  * Tracking the NMI-blocked state in software is built upon
5027                  * finding the next open IRQ window. This, in turn, depends on
5028                  * well-behaving guests: They have to keep IRQs disabled at
5029                  * least as long as the NMI handler runs. Otherwise we may
5030                  * cause NMI nesting, maybe breaking the guest. But as this is
5031                  * highly unlikely, we can live with the residual risk.
5032                  */
5033                 vmx->soft_vnmi_blocked = 1;
5034                 vmx->vnmi_blocked_time = 0;
5035         }
5036
5037         ++vcpu->stat.nmi_injections;
5038         vmx->nmi_known_unmasked = false;
5039         if (vmx->rmode.vm86_active) {
5040                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5041                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5042                 return;
5043         }
5044         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5045                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5046 }
5047
5048 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5049 {
5050         if (!cpu_has_virtual_nmis())
5051                 return to_vmx(vcpu)->soft_vnmi_blocked;
5052         if (to_vmx(vcpu)->nmi_known_unmasked)
5053                 return false;
5054         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5055 }
5056
5057 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5058 {
5059         struct vcpu_vmx *vmx = to_vmx(vcpu);
5060
5061         if (!cpu_has_virtual_nmis()) {
5062                 if (vmx->soft_vnmi_blocked != masked) {
5063                         vmx->soft_vnmi_blocked = masked;
5064                         vmx->vnmi_blocked_time = 0;
5065                 }
5066         } else {
5067                 vmx->nmi_known_unmasked = !masked;
5068                 if (masked)
5069                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5070                                       GUEST_INTR_STATE_NMI);
5071                 else
5072                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5073                                         GUEST_INTR_STATE_NMI);
5074         }
5075 }
5076
5077 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5078 {
5079         if (to_vmx(vcpu)->nested.nested_run_pending)
5080                 return 0;
5081
5082         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5083                 return 0;
5084
5085         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5086                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5087                    | GUEST_INTR_STATE_NMI));
5088 }
5089
5090 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5091 {
5092         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5093                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5094                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5095                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5096 }
5097
5098 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5099 {
5100         int ret;
5101
5102         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5103                                     PAGE_SIZE * 3);
5104         if (ret)
5105                 return ret;
5106         kvm->arch.tss_addr = addr;
5107         return init_rmode_tss(kvm);
5108 }
5109
5110 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5111 {
5112         switch (vec) {
5113         case BP_VECTOR:
5114                 /*
5115                  * Update instruction length as we may reinject the exception
5116                  * from user space while in guest debugging mode.
5117                  */
5118                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5119                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5120                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5121                         return false;
5122                 /* fall through */
5123         case DB_VECTOR:
5124                 if (vcpu->guest_debug &
5125                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5126                         return false;
5127                 /* fall through */
5128         case DE_VECTOR:
5129         case OF_VECTOR:
5130         case BR_VECTOR:
5131         case UD_VECTOR:
5132         case DF_VECTOR:
5133         case SS_VECTOR:
5134         case GP_VECTOR:
5135         case MF_VECTOR:
5136                 return true;
5137         break;
5138         }
5139         return false;
5140 }
5141
5142 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5143                                   int vec, u32 err_code)
5144 {
5145         /*
5146          * Instruction with address size override prefix opcode 0x67
5147          * Cause the #SS fault with 0 error code in VM86 mode.
5148          */
5149         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5150                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5151                         if (vcpu->arch.halt_request) {
5152                                 vcpu->arch.halt_request = 0;
5153                                 return kvm_vcpu_halt(vcpu);
5154                         }
5155                         return 1;
5156                 }
5157                 return 0;
5158         }
5159
5160         /*
5161          * Forward all other exceptions that are valid in real mode.
5162          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5163          *        the required debugging infrastructure rework.
5164          */
5165         kvm_queue_exception(vcpu, vec);
5166         return 1;
5167 }
5168
5169 /*
5170  * Trigger machine check on the host. We assume all the MSRs are already set up
5171  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5172  * We pass a fake environment to the machine check handler because we want
5173  * the guest to be always treated like user space, no matter what context
5174  * it used internally.
5175  */
5176 static void kvm_machine_check(void)
5177 {
5178 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5179         struct pt_regs regs = {
5180                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5181                 .flags = X86_EFLAGS_IF,
5182         };
5183
5184         do_machine_check(&regs, 0);
5185 #endif
5186 }
5187
5188 static int handle_machine_check(struct kvm_vcpu *vcpu)
5189 {
5190         /* already handled by vcpu_run */
5191         return 1;
5192 }
5193
5194 static int handle_exception(struct kvm_vcpu *vcpu)
5195 {
5196         struct vcpu_vmx *vmx = to_vmx(vcpu);
5197         struct kvm_run *kvm_run = vcpu->run;
5198         u32 intr_info, ex_no, error_code;
5199         unsigned long cr2, rip, dr6;
5200         u32 vect_info;
5201         enum emulation_result er;
5202
5203         vect_info = vmx->idt_vectoring_info;
5204         intr_info = vmx->exit_intr_info;
5205
5206         if (is_machine_check(intr_info))
5207                 return handle_machine_check(vcpu);
5208
5209         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5210                 return 1;  /* already handled by vmx_vcpu_run() */
5211
5212         if (is_no_device(intr_info)) {
5213                 vmx_fpu_activate(vcpu);
5214                 return 1;
5215         }
5216
5217         if (is_invalid_opcode(intr_info)) {
5218                 if (is_guest_mode(vcpu)) {
5219                         kvm_queue_exception(vcpu, UD_VECTOR);
5220                         return 1;
5221                 }
5222                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5223                 if (er != EMULATE_DONE)
5224                         kvm_queue_exception(vcpu, UD_VECTOR);
5225                 return 1;
5226         }
5227
5228         error_code = 0;
5229         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5230                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5231
5232         /*
5233          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5234          * MMIO, it is better to report an internal error.
5235          * See the comments in vmx_handle_exit.
5236          */
5237         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5238             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5239                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5240                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5241                 vcpu->run->internal.ndata = 3;
5242                 vcpu->run->internal.data[0] = vect_info;
5243                 vcpu->run->internal.data[1] = intr_info;
5244                 vcpu->run->internal.data[2] = error_code;
5245                 return 0;
5246         }
5247
5248         if (is_page_fault(intr_info)) {
5249                 /* EPT won't cause page fault directly */
5250                 BUG_ON(enable_ept);
5251                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5252                 trace_kvm_page_fault(cr2, error_code);
5253
5254                 if (kvm_event_needs_reinjection(vcpu))
5255                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5256                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5257         }
5258
5259         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5260
5261         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5262                 return handle_rmode_exception(vcpu, ex_no, error_code);
5263
5264         switch (ex_no) {
5265         case AC_VECTOR:
5266                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5267                 return 1;
5268         case DB_VECTOR:
5269                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5270                 if (!(vcpu->guest_debug &
5271                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5272                         vcpu->arch.dr6 &= ~15;
5273                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5274                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5275                                 skip_emulated_instruction(vcpu);
5276
5277                         kvm_queue_exception(vcpu, DB_VECTOR);
5278                         return 1;
5279                 }
5280                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5281                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5282                 /* fall through */
5283         case BP_VECTOR:
5284                 /*
5285                  * Update instruction length as we may reinject #BP from
5286                  * user space while in guest debugging mode. Reading it for
5287                  * #DB as well causes no harm, it is not used in that case.
5288                  */
5289                 vmx->vcpu.arch.event_exit_inst_len =
5290                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5291                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5292                 rip = kvm_rip_read(vcpu);
5293                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5294                 kvm_run->debug.arch.exception = ex_no;
5295                 break;
5296         default:
5297                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5298                 kvm_run->ex.exception = ex_no;
5299                 kvm_run->ex.error_code = error_code;
5300                 break;
5301         }
5302         return 0;
5303 }
5304
5305 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5306 {
5307         ++vcpu->stat.irq_exits;
5308         return 1;
5309 }
5310
5311 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5312 {
5313         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5314         return 0;
5315 }
5316
5317 static int handle_io(struct kvm_vcpu *vcpu)
5318 {
5319         unsigned long exit_qualification;
5320         int size, in, string;
5321         unsigned port;
5322
5323         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5324         string = (exit_qualification & 16) != 0;
5325         in = (exit_qualification & 8) != 0;
5326
5327         ++vcpu->stat.io_exits;
5328
5329         if (string || in)
5330                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5331
5332         port = exit_qualification >> 16;
5333         size = (exit_qualification & 7) + 1;
5334         skip_emulated_instruction(vcpu);
5335
5336         return kvm_fast_pio_out(vcpu, size, port);
5337 }
5338
5339 static void
5340 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5341 {
5342         /*
5343          * Patch in the VMCALL instruction:
5344          */
5345         hypercall[0] = 0x0f;
5346         hypercall[1] = 0x01;
5347         hypercall[2] = 0xc1;
5348 }
5349
5350 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5351 {
5352         unsigned long always_on = VMXON_CR0_ALWAYSON;
5353         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5354
5355         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5356                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5357             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5358                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5359         return (val & always_on) == always_on;
5360 }
5361
5362 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5363 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5364 {
5365         if (is_guest_mode(vcpu)) {
5366                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5367                 unsigned long orig_val = val;
5368
5369                 /*
5370                  * We get here when L2 changed cr0 in a way that did not change
5371                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5372                  * but did change L0 shadowed bits. So we first calculate the
5373                  * effective cr0 value that L1 would like to write into the
5374                  * hardware. It consists of the L2-owned bits from the new
5375                  * value combined with the L1-owned bits from L1's guest_cr0.
5376                  */
5377                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5378                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5379
5380                 if (!nested_cr0_valid(vcpu, val))
5381                         return 1;
5382
5383                 if (kvm_set_cr0(vcpu, val))
5384                         return 1;
5385                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5386                 return 0;
5387         } else {
5388                 if (to_vmx(vcpu)->nested.vmxon &&
5389                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5390                         return 1;
5391                 return kvm_set_cr0(vcpu, val);
5392         }
5393 }
5394
5395 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5396 {
5397         if (is_guest_mode(vcpu)) {
5398                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5399                 unsigned long orig_val = val;
5400
5401                 /* analogously to handle_set_cr0 */
5402                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5403                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5404                 if (kvm_set_cr4(vcpu, val))
5405                         return 1;
5406                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5407                 return 0;
5408         } else
5409                 return kvm_set_cr4(vcpu, val);
5410 }
5411
5412 /* called to set cr0 as approriate for clts instruction exit. */
5413 static void handle_clts(struct kvm_vcpu *vcpu)
5414 {
5415         if (is_guest_mode(vcpu)) {
5416                 /*
5417                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5418                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5419                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5420                  */
5421                 vmcs_writel(CR0_READ_SHADOW,
5422                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5423                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5424         } else
5425                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5426 }
5427
5428 static int handle_cr(struct kvm_vcpu *vcpu)
5429 {
5430         unsigned long exit_qualification, val;
5431         int cr;
5432         int reg;
5433         int err;
5434
5435         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5436         cr = exit_qualification & 15;
5437         reg = (exit_qualification >> 8) & 15;
5438         switch ((exit_qualification >> 4) & 3) {
5439         case 0: /* mov to cr */
5440                 val = kvm_register_readl(vcpu, reg);
5441                 trace_kvm_cr_write(cr, val);
5442                 switch (cr) {
5443                 case 0:
5444                         err = handle_set_cr0(vcpu, val);
5445                         kvm_complete_insn_gp(vcpu, err);
5446                         return 1;
5447                 case 3:
5448                         err = kvm_set_cr3(vcpu, val);
5449                         kvm_complete_insn_gp(vcpu, err);
5450                         return 1;
5451                 case 4:
5452                         err = handle_set_cr4(vcpu, val);
5453                         kvm_complete_insn_gp(vcpu, err);
5454                         return 1;
5455                 case 8: {
5456                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5457                                 u8 cr8 = (u8)val;
5458                                 err = kvm_set_cr8(vcpu, cr8);
5459                                 kvm_complete_insn_gp(vcpu, err);
5460                                 if (lapic_in_kernel(vcpu))
5461                                         return 1;
5462                                 if (cr8_prev <= cr8)
5463                                         return 1;
5464                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5465                                 return 0;
5466                         }
5467                 }
5468                 break;
5469         case 2: /* clts */
5470                 handle_clts(vcpu);
5471                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5472                 skip_emulated_instruction(vcpu);
5473                 vmx_fpu_activate(vcpu);
5474                 return 1;
5475         case 1: /*mov from cr*/
5476                 switch (cr) {
5477                 case 3:
5478                         val = kvm_read_cr3(vcpu);
5479                         kvm_register_write(vcpu, reg, val);
5480                         trace_kvm_cr_read(cr, val);
5481                         skip_emulated_instruction(vcpu);
5482                         return 1;
5483                 case 8:
5484                         val = kvm_get_cr8(vcpu);
5485                         kvm_register_write(vcpu, reg, val);
5486                         trace_kvm_cr_read(cr, val);
5487                         skip_emulated_instruction(vcpu);
5488                         return 1;
5489                 }
5490                 break;
5491         case 3: /* lmsw */
5492                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5493                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5494                 kvm_lmsw(vcpu, val);
5495
5496                 skip_emulated_instruction(vcpu);
5497                 return 1;
5498         default:
5499                 break;
5500         }
5501         vcpu->run->exit_reason = 0;
5502         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5503                (int)(exit_qualification >> 4) & 3, cr);
5504         return 0;
5505 }
5506
5507 static int handle_dr(struct kvm_vcpu *vcpu)
5508 {
5509         unsigned long exit_qualification;
5510         int dr, dr7, reg;
5511
5512         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5513         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5514
5515         /* First, if DR does not exist, trigger UD */
5516         if (!kvm_require_dr(vcpu, dr))
5517                 return 1;
5518
5519         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5520         if (!kvm_require_cpl(vcpu, 0))
5521                 return 1;
5522         dr7 = vmcs_readl(GUEST_DR7);
5523         if (dr7 & DR7_GD) {
5524                 /*
5525                  * As the vm-exit takes precedence over the debug trap, we
5526                  * need to emulate the latter, either for the host or the
5527                  * guest debugging itself.
5528                  */
5529                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5530                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5531                         vcpu->run->debug.arch.dr7 = dr7;
5532                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5533                         vcpu->run->debug.arch.exception = DB_VECTOR;
5534                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5535                         return 0;
5536                 } else {
5537                         vcpu->arch.dr6 &= ~15;
5538                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5539                         kvm_queue_exception(vcpu, DB_VECTOR);
5540                         return 1;
5541                 }
5542         }
5543
5544         if (vcpu->guest_debug == 0) {
5545                 u32 cpu_based_vm_exec_control;
5546
5547                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5548                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5549                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5550
5551                 /*
5552                  * No more DR vmexits; force a reload of the debug registers
5553                  * and reenter on this instruction.  The next vmexit will
5554                  * retrieve the full state of the debug registers.
5555                  */
5556                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5557                 return 1;
5558         }
5559
5560         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5561         if (exit_qualification & TYPE_MOV_FROM_DR) {
5562                 unsigned long val;
5563
5564                 if (kvm_get_dr(vcpu, dr, &val))
5565                         return 1;
5566                 kvm_register_write(vcpu, reg, val);
5567         } else
5568                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5569                         return 1;
5570
5571         skip_emulated_instruction(vcpu);
5572         return 1;
5573 }
5574
5575 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5576 {
5577         return vcpu->arch.dr6;
5578 }
5579
5580 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5581 {
5582 }
5583
5584 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5585 {
5586         u32 cpu_based_vm_exec_control;
5587
5588         get_debugreg(vcpu->arch.db[0], 0);
5589         get_debugreg(vcpu->arch.db[1], 1);
5590         get_debugreg(vcpu->arch.db[2], 2);
5591         get_debugreg(vcpu->arch.db[3], 3);
5592         get_debugreg(vcpu->arch.dr6, 6);
5593         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5594
5595         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5596
5597         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5598         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5599         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5600 }
5601
5602 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5603 {
5604         vmcs_writel(GUEST_DR7, val);
5605 }
5606
5607 static int handle_cpuid(struct kvm_vcpu *vcpu)
5608 {
5609         kvm_emulate_cpuid(vcpu);
5610         return 1;
5611 }
5612
5613 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5614 {
5615         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5616         struct msr_data msr_info;
5617
5618         msr_info.index = ecx;
5619         msr_info.host_initiated = false;
5620         if (vmx_get_msr(vcpu, &msr_info)) {
5621                 trace_kvm_msr_read_ex(ecx);
5622                 kvm_inject_gp(vcpu, 0);
5623                 return 1;
5624         }
5625
5626         trace_kvm_msr_read(ecx, msr_info.data);
5627
5628         /* FIXME: handling of bits 32:63 of rax, rdx */
5629         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5630         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5631         skip_emulated_instruction(vcpu);
5632         return 1;
5633 }
5634
5635 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5636 {
5637         struct msr_data msr;
5638         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5639         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5640                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5641
5642         msr.data = data;
5643         msr.index = ecx;
5644         msr.host_initiated = false;
5645         if (kvm_set_msr(vcpu, &msr) != 0) {
5646                 trace_kvm_msr_write_ex(ecx, data);
5647                 kvm_inject_gp(vcpu, 0);
5648                 return 1;
5649         }
5650
5651         trace_kvm_msr_write(ecx, data);
5652         skip_emulated_instruction(vcpu);
5653         return 1;
5654 }
5655
5656 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5657 {
5658         kvm_make_request(KVM_REQ_EVENT, vcpu);
5659         return 1;
5660 }
5661
5662 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5663 {
5664         u32 cpu_based_vm_exec_control;
5665
5666         /* clear pending irq */
5667         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5668         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5669         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5670
5671         kvm_make_request(KVM_REQ_EVENT, vcpu);
5672
5673         ++vcpu->stat.irq_window_exits;
5674         return 1;
5675 }
5676
5677 static int handle_halt(struct kvm_vcpu *vcpu)
5678 {
5679         return kvm_emulate_halt(vcpu);
5680 }
5681
5682 static int handle_vmcall(struct kvm_vcpu *vcpu)
5683 {
5684         kvm_emulate_hypercall(vcpu);
5685         return 1;
5686 }
5687
5688 static int handle_invd(struct kvm_vcpu *vcpu)
5689 {
5690         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5691 }
5692
5693 static int handle_invlpg(struct kvm_vcpu *vcpu)
5694 {
5695         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5696
5697         kvm_mmu_invlpg(vcpu, exit_qualification);
5698         skip_emulated_instruction(vcpu);
5699         return 1;
5700 }
5701
5702 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5703 {
5704         int err;
5705
5706         err = kvm_rdpmc(vcpu);
5707         kvm_complete_insn_gp(vcpu, err);
5708
5709         return 1;
5710 }
5711
5712 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5713 {
5714         kvm_emulate_wbinvd(vcpu);
5715         return 1;
5716 }
5717
5718 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5719 {
5720         u64 new_bv = kvm_read_edx_eax(vcpu);
5721         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5722
5723         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5724                 skip_emulated_instruction(vcpu);
5725         return 1;
5726 }
5727
5728 static int handle_xsaves(struct kvm_vcpu *vcpu)
5729 {
5730         skip_emulated_instruction(vcpu);
5731         WARN(1, "this should never happen\n");
5732         return 1;
5733 }
5734
5735 static int handle_xrstors(struct kvm_vcpu *vcpu)
5736 {
5737         skip_emulated_instruction(vcpu);
5738         WARN(1, "this should never happen\n");
5739         return 1;
5740 }
5741
5742 static int handle_apic_access(struct kvm_vcpu *vcpu)
5743 {
5744         if (likely(fasteoi)) {
5745                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5746                 int access_type, offset;
5747
5748                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5749                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5750                 /*
5751                  * Sane guest uses MOV to write EOI, with written value
5752                  * not cared. So make a short-circuit here by avoiding
5753                  * heavy instruction emulation.
5754                  */
5755                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5756                     (offset == APIC_EOI)) {
5757                         kvm_lapic_set_eoi(vcpu);
5758                         skip_emulated_instruction(vcpu);
5759                         return 1;
5760                 }
5761         }
5762         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5763 }
5764
5765 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5766 {
5767         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5768         int vector = exit_qualification & 0xff;
5769
5770         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5771         kvm_apic_set_eoi_accelerated(vcpu, vector);
5772         return 1;
5773 }
5774
5775 static int handle_apic_write(struct kvm_vcpu *vcpu)
5776 {
5777         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5778         u32 offset = exit_qualification & 0xfff;
5779
5780         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5781         kvm_apic_write_nodecode(vcpu, offset);
5782         return 1;
5783 }
5784
5785 static int handle_task_switch(struct kvm_vcpu *vcpu)
5786 {
5787         struct vcpu_vmx *vmx = to_vmx(vcpu);
5788         unsigned long exit_qualification;
5789         bool has_error_code = false;
5790         u32 error_code = 0;
5791         u16 tss_selector;
5792         int reason, type, idt_v, idt_index;
5793
5794         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5795         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5796         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5797
5798         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5799
5800         reason = (u32)exit_qualification >> 30;
5801         if (reason == TASK_SWITCH_GATE && idt_v) {
5802                 switch (type) {
5803                 case INTR_TYPE_NMI_INTR:
5804                         vcpu->arch.nmi_injected = false;
5805                         vmx_set_nmi_mask(vcpu, true);
5806                         break;
5807                 case INTR_TYPE_EXT_INTR:
5808                 case INTR_TYPE_SOFT_INTR:
5809                         kvm_clear_interrupt_queue(vcpu);
5810                         break;
5811                 case INTR_TYPE_HARD_EXCEPTION:
5812                         if (vmx->idt_vectoring_info &
5813                             VECTORING_INFO_DELIVER_CODE_MASK) {
5814                                 has_error_code = true;
5815                                 error_code =
5816                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5817                         }
5818                         /* fall through */
5819                 case INTR_TYPE_SOFT_EXCEPTION:
5820                         kvm_clear_exception_queue(vcpu);
5821                         break;
5822                 default:
5823                         break;
5824                 }
5825         }
5826         tss_selector = exit_qualification;
5827
5828         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5829                        type != INTR_TYPE_EXT_INTR &&
5830                        type != INTR_TYPE_NMI_INTR))
5831                 skip_emulated_instruction(vcpu);
5832
5833         if (kvm_task_switch(vcpu, tss_selector,
5834                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5835                             has_error_code, error_code) == EMULATE_FAIL) {
5836                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5837                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5838                 vcpu->run->internal.ndata = 0;
5839                 return 0;
5840         }
5841
5842         /*
5843          * TODO: What about debug traps on tss switch?
5844          *       Are we supposed to inject them and update dr6?
5845          */
5846
5847         return 1;
5848 }
5849
5850 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5851 {
5852         unsigned long exit_qualification;
5853         gpa_t gpa;
5854         u32 error_code;
5855         int gla_validity;
5856
5857         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5858
5859         gla_validity = (exit_qualification >> 7) & 0x3;
5860         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5861                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5862                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5863                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5864                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5865                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5866                         (long unsigned int)exit_qualification);
5867                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5868                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5869                 return 0;
5870         }
5871
5872         /*
5873          * EPT violation happened while executing iret from NMI,
5874          * "blocked by NMI" bit has to be set before next VM entry.
5875          * There are errata that may cause this bit to not be set:
5876          * AAK134, BY25.
5877          */
5878         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5879                         cpu_has_virtual_nmis() &&
5880                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5881                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5882
5883         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5884         trace_kvm_page_fault(gpa, exit_qualification);
5885
5886         /* It is a write fault? */
5887         error_code = exit_qualification & PFERR_WRITE_MASK;
5888         /* It is a fetch fault? */
5889         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5890         /* ept page table is present? */
5891         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5892
5893         vcpu->arch.exit_qualification = exit_qualification;
5894
5895         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5896 }
5897
5898 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5899 {
5900         int ret;
5901         gpa_t gpa;
5902
5903         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5904         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5905                 skip_emulated_instruction(vcpu);
5906                 trace_kvm_fast_mmio(gpa);
5907                 return 1;
5908         }
5909
5910         ret = handle_mmio_page_fault(vcpu, gpa, true);
5911         if (likely(ret == RET_MMIO_PF_EMULATE))
5912                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5913                                               EMULATE_DONE;
5914
5915         if (unlikely(ret == RET_MMIO_PF_INVALID))
5916                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5917
5918         if (unlikely(ret == RET_MMIO_PF_RETRY))
5919                 return 1;
5920
5921         /* It is the real ept misconfig */
5922         WARN_ON(1);
5923
5924         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5925         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5926
5927         return 0;
5928 }
5929
5930 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5931 {
5932         u32 cpu_based_vm_exec_control;
5933
5934         /* clear pending NMI */
5935         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5936         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5937         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5938         ++vcpu->stat.nmi_window_exits;
5939         kvm_make_request(KVM_REQ_EVENT, vcpu);
5940
5941         return 1;
5942 }
5943
5944 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5945 {
5946         struct vcpu_vmx *vmx = to_vmx(vcpu);
5947         enum emulation_result err = EMULATE_DONE;
5948         int ret = 1;
5949         u32 cpu_exec_ctrl;
5950         bool intr_window_requested;
5951         unsigned count = 130;
5952
5953         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5954         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5955
5956         while (vmx->emulation_required && count-- != 0) {
5957                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5958                         return handle_interrupt_window(&vmx->vcpu);
5959
5960                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5961                         return 1;
5962
5963                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5964
5965                 if (err == EMULATE_USER_EXIT) {
5966                         ++vcpu->stat.mmio_exits;
5967                         ret = 0;
5968                         goto out;
5969                 }
5970
5971                 if (err != EMULATE_DONE) {
5972                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5973                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5974                         vcpu->run->internal.ndata = 0;
5975                         return 0;
5976                 }
5977
5978                 if (vcpu->arch.halt_request) {
5979                         vcpu->arch.halt_request = 0;
5980                         ret = kvm_vcpu_halt(vcpu);
5981                         goto out;
5982                 }
5983
5984                 if (signal_pending(current))
5985                         goto out;
5986                 if (need_resched())
5987                         schedule();
5988         }
5989
5990 out:
5991         return ret;
5992 }
5993
5994 static int __grow_ple_window(int val)
5995 {
5996         if (ple_window_grow < 1)
5997                 return ple_window;
5998
5999         val = min(val, ple_window_actual_max);
6000
6001         if (ple_window_grow < ple_window)
6002                 val *= ple_window_grow;
6003         else
6004                 val += ple_window_grow;
6005
6006         return val;
6007 }
6008
6009 static int __shrink_ple_window(int val, int modifier, int minimum)
6010 {
6011         if (modifier < 1)
6012                 return ple_window;
6013
6014         if (modifier < ple_window)
6015                 val /= modifier;
6016         else
6017                 val -= modifier;
6018
6019         return max(val, minimum);
6020 }
6021
6022 static void grow_ple_window(struct kvm_vcpu *vcpu)
6023 {
6024         struct vcpu_vmx *vmx = to_vmx(vcpu);
6025         int old = vmx->ple_window;
6026
6027         vmx->ple_window = __grow_ple_window(old);
6028
6029         if (vmx->ple_window != old)
6030                 vmx->ple_window_dirty = true;
6031
6032         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6033 }
6034
6035 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6036 {
6037         struct vcpu_vmx *vmx = to_vmx(vcpu);
6038         int old = vmx->ple_window;
6039
6040         vmx->ple_window = __shrink_ple_window(old,
6041                                               ple_window_shrink, ple_window);
6042
6043         if (vmx->ple_window != old)
6044                 vmx->ple_window_dirty = true;
6045
6046         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6047 }
6048
6049 /*
6050  * ple_window_actual_max is computed to be one grow_ple_window() below
6051  * ple_window_max. (See __grow_ple_window for the reason.)
6052  * This prevents overflows, because ple_window_max is int.
6053  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6054  * this process.
6055  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6056  */
6057 static void update_ple_window_actual_max(void)
6058 {
6059         ple_window_actual_max =
6060                         __shrink_ple_window(max(ple_window_max, ple_window),
6061                                             ple_window_grow, INT_MIN);
6062 }
6063
6064 /*
6065  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6066  */
6067 static void wakeup_handler(void)
6068 {
6069         struct kvm_vcpu *vcpu;
6070         int cpu = smp_processor_id();
6071
6072         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6073         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6074                         blocked_vcpu_list) {
6075                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6076
6077                 if (pi_test_on(pi_desc) == 1)
6078                         kvm_vcpu_kick(vcpu);
6079         }
6080         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6081 }
6082
6083 static __init int hardware_setup(void)
6084 {
6085         int r = -ENOMEM, i, msr;
6086
6087         rdmsrl_safe(MSR_EFER, &host_efer);
6088
6089         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6090                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6091
6092         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6093         if (!vmx_io_bitmap_a)
6094                 return r;
6095
6096         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6097         if (!vmx_io_bitmap_b)
6098                 goto out;
6099
6100         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6101         if (!vmx_msr_bitmap_legacy)
6102                 goto out1;
6103
6104         vmx_msr_bitmap_legacy_x2apic =
6105                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6106         if (!vmx_msr_bitmap_legacy_x2apic)
6107                 goto out2;
6108
6109         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6110         if (!vmx_msr_bitmap_longmode)
6111                 goto out3;
6112
6113         vmx_msr_bitmap_longmode_x2apic =
6114                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6115         if (!vmx_msr_bitmap_longmode_x2apic)
6116                 goto out4;
6117
6118         if (nested) {
6119                 vmx_msr_bitmap_nested =
6120                         (unsigned long *)__get_free_page(GFP_KERNEL);
6121                 if (!vmx_msr_bitmap_nested)
6122                         goto out5;
6123         }
6124
6125         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6126         if (!vmx_vmread_bitmap)
6127                 goto out6;
6128
6129         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6130         if (!vmx_vmwrite_bitmap)
6131                 goto out7;
6132
6133         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6134         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6135
6136         /*
6137          * Allow direct access to the PC debug port (it is often used for I/O
6138          * delays, but the vmexits simply slow things down).
6139          */
6140         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6141         clear_bit(0x80, vmx_io_bitmap_a);
6142
6143         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6144
6145         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6146         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6147         if (nested)
6148                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6149
6150         if (setup_vmcs_config(&vmcs_config) < 0) {
6151                 r = -EIO;
6152                 goto out8;
6153         }
6154
6155         if (boot_cpu_has(X86_FEATURE_NX))
6156                 kvm_enable_efer_bits(EFER_NX);
6157
6158         if (!cpu_has_vmx_vpid())
6159                 enable_vpid = 0;
6160         if (!cpu_has_vmx_shadow_vmcs())
6161                 enable_shadow_vmcs = 0;
6162         if (enable_shadow_vmcs)
6163                 init_vmcs_shadow_fields();
6164
6165         if (!cpu_has_vmx_ept() ||
6166             !cpu_has_vmx_ept_4levels()) {
6167                 enable_ept = 0;
6168                 enable_unrestricted_guest = 0;
6169                 enable_ept_ad_bits = 0;
6170         }
6171
6172         if (!cpu_has_vmx_ept_ad_bits())
6173                 enable_ept_ad_bits = 0;
6174
6175         if (!cpu_has_vmx_unrestricted_guest())
6176                 enable_unrestricted_guest = 0;
6177
6178         if (!cpu_has_vmx_flexpriority())
6179                 flexpriority_enabled = 0;
6180
6181         /*
6182          * set_apic_access_page_addr() is used to reload apic access
6183          * page upon invalidation.  No need to do anything if not
6184          * using the APIC_ACCESS_ADDR VMCS field.
6185          */
6186         if (!flexpriority_enabled)
6187                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6188
6189         if (!cpu_has_vmx_tpr_shadow())
6190                 kvm_x86_ops->update_cr8_intercept = NULL;
6191
6192         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6193                 kvm_disable_largepages();
6194
6195         if (!cpu_has_vmx_ple())
6196                 ple_gap = 0;
6197
6198         if (!cpu_has_vmx_apicv())
6199                 enable_apicv = 0;
6200
6201         if (cpu_has_vmx_tsc_scaling()) {
6202                 kvm_has_tsc_control = true;
6203                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6204                 kvm_tsc_scaling_ratio_frac_bits = 48;
6205         }
6206
6207         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6208         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6209         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6210         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6211         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6212         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6213         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6214
6215         memcpy(vmx_msr_bitmap_legacy_x2apic,
6216                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6217         memcpy(vmx_msr_bitmap_longmode_x2apic,
6218                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6219
6220         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6221
6222         if (enable_apicv) {
6223                 for (msr = 0x800; msr <= 0x8ff; msr++)
6224                         vmx_disable_intercept_msr_read_x2apic(msr);
6225
6226                 /* According SDM, in x2apic mode, the whole id reg is used.
6227                  * But in KVM, it only use the highest eight bits. Need to
6228                  * intercept it */
6229                 vmx_enable_intercept_msr_read_x2apic(0x802);
6230                 /* TMCCT */
6231                 vmx_enable_intercept_msr_read_x2apic(0x839);
6232                 /* TPR */
6233                 vmx_disable_intercept_msr_write_x2apic(0x808);
6234                 /* EOI */
6235                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6236                 /* SELF-IPI */
6237                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6238         }
6239
6240         if (enable_ept) {
6241                 kvm_mmu_set_mask_ptes(0ull,
6242                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6243                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6244                         0ull, VMX_EPT_EXECUTABLE_MASK);
6245                 ept_set_mmio_spte_mask();
6246                 kvm_enable_tdp();
6247         } else
6248                 kvm_disable_tdp();
6249
6250         update_ple_window_actual_max();
6251
6252         /*
6253          * Only enable PML when hardware supports PML feature, and both EPT
6254          * and EPT A/D bit features are enabled -- PML depends on them to work.
6255          */
6256         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6257                 enable_pml = 0;
6258
6259         if (!enable_pml) {
6260                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6261                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6262                 kvm_x86_ops->flush_log_dirty = NULL;
6263                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6264         }
6265
6266         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6267
6268         return alloc_kvm_area();
6269
6270 out8:
6271         free_page((unsigned long)vmx_vmwrite_bitmap);
6272 out7:
6273         free_page((unsigned long)vmx_vmread_bitmap);
6274 out6:
6275         if (nested)
6276                 free_page((unsigned long)vmx_msr_bitmap_nested);
6277 out5:
6278         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6279 out4:
6280         free_page((unsigned long)vmx_msr_bitmap_longmode);
6281 out3:
6282         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6283 out2:
6284         free_page((unsigned long)vmx_msr_bitmap_legacy);
6285 out1:
6286         free_page((unsigned long)vmx_io_bitmap_b);
6287 out:
6288         free_page((unsigned long)vmx_io_bitmap_a);
6289
6290     return r;
6291 }
6292
6293 static __exit void hardware_unsetup(void)
6294 {
6295         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6296         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6297         free_page((unsigned long)vmx_msr_bitmap_legacy);
6298         free_page((unsigned long)vmx_msr_bitmap_longmode);
6299         free_page((unsigned long)vmx_io_bitmap_b);
6300         free_page((unsigned long)vmx_io_bitmap_a);
6301         free_page((unsigned long)vmx_vmwrite_bitmap);
6302         free_page((unsigned long)vmx_vmread_bitmap);
6303         if (nested)
6304                 free_page((unsigned long)vmx_msr_bitmap_nested);
6305
6306         free_kvm_area();
6307 }
6308
6309 /*
6310  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6311  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6312  */
6313 static int handle_pause(struct kvm_vcpu *vcpu)
6314 {
6315         if (ple_gap)
6316                 grow_ple_window(vcpu);
6317
6318         skip_emulated_instruction(vcpu);
6319         kvm_vcpu_on_spin(vcpu);
6320
6321         return 1;
6322 }
6323
6324 static int handle_nop(struct kvm_vcpu *vcpu)
6325 {
6326         skip_emulated_instruction(vcpu);
6327         return 1;
6328 }
6329
6330 static int handle_mwait(struct kvm_vcpu *vcpu)
6331 {
6332         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6333         return handle_nop(vcpu);
6334 }
6335
6336 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6337 {
6338         return 1;
6339 }
6340
6341 static int handle_monitor(struct kvm_vcpu *vcpu)
6342 {
6343         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6344         return handle_nop(vcpu);
6345 }
6346
6347 /*
6348  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6349  * We could reuse a single VMCS for all the L2 guests, but we also want the
6350  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6351  * allows keeping them loaded on the processor, and in the future will allow
6352  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6353  * every entry if they never change.
6354  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6355  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6356  *
6357  * The following functions allocate and free a vmcs02 in this pool.
6358  */
6359
6360 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6361 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6362 {
6363         struct vmcs02_list *item;
6364         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6365                 if (item->vmptr == vmx->nested.current_vmptr) {
6366                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6367                         return &item->vmcs02;
6368                 }
6369
6370         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6371                 /* Recycle the least recently used VMCS. */
6372                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6373                         struct vmcs02_list, list);
6374                 item->vmptr = vmx->nested.current_vmptr;
6375                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6376                 return &item->vmcs02;
6377         }
6378
6379         /* Create a new VMCS */
6380         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6381         if (!item)
6382                 return NULL;
6383         item->vmcs02.vmcs = alloc_vmcs();
6384         if (!item->vmcs02.vmcs) {
6385                 kfree(item);
6386                 return NULL;
6387         }
6388         loaded_vmcs_init(&item->vmcs02);
6389         item->vmptr = vmx->nested.current_vmptr;
6390         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6391         vmx->nested.vmcs02_num++;
6392         return &item->vmcs02;
6393 }
6394
6395 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6396 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6397 {
6398         struct vmcs02_list *item;
6399         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6400                 if (item->vmptr == vmptr) {
6401                         free_loaded_vmcs(&item->vmcs02);
6402                         list_del(&item->list);
6403                         kfree(item);
6404                         vmx->nested.vmcs02_num--;
6405                         return;
6406                 }
6407 }
6408
6409 /*
6410  * Free all VMCSs saved for this vcpu, except the one pointed by
6411  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6412  * must be &vmx->vmcs01.
6413  */
6414 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6415 {
6416         struct vmcs02_list *item, *n;
6417
6418         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6419         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6420                 /*
6421                  * Something will leak if the above WARN triggers.  Better than
6422                  * a use-after-free.
6423                  */
6424                 if (vmx->loaded_vmcs == &item->vmcs02)
6425                         continue;
6426
6427                 free_loaded_vmcs(&item->vmcs02);
6428                 list_del(&item->list);
6429                 kfree(item);
6430                 vmx->nested.vmcs02_num--;
6431         }
6432 }
6433
6434 /*
6435  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6436  * set the success or error code of an emulated VMX instruction, as specified
6437  * by Vol 2B, VMX Instruction Reference, "Conventions".
6438  */
6439 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6440 {
6441         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6442                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6443                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6444 }
6445
6446 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6447 {
6448         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6449                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6450                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6451                         | X86_EFLAGS_CF);
6452 }
6453
6454 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6455                                         u32 vm_instruction_error)
6456 {
6457         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6458                 /*
6459                  * failValid writes the error number to the current VMCS, which
6460                  * can't be done there isn't a current VMCS.
6461                  */
6462                 nested_vmx_failInvalid(vcpu);
6463                 return;
6464         }
6465         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6466                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6467                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6468                         | X86_EFLAGS_ZF);
6469         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6470         /*
6471          * We don't need to force a shadow sync because
6472          * VM_INSTRUCTION_ERROR is not shadowed
6473          */
6474 }
6475
6476 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6477 {
6478         /* TODO: not to reset guest simply here. */
6479         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6480         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6481 }
6482
6483 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6484 {
6485         struct vcpu_vmx *vmx =
6486                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6487
6488         vmx->nested.preemption_timer_expired = true;
6489         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6490         kvm_vcpu_kick(&vmx->vcpu);
6491
6492         return HRTIMER_NORESTART;
6493 }
6494
6495 /*
6496  * Decode the memory-address operand of a vmx instruction, as recorded on an
6497  * exit caused by such an instruction (run by a guest hypervisor).
6498  * On success, returns 0. When the operand is invalid, returns 1 and throws
6499  * #UD or #GP.
6500  */
6501 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6502                                  unsigned long exit_qualification,
6503                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6504 {
6505         gva_t off;
6506         bool exn;
6507         struct kvm_segment s;
6508
6509         /*
6510          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6511          * Execution", on an exit, vmx_instruction_info holds most of the
6512          * addressing components of the operand. Only the displacement part
6513          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6514          * For how an actual address is calculated from all these components,
6515          * refer to Vol. 1, "Operand Addressing".
6516          */
6517         int  scaling = vmx_instruction_info & 3;
6518         int  addr_size = (vmx_instruction_info >> 7) & 7;
6519         bool is_reg = vmx_instruction_info & (1u << 10);
6520         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6521         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6522         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6523         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6524         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6525
6526         if (is_reg) {
6527                 kvm_queue_exception(vcpu, UD_VECTOR);
6528                 return 1;
6529         }
6530
6531         /* Addr = segment_base + offset */
6532         /* offset = base + [index * scale] + displacement */
6533         off = exit_qualification; /* holds the displacement */
6534         if (base_is_valid)
6535                 off += kvm_register_read(vcpu, base_reg);
6536         if (index_is_valid)
6537                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6538         vmx_get_segment(vcpu, &s, seg_reg);
6539         *ret = s.base + off;
6540
6541         if (addr_size == 1) /* 32 bit */
6542                 *ret &= 0xffffffff;
6543
6544         /* Checks for #GP/#SS exceptions. */
6545         exn = false;
6546         if (is_protmode(vcpu)) {
6547                 /* Protected mode: apply checks for segment validity in the
6548                  * following order:
6549                  * - segment type check (#GP(0) may be thrown)
6550                  * - usability check (#GP(0)/#SS(0))
6551                  * - limit check (#GP(0)/#SS(0))
6552                  */
6553                 if (wr)
6554                         /* #GP(0) if the destination operand is located in a
6555                          * read-only data segment or any code segment.
6556                          */
6557                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6558                 else
6559                         /* #GP(0) if the source operand is located in an
6560                          * execute-only code segment
6561                          */
6562                         exn = ((s.type & 0xa) == 8);
6563         }
6564         if (exn) {
6565                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6566                 return 1;
6567         }
6568         if (is_long_mode(vcpu)) {
6569                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6570                  * non-canonical form. This is an only check for long mode.
6571                  */
6572                 exn = is_noncanonical_address(*ret);
6573         } else if (is_protmode(vcpu)) {
6574                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6575                  */
6576                 exn = (s.unusable != 0);
6577                 /* Protected mode: #GP(0)/#SS(0) if the memory
6578                  * operand is outside the segment limit.
6579                  */
6580                 exn = exn || (off + sizeof(u64) > s.limit);
6581         }
6582         if (exn) {
6583                 kvm_queue_exception_e(vcpu,
6584                                       seg_reg == VCPU_SREG_SS ?
6585                                                 SS_VECTOR : GP_VECTOR,
6586                                       0);
6587                 return 1;
6588         }
6589
6590         return 0;
6591 }
6592
6593 /*
6594  * This function performs the various checks including
6595  * - if it's 4KB aligned
6596  * - No bits beyond the physical address width are set
6597  * - Returns 0 on success or else 1
6598  * (Intel SDM Section 30.3)
6599  */
6600 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6601                                   gpa_t *vmpointer)
6602 {
6603         gva_t gva;
6604         gpa_t vmptr;
6605         struct x86_exception e;
6606         struct page *page;
6607         struct vcpu_vmx *vmx = to_vmx(vcpu);
6608         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6609
6610         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6611                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6612                 return 1;
6613
6614         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6615                                 sizeof(vmptr), &e)) {
6616                 kvm_inject_page_fault(vcpu, &e);
6617                 return 1;
6618         }
6619
6620         switch (exit_reason) {
6621         case EXIT_REASON_VMON:
6622                 /*
6623                  * SDM 3: 24.11.5
6624                  * The first 4 bytes of VMXON region contain the supported
6625                  * VMCS revision identifier
6626                  *
6627                  * Note - IA32_VMX_BASIC[48] will never be 1
6628                  * for the nested case;
6629                  * which replaces physical address width with 32
6630                  *
6631                  */
6632                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6633                         nested_vmx_failInvalid(vcpu);
6634                         skip_emulated_instruction(vcpu);
6635                         return 1;
6636                 }
6637
6638                 page = nested_get_page(vcpu, vmptr);
6639                 if (page == NULL ||
6640                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6641                         nested_vmx_failInvalid(vcpu);
6642                         kunmap(page);
6643                         skip_emulated_instruction(vcpu);
6644                         return 1;
6645                 }
6646                 kunmap(page);
6647                 vmx->nested.vmxon_ptr = vmptr;
6648                 break;
6649         case EXIT_REASON_VMCLEAR:
6650                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6651                         nested_vmx_failValid(vcpu,
6652                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6653                         skip_emulated_instruction(vcpu);
6654                         return 1;
6655                 }
6656
6657                 if (vmptr == vmx->nested.vmxon_ptr) {
6658                         nested_vmx_failValid(vcpu,
6659                                              VMXERR_VMCLEAR_VMXON_POINTER);
6660                         skip_emulated_instruction(vcpu);
6661                         return 1;
6662                 }
6663                 break;
6664         case EXIT_REASON_VMPTRLD:
6665                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6666                         nested_vmx_failValid(vcpu,
6667                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6668                         skip_emulated_instruction(vcpu);
6669                         return 1;
6670                 }
6671
6672                 if (vmptr == vmx->nested.vmxon_ptr) {
6673                         nested_vmx_failValid(vcpu,
6674                                              VMXERR_VMCLEAR_VMXON_POINTER);
6675                         skip_emulated_instruction(vcpu);
6676                         return 1;
6677                 }
6678                 break;
6679         default:
6680                 return 1; /* shouldn't happen */
6681         }
6682
6683         if (vmpointer)
6684                 *vmpointer = vmptr;
6685         return 0;
6686 }
6687
6688 /*
6689  * Emulate the VMXON instruction.
6690  * Currently, we just remember that VMX is active, and do not save or even
6691  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6692  * do not currently need to store anything in that guest-allocated memory
6693  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6694  * argument is different from the VMXON pointer (which the spec says they do).
6695  */
6696 static int handle_vmon(struct kvm_vcpu *vcpu)
6697 {
6698         struct kvm_segment cs;
6699         struct vcpu_vmx *vmx = to_vmx(vcpu);
6700         struct vmcs *shadow_vmcs;
6701         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6702                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6703
6704         /* The Intel VMX Instruction Reference lists a bunch of bits that
6705          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6706          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6707          * Otherwise, we should fail with #UD. We test these now:
6708          */
6709         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6710             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6711             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6712                 kvm_queue_exception(vcpu, UD_VECTOR);
6713                 return 1;
6714         }
6715
6716         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6717         if (is_long_mode(vcpu) && !cs.l) {
6718                 kvm_queue_exception(vcpu, UD_VECTOR);
6719                 return 1;
6720         }
6721
6722         if (vmx_get_cpl(vcpu)) {
6723                 kvm_inject_gp(vcpu, 0);
6724                 return 1;
6725         }
6726
6727         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6728                 return 1;
6729
6730         if (vmx->nested.vmxon) {
6731                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6732                 skip_emulated_instruction(vcpu);
6733                 return 1;
6734         }
6735
6736         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6737                         != VMXON_NEEDED_FEATURES) {
6738                 kvm_inject_gp(vcpu, 0);
6739                 return 1;
6740         }
6741
6742         if (enable_shadow_vmcs) {
6743                 shadow_vmcs = alloc_vmcs();
6744                 if (!shadow_vmcs)
6745                         return -ENOMEM;
6746                 /* mark vmcs as shadow */
6747                 shadow_vmcs->revision_id |= (1u << 31);
6748                 /* init shadow vmcs */
6749                 vmcs_clear(shadow_vmcs);
6750                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6751         }
6752
6753         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6754         vmx->nested.vmcs02_num = 0;
6755
6756         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6757                      HRTIMER_MODE_REL);
6758         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6759
6760         vmx->nested.vmxon = true;
6761
6762         skip_emulated_instruction(vcpu);
6763         nested_vmx_succeed(vcpu);
6764         return 1;
6765 }
6766
6767 /*
6768  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6769  * for running VMX instructions (except VMXON, whose prerequisites are
6770  * slightly different). It also specifies what exception to inject otherwise.
6771  */
6772 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6773 {
6774         struct kvm_segment cs;
6775         struct vcpu_vmx *vmx = to_vmx(vcpu);
6776
6777         if (!vmx->nested.vmxon) {
6778                 kvm_queue_exception(vcpu, UD_VECTOR);
6779                 return 0;
6780         }
6781
6782         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6783         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6784             (is_long_mode(vcpu) && !cs.l)) {
6785                 kvm_queue_exception(vcpu, UD_VECTOR);
6786                 return 0;
6787         }
6788
6789         if (vmx_get_cpl(vcpu)) {
6790                 kvm_inject_gp(vcpu, 0);
6791                 return 0;
6792         }
6793
6794         return 1;
6795 }
6796
6797 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6798 {
6799         if (vmx->nested.current_vmptr == -1ull)
6800                 return;
6801
6802         /* current_vmptr and current_vmcs12 are always set/reset together */
6803         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6804                 return;
6805
6806         if (enable_shadow_vmcs) {
6807                 /* copy to memory all shadowed fields in case
6808                    they were modified */
6809                 copy_shadow_to_vmcs12(vmx);
6810                 vmx->nested.sync_shadow_vmcs = false;
6811                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6812                                 SECONDARY_EXEC_SHADOW_VMCS);
6813                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6814         }
6815         vmx->nested.posted_intr_nv = -1;
6816         kunmap(vmx->nested.current_vmcs12_page);
6817         nested_release_page(vmx->nested.current_vmcs12_page);
6818         vmx->nested.current_vmptr = -1ull;
6819         vmx->nested.current_vmcs12 = NULL;
6820 }
6821
6822 /*
6823  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6824  * just stops using VMX.
6825  */
6826 static void free_nested(struct vcpu_vmx *vmx)
6827 {
6828         if (!vmx->nested.vmxon)
6829                 return;
6830
6831         vmx->nested.vmxon = false;
6832         free_vpid(vmx->nested.vpid02);
6833         nested_release_vmcs12(vmx);
6834         if (enable_shadow_vmcs)
6835                 free_vmcs(vmx->nested.current_shadow_vmcs);
6836         /* Unpin physical memory we referred to in current vmcs02 */
6837         if (vmx->nested.apic_access_page) {
6838                 nested_release_page(vmx->nested.apic_access_page);
6839                 vmx->nested.apic_access_page = NULL;
6840         }
6841         if (vmx->nested.virtual_apic_page) {
6842                 nested_release_page(vmx->nested.virtual_apic_page);
6843                 vmx->nested.virtual_apic_page = NULL;
6844         }
6845         if (vmx->nested.pi_desc_page) {
6846                 kunmap(vmx->nested.pi_desc_page);
6847                 nested_release_page(vmx->nested.pi_desc_page);
6848                 vmx->nested.pi_desc_page = NULL;
6849                 vmx->nested.pi_desc = NULL;
6850         }
6851
6852         nested_free_all_saved_vmcss(vmx);
6853 }
6854
6855 /* Emulate the VMXOFF instruction */
6856 static int handle_vmoff(struct kvm_vcpu *vcpu)
6857 {
6858         if (!nested_vmx_check_permission(vcpu))
6859                 return 1;
6860         free_nested(to_vmx(vcpu));
6861         skip_emulated_instruction(vcpu);
6862         nested_vmx_succeed(vcpu);
6863         return 1;
6864 }
6865
6866 /* Emulate the VMCLEAR instruction */
6867 static int handle_vmclear(struct kvm_vcpu *vcpu)
6868 {
6869         struct vcpu_vmx *vmx = to_vmx(vcpu);
6870         gpa_t vmptr;
6871         struct vmcs12 *vmcs12;
6872         struct page *page;
6873
6874         if (!nested_vmx_check_permission(vcpu))
6875                 return 1;
6876
6877         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6878                 return 1;
6879
6880         if (vmptr == vmx->nested.current_vmptr)
6881                 nested_release_vmcs12(vmx);
6882
6883         page = nested_get_page(vcpu, vmptr);
6884         if (page == NULL) {
6885                 /*
6886                  * For accurate processor emulation, VMCLEAR beyond available
6887                  * physical memory should do nothing at all. However, it is
6888                  * possible that a nested vmx bug, not a guest hypervisor bug,
6889                  * resulted in this case, so let's shut down before doing any
6890                  * more damage:
6891                  */
6892                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6893                 return 1;
6894         }
6895         vmcs12 = kmap(page);
6896         vmcs12->launch_state = 0;
6897         kunmap(page);
6898         nested_release_page(page);
6899
6900         nested_free_vmcs02(vmx, vmptr);
6901
6902         skip_emulated_instruction(vcpu);
6903         nested_vmx_succeed(vcpu);
6904         return 1;
6905 }
6906
6907 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6908
6909 /* Emulate the VMLAUNCH instruction */
6910 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6911 {
6912         return nested_vmx_run(vcpu, true);
6913 }
6914
6915 /* Emulate the VMRESUME instruction */
6916 static int handle_vmresume(struct kvm_vcpu *vcpu)
6917 {
6918
6919         return nested_vmx_run(vcpu, false);
6920 }
6921
6922 enum vmcs_field_type {
6923         VMCS_FIELD_TYPE_U16 = 0,
6924         VMCS_FIELD_TYPE_U64 = 1,
6925         VMCS_FIELD_TYPE_U32 = 2,
6926         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6927 };
6928
6929 static inline int vmcs_field_type(unsigned long field)
6930 {
6931         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6932                 return VMCS_FIELD_TYPE_U32;
6933         return (field >> 13) & 0x3 ;
6934 }
6935
6936 static inline int vmcs_field_readonly(unsigned long field)
6937 {
6938         return (((field >> 10) & 0x3) == 1);
6939 }
6940
6941 /*
6942  * Read a vmcs12 field. Since these can have varying lengths and we return
6943  * one type, we chose the biggest type (u64) and zero-extend the return value
6944  * to that size. Note that the caller, handle_vmread, might need to use only
6945  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6946  * 64-bit fields are to be returned).
6947  */
6948 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6949                                   unsigned long field, u64 *ret)
6950 {
6951         short offset = vmcs_field_to_offset(field);
6952         char *p;
6953
6954         if (offset < 0)
6955                 return offset;
6956
6957         p = ((char *)(get_vmcs12(vcpu))) + offset;
6958
6959         switch (vmcs_field_type(field)) {
6960         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6961                 *ret = *((natural_width *)p);
6962                 return 0;
6963         case VMCS_FIELD_TYPE_U16:
6964                 *ret = *((u16 *)p);
6965                 return 0;
6966         case VMCS_FIELD_TYPE_U32:
6967                 *ret = *((u32 *)p);
6968                 return 0;
6969         case VMCS_FIELD_TYPE_U64:
6970                 *ret = *((u64 *)p);
6971                 return 0;
6972         default:
6973                 WARN_ON(1);
6974                 return -ENOENT;
6975         }
6976 }
6977
6978
6979 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6980                                    unsigned long field, u64 field_value){
6981         short offset = vmcs_field_to_offset(field);
6982         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6983         if (offset < 0)
6984                 return offset;
6985
6986         switch (vmcs_field_type(field)) {
6987         case VMCS_FIELD_TYPE_U16:
6988                 *(u16 *)p = field_value;
6989                 return 0;
6990         case VMCS_FIELD_TYPE_U32:
6991                 *(u32 *)p = field_value;
6992                 return 0;
6993         case VMCS_FIELD_TYPE_U64:
6994                 *(u64 *)p = field_value;
6995                 return 0;
6996         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6997                 *(natural_width *)p = field_value;
6998                 return 0;
6999         default:
7000                 WARN_ON(1);
7001                 return -ENOENT;
7002         }
7003
7004 }
7005
7006 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7007 {
7008         int i;
7009         unsigned long field;
7010         u64 field_value;
7011         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7012         const unsigned long *fields = shadow_read_write_fields;
7013         const int num_fields = max_shadow_read_write_fields;
7014
7015         preempt_disable();
7016
7017         vmcs_load(shadow_vmcs);
7018
7019         for (i = 0; i < num_fields; i++) {
7020                 field = fields[i];
7021                 switch (vmcs_field_type(field)) {
7022                 case VMCS_FIELD_TYPE_U16:
7023                         field_value = vmcs_read16(field);
7024                         break;
7025                 case VMCS_FIELD_TYPE_U32:
7026                         field_value = vmcs_read32(field);
7027                         break;
7028                 case VMCS_FIELD_TYPE_U64:
7029                         field_value = vmcs_read64(field);
7030                         break;
7031                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7032                         field_value = vmcs_readl(field);
7033                         break;
7034                 default:
7035                         WARN_ON(1);
7036                         continue;
7037                 }
7038                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7039         }
7040
7041         vmcs_clear(shadow_vmcs);
7042         vmcs_load(vmx->loaded_vmcs->vmcs);
7043
7044         preempt_enable();
7045 }
7046
7047 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7048 {
7049         const unsigned long *fields[] = {
7050                 shadow_read_write_fields,
7051                 shadow_read_only_fields
7052         };
7053         const int max_fields[] = {
7054                 max_shadow_read_write_fields,
7055                 max_shadow_read_only_fields
7056         };
7057         int i, q;
7058         unsigned long field;
7059         u64 field_value = 0;
7060         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7061
7062         vmcs_load(shadow_vmcs);
7063
7064         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7065                 for (i = 0; i < max_fields[q]; i++) {
7066                         field = fields[q][i];
7067                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7068
7069                         switch (vmcs_field_type(field)) {
7070                         case VMCS_FIELD_TYPE_U16:
7071                                 vmcs_write16(field, (u16)field_value);
7072                                 break;
7073                         case VMCS_FIELD_TYPE_U32:
7074                                 vmcs_write32(field, (u32)field_value);
7075                                 break;
7076                         case VMCS_FIELD_TYPE_U64:
7077                                 vmcs_write64(field, (u64)field_value);
7078                                 break;
7079                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7080                                 vmcs_writel(field, (long)field_value);
7081                                 break;
7082                         default:
7083                                 WARN_ON(1);
7084                                 break;
7085                         }
7086                 }
7087         }
7088
7089         vmcs_clear(shadow_vmcs);
7090         vmcs_load(vmx->loaded_vmcs->vmcs);
7091 }
7092
7093 /*
7094  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7095  * used before) all generate the same failure when it is missing.
7096  */
7097 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7098 {
7099         struct vcpu_vmx *vmx = to_vmx(vcpu);
7100         if (vmx->nested.current_vmptr == -1ull) {
7101                 nested_vmx_failInvalid(vcpu);
7102                 skip_emulated_instruction(vcpu);
7103                 return 0;
7104         }
7105         return 1;
7106 }
7107
7108 static int handle_vmread(struct kvm_vcpu *vcpu)
7109 {
7110         unsigned long field;
7111         u64 field_value;
7112         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7113         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7114         gva_t gva = 0;
7115
7116         if (!nested_vmx_check_permission(vcpu) ||
7117             !nested_vmx_check_vmcs12(vcpu))
7118                 return 1;
7119
7120         /* Decode instruction info and find the field to read */
7121         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7122         /* Read the field, zero-extended to a u64 field_value */
7123         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7124                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7125                 skip_emulated_instruction(vcpu);
7126                 return 1;
7127         }
7128         /*
7129          * Now copy part of this value to register or memory, as requested.
7130          * Note that the number of bits actually copied is 32 or 64 depending
7131          * on the guest's mode (32 or 64 bit), not on the given field's length.
7132          */
7133         if (vmx_instruction_info & (1u << 10)) {
7134                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7135                         field_value);
7136         } else {
7137                 if (get_vmx_mem_address(vcpu, exit_qualification,
7138                                 vmx_instruction_info, true, &gva))
7139                         return 1;
7140                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7141                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7142                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7143         }
7144
7145         nested_vmx_succeed(vcpu);
7146         skip_emulated_instruction(vcpu);
7147         return 1;
7148 }
7149
7150
7151 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7152 {
7153         unsigned long field;
7154         gva_t gva;
7155         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7156         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7157         /* The value to write might be 32 or 64 bits, depending on L1's long
7158          * mode, and eventually we need to write that into a field of several
7159          * possible lengths. The code below first zero-extends the value to 64
7160          * bit (field_value), and then copies only the approriate number of
7161          * bits into the vmcs12 field.
7162          */
7163         u64 field_value = 0;
7164         struct x86_exception e;
7165
7166         if (!nested_vmx_check_permission(vcpu) ||
7167             !nested_vmx_check_vmcs12(vcpu))
7168                 return 1;
7169
7170         if (vmx_instruction_info & (1u << 10))
7171                 field_value = kvm_register_readl(vcpu,
7172                         (((vmx_instruction_info) >> 3) & 0xf));
7173         else {
7174                 if (get_vmx_mem_address(vcpu, exit_qualification,
7175                                 vmx_instruction_info, false, &gva))
7176                         return 1;
7177                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7178                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7179                         kvm_inject_page_fault(vcpu, &e);
7180                         return 1;
7181                 }
7182         }
7183
7184
7185         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7186         if (vmcs_field_readonly(field)) {
7187                 nested_vmx_failValid(vcpu,
7188                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7189                 skip_emulated_instruction(vcpu);
7190                 return 1;
7191         }
7192
7193         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7194                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7195                 skip_emulated_instruction(vcpu);
7196                 return 1;
7197         }
7198
7199         nested_vmx_succeed(vcpu);
7200         skip_emulated_instruction(vcpu);
7201         return 1;
7202 }
7203
7204 /* Emulate the VMPTRLD instruction */
7205 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7206 {
7207         struct vcpu_vmx *vmx = to_vmx(vcpu);
7208         gpa_t vmptr;
7209
7210         if (!nested_vmx_check_permission(vcpu))
7211                 return 1;
7212
7213         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7214                 return 1;
7215
7216         if (vmx->nested.current_vmptr != vmptr) {
7217                 struct vmcs12 *new_vmcs12;
7218                 struct page *page;
7219                 page = nested_get_page(vcpu, vmptr);
7220                 if (page == NULL) {
7221                         nested_vmx_failInvalid(vcpu);
7222                         skip_emulated_instruction(vcpu);
7223                         return 1;
7224                 }
7225                 new_vmcs12 = kmap(page);
7226                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7227                         kunmap(page);
7228                         nested_release_page_clean(page);
7229                         nested_vmx_failValid(vcpu,
7230                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7231                         skip_emulated_instruction(vcpu);
7232                         return 1;
7233                 }
7234
7235                 nested_release_vmcs12(vmx);
7236                 vmx->nested.current_vmptr = vmptr;
7237                 vmx->nested.current_vmcs12 = new_vmcs12;
7238                 vmx->nested.current_vmcs12_page = page;
7239                 if (enable_shadow_vmcs) {
7240                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7241                                       SECONDARY_EXEC_SHADOW_VMCS);
7242                         vmcs_write64(VMCS_LINK_POINTER,
7243                                      __pa(vmx->nested.current_shadow_vmcs));
7244                         vmx->nested.sync_shadow_vmcs = true;
7245                 }
7246         }
7247
7248         nested_vmx_succeed(vcpu);
7249         skip_emulated_instruction(vcpu);
7250         return 1;
7251 }
7252
7253 /* Emulate the VMPTRST instruction */
7254 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7255 {
7256         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7257         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7258         gva_t vmcs_gva;
7259         struct x86_exception e;
7260
7261         if (!nested_vmx_check_permission(vcpu))
7262                 return 1;
7263
7264         if (get_vmx_mem_address(vcpu, exit_qualification,
7265                         vmx_instruction_info, true, &vmcs_gva))
7266                 return 1;
7267         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7268         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7269                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7270                                  sizeof(u64), &e)) {
7271                 kvm_inject_page_fault(vcpu, &e);
7272                 return 1;
7273         }
7274         nested_vmx_succeed(vcpu);
7275         skip_emulated_instruction(vcpu);
7276         return 1;
7277 }
7278
7279 /* Emulate the INVEPT instruction */
7280 static int handle_invept(struct kvm_vcpu *vcpu)
7281 {
7282         struct vcpu_vmx *vmx = to_vmx(vcpu);
7283         u32 vmx_instruction_info, types;
7284         unsigned long type;
7285         gva_t gva;
7286         struct x86_exception e;
7287         struct {
7288                 u64 eptp, gpa;
7289         } operand;
7290
7291         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7292               SECONDARY_EXEC_ENABLE_EPT) ||
7293             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7294                 kvm_queue_exception(vcpu, UD_VECTOR);
7295                 return 1;
7296         }
7297
7298         if (!nested_vmx_check_permission(vcpu))
7299                 return 1;
7300
7301         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7302                 kvm_queue_exception(vcpu, UD_VECTOR);
7303                 return 1;
7304         }
7305
7306         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7307         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7308
7309         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7310
7311         if (!(types & (1UL << type))) {
7312                 nested_vmx_failValid(vcpu,
7313                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7314                 return 1;
7315         }
7316
7317         /* According to the Intel VMX instruction reference, the memory
7318          * operand is read even if it isn't needed (e.g., for type==global)
7319          */
7320         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7321                         vmx_instruction_info, false, &gva))
7322                 return 1;
7323         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7324                                 sizeof(operand), &e)) {
7325                 kvm_inject_page_fault(vcpu, &e);
7326                 return 1;
7327         }
7328
7329         switch (type) {
7330         case VMX_EPT_EXTENT_GLOBAL:
7331                 kvm_mmu_sync_roots(vcpu);
7332                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7333                 nested_vmx_succeed(vcpu);
7334                 break;
7335         default:
7336                 /* Trap single context invalidation invept calls */
7337                 BUG_ON(1);
7338                 break;
7339         }
7340
7341         skip_emulated_instruction(vcpu);
7342         return 1;
7343 }
7344
7345 static int handle_invvpid(struct kvm_vcpu *vcpu)
7346 {
7347         struct vcpu_vmx *vmx = to_vmx(vcpu);
7348         u32 vmx_instruction_info;
7349         unsigned long type, types;
7350         gva_t gva;
7351         struct x86_exception e;
7352         int vpid;
7353
7354         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7355               SECONDARY_EXEC_ENABLE_VPID) ||
7356                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7357                 kvm_queue_exception(vcpu, UD_VECTOR);
7358                 return 1;
7359         }
7360
7361         if (!nested_vmx_check_permission(vcpu))
7362                 return 1;
7363
7364         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7365         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7366
7367         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7368
7369         if (!(types & (1UL << type))) {
7370                 nested_vmx_failValid(vcpu,
7371                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7372                 return 1;
7373         }
7374
7375         /* according to the intel vmx instruction reference, the memory
7376          * operand is read even if it isn't needed (e.g., for type==global)
7377          */
7378         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7379                         vmx_instruction_info, false, &gva))
7380                 return 1;
7381         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7382                                 sizeof(u32), &e)) {
7383                 kvm_inject_page_fault(vcpu, &e);
7384                 return 1;
7385         }
7386
7387         switch (type) {
7388         case VMX_VPID_EXTENT_ALL_CONTEXT:
7389                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7390                 nested_vmx_succeed(vcpu);
7391                 break;
7392         default:
7393                 /* Trap single context invalidation invvpid calls */
7394                 BUG_ON(1);
7395                 break;
7396         }
7397
7398         skip_emulated_instruction(vcpu);
7399         return 1;
7400 }
7401
7402 static int handle_pml_full(struct kvm_vcpu *vcpu)
7403 {
7404         unsigned long exit_qualification;
7405
7406         trace_kvm_pml_full(vcpu->vcpu_id);
7407
7408         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7409
7410         /*
7411          * PML buffer FULL happened while executing iret from NMI,
7412          * "blocked by NMI" bit has to be set before next VM entry.
7413          */
7414         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7415                         cpu_has_virtual_nmis() &&
7416                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7417                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7418                                 GUEST_INTR_STATE_NMI);
7419
7420         /*
7421          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7422          * here.., and there's no userspace involvement needed for PML.
7423          */
7424         return 1;
7425 }
7426
7427 static int handle_pcommit(struct kvm_vcpu *vcpu)
7428 {
7429         /* we never catch pcommit instruct for L1 guest. */
7430         WARN_ON(1);
7431         return 1;
7432 }
7433
7434 /*
7435  * The exit handlers return 1 if the exit was handled fully and guest execution
7436  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7437  * to be done to userspace and return 0.
7438  */
7439 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7440         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7441         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7442         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7443         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7444         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7445         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7446         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7447         [EXIT_REASON_CPUID]                   = handle_cpuid,
7448         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7449         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7450         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7451         [EXIT_REASON_HLT]                     = handle_halt,
7452         [EXIT_REASON_INVD]                    = handle_invd,
7453         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7454         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7455         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7456         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7457         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7458         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7459         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7460         [EXIT_REASON_VMREAD]                  = handle_vmread,
7461         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7462         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7463         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7464         [EXIT_REASON_VMON]                    = handle_vmon,
7465         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7466         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7467         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7468         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7469         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7470         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7471         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7472         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7473         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7474         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7475         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7476         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7477         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7478         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7479         [EXIT_REASON_INVEPT]                  = handle_invept,
7480         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7481         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7482         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7483         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7484         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7485 };
7486
7487 static const int kvm_vmx_max_exit_handlers =
7488         ARRAY_SIZE(kvm_vmx_exit_handlers);
7489
7490 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7491                                        struct vmcs12 *vmcs12)
7492 {
7493         unsigned long exit_qualification;
7494         gpa_t bitmap, last_bitmap;
7495         unsigned int port;
7496         int size;
7497         u8 b;
7498
7499         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7500                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7501
7502         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7503
7504         port = exit_qualification >> 16;
7505         size = (exit_qualification & 7) + 1;
7506
7507         last_bitmap = (gpa_t)-1;
7508         b = -1;
7509
7510         while (size > 0) {
7511                 if (port < 0x8000)
7512                         bitmap = vmcs12->io_bitmap_a;
7513                 else if (port < 0x10000)
7514                         bitmap = vmcs12->io_bitmap_b;
7515                 else
7516                         return true;
7517                 bitmap += (port & 0x7fff) / 8;
7518
7519                 if (last_bitmap != bitmap)
7520                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7521                                 return true;
7522                 if (b & (1 << (port & 7)))
7523                         return true;
7524
7525                 port++;
7526                 size--;
7527                 last_bitmap = bitmap;
7528         }
7529
7530         return false;
7531 }
7532
7533 /*
7534  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7535  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7536  * disinterest in the current event (read or write a specific MSR) by using an
7537  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7538  */
7539 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7540         struct vmcs12 *vmcs12, u32 exit_reason)
7541 {
7542         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7543         gpa_t bitmap;
7544
7545         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7546                 return true;
7547
7548         /*
7549          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7550          * for the four combinations of read/write and low/high MSR numbers.
7551          * First we need to figure out which of the four to use:
7552          */
7553         bitmap = vmcs12->msr_bitmap;
7554         if (exit_reason == EXIT_REASON_MSR_WRITE)
7555                 bitmap += 2048;
7556         if (msr_index >= 0xc0000000) {
7557                 msr_index -= 0xc0000000;
7558                 bitmap += 1024;
7559         }
7560
7561         /* Then read the msr_index'th bit from this bitmap: */
7562         if (msr_index < 1024*8) {
7563                 unsigned char b;
7564                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7565                         return true;
7566                 return 1 & (b >> (msr_index & 7));
7567         } else
7568                 return true; /* let L1 handle the wrong parameter */
7569 }
7570
7571 /*
7572  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7573  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7574  * intercept (via guest_host_mask etc.) the current event.
7575  */
7576 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7577         struct vmcs12 *vmcs12)
7578 {
7579         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7580         int cr = exit_qualification & 15;
7581         int reg = (exit_qualification >> 8) & 15;
7582         unsigned long val = kvm_register_readl(vcpu, reg);
7583
7584         switch ((exit_qualification >> 4) & 3) {
7585         case 0: /* mov to cr */
7586                 switch (cr) {
7587                 case 0:
7588                         if (vmcs12->cr0_guest_host_mask &
7589                             (val ^ vmcs12->cr0_read_shadow))
7590                                 return true;
7591                         break;
7592                 case 3:
7593                         if ((vmcs12->cr3_target_count >= 1 &&
7594                                         vmcs12->cr3_target_value0 == val) ||
7595                                 (vmcs12->cr3_target_count >= 2 &&
7596                                         vmcs12->cr3_target_value1 == val) ||
7597                                 (vmcs12->cr3_target_count >= 3 &&
7598                                         vmcs12->cr3_target_value2 == val) ||
7599                                 (vmcs12->cr3_target_count >= 4 &&
7600                                         vmcs12->cr3_target_value3 == val))
7601                                 return false;
7602                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7603                                 return true;
7604                         break;
7605                 case 4:
7606                         if (vmcs12->cr4_guest_host_mask &
7607                             (vmcs12->cr4_read_shadow ^ val))
7608                                 return true;
7609                         break;
7610                 case 8:
7611                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7612                                 return true;
7613                         break;
7614                 }
7615                 break;
7616         case 2: /* clts */
7617                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7618                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7619                         return true;
7620                 break;
7621         case 1: /* mov from cr */
7622                 switch (cr) {
7623                 case 3:
7624                         if (vmcs12->cpu_based_vm_exec_control &
7625                             CPU_BASED_CR3_STORE_EXITING)
7626                                 return true;
7627                         break;
7628                 case 8:
7629                         if (vmcs12->cpu_based_vm_exec_control &
7630                             CPU_BASED_CR8_STORE_EXITING)
7631                                 return true;
7632                         break;
7633                 }
7634                 break;
7635         case 3: /* lmsw */
7636                 /*
7637                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7638                  * cr0. Other attempted changes are ignored, with no exit.
7639                  */
7640                 if (vmcs12->cr0_guest_host_mask & 0xe &
7641                     (val ^ vmcs12->cr0_read_shadow))
7642                         return true;
7643                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7644                     !(vmcs12->cr0_read_shadow & 0x1) &&
7645                     (val & 0x1))
7646                         return true;
7647                 break;
7648         }
7649         return false;
7650 }
7651
7652 /*
7653  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7654  * should handle it ourselves in L0 (and then continue L2). Only call this
7655  * when in is_guest_mode (L2).
7656  */
7657 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7658 {
7659         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7660         struct vcpu_vmx *vmx = to_vmx(vcpu);
7661         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7662         u32 exit_reason = vmx->exit_reason;
7663
7664         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7665                                 vmcs_readl(EXIT_QUALIFICATION),
7666                                 vmx->idt_vectoring_info,
7667                                 intr_info,
7668                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7669                                 KVM_ISA_VMX);
7670
7671         if (vmx->nested.nested_run_pending)
7672                 return false;
7673
7674         if (unlikely(vmx->fail)) {
7675                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7676                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7677                 return true;
7678         }
7679
7680         switch (exit_reason) {
7681         case EXIT_REASON_EXCEPTION_NMI:
7682                 if (!is_exception(intr_info))
7683                         return false;
7684                 else if (is_page_fault(intr_info))
7685                         return enable_ept;
7686                 else if (is_no_device(intr_info) &&
7687                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7688                         return false;
7689                 return vmcs12->exception_bitmap &
7690                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7691         case EXIT_REASON_EXTERNAL_INTERRUPT:
7692                 return false;
7693         case EXIT_REASON_TRIPLE_FAULT:
7694                 return true;
7695         case EXIT_REASON_PENDING_INTERRUPT:
7696                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7697         case EXIT_REASON_NMI_WINDOW:
7698                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7699         case EXIT_REASON_TASK_SWITCH:
7700                 return true;
7701         case EXIT_REASON_CPUID:
7702                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7703                         return false;
7704                 return true;
7705         case EXIT_REASON_HLT:
7706                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7707         case EXIT_REASON_INVD:
7708                 return true;
7709         case EXIT_REASON_INVLPG:
7710                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7711         case EXIT_REASON_RDPMC:
7712                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7713         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7714                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7715         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7716         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7717         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7718         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7719         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7720         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7721                 /*
7722                  * VMX instructions trap unconditionally. This allows L1 to
7723                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7724                  */
7725                 return true;
7726         case EXIT_REASON_CR_ACCESS:
7727                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7728         case EXIT_REASON_DR_ACCESS:
7729                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7730         case EXIT_REASON_IO_INSTRUCTION:
7731                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7732         case EXIT_REASON_MSR_READ:
7733         case EXIT_REASON_MSR_WRITE:
7734                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7735         case EXIT_REASON_INVALID_STATE:
7736                 return true;
7737         case EXIT_REASON_MWAIT_INSTRUCTION:
7738                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7739         case EXIT_REASON_MONITOR_TRAP_FLAG:
7740                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7741         case EXIT_REASON_MONITOR_INSTRUCTION:
7742                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7743         case EXIT_REASON_PAUSE_INSTRUCTION:
7744                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7745                         nested_cpu_has2(vmcs12,
7746                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7747         case EXIT_REASON_MCE_DURING_VMENTRY:
7748                 return false;
7749         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7750                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7751         case EXIT_REASON_APIC_ACCESS:
7752                 return nested_cpu_has2(vmcs12,
7753                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7754         case EXIT_REASON_APIC_WRITE:
7755         case EXIT_REASON_EOI_INDUCED:
7756                 /* apic_write and eoi_induced should exit unconditionally. */
7757                 return true;
7758         case EXIT_REASON_EPT_VIOLATION:
7759                 /*
7760                  * L0 always deals with the EPT violation. If nested EPT is
7761                  * used, and the nested mmu code discovers that the address is
7762                  * missing in the guest EPT table (EPT12), the EPT violation
7763                  * will be injected with nested_ept_inject_page_fault()
7764                  */
7765                 return false;
7766         case EXIT_REASON_EPT_MISCONFIG:
7767                 /*
7768                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7769                  * table (shadow on EPT) or a merged EPT table that L0 built
7770                  * (EPT on EPT). So any problems with the structure of the
7771                  * table is L0's fault.
7772                  */
7773                 return false;
7774         case EXIT_REASON_WBINVD:
7775                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7776         case EXIT_REASON_XSETBV:
7777                 return true;
7778         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7779                 /*
7780                  * This should never happen, since it is not possible to
7781                  * set XSS to a non-zero value---neither in L1 nor in L2.
7782                  * If if it were, XSS would have to be checked against
7783                  * the XSS exit bitmap in vmcs12.
7784                  */
7785                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7786         case EXIT_REASON_PCOMMIT:
7787                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7788         default:
7789                 return true;
7790         }
7791 }
7792
7793 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7794 {
7795         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7796         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7797 }
7798
7799 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7800 {
7801         struct page *pml_pg;
7802
7803         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7804         if (!pml_pg)
7805                 return -ENOMEM;
7806
7807         vmx->pml_pg = pml_pg;
7808
7809         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7810         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7811
7812         return 0;
7813 }
7814
7815 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7816 {
7817         if (vmx->pml_pg) {
7818                 __free_page(vmx->pml_pg);
7819                 vmx->pml_pg = NULL;
7820         }
7821 }
7822
7823 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7824 {
7825         struct vcpu_vmx *vmx = to_vmx(vcpu);
7826         u64 *pml_buf;
7827         u16 pml_idx;
7828
7829         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7830
7831         /* Do nothing if PML buffer is empty */
7832         if (pml_idx == (PML_ENTITY_NUM - 1))
7833                 return;
7834
7835         /* PML index always points to next available PML buffer entity */
7836         if (pml_idx >= PML_ENTITY_NUM)
7837                 pml_idx = 0;
7838         else
7839                 pml_idx++;
7840
7841         pml_buf = page_address(vmx->pml_pg);
7842         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7843                 u64 gpa;
7844
7845                 gpa = pml_buf[pml_idx];
7846                 WARN_ON(gpa & (PAGE_SIZE - 1));
7847                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7848         }
7849
7850         /* reset PML index */
7851         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7852 }
7853
7854 /*
7855  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7856  * Called before reporting dirty_bitmap to userspace.
7857  */
7858 static void kvm_flush_pml_buffers(struct kvm *kvm)
7859 {
7860         int i;
7861         struct kvm_vcpu *vcpu;
7862         /*
7863          * We only need to kick vcpu out of guest mode here, as PML buffer
7864          * is flushed at beginning of all VMEXITs, and it's obvious that only
7865          * vcpus running in guest are possible to have unflushed GPAs in PML
7866          * buffer.
7867          */
7868         kvm_for_each_vcpu(i, vcpu, kvm)
7869                 kvm_vcpu_kick(vcpu);
7870 }
7871
7872 static void vmx_dump_sel(char *name, uint32_t sel)
7873 {
7874         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7875                name, vmcs_read32(sel),
7876                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7877                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7878                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7879 }
7880
7881 static void vmx_dump_dtsel(char *name, uint32_t limit)
7882 {
7883         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7884                name, vmcs_read32(limit),
7885                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7886 }
7887
7888 static void dump_vmcs(void)
7889 {
7890         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7891         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7892         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7893         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7894         u32 secondary_exec_control = 0;
7895         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7896         u64 efer = vmcs_read64(GUEST_IA32_EFER);
7897         int i, n;
7898
7899         if (cpu_has_secondary_exec_ctrls())
7900                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7901
7902         pr_err("*** Guest State ***\n");
7903         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7904                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7905                vmcs_readl(CR0_GUEST_HOST_MASK));
7906         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7907                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7908         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7909         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7910             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7911         {
7912                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
7913                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
7914                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
7915                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
7916         }
7917         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7918                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7919         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7920                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7921         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7922                vmcs_readl(GUEST_SYSENTER_ESP),
7923                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7924         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7925         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7926         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7927         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7928         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7929         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7930         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7931         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7932         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7933         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7934         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7935             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7936                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
7937                        efer, vmcs_read64(GUEST_IA32_PAT));
7938         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
7939                vmcs_read64(GUEST_IA32_DEBUGCTL),
7940                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7941         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7942                 pr_err("PerfGlobCtl = 0x%016llx\n",
7943                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
7944         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7945                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
7946         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7947                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7948                vmcs_read32(GUEST_ACTIVITY_STATE));
7949         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7950                 pr_err("InterruptStatus = %04x\n",
7951                        vmcs_read16(GUEST_INTR_STATUS));
7952
7953         pr_err("*** Host State ***\n");
7954         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7955                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7956         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7957                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7958                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7959                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7960                vmcs_read16(HOST_TR_SELECTOR));
7961         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7962                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7963                vmcs_readl(HOST_TR_BASE));
7964         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7965                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7966         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7967                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7968                vmcs_readl(HOST_CR4));
7969         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7970                vmcs_readl(HOST_IA32_SYSENTER_ESP),
7971                vmcs_read32(HOST_IA32_SYSENTER_CS),
7972                vmcs_readl(HOST_IA32_SYSENTER_EIP));
7973         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7974                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
7975                        vmcs_read64(HOST_IA32_EFER),
7976                        vmcs_read64(HOST_IA32_PAT));
7977         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7978                 pr_err("PerfGlobCtl = 0x%016llx\n",
7979                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
7980
7981         pr_err("*** Control State ***\n");
7982         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7983                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7984         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7985         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7986                vmcs_read32(EXCEPTION_BITMAP),
7987                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7988                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7989         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7990                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7991                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7992                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7993         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7994                vmcs_read32(VM_EXIT_INTR_INFO),
7995                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7996                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7997         pr_err("        reason=%08x qualification=%016lx\n",
7998                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7999         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8000                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8001                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8002         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8003         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8004                 pr_err("TSC Multiplier = 0x%016llx\n",
8005                        vmcs_read64(TSC_MULTIPLIER));
8006         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8007                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8008         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8009                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8010         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8011                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8012         n = vmcs_read32(CR3_TARGET_COUNT);
8013         for (i = 0; i + 1 < n; i += 4)
8014                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8015                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8016                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8017         if (i < n)
8018                 pr_err("CR3 target%u=%016lx\n",
8019                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8020         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8021                 pr_err("PLE Gap=%08x Window=%08x\n",
8022                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8023         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8024                 pr_err("Virtual processor ID = 0x%04x\n",
8025                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8026 }
8027
8028 /*
8029  * The guest has exited.  See if we can fix it or if we need userspace
8030  * assistance.
8031  */
8032 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8033 {
8034         struct vcpu_vmx *vmx = to_vmx(vcpu);
8035         u32 exit_reason = vmx->exit_reason;
8036         u32 vectoring_info = vmx->idt_vectoring_info;
8037
8038         /*
8039          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8040          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8041          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8042          * mode as if vcpus is in root mode, the PML buffer must has been
8043          * flushed already.
8044          */
8045         if (enable_pml)
8046                 vmx_flush_pml_buffer(vcpu);
8047
8048         /* If guest state is invalid, start emulating */
8049         if (vmx->emulation_required)
8050                 return handle_invalid_guest_state(vcpu);
8051
8052         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8053                 nested_vmx_vmexit(vcpu, exit_reason,
8054                                   vmcs_read32(VM_EXIT_INTR_INFO),
8055                                   vmcs_readl(EXIT_QUALIFICATION));
8056                 return 1;
8057         }
8058
8059         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8060                 dump_vmcs();
8061                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8062                 vcpu->run->fail_entry.hardware_entry_failure_reason
8063                         = exit_reason;
8064                 return 0;
8065         }
8066
8067         if (unlikely(vmx->fail)) {
8068                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8069                 vcpu->run->fail_entry.hardware_entry_failure_reason
8070                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8071                 return 0;
8072         }
8073
8074         /*
8075          * Note:
8076          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8077          * delivery event since it indicates guest is accessing MMIO.
8078          * The vm-exit can be triggered again after return to guest that
8079          * will cause infinite loop.
8080          */
8081         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8082                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8083                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8084                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8085                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8086                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8087                 vcpu->run->internal.ndata = 2;
8088                 vcpu->run->internal.data[0] = vectoring_info;
8089                 vcpu->run->internal.data[1] = exit_reason;
8090                 return 0;
8091         }
8092
8093         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8094             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8095                                         get_vmcs12(vcpu))))) {
8096                 if (vmx_interrupt_allowed(vcpu)) {
8097                         vmx->soft_vnmi_blocked = 0;
8098                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8099                            vcpu->arch.nmi_pending) {
8100                         /*
8101                          * This CPU don't support us in finding the end of an
8102                          * NMI-blocked window if the guest runs with IRQs
8103                          * disabled. So we pull the trigger after 1 s of
8104                          * futile waiting, but inform the user about this.
8105                          */
8106                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8107                                "state on VCPU %d after 1 s timeout\n",
8108                                __func__, vcpu->vcpu_id);
8109                         vmx->soft_vnmi_blocked = 0;
8110                 }
8111         }
8112
8113         if (exit_reason < kvm_vmx_max_exit_handlers
8114             && kvm_vmx_exit_handlers[exit_reason])
8115                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8116         else {
8117                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8118                 kvm_queue_exception(vcpu, UD_VECTOR);
8119                 return 1;
8120         }
8121 }
8122
8123 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8124 {
8125         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8126
8127         if (is_guest_mode(vcpu) &&
8128                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8129                 return;
8130
8131         if (irr == -1 || tpr < irr) {
8132                 vmcs_write32(TPR_THRESHOLD, 0);
8133                 return;
8134         }
8135
8136         vmcs_write32(TPR_THRESHOLD, irr);
8137 }
8138
8139 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8140 {
8141         u32 sec_exec_control;
8142
8143         /*
8144          * There is not point to enable virtualize x2apic without enable
8145          * apicv
8146          */
8147         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8148                                 !kvm_vcpu_apicv_active(vcpu))
8149                 return;
8150
8151         if (!cpu_need_tpr_shadow(vcpu))
8152                 return;
8153
8154         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8155
8156         if (set) {
8157                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8158                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8159         } else {
8160                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8161                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8162         }
8163         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8164
8165         vmx_set_msr_bitmap(vcpu);
8166 }
8167
8168 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8169 {
8170         struct vcpu_vmx *vmx = to_vmx(vcpu);
8171
8172         /*
8173          * Currently we do not handle the nested case where L2 has an
8174          * APIC access page of its own; that page is still pinned.
8175          * Hence, we skip the case where the VCPU is in guest mode _and_
8176          * L1 prepared an APIC access page for L2.
8177          *
8178          * For the case where L1 and L2 share the same APIC access page
8179          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8180          * in the vmcs12), this function will only update either the vmcs01
8181          * or the vmcs02.  If the former, the vmcs02 will be updated by
8182          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8183          * the next L2->L1 exit.
8184          */
8185         if (!is_guest_mode(vcpu) ||
8186             !nested_cpu_has2(vmx->nested.current_vmcs12,
8187                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8188                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8189 }
8190
8191 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8192 {
8193         u16 status;
8194         u8 old;
8195
8196         if (isr == -1)
8197                 isr = 0;
8198
8199         status = vmcs_read16(GUEST_INTR_STATUS);
8200         old = status >> 8;
8201         if (isr != old) {
8202                 status &= 0xff;
8203                 status |= isr << 8;
8204                 vmcs_write16(GUEST_INTR_STATUS, status);
8205         }
8206 }
8207
8208 static void vmx_set_rvi(int vector)
8209 {
8210         u16 status;
8211         u8 old;
8212
8213         if (vector == -1)
8214                 vector = 0;
8215
8216         status = vmcs_read16(GUEST_INTR_STATUS);
8217         old = (u8)status & 0xff;
8218         if ((u8)vector != old) {
8219                 status &= ~0xff;
8220                 status |= (u8)vector;
8221                 vmcs_write16(GUEST_INTR_STATUS, status);
8222         }
8223 }
8224
8225 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8226 {
8227         if (!is_guest_mode(vcpu)) {
8228                 vmx_set_rvi(max_irr);
8229                 return;
8230         }
8231
8232         if (max_irr == -1)
8233                 return;
8234
8235         /*
8236          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8237          * handles it.
8238          */
8239         if (nested_exit_on_intr(vcpu))
8240                 return;
8241
8242         /*
8243          * Else, fall back to pre-APICv interrupt injection since L2
8244          * is run without virtual interrupt delivery.
8245          */
8246         if (!kvm_event_needs_reinjection(vcpu) &&
8247             vmx_interrupt_allowed(vcpu)) {
8248                 kvm_queue_interrupt(vcpu, max_irr, false);
8249                 vmx_inject_irq(vcpu);
8250         }
8251 }
8252
8253 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8254 {
8255         if (!kvm_vcpu_apicv_active(vcpu))
8256                 return;
8257
8258         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8259         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8260         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8261         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8262 }
8263
8264 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8265 {
8266         u32 exit_intr_info;
8267
8268         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8269               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8270                 return;
8271
8272         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8273         exit_intr_info = vmx->exit_intr_info;
8274
8275         /* Handle machine checks before interrupts are enabled */
8276         if (is_machine_check(exit_intr_info))
8277                 kvm_machine_check();
8278
8279         /* We need to handle NMIs before interrupts are enabled */
8280         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8281             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8282                 kvm_before_handle_nmi(&vmx->vcpu);
8283                 asm("int $2");
8284                 kvm_after_handle_nmi(&vmx->vcpu);
8285         }
8286 }
8287
8288 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8289 {
8290         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8291
8292         /*
8293          * If external interrupt exists, IF bit is set in rflags/eflags on the
8294          * interrupt stack frame, and interrupt will be enabled on a return
8295          * from interrupt handler.
8296          */
8297         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8298                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8299                 unsigned int vector;
8300                 unsigned long entry;
8301                 gate_desc *desc;
8302                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8303 #ifdef CONFIG_X86_64
8304                 unsigned long tmp;
8305 #endif
8306
8307                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8308                 desc = (gate_desc *)vmx->host_idt_base + vector;
8309                 entry = gate_offset(*desc);
8310                 asm volatile(
8311 #ifdef CONFIG_X86_64
8312                         "mov %%" _ASM_SP ", %[sp]\n\t"
8313                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8314                         "push $%c[ss]\n\t"
8315                         "push %[sp]\n\t"
8316 #endif
8317                         "pushf\n\t"
8318                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8319                         __ASM_SIZE(push) " $%c[cs]\n\t"
8320                         "call *%[entry]\n\t"
8321                         :
8322 #ifdef CONFIG_X86_64
8323                         [sp]"=&r"(tmp)
8324 #endif
8325                         :
8326                         [entry]"r"(entry),
8327                         [ss]"i"(__KERNEL_DS),
8328                         [cs]"i"(__KERNEL_CS)
8329                         );
8330         } else
8331                 local_irq_enable();
8332 }
8333
8334 static bool vmx_has_high_real_mode_segbase(void)
8335 {
8336         return enable_unrestricted_guest || emulate_invalid_guest_state;
8337 }
8338
8339 static bool vmx_mpx_supported(void)
8340 {
8341         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8342                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8343 }
8344
8345 static bool vmx_xsaves_supported(void)
8346 {
8347         return vmcs_config.cpu_based_2nd_exec_ctrl &
8348                 SECONDARY_EXEC_XSAVES;
8349 }
8350
8351 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8352 {
8353         u32 exit_intr_info;
8354         bool unblock_nmi;
8355         u8 vector;
8356         bool idtv_info_valid;
8357
8358         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8359
8360         if (cpu_has_virtual_nmis()) {
8361                 if (vmx->nmi_known_unmasked)
8362                         return;
8363                 /*
8364                  * Can't use vmx->exit_intr_info since we're not sure what
8365                  * the exit reason is.
8366                  */
8367                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8368                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8369                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8370                 /*
8371                  * SDM 3: 27.7.1.2 (September 2008)
8372                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8373                  * a guest IRET fault.
8374                  * SDM 3: 23.2.2 (September 2008)
8375                  * Bit 12 is undefined in any of the following cases:
8376                  *  If the VM exit sets the valid bit in the IDT-vectoring
8377                  *   information field.
8378                  *  If the VM exit is due to a double fault.
8379                  */
8380                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8381                     vector != DF_VECTOR && !idtv_info_valid)
8382                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8383                                       GUEST_INTR_STATE_NMI);
8384                 else
8385                         vmx->nmi_known_unmasked =
8386                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8387                                   & GUEST_INTR_STATE_NMI);
8388         } else if (unlikely(vmx->soft_vnmi_blocked))
8389                 vmx->vnmi_blocked_time +=
8390                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8391 }
8392
8393 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8394                                       u32 idt_vectoring_info,
8395                                       int instr_len_field,
8396                                       int error_code_field)
8397 {
8398         u8 vector;
8399         int type;
8400         bool idtv_info_valid;
8401
8402         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8403
8404         vcpu->arch.nmi_injected = false;
8405         kvm_clear_exception_queue(vcpu);
8406         kvm_clear_interrupt_queue(vcpu);
8407
8408         if (!idtv_info_valid)
8409                 return;
8410
8411         kvm_make_request(KVM_REQ_EVENT, vcpu);
8412
8413         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8414         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8415
8416         switch (type) {
8417         case INTR_TYPE_NMI_INTR:
8418                 vcpu->arch.nmi_injected = true;
8419                 /*
8420                  * SDM 3: 27.7.1.2 (September 2008)
8421                  * Clear bit "block by NMI" before VM entry if a NMI
8422                  * delivery faulted.
8423                  */
8424                 vmx_set_nmi_mask(vcpu, false);
8425                 break;
8426         case INTR_TYPE_SOFT_EXCEPTION:
8427                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8428                 /* fall through */
8429         case INTR_TYPE_HARD_EXCEPTION:
8430                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8431                         u32 err = vmcs_read32(error_code_field);
8432                         kvm_requeue_exception_e(vcpu, vector, err);
8433                 } else
8434                         kvm_requeue_exception(vcpu, vector);
8435                 break;
8436         case INTR_TYPE_SOFT_INTR:
8437                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8438                 /* fall through */
8439         case INTR_TYPE_EXT_INTR:
8440                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8441                 break;
8442         default:
8443                 break;
8444         }
8445 }
8446
8447 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8448 {
8449         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8450                                   VM_EXIT_INSTRUCTION_LEN,
8451                                   IDT_VECTORING_ERROR_CODE);
8452 }
8453
8454 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8455 {
8456         __vmx_complete_interrupts(vcpu,
8457                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8458                                   VM_ENTRY_INSTRUCTION_LEN,
8459                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8460
8461         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8462 }
8463
8464 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8465 {
8466         int i, nr_msrs;
8467         struct perf_guest_switch_msr *msrs;
8468
8469         msrs = perf_guest_get_msrs(&nr_msrs);
8470
8471         if (!msrs)
8472                 return;
8473
8474         for (i = 0; i < nr_msrs; i++)
8475                 if (msrs[i].host == msrs[i].guest)
8476                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8477                 else
8478                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8479                                         msrs[i].host);
8480 }
8481
8482 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8483 {
8484         struct vcpu_vmx *vmx = to_vmx(vcpu);
8485         unsigned long debugctlmsr, cr4;
8486
8487         /* Record the guest's net vcpu time for enforced NMI injections. */
8488         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8489                 vmx->entry_time = ktime_get();
8490
8491         /* Don't enter VMX if guest state is invalid, let the exit handler
8492            start emulation until we arrive back to a valid state */
8493         if (vmx->emulation_required)
8494                 return;
8495
8496         if (vmx->ple_window_dirty) {
8497                 vmx->ple_window_dirty = false;
8498                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8499         }
8500
8501         if (vmx->nested.sync_shadow_vmcs) {
8502                 copy_vmcs12_to_shadow(vmx);
8503                 vmx->nested.sync_shadow_vmcs = false;
8504         }
8505
8506         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8507                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8508         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8509                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8510
8511         cr4 = cr4_read_shadow();
8512         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8513                 vmcs_writel(HOST_CR4, cr4);
8514                 vmx->host_state.vmcs_host_cr4 = cr4;
8515         }
8516
8517         /* When single-stepping over STI and MOV SS, we must clear the
8518          * corresponding interruptibility bits in the guest state. Otherwise
8519          * vmentry fails as it then expects bit 14 (BS) in pending debug
8520          * exceptions being set, but that's not correct for the guest debugging
8521          * case. */
8522         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8523                 vmx_set_interrupt_shadow(vcpu, 0);
8524
8525         atomic_switch_perf_msrs(vmx);
8526         debugctlmsr = get_debugctlmsr();
8527
8528         vmx->__launched = vmx->loaded_vmcs->launched;
8529         asm(
8530                 /* Store host registers */
8531                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8532                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8533                 "push %%" _ASM_CX " \n\t"
8534                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8535                 "je 1f \n\t"
8536                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8537                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8538                 "1: \n\t"
8539                 /* Reload cr2 if changed */
8540                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8541                 "mov %%cr2, %%" _ASM_DX " \n\t"
8542                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8543                 "je 2f \n\t"
8544                 "mov %%" _ASM_AX", %%cr2 \n\t"
8545                 "2: \n\t"
8546                 /* Check if vmlaunch of vmresume is needed */
8547                 "cmpl $0, %c[launched](%0) \n\t"
8548                 /* Load guest registers.  Don't clobber flags. */
8549                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8550                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8551                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8552                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8553                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8554                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8555 #ifdef CONFIG_X86_64
8556                 "mov %c[r8](%0),  %%r8  \n\t"
8557                 "mov %c[r9](%0),  %%r9  \n\t"
8558                 "mov %c[r10](%0), %%r10 \n\t"
8559                 "mov %c[r11](%0), %%r11 \n\t"
8560                 "mov %c[r12](%0), %%r12 \n\t"
8561                 "mov %c[r13](%0), %%r13 \n\t"
8562                 "mov %c[r14](%0), %%r14 \n\t"
8563                 "mov %c[r15](%0), %%r15 \n\t"
8564 #endif
8565                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8566
8567                 /* Enter guest mode */
8568                 "jne 1f \n\t"
8569                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8570                 "jmp 2f \n\t"
8571                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8572                 "2: "
8573                 /* Save guest registers, load host registers, keep flags */
8574                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8575                 "pop %0 \n\t"
8576                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8577                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8578                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8579                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8580                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8581                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8582                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8583 #ifdef CONFIG_X86_64
8584                 "mov %%r8,  %c[r8](%0) \n\t"
8585                 "mov %%r9,  %c[r9](%0) \n\t"
8586                 "mov %%r10, %c[r10](%0) \n\t"
8587                 "mov %%r11, %c[r11](%0) \n\t"
8588                 "mov %%r12, %c[r12](%0) \n\t"
8589                 "mov %%r13, %c[r13](%0) \n\t"
8590                 "mov %%r14, %c[r14](%0) \n\t"
8591                 "mov %%r15, %c[r15](%0) \n\t"
8592 #endif
8593                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8594                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8595
8596                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8597                 "setbe %c[fail](%0) \n\t"
8598                 ".pushsection .rodata \n\t"
8599                 ".global vmx_return \n\t"
8600                 "vmx_return: " _ASM_PTR " 2b \n\t"
8601                 ".popsection"
8602               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8603                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8604                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8605                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8606                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8607                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8608                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8609                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8610                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8611                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8612                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8613 #ifdef CONFIG_X86_64
8614                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8615                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8616                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8617                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8618                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8619                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8620                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8621                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8622 #endif
8623                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8624                 [wordsize]"i"(sizeof(ulong))
8625               : "cc", "memory"
8626 #ifdef CONFIG_X86_64
8627                 , "rax", "rbx", "rdi", "rsi"
8628                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8629 #else
8630                 , "eax", "ebx", "edi", "esi"
8631 #endif
8632               );
8633
8634         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8635         if (debugctlmsr)
8636                 update_debugctlmsr(debugctlmsr);
8637
8638 #ifndef CONFIG_X86_64
8639         /*
8640          * The sysexit path does not restore ds/es, so we must set them to
8641          * a reasonable value ourselves.
8642          *
8643          * We can't defer this to vmx_load_host_state() since that function
8644          * may be executed in interrupt context, which saves and restore segments
8645          * around it, nullifying its effect.
8646          */
8647         loadsegment(ds, __USER_DS);
8648         loadsegment(es, __USER_DS);
8649 #endif
8650
8651         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8652                                   | (1 << VCPU_EXREG_RFLAGS)
8653                                   | (1 << VCPU_EXREG_PDPTR)
8654                                   | (1 << VCPU_EXREG_SEGMENTS)
8655                                   | (1 << VCPU_EXREG_CR3));
8656         vcpu->arch.regs_dirty = 0;
8657
8658         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8659
8660         vmx->loaded_vmcs->launched = 1;
8661
8662         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8663         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8664
8665         /*
8666          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8667          * we did not inject a still-pending event to L1 now because of
8668          * nested_run_pending, we need to re-enable this bit.
8669          */
8670         if (vmx->nested.nested_run_pending)
8671                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8672
8673         vmx->nested.nested_run_pending = 0;
8674
8675         vmx_complete_atomic_exit(vmx);
8676         vmx_recover_nmi_blocking(vmx);
8677         vmx_complete_interrupts(vmx);
8678 }
8679
8680 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8681 {
8682         struct vcpu_vmx *vmx = to_vmx(vcpu);
8683         int cpu;
8684
8685         if (vmx->loaded_vmcs == &vmx->vmcs01)
8686                 return;
8687
8688         cpu = get_cpu();
8689         vmx->loaded_vmcs = &vmx->vmcs01;
8690         vmx_vcpu_put(vcpu);
8691         vmx_vcpu_load(vcpu, cpu);
8692         vcpu->cpu = cpu;
8693         put_cpu();
8694 }
8695
8696 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8697 {
8698         struct vcpu_vmx *vmx = to_vmx(vcpu);
8699
8700         if (enable_pml)
8701                 vmx_destroy_pml_buffer(vmx);
8702         free_vpid(vmx->vpid);
8703         leave_guest_mode(vcpu);
8704         vmx_load_vmcs01(vcpu);
8705         free_nested(vmx);
8706         free_loaded_vmcs(vmx->loaded_vmcs);
8707         kfree(vmx->guest_msrs);
8708         kvm_vcpu_uninit(vcpu);
8709         kmem_cache_free(kvm_vcpu_cache, vmx);
8710 }
8711
8712 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8713 {
8714         int err;
8715         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8716         int cpu;
8717
8718         if (!vmx)
8719                 return ERR_PTR(-ENOMEM);
8720
8721         vmx->vpid = allocate_vpid();
8722
8723         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8724         if (err)
8725                 goto free_vcpu;
8726
8727         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8728         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8729                      > PAGE_SIZE);
8730
8731         err = -ENOMEM;
8732         if (!vmx->guest_msrs) {
8733                 goto uninit_vcpu;
8734         }
8735
8736         vmx->loaded_vmcs = &vmx->vmcs01;
8737         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8738         if (!vmx->loaded_vmcs->vmcs)
8739                 goto free_msrs;
8740         if (!vmm_exclusive)
8741                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8742         loaded_vmcs_init(vmx->loaded_vmcs);
8743         if (!vmm_exclusive)
8744                 kvm_cpu_vmxoff();
8745
8746         cpu = get_cpu();
8747         vmx_vcpu_load(&vmx->vcpu, cpu);
8748         vmx->vcpu.cpu = cpu;
8749         err = vmx_vcpu_setup(vmx);
8750         vmx_vcpu_put(&vmx->vcpu);
8751         put_cpu();
8752         if (err)
8753                 goto free_vmcs;
8754         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8755                 err = alloc_apic_access_page(kvm);
8756                 if (err)
8757                         goto free_vmcs;
8758         }
8759
8760         if (enable_ept) {
8761                 if (!kvm->arch.ept_identity_map_addr)
8762                         kvm->arch.ept_identity_map_addr =
8763                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8764                 err = init_rmode_identity_map(kvm);
8765                 if (err)
8766                         goto free_vmcs;
8767         }
8768
8769         if (nested) {
8770                 nested_vmx_setup_ctls_msrs(vmx);
8771                 vmx->nested.vpid02 = allocate_vpid();
8772         }
8773
8774         vmx->nested.posted_intr_nv = -1;
8775         vmx->nested.current_vmptr = -1ull;
8776         vmx->nested.current_vmcs12 = NULL;
8777
8778         /*
8779          * If PML is turned on, failure on enabling PML just results in failure
8780          * of creating the vcpu, therefore we can simplify PML logic (by
8781          * avoiding dealing with cases, such as enabling PML partially on vcpus
8782          * for the guest, etc.
8783          */
8784         if (enable_pml) {
8785                 err = vmx_create_pml_buffer(vmx);
8786                 if (err)
8787                         goto free_vmcs;
8788         }
8789
8790         return &vmx->vcpu;
8791
8792 free_vmcs:
8793         free_vpid(vmx->nested.vpid02);
8794         free_loaded_vmcs(vmx->loaded_vmcs);
8795 free_msrs:
8796         kfree(vmx->guest_msrs);
8797 uninit_vcpu:
8798         kvm_vcpu_uninit(&vmx->vcpu);
8799 free_vcpu:
8800         free_vpid(vmx->vpid);
8801         kmem_cache_free(kvm_vcpu_cache, vmx);
8802         return ERR_PTR(err);
8803 }
8804
8805 static void __init vmx_check_processor_compat(void *rtn)
8806 {
8807         struct vmcs_config vmcs_conf;
8808
8809         *(int *)rtn = 0;
8810         if (setup_vmcs_config(&vmcs_conf) < 0)
8811                 *(int *)rtn = -EIO;
8812         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8813                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8814                                 smp_processor_id());
8815                 *(int *)rtn = -EIO;
8816         }
8817 }
8818
8819 static int get_ept_level(void)
8820 {
8821         return VMX_EPT_DEFAULT_GAW + 1;
8822 }
8823
8824 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8825 {
8826         u8 cache;
8827         u64 ipat = 0;
8828
8829         /* For VT-d and EPT combination
8830          * 1. MMIO: always map as UC
8831          * 2. EPT with VT-d:
8832          *   a. VT-d without snooping control feature: can't guarantee the
8833          *      result, try to trust guest.
8834          *   b. VT-d with snooping control feature: snooping control feature of
8835          *      VT-d engine can guarantee the cache correctness. Just set it
8836          *      to WB to keep consistent with host. So the same as item 3.
8837          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8838          *    consistent with host MTRR
8839          */
8840         if (is_mmio) {
8841                 cache = MTRR_TYPE_UNCACHABLE;
8842                 goto exit;
8843         }
8844
8845         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8846                 ipat = VMX_EPT_IPAT_BIT;
8847                 cache = MTRR_TYPE_WRBACK;
8848                 goto exit;
8849         }
8850
8851         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8852                 ipat = VMX_EPT_IPAT_BIT;
8853                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8854                         cache = MTRR_TYPE_WRBACK;
8855                 else
8856                         cache = MTRR_TYPE_UNCACHABLE;
8857                 goto exit;
8858         }
8859
8860         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8861
8862 exit:
8863         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8864 }
8865
8866 static int vmx_get_lpage_level(void)
8867 {
8868         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8869                 return PT_DIRECTORY_LEVEL;
8870         else
8871                 /* For shadow and EPT supported 1GB page */
8872                 return PT_PDPE_LEVEL;
8873 }
8874
8875 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8876 {
8877         /*
8878          * These bits in the secondary execution controls field
8879          * are dynamic, the others are mostly based on the hypervisor
8880          * architecture and the guest's CPUID.  Do not touch the
8881          * dynamic bits.
8882          */
8883         u32 mask =
8884                 SECONDARY_EXEC_SHADOW_VMCS |
8885                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8886                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8887
8888         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8889
8890         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8891                      (new_ctl & ~mask) | (cur_ctl & mask));
8892 }
8893
8894 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8895 {
8896         struct kvm_cpuid_entry2 *best;
8897         struct vcpu_vmx *vmx = to_vmx(vcpu);
8898         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8899
8900         if (vmx_rdtscp_supported()) {
8901                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8902                 if (!rdtscp_enabled)
8903                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8904
8905                 if (nested) {
8906                         if (rdtscp_enabled)
8907                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8908                                         SECONDARY_EXEC_RDTSCP;
8909                         else
8910                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8911                                         ~SECONDARY_EXEC_RDTSCP;
8912                 }
8913         }
8914
8915         /* Exposing INVPCID only when PCID is exposed */
8916         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8917         if (vmx_invpcid_supported() &&
8918             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8919             !guest_cpuid_has_pcid(vcpu))) {
8920                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8921
8922                 if (best)
8923                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8924         }
8925
8926         vmcs_set_secondary_exec_control(secondary_exec_ctl);
8927
8928         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8929                 if (guest_cpuid_has_pcommit(vcpu))
8930                         vmx->nested.nested_vmx_secondary_ctls_high |=
8931                                 SECONDARY_EXEC_PCOMMIT;
8932                 else
8933                         vmx->nested.nested_vmx_secondary_ctls_high &=
8934                                 ~SECONDARY_EXEC_PCOMMIT;
8935         }
8936 }
8937
8938 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8939 {
8940         if (func == 1 && nested)
8941                 entry->ecx |= bit(X86_FEATURE_VMX);
8942 }
8943
8944 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8945                 struct x86_exception *fault)
8946 {
8947         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8948         u32 exit_reason;
8949
8950         if (fault->error_code & PFERR_RSVD_MASK)
8951                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8952         else
8953                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8954         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8955         vmcs12->guest_physical_address = fault->address;
8956 }
8957
8958 /* Callbacks for nested_ept_init_mmu_context: */
8959
8960 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8961 {
8962         /* return the page table to be shadowed - in our case, EPT12 */
8963         return get_vmcs12(vcpu)->ept_pointer;
8964 }
8965
8966 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8967 {
8968         WARN_ON(mmu_is_nested(vcpu));
8969         kvm_init_shadow_ept_mmu(vcpu,
8970                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8971                         VMX_EPT_EXECUTE_ONLY_BIT);
8972         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8973         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8974         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8975
8976         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8977 }
8978
8979 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8980 {
8981         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8982 }
8983
8984 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8985                                             u16 error_code)
8986 {
8987         bool inequality, bit;
8988
8989         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8990         inequality =
8991                 (error_code & vmcs12->page_fault_error_code_mask) !=
8992                  vmcs12->page_fault_error_code_match;
8993         return inequality ^ bit;
8994 }
8995
8996 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8997                 struct x86_exception *fault)
8998 {
8999         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9000
9001         WARN_ON(!is_guest_mode(vcpu));
9002
9003         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9004                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9005                                   vmcs_read32(VM_EXIT_INTR_INFO),
9006                                   vmcs_readl(EXIT_QUALIFICATION));
9007         else
9008                 kvm_inject_page_fault(vcpu, fault);
9009 }
9010
9011 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9012                                         struct vmcs12 *vmcs12)
9013 {
9014         struct vcpu_vmx *vmx = to_vmx(vcpu);
9015         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9016
9017         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9018                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9019                     vmcs12->apic_access_addr >> maxphyaddr)
9020                         return false;
9021
9022                 /*
9023                  * Translate L1 physical address to host physical
9024                  * address for vmcs02. Keep the page pinned, so this
9025                  * physical address remains valid. We keep a reference
9026                  * to it so we can release it later.
9027                  */
9028                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9029                         nested_release_page(vmx->nested.apic_access_page);
9030                 vmx->nested.apic_access_page =
9031                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9032         }
9033
9034         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9035                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9036                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9037                         return false;
9038
9039                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9040                         nested_release_page(vmx->nested.virtual_apic_page);
9041                 vmx->nested.virtual_apic_page =
9042                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9043
9044                 /*
9045                  * Failing the vm entry is _not_ what the processor does
9046                  * but it's basically the only possibility we have.
9047                  * We could still enter the guest if CR8 load exits are
9048                  * enabled, CR8 store exits are enabled, and virtualize APIC
9049                  * access is disabled; in this case the processor would never
9050                  * use the TPR shadow and we could simply clear the bit from
9051                  * the execution control.  But such a configuration is useless,
9052                  * so let's keep the code simple.
9053                  */
9054                 if (!vmx->nested.virtual_apic_page)
9055                         return false;
9056         }
9057
9058         if (nested_cpu_has_posted_intr(vmcs12)) {
9059                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9060                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9061                         return false;
9062
9063                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9064                         kunmap(vmx->nested.pi_desc_page);
9065                         nested_release_page(vmx->nested.pi_desc_page);
9066                 }
9067                 vmx->nested.pi_desc_page =
9068                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9069                 if (!vmx->nested.pi_desc_page)
9070                         return false;
9071
9072                 vmx->nested.pi_desc =
9073                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9074                 if (!vmx->nested.pi_desc) {
9075                         nested_release_page_clean(vmx->nested.pi_desc_page);
9076                         return false;
9077                 }
9078                 vmx->nested.pi_desc =
9079                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9080                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9081                         (PAGE_SIZE - 1)));
9082         }
9083
9084         return true;
9085 }
9086
9087 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9088 {
9089         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9090         struct vcpu_vmx *vmx = to_vmx(vcpu);
9091
9092         if (vcpu->arch.virtual_tsc_khz == 0)
9093                 return;
9094
9095         /* Make sure short timeouts reliably trigger an immediate vmexit.
9096          * hrtimer_start does not guarantee this. */
9097         if (preemption_timeout <= 1) {
9098                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9099                 return;
9100         }
9101
9102         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9103         preemption_timeout *= 1000000;
9104         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9105         hrtimer_start(&vmx->nested.preemption_timer,
9106                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9107 }
9108
9109 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9110                                                 struct vmcs12 *vmcs12)
9111 {
9112         int maxphyaddr;
9113         u64 addr;
9114
9115         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9116                 return 0;
9117
9118         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9119                 WARN_ON(1);
9120                 return -EINVAL;
9121         }
9122         maxphyaddr = cpuid_maxphyaddr(vcpu);
9123
9124         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9125            ((addr + PAGE_SIZE) >> maxphyaddr))
9126                 return -EINVAL;
9127
9128         return 0;
9129 }
9130
9131 /*
9132  * Merge L0's and L1's MSR bitmap, return false to indicate that
9133  * we do not use the hardware.
9134  */
9135 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9136                                                struct vmcs12 *vmcs12)
9137 {
9138         int msr;
9139         struct page *page;
9140         unsigned long *msr_bitmap;
9141
9142         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9143                 return false;
9144
9145         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9146         if (!page) {
9147                 WARN_ON(1);
9148                 return false;
9149         }
9150         msr_bitmap = (unsigned long *)kmap(page);
9151         if (!msr_bitmap) {
9152                 nested_release_page_clean(page);
9153                 WARN_ON(1);
9154                 return false;
9155         }
9156
9157         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9158                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9159                         for (msr = 0x800; msr <= 0x8ff; msr++)
9160                                 nested_vmx_disable_intercept_for_msr(
9161                                         msr_bitmap,
9162                                         vmx_msr_bitmap_nested,
9163                                         msr, MSR_TYPE_R);
9164                 /* TPR is allowed */
9165                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9166                                 vmx_msr_bitmap_nested,
9167                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9168                                 MSR_TYPE_R | MSR_TYPE_W);
9169                 if (nested_cpu_has_vid(vmcs12)) {
9170                         /* EOI and self-IPI are allowed */
9171                         nested_vmx_disable_intercept_for_msr(
9172                                 msr_bitmap,
9173                                 vmx_msr_bitmap_nested,
9174                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9175                                 MSR_TYPE_W);
9176                         nested_vmx_disable_intercept_for_msr(
9177                                 msr_bitmap,
9178                                 vmx_msr_bitmap_nested,
9179                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9180                                 MSR_TYPE_W);
9181                 }
9182         } else {
9183                 /*
9184                  * Enable reading intercept of all the x2apic
9185                  * MSRs. We should not rely on vmcs12 to do any
9186                  * optimizations here, it may have been modified
9187                  * by L1.
9188                  */
9189                 for (msr = 0x800; msr <= 0x8ff; msr++)
9190                         __vmx_enable_intercept_for_msr(
9191                                 vmx_msr_bitmap_nested,
9192                                 msr,
9193                                 MSR_TYPE_R);
9194
9195                 __vmx_enable_intercept_for_msr(
9196                                 vmx_msr_bitmap_nested,
9197                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9198                                 MSR_TYPE_W);
9199                 __vmx_enable_intercept_for_msr(
9200                                 vmx_msr_bitmap_nested,
9201                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9202                                 MSR_TYPE_W);
9203                 __vmx_enable_intercept_for_msr(
9204                                 vmx_msr_bitmap_nested,
9205                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9206                                 MSR_TYPE_W);
9207         }
9208         kunmap(page);
9209         nested_release_page_clean(page);
9210
9211         return true;
9212 }
9213
9214 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9215                                            struct vmcs12 *vmcs12)
9216 {
9217         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9218             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9219             !nested_cpu_has_vid(vmcs12) &&
9220             !nested_cpu_has_posted_intr(vmcs12))
9221                 return 0;
9222
9223         /*
9224          * If virtualize x2apic mode is enabled,
9225          * virtualize apic access must be disabled.
9226          */
9227         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9228             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9229                 return -EINVAL;
9230
9231         /*
9232          * If virtual interrupt delivery is enabled,
9233          * we must exit on external interrupts.
9234          */
9235         if (nested_cpu_has_vid(vmcs12) &&
9236            !nested_exit_on_intr(vcpu))
9237                 return -EINVAL;
9238
9239         /*
9240          * bits 15:8 should be zero in posted_intr_nv,
9241          * the descriptor address has been already checked
9242          * in nested_get_vmcs12_pages.
9243          */
9244         if (nested_cpu_has_posted_intr(vmcs12) &&
9245            (!nested_cpu_has_vid(vmcs12) ||
9246             !nested_exit_intr_ack_set(vcpu) ||
9247             vmcs12->posted_intr_nv & 0xff00))
9248                 return -EINVAL;
9249
9250         /* tpr shadow is needed by all apicv features. */
9251         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9252                 return -EINVAL;
9253
9254         return 0;
9255 }
9256
9257 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9258                                        unsigned long count_field,
9259                                        unsigned long addr_field)
9260 {
9261         int maxphyaddr;
9262         u64 count, addr;
9263
9264         if (vmcs12_read_any(vcpu, count_field, &count) ||
9265             vmcs12_read_any(vcpu, addr_field, &addr)) {
9266                 WARN_ON(1);
9267                 return -EINVAL;
9268         }
9269         if (count == 0)
9270                 return 0;
9271         maxphyaddr = cpuid_maxphyaddr(vcpu);
9272         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9273             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9274                 pr_warn_ratelimited(
9275                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9276                         addr_field, maxphyaddr, count, addr);
9277                 return -EINVAL;
9278         }
9279         return 0;
9280 }
9281
9282 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9283                                                 struct vmcs12 *vmcs12)
9284 {
9285         if (vmcs12->vm_exit_msr_load_count == 0 &&
9286             vmcs12->vm_exit_msr_store_count == 0 &&
9287             vmcs12->vm_entry_msr_load_count == 0)
9288                 return 0; /* Fast path */
9289         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9290                                         VM_EXIT_MSR_LOAD_ADDR) ||
9291             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9292                                         VM_EXIT_MSR_STORE_ADDR) ||
9293             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9294                                         VM_ENTRY_MSR_LOAD_ADDR))
9295                 return -EINVAL;
9296         return 0;
9297 }
9298
9299 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9300                                        struct vmx_msr_entry *e)
9301 {
9302         /* x2APIC MSR accesses are not allowed */
9303         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9304                 return -EINVAL;
9305         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9306             e->index == MSR_IA32_UCODE_REV)
9307                 return -EINVAL;
9308         if (e->reserved != 0)
9309                 return -EINVAL;
9310         return 0;
9311 }
9312
9313 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9314                                      struct vmx_msr_entry *e)
9315 {
9316         if (e->index == MSR_FS_BASE ||
9317             e->index == MSR_GS_BASE ||
9318             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9319             nested_vmx_msr_check_common(vcpu, e))
9320                 return -EINVAL;
9321         return 0;
9322 }
9323
9324 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9325                                       struct vmx_msr_entry *e)
9326 {
9327         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9328             nested_vmx_msr_check_common(vcpu, e))
9329                 return -EINVAL;
9330         return 0;
9331 }
9332
9333 /*
9334  * Load guest's/host's msr at nested entry/exit.
9335  * return 0 for success, entry index for failure.
9336  */
9337 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9338 {
9339         u32 i;
9340         struct vmx_msr_entry e;
9341         struct msr_data msr;
9342
9343         msr.host_initiated = false;
9344         for (i = 0; i < count; i++) {
9345                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9346                                         &e, sizeof(e))) {
9347                         pr_warn_ratelimited(
9348                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9349                                 __func__, i, gpa + i * sizeof(e));
9350                         goto fail;
9351                 }
9352                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9353                         pr_warn_ratelimited(
9354                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9355                                 __func__, i, e.index, e.reserved);
9356                         goto fail;
9357                 }
9358                 msr.index = e.index;
9359                 msr.data = e.value;
9360                 if (kvm_set_msr(vcpu, &msr)) {
9361                         pr_warn_ratelimited(
9362                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9363                                 __func__, i, e.index, e.value);
9364                         goto fail;
9365                 }
9366         }
9367         return 0;
9368 fail:
9369         return i + 1;
9370 }
9371
9372 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9373 {
9374         u32 i;
9375         struct vmx_msr_entry e;
9376
9377         for (i = 0; i < count; i++) {
9378                 struct msr_data msr_info;
9379                 if (kvm_vcpu_read_guest(vcpu,
9380                                         gpa + i * sizeof(e),
9381                                         &e, 2 * sizeof(u32))) {
9382                         pr_warn_ratelimited(
9383                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9384                                 __func__, i, gpa + i * sizeof(e));
9385                         return -EINVAL;
9386                 }
9387                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9388                         pr_warn_ratelimited(
9389                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9390                                 __func__, i, e.index, e.reserved);
9391                         return -EINVAL;
9392                 }
9393                 msr_info.host_initiated = false;
9394                 msr_info.index = e.index;
9395                 if (kvm_get_msr(vcpu, &msr_info)) {
9396                         pr_warn_ratelimited(
9397                                 "%s cannot read MSR (%u, 0x%x)\n",
9398                                 __func__, i, e.index);
9399                         return -EINVAL;
9400                 }
9401                 if (kvm_vcpu_write_guest(vcpu,
9402                                          gpa + i * sizeof(e) +
9403                                              offsetof(struct vmx_msr_entry, value),
9404                                          &msr_info.data, sizeof(msr_info.data))) {
9405                         pr_warn_ratelimited(
9406                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9407                                 __func__, i, e.index, msr_info.data);
9408                         return -EINVAL;
9409                 }
9410         }
9411         return 0;
9412 }
9413
9414 /*
9415  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9416  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9417  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9418  * guest in a way that will both be appropriate to L1's requests, and our
9419  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9420  * function also has additional necessary side-effects, like setting various
9421  * vcpu->arch fields.
9422  */
9423 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9424 {
9425         struct vcpu_vmx *vmx = to_vmx(vcpu);
9426         u32 exec_control;
9427
9428         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9429         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9430         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9431         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9432         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9433         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9434         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9435         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9436         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9437         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9438         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9439         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9440         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9441         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9442         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9443         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9444         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9445         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9446         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9447         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9448         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9449         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9450         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9451         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9452         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9453         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9454         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9455         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9456         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9457         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9458         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9459         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9460         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9461         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9462         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9463         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9464
9465         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9466                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9467                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9468         } else {
9469                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9470                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9471         }
9472         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9473                 vmcs12->vm_entry_intr_info_field);
9474         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9475                 vmcs12->vm_entry_exception_error_code);
9476         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9477                 vmcs12->vm_entry_instruction_len);
9478         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9479                 vmcs12->guest_interruptibility_info);
9480         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9481         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9482         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9483                 vmcs12->guest_pending_dbg_exceptions);
9484         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9485         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9486
9487         if (nested_cpu_has_xsaves(vmcs12))
9488                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9489         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9490
9491         exec_control = vmcs12->pin_based_vm_exec_control;
9492         exec_control |= vmcs_config.pin_based_exec_ctrl;
9493         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9494
9495         if (nested_cpu_has_posted_intr(vmcs12)) {
9496                 /*
9497                  * Note that we use L0's vector here and in
9498                  * vmx_deliver_nested_posted_interrupt.
9499                  */
9500                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9501                 vmx->nested.pi_pending = false;
9502                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9503                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9504                         page_to_phys(vmx->nested.pi_desc_page) +
9505                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9506                         (PAGE_SIZE - 1)));
9507         } else
9508                 exec_control &= ~PIN_BASED_POSTED_INTR;
9509
9510         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9511
9512         vmx->nested.preemption_timer_expired = false;
9513         if (nested_cpu_has_preemption_timer(vmcs12))
9514                 vmx_start_preemption_timer(vcpu);
9515
9516         /*
9517          * Whether page-faults are trapped is determined by a combination of
9518          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9519          * If enable_ept, L0 doesn't care about page faults and we should
9520          * set all of these to L1's desires. However, if !enable_ept, L0 does
9521          * care about (at least some) page faults, and because it is not easy
9522          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9523          * to exit on each and every L2 page fault. This is done by setting
9524          * MASK=MATCH=0 and (see below) EB.PF=1.
9525          * Note that below we don't need special code to set EB.PF beyond the
9526          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9527          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9528          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9529          *
9530          * A problem with this approach (when !enable_ept) is that L1 may be
9531          * injected with more page faults than it asked for. This could have
9532          * caused problems, but in practice existing hypervisors don't care.
9533          * To fix this, we will need to emulate the PFEC checking (on the L1
9534          * page tables), using walk_addr(), when injecting PFs to L1.
9535          */
9536         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9537                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9538         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9539                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9540
9541         if (cpu_has_secondary_exec_ctrls()) {
9542                 exec_control = vmx_secondary_exec_control(vmx);
9543
9544                 /* Take the following fields only from vmcs12 */
9545                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9546                                   SECONDARY_EXEC_RDTSCP |
9547                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9548                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9549                                   SECONDARY_EXEC_PCOMMIT);
9550                 if (nested_cpu_has(vmcs12,
9551                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9552                         exec_control |= vmcs12->secondary_vm_exec_control;
9553
9554                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9555                         /*
9556                          * If translation failed, no matter: This feature asks
9557                          * to exit when accessing the given address, and if it
9558                          * can never be accessed, this feature won't do
9559                          * anything anyway.
9560                          */
9561                         if (!vmx->nested.apic_access_page)
9562                                 exec_control &=
9563                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9564                         else
9565                                 vmcs_write64(APIC_ACCESS_ADDR,
9566                                   page_to_phys(vmx->nested.apic_access_page));
9567                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9568                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9569                         exec_control |=
9570                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9571                         kvm_vcpu_reload_apic_access_page(vcpu);
9572                 }
9573
9574                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9575                         vmcs_write64(EOI_EXIT_BITMAP0,
9576                                 vmcs12->eoi_exit_bitmap0);
9577                         vmcs_write64(EOI_EXIT_BITMAP1,
9578                                 vmcs12->eoi_exit_bitmap1);
9579                         vmcs_write64(EOI_EXIT_BITMAP2,
9580                                 vmcs12->eoi_exit_bitmap2);
9581                         vmcs_write64(EOI_EXIT_BITMAP3,
9582                                 vmcs12->eoi_exit_bitmap3);
9583                         vmcs_write16(GUEST_INTR_STATUS,
9584                                 vmcs12->guest_intr_status);
9585                 }
9586
9587                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9588         }
9589
9590
9591         /*
9592          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9593          * Some constant fields are set here by vmx_set_constant_host_state().
9594          * Other fields are different per CPU, and will be set later when
9595          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9596          */
9597         vmx_set_constant_host_state(vmx);
9598
9599         /*
9600          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9601          * entry, but only if the current (host) sp changed from the value
9602          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9603          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9604          * here we just force the write to happen on entry.
9605          */
9606         vmx->host_rsp = 0;
9607
9608         exec_control = vmx_exec_control(vmx); /* L0's desires */
9609         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9610         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9611         exec_control &= ~CPU_BASED_TPR_SHADOW;
9612         exec_control |= vmcs12->cpu_based_vm_exec_control;
9613
9614         if (exec_control & CPU_BASED_TPR_SHADOW) {
9615                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9616                                 page_to_phys(vmx->nested.virtual_apic_page));
9617                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9618         }
9619
9620         if (cpu_has_vmx_msr_bitmap() &&
9621             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9622                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9623                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9624         } else
9625                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9626
9627         /*
9628          * Merging of IO bitmap not currently supported.
9629          * Rather, exit every time.
9630          */
9631         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9632         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9633
9634         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9635
9636         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9637          * bitwise-or of what L1 wants to trap for L2, and what we want to
9638          * trap. Note that CR0.TS also needs updating - we do this later.
9639          */
9640         update_exception_bitmap(vcpu);
9641         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9642         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9643
9644         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9645          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9646          * bits are further modified by vmx_set_efer() below.
9647          */
9648         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9649
9650         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9651          * emulated by vmx_set_efer(), below.
9652          */
9653         vm_entry_controls_init(vmx,
9654                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9655                         ~VM_ENTRY_IA32E_MODE) |
9656                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9657
9658         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9659                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9660                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9661         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9662                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9663
9664
9665         set_cr4_guest_host_mask(vmx);
9666
9667         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9668                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9669
9670         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9671                 vmcs_write64(TSC_OFFSET,
9672                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9673         else
9674                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9675
9676         if (enable_vpid) {
9677                 /*
9678                  * There is no direct mapping between vpid02 and vpid12, the
9679                  * vpid02 is per-vCPU for L0 and reused while the value of
9680                  * vpid12 is changed w/ one invvpid during nested vmentry.
9681                  * The vpid12 is allocated by L1 for L2, so it will not
9682                  * influence global bitmap(for vpid01 and vpid02 allocation)
9683                  * even if spawn a lot of nested vCPUs.
9684                  */
9685                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9686                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9687                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9688                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9689                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9690                         }
9691                 } else {
9692                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9693                         vmx_flush_tlb(vcpu);
9694                 }
9695
9696         }
9697
9698         if (nested_cpu_has_ept(vmcs12)) {
9699                 kvm_mmu_unload(vcpu);
9700                 nested_ept_init_mmu_context(vcpu);
9701         }
9702
9703         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9704                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9705         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9706                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9707         else
9708                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9709         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9710         vmx_set_efer(vcpu, vcpu->arch.efer);
9711
9712         /*
9713          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9714          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9715          * The CR0_READ_SHADOW is what L2 should have expected to read given
9716          * the specifications by L1; It's not enough to take
9717          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9718          * have more bits than L1 expected.
9719          */
9720         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9721         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9722
9723         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9724         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9725
9726         /* shadow page tables on either EPT or shadow page tables */
9727         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9728         kvm_mmu_reset_context(vcpu);
9729
9730         if (!enable_ept)
9731                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9732
9733         /*
9734          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9735          */
9736         if (enable_ept) {
9737                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9738                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9739                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9740                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9741         }
9742
9743         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9744         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9745 }
9746
9747 /*
9748  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9749  * for running an L2 nested guest.
9750  */
9751 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9752 {
9753         struct vmcs12 *vmcs12;
9754         struct vcpu_vmx *vmx = to_vmx(vcpu);
9755         int cpu;
9756         struct loaded_vmcs *vmcs02;
9757         bool ia32e;
9758         u32 msr_entry_idx;
9759
9760         if (!nested_vmx_check_permission(vcpu) ||
9761             !nested_vmx_check_vmcs12(vcpu))
9762                 return 1;
9763
9764         skip_emulated_instruction(vcpu);
9765         vmcs12 = get_vmcs12(vcpu);
9766
9767         if (enable_shadow_vmcs)
9768                 copy_shadow_to_vmcs12(vmx);
9769
9770         /*
9771          * The nested entry process starts with enforcing various prerequisites
9772          * on vmcs12 as required by the Intel SDM, and act appropriately when
9773          * they fail: As the SDM explains, some conditions should cause the
9774          * instruction to fail, while others will cause the instruction to seem
9775          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9776          * To speed up the normal (success) code path, we should avoid checking
9777          * for misconfigurations which will anyway be caught by the processor
9778          * when using the merged vmcs02.
9779          */
9780         if (vmcs12->launch_state == launch) {
9781                 nested_vmx_failValid(vcpu,
9782                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9783                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9784                 return 1;
9785         }
9786
9787         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9788             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9789                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9790                 return 1;
9791         }
9792
9793         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9794                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9795                 return 1;
9796         }
9797
9798         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9799                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9800                 return 1;
9801         }
9802
9803         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9804                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9805                 return 1;
9806         }
9807
9808         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9809                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9810                 return 1;
9811         }
9812
9813         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9814                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9815                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9816             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9817                                 vmx->nested.nested_vmx_secondary_ctls_low,
9818                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9819             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9820                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9821                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9822             !vmx_control_verify(vmcs12->vm_exit_controls,
9823                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9824                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9825             !vmx_control_verify(vmcs12->vm_entry_controls,
9826                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9827                                 vmx->nested.nested_vmx_entry_ctls_high))
9828         {
9829                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9830                 return 1;
9831         }
9832
9833         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9834             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9835                 nested_vmx_failValid(vcpu,
9836                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9837                 return 1;
9838         }
9839
9840         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9841             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9842                 nested_vmx_entry_failure(vcpu, vmcs12,
9843                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9844                 return 1;
9845         }
9846         if (vmcs12->vmcs_link_pointer != -1ull) {
9847                 nested_vmx_entry_failure(vcpu, vmcs12,
9848                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9849                 return 1;
9850         }
9851
9852         /*
9853          * If the load IA32_EFER VM-entry control is 1, the following checks
9854          * are performed on the field for the IA32_EFER MSR:
9855          * - Bits reserved in the IA32_EFER MSR must be 0.
9856          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9857          *   the IA-32e mode guest VM-exit control. It must also be identical
9858          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9859          *   CR0.PG) is 1.
9860          */
9861         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9862                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9863                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9864                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9865                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9866                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9867                         nested_vmx_entry_failure(vcpu, vmcs12,
9868                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9869                         return 1;
9870                 }
9871         }
9872
9873         /*
9874          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9875          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9876          * the values of the LMA and LME bits in the field must each be that of
9877          * the host address-space size VM-exit control.
9878          */
9879         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9880                 ia32e = (vmcs12->vm_exit_controls &
9881                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9882                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9883                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9884                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9885                         nested_vmx_entry_failure(vcpu, vmcs12,
9886                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9887                         return 1;
9888                 }
9889         }
9890
9891         /*
9892          * We're finally done with prerequisite checking, and can start with
9893          * the nested entry.
9894          */
9895
9896         vmcs02 = nested_get_current_vmcs02(vmx);
9897         if (!vmcs02)
9898                 return -ENOMEM;
9899
9900         enter_guest_mode(vcpu);
9901
9902         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9903
9904         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9905                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9906
9907         cpu = get_cpu();
9908         vmx->loaded_vmcs = vmcs02;
9909         vmx_vcpu_put(vcpu);
9910         vmx_vcpu_load(vcpu, cpu);
9911         vcpu->cpu = cpu;
9912         put_cpu();
9913
9914         vmx_segment_cache_clear(vmx);
9915
9916         prepare_vmcs02(vcpu, vmcs12);
9917
9918         msr_entry_idx = nested_vmx_load_msr(vcpu,
9919                                             vmcs12->vm_entry_msr_load_addr,
9920                                             vmcs12->vm_entry_msr_load_count);
9921         if (msr_entry_idx) {
9922                 leave_guest_mode(vcpu);
9923                 vmx_load_vmcs01(vcpu);
9924                 nested_vmx_entry_failure(vcpu, vmcs12,
9925                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9926                 return 1;
9927         }
9928
9929         vmcs12->launch_state = 1;
9930
9931         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9932                 return kvm_vcpu_halt(vcpu);
9933
9934         vmx->nested.nested_run_pending = 1;
9935
9936         /*
9937          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9938          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9939          * returned as far as L1 is concerned. It will only return (and set
9940          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9941          */
9942         return 1;
9943 }
9944
9945 /*
9946  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9947  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9948  * This function returns the new value we should put in vmcs12.guest_cr0.
9949  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9950  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9951  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9952  *     didn't trap the bit, because if L1 did, so would L0).
9953  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9954  *     been modified by L2, and L1 knows it. So just leave the old value of
9955  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9956  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9957  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9958  *     changed these bits, and therefore they need to be updated, but L0
9959  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9960  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9961  */
9962 static inline unsigned long
9963 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9964 {
9965         return
9966         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9967         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9968         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9969                         vcpu->arch.cr0_guest_owned_bits));
9970 }
9971
9972 static inline unsigned long
9973 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9974 {
9975         return
9976         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9977         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9978         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9979                         vcpu->arch.cr4_guest_owned_bits));
9980 }
9981
9982 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9983                                        struct vmcs12 *vmcs12)
9984 {
9985         u32 idt_vectoring;
9986         unsigned int nr;
9987
9988         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9989                 nr = vcpu->arch.exception.nr;
9990                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9991
9992                 if (kvm_exception_is_soft(nr)) {
9993                         vmcs12->vm_exit_instruction_len =
9994                                 vcpu->arch.event_exit_inst_len;
9995                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9996                 } else
9997                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9998
9999                 if (vcpu->arch.exception.has_error_code) {
10000                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10001                         vmcs12->idt_vectoring_error_code =
10002                                 vcpu->arch.exception.error_code;
10003                 }
10004
10005                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10006         } else if (vcpu->arch.nmi_injected) {
10007                 vmcs12->idt_vectoring_info_field =
10008                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10009         } else if (vcpu->arch.interrupt.pending) {
10010                 nr = vcpu->arch.interrupt.nr;
10011                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10012
10013                 if (vcpu->arch.interrupt.soft) {
10014                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10015                         vmcs12->vm_entry_instruction_len =
10016                                 vcpu->arch.event_exit_inst_len;
10017                 } else
10018                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10019
10020                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10021         }
10022 }
10023
10024 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10025 {
10026         struct vcpu_vmx *vmx = to_vmx(vcpu);
10027
10028         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10029             vmx->nested.preemption_timer_expired) {
10030                 if (vmx->nested.nested_run_pending)
10031                         return -EBUSY;
10032                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10033                 return 0;
10034         }
10035
10036         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10037                 if (vmx->nested.nested_run_pending ||
10038                     vcpu->arch.interrupt.pending)
10039                         return -EBUSY;
10040                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10041                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10042                                   INTR_INFO_VALID_MASK, 0);
10043                 /*
10044                  * The NMI-triggered VM exit counts as injection:
10045                  * clear this one and block further NMIs.
10046                  */
10047                 vcpu->arch.nmi_pending = 0;
10048                 vmx_set_nmi_mask(vcpu, true);
10049                 return 0;
10050         }
10051
10052         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10053             nested_exit_on_intr(vcpu)) {
10054                 if (vmx->nested.nested_run_pending)
10055                         return -EBUSY;
10056                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10057                 return 0;
10058         }
10059
10060         return vmx_complete_nested_posted_interrupt(vcpu);
10061 }
10062
10063 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10064 {
10065         ktime_t remaining =
10066                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10067         u64 value;
10068
10069         if (ktime_to_ns(remaining) <= 0)
10070                 return 0;
10071
10072         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10073         do_div(value, 1000000);
10074         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10075 }
10076
10077 /*
10078  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10079  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10080  * and this function updates it to reflect the changes to the guest state while
10081  * L2 was running (and perhaps made some exits which were handled directly by L0
10082  * without going back to L1), and to reflect the exit reason.
10083  * Note that we do not have to copy here all VMCS fields, just those that
10084  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10085  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10086  * which already writes to vmcs12 directly.
10087  */
10088 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10089                            u32 exit_reason, u32 exit_intr_info,
10090                            unsigned long exit_qualification)
10091 {
10092         /* update guest state fields: */
10093         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10094         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10095
10096         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10097         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10098         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10099
10100         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10101         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10102         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10103         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10104         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10105         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10106         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10107         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10108         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10109         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10110         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10111         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10112         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10113         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10114         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10115         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10116         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10117         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10118         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10119         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10120         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10121         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10122         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10123         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10124         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10125         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10126         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10127         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10128         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10129         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10130         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10131         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10132         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10133         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10134         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10135         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10136
10137         vmcs12->guest_interruptibility_info =
10138                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10139         vmcs12->guest_pending_dbg_exceptions =
10140                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10141         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10142                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10143         else
10144                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10145
10146         if (nested_cpu_has_preemption_timer(vmcs12)) {
10147                 if (vmcs12->vm_exit_controls &
10148                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10149                         vmcs12->vmx_preemption_timer_value =
10150                                 vmx_get_preemption_timer_value(vcpu);
10151                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10152         }
10153
10154         /*
10155          * In some cases (usually, nested EPT), L2 is allowed to change its
10156          * own CR3 without exiting. If it has changed it, we must keep it.
10157          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10158          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10159          *
10160          * Additionally, restore L2's PDPTR to vmcs12.
10161          */
10162         if (enable_ept) {
10163                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10164                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10165                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10166                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10167                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10168         }
10169
10170         if (nested_cpu_has_vid(vmcs12))
10171                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10172
10173         vmcs12->vm_entry_controls =
10174                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10175                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10176
10177         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10178                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10179                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10180         }
10181
10182         /* TODO: These cannot have changed unless we have MSR bitmaps and
10183          * the relevant bit asks not to trap the change */
10184         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10185                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10186         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10187                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10188         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10189         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10190         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10191         if (vmx_mpx_supported())
10192                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10193         if (nested_cpu_has_xsaves(vmcs12))
10194                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10195
10196         /* update exit information fields: */
10197
10198         vmcs12->vm_exit_reason = exit_reason;
10199         vmcs12->exit_qualification = exit_qualification;
10200
10201         vmcs12->vm_exit_intr_info = exit_intr_info;
10202         if ((vmcs12->vm_exit_intr_info &
10203              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10204             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10205                 vmcs12->vm_exit_intr_error_code =
10206                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10207         vmcs12->idt_vectoring_info_field = 0;
10208         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10209         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10210
10211         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10212                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10213                  * instead of reading the real value. */
10214                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10215
10216                 /*
10217                  * Transfer the event that L0 or L1 may wanted to inject into
10218                  * L2 to IDT_VECTORING_INFO_FIELD.
10219                  */
10220                 vmcs12_save_pending_event(vcpu, vmcs12);
10221         }
10222
10223         /*
10224          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10225          * preserved above and would only end up incorrectly in L1.
10226          */
10227         vcpu->arch.nmi_injected = false;
10228         kvm_clear_exception_queue(vcpu);
10229         kvm_clear_interrupt_queue(vcpu);
10230 }
10231
10232 /*
10233  * A part of what we need to when the nested L2 guest exits and we want to
10234  * run its L1 parent, is to reset L1's guest state to the host state specified
10235  * in vmcs12.
10236  * This function is to be called not only on normal nested exit, but also on
10237  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10238  * Failures During or After Loading Guest State").
10239  * This function should be called when the active VMCS is L1's (vmcs01).
10240  */
10241 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10242                                    struct vmcs12 *vmcs12)
10243 {
10244         struct kvm_segment seg;
10245
10246         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10247                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10248         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10249                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10250         else
10251                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10252         vmx_set_efer(vcpu, vcpu->arch.efer);
10253
10254         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10255         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10256         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10257         /*
10258          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10259          * actually changed, because it depends on the current state of
10260          * fpu_active (which may have changed).
10261          * Note that vmx_set_cr0 refers to efer set above.
10262          */
10263         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10264         /*
10265          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10266          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10267          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10268          */
10269         update_exception_bitmap(vcpu);
10270         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10271         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10272
10273         /*
10274          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10275          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10276          */
10277         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10278         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10279
10280         nested_ept_uninit_mmu_context(vcpu);
10281
10282         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10283         kvm_mmu_reset_context(vcpu);
10284
10285         if (!enable_ept)
10286                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10287
10288         if (enable_vpid) {
10289                 /*
10290                  * Trivially support vpid by letting L2s share their parent
10291                  * L1's vpid. TODO: move to a more elaborate solution, giving
10292                  * each L2 its own vpid and exposing the vpid feature to L1.
10293                  */
10294                 vmx_flush_tlb(vcpu);
10295         }
10296
10297
10298         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10299         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10300         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10301         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10302         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10303
10304         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10305         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10306                 vmcs_write64(GUEST_BNDCFGS, 0);
10307
10308         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10309                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10310                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10311         }
10312         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10313                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10314                         vmcs12->host_ia32_perf_global_ctrl);
10315
10316         /* Set L1 segment info according to Intel SDM
10317             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10318         seg = (struct kvm_segment) {
10319                 .base = 0,
10320                 .limit = 0xFFFFFFFF,
10321                 .selector = vmcs12->host_cs_selector,
10322                 .type = 11,
10323                 .present = 1,
10324                 .s = 1,
10325                 .g = 1
10326         };
10327         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10328                 seg.l = 1;
10329         else
10330                 seg.db = 1;
10331         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10332         seg = (struct kvm_segment) {
10333                 .base = 0,
10334                 .limit = 0xFFFFFFFF,
10335                 .type = 3,
10336                 .present = 1,
10337                 .s = 1,
10338                 .db = 1,
10339                 .g = 1
10340         };
10341         seg.selector = vmcs12->host_ds_selector;
10342         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10343         seg.selector = vmcs12->host_es_selector;
10344         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10345         seg.selector = vmcs12->host_ss_selector;
10346         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10347         seg.selector = vmcs12->host_fs_selector;
10348         seg.base = vmcs12->host_fs_base;
10349         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10350         seg.selector = vmcs12->host_gs_selector;
10351         seg.base = vmcs12->host_gs_base;
10352         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10353         seg = (struct kvm_segment) {
10354                 .base = vmcs12->host_tr_base,
10355                 .limit = 0x67,
10356                 .selector = vmcs12->host_tr_selector,
10357                 .type = 11,
10358                 .present = 1
10359         };
10360         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10361
10362         kvm_set_dr(vcpu, 7, 0x400);
10363         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10364
10365         if (cpu_has_vmx_msr_bitmap())
10366                 vmx_set_msr_bitmap(vcpu);
10367
10368         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10369                                 vmcs12->vm_exit_msr_load_count))
10370                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10371 }
10372
10373 /*
10374  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10375  * and modify vmcs12 to make it see what it would expect to see there if
10376  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10377  */
10378 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10379                               u32 exit_intr_info,
10380                               unsigned long exit_qualification)
10381 {
10382         struct vcpu_vmx *vmx = to_vmx(vcpu);
10383         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10384
10385         /* trying to cancel vmlaunch/vmresume is a bug */
10386         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10387
10388         leave_guest_mode(vcpu);
10389         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10390                        exit_qualification);
10391
10392         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10393                                  vmcs12->vm_exit_msr_store_count))
10394                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10395
10396         vmx_load_vmcs01(vcpu);
10397
10398         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10399             && nested_exit_intr_ack_set(vcpu)) {
10400                 int irq = kvm_cpu_get_interrupt(vcpu);
10401                 WARN_ON(irq < 0);
10402                 vmcs12->vm_exit_intr_info = irq |
10403                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10404         }
10405
10406         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10407                                        vmcs12->exit_qualification,
10408                                        vmcs12->idt_vectoring_info_field,
10409                                        vmcs12->vm_exit_intr_info,
10410                                        vmcs12->vm_exit_intr_error_code,
10411                                        KVM_ISA_VMX);
10412
10413         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10414         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10415         vmx_segment_cache_clear(vmx);
10416
10417         /* if no vmcs02 cache requested, remove the one we used */
10418         if (VMCS02_POOL_SIZE == 0)
10419                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10420
10421         load_vmcs12_host_state(vcpu, vmcs12);
10422
10423         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10424         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10425
10426         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10427         vmx->host_rsp = 0;
10428
10429         /* Unpin physical memory we referred to in vmcs02 */
10430         if (vmx->nested.apic_access_page) {
10431                 nested_release_page(vmx->nested.apic_access_page);
10432                 vmx->nested.apic_access_page = NULL;
10433         }
10434         if (vmx->nested.virtual_apic_page) {
10435                 nested_release_page(vmx->nested.virtual_apic_page);
10436                 vmx->nested.virtual_apic_page = NULL;
10437         }
10438         if (vmx->nested.pi_desc_page) {
10439                 kunmap(vmx->nested.pi_desc_page);
10440                 nested_release_page(vmx->nested.pi_desc_page);
10441                 vmx->nested.pi_desc_page = NULL;
10442                 vmx->nested.pi_desc = NULL;
10443         }
10444
10445         /*
10446          * We are now running in L2, mmu_notifier will force to reload the
10447          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10448          */
10449         kvm_vcpu_reload_apic_access_page(vcpu);
10450
10451         /*
10452          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10453          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10454          * success or failure flag accordingly.
10455          */
10456         if (unlikely(vmx->fail)) {
10457                 vmx->fail = 0;
10458                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10459         } else
10460                 nested_vmx_succeed(vcpu);
10461         if (enable_shadow_vmcs)
10462                 vmx->nested.sync_shadow_vmcs = true;
10463
10464         /* in case we halted in L2 */
10465         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10466 }
10467
10468 /*
10469  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10470  */
10471 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10472 {
10473         if (is_guest_mode(vcpu))
10474                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10475         free_nested(to_vmx(vcpu));
10476 }
10477
10478 /*
10479  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10480  * 23.7 "VM-entry failures during or after loading guest state" (this also
10481  * lists the acceptable exit-reason and exit-qualification parameters).
10482  * It should only be called before L2 actually succeeded to run, and when
10483  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10484  */
10485 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10486                         struct vmcs12 *vmcs12,
10487                         u32 reason, unsigned long qualification)
10488 {
10489         load_vmcs12_host_state(vcpu, vmcs12);
10490         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10491         vmcs12->exit_qualification = qualification;
10492         nested_vmx_succeed(vcpu);
10493         if (enable_shadow_vmcs)
10494                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10495 }
10496
10497 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10498                                struct x86_instruction_info *info,
10499                                enum x86_intercept_stage stage)
10500 {
10501         return X86EMUL_CONTINUE;
10502 }
10503
10504 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10505 {
10506         if (ple_gap)
10507                 shrink_ple_window(vcpu);
10508 }
10509
10510 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10511                                      struct kvm_memory_slot *slot)
10512 {
10513         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10514         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10515 }
10516
10517 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10518                                        struct kvm_memory_slot *slot)
10519 {
10520         kvm_mmu_slot_set_dirty(kvm, slot);
10521 }
10522
10523 static void vmx_flush_log_dirty(struct kvm *kvm)
10524 {
10525         kvm_flush_pml_buffers(kvm);
10526 }
10527
10528 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10529                                            struct kvm_memory_slot *memslot,
10530                                            gfn_t offset, unsigned long mask)
10531 {
10532         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10533 }
10534
10535 /*
10536  * This routine does the following things for vCPU which is going
10537  * to be blocked if VT-d PI is enabled.
10538  * - Store the vCPU to the wakeup list, so when interrupts happen
10539  *   we can find the right vCPU to wake up.
10540  * - Change the Posted-interrupt descriptor as below:
10541  *      'NDST' <-- vcpu->pre_pcpu
10542  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10543  * - If 'ON' is set during this process, which means at least one
10544  *   interrupt is posted for this vCPU, we cannot block it, in
10545  *   this case, return 1, otherwise, return 0.
10546  *
10547  */
10548 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10549 {
10550         unsigned long flags;
10551         unsigned int dest;
10552         struct pi_desc old, new;
10553         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10554
10555         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10556                 !irq_remapping_cap(IRQ_POSTING_CAP))
10557                 return 0;
10558
10559         vcpu->pre_pcpu = vcpu->cpu;
10560         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10561                           vcpu->pre_pcpu), flags);
10562         list_add_tail(&vcpu->blocked_vcpu_list,
10563                       &per_cpu(blocked_vcpu_on_cpu,
10564                       vcpu->pre_pcpu));
10565         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10566                                vcpu->pre_pcpu), flags);
10567
10568         do {
10569                 old.control = new.control = pi_desc->control;
10570
10571                 /*
10572                  * We should not block the vCPU if
10573                  * an interrupt is posted for it.
10574                  */
10575                 if (pi_test_on(pi_desc) == 1) {
10576                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10577                                           vcpu->pre_pcpu), flags);
10578                         list_del(&vcpu->blocked_vcpu_list);
10579                         spin_unlock_irqrestore(
10580                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10581                                         vcpu->pre_pcpu), flags);
10582                         vcpu->pre_pcpu = -1;
10583
10584                         return 1;
10585                 }
10586
10587                 WARN((pi_desc->sn == 1),
10588                      "Warning: SN field of posted-interrupts "
10589                      "is set before blocking\n");
10590
10591                 /*
10592                  * Since vCPU can be preempted during this process,
10593                  * vcpu->cpu could be different with pre_pcpu, we
10594                  * need to set pre_pcpu as the destination of wakeup
10595                  * notification event, then we can find the right vCPU
10596                  * to wakeup in wakeup handler if interrupts happen
10597                  * when the vCPU is in blocked state.
10598                  */
10599                 dest = cpu_physical_id(vcpu->pre_pcpu);
10600
10601                 if (x2apic_enabled())
10602                         new.ndst = dest;
10603                 else
10604                         new.ndst = (dest << 8) & 0xFF00;
10605
10606                 /* set 'NV' to 'wakeup vector' */
10607                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10608         } while (cmpxchg(&pi_desc->control, old.control,
10609                         new.control) != old.control);
10610
10611         return 0;
10612 }
10613
10614 static void vmx_post_block(struct kvm_vcpu *vcpu)
10615 {
10616         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10617         struct pi_desc old, new;
10618         unsigned int dest;
10619         unsigned long flags;
10620
10621         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10622                 !irq_remapping_cap(IRQ_POSTING_CAP))
10623                 return;
10624
10625         do {
10626                 old.control = new.control = pi_desc->control;
10627
10628                 dest = cpu_physical_id(vcpu->cpu);
10629
10630                 if (x2apic_enabled())
10631                         new.ndst = dest;
10632                 else
10633                         new.ndst = (dest << 8) & 0xFF00;
10634
10635                 /* Allow posting non-urgent interrupts */
10636                 new.sn = 0;
10637
10638                 /* set 'NV' to 'notification vector' */
10639                 new.nv = POSTED_INTR_VECTOR;
10640         } while (cmpxchg(&pi_desc->control, old.control,
10641                         new.control) != old.control);
10642
10643         if(vcpu->pre_pcpu != -1) {
10644                 spin_lock_irqsave(
10645                         &per_cpu(blocked_vcpu_on_cpu_lock,
10646                         vcpu->pre_pcpu), flags);
10647                 list_del(&vcpu->blocked_vcpu_list);
10648                 spin_unlock_irqrestore(
10649                         &per_cpu(blocked_vcpu_on_cpu_lock,
10650                         vcpu->pre_pcpu), flags);
10651                 vcpu->pre_pcpu = -1;
10652         }
10653 }
10654
10655 /*
10656  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10657  *
10658  * @kvm: kvm
10659  * @host_irq: host irq of the interrupt
10660  * @guest_irq: gsi of the interrupt
10661  * @set: set or unset PI
10662  * returns 0 on success, < 0 on failure
10663  */
10664 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10665                               uint32_t guest_irq, bool set)
10666 {
10667         struct kvm_kernel_irq_routing_entry *e;
10668         struct kvm_irq_routing_table *irq_rt;
10669         struct kvm_lapic_irq irq;
10670         struct kvm_vcpu *vcpu;
10671         struct vcpu_data vcpu_info;
10672         int idx, ret = -EINVAL;
10673
10674         if (!kvm_arch_has_assigned_device(kvm) ||
10675                 !irq_remapping_cap(IRQ_POSTING_CAP))
10676                 return 0;
10677
10678         idx = srcu_read_lock(&kvm->irq_srcu);
10679         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10680         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10681
10682         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10683                 if (e->type != KVM_IRQ_ROUTING_MSI)
10684                         continue;
10685                 /*
10686                  * VT-d PI cannot support posting multicast/broadcast
10687                  * interrupts to a vCPU, we still use interrupt remapping
10688                  * for these kind of interrupts.
10689                  *
10690                  * For lowest-priority interrupts, we only support
10691                  * those with single CPU as the destination, e.g. user
10692                  * configures the interrupts via /proc/irq or uses
10693                  * irqbalance to make the interrupts single-CPU.
10694                  *
10695                  * We will support full lowest-priority interrupt later.
10696                  */
10697
10698                 kvm_set_msi_irq(e, &irq);
10699                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10700                         continue;
10701
10702                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10703                 vcpu_info.vector = irq.vector;
10704
10705                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10706                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10707
10708                 if (set)
10709                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10710                 else {
10711                         /* suppress notification event before unposting */
10712                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10713                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10714                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10715                 }
10716
10717                 if (ret < 0) {
10718                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10719                                         __func__);
10720                         goto out;
10721                 }
10722         }
10723
10724         ret = 0;
10725 out:
10726         srcu_read_unlock(&kvm->irq_srcu, idx);
10727         return ret;
10728 }
10729
10730 static struct kvm_x86_ops vmx_x86_ops = {
10731         .cpu_has_kvm_support = cpu_has_kvm_support,
10732         .disabled_by_bios = vmx_disabled_by_bios,
10733         .hardware_setup = hardware_setup,
10734         .hardware_unsetup = hardware_unsetup,
10735         .check_processor_compatibility = vmx_check_processor_compat,
10736         .hardware_enable = hardware_enable,
10737         .hardware_disable = hardware_disable,
10738         .cpu_has_accelerated_tpr = report_flexpriority,
10739         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10740
10741         .vcpu_create = vmx_create_vcpu,
10742         .vcpu_free = vmx_free_vcpu,
10743         .vcpu_reset = vmx_vcpu_reset,
10744
10745         .prepare_guest_switch = vmx_save_host_state,
10746         .vcpu_load = vmx_vcpu_load,
10747         .vcpu_put = vmx_vcpu_put,
10748
10749         .update_bp_intercept = update_exception_bitmap,
10750         .get_msr = vmx_get_msr,
10751         .set_msr = vmx_set_msr,
10752         .get_segment_base = vmx_get_segment_base,
10753         .get_segment = vmx_get_segment,
10754         .set_segment = vmx_set_segment,
10755         .get_cpl = vmx_get_cpl,
10756         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10757         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10758         .decache_cr3 = vmx_decache_cr3,
10759         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10760         .set_cr0 = vmx_set_cr0,
10761         .set_cr3 = vmx_set_cr3,
10762         .set_cr4 = vmx_set_cr4,
10763         .set_efer = vmx_set_efer,
10764         .get_idt = vmx_get_idt,
10765         .set_idt = vmx_set_idt,
10766         .get_gdt = vmx_get_gdt,
10767         .set_gdt = vmx_set_gdt,
10768         .get_dr6 = vmx_get_dr6,
10769         .set_dr6 = vmx_set_dr6,
10770         .set_dr7 = vmx_set_dr7,
10771         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10772         .cache_reg = vmx_cache_reg,
10773         .get_rflags = vmx_get_rflags,
10774         .set_rflags = vmx_set_rflags,
10775         .fpu_activate = vmx_fpu_activate,
10776         .fpu_deactivate = vmx_fpu_deactivate,
10777
10778         .tlb_flush = vmx_flush_tlb,
10779
10780         .run = vmx_vcpu_run,
10781         .handle_exit = vmx_handle_exit,
10782         .skip_emulated_instruction = skip_emulated_instruction,
10783         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10784         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10785         .patch_hypercall = vmx_patch_hypercall,
10786         .set_irq = vmx_inject_irq,
10787         .set_nmi = vmx_inject_nmi,
10788         .queue_exception = vmx_queue_exception,
10789         .cancel_injection = vmx_cancel_injection,
10790         .interrupt_allowed = vmx_interrupt_allowed,
10791         .nmi_allowed = vmx_nmi_allowed,
10792         .get_nmi_mask = vmx_get_nmi_mask,
10793         .set_nmi_mask = vmx_set_nmi_mask,
10794         .enable_nmi_window = enable_nmi_window,
10795         .enable_irq_window = enable_irq_window,
10796         .update_cr8_intercept = update_cr8_intercept,
10797         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10798         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10799         .get_enable_apicv = vmx_get_enable_apicv,
10800         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10801         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10802         .hwapic_irr_update = vmx_hwapic_irr_update,
10803         .hwapic_isr_update = vmx_hwapic_isr_update,
10804         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10805         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10806
10807         .set_tss_addr = vmx_set_tss_addr,
10808         .get_tdp_level = get_ept_level,
10809         .get_mt_mask = vmx_get_mt_mask,
10810
10811         .get_exit_info = vmx_get_exit_info,
10812
10813         .get_lpage_level = vmx_get_lpage_level,
10814
10815         .cpuid_update = vmx_cpuid_update,
10816
10817         .rdtscp_supported = vmx_rdtscp_supported,
10818         .invpcid_supported = vmx_invpcid_supported,
10819
10820         .set_supported_cpuid = vmx_set_supported_cpuid,
10821
10822         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10823
10824         .read_tsc_offset = vmx_read_tsc_offset,
10825         .write_tsc_offset = vmx_write_tsc_offset,
10826         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10827         .read_l1_tsc = vmx_read_l1_tsc,
10828
10829         .set_tdp_cr3 = vmx_set_cr3,
10830
10831         .check_intercept = vmx_check_intercept,
10832         .handle_external_intr = vmx_handle_external_intr,
10833         .mpx_supported = vmx_mpx_supported,
10834         .xsaves_supported = vmx_xsaves_supported,
10835
10836         .check_nested_events = vmx_check_nested_events,
10837
10838         .sched_in = vmx_sched_in,
10839
10840         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10841         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10842         .flush_log_dirty = vmx_flush_log_dirty,
10843         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10844
10845         .pre_block = vmx_pre_block,
10846         .post_block = vmx_post_block,
10847
10848         .pmu_ops = &intel_pmu_ops,
10849
10850         .update_pi_irte = vmx_update_pi_irte,
10851 };
10852
10853 static int __init vmx_init(void)
10854 {
10855         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10856                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10857         if (r)
10858                 return r;
10859
10860 #ifdef CONFIG_KEXEC_CORE
10861         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10862                            crash_vmclear_local_loaded_vmcss);
10863 #endif
10864
10865         return 0;
10866 }
10867
10868 static void __exit vmx_exit(void)
10869 {
10870 #ifdef CONFIG_KEXEC_CORE
10871         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10872         synchronize_rcu();
10873 #endif
10874
10875         kvm_exit();
10876 }
10877
10878 module_init(vmx_init)
10879 module_exit(vmx_exit)