arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601 };
 602
 603 enum segment_cache_field {
 604         SEG_FIELD_SEL = 0,
 605         SEG_FIELD_BASE = 1,
 606         SEG_FIELD_LIMIT = 2,
 607         SEG_FIELD_AR = 3,
 608
 609         SEG_FIELD_NR = 4
 610 };
 611
 612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 613 {
 614         return container_of(vcpu, struct vcpu_vmx, vcpu);
 615 }
 616
 617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 618 {
 619         return &(to_vmx(vcpu)->pi_desc);
 620 }
 621
 622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 623 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 624 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 625                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 626
 627
 628 static unsigned long shadow_read_only_fields[] = {
 629         /*
 630          * We do NOT shadow fields that are modified when L0
 631          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 632          * VMXON...) executed by L1.
 633          * For example, VM_INSTRUCTION_ERROR is read
 634          * by L1 if a vmx instruction fails (part of the error path).
 635          * Note the code assumes this logic. If for some reason
 636          * we start shadowing these fields then we need to
 637          * force a shadow sync when L0 emulates vmx instructions
 638          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 639          * by nested_vmx_failValid)
 640          */
 641         VM_EXIT_REASON,
 642         VM_EXIT_INTR_INFO,
 643         VM_EXIT_INSTRUCTION_LEN,
 644         IDT_VECTORING_INFO_FIELD,
 645         IDT_VECTORING_ERROR_CODE,
 646         VM_EXIT_INTR_ERROR_CODE,
 647         EXIT_QUALIFICATION,
 648         GUEST_LINEAR_ADDRESS,
 649         GUEST_PHYSICAL_ADDRESS
 650 };
 651 static int max_shadow_read_only_fields =
 652         ARRAY_SIZE(shadow_read_only_fields);
 653
 654 static unsigned long shadow_read_write_fields[] = {
 655         TPR_THRESHOLD,
 656         GUEST_RIP,
 657         GUEST_RSP,
 658         GUEST_CR0,
 659         GUEST_CR3,
 660         GUEST_CR4,
 661         GUEST_INTERRUPTIBILITY_INFO,
 662         GUEST_RFLAGS,
 663         GUEST_CS_SELECTOR,
 664         GUEST_CS_AR_BYTES,
 665         GUEST_CS_LIMIT,
 666         GUEST_CS_BASE,
 667         GUEST_ES_BASE,
 668         GUEST_BNDCFGS,
 669         CR0_GUEST_HOST_MASK,
 670         CR0_READ_SHADOW,
 671         CR4_READ_SHADOW,
 672         TSC_OFFSET,
 673         EXCEPTION_BITMAP,
 674         CPU_BASED_VM_EXEC_CONTROL,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         VM_ENTRY_INTR_INFO_FIELD,
 677         VM_ENTRY_INSTRUCTION_LEN,
 678         VM_ENTRY_EXCEPTION_ERROR_CODE,
 679         HOST_FS_BASE,
 680         HOST_GS_BASE,
 681         HOST_FS_SELECTOR,
 682         HOST_GS_SELECTOR
 683 };
 684 static int max_shadow_read_write_fields =
 685         ARRAY_SIZE(shadow_read_write_fields);
 686
 687 static const unsigned short vmcs_field_to_offset_table[] = {
 688         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 689         FIELD(POSTED_INTR_NV, posted_intr_nv),
 690         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 691         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 692         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 693         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 694         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 695         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 696         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 697         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 698         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 699         FIELD(HOST_ES_SELECTOR, host_es_selector),
 700         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 701         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 702         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 703         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 704         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 705         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 706         FIELD64(IO_BITMAP_A, io_bitmap_a),
 707         FIELD64(IO_BITMAP_B, io_bitmap_b),
 708         FIELD64(MSR_BITMAP, msr_bitmap),
 709         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 710         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 711         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 712         FIELD64(TSC_OFFSET, tsc_offset),
 713         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 714         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 715         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 716         FIELD64(EPT_POINTER, ept_pointer),
 717         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 718         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 719         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 720         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 721         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 722         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 723         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 724         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 725         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 726         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 727         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 728         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 729         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 730         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 731         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 732         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 733         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 734         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 735         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 736         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 737         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 738         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 740         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 741         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 742         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 743         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 744         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 745         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 746         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 747         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 748         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 749         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 750         FIELD(TPR_THRESHOLD, tpr_threshold),
 751         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 752         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 753         FIELD(VM_EXIT_REASON, vm_exit_reason),
 754         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 755         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 756         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 757         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 758         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 759         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 760         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 761         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 762         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 763         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 764         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 765         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 766         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 767         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 768         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 769         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 770         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 771         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 772         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 773         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 774         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 775         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 776         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 777         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 778         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 779         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 780         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 781         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 782         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 783         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 784         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 785         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 786         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 787         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 788         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 789         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 790         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 791         FIELD(EXIT_QUALIFICATION, exit_qualification),
 792         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 793         FIELD(GUEST_CR0, guest_cr0),
 794         FIELD(GUEST_CR3, guest_cr3),
 795         FIELD(GUEST_CR4, guest_cr4),
 796         FIELD(GUEST_ES_BASE, guest_es_base),
 797         FIELD(GUEST_CS_BASE, guest_cs_base),
 798         FIELD(GUEST_SS_BASE, guest_ss_base),
 799         FIELD(GUEST_DS_BASE, guest_ds_base),
 800         FIELD(GUEST_FS_BASE, guest_fs_base),
 801         FIELD(GUEST_GS_BASE, guest_gs_base),
 802         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 803         FIELD(GUEST_TR_BASE, guest_tr_base),
 804         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 805         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 806         FIELD(GUEST_DR7, guest_dr7),
 807         FIELD(GUEST_RSP, guest_rsp),
 808         FIELD(GUEST_RIP, guest_rip),
 809         FIELD(GUEST_RFLAGS, guest_rflags),
 810         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 811         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 812         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 813         FIELD(HOST_CR0, host_cr0),
 814         FIELD(HOST_CR3, host_cr3),
 815         FIELD(HOST_CR4, host_cr4),
 816         FIELD(HOST_FS_BASE, host_fs_base),
 817         FIELD(HOST_GS_BASE, host_gs_base),
 818         FIELD(HOST_TR_BASE, host_tr_base),
 819         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 820         FIELD(HOST_IDTR_BASE, host_idtr_base),
 821         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 822         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 823         FIELD(HOST_RSP, host_rsp),
 824         FIELD(HOST_RIP, host_rip),
 825 };
 826
 827 static inline short vmcs_field_to_offset(unsigned long field)
 828 {
 829         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 830
 831         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 832             vmcs_field_to_offset_table[field] == 0)
 833                 return -ENOENT;
 834
 835         return vmcs_field_to_offset_table[field];
 836 }
 837
 838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 839 {
 840         return to_vmx(vcpu)->nested.current_vmcs12;
 841 }
 842
 843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 844 {
 845         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 846         if (is_error_page(page))
 847                 return NULL;
 848
 849         return page;
 850 }
 851
 852 static void nested_release_page(struct page *page)
 853 {
 854         kvm_release_page_dirty(page);
 855 }
 856
 857 static void nested_release_page_clean(struct page *page)
 858 {
 859         kvm_release_page_clean(page);
 860 }
 861
 862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 863 static u64 construct_eptp(unsigned long root_hpa);
 864 static void kvm_cpu_vmxon(u64 addr);
 865 static void kvm_cpu_vmxoff(void);
 866 static bool vmx_mpx_supported(void);
 867 static bool vmx_xsaves_supported(void);
 868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 872                             struct kvm_segment *var, int seg);
 873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 875 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 876 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 877 static int alloc_identity_pagetable(struct kvm *kvm);
 878
 879 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 880 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 881 /*
 882  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 883  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 884  */
 885 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 886 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 887
 888 /*
 889  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 890  * can find which vCPU should be waken up.
 891  */
 892 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 893 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 894
 895 static unsigned long *vmx_io_bitmap_a;
 896 static unsigned long *vmx_io_bitmap_b;
 897 static unsigned long *vmx_msr_bitmap_legacy;
 898 static unsigned long *vmx_msr_bitmap_longmode;
 899 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 900 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 901 static unsigned long *vmx_msr_bitmap_nested;
 902 static unsigned long *vmx_vmread_bitmap;
 903 static unsigned long *vmx_vmwrite_bitmap;
 904
 905 static bool cpu_has_load_ia32_efer;
 906 static bool cpu_has_load_perf_global_ctrl;
 907
 908 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 909 static DEFINE_SPINLOCK(vmx_vpid_lock);
 910
 911 static struct vmcs_config {
 912         int size;
 913         int order;
 914         u32 revision_id;
 915         u32 pin_based_exec_ctrl;
 916         u32 cpu_based_exec_ctrl;
 917         u32 cpu_based_2nd_exec_ctrl;
 918         u32 vmexit_ctrl;
 919         u32 vmentry_ctrl;
 920 } vmcs_config;
 921
 922 static struct vmx_capability {
 923         u32 ept;
 924         u32 vpid;
 925 } vmx_capability;
 926
 927 #define VMX_SEGMENT_FIELD(seg)                                  \
 928         [VCPU_SREG_##seg] = {                                   \
 929                 .selector = GUEST_##seg##_SELECTOR,             \
 930                 .base = GUEST_##seg##_BASE,                     \
 931                 .limit = GUEST_##seg##_LIMIT,                   \
 932                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 933         }
 934
 935 static const struct kvm_vmx_segment_field {
 936         unsigned selector;
 937         unsigned base;
 938         unsigned limit;
 939         unsigned ar_bytes;
 940 } kvm_vmx_segment_fields[] = {
 941         VMX_SEGMENT_FIELD(CS),
 942         VMX_SEGMENT_FIELD(DS),
 943         VMX_SEGMENT_FIELD(ES),
 944         VMX_SEGMENT_FIELD(FS),
 945         VMX_SEGMENT_FIELD(GS),
 946         VMX_SEGMENT_FIELD(SS),
 947         VMX_SEGMENT_FIELD(TR),
 948         VMX_SEGMENT_FIELD(LDTR),
 949 };
 950
 951 static u64 host_efer;
 952
 953 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 954
 955 /*
 956  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 957  * away by decrementing the array size.
 958  */
 959 static const u32 vmx_msr_index[] = {
 960 #ifdef CONFIG_X86_64
 961         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 962 #endif
 963         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 964 };
 965
 966 static inline bool is_exception_n(u32 intr_info, u8 vector)
 967 {
 968         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 969                              INTR_INFO_VALID_MASK)) ==
 970                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 971 }
 972
 973 static inline bool is_debug(u32 intr_info)
 974 {
 975         return is_exception_n(intr_info, DB_VECTOR);
 976 }
 977
 978 static inline bool is_breakpoint(u32 intr_info)
 979 {
 980         return is_exception_n(intr_info, BP_VECTOR);
 981 }
 982
 983 static inline bool is_page_fault(u32 intr_info)
 984 {
 985         return is_exception_n(intr_info, PF_VECTOR);
 986 }
 987
 988 static inline bool is_no_device(u32 intr_info)
 989 {
 990         return is_exception_n(intr_info, NM_VECTOR);
 991 }
 992
 993 static inline bool is_invalid_opcode(u32 intr_info)
 994 {
 995         return is_exception_n(intr_info, UD_VECTOR);
 996 }
 997
 998 static inline bool is_external_interrupt(u32 intr_info)
 999 {
1000         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1001                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1002 }
1003
1004 static inline bool is_machine_check(u32 intr_info)
1005 {
1006         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1007                              INTR_INFO_VALID_MASK)) ==
1008                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1009 }
1010
1011 static inline bool cpu_has_vmx_msr_bitmap(void)
1012 {
1013         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1014 }
1015
1016 static inline bool cpu_has_vmx_tpr_shadow(void)
1017 {
1018         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1019 }
1020
1021 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1022 {
1023         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1024 }
1025
1026 static inline bool cpu_has_secondary_exec_ctrls(void)
1027 {
1028         return vmcs_config.cpu_based_exec_ctrl &
1029                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1030 }
1031
1032 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1033 {
1034         return vmcs_config.cpu_based_2nd_exec_ctrl &
1035                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1036 }
1037
1038 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1039 {
1040         return vmcs_config.cpu_based_2nd_exec_ctrl &
1041                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1042 }
1043
1044 static inline bool cpu_has_vmx_apic_register_virt(void)
1045 {
1046         return vmcs_config.cpu_based_2nd_exec_ctrl &
1047                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1048 }
1049
1050 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1051 {
1052         return vmcs_config.cpu_based_2nd_exec_ctrl &
1053                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1054 }
1055
1056 static inline bool cpu_has_vmx_posted_intr(void)
1057 {
1058         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1059                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1060 }
1061
1062 static inline bool cpu_has_vmx_apicv(void)
1063 {
1064         return cpu_has_vmx_apic_register_virt() &&
1065                 cpu_has_vmx_virtual_intr_delivery() &&
1066                 cpu_has_vmx_posted_intr();
1067 }
1068
1069 static inline bool cpu_has_vmx_flexpriority(void)
1070 {
1071         return cpu_has_vmx_tpr_shadow() &&
1072                 cpu_has_vmx_virtualize_apic_accesses();
1073 }
1074
1075 static inline bool cpu_has_vmx_ept_execute_only(void)
1076 {
1077         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1078 }
1079
1080 static inline bool cpu_has_vmx_ept_2m_page(void)
1081 {
1082         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1083 }
1084
1085 static inline bool cpu_has_vmx_ept_1g_page(void)
1086 {
1087         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1088 }
1089
1090 static inline bool cpu_has_vmx_ept_4levels(void)
1091 {
1092         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1093 }
1094
1095 static inline bool cpu_has_vmx_ept_ad_bits(void)
1096 {
1097         return vmx_capability.ept & VMX_EPT_AD_BIT;
1098 }
1099
1100 static inline bool cpu_has_vmx_invept_context(void)
1101 {
1102         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1103 }
1104
1105 static inline bool cpu_has_vmx_invept_global(void)
1106 {
1107         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1108 }
1109
1110 static inline bool cpu_has_vmx_invvpid_single(void)
1111 {
1112         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1113 }
1114
1115 static inline bool cpu_has_vmx_invvpid_global(void)
1116 {
1117         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1118 }
1119
1120 static inline bool cpu_has_vmx_ept(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_ENABLE_EPT;
1124 }
1125
1126 static inline bool cpu_has_vmx_unrestricted_guest(void)
1127 {
1128         return vmcs_config.cpu_based_2nd_exec_ctrl &
1129                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1130 }
1131
1132 static inline bool cpu_has_vmx_ple(void)
1133 {
1134         return vmcs_config.cpu_based_2nd_exec_ctrl &
1135                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1136 }
1137
1138 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1139 {
1140         return flexpriority_enabled && lapic_in_kernel(vcpu);
1141 }
1142
1143 static inline bool cpu_has_vmx_vpid(void)
1144 {
1145         return vmcs_config.cpu_based_2nd_exec_ctrl &
1146                 SECONDARY_EXEC_ENABLE_VPID;
1147 }
1148
1149 static inline bool cpu_has_vmx_rdtscp(void)
1150 {
1151         return vmcs_config.cpu_based_2nd_exec_ctrl &
1152                 SECONDARY_EXEC_RDTSCP;
1153 }
1154
1155 static inline bool cpu_has_vmx_invpcid(void)
1156 {
1157         return vmcs_config.cpu_based_2nd_exec_ctrl &
1158                 SECONDARY_EXEC_ENABLE_INVPCID;
1159 }
1160
1161 static inline bool cpu_has_virtual_nmis(void)
1162 {
1163         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1164 }
1165
1166 static inline bool cpu_has_vmx_wbinvd_exit(void)
1167 {
1168         return vmcs_config.cpu_based_2nd_exec_ctrl &
1169                 SECONDARY_EXEC_WBINVD_EXITING;
1170 }
1171
1172 static inline bool cpu_has_vmx_shadow_vmcs(void)
1173 {
1174         u64 vmx_msr;
1175         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1176         /* check if the cpu supports writing r/o exit information fields */
1177         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1178                 return false;
1179
1180         return vmcs_config.cpu_based_2nd_exec_ctrl &
1181                 SECONDARY_EXEC_SHADOW_VMCS;
1182 }
1183
1184 static inline bool cpu_has_vmx_pml(void)
1185 {
1186         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1187 }
1188
1189 static inline bool cpu_has_vmx_tsc_scaling(void)
1190 {
1191         return vmcs_config.cpu_based_2nd_exec_ctrl &
1192                 SECONDARY_EXEC_TSC_SCALING;
1193 }
1194
1195 static inline bool report_flexpriority(void)
1196 {
1197         return flexpriority_enabled;
1198 }
1199
1200 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1201 {
1202         return vmcs12->cpu_based_vm_exec_control & bit;
1203 }
1204
1205 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1206 {
1207         return (vmcs12->cpu_based_vm_exec_control &
1208                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1209                 (vmcs12->secondary_vm_exec_control & bit);
1210 }
1211
1212 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1213 {
1214         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1215 }
1216
1217 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1218 {
1219         return vmcs12->pin_based_vm_exec_control &
1220                 PIN_BASED_VMX_PREEMPTION_TIMER;
1221 }
1222
1223 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1224 {
1225         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1226 }
1227
1228 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1229 {
1230         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1231                 vmx_xsaves_supported();
1232 }
1233
1234 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1235 {
1236         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1237 }
1238
1239 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1240 {
1241         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1242 }
1243
1244 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1245 {
1246         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1247 }
1248
1249 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1250 {
1251         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1252 }
1253
1254 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1255 {
1256         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1257 }
1258
1259 static inline bool is_exception(u32 intr_info)
1260 {
1261         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1262                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1263 }
1264
1265 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1266                               u32 exit_intr_info,
1267                               unsigned long exit_qualification);
1268 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1269                         struct vmcs12 *vmcs12,
1270                         u32 reason, unsigned long qualification);
1271
1272 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1273 {
1274         int i;
1275
1276         for (i = 0; i < vmx->nmsrs; ++i)
1277                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1278                         return i;
1279         return -1;
1280 }
1281
1282 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1283 {
1284     struct {
1285         u64 vpid : 16;
1286         u64 rsvd : 48;
1287         u64 gva;
1288     } operand = { vpid, 0, gva };
1289
1290     asm volatile (__ex(ASM_VMX_INVVPID)
1291                   /* CF==1 or ZF==1 --> rc = -1 */
1292                   "; ja 1f ; ud2 ; 1:"
1293                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1294 }
1295
1296 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1297 {
1298         struct {
1299                 u64 eptp, gpa;
1300         } operand = {eptp, gpa};
1301
1302         asm volatile (__ex(ASM_VMX_INVEPT)
1303                         /* CF==1 or ZF==1 --> rc = -1 */
1304                         "; ja 1f ; ud2 ; 1:\n"
1305                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1306 }
1307
1308 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1309 {
1310         int i;
1311
1312         i = __find_msr_index(vmx, msr);
1313         if (i >= 0)
1314                 return &vmx->guest_msrs[i];
1315         return NULL;
1316 }
1317
1318 static void vmcs_clear(struct vmcs *vmcs)
1319 {
1320         u64 phys_addr = __pa(vmcs);
1321         u8 error;
1322
1323         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1324                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1325                       : "cc", "memory");
1326         if (error)
1327                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1328                        vmcs, phys_addr);
1329 }
1330
1331 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         vmcs_clear(loaded_vmcs->vmcs);
1334         loaded_vmcs->cpu = -1;
1335         loaded_vmcs->launched = 0;
1336 }
1337
1338 static void vmcs_load(struct vmcs *vmcs)
1339 {
1340         u64 phys_addr = __pa(vmcs);
1341         u8 error;
1342
1343         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1344                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1345                         : "cc", "memory");
1346         if (error)
1347                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1348                        vmcs, phys_addr);
1349 }
1350
1351 #ifdef CONFIG_KEXEC_CORE
1352 /*
1353  * This bitmap is used to indicate whether the vmclear
1354  * operation is enabled on all cpus. All disabled by
1355  * default.
1356  */
1357 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1358
1359 static inline void crash_enable_local_vmclear(int cpu)
1360 {
1361         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1362 }
1363
1364 static inline void crash_disable_local_vmclear(int cpu)
1365 {
1366         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1367 }
1368
1369 static inline int crash_local_vmclear_enabled(int cpu)
1370 {
1371         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1372 }
1373
1374 static void crash_vmclear_local_loaded_vmcss(void)
1375 {
1376         int cpu = raw_smp_processor_id();
1377         struct loaded_vmcs *v;
1378
1379         if (!crash_local_vmclear_enabled(cpu))
1380                 return;
1381
1382         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1383                             loaded_vmcss_on_cpu_link)
1384                 vmcs_clear(v->vmcs);
1385 }
1386 #else
1387 static inline void crash_enable_local_vmclear(int cpu) { }
1388 static inline void crash_disable_local_vmclear(int cpu) { }
1389 #endif /* CONFIG_KEXEC_CORE */
1390
1391 static void __loaded_vmcs_clear(void *arg)
1392 {
1393         struct loaded_vmcs *loaded_vmcs = arg;
1394         int cpu = raw_smp_processor_id();
1395
1396         if (loaded_vmcs->cpu != cpu)
1397                 return; /* vcpu migration can race with cpu offline */
1398         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1399                 per_cpu(current_vmcs, cpu) = NULL;
1400         crash_disable_local_vmclear(cpu);
1401         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1402
1403         /*
1404          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1405          * is before setting loaded_vmcs->vcpu to -1 which is done in
1406          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1407          * then adds the vmcs into percpu list before it is deleted.
1408          */
1409         smp_wmb();
1410
1411         loaded_vmcs_init(loaded_vmcs);
1412         crash_enable_local_vmclear(cpu);
1413 }
1414
1415 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1416 {
1417         int cpu = loaded_vmcs->cpu;
1418
1419         if (cpu != -1)
1420                 smp_call_function_single(cpu,
1421                          __loaded_vmcs_clear, loaded_vmcs, 1);
1422 }
1423
1424 static inline void vpid_sync_vcpu_single(int vpid)
1425 {
1426         if (vpid == 0)
1427                 return;
1428
1429         if (cpu_has_vmx_invvpid_single())
1430                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1431 }
1432
1433 static inline void vpid_sync_vcpu_global(void)
1434 {
1435         if (cpu_has_vmx_invvpid_global())
1436                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1437 }
1438
1439 static inline void vpid_sync_context(int vpid)
1440 {
1441         if (cpu_has_vmx_invvpid_single())
1442                 vpid_sync_vcpu_single(vpid);
1443         else
1444                 vpid_sync_vcpu_global();
1445 }
1446
1447 static inline void ept_sync_global(void)
1448 {
1449         if (cpu_has_vmx_invept_global())
1450                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1451 }
1452
1453 static inline void ept_sync_context(u64 eptp)
1454 {
1455         if (enable_ept) {
1456                 if (cpu_has_vmx_invept_context())
1457                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1458                 else
1459                         ept_sync_global();
1460         }
1461 }
1462
1463 static __always_inline void vmcs_check16(unsigned long field)
1464 {
1465         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1466                          "16-bit accessor invalid for 64-bit field");
1467         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1468                          "16-bit accessor invalid for 64-bit high field");
1469         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1470                          "16-bit accessor invalid for 32-bit high field");
1471         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1472                          "16-bit accessor invalid for natural width field");
1473 }
1474
1475 static __always_inline void vmcs_check32(unsigned long field)
1476 {
1477         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1478                          "32-bit accessor invalid for 16-bit field");
1479         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1480                          "32-bit accessor invalid for natural width field");
1481 }
1482
1483 static __always_inline void vmcs_check64(unsigned long field)
1484 {
1485         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1486                          "64-bit accessor invalid for 16-bit field");
1487         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1488                          "64-bit accessor invalid for 64-bit high field");
1489         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1490                          "64-bit accessor invalid for 32-bit field");
1491         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1492                          "64-bit accessor invalid for natural width field");
1493 }
1494
1495 static __always_inline void vmcs_checkl(unsigned long field)
1496 {
1497         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1498                          "Natural width accessor invalid for 16-bit field");
1499         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1500                          "Natural width accessor invalid for 64-bit field");
1501         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1502                          "Natural width accessor invalid for 64-bit high field");
1503         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1504                          "Natural width accessor invalid for 32-bit field");
1505 }
1506
1507 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1508 {
1509         unsigned long value;
1510
1511         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1512                       : "=a"(value) : "d"(field) : "cc");
1513         return value;
1514 }
1515
1516 static __always_inline u16 vmcs_read16(unsigned long field)
1517 {
1518         vmcs_check16(field);
1519         return __vmcs_readl(field);
1520 }
1521
1522 static __always_inline u32 vmcs_read32(unsigned long field)
1523 {
1524         vmcs_check32(field);
1525         return __vmcs_readl(field);
1526 }
1527
1528 static __always_inline u64 vmcs_read64(unsigned long field)
1529 {
1530         vmcs_check64(field);
1531 #ifdef CONFIG_X86_64
1532         return __vmcs_readl(field);
1533 #else
1534         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1535 #endif
1536 }
1537
1538 static __always_inline unsigned long vmcs_readl(unsigned long field)
1539 {
1540         vmcs_checkl(field);
1541         return __vmcs_readl(field);
1542 }
1543
1544 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1545 {
1546         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1547                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1548         dump_stack();
1549 }
1550
1551 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1552 {
1553         u8 error;
1554
1555         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1556                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1557         if (unlikely(error))
1558                 vmwrite_error(field, value);
1559 }
1560
1561 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1562 {
1563         vmcs_check16(field);
1564         __vmcs_writel(field, value);
1565 }
1566
1567 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1568 {
1569         vmcs_check32(field);
1570         __vmcs_writel(field, value);
1571 }
1572
1573 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1574 {
1575         vmcs_check64(field);
1576         __vmcs_writel(field, value);
1577 #ifndef CONFIG_X86_64
1578         asm volatile ("");
1579         __vmcs_writel(field+1, value >> 32);
1580 #endif
1581 }
1582
1583 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1584 {
1585         vmcs_checkl(field);
1586         __vmcs_writel(field, value);
1587 }
1588
1589 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1590 {
1591         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1592                          "vmcs_clear_bits does not support 64-bit fields");
1593         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1594 }
1595
1596 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1597 {
1598         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1599                          "vmcs_set_bits does not support 64-bit fields");
1600         __vmcs_writel(field, __vmcs_readl(field) | mask);
1601 }
1602
1603 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1604 {
1605         vmcs_write32(VM_ENTRY_CONTROLS, val);
1606         vmx->vm_entry_controls_shadow = val;
1607 }
1608
1609 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1610 {
1611         if (vmx->vm_entry_controls_shadow != val)
1612                 vm_entry_controls_init(vmx, val);
1613 }
1614
1615 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1616 {
1617         return vmx->vm_entry_controls_shadow;
1618 }
1619
1620
1621 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1622 {
1623         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1624 }
1625
1626 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1627 {
1628         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1629 }
1630
1631 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1632 {
1633         vmcs_write32(VM_EXIT_CONTROLS, val);
1634         vmx->vm_exit_controls_shadow = val;
1635 }
1636
1637 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1638 {
1639         if (vmx->vm_exit_controls_shadow != val)
1640                 vm_exit_controls_init(vmx, val);
1641 }
1642
1643 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1644 {
1645         return vmx->vm_exit_controls_shadow;
1646 }
1647
1648
1649 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1650 {
1651         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1652 }
1653
1654 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1655 {
1656         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1657 }
1658
1659 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1660 {
1661         vmx->segment_cache.bitmask = 0;
1662 }
1663
1664 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1665                                        unsigned field)
1666 {
1667         bool ret;
1668         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1669
1670         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1671                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1672                 vmx->segment_cache.bitmask = 0;
1673         }
1674         ret = vmx->segment_cache.bitmask & mask;
1675         vmx->segment_cache.bitmask |= mask;
1676         return ret;
1677 }
1678
1679 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1680 {
1681         u16 *p = &vmx->segment_cache.seg[seg].selector;
1682
1683         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1684                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1685         return *p;
1686 }
1687
1688 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1689 {
1690         ulong *p = &vmx->segment_cache.seg[seg].base;
1691
1692         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1693                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1694         return *p;
1695 }
1696
1697 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1698 {
1699         u32 *p = &vmx->segment_cache.seg[seg].limit;
1700
1701         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1702                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1703         return *p;
1704 }
1705
1706 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1707 {
1708         u32 *p = &vmx->segment_cache.seg[seg].ar;
1709
1710         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1711                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1712         return *p;
1713 }
1714
1715 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1716 {
1717         u32 eb;
1718
1719         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1720              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1721         if ((vcpu->guest_debug &
1722              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1723             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1724                 eb |= 1u << BP_VECTOR;
1725         if (to_vmx(vcpu)->rmode.vm86_active)
1726                 eb = ~0;
1727         if (enable_ept)
1728                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1729         if (vcpu->fpu_active)
1730                 eb &= ~(1u << NM_VECTOR);
1731
1732         /* When we are running a nested L2 guest and L1 specified for it a
1733          * certain exception bitmap, we must trap the same exceptions and pass
1734          * them to L1. When running L2, we will only handle the exceptions
1735          * specified above if L1 did not want them.
1736          */
1737         if (is_guest_mode(vcpu))
1738                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1739
1740         vmcs_write32(EXCEPTION_BITMAP, eb);
1741 }
1742
1743 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1744                 unsigned long entry, unsigned long exit)
1745 {
1746         vm_entry_controls_clearbit(vmx, entry);
1747         vm_exit_controls_clearbit(vmx, exit);
1748 }
1749
1750 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1751 {
1752         unsigned i;
1753         struct msr_autoload *m = &vmx->msr_autoload;
1754
1755         switch (msr) {
1756         case MSR_EFER:
1757                 if (cpu_has_load_ia32_efer) {
1758                         clear_atomic_switch_msr_special(vmx,
1759                                         VM_ENTRY_LOAD_IA32_EFER,
1760                                         VM_EXIT_LOAD_IA32_EFER);
1761                         return;
1762                 }
1763                 break;
1764         case MSR_CORE_PERF_GLOBAL_CTRL:
1765                 if (cpu_has_load_perf_global_ctrl) {
1766                         clear_atomic_switch_msr_special(vmx,
1767                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1768                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1769                         return;
1770                 }
1771                 break;
1772         }
1773
1774         for (i = 0; i < m->nr; ++i)
1775                 if (m->guest[i].index == msr)
1776                         break;
1777
1778         if (i == m->nr)
1779                 return;
1780         --m->nr;
1781         m->guest[i] = m->guest[m->nr];
1782         m->host[i] = m->host[m->nr];
1783         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1784         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1785 }
1786
1787 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1788                 unsigned long entry, unsigned long exit,
1789                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1790                 u64 guest_val, u64 host_val)
1791 {
1792         vmcs_write64(guest_val_vmcs, guest_val);
1793         vmcs_write64(host_val_vmcs, host_val);
1794         vm_entry_controls_setbit(vmx, entry);
1795         vm_exit_controls_setbit(vmx, exit);
1796 }
1797
1798 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1799                                   u64 guest_val, u64 host_val)
1800 {
1801         unsigned i;
1802         struct msr_autoload *m = &vmx->msr_autoload;
1803
1804         switch (msr) {
1805         case MSR_EFER:
1806                 if (cpu_has_load_ia32_efer) {
1807                         add_atomic_switch_msr_special(vmx,
1808                                         VM_ENTRY_LOAD_IA32_EFER,
1809                                         VM_EXIT_LOAD_IA32_EFER,
1810                                         GUEST_IA32_EFER,
1811                                         HOST_IA32_EFER,
1812                                         guest_val, host_val);
1813                         return;
1814                 }
1815                 break;
1816         case MSR_CORE_PERF_GLOBAL_CTRL:
1817                 if (cpu_has_load_perf_global_ctrl) {
1818                         add_atomic_switch_msr_special(vmx,
1819                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1820                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1821                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1822                                         HOST_IA32_PERF_GLOBAL_CTRL,
1823                                         guest_val, host_val);
1824                         return;
1825                 }
1826                 break;
1827         }
1828
1829         for (i = 0; i < m->nr; ++i)
1830                 if (m->guest[i].index == msr)
1831                         break;
1832
1833         if (i == NR_AUTOLOAD_MSRS) {
1834                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1835                                 "Can't add msr %x\n", msr);
1836                 return;
1837         } else if (i == m->nr) {
1838                 ++m->nr;
1839                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1840                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1841         }
1842
1843         m->guest[i].index = msr;
1844         m->guest[i].value = guest_val;
1845         m->host[i].index = msr;
1846         m->host[i].value = host_val;
1847 }
1848
1849 static void reload_tss(void)
1850 {
1851         /*
1852          * VT restores TR but not its size.  Useless.
1853          */
1854         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1855         struct desc_struct *descs;
1856
1857         descs = (void *)gdt->address;
1858         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1859         load_TR_desc();
1860 }
1861
1862 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1863 {
1864         u64 guest_efer;
1865         u64 ignore_bits;
1866
1867         guest_efer = vmx->vcpu.arch.efer;
1868
1869         /*
1870          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1871          * outside long mode
1872          */
1873         ignore_bits = EFER_NX | EFER_SCE;
1874 #ifdef CONFIG_X86_64
1875         ignore_bits |= EFER_LMA | EFER_LME;
1876         /* SCE is meaningful only in long mode on Intel */
1877         if (guest_efer & EFER_LMA)
1878                 ignore_bits &= ~(u64)EFER_SCE;
1879 #endif
1880         guest_efer &= ~ignore_bits;
1881         guest_efer |= host_efer & ignore_bits;
1882         vmx->guest_msrs[efer_offset].data = guest_efer;
1883         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1884
1885         clear_atomic_switch_msr(vmx, MSR_EFER);
1886
1887         /*
1888          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1889          * On CPUs that support "load IA32_EFER", always switch EFER
1890          * atomically, since it's faster than switching it manually.
1891          */
1892         if (cpu_has_load_ia32_efer ||
1893             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1894                 guest_efer = vmx->vcpu.arch.efer;
1895                 if (!(guest_efer & EFER_LMA))
1896                         guest_efer &= ~EFER_LME;
1897                 if (guest_efer != host_efer)
1898                         add_atomic_switch_msr(vmx, MSR_EFER,
1899                                               guest_efer, host_efer);
1900                 return false;
1901         }
1902
1903         return true;
1904 }
1905
1906 static unsigned long segment_base(u16 selector)
1907 {
1908         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1909         struct desc_struct *d;
1910         unsigned long table_base;
1911         unsigned long v;
1912
1913         if (!(selector & ~3))
1914                 return 0;
1915
1916         table_base = gdt->address;
1917
1918         if (selector & 4) {           /* from ldt */
1919                 u16 ldt_selector = kvm_read_ldt();
1920
1921                 if (!(ldt_selector & ~3))
1922                         return 0;
1923
1924                 table_base = segment_base(ldt_selector);
1925         }
1926         d = (struct desc_struct *)(table_base + (selector & ~7));
1927         v = get_desc_base(d);
1928 #ifdef CONFIG_X86_64
1929        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1930                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1931 #endif
1932         return v;
1933 }
1934
1935 static inline unsigned long kvm_read_tr_base(void)
1936 {
1937         u16 tr;
1938         asm("str %0" : "=g"(tr));
1939         return segment_base(tr);
1940 }
1941
1942 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1943 {
1944         struct vcpu_vmx *vmx = to_vmx(vcpu);
1945         int i;
1946
1947         if (vmx->host_state.loaded)
1948                 return;
1949
1950         vmx->host_state.loaded = 1;
1951         /*
1952          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1953          * allow segment selectors with cpl > 0 or ti == 1.
1954          */
1955         vmx->host_state.ldt_sel = kvm_read_ldt();
1956         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1957         savesegment(fs, vmx->host_state.fs_sel);
1958         if (!(vmx->host_state.fs_sel & 7)) {
1959                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1960                 vmx->host_state.fs_reload_needed = 0;
1961         } else {
1962                 vmcs_write16(HOST_FS_SELECTOR, 0);
1963                 vmx->host_state.fs_reload_needed = 1;
1964         }
1965         savesegment(gs, vmx->host_state.gs_sel);
1966         if (!(vmx->host_state.gs_sel & 7))
1967                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1968         else {
1969                 vmcs_write16(HOST_GS_SELECTOR, 0);
1970                 vmx->host_state.gs_ldt_reload_needed = 1;
1971         }
1972
1973 #ifdef CONFIG_X86_64
1974         savesegment(ds, vmx->host_state.ds_sel);
1975         savesegment(es, vmx->host_state.es_sel);
1976 #endif
1977
1978 #ifdef CONFIG_X86_64
1979         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1980         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1981 #else
1982         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1983         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1984 #endif
1985
1986 #ifdef CONFIG_X86_64
1987         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1988         if (is_long_mode(&vmx->vcpu))
1989                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1990 #endif
1991         if (boot_cpu_has(X86_FEATURE_MPX))
1992                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1993         for (i = 0; i < vmx->save_nmsrs; ++i)
1994                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1995                                    vmx->guest_msrs[i].data,
1996                                    vmx->guest_msrs[i].mask);
1997 }
1998
1999 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2000 {
2001         if (!vmx->host_state.loaded)
2002                 return;
2003
2004         ++vmx->vcpu.stat.host_state_reload;
2005         vmx->host_state.loaded = 0;
2006 #ifdef CONFIG_X86_64
2007         if (is_long_mode(&vmx->vcpu))
2008                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2009 #endif
2010         if (vmx->host_state.gs_ldt_reload_needed) {
2011                 kvm_load_ldt(vmx->host_state.ldt_sel);
2012 #ifdef CONFIG_X86_64
2013                 load_gs_index(vmx->host_state.gs_sel);
2014 #else
2015                 loadsegment(gs, vmx->host_state.gs_sel);
2016 #endif
2017         }
2018         if (vmx->host_state.fs_reload_needed)
2019                 loadsegment(fs, vmx->host_state.fs_sel);
2020 #ifdef CONFIG_X86_64
2021         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2022                 loadsegment(ds, vmx->host_state.ds_sel);
2023                 loadsegment(es, vmx->host_state.es_sel);
2024         }
2025 #endif
2026         reload_tss();
2027 #ifdef CONFIG_X86_64
2028         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2029 #endif
2030         if (vmx->host_state.msr_host_bndcfgs)
2031                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2032         /*
2033          * If the FPU is not active (through the host task or
2034          * the guest vcpu), then restore the cr0.TS bit.
2035          */
2036         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2037                 stts();
2038         load_gdt(this_cpu_ptr(&host_gdt));
2039 }
2040
2041 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2042 {
2043         preempt_disable();
2044         __vmx_load_host_state(vmx);
2045         preempt_enable();
2046 }
2047
2048 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2049 {
2050         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2051         struct pi_desc old, new;
2052         unsigned int dest;
2053
2054         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2055                 !irq_remapping_cap(IRQ_POSTING_CAP))
2056                 return;
2057
2058         do {
2059                 old.control = new.control = pi_desc->control;
2060
2061                 /*
2062                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2063                  * are two possible cases:
2064                  * 1. After running 'pre_block', context switch
2065                  *    happened. For this case, 'sn' was set in
2066                  *    vmx_vcpu_put(), so we need to clear it here.
2067                  * 2. After running 'pre_block', we were blocked,
2068                  *    and woken up by some other guy. For this case,
2069                  *    we don't need to do anything, 'pi_post_block'
2070                  *    will do everything for us. However, we cannot
2071                  *    check whether it is case #1 or case #2 here
2072                  *    (maybe, not needed), so we also clear sn here,
2073                  *    I think it is not a big deal.
2074                  */
2075                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2076                         if (vcpu->cpu != cpu) {
2077                                 dest = cpu_physical_id(cpu);
2078
2079                                 if (x2apic_enabled())
2080                                         new.ndst = dest;
2081                                 else
2082                                         new.ndst = (dest << 8) & 0xFF00;
2083                         }
2084
2085                         /* set 'NV' to 'notification vector' */
2086                         new.nv = POSTED_INTR_VECTOR;
2087                 }
2088
2089                 /* Allow posting non-urgent interrupts */
2090                 new.sn = 0;
2091         } while (cmpxchg(&pi_desc->control, old.control,
2092                         new.control) != old.control);
2093 }
2094 /*
2095  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2096  * vcpu mutex is already taken.
2097  */
2098 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2099 {
2100         struct vcpu_vmx *vmx = to_vmx(vcpu);
2101         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2102
2103         if (!vmm_exclusive)
2104                 kvm_cpu_vmxon(phys_addr);
2105         else if (vmx->loaded_vmcs->cpu != cpu)
2106                 loaded_vmcs_clear(vmx->loaded_vmcs);
2107
2108         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2109                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2110                 vmcs_load(vmx->loaded_vmcs->vmcs);
2111         }
2112
2113         if (vmx->loaded_vmcs->cpu != cpu) {
2114                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2115                 unsigned long sysenter_esp;
2116
2117                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2118                 local_irq_disable();
2119                 crash_disable_local_vmclear(cpu);
2120
2121                 /*
2122                  * Read loaded_vmcs->cpu should be before fetching
2123                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2124                  * See the comments in __loaded_vmcs_clear().
2125                  */
2126                 smp_rmb();
2127
2128                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2129                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2130                 crash_enable_local_vmclear(cpu);
2131                 local_irq_enable();
2132
2133                 /*
2134                  * Linux uses per-cpu TSS and GDT, so set these when switching
2135                  * processors.
2136                  */
2137                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2138                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2139
2140                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2141                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2142
2143                 vmx->loaded_vmcs->cpu = cpu;
2144         }
2145
2146         /* Setup TSC multiplier */
2147         if (kvm_has_tsc_control &&
2148             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2149                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2150                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2151         }
2152
2153         vmx_vcpu_pi_load(vcpu, cpu);
2154 }
2155
2156 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2157 {
2158         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2159
2160         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2161                 !irq_remapping_cap(IRQ_POSTING_CAP))
2162                 return;
2163
2164         /* Set SN when the vCPU is preempted */
2165         if (vcpu->preempted)
2166                 pi_set_sn(pi_desc);
2167 }
2168
2169 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2170 {
2171         vmx_vcpu_pi_put(vcpu);
2172
2173         __vmx_load_host_state(to_vmx(vcpu));
2174         if (!vmm_exclusive) {
2175                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2176                 vcpu->cpu = -1;
2177                 kvm_cpu_vmxoff();
2178         }
2179 }
2180
2181 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2182 {
2183         ulong cr0;
2184
2185         if (vcpu->fpu_active)
2186                 return;
2187         vcpu->fpu_active = 1;
2188         cr0 = vmcs_readl(GUEST_CR0);
2189         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2190         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2191         vmcs_writel(GUEST_CR0, cr0);
2192         update_exception_bitmap(vcpu);
2193         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2194         if (is_guest_mode(vcpu))
2195                 vcpu->arch.cr0_guest_owned_bits &=
2196                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2197         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2198 }
2199
2200 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2201
2202 /*
2203  * Return the cr0 value that a nested guest would read. This is a combination
2204  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2205  * its hypervisor (cr0_read_shadow).
2206  */
2207 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2208 {
2209         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2210                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2211 }
2212 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2213 {
2214         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2215                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2216 }
2217
2218 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2219 {
2220         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2221          * set this *before* calling this function.
2222          */
2223         vmx_decache_cr0_guest_bits(vcpu);
2224         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2225         update_exception_bitmap(vcpu);
2226         vcpu->arch.cr0_guest_owned_bits = 0;
2227         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2228         if (is_guest_mode(vcpu)) {
2229                 /*
2230                  * L1's specified read shadow might not contain the TS bit,
2231                  * so now that we turned on shadowing of this bit, we need to
2232                  * set this bit of the shadow. Like in nested_vmx_run we need
2233                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2234                  * up-to-date here because we just decached cr0.TS (and we'll
2235                  * only update vmcs12->guest_cr0 on nested exit).
2236                  */
2237                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2238                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2239                         (vcpu->arch.cr0 & X86_CR0_TS);
2240                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2241         } else
2242                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2243 }
2244
2245 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2246 {
2247         unsigned long rflags, save_rflags;
2248
2249         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2250                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2251                 rflags = vmcs_readl(GUEST_RFLAGS);
2252                 if (to_vmx(vcpu)->rmode.vm86_active) {
2253                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2254                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2255                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2256                 }
2257                 to_vmx(vcpu)->rflags = rflags;
2258         }
2259         return to_vmx(vcpu)->rflags;
2260 }
2261
2262 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2263 {
2264         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2265         to_vmx(vcpu)->rflags = rflags;
2266         if (to_vmx(vcpu)->rmode.vm86_active) {
2267                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2268                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2269         }
2270         vmcs_writel(GUEST_RFLAGS, rflags);
2271 }
2272
2273 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2274 {
2275         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2276         int ret = 0;
2277
2278         if (interruptibility & GUEST_INTR_STATE_STI)
2279                 ret |= KVM_X86_SHADOW_INT_STI;
2280         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2281                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2282
2283         return ret;
2284 }
2285
2286 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2287 {
2288         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2289         u32 interruptibility = interruptibility_old;
2290
2291         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2292
2293         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2294                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2295         else if (mask & KVM_X86_SHADOW_INT_STI)
2296                 interruptibility |= GUEST_INTR_STATE_STI;
2297
2298         if ((interruptibility != interruptibility_old))
2299                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2300 }
2301
2302 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2303 {
2304         unsigned long rip;
2305
2306         rip = kvm_rip_read(vcpu);
2307         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2308         kvm_rip_write(vcpu, rip);
2309
2310         /* skipping an emulated instruction also counts */
2311         vmx_set_interrupt_shadow(vcpu, 0);
2312 }
2313
2314 /*
2315  * KVM wants to inject page-faults which it got to the guest. This function
2316  * checks whether in a nested guest, we need to inject them to L1 or L2.
2317  */
2318 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2319 {
2320         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2321
2322         if (!(vmcs12->exception_bitmap & (1u << nr)))
2323                 return 0;
2324
2325         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2326                           vmcs_read32(VM_EXIT_INTR_INFO),
2327                           vmcs_readl(EXIT_QUALIFICATION));
2328         return 1;
2329 }
2330
2331 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2332                                 bool has_error_code, u32 error_code,
2333                                 bool reinject)
2334 {
2335         struct vcpu_vmx *vmx = to_vmx(vcpu);
2336         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2337
2338         if (!reinject && is_guest_mode(vcpu) &&
2339             nested_vmx_check_exception(vcpu, nr))
2340                 return;
2341
2342         if (has_error_code) {
2343                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2344                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2345         }
2346
2347         if (vmx->rmode.vm86_active) {
2348                 int inc_eip = 0;
2349                 if (kvm_exception_is_soft(nr))
2350                         inc_eip = vcpu->arch.event_exit_inst_len;
2351                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2352                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2353                 return;
2354         }
2355
2356         if (kvm_exception_is_soft(nr)) {
2357                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2358                              vmx->vcpu.arch.event_exit_inst_len);
2359                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2360         } else
2361                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2362
2363         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2364 }
2365
2366 static bool vmx_rdtscp_supported(void)
2367 {
2368         return cpu_has_vmx_rdtscp();
2369 }
2370
2371 static bool vmx_invpcid_supported(void)
2372 {
2373         return cpu_has_vmx_invpcid() && enable_ept;
2374 }
2375
2376 /*
2377  * Swap MSR entry in host/guest MSR entry array.
2378  */
2379 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2380 {
2381         struct shared_msr_entry tmp;
2382
2383         tmp = vmx->guest_msrs[to];
2384         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2385         vmx->guest_msrs[from] = tmp;
2386 }
2387
2388 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2389 {
2390         unsigned long *msr_bitmap;
2391
2392         if (is_guest_mode(vcpu))
2393                 msr_bitmap = vmx_msr_bitmap_nested;
2394         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2395                 if (is_long_mode(vcpu))
2396                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2397                 else
2398                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2399         } else {
2400                 if (is_long_mode(vcpu))
2401                         msr_bitmap = vmx_msr_bitmap_longmode;
2402                 else
2403                         msr_bitmap = vmx_msr_bitmap_legacy;
2404         }
2405
2406         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2407 }
2408
2409 /*
2410  * Set up the vmcs to automatically save and restore system
2411  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2412  * mode, as fiddling with msrs is very expensive.
2413  */
2414 static void setup_msrs(struct vcpu_vmx *vmx)
2415 {
2416         int save_nmsrs, index;
2417
2418         save_nmsrs = 0;
2419 #ifdef CONFIG_X86_64
2420         if (is_long_mode(&vmx->vcpu)) {
2421                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2422                 if (index >= 0)
2423                         move_msr_up(vmx, index, save_nmsrs++);
2424                 index = __find_msr_index(vmx, MSR_LSTAR);
2425                 if (index >= 0)
2426                         move_msr_up(vmx, index, save_nmsrs++);
2427                 index = __find_msr_index(vmx, MSR_CSTAR);
2428                 if (index >= 0)
2429                         move_msr_up(vmx, index, save_nmsrs++);
2430                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2431                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2432                         move_msr_up(vmx, index, save_nmsrs++);
2433                 /*
2434                  * MSR_STAR is only needed on long mode guests, and only
2435                  * if efer.sce is enabled.
2436                  */
2437                 index = __find_msr_index(vmx, MSR_STAR);
2438                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2439                         move_msr_up(vmx, index, save_nmsrs++);
2440         }
2441 #endif
2442         index = __find_msr_index(vmx, MSR_EFER);
2443         if (index >= 0 && update_transition_efer(vmx, index))
2444                 move_msr_up(vmx, index, save_nmsrs++);
2445
2446         vmx->save_nmsrs = save_nmsrs;
2447
2448         if (cpu_has_vmx_msr_bitmap())
2449                 vmx_set_msr_bitmap(&vmx->vcpu);
2450 }
2451
2452 /*
2453  * reads and returns guest's timestamp counter "register"
2454  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2455  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2456  */
2457 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2458 {
2459         u64 host_tsc, tsc_offset;
2460
2461         host_tsc = rdtsc();
2462         tsc_offset = vmcs_read64(TSC_OFFSET);
2463         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2464 }
2465
2466 /*
2467  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2468  * counter, even if a nested guest (L2) is currently running.
2469  */
2470 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2471 {
2472         u64 tsc_offset;
2473
2474         tsc_offset = is_guest_mode(vcpu) ?
2475                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2476                 vmcs_read64(TSC_OFFSET);
2477         return host_tsc + tsc_offset;
2478 }
2479
2480 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2481 {
2482         return vmcs_read64(TSC_OFFSET);
2483 }
2484
2485 /*
2486  * writes 'offset' into guest's timestamp counter offset register
2487  */
2488 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2489 {
2490         if (is_guest_mode(vcpu)) {
2491                 /*
2492                  * We're here if L1 chose not to trap WRMSR to TSC. According
2493                  * to the spec, this should set L1's TSC; The offset that L1
2494                  * set for L2 remains unchanged, and still needs to be added
2495                  * to the newly set TSC to get L2's TSC.
2496                  */
2497                 struct vmcs12 *vmcs12;
2498                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2499                 /* recalculate vmcs02.TSC_OFFSET: */
2500                 vmcs12 = get_vmcs12(vcpu);
2501                 vmcs_write64(TSC_OFFSET, offset +
2502                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2503                          vmcs12->tsc_offset : 0));
2504         } else {
2505                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2506                                            vmcs_read64(TSC_OFFSET), offset);
2507                 vmcs_write64(TSC_OFFSET, offset);
2508         }
2509 }
2510
2511 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2512 {
2513         u64 offset = vmcs_read64(TSC_OFFSET);
2514
2515         vmcs_write64(TSC_OFFSET, offset + adjustment);
2516         if (is_guest_mode(vcpu)) {
2517                 /* Even when running L2, the adjustment needs to apply to L1 */
2518                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2519         } else
2520                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2521                                            offset + adjustment);
2522 }
2523
2524 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2525 {
2526         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2527         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2528 }
2529
2530 /*
2531  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2532  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2533  * all guests if the "nested" module option is off, and can also be disabled
2534  * for a single guest by disabling its VMX cpuid bit.
2535  */
2536 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2537 {
2538         return nested && guest_cpuid_has_vmx(vcpu);
2539 }
2540
2541 /*
2542  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2543  * returned for the various VMX controls MSRs when nested VMX is enabled.
2544  * The same values should also be used to verify that vmcs12 control fields are
2545  * valid during nested entry from L1 to L2.
2546  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2547  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2548  * bit in the high half is on if the corresponding bit in the control field
2549  * may be on. See also vmx_control_verify().
2550  */
2551 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2552 {
2553         /*
2554          * Note that as a general rule, the high half of the MSRs (bits in
2555          * the control fields which may be 1) should be initialized by the
2556          * intersection of the underlying hardware's MSR (i.e., features which
2557          * can be supported) and the list of features we want to expose -
2558          * because they are known to be properly supported in our code.
2559          * Also, usually, the low half of the MSRs (bits which must be 1) can
2560          * be set to 0, meaning that L1 may turn off any of these bits. The
2561          * reason is that if one of these bits is necessary, it will appear
2562          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2563          * fields of vmcs01 and vmcs02, will turn these bits off - and
2564          * nested_vmx_exit_handled() will not pass related exits to L1.
2565          * These rules have exceptions below.
2566          */
2567
2568         /* pin-based controls */
2569         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2570                 vmx->nested.nested_vmx_pinbased_ctls_low,
2571                 vmx->nested.nested_vmx_pinbased_ctls_high);
2572         vmx->nested.nested_vmx_pinbased_ctls_low |=
2573                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2574         vmx->nested.nested_vmx_pinbased_ctls_high &=
2575                 PIN_BASED_EXT_INTR_MASK |
2576                 PIN_BASED_NMI_EXITING |
2577                 PIN_BASED_VIRTUAL_NMIS;
2578         vmx->nested.nested_vmx_pinbased_ctls_high |=
2579                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2580                 PIN_BASED_VMX_PREEMPTION_TIMER;
2581         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2582                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2583                         PIN_BASED_POSTED_INTR;
2584
2585         /* exit controls */
2586         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2587                 vmx->nested.nested_vmx_exit_ctls_low,
2588                 vmx->nested.nested_vmx_exit_ctls_high);
2589         vmx->nested.nested_vmx_exit_ctls_low =
2590                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2591
2592         vmx->nested.nested_vmx_exit_ctls_high &=
2593 #ifdef CONFIG_X86_64
2594                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2595 #endif
2596                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2597         vmx->nested.nested_vmx_exit_ctls_high |=
2598                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2599                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2600                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2601
2602         if (vmx_mpx_supported())
2603                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2604
2605         /* We support free control of debug control saving. */
2606         vmx->nested.nested_vmx_true_exit_ctls_low =
2607                 vmx->nested.nested_vmx_exit_ctls_low &
2608                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2609
2610         /* entry controls */
2611         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2612                 vmx->nested.nested_vmx_entry_ctls_low,
2613                 vmx->nested.nested_vmx_entry_ctls_high);
2614         vmx->nested.nested_vmx_entry_ctls_low =
2615                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2616         vmx->nested.nested_vmx_entry_ctls_high &=
2617 #ifdef CONFIG_X86_64
2618                 VM_ENTRY_IA32E_MODE |
2619 #endif
2620                 VM_ENTRY_LOAD_IA32_PAT;
2621         vmx->nested.nested_vmx_entry_ctls_high |=
2622                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2623         if (vmx_mpx_supported())
2624                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2625
2626         /* We support free control of debug control loading. */
2627         vmx->nested.nested_vmx_true_entry_ctls_low =
2628                 vmx->nested.nested_vmx_entry_ctls_low &
2629                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2630
2631         /* cpu-based controls */
2632         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2633                 vmx->nested.nested_vmx_procbased_ctls_low,
2634                 vmx->nested.nested_vmx_procbased_ctls_high);
2635         vmx->nested.nested_vmx_procbased_ctls_low =
2636                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2637         vmx->nested.nested_vmx_procbased_ctls_high &=
2638                 CPU_BASED_VIRTUAL_INTR_PENDING |
2639                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2640                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2641                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2642                 CPU_BASED_CR3_STORE_EXITING |
2643 #ifdef CONFIG_X86_64
2644                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2645 #endif
2646                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2647                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2648                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2649                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2650                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2651         /*
2652          * We can allow some features even when not supported by the
2653          * hardware. For example, L1 can specify an MSR bitmap - and we
2654          * can use it to avoid exits to L1 - even when L0 runs L2
2655          * without MSR bitmaps.
2656          */
2657         vmx->nested.nested_vmx_procbased_ctls_high |=
2658                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2659                 CPU_BASED_USE_MSR_BITMAPS;
2660
2661         /* We support free control of CR3 access interception. */
2662         vmx->nested.nested_vmx_true_procbased_ctls_low =
2663                 vmx->nested.nested_vmx_procbased_ctls_low &
2664                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2665
2666         /* secondary cpu-based controls */
2667         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2668                 vmx->nested.nested_vmx_secondary_ctls_low,
2669                 vmx->nested.nested_vmx_secondary_ctls_high);
2670         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2671         vmx->nested.nested_vmx_secondary_ctls_high &=
2672                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2673                 SECONDARY_EXEC_RDTSCP |
2674                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2675                 SECONDARY_EXEC_ENABLE_VPID |
2676                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2677                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2678                 SECONDARY_EXEC_WBINVD_EXITING |
2679                 SECONDARY_EXEC_XSAVES |
2680                 SECONDARY_EXEC_PCOMMIT;
2681
2682         if (enable_ept) {
2683                 /* nested EPT: emulate EPT also to L1 */
2684                 vmx->nested.nested_vmx_secondary_ctls_high |=
2685                         SECONDARY_EXEC_ENABLE_EPT;
2686                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2687                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2688                          VMX_EPT_INVEPT_BIT;
2689                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2690                 /*
2691                  * For nested guests, we don't do anything specific
2692                  * for single context invalidation. Hence, only advertise
2693                  * support for global context invalidation.
2694                  */
2695                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2696         } else
2697                 vmx->nested.nested_vmx_ept_caps = 0;
2698
2699         if (enable_vpid)
2700                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2701                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2702         else
2703                 vmx->nested.nested_vmx_vpid_caps = 0;
2704
2705         if (enable_unrestricted_guest)
2706                 vmx->nested.nested_vmx_secondary_ctls_high |=
2707                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2708
2709         /* miscellaneous data */
2710         rdmsr(MSR_IA32_VMX_MISC,
2711                 vmx->nested.nested_vmx_misc_low,
2712                 vmx->nested.nested_vmx_misc_high);
2713         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2714         vmx->nested.nested_vmx_misc_low |=
2715                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2716                 VMX_MISC_ACTIVITY_HLT;
2717         vmx->nested.nested_vmx_misc_high = 0;
2718 }
2719
2720 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2721 {
2722         /*
2723          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2724          */
2725         return ((control & high) | low) == control;
2726 }
2727
2728 static inline u64 vmx_control_msr(u32 low, u32 high)
2729 {
2730         return low | ((u64)high << 32);
2731 }
2732
2733 /* Returns 0 on success, non-0 otherwise. */
2734 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2735 {
2736         struct vcpu_vmx *vmx = to_vmx(vcpu);
2737
2738         switch (msr_index) {
2739         case MSR_IA32_VMX_BASIC:
2740                 /*
2741                  * This MSR reports some information about VMX support. We
2742                  * should return information about the VMX we emulate for the
2743                  * guest, and the VMCS structure we give it - not about the
2744                  * VMX support of the underlying hardware.
2745                  */
2746                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2747                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2748                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2749                 break;
2750         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2751         case MSR_IA32_VMX_PINBASED_CTLS:
2752                 *pdata = vmx_control_msr(
2753                         vmx->nested.nested_vmx_pinbased_ctls_low,
2754                         vmx->nested.nested_vmx_pinbased_ctls_high);
2755                 break;
2756         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2757                 *pdata = vmx_control_msr(
2758                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2759                         vmx->nested.nested_vmx_procbased_ctls_high);
2760                 break;
2761         case MSR_IA32_VMX_PROCBASED_CTLS:
2762                 *pdata = vmx_control_msr(
2763                         vmx->nested.nested_vmx_procbased_ctls_low,
2764                         vmx->nested.nested_vmx_procbased_ctls_high);
2765                 break;
2766         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2767                 *pdata = vmx_control_msr(
2768                         vmx->nested.nested_vmx_true_exit_ctls_low,
2769                         vmx->nested.nested_vmx_exit_ctls_high);
2770                 break;
2771         case MSR_IA32_VMX_EXIT_CTLS:
2772                 *pdata = vmx_control_msr(
2773                         vmx->nested.nested_vmx_exit_ctls_low,
2774                         vmx->nested.nested_vmx_exit_ctls_high);
2775                 break;
2776         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2777                 *pdata = vmx_control_msr(
2778                         vmx->nested.nested_vmx_true_entry_ctls_low,
2779                         vmx->nested.nested_vmx_entry_ctls_high);
2780                 break;
2781         case MSR_IA32_VMX_ENTRY_CTLS:
2782                 *pdata = vmx_control_msr(
2783                         vmx->nested.nested_vmx_entry_ctls_low,
2784                         vmx->nested.nested_vmx_entry_ctls_high);
2785                 break;
2786         case MSR_IA32_VMX_MISC:
2787                 *pdata = vmx_control_msr(
2788                         vmx->nested.nested_vmx_misc_low,
2789                         vmx->nested.nested_vmx_misc_high);
2790                 break;
2791         /*
2792          * These MSRs specify bits which the guest must keep fixed (on or off)
2793          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2794          * We picked the standard core2 setting.
2795          */
2796 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2797 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2798         case MSR_IA32_VMX_CR0_FIXED0:
2799                 *pdata = VMXON_CR0_ALWAYSON;
2800                 break;
2801         case MSR_IA32_VMX_CR0_FIXED1:
2802                 *pdata = -1ULL;
2803                 break;
2804         case MSR_IA32_VMX_CR4_FIXED0:
2805                 *pdata = VMXON_CR4_ALWAYSON;
2806                 break;
2807         case MSR_IA32_VMX_CR4_FIXED1:
2808                 *pdata = -1ULL;
2809                 break;
2810         case MSR_IA32_VMX_VMCS_ENUM:
2811                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2812                 break;
2813         case MSR_IA32_VMX_PROCBASED_CTLS2:
2814                 *pdata = vmx_control_msr(
2815                         vmx->nested.nested_vmx_secondary_ctls_low,
2816                         vmx->nested.nested_vmx_secondary_ctls_high);
2817                 break;
2818         case MSR_IA32_VMX_EPT_VPID_CAP:
2819                 /* Currently, no nested vpid support */
2820                 *pdata = vmx->nested.nested_vmx_ept_caps |
2821                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2822                 break;
2823         default:
2824                 return 1;
2825         }
2826
2827         return 0;
2828 }
2829
2830 /*
2831  * Reads an msr value (of 'msr_index') into 'pdata'.
2832  * Returns 0 on success, non-0 otherwise.
2833  * Assumes vcpu_load() was already called.
2834  */
2835 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2836 {
2837         struct shared_msr_entry *msr;
2838
2839         switch (msr_info->index) {
2840 #ifdef CONFIG_X86_64
2841         case MSR_FS_BASE:
2842                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2843                 break;
2844         case MSR_GS_BASE:
2845                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2846                 break;
2847         case MSR_KERNEL_GS_BASE:
2848                 vmx_load_host_state(to_vmx(vcpu));
2849                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2850                 break;
2851 #endif
2852         case MSR_EFER:
2853                 return kvm_get_msr_common(vcpu, msr_info);
2854         case MSR_IA32_TSC:
2855                 msr_info->data = guest_read_tsc(vcpu);
2856                 break;
2857         case MSR_IA32_SYSENTER_CS:
2858                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2859                 break;
2860         case MSR_IA32_SYSENTER_EIP:
2861                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2862                 break;
2863         case MSR_IA32_SYSENTER_ESP:
2864                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2865                 break;
2866         case MSR_IA32_BNDCFGS:
2867                 if (!vmx_mpx_supported())
2868                         return 1;
2869                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2870                 break;
2871         case MSR_IA32_FEATURE_CONTROL:
2872                 if (!nested_vmx_allowed(vcpu))
2873                         return 1;
2874                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2875                 break;
2876         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2877                 if (!nested_vmx_allowed(vcpu))
2878                         return 1;
2879                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2880         case MSR_IA32_XSS:
2881                 if (!vmx_xsaves_supported())
2882                         return 1;
2883                 msr_info->data = vcpu->arch.ia32_xss;
2884                 break;
2885         case MSR_TSC_AUX:
2886                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2887                         return 1;
2888                 /* Otherwise falls through */
2889         default:
2890                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2891                 if (msr) {
2892                         msr_info->data = msr->data;
2893                         break;
2894                 }
2895                 return kvm_get_msr_common(vcpu, msr_info);
2896         }
2897
2898         return 0;
2899 }
2900
2901 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2902
2903 /*
2904  * Writes msr value into into the appropriate "register".
2905  * Returns 0 on success, non-0 otherwise.
2906  * Assumes vcpu_load() was already called.
2907  */
2908 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2909 {
2910         struct vcpu_vmx *vmx = to_vmx(vcpu);
2911         struct shared_msr_entry *msr;
2912         int ret = 0;
2913         u32 msr_index = msr_info->index;
2914         u64 data = msr_info->data;
2915
2916         switch (msr_index) {
2917         case MSR_EFER:
2918                 ret = kvm_set_msr_common(vcpu, msr_info);
2919                 break;
2920 #ifdef CONFIG_X86_64
2921         case MSR_FS_BASE:
2922                 vmx_segment_cache_clear(vmx);
2923                 vmcs_writel(GUEST_FS_BASE, data);
2924                 break;
2925         case MSR_GS_BASE:
2926                 vmx_segment_cache_clear(vmx);
2927                 vmcs_writel(GUEST_GS_BASE, data);
2928                 break;
2929         case MSR_KERNEL_GS_BASE:
2930                 vmx_load_host_state(vmx);
2931                 vmx->msr_guest_kernel_gs_base = data;
2932                 break;
2933 #endif
2934         case MSR_IA32_SYSENTER_CS:
2935                 vmcs_write32(GUEST_SYSENTER_CS, data);
2936                 break;
2937         case MSR_IA32_SYSENTER_EIP:
2938                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2939                 break;
2940         case MSR_IA32_SYSENTER_ESP:
2941                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2942                 break;
2943         case MSR_IA32_BNDCFGS:
2944                 if (!vmx_mpx_supported())
2945                         return 1;
2946                 vmcs_write64(GUEST_BNDCFGS, data);
2947                 break;
2948         case MSR_IA32_TSC:
2949                 kvm_write_tsc(vcpu, msr_info);
2950                 break;
2951         case MSR_IA32_CR_PAT:
2952                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2953                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2954                                 return 1;
2955                         vmcs_write64(GUEST_IA32_PAT, data);
2956                         vcpu->arch.pat = data;
2957                         break;
2958                 }
2959                 ret = kvm_set_msr_common(vcpu, msr_info);
2960                 break;
2961         case MSR_IA32_TSC_ADJUST:
2962                 ret = kvm_set_msr_common(vcpu, msr_info);
2963                 break;
2964         case MSR_IA32_FEATURE_CONTROL:
2965                 if (!nested_vmx_allowed(vcpu) ||
2966                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2967                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2968                         return 1;
2969                 vmx->nested.msr_ia32_feature_control = data;
2970                 if (msr_info->host_initiated && data == 0)
2971                         vmx_leave_nested(vcpu);
2972                 break;
2973         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2974                 return 1; /* they are read-only */
2975         case MSR_IA32_XSS:
2976                 if (!vmx_xsaves_supported())
2977                         return 1;
2978                 /*
2979                  * The only supported bit as of Skylake is bit 8, but
2980                  * it is not supported on KVM.
2981                  */
2982                 if (data != 0)
2983                         return 1;
2984                 vcpu->arch.ia32_xss = data;
2985                 if (vcpu->arch.ia32_xss != host_xss)
2986                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2987                                 vcpu->arch.ia32_xss, host_xss);
2988                 else
2989                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2990                 break;
2991         case MSR_TSC_AUX:
2992                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2993                         return 1;
2994                 /* Check reserved bit, higher 32 bits should be zero */
2995                 if ((data >> 32) != 0)
2996                         return 1;
2997                 /* Otherwise falls through */
2998         default:
2999                 msr = find_msr_entry(vmx, msr_index);
3000                 if (msr) {
3001                         u64 old_msr_data = msr->data;
3002                         msr->data = data;
3003                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3004                                 preempt_disable();
3005                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3006                                                          msr->mask);
3007                                 preempt_enable();
3008                                 if (ret)
3009                                         msr->data = old_msr_data;
3010                         }
3011                         break;
3012                 }
3013                 ret = kvm_set_msr_common(vcpu, msr_info);
3014         }
3015
3016         return ret;
3017 }
3018
3019 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3020 {
3021         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3022         switch (reg) {
3023         case VCPU_REGS_RSP:
3024                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3025                 break;
3026         case VCPU_REGS_RIP:
3027                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3028                 break;
3029         case VCPU_EXREG_PDPTR:
3030                 if (enable_ept)
3031                         ept_save_pdptrs(vcpu);
3032                 break;
3033         default:
3034                 break;
3035         }
3036 }
3037
3038 static __init int cpu_has_kvm_support(void)
3039 {
3040         return cpu_has_vmx();
3041 }
3042
3043 static __init int vmx_disabled_by_bios(void)
3044 {
3045         u64 msr;
3046
3047         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3048         if (msr & FEATURE_CONTROL_LOCKED) {
3049                 /* launched w/ TXT and VMX disabled */
3050                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3051                         && tboot_enabled())
3052                         return 1;
3053                 /* launched w/o TXT and VMX only enabled w/ TXT */
3054                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3055                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3056                         && !tboot_enabled()) {
3057                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3058                                 "activate TXT before enabling KVM\n");
3059                         return 1;
3060                 }
3061                 /* launched w/o TXT and VMX disabled */
3062                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3063                         && !tboot_enabled())
3064                         return 1;
3065         }
3066
3067         return 0;
3068 }
3069
3070 static void kvm_cpu_vmxon(u64 addr)
3071 {
3072         asm volatile (ASM_VMX_VMXON_RAX
3073                         : : "a"(&addr), "m"(addr)
3074                         : "memory", "cc");
3075 }
3076
3077 static int hardware_enable(void)
3078 {
3079         int cpu = raw_smp_processor_id();
3080         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3081         u64 old, test_bits;
3082
3083         if (cr4_read_shadow() & X86_CR4_VMXE)
3084                 return -EBUSY;
3085
3086         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3087         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3088         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3089
3090         /*
3091          * Now we can enable the vmclear operation in kdump
3092          * since the loaded_vmcss_on_cpu list on this cpu
3093          * has been initialized.
3094          *
3095          * Though the cpu is not in VMX operation now, there
3096          * is no problem to enable the vmclear operation
3097          * for the loaded_vmcss_on_cpu list is empty!
3098          */
3099         crash_enable_local_vmclear(cpu);
3100
3101         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3102
3103         test_bits = FEATURE_CONTROL_LOCKED;
3104         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3105         if (tboot_enabled())
3106                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3107
3108         if ((old & test_bits) != test_bits) {
3109                 /* enable and lock */
3110                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3111         }
3112         cr4_set_bits(X86_CR4_VMXE);
3113
3114         if (vmm_exclusive) {
3115                 kvm_cpu_vmxon(phys_addr);
3116                 ept_sync_global();
3117         }
3118
3119         native_store_gdt(this_cpu_ptr(&host_gdt));
3120
3121         return 0;
3122 }
3123
3124 static void vmclear_local_loaded_vmcss(void)
3125 {
3126         int cpu = raw_smp_processor_id();
3127         struct loaded_vmcs *v, *n;
3128
3129         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3130                                  loaded_vmcss_on_cpu_link)
3131                 __loaded_vmcs_clear(v);
3132 }
3133
3134
3135 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3136  * tricks.
3137  */
3138 static void kvm_cpu_vmxoff(void)
3139 {
3140         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3141 }
3142
3143 static void hardware_disable(void)
3144 {
3145         if (vmm_exclusive) {
3146                 vmclear_local_loaded_vmcss();
3147                 kvm_cpu_vmxoff();
3148         }
3149         cr4_clear_bits(X86_CR4_VMXE);
3150 }
3151
3152 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3153                                       u32 msr, u32 *result)
3154 {
3155         u32 vmx_msr_low, vmx_msr_high;
3156         u32 ctl = ctl_min | ctl_opt;
3157
3158         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3159
3160         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3161         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3162
3163         /* Ensure minimum (required) set of control bits are supported. */
3164         if (ctl_min & ~ctl)
3165                 return -EIO;
3166
3167         *result = ctl;
3168         return 0;
3169 }
3170
3171 static __init bool allow_1_setting(u32 msr, u32 ctl)
3172 {
3173         u32 vmx_msr_low, vmx_msr_high;
3174
3175         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3176         return vmx_msr_high & ctl;
3177 }
3178
3179 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3180 {
3181         u32 vmx_msr_low, vmx_msr_high;
3182         u32 min, opt, min2, opt2;
3183         u32 _pin_based_exec_control = 0;
3184         u32 _cpu_based_exec_control = 0;
3185         u32 _cpu_based_2nd_exec_control = 0;
3186         u32 _vmexit_control = 0;
3187         u32 _vmentry_control = 0;
3188
3189         min = CPU_BASED_HLT_EXITING |
3190 #ifdef CONFIG_X86_64
3191               CPU_BASED_CR8_LOAD_EXITING |
3192               CPU_BASED_CR8_STORE_EXITING |
3193 #endif
3194               CPU_BASED_CR3_LOAD_EXITING |
3195               CPU_BASED_CR3_STORE_EXITING |
3196               CPU_BASED_USE_IO_BITMAPS |
3197               CPU_BASED_MOV_DR_EXITING |
3198               CPU_BASED_USE_TSC_OFFSETING |
3199               CPU_BASED_MWAIT_EXITING |
3200               CPU_BASED_MONITOR_EXITING |
3201               CPU_BASED_INVLPG_EXITING |
3202               CPU_BASED_RDPMC_EXITING;
3203
3204         opt = CPU_BASED_TPR_SHADOW |
3205               CPU_BASED_USE_MSR_BITMAPS |
3206               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3207         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3208                                 &_cpu_based_exec_control) < 0)
3209                 return -EIO;
3210 #ifdef CONFIG_X86_64
3211         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3212                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3213                                            ~CPU_BASED_CR8_STORE_EXITING;
3214 #endif
3215         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3216                 min2 = 0;
3217                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3218                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3219                         SECONDARY_EXEC_WBINVD_EXITING |
3220                         SECONDARY_EXEC_ENABLE_VPID |
3221                         SECONDARY_EXEC_ENABLE_EPT |
3222                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3223                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3224                         SECONDARY_EXEC_RDTSCP |
3225                         SECONDARY_EXEC_ENABLE_INVPCID |
3226                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3227                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3228                         SECONDARY_EXEC_SHADOW_VMCS |
3229                         SECONDARY_EXEC_XSAVES |
3230                         SECONDARY_EXEC_ENABLE_PML |
3231                         SECONDARY_EXEC_PCOMMIT |
3232                         SECONDARY_EXEC_TSC_SCALING;
3233                 if (adjust_vmx_controls(min2, opt2,
3234                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3235                                         &_cpu_based_2nd_exec_control) < 0)
3236                         return -EIO;
3237         }
3238 #ifndef CONFIG_X86_64
3239         if (!(_cpu_based_2nd_exec_control &
3240                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3241                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3242 #endif
3243
3244         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3245                 _cpu_based_2nd_exec_control &= ~(
3246                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3247                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3248                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3249
3250         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3251                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3252                    enabled */
3253                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3254                                              CPU_BASED_CR3_STORE_EXITING |
3255                                              CPU_BASED_INVLPG_EXITING);
3256                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3257                       vmx_capability.ept, vmx_capability.vpid);
3258         }
3259
3260         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3261 #ifdef CONFIG_X86_64
3262         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3263 #endif
3264         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3265                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3266         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3267                                 &_vmexit_control) < 0)
3268                 return -EIO;
3269
3270         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3271         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3272         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3273                                 &_pin_based_exec_control) < 0)
3274                 return -EIO;
3275
3276         if (!(_cpu_based_2nd_exec_control &
3277                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3278                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3279                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3280
3281         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3282         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3283         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3284                                 &_vmentry_control) < 0)
3285                 return -EIO;
3286
3287         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3288
3289         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3290         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3291                 return -EIO;
3292
3293 #ifdef CONFIG_X86_64
3294         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3295         if (vmx_msr_high & (1u<<16))
3296                 return -EIO;
3297 #endif
3298
3299         /* Require Write-Back (WB) memory type for VMCS accesses. */
3300         if (((vmx_msr_high >> 18) & 15) != 6)
3301                 return -EIO;
3302
3303         vmcs_conf->size = vmx_msr_high & 0x1fff;
3304         vmcs_conf->order = get_order(vmcs_config.size);
3305         vmcs_conf->revision_id = vmx_msr_low;
3306
3307         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3308         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3309         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3310         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3311         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3312
3313         cpu_has_load_ia32_efer =
3314                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3315                                 VM_ENTRY_LOAD_IA32_EFER)
3316                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3317                                    VM_EXIT_LOAD_IA32_EFER);
3318
3319         cpu_has_load_perf_global_ctrl =
3320                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3321                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3322                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3323                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3324
3325         /*
3326          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3327          * but due to arrata below it can't be used. Workaround is to use
3328          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3329          *
3330          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3331          *
3332          * AAK155             (model 26)
3333          * AAP115             (model 30)
3334          * AAT100             (model 37)
3335          * BC86,AAY89,BD102   (model 44)
3336          * BA97               (model 46)
3337          *
3338          */
3339         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3340                 switch (boot_cpu_data.x86_model) {
3341                 case 26:
3342                 case 30:
3343                 case 37:
3344                 case 44:
3345                 case 46:
3346                         cpu_has_load_perf_global_ctrl = false;
3347                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3348                                         "does not work properly. Using workaround\n");
3349                         break;
3350                 default:
3351                         break;
3352                 }
3353         }
3354
3355         if (cpu_has_xsaves)
3356                 rdmsrl(MSR_IA32_XSS, host_xss);
3357
3358         return 0;
3359 }
3360
3361 static struct vmcs *alloc_vmcs_cpu(int cpu)
3362 {
3363         int node = cpu_to_node(cpu);
3364         struct page *pages;
3365         struct vmcs *vmcs;
3366
3367         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3368         if (!pages)
3369                 return NULL;
3370         vmcs = page_address(pages);
3371         memset(vmcs, 0, vmcs_config.size);
3372         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3373         return vmcs;
3374 }
3375
3376 static struct vmcs *alloc_vmcs(void)
3377 {
3378         return alloc_vmcs_cpu(raw_smp_processor_id());
3379 }
3380
3381 static void free_vmcs(struct vmcs *vmcs)
3382 {
3383         free_pages((unsigned long)vmcs, vmcs_config.order);
3384 }
3385
3386 /*
3387  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3388  */
3389 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3390 {
3391         if (!loaded_vmcs->vmcs)
3392                 return;
3393         loaded_vmcs_clear(loaded_vmcs);
3394         free_vmcs(loaded_vmcs->vmcs);
3395         loaded_vmcs->vmcs = NULL;
3396 }
3397
3398 static void free_kvm_area(void)
3399 {
3400         int cpu;
3401
3402         for_each_possible_cpu(cpu) {
3403                 free_vmcs(per_cpu(vmxarea, cpu));
3404                 per_cpu(vmxarea, cpu) = NULL;
3405         }
3406 }
3407
3408 static void init_vmcs_shadow_fields(void)
3409 {
3410         int i, j;
3411
3412         /* No checks for read only fields yet */
3413
3414         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3415                 switch (shadow_read_write_fields[i]) {
3416                 case GUEST_BNDCFGS:
3417                         if (!vmx_mpx_supported())
3418                                 continue;
3419                         break;
3420                 default:
3421                         break;
3422                 }
3423
3424                 if (j < i)
3425                         shadow_read_write_fields[j] =
3426                                 shadow_read_write_fields[i];
3427                 j++;
3428         }
3429         max_shadow_read_write_fields = j;
3430
3431         /* shadowed fields guest access without vmexit */
3432         for (i = 0; i < max_shadow_read_write_fields; i++) {
3433                 clear_bit(shadow_read_write_fields[i],
3434                           vmx_vmwrite_bitmap);
3435                 clear_bit(shadow_read_write_fields[i],
3436                           vmx_vmread_bitmap);
3437         }
3438         for (i = 0; i < max_shadow_read_only_fields; i++)
3439                 clear_bit(shadow_read_only_fields[i],
3440                           vmx_vmread_bitmap);
3441 }
3442
3443 static __init int alloc_kvm_area(void)
3444 {
3445         int cpu;
3446
3447         for_each_possible_cpu(cpu) {
3448                 struct vmcs *vmcs;
3449
3450                 vmcs = alloc_vmcs_cpu(cpu);
3451                 if (!vmcs) {
3452                         free_kvm_area();
3453                         return -ENOMEM;
3454                 }
3455
3456                 per_cpu(vmxarea, cpu) = vmcs;
3457         }
3458         return 0;
3459 }
3460
3461 static bool emulation_required(struct kvm_vcpu *vcpu)
3462 {
3463         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3464 }
3465
3466 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3467                 struct kvm_segment *save)
3468 {
3469         if (!emulate_invalid_guest_state) {
3470                 /*
3471                  * CS and SS RPL should be equal during guest entry according
3472                  * to VMX spec, but in reality it is not always so. Since vcpu
3473                  * is in the middle of the transition from real mode to
3474                  * protected mode it is safe to assume that RPL 0 is a good
3475                  * default value.
3476                  */
3477                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3478                         save->selector &= ~SEGMENT_RPL_MASK;
3479                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3480                 save->s = 1;
3481         }
3482         vmx_set_segment(vcpu, save, seg);
3483 }
3484
3485 static void enter_pmode(struct kvm_vcpu *vcpu)
3486 {
3487         unsigned long flags;
3488         struct vcpu_vmx *vmx = to_vmx(vcpu);
3489
3490         /*
3491          * Update real mode segment cache. It may be not up-to-date if sement
3492          * register was written while vcpu was in a guest mode.
3493          */
3494         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3495         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3496         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3497         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3498         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3499         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3500
3501         vmx->rmode.vm86_active = 0;
3502
3503         vmx_segment_cache_clear(vmx);
3504
3505         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3506
3507         flags = vmcs_readl(GUEST_RFLAGS);
3508         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3509         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3510         vmcs_writel(GUEST_RFLAGS, flags);
3511
3512         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3513                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3514
3515         update_exception_bitmap(vcpu);
3516
3517         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3518         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3519         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3520         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3521         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3522         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3523 }
3524
3525 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3526 {
3527         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3528         struct kvm_segment var = *save;
3529
3530         var.dpl = 0x3;
3531         if (seg == VCPU_SREG_CS)
3532                 var.type = 0x3;
3533
3534         if (!emulate_invalid_guest_state) {
3535                 var.selector = var.base >> 4;
3536                 var.base = var.base & 0xffff0;
3537                 var.limit = 0xffff;
3538                 var.g = 0;
3539                 var.db = 0;
3540                 var.present = 1;
3541                 var.s = 1;
3542                 var.l = 0;
3543                 var.unusable = 0;
3544                 var.type = 0x3;
3545                 var.avl = 0;
3546                 if (save->base & 0xf)
3547                         printk_once(KERN_WARNING "kvm: segment base is not "
3548                                         "paragraph aligned when entering "
3549                                         "protected mode (seg=%d)", seg);
3550         }
3551
3552         vmcs_write16(sf->selector, var.selector);
3553         vmcs_write32(sf->base, var.base);
3554         vmcs_write32(sf->limit, var.limit);
3555         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3556 }
3557
3558 static void enter_rmode(struct kvm_vcpu *vcpu)
3559 {
3560         unsigned long flags;
3561         struct vcpu_vmx *vmx = to_vmx(vcpu);
3562
3563         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3564         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3565         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3566         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3567         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3568         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3569         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3570
3571         vmx->rmode.vm86_active = 1;
3572
3573         /*
3574          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3575          * vcpu. Warn the user that an update is overdue.
3576          */
3577         if (!vcpu->kvm->arch.tss_addr)
3578                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3579                              "called before entering vcpu\n");
3580
3581         vmx_segment_cache_clear(vmx);
3582
3583         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3584         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3585         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3586
3587         flags = vmcs_readl(GUEST_RFLAGS);
3588         vmx->rmode.save_rflags = flags;
3589
3590         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3591
3592         vmcs_writel(GUEST_RFLAGS, flags);
3593         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3594         update_exception_bitmap(vcpu);
3595
3596         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3597         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3598         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3599         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3600         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3601         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3602
3603         kvm_mmu_reset_context(vcpu);
3604 }
3605
3606 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3607 {
3608         struct vcpu_vmx *vmx = to_vmx(vcpu);
3609         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3610
3611         if (!msr)
3612                 return;
3613
3614         /*
3615          * Force kernel_gs_base reloading before EFER changes, as control
3616          * of this msr depends on is_long_mode().
3617          */
3618         vmx_load_host_state(to_vmx(vcpu));
3619         vcpu->arch.efer = efer;
3620         if (efer & EFER_LMA) {
3621                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3622                 msr->data = efer;
3623         } else {
3624                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3625
3626                 msr->data = efer & ~EFER_LME;
3627         }
3628         setup_msrs(vmx);
3629 }
3630
3631 #ifdef CONFIG_X86_64
3632
3633 static void enter_lmode(struct kvm_vcpu *vcpu)
3634 {
3635         u32 guest_tr_ar;
3636
3637         vmx_segment_cache_clear(to_vmx(vcpu));
3638
3639         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3640         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3641                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3642                                      __func__);
3643                 vmcs_write32(GUEST_TR_AR_BYTES,
3644                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3645                              | VMX_AR_TYPE_BUSY_64_TSS);
3646         }
3647         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3648 }
3649
3650 static void exit_lmode(struct kvm_vcpu *vcpu)
3651 {
3652         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3653         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3654 }
3655
3656 #endif
3657
3658 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3659 {
3660         vpid_sync_context(vpid);
3661         if (enable_ept) {
3662                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3663                         return;
3664                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3665         }
3666 }
3667
3668 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3669 {
3670         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3671 }
3672
3673 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3674 {
3675         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3676
3677         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3678         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3679 }
3680
3681 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3682 {
3683         if (enable_ept && is_paging(vcpu))
3684                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3685         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3686 }
3687
3688 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3689 {
3690         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3691
3692         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3693         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3694 }
3695
3696 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3697 {
3698         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3699
3700         if (!test_bit(VCPU_EXREG_PDPTR,
3701                       (unsigned long *)&vcpu->arch.regs_dirty))
3702                 return;
3703
3704         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3705                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3706                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3707                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3708                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3709         }
3710 }
3711
3712 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3713 {
3714         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3715
3716         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3717                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3718                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3719                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3720                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3721         }
3722
3723         __set_bit(VCPU_EXREG_PDPTR,
3724                   (unsigned long *)&vcpu->arch.regs_avail);
3725         __set_bit(VCPU_EXREG_PDPTR,
3726                   (unsigned long *)&vcpu->arch.regs_dirty);
3727 }
3728
3729 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3730
3731 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3732                                         unsigned long cr0,
3733                                         struct kvm_vcpu *vcpu)
3734 {
3735         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3736                 vmx_decache_cr3(vcpu);
3737         if (!(cr0 & X86_CR0_PG)) {
3738                 /* From paging/starting to nonpaging */
3739                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3740                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3741                              (CPU_BASED_CR3_LOAD_EXITING |
3742                               CPU_BASED_CR3_STORE_EXITING));
3743                 vcpu->arch.cr0 = cr0;
3744                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3745         } else if (!is_paging(vcpu)) {
3746                 /* From nonpaging to paging */
3747                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3748                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3749                              ~(CPU_BASED_CR3_LOAD_EXITING |
3750                                CPU_BASED_CR3_STORE_EXITING));
3751                 vcpu->arch.cr0 = cr0;
3752                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3753         }
3754
3755         if (!(cr0 & X86_CR0_WP))
3756                 *hw_cr0 &= ~X86_CR0_WP;
3757 }
3758
3759 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3760 {
3761         struct vcpu_vmx *vmx = to_vmx(vcpu);
3762         unsigned long hw_cr0;
3763
3764         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3765         if (enable_unrestricted_guest)
3766                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3767         else {
3768                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3769
3770                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3771                         enter_pmode(vcpu);
3772
3773                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3774                         enter_rmode(vcpu);
3775         }
3776
3777 #ifdef CONFIG_X86_64
3778         if (vcpu->arch.efer & EFER_LME) {
3779                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3780                         enter_lmode(vcpu);
3781                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3782                         exit_lmode(vcpu);
3783         }
3784 #endif
3785
3786         if (enable_ept)
3787                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3788
3789         if (!vcpu->fpu_active)
3790                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3791
3792         vmcs_writel(CR0_READ_SHADOW, cr0);
3793         vmcs_writel(GUEST_CR0, hw_cr0);
3794         vcpu->arch.cr0 = cr0;
3795
3796         /* depends on vcpu->arch.cr0 to be set to a new value */
3797         vmx->emulation_required = emulation_required(vcpu);
3798 }
3799
3800 static u64 construct_eptp(unsigned long root_hpa)
3801 {
3802         u64 eptp;
3803
3804         /* TODO write the value reading from MSR */
3805         eptp = VMX_EPT_DEFAULT_MT |
3806                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3807         if (enable_ept_ad_bits)
3808                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3809         eptp |= (root_hpa & PAGE_MASK);
3810
3811         return eptp;
3812 }
3813
3814 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3815 {
3816         unsigned long guest_cr3;
3817         u64 eptp;
3818
3819         guest_cr3 = cr3;
3820         if (enable_ept) {
3821                 eptp = construct_eptp(cr3);
3822                 vmcs_write64(EPT_POINTER, eptp);
3823                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3824                         guest_cr3 = kvm_read_cr3(vcpu);
3825                 else
3826                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3827                 ept_load_pdptrs(vcpu);
3828         }
3829
3830         vmx_flush_tlb(vcpu);
3831         vmcs_writel(GUEST_CR3, guest_cr3);
3832 }
3833
3834 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3835 {
3836         /*
3837          * Pass through host's Machine Check Enable value to hw_cr4, which
3838          * is in force while we are in guest mode.  Do not let guests control
3839          * this bit, even if host CR4.MCE == 0.
3840          */
3841         unsigned long hw_cr4 =
3842                 (cr4_read_shadow() & X86_CR4_MCE) |
3843                 (cr4 & ~X86_CR4_MCE) |
3844                 (to_vmx(vcpu)->rmode.vm86_active ?
3845                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3846
3847         if (cr4 & X86_CR4_VMXE) {
3848                 /*
3849                  * To use VMXON (and later other VMX instructions), a guest
3850                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3851                  * So basically the check on whether to allow nested VMX
3852                  * is here.
3853                  */
3854                 if (!nested_vmx_allowed(vcpu))
3855                         return 1;
3856         }
3857         if (to_vmx(vcpu)->nested.vmxon &&
3858             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3859                 return 1;
3860
3861         vcpu->arch.cr4 = cr4;
3862         if (enable_ept) {
3863                 if (!is_paging(vcpu)) {
3864                         hw_cr4 &= ~X86_CR4_PAE;
3865                         hw_cr4 |= X86_CR4_PSE;
3866                 } else if (!(cr4 & X86_CR4_PAE)) {
3867                         hw_cr4 &= ~X86_CR4_PAE;
3868                 }
3869         }
3870
3871         if (!enable_unrestricted_guest && !is_paging(vcpu))
3872                 /*
3873                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3874                  * hardware.  However KVM always uses paging mode without
3875                  * unrestricted guest.
3876                  * To emulate this behavior, SMEP/SMAP needs to be manually
3877                  * disabled when guest switches to non-paging mode.
3878                  */
3879                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3880
3881         vmcs_writel(CR4_READ_SHADOW, cr4);
3882         vmcs_writel(GUEST_CR4, hw_cr4);
3883         return 0;
3884 }
3885
3886 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3887                             struct kvm_segment *var, int seg)
3888 {
3889         struct vcpu_vmx *vmx = to_vmx(vcpu);
3890         u32 ar;
3891
3892         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3893                 *var = vmx->rmode.segs[seg];
3894                 if (seg == VCPU_SREG_TR
3895                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3896                         return;
3897                 var->base = vmx_read_guest_seg_base(vmx, seg);
3898                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3899                 return;
3900         }
3901         var->base = vmx_read_guest_seg_base(vmx, seg);
3902         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3903         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3904         ar = vmx_read_guest_seg_ar(vmx, seg);
3905         var->unusable = (ar >> 16) & 1;
3906         var->type = ar & 15;
3907         var->s = (ar >> 4) & 1;
3908         var->dpl = (ar >> 5) & 3;
3909         /*
3910          * Some userspaces do not preserve unusable property. Since usable
3911          * segment has to be present according to VMX spec we can use present
3912          * property to amend userspace bug by making unusable segment always
3913          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3914          * segment as unusable.
3915          */
3916         var->present = !var->unusable;
3917         var->avl = (ar >> 12) & 1;
3918         var->l = (ar >> 13) & 1;
3919         var->db = (ar >> 14) & 1;
3920         var->g = (ar >> 15) & 1;
3921 }
3922
3923 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3924 {
3925         struct kvm_segment s;
3926
3927         if (to_vmx(vcpu)->rmode.vm86_active) {
3928                 vmx_get_segment(vcpu, &s, seg);
3929                 return s.base;
3930         }
3931         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3932 }
3933
3934 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3935 {
3936         struct vcpu_vmx *vmx = to_vmx(vcpu);
3937
3938         if (unlikely(vmx->rmode.vm86_active))
3939                 return 0;
3940         else {
3941                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3942                 return VMX_AR_DPL(ar);
3943         }
3944 }
3945
3946 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3947 {
3948         u32 ar;
3949
3950         if (var->unusable || !var->present)
3951                 ar = 1 << 16;
3952         else {
3953                 ar = var->type & 15;
3954                 ar |= (var->s & 1) << 4;
3955                 ar |= (var->dpl & 3) << 5;
3956                 ar |= (var->present & 1) << 7;
3957                 ar |= (var->avl & 1) << 12;
3958                 ar |= (var->l & 1) << 13;
3959                 ar |= (var->db & 1) << 14;
3960                 ar |= (var->g & 1) << 15;
3961         }
3962
3963         return ar;
3964 }
3965
3966 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3967                             struct kvm_segment *var, int seg)
3968 {
3969         struct vcpu_vmx *vmx = to_vmx(vcpu);
3970         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3971
3972         vmx_segment_cache_clear(vmx);
3973
3974         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3975                 vmx->rmode.segs[seg] = *var;
3976                 if (seg == VCPU_SREG_TR)
3977                         vmcs_write16(sf->selector, var->selector);
3978                 else if (var->s)
3979                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3980                 goto out;
3981         }
3982
3983         vmcs_writel(sf->base, var->base);
3984         vmcs_write32(sf->limit, var->limit);
3985         vmcs_write16(sf->selector, var->selector);
3986
3987         /*
3988          *   Fix the "Accessed" bit in AR field of segment registers for older
3989          * qemu binaries.
3990          *   IA32 arch specifies that at the time of processor reset the
3991          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3992          * is setting it to 0 in the userland code. This causes invalid guest
3993          * state vmexit when "unrestricted guest" mode is turned on.
3994          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3995          * tree. Newer qemu binaries with that qemu fix would not need this
3996          * kvm hack.
3997          */
3998         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3999                 var->type |= 0x1; /* Accessed */
4000
4001         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4002
4003 out:
4004         vmx->emulation_required = emulation_required(vcpu);
4005 }
4006
4007 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4008 {
4009         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4010
4011         *db = (ar >> 14) & 1;
4012         *l = (ar >> 13) & 1;
4013 }
4014
4015 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4016 {
4017         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4018         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4019 }
4020
4021 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4022 {
4023         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4024         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4025 }
4026
4027 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4028 {
4029         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4030         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4031 }
4032
4033 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4034 {
4035         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4036         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4037 }
4038
4039 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4040 {
4041         struct kvm_segment var;
4042         u32 ar;
4043
4044         vmx_get_segment(vcpu, &var, seg);
4045         var.dpl = 0x3;
4046         if (seg == VCPU_SREG_CS)
4047                 var.type = 0x3;
4048         ar = vmx_segment_access_rights(&var);
4049
4050         if (var.base != (var.selector << 4))
4051                 return false;
4052         if (var.limit != 0xffff)
4053                 return false;
4054         if (ar != 0xf3)
4055                 return false;
4056
4057         return true;
4058 }
4059
4060 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4061 {
4062         struct kvm_segment cs;
4063         unsigned int cs_rpl;
4064
4065         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4066         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4067
4068         if (cs.unusable)
4069                 return false;
4070         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4071                 return false;
4072         if (!cs.s)
4073                 return false;
4074         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4075                 if (cs.dpl > cs_rpl)
4076                         return false;
4077         } else {
4078                 if (cs.dpl != cs_rpl)
4079                         return false;
4080         }
4081         if (!cs.present)
4082                 return false;
4083
4084         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4085         return true;
4086 }
4087
4088 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4089 {
4090         struct kvm_segment ss;
4091         unsigned int ss_rpl;
4092
4093         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4094         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4095
4096         if (ss.unusable)
4097                 return true;
4098         if (ss.type != 3 && ss.type != 7)
4099                 return false;
4100         if (!ss.s)
4101                 return false;
4102         if (ss.dpl != ss_rpl) /* DPL != RPL */
4103                 return false;
4104         if (!ss.present)
4105                 return false;
4106
4107         return true;
4108 }
4109
4110 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4111 {
4112         struct kvm_segment var;
4113         unsigned int rpl;
4114
4115         vmx_get_segment(vcpu, &var, seg);
4116         rpl = var.selector & SEGMENT_RPL_MASK;
4117
4118         if (var.unusable)
4119                 return true;
4120         if (!var.s)
4121                 return false;
4122         if (!var.present)
4123                 return false;
4124         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4125                 if (var.dpl < rpl) /* DPL < RPL */
4126                         return false;
4127         }
4128
4129         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4130          * rights flags
4131          */
4132         return true;
4133 }
4134
4135 static bool tr_valid(struct kvm_vcpu *vcpu)
4136 {
4137         struct kvm_segment tr;
4138
4139         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4140
4141         if (tr.unusable)
4142                 return false;
4143         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4144                 return false;
4145         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4146                 return false;
4147         if (!tr.present)
4148                 return false;
4149
4150         return true;
4151 }
4152
4153 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4154 {
4155         struct kvm_segment ldtr;
4156
4157         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4158
4159         if (ldtr.unusable)
4160                 return true;
4161         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4162                 return false;
4163         if (ldtr.type != 2)
4164                 return false;
4165         if (!ldtr.present)
4166                 return false;
4167
4168         return true;
4169 }
4170
4171 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4172 {
4173         struct kvm_segment cs, ss;
4174
4175         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4176         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4177
4178         return ((cs.selector & SEGMENT_RPL_MASK) ==
4179                  (ss.selector & SEGMENT_RPL_MASK));
4180 }
4181
4182 /*
4183  * Check if guest state is valid. Returns true if valid, false if
4184  * not.
4185  * We assume that registers are always usable
4186  */
4187 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4188 {
4189         if (enable_unrestricted_guest)
4190                 return true;
4191
4192         /* real mode guest state checks */
4193         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4194                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4195                         return false;
4196                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4197                         return false;
4198                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4199                         return false;
4200                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4201                         return false;
4202                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4203                         return false;
4204                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4205                         return false;
4206         } else {
4207         /* protected mode guest state checks */
4208                 if (!cs_ss_rpl_check(vcpu))
4209                         return false;
4210                 if (!code_segment_valid(vcpu))
4211                         return false;
4212                 if (!stack_segment_valid(vcpu))
4213                         return false;
4214                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4215                         return false;
4216                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4217                         return false;
4218                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4219                         return false;
4220                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4221                         return false;
4222                 if (!tr_valid(vcpu))
4223                         return false;
4224                 if (!ldtr_valid(vcpu))
4225                         return false;
4226         }
4227         /* TODO:
4228          * - Add checks on RIP
4229          * - Add checks on RFLAGS
4230          */
4231
4232         return true;
4233 }
4234
4235 static int init_rmode_tss(struct kvm *kvm)
4236 {
4237         gfn_t fn;
4238         u16 data = 0;
4239         int idx, r;
4240
4241         idx = srcu_read_lock(&kvm->srcu);
4242         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4243         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4244         if (r < 0)
4245                 goto out;
4246         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4247         r = kvm_write_guest_page(kvm, fn++, &data,
4248                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4249         if (r < 0)
4250                 goto out;
4251         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4252         if (r < 0)
4253                 goto out;
4254         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4255         if (r < 0)
4256                 goto out;
4257         data = ~0;
4258         r = kvm_write_guest_page(kvm, fn, &data,
4259                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4260                                  sizeof(u8));
4261 out:
4262         srcu_read_unlock(&kvm->srcu, idx);
4263         return r;
4264 }
4265
4266 static int init_rmode_identity_map(struct kvm *kvm)
4267 {
4268         int i, idx, r = 0;
4269         kvm_pfn_t identity_map_pfn;
4270         u32 tmp;
4271
4272         if (!enable_ept)
4273                 return 0;
4274
4275         /* Protect kvm->arch.ept_identity_pagetable_done. */
4276         mutex_lock(&kvm->slots_lock);
4277
4278         if (likely(kvm->arch.ept_identity_pagetable_done))
4279                 goto out2;
4280
4281         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4282
4283         r = alloc_identity_pagetable(kvm);
4284         if (r < 0)
4285                 goto out2;
4286
4287         idx = srcu_read_lock(&kvm->srcu);
4288         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4289         if (r < 0)
4290                 goto out;
4291         /* Set up identity-mapping pagetable for EPT in real mode */
4292         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4293                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4294                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4295                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4296                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4297                 if (r < 0)
4298                         goto out;
4299         }
4300         kvm->arch.ept_identity_pagetable_done = true;
4301
4302 out:
4303         srcu_read_unlock(&kvm->srcu, idx);
4304
4305 out2:
4306         mutex_unlock(&kvm->slots_lock);
4307         return r;
4308 }
4309
4310 static void seg_setup(int seg)
4311 {
4312         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4313         unsigned int ar;
4314
4315         vmcs_write16(sf->selector, 0);
4316         vmcs_writel(sf->base, 0);
4317         vmcs_write32(sf->limit, 0xffff);
4318         ar = 0x93;
4319         if (seg == VCPU_SREG_CS)
4320                 ar |= 0x08; /* code segment */
4321
4322         vmcs_write32(sf->ar_bytes, ar);
4323 }
4324
4325 static int alloc_apic_access_page(struct kvm *kvm)
4326 {
4327         struct page *page;
4328         int r = 0;
4329
4330         mutex_lock(&kvm->slots_lock);
4331         if (kvm->arch.apic_access_page_done)
4332                 goto out;
4333         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4334                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4335         if (r)
4336                 goto out;
4337
4338         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4339         if (is_error_page(page)) {
4340                 r = -EFAULT;
4341                 goto out;
4342         }
4343
4344         /*
4345          * Do not pin the page in memory, so that memory hot-unplug
4346          * is able to migrate it.
4347          */
4348         put_page(page);
4349         kvm->arch.apic_access_page_done = true;
4350 out:
4351         mutex_unlock(&kvm->slots_lock);
4352         return r;
4353 }
4354
4355 static int alloc_identity_pagetable(struct kvm *kvm)
4356 {
4357         /* Called with kvm->slots_lock held. */
4358
4359         int r = 0;
4360
4361         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4362
4363         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4364                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4365
4366         return r;
4367 }
4368
4369 static int allocate_vpid(void)
4370 {
4371         int vpid;
4372
4373         if (!enable_vpid)
4374                 return 0;
4375         spin_lock(&vmx_vpid_lock);
4376         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4377         if (vpid < VMX_NR_VPIDS)
4378                 __set_bit(vpid, vmx_vpid_bitmap);
4379         else
4380                 vpid = 0;
4381         spin_unlock(&vmx_vpid_lock);
4382         return vpid;
4383 }
4384
4385 static void free_vpid(int vpid)
4386 {
4387         if (!enable_vpid || vpid == 0)
4388                 return;
4389         spin_lock(&vmx_vpid_lock);
4390         __clear_bit(vpid, vmx_vpid_bitmap);
4391         spin_unlock(&vmx_vpid_lock);
4392 }
4393
4394 #define MSR_TYPE_R      1
4395 #define MSR_TYPE_W      2
4396 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4397                                                 u32 msr, int type)
4398 {
4399         int f = sizeof(unsigned long);
4400
4401         if (!cpu_has_vmx_msr_bitmap())
4402                 return;
4403
4404         /*
4405          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4406          * have the write-low and read-high bitmap offsets the wrong way round.
4407          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4408          */
4409         if (msr <= 0x1fff) {
4410                 if (type & MSR_TYPE_R)
4411                         /* read-low */
4412                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4413
4414                 if (type & MSR_TYPE_W)
4415                         /* write-low */
4416                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4417
4418         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4419                 msr &= 0x1fff;
4420                 if (type & MSR_TYPE_R)
4421                         /* read-high */
4422                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4423
4424                 if (type & MSR_TYPE_W)
4425                         /* write-high */
4426                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4427
4428         }
4429 }
4430
4431 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4432                                                 u32 msr, int type)
4433 {
4434         int f = sizeof(unsigned long);
4435
4436         if (!cpu_has_vmx_msr_bitmap())
4437                 return;
4438
4439         /*
4440          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4441          * have the write-low and read-high bitmap offsets the wrong way round.
4442          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4443          */
4444         if (msr <= 0x1fff) {
4445                 if (type & MSR_TYPE_R)
4446                         /* read-low */
4447                         __set_bit(msr, msr_bitmap + 0x000 / f);
4448
4449                 if (type & MSR_TYPE_W)
4450                         /* write-low */
4451                         __set_bit(msr, msr_bitmap + 0x800 / f);
4452
4453         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4454                 msr &= 0x1fff;
4455                 if (type & MSR_TYPE_R)
4456                         /* read-high */
4457                         __set_bit(msr, msr_bitmap + 0x400 / f);
4458
4459                 if (type & MSR_TYPE_W)
4460                         /* write-high */
4461                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4462
4463         }
4464 }
4465
4466 /*
4467  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4468  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4469  */
4470 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4471                                                unsigned long *msr_bitmap_nested,
4472                                                u32 msr, int type)
4473 {
4474         int f = sizeof(unsigned long);
4475
4476         if (!cpu_has_vmx_msr_bitmap()) {
4477                 WARN_ON(1);
4478                 return;
4479         }
4480
4481         /*
4482          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4483          * have the write-low and read-high bitmap offsets the wrong way round.
4484          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4485          */
4486         if (msr <= 0x1fff) {
4487                 if (type & MSR_TYPE_R &&
4488                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4489                         /* read-low */
4490                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4491
4492                 if (type & MSR_TYPE_W &&
4493                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4494                         /* write-low */
4495                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4496
4497         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4498                 msr &= 0x1fff;
4499                 if (type & MSR_TYPE_R &&
4500                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4501                         /* read-high */
4502                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4503
4504                 if (type & MSR_TYPE_W &&
4505                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4506                         /* write-high */
4507                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4508
4509         }
4510 }
4511
4512 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4513 {
4514         if (!longmode_only)
4515                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4516                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4517         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4518                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4519 }
4520
4521 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4522 {
4523         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4524                         msr, MSR_TYPE_R);
4525         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4526                         msr, MSR_TYPE_R);
4527 }
4528
4529 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4530 {
4531         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4532                         msr, MSR_TYPE_R);
4533         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4534                         msr, MSR_TYPE_R);
4535 }
4536
4537 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4538 {
4539         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4540                         msr, MSR_TYPE_W);
4541         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4542                         msr, MSR_TYPE_W);
4543 }
4544
4545 static bool vmx_get_enable_apicv(void)
4546 {
4547         return enable_apicv;
4548 }
4549
4550 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4551 {
4552         struct vcpu_vmx *vmx = to_vmx(vcpu);
4553         int max_irr;
4554         void *vapic_page;
4555         u16 status;
4556
4557         if (vmx->nested.pi_desc &&
4558             vmx->nested.pi_pending) {
4559                 vmx->nested.pi_pending = false;
4560                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4561                         return 0;
4562
4563                 max_irr = find_last_bit(
4564                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4565
4566                 if (max_irr == 256)
4567                         return 0;
4568
4569                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4570                 if (!vapic_page) {
4571                         WARN_ON(1);
4572                         return -ENOMEM;
4573                 }
4574                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4575                 kunmap(vmx->nested.virtual_apic_page);
4576
4577                 status = vmcs_read16(GUEST_INTR_STATUS);
4578                 if ((u8)max_irr > ((u8)status & 0xff)) {
4579                         status &= ~0xff;
4580                         status |= (u8)max_irr;
4581                         vmcs_write16(GUEST_INTR_STATUS, status);
4582                 }
4583         }
4584         return 0;
4585 }
4586
4587 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4588 {
4589 #ifdef CONFIG_SMP
4590         if (vcpu->mode == IN_GUEST_MODE) {
4591                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4592
4593                 /*
4594                  * Currently, we don't support urgent interrupt,
4595                  * all interrupts are recognized as non-urgent
4596                  * interrupt, so we cannot post interrupts when
4597                  * 'SN' is set.
4598                  *
4599                  * If the vcpu is in guest mode, it means it is
4600                  * running instead of being scheduled out and
4601                  * waiting in the run queue, and that's the only
4602                  * case when 'SN' is set currently, warning if
4603                  * 'SN' is set.
4604                  */
4605                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4606
4607                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4608                                 POSTED_INTR_VECTOR);
4609                 return true;
4610         }
4611 #endif
4612         return false;
4613 }
4614
4615 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4616                                                 int vector)
4617 {
4618         struct vcpu_vmx *vmx = to_vmx(vcpu);
4619
4620         if (is_guest_mode(vcpu) &&
4621             vector == vmx->nested.posted_intr_nv) {
4622                 /* the PIR and ON have been set by L1. */
4623                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4624                 /*
4625                  * If a posted intr is not recognized by hardware,
4626                  * we will accomplish it in the next vmentry.
4627                  */
4628                 vmx->nested.pi_pending = true;
4629                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4630                 return 0;
4631         }
4632         return -1;
4633 }
4634 /*
4635  * Send interrupt to vcpu via posted interrupt way.
4636  * 1. If target vcpu is running(non-root mode), send posted interrupt
4637  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4638  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4639  * interrupt from PIR in next vmentry.
4640  */
4641 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4642 {
4643         struct vcpu_vmx *vmx = to_vmx(vcpu);
4644         int r;
4645
4646         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4647         if (!r)
4648                 return;
4649
4650         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4651                 return;
4652
4653         r = pi_test_and_set_on(&vmx->pi_desc);
4654         kvm_make_request(KVM_REQ_EVENT, vcpu);
4655         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4656                 kvm_vcpu_kick(vcpu);
4657 }
4658
4659 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4660 {
4661         struct vcpu_vmx *vmx = to_vmx(vcpu);
4662
4663         if (!pi_test_and_clear_on(&vmx->pi_desc))
4664                 return;
4665
4666         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4667 }
4668
4669 /*
4670  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4671  * will not change in the lifetime of the guest.
4672  * Note that host-state that does change is set elsewhere. E.g., host-state
4673  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4674  */
4675 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4676 {
4677         u32 low32, high32;
4678         unsigned long tmpl;
4679         struct desc_ptr dt;
4680         unsigned long cr4;
4681
4682         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4683         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4684
4685         /* Save the most likely value for this task's CR4 in the VMCS. */
4686         cr4 = cr4_read_shadow();
4687         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4688         vmx->host_state.vmcs_host_cr4 = cr4;
4689
4690         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4691 #ifdef CONFIG_X86_64
4692         /*
4693          * Load null selectors, so we can avoid reloading them in
4694          * __vmx_load_host_state(), in case userspace uses the null selectors
4695          * too (the expected case).
4696          */
4697         vmcs_write16(HOST_DS_SELECTOR, 0);
4698         vmcs_write16(HOST_ES_SELECTOR, 0);
4699 #else
4700         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4701         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4702 #endif
4703         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4704         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4705
4706         native_store_idt(&dt);
4707         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4708         vmx->host_idt_base = dt.address;
4709
4710         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4711
4712         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4713         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4714         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4715         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4716
4717         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4718                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4719                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4720         }
4721 }
4722
4723 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4724 {
4725         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4726         if (enable_ept)
4727                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4728         if (is_guest_mode(&vmx->vcpu))
4729                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4730                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4731         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4732 }
4733
4734 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4735 {
4736         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4737
4738         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4739                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4740         return pin_based_exec_ctrl;
4741 }
4742
4743 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4744 {
4745         struct vcpu_vmx *vmx = to_vmx(vcpu);
4746
4747         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4748 }
4749
4750 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4751 {
4752         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4753
4754         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4755                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4756
4757         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4758                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4759 #ifdef CONFIG_X86_64
4760                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4761                                 CPU_BASED_CR8_LOAD_EXITING;
4762 #endif
4763         }
4764         if (!enable_ept)
4765                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4766                                 CPU_BASED_CR3_LOAD_EXITING  |
4767                                 CPU_BASED_INVLPG_EXITING;
4768         return exec_control;
4769 }
4770
4771 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4772 {
4773         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4774         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4775                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4776         if (vmx->vpid == 0)
4777                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4778         if (!enable_ept) {
4779                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4780                 enable_unrestricted_guest = 0;
4781                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4782                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4783         }
4784         if (!enable_unrestricted_guest)
4785                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4786         if (!ple_gap)
4787                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4788         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4789                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4790                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4791         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4792         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4793            (handle_vmptrld).
4794            We can NOT enable shadow_vmcs here because we don't have yet
4795            a current VMCS12
4796         */
4797         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4798
4799         if (!enable_pml)
4800                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4801
4802         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4803         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4804
4805         return exec_control;
4806 }
4807
4808 static void ept_set_mmio_spte_mask(void)
4809 {
4810         /*
4811          * EPT Misconfigurations can be generated if the value of bits 2:0
4812          * of an EPT paging-structure entry is 110b (write/execute).
4813          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4814          * spte.
4815          */
4816         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4817 }
4818
4819 #define VMX_XSS_EXIT_BITMAP 0
4820 /*
4821  * Sets up the vmcs for emulated real mode.
4822  */
4823 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4824 {
4825 #ifdef CONFIG_X86_64
4826         unsigned long a;
4827 #endif
4828         int i;
4829
4830         /* I/O */
4831         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4832         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4833
4834         if (enable_shadow_vmcs) {
4835                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4836                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4837         }
4838         if (cpu_has_vmx_msr_bitmap())
4839                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4840
4841         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4842
4843         /* Control */
4844         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4845
4846         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4847
4848         if (cpu_has_secondary_exec_ctrls())
4849                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4850                                 vmx_secondary_exec_control(vmx));
4851
4852         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4853                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4854                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4855                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4856                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4857
4858                 vmcs_write16(GUEST_INTR_STATUS, 0);
4859
4860                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4861                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4862         }
4863
4864         if (ple_gap) {
4865                 vmcs_write32(PLE_GAP, ple_gap);
4866                 vmx->ple_window = ple_window;
4867                 vmx->ple_window_dirty = true;
4868         }
4869
4870         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4871         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4872         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4873
4874         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4875         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4876         vmx_set_constant_host_state(vmx);
4877 #ifdef CONFIG_X86_64
4878         rdmsrl(MSR_FS_BASE, a);
4879         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4880         rdmsrl(MSR_GS_BASE, a);
4881         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4882 #else
4883         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4884         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4885 #endif
4886
4887         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4888         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4889         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4890         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4891         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4892
4893         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4894                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4895
4896         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4897                 u32 index = vmx_msr_index[i];
4898                 u32 data_low, data_high;
4899                 int j = vmx->nmsrs;
4900
4901                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4902                         continue;
4903                 if (wrmsr_safe(index, data_low, data_high) < 0)
4904                         continue;
4905                 vmx->guest_msrs[j].index = i;
4906                 vmx->guest_msrs[j].data = 0;
4907                 vmx->guest_msrs[j].mask = -1ull;
4908                 ++vmx->nmsrs;
4909         }
4910
4911
4912         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4913
4914         /* 22.2.1, 20.8.1 */
4915         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4916
4917         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4918         set_cr4_guest_host_mask(vmx);
4919
4920         if (vmx_xsaves_supported())
4921                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4922
4923         return 0;
4924 }
4925
4926 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4927 {
4928         struct vcpu_vmx *vmx = to_vmx(vcpu);
4929         struct msr_data apic_base_msr;
4930         u64 cr0;
4931
4932         vmx->rmode.vm86_active = 0;
4933
4934         vmx->soft_vnmi_blocked = 0;
4935
4936         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4937         kvm_set_cr8(vcpu, 0);
4938
4939         if (!init_event) {
4940                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4941                                      MSR_IA32_APICBASE_ENABLE;
4942                 if (kvm_vcpu_is_reset_bsp(vcpu))
4943                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4944                 apic_base_msr.host_initiated = true;
4945                 kvm_set_apic_base(vcpu, &apic_base_msr);
4946         }
4947
4948         vmx_segment_cache_clear(vmx);
4949
4950         seg_setup(VCPU_SREG_CS);
4951         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4952         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4953
4954         seg_setup(VCPU_SREG_DS);
4955         seg_setup(VCPU_SREG_ES);
4956         seg_setup(VCPU_SREG_FS);
4957         seg_setup(VCPU_SREG_GS);
4958         seg_setup(VCPU_SREG_SS);
4959
4960         vmcs_write16(GUEST_TR_SELECTOR, 0);
4961         vmcs_writel(GUEST_TR_BASE, 0);
4962         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4963         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4964
4965         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4966         vmcs_writel(GUEST_LDTR_BASE, 0);
4967         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4968         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4969
4970         if (!init_event) {
4971                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4972                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4973                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4974                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4975         }
4976
4977         vmcs_writel(GUEST_RFLAGS, 0x02);
4978         kvm_rip_write(vcpu, 0xfff0);
4979
4980         vmcs_writel(GUEST_GDTR_BASE, 0);
4981         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4982
4983         vmcs_writel(GUEST_IDTR_BASE, 0);
4984         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4985
4986         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4987         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4988         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4989
4990         setup_msrs(vmx);
4991
4992         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4993
4994         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4995                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4996                 if (cpu_need_tpr_shadow(vcpu))
4997                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4998                                      __pa(vcpu->arch.apic->regs));
4999                 vmcs_write32(TPR_THRESHOLD, 0);
5000         }
5001
5002         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5003
5004         if (kvm_vcpu_apicv_active(vcpu))
5005                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5006
5007         if (vmx->vpid != 0)
5008                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5009
5010         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5011         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5012         vmx->vcpu.arch.cr0 = cr0;
5013         vmx_set_cr4(vcpu, 0);
5014         vmx_set_efer(vcpu, 0);
5015         vmx_fpu_activate(vcpu);
5016         update_exception_bitmap(vcpu);
5017
5018         vpid_sync_context(vmx->vpid);
5019 }
5020
5021 /*
5022  * In nested virtualization, check if L1 asked to exit on external interrupts.
5023  * For most existing hypervisors, this will always return true.
5024  */
5025 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5026 {
5027         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5028                 PIN_BASED_EXT_INTR_MASK;
5029 }
5030
5031 /*
5032  * In nested virtualization, check if L1 has set
5033  * VM_EXIT_ACK_INTR_ON_EXIT
5034  */
5035 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5036 {
5037         return get_vmcs12(vcpu)->vm_exit_controls &
5038                 VM_EXIT_ACK_INTR_ON_EXIT;
5039 }
5040
5041 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5042 {
5043         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5044                 PIN_BASED_NMI_EXITING;
5045 }
5046
5047 static void enable_irq_window(struct kvm_vcpu *vcpu)
5048 {
5049         u32 cpu_based_vm_exec_control;
5050
5051         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5052         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5053         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5054 }
5055
5056 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5057 {
5058         u32 cpu_based_vm_exec_control;
5059
5060         if (!cpu_has_virtual_nmis() ||
5061             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5062                 enable_irq_window(vcpu);
5063                 return;
5064         }
5065
5066         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5067         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5068         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5069 }
5070
5071 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5072 {
5073         struct vcpu_vmx *vmx = to_vmx(vcpu);
5074         uint32_t intr;
5075         int irq = vcpu->arch.interrupt.nr;
5076
5077         trace_kvm_inj_virq(irq);
5078
5079         ++vcpu->stat.irq_injections;
5080         if (vmx->rmode.vm86_active) {
5081                 int inc_eip = 0;
5082                 if (vcpu->arch.interrupt.soft)
5083                         inc_eip = vcpu->arch.event_exit_inst_len;
5084                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5085                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5086                 return;
5087         }
5088         intr = irq | INTR_INFO_VALID_MASK;
5089         if (vcpu->arch.interrupt.soft) {
5090                 intr |= INTR_TYPE_SOFT_INTR;
5091                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5092                              vmx->vcpu.arch.event_exit_inst_len);
5093         } else
5094                 intr |= INTR_TYPE_EXT_INTR;
5095         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5096 }
5097
5098 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5099 {
5100         struct vcpu_vmx *vmx = to_vmx(vcpu);
5101
5102         if (is_guest_mode(vcpu))
5103                 return;
5104
5105         if (!cpu_has_virtual_nmis()) {
5106                 /*
5107                  * Tracking the NMI-blocked state in software is built upon
5108                  * finding the next open IRQ window. This, in turn, depends on
5109                  * well-behaving guests: They have to keep IRQs disabled at
5110                  * least as long as the NMI handler runs. Otherwise we may
5111                  * cause NMI nesting, maybe breaking the guest. But as this is
5112                  * highly unlikely, we can live with the residual risk.
5113                  */
5114                 vmx->soft_vnmi_blocked = 1;
5115                 vmx->vnmi_blocked_time = 0;
5116         }
5117
5118         ++vcpu->stat.nmi_injections;
5119         vmx->nmi_known_unmasked = false;
5120         if (vmx->rmode.vm86_active) {
5121                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5122                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5123                 return;
5124         }
5125         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5126                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5127 }
5128
5129 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5130 {
5131         if (!cpu_has_virtual_nmis())
5132                 return to_vmx(vcpu)->soft_vnmi_blocked;
5133         if (to_vmx(vcpu)->nmi_known_unmasked)
5134                 return false;
5135         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5136 }
5137
5138 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5139 {
5140         struct vcpu_vmx *vmx = to_vmx(vcpu);
5141
5142         if (!cpu_has_virtual_nmis()) {
5143                 if (vmx->soft_vnmi_blocked != masked) {
5144                         vmx->soft_vnmi_blocked = masked;
5145                         vmx->vnmi_blocked_time = 0;
5146                 }
5147         } else {
5148                 vmx->nmi_known_unmasked = !masked;
5149                 if (masked)
5150                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5151                                       GUEST_INTR_STATE_NMI);
5152                 else
5153                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5154                                         GUEST_INTR_STATE_NMI);
5155         }
5156 }
5157
5158 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5159 {
5160         if (to_vmx(vcpu)->nested.nested_run_pending)
5161                 return 0;
5162
5163         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5164                 return 0;
5165
5166         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5167                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5168                    | GUEST_INTR_STATE_NMI));
5169 }
5170
5171 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5172 {
5173         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5174                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5175                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5176                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5177 }
5178
5179 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5180 {
5181         int ret;
5182
5183         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5184                                     PAGE_SIZE * 3);
5185         if (ret)
5186                 return ret;
5187         kvm->arch.tss_addr = addr;
5188         return init_rmode_tss(kvm);
5189 }
5190
5191 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5192 {
5193         switch (vec) {
5194         case BP_VECTOR:
5195                 /*
5196                  * Update instruction length as we may reinject the exception
5197                  * from user space while in guest debugging mode.
5198                  */
5199                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5200                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5201                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5202                         return false;
5203                 /* fall through */
5204         case DB_VECTOR:
5205                 if (vcpu->guest_debug &
5206                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5207                         return false;
5208                 /* fall through */
5209         case DE_VECTOR:
5210         case OF_VECTOR:
5211         case BR_VECTOR:
5212         case UD_VECTOR:
5213         case DF_VECTOR:
5214         case SS_VECTOR:
5215         case GP_VECTOR:
5216         case MF_VECTOR:
5217                 return true;
5218         break;
5219         }
5220         return false;
5221 }
5222
5223 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5224                                   int vec, u32 err_code)
5225 {
5226         /*
5227          * Instruction with address size override prefix opcode 0x67
5228          * Cause the #SS fault with 0 error code in VM86 mode.
5229          */
5230         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5231                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5232                         if (vcpu->arch.halt_request) {
5233                                 vcpu->arch.halt_request = 0;
5234                                 return kvm_vcpu_halt(vcpu);
5235                         }
5236                         return 1;
5237                 }
5238                 return 0;
5239         }
5240
5241         /*
5242          * Forward all other exceptions that are valid in real mode.
5243          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5244          *        the required debugging infrastructure rework.
5245          */
5246         kvm_queue_exception(vcpu, vec);
5247         return 1;
5248 }
5249
5250 /*
5251  * Trigger machine check on the host. We assume all the MSRs are already set up
5252  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5253  * We pass a fake environment to the machine check handler because we want
5254  * the guest to be always treated like user space, no matter what context
5255  * it used internally.
5256  */
5257 static void kvm_machine_check(void)
5258 {
5259 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5260         struct pt_regs regs = {
5261                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5262                 .flags = X86_EFLAGS_IF,
5263         };
5264
5265         do_machine_check(&regs, 0);
5266 #endif
5267 }
5268
5269 static int handle_machine_check(struct kvm_vcpu *vcpu)
5270 {
5271         /* already handled by vcpu_run */
5272         return 1;
5273 }
5274
5275 static int handle_exception(struct kvm_vcpu *vcpu)
5276 {
5277         struct vcpu_vmx *vmx = to_vmx(vcpu);
5278         struct kvm_run *kvm_run = vcpu->run;
5279         u32 intr_info, ex_no, error_code;
5280         unsigned long cr2, rip, dr6;
5281         u32 vect_info;
5282         enum emulation_result er;
5283
5284         vect_info = vmx->idt_vectoring_info;
5285         intr_info = vmx->exit_intr_info;
5286
5287         if (is_machine_check(intr_info))
5288                 return handle_machine_check(vcpu);
5289
5290         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5291                 return 1;  /* already handled by vmx_vcpu_run() */
5292
5293         if (is_no_device(intr_info)) {
5294                 vmx_fpu_activate(vcpu);
5295                 return 1;
5296         }
5297
5298         if (is_invalid_opcode(intr_info)) {
5299                 if (is_guest_mode(vcpu)) {
5300                         kvm_queue_exception(vcpu, UD_VECTOR);
5301                         return 1;
5302                 }
5303                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5304                 if (er != EMULATE_DONE)
5305                         kvm_queue_exception(vcpu, UD_VECTOR);
5306                 return 1;
5307         }
5308
5309         error_code = 0;
5310         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5311                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5312
5313         /*
5314          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5315          * MMIO, it is better to report an internal error.
5316          * See the comments in vmx_handle_exit.
5317          */
5318         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5319             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5320                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5321                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5322                 vcpu->run->internal.ndata = 3;
5323                 vcpu->run->internal.data[0] = vect_info;
5324                 vcpu->run->internal.data[1] = intr_info;
5325                 vcpu->run->internal.data[2] = error_code;
5326                 return 0;
5327         }
5328
5329         if (is_page_fault(intr_info)) {
5330                 /* EPT won't cause page fault directly */
5331                 BUG_ON(enable_ept);
5332                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5333                 trace_kvm_page_fault(cr2, error_code);
5334
5335                 if (kvm_event_needs_reinjection(vcpu))
5336                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5337                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5338         }
5339
5340         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5341
5342         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5343                 return handle_rmode_exception(vcpu, ex_no, error_code);
5344
5345         switch (ex_no) {
5346         case AC_VECTOR:
5347                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5348                 return 1;
5349         case DB_VECTOR:
5350                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5351                 if (!(vcpu->guest_debug &
5352                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5353                         vcpu->arch.dr6 &= ~15;
5354                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5355                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5356                                 skip_emulated_instruction(vcpu);
5357
5358                         kvm_queue_exception(vcpu, DB_VECTOR);
5359                         return 1;
5360                 }
5361                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5362                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5363                 /* fall through */
5364         case BP_VECTOR:
5365                 /*
5366                  * Update instruction length as we may reinject #BP from
5367                  * user space while in guest debugging mode. Reading it for
5368                  * #DB as well causes no harm, it is not used in that case.
5369                  */
5370                 vmx->vcpu.arch.event_exit_inst_len =
5371                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5372                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5373                 rip = kvm_rip_read(vcpu);
5374                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5375                 kvm_run->debug.arch.exception = ex_no;
5376                 break;
5377         default:
5378                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5379                 kvm_run->ex.exception = ex_no;
5380                 kvm_run->ex.error_code = error_code;
5381                 break;
5382         }
5383         return 0;
5384 }
5385
5386 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5387 {
5388         ++vcpu->stat.irq_exits;
5389         return 1;
5390 }
5391
5392 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5393 {
5394         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5395         return 0;
5396 }
5397
5398 static int handle_io(struct kvm_vcpu *vcpu)
5399 {
5400         unsigned long exit_qualification;
5401         int size, in, string;
5402         unsigned port;
5403
5404         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5405         string = (exit_qualification & 16) != 0;
5406         in = (exit_qualification & 8) != 0;
5407
5408         ++vcpu->stat.io_exits;
5409
5410         if (string || in)
5411                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5412
5413         port = exit_qualification >> 16;
5414         size = (exit_qualification & 7) + 1;
5415         skip_emulated_instruction(vcpu);
5416
5417         return kvm_fast_pio_out(vcpu, size, port);
5418 }
5419
5420 static void
5421 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5422 {
5423         /*
5424          * Patch in the VMCALL instruction:
5425          */
5426         hypercall[0] = 0x0f;
5427         hypercall[1] = 0x01;
5428         hypercall[2] = 0xc1;
5429 }
5430
5431 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5432 {
5433         unsigned long always_on = VMXON_CR0_ALWAYSON;
5434         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5435
5436         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5437                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5438             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5439                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5440         return (val & always_on) == always_on;
5441 }
5442
5443 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5444 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5445 {
5446         if (is_guest_mode(vcpu)) {
5447                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5448                 unsigned long orig_val = val;
5449
5450                 /*
5451                  * We get here when L2 changed cr0 in a way that did not change
5452                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5453                  * but did change L0 shadowed bits. So we first calculate the
5454                  * effective cr0 value that L1 would like to write into the
5455                  * hardware. It consists of the L2-owned bits from the new
5456                  * value combined with the L1-owned bits from L1's guest_cr0.
5457                  */
5458                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5459                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5460
5461                 if (!nested_cr0_valid(vcpu, val))
5462                         return 1;
5463
5464                 if (kvm_set_cr0(vcpu, val))
5465                         return 1;
5466                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5467                 return 0;
5468         } else {
5469                 if (to_vmx(vcpu)->nested.vmxon &&
5470                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5471                         return 1;
5472                 return kvm_set_cr0(vcpu, val);
5473         }
5474 }
5475
5476 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5477 {
5478         if (is_guest_mode(vcpu)) {
5479                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5480                 unsigned long orig_val = val;
5481
5482                 /* analogously to handle_set_cr0 */
5483                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5484                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5485                 if (kvm_set_cr4(vcpu, val))
5486                         return 1;
5487                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5488                 return 0;
5489         } else
5490                 return kvm_set_cr4(vcpu, val);
5491 }
5492
5493 /* called to set cr0 as appropriate for clts instruction exit. */
5494 static void handle_clts(struct kvm_vcpu *vcpu)
5495 {
5496         if (is_guest_mode(vcpu)) {
5497                 /*
5498                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5499                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5500                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5501                  */
5502                 vmcs_writel(CR0_READ_SHADOW,
5503                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5504                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5505         } else
5506                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5507 }
5508
5509 static int handle_cr(struct kvm_vcpu *vcpu)
5510 {
5511         unsigned long exit_qualification, val;
5512         int cr;
5513         int reg;
5514         int err;
5515
5516         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5517         cr = exit_qualification & 15;
5518         reg = (exit_qualification >> 8) & 15;
5519         switch ((exit_qualification >> 4) & 3) {
5520         case 0: /* mov to cr */
5521                 val = kvm_register_readl(vcpu, reg);
5522                 trace_kvm_cr_write(cr, val);
5523                 switch (cr) {
5524                 case 0:
5525                         err = handle_set_cr0(vcpu, val);
5526                         kvm_complete_insn_gp(vcpu, err);
5527                         return 1;
5528                 case 3:
5529                         err = kvm_set_cr3(vcpu, val);
5530                         kvm_complete_insn_gp(vcpu, err);
5531                         return 1;
5532                 case 4:
5533                         err = handle_set_cr4(vcpu, val);
5534                         kvm_complete_insn_gp(vcpu, err);
5535                         return 1;
5536                 case 8: {
5537                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5538                                 u8 cr8 = (u8)val;
5539                                 err = kvm_set_cr8(vcpu, cr8);
5540                                 kvm_complete_insn_gp(vcpu, err);
5541                                 if (lapic_in_kernel(vcpu))
5542                                         return 1;
5543                                 if (cr8_prev <= cr8)
5544                                         return 1;
5545                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5546                                 return 0;
5547                         }
5548                 }
5549                 break;
5550         case 2: /* clts */
5551                 handle_clts(vcpu);
5552                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5553                 skip_emulated_instruction(vcpu);
5554                 vmx_fpu_activate(vcpu);
5555                 return 1;
5556         case 1: /*mov from cr*/
5557                 switch (cr) {
5558                 case 3:
5559                         val = kvm_read_cr3(vcpu);
5560                         kvm_register_write(vcpu, reg, val);
5561                         trace_kvm_cr_read(cr, val);
5562                         skip_emulated_instruction(vcpu);
5563                         return 1;
5564                 case 8:
5565                         val = kvm_get_cr8(vcpu);
5566                         kvm_register_write(vcpu, reg, val);
5567                         trace_kvm_cr_read(cr, val);
5568                         skip_emulated_instruction(vcpu);
5569                         return 1;
5570                 }
5571                 break;
5572         case 3: /* lmsw */
5573                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5574                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5575                 kvm_lmsw(vcpu, val);
5576
5577                 skip_emulated_instruction(vcpu);
5578                 return 1;
5579         default:
5580                 break;
5581         }
5582         vcpu->run->exit_reason = 0;
5583         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5584                (int)(exit_qualification >> 4) & 3, cr);
5585         return 0;
5586 }
5587
5588 static int handle_dr(struct kvm_vcpu *vcpu)
5589 {
5590         unsigned long exit_qualification;
5591         int dr, dr7, reg;
5592
5593         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5594         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5595
5596         /* First, if DR does not exist, trigger UD */
5597         if (!kvm_require_dr(vcpu, dr))
5598                 return 1;
5599
5600         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5601         if (!kvm_require_cpl(vcpu, 0))
5602                 return 1;
5603         dr7 = vmcs_readl(GUEST_DR7);
5604         if (dr7 & DR7_GD) {
5605                 /*
5606                  * As the vm-exit takes precedence over the debug trap, we
5607                  * need to emulate the latter, either for the host or the
5608                  * guest debugging itself.
5609                  */
5610                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5611                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5612                         vcpu->run->debug.arch.dr7 = dr7;
5613                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5614                         vcpu->run->debug.arch.exception = DB_VECTOR;
5615                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5616                         return 0;
5617                 } else {
5618                         vcpu->arch.dr6 &= ~15;
5619                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5620                         kvm_queue_exception(vcpu, DB_VECTOR);
5621                         return 1;
5622                 }
5623         }
5624
5625         if (vcpu->guest_debug == 0) {
5626                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5627                                 CPU_BASED_MOV_DR_EXITING);
5628
5629                 /*
5630                  * No more DR vmexits; force a reload of the debug registers
5631                  * and reenter on this instruction.  The next vmexit will
5632                  * retrieve the full state of the debug registers.
5633                  */
5634                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5635                 return 1;
5636         }
5637
5638         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5639         if (exit_qualification & TYPE_MOV_FROM_DR) {
5640                 unsigned long val;
5641
5642                 if (kvm_get_dr(vcpu, dr, &val))
5643                         return 1;
5644                 kvm_register_write(vcpu, reg, val);
5645         } else
5646                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5647                         return 1;
5648
5649         skip_emulated_instruction(vcpu);
5650         return 1;
5651 }
5652
5653 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5654 {
5655         return vcpu->arch.dr6;
5656 }
5657
5658 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5659 {
5660 }
5661
5662 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5663 {
5664         get_debugreg(vcpu->arch.db[0], 0);
5665         get_debugreg(vcpu->arch.db[1], 1);
5666         get_debugreg(vcpu->arch.db[2], 2);
5667         get_debugreg(vcpu->arch.db[3], 3);
5668         get_debugreg(vcpu->arch.dr6, 6);
5669         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5670
5671         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5672         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5673 }
5674
5675 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5676 {
5677         vmcs_writel(GUEST_DR7, val);
5678 }
5679
5680 static int handle_cpuid(struct kvm_vcpu *vcpu)
5681 {
5682         kvm_emulate_cpuid(vcpu);
5683         return 1;
5684 }
5685
5686 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5687 {
5688         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5689         struct msr_data msr_info;
5690
5691         msr_info.index = ecx;
5692         msr_info.host_initiated = false;
5693         if (vmx_get_msr(vcpu, &msr_info)) {
5694                 trace_kvm_msr_read_ex(ecx);
5695                 kvm_inject_gp(vcpu, 0);
5696                 return 1;
5697         }
5698
5699         trace_kvm_msr_read(ecx, msr_info.data);
5700
5701         /* FIXME: handling of bits 32:63 of rax, rdx */
5702         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5703         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5704         skip_emulated_instruction(vcpu);
5705         return 1;
5706 }
5707
5708 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5709 {
5710         struct msr_data msr;
5711         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5712         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5713                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5714
5715         msr.data = data;
5716         msr.index = ecx;
5717         msr.host_initiated = false;
5718         if (kvm_set_msr(vcpu, &msr) != 0) {
5719                 trace_kvm_msr_write_ex(ecx, data);
5720                 kvm_inject_gp(vcpu, 0);
5721                 return 1;
5722         }
5723
5724         trace_kvm_msr_write(ecx, data);
5725         skip_emulated_instruction(vcpu);
5726         return 1;
5727 }
5728
5729 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5730 {
5731         kvm_make_request(KVM_REQ_EVENT, vcpu);
5732         return 1;
5733 }
5734
5735 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5736 {
5737         u32 cpu_based_vm_exec_control;
5738
5739         /* clear pending irq */
5740         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5741         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5742         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5743
5744         kvm_make_request(KVM_REQ_EVENT, vcpu);
5745
5746         ++vcpu->stat.irq_window_exits;
5747         return 1;
5748 }
5749
5750 static int handle_halt(struct kvm_vcpu *vcpu)
5751 {
5752         return kvm_emulate_halt(vcpu);
5753 }
5754
5755 static int handle_vmcall(struct kvm_vcpu *vcpu)
5756 {
5757         return kvm_emulate_hypercall(vcpu);
5758 }
5759
5760 static int handle_invd(struct kvm_vcpu *vcpu)
5761 {
5762         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5763 }
5764
5765 static int handle_invlpg(struct kvm_vcpu *vcpu)
5766 {
5767         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5768
5769         kvm_mmu_invlpg(vcpu, exit_qualification);
5770         skip_emulated_instruction(vcpu);
5771         return 1;
5772 }
5773
5774 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5775 {
5776         int err;
5777
5778         err = kvm_rdpmc(vcpu);
5779         kvm_complete_insn_gp(vcpu, err);
5780
5781         return 1;
5782 }
5783
5784 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5785 {
5786         kvm_emulate_wbinvd(vcpu);
5787         return 1;
5788 }
5789
5790 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5791 {
5792         u64 new_bv = kvm_read_edx_eax(vcpu);
5793         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5794
5795         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5796                 skip_emulated_instruction(vcpu);
5797         return 1;
5798 }
5799
5800 static int handle_xsaves(struct kvm_vcpu *vcpu)
5801 {
5802         skip_emulated_instruction(vcpu);
5803         WARN(1, "this should never happen\n");
5804         return 1;
5805 }
5806
5807 static int handle_xrstors(struct kvm_vcpu *vcpu)
5808 {
5809         skip_emulated_instruction(vcpu);
5810         WARN(1, "this should never happen\n");
5811         return 1;
5812 }
5813
5814 static int handle_apic_access(struct kvm_vcpu *vcpu)
5815 {
5816         if (likely(fasteoi)) {
5817                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5818                 int access_type, offset;
5819
5820                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5821                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5822                 /*
5823                  * Sane guest uses MOV to write EOI, with written value
5824                  * not cared. So make a short-circuit here by avoiding
5825                  * heavy instruction emulation.
5826                  */
5827                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5828                     (offset == APIC_EOI)) {
5829                         kvm_lapic_set_eoi(vcpu);
5830                         skip_emulated_instruction(vcpu);
5831                         return 1;
5832                 }
5833         }
5834         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5835 }
5836
5837 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5838 {
5839         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5840         int vector = exit_qualification & 0xff;
5841
5842         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5843         kvm_apic_set_eoi_accelerated(vcpu, vector);
5844         return 1;
5845 }
5846
5847 static int handle_apic_write(struct kvm_vcpu *vcpu)
5848 {
5849         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5850         u32 offset = exit_qualification & 0xfff;
5851
5852         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5853         kvm_apic_write_nodecode(vcpu, offset);
5854         return 1;
5855 }
5856
5857 static int handle_task_switch(struct kvm_vcpu *vcpu)
5858 {
5859         struct vcpu_vmx *vmx = to_vmx(vcpu);
5860         unsigned long exit_qualification;
5861         bool has_error_code = false;
5862         u32 error_code = 0;
5863         u16 tss_selector;
5864         int reason, type, idt_v, idt_index;
5865
5866         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5867         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5868         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5869
5870         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5871
5872         reason = (u32)exit_qualification >> 30;
5873         if (reason == TASK_SWITCH_GATE && idt_v) {
5874                 switch (type) {
5875                 case INTR_TYPE_NMI_INTR:
5876                         vcpu->arch.nmi_injected = false;
5877                         vmx_set_nmi_mask(vcpu, true);
5878                         break;
5879                 case INTR_TYPE_EXT_INTR:
5880                 case INTR_TYPE_SOFT_INTR:
5881                         kvm_clear_interrupt_queue(vcpu);
5882                         break;
5883                 case INTR_TYPE_HARD_EXCEPTION:
5884                         if (vmx->idt_vectoring_info &
5885                             VECTORING_INFO_DELIVER_CODE_MASK) {
5886                                 has_error_code = true;
5887                                 error_code =
5888                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5889                         }
5890                         /* fall through */
5891                 case INTR_TYPE_SOFT_EXCEPTION:
5892                         kvm_clear_exception_queue(vcpu);
5893                         break;
5894                 default:
5895                         break;
5896                 }
5897         }
5898         tss_selector = exit_qualification;
5899
5900         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5901                        type != INTR_TYPE_EXT_INTR &&
5902                        type != INTR_TYPE_NMI_INTR))
5903                 skip_emulated_instruction(vcpu);
5904
5905         if (kvm_task_switch(vcpu, tss_selector,
5906                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5907                             has_error_code, error_code) == EMULATE_FAIL) {
5908                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5909                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5910                 vcpu->run->internal.ndata = 0;
5911                 return 0;
5912         }
5913
5914         /*
5915          * TODO: What about debug traps on tss switch?
5916          *       Are we supposed to inject them and update dr6?
5917          */
5918
5919         return 1;
5920 }
5921
5922 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5923 {
5924         unsigned long exit_qualification;
5925         gpa_t gpa;
5926         u32 error_code;
5927         int gla_validity;
5928
5929         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5930
5931         gla_validity = (exit_qualification >> 7) & 0x3;
5932         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5933                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5934                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5935                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5936                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5937                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5938                         (long unsigned int)exit_qualification);
5939                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5940                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5941                 return 0;
5942         }
5943
5944         /*
5945          * EPT violation happened while executing iret from NMI,
5946          * "blocked by NMI" bit has to be set before next VM entry.
5947          * There are errata that may cause this bit to not be set:
5948          * AAK134, BY25.
5949          */
5950         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5951                         cpu_has_virtual_nmis() &&
5952                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5953                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5954
5955         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5956         trace_kvm_page_fault(gpa, exit_qualification);
5957
5958         /* It is a write fault? */
5959         error_code = exit_qualification & PFERR_WRITE_MASK;
5960         /* It is a fetch fault? */
5961         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5962         /* ept page table is present? */
5963         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5964
5965         vcpu->arch.exit_qualification = exit_qualification;
5966
5967         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5968 }
5969
5970 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5971 {
5972         int ret;
5973         gpa_t gpa;
5974
5975         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5976         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5977                 skip_emulated_instruction(vcpu);
5978                 trace_kvm_fast_mmio(gpa);
5979                 return 1;
5980         }
5981
5982         ret = handle_mmio_page_fault(vcpu, gpa, true);
5983         if (likely(ret == RET_MMIO_PF_EMULATE))
5984                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5985                                               EMULATE_DONE;
5986
5987         if (unlikely(ret == RET_MMIO_PF_INVALID))
5988                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5989
5990         if (unlikely(ret == RET_MMIO_PF_RETRY))
5991                 return 1;
5992
5993         /* It is the real ept misconfig */
5994         WARN_ON(1);
5995
5996         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5997         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5998
5999         return 0;
6000 }
6001
6002 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6003 {
6004         u32 cpu_based_vm_exec_control;
6005
6006         /* clear pending NMI */
6007         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6008         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6009         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6010         ++vcpu->stat.nmi_window_exits;
6011         kvm_make_request(KVM_REQ_EVENT, vcpu);
6012
6013         return 1;
6014 }
6015
6016 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6017 {
6018         struct vcpu_vmx *vmx = to_vmx(vcpu);
6019         enum emulation_result err = EMULATE_DONE;
6020         int ret = 1;
6021         u32 cpu_exec_ctrl;
6022         bool intr_window_requested;
6023         unsigned count = 130;
6024
6025         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6026         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6027
6028         while (vmx->emulation_required && count-- != 0) {
6029                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6030                         return handle_interrupt_window(&vmx->vcpu);
6031
6032                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6033                         return 1;
6034
6035                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6036
6037                 if (err == EMULATE_USER_EXIT) {
6038                         ++vcpu->stat.mmio_exits;
6039                         ret = 0;
6040                         goto out;
6041                 }
6042
6043                 if (err != EMULATE_DONE) {
6044                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6045                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6046                         vcpu->run->internal.ndata = 0;
6047                         return 0;
6048                 }
6049
6050                 if (vcpu->arch.halt_request) {
6051                         vcpu->arch.halt_request = 0;
6052                         ret = kvm_vcpu_halt(vcpu);
6053                         goto out;
6054                 }
6055
6056                 if (signal_pending(current))
6057                         goto out;
6058                 if (need_resched())
6059                         schedule();
6060         }
6061
6062 out:
6063         return ret;
6064 }
6065
6066 static int __grow_ple_window(int val)
6067 {
6068         if (ple_window_grow < 1)
6069                 return ple_window;
6070
6071         val = min(val, ple_window_actual_max);
6072
6073         if (ple_window_grow < ple_window)
6074                 val *= ple_window_grow;
6075         else
6076                 val += ple_window_grow;
6077
6078         return val;
6079 }
6080
6081 static int __shrink_ple_window(int val, int modifier, int minimum)
6082 {
6083         if (modifier < 1)
6084                 return ple_window;
6085
6086         if (modifier < ple_window)
6087                 val /= modifier;
6088         else
6089                 val -= modifier;
6090
6091         return max(val, minimum);
6092 }
6093
6094 static void grow_ple_window(struct kvm_vcpu *vcpu)
6095 {
6096         struct vcpu_vmx *vmx = to_vmx(vcpu);
6097         int old = vmx->ple_window;
6098
6099         vmx->ple_window = __grow_ple_window(old);
6100
6101         if (vmx->ple_window != old)
6102                 vmx->ple_window_dirty = true;
6103
6104         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6105 }
6106
6107 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6108 {
6109         struct vcpu_vmx *vmx = to_vmx(vcpu);
6110         int old = vmx->ple_window;
6111
6112         vmx->ple_window = __shrink_ple_window(old,
6113                                               ple_window_shrink, ple_window);
6114
6115         if (vmx->ple_window != old)
6116                 vmx->ple_window_dirty = true;
6117
6118         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6119 }
6120
6121 /*
6122  * ple_window_actual_max is computed to be one grow_ple_window() below
6123  * ple_window_max. (See __grow_ple_window for the reason.)
6124  * This prevents overflows, because ple_window_max is int.
6125  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6126  * this process.
6127  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6128  */
6129 static void update_ple_window_actual_max(void)
6130 {
6131         ple_window_actual_max =
6132                         __shrink_ple_window(max(ple_window_max, ple_window),
6133                                             ple_window_grow, INT_MIN);
6134 }
6135
6136 /*
6137  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6138  */
6139 static void wakeup_handler(void)
6140 {
6141         struct kvm_vcpu *vcpu;
6142         int cpu = smp_processor_id();
6143
6144         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6145         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6146                         blocked_vcpu_list) {
6147                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6148
6149                 if (pi_test_on(pi_desc) == 1)
6150                         kvm_vcpu_kick(vcpu);
6151         }
6152         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6153 }
6154
6155 static __init int hardware_setup(void)
6156 {
6157         int r = -ENOMEM, i, msr;
6158
6159         rdmsrl_safe(MSR_EFER, &host_efer);
6160
6161         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6162                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6163
6164         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6165         if (!vmx_io_bitmap_a)
6166                 return r;
6167
6168         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6169         if (!vmx_io_bitmap_b)
6170                 goto out;
6171
6172         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6173         if (!vmx_msr_bitmap_legacy)
6174                 goto out1;
6175
6176         vmx_msr_bitmap_legacy_x2apic =
6177                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6178         if (!vmx_msr_bitmap_legacy_x2apic)
6179                 goto out2;
6180
6181         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6182         if (!vmx_msr_bitmap_longmode)
6183                 goto out3;
6184
6185         vmx_msr_bitmap_longmode_x2apic =
6186                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6187         if (!vmx_msr_bitmap_longmode_x2apic)
6188                 goto out4;
6189
6190         if (nested) {
6191                 vmx_msr_bitmap_nested =
6192                         (unsigned long *)__get_free_page(GFP_KERNEL);
6193                 if (!vmx_msr_bitmap_nested)
6194                         goto out5;
6195         }
6196
6197         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6198         if (!vmx_vmread_bitmap)
6199                 goto out6;
6200
6201         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6202         if (!vmx_vmwrite_bitmap)
6203                 goto out7;
6204
6205         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6206         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6207
6208         /*
6209          * Allow direct access to the PC debug port (it is often used for I/O
6210          * delays, but the vmexits simply slow things down).
6211          */
6212         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6213         clear_bit(0x80, vmx_io_bitmap_a);
6214
6215         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6216
6217         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6218         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6219         if (nested)
6220                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6221
6222         if (setup_vmcs_config(&vmcs_config) < 0) {
6223                 r = -EIO;
6224                 goto out8;
6225         }
6226
6227         if (boot_cpu_has(X86_FEATURE_NX))
6228                 kvm_enable_efer_bits(EFER_NX);
6229
6230         if (!cpu_has_vmx_vpid())
6231                 enable_vpid = 0;
6232         if (!cpu_has_vmx_shadow_vmcs())
6233                 enable_shadow_vmcs = 0;
6234         if (enable_shadow_vmcs)
6235                 init_vmcs_shadow_fields();
6236
6237         if (!cpu_has_vmx_ept() ||
6238             !cpu_has_vmx_ept_4levels()) {
6239                 enable_ept = 0;
6240                 enable_unrestricted_guest = 0;
6241                 enable_ept_ad_bits = 0;
6242         }
6243
6244         if (!cpu_has_vmx_ept_ad_bits())
6245                 enable_ept_ad_bits = 0;
6246
6247         if (!cpu_has_vmx_unrestricted_guest())
6248                 enable_unrestricted_guest = 0;
6249
6250         if (!cpu_has_vmx_flexpriority())
6251                 flexpriority_enabled = 0;
6252
6253         /*
6254          * set_apic_access_page_addr() is used to reload apic access
6255          * page upon invalidation.  No need to do anything if not
6256          * using the APIC_ACCESS_ADDR VMCS field.
6257          */
6258         if (!flexpriority_enabled)
6259                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6260
6261         if (!cpu_has_vmx_tpr_shadow())
6262                 kvm_x86_ops->update_cr8_intercept = NULL;
6263
6264         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6265                 kvm_disable_largepages();
6266
6267         if (!cpu_has_vmx_ple())
6268                 ple_gap = 0;
6269
6270         if (!cpu_has_vmx_apicv())
6271                 enable_apicv = 0;
6272
6273         if (cpu_has_vmx_tsc_scaling()) {
6274                 kvm_has_tsc_control = true;
6275                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6276                 kvm_tsc_scaling_ratio_frac_bits = 48;
6277         }
6278
6279         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6280         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6281         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6282         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6283         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6284         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6285         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6286
6287         memcpy(vmx_msr_bitmap_legacy_x2apic,
6288                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6289         memcpy(vmx_msr_bitmap_longmode_x2apic,
6290                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6291
6292         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6293
6294         if (enable_apicv) {
6295                 for (msr = 0x800; msr <= 0x8ff; msr++)
6296                         vmx_disable_intercept_msr_read_x2apic(msr);
6297
6298                 /* According SDM, in x2apic mode, the whole id reg is used.
6299                  * But in KVM, it only use the highest eight bits. Need to
6300                  * intercept it */
6301                 vmx_enable_intercept_msr_read_x2apic(0x802);
6302                 /* TMCCT */
6303                 vmx_enable_intercept_msr_read_x2apic(0x839);
6304                 /* TPR */
6305                 vmx_disable_intercept_msr_write_x2apic(0x808);
6306                 /* EOI */
6307                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6308                 /* SELF-IPI */
6309                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6310         }
6311
6312         if (enable_ept) {
6313                 kvm_mmu_set_mask_ptes(0ull,
6314                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6315                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6316                         0ull, VMX_EPT_EXECUTABLE_MASK);
6317                 ept_set_mmio_spte_mask();
6318                 kvm_enable_tdp();
6319         } else
6320                 kvm_disable_tdp();
6321
6322         update_ple_window_actual_max();
6323
6324         /*
6325          * Only enable PML when hardware supports PML feature, and both EPT
6326          * and EPT A/D bit features are enabled -- PML depends on them to work.
6327          */
6328         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6329                 enable_pml = 0;
6330
6331         if (!enable_pml) {
6332                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6333                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6334                 kvm_x86_ops->flush_log_dirty = NULL;
6335                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6336         }
6337
6338         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6339
6340         return alloc_kvm_area();
6341
6342 out8:
6343         free_page((unsigned long)vmx_vmwrite_bitmap);
6344 out7:
6345         free_page((unsigned long)vmx_vmread_bitmap);
6346 out6:
6347         if (nested)
6348                 free_page((unsigned long)vmx_msr_bitmap_nested);
6349 out5:
6350         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6351 out4:
6352         free_page((unsigned long)vmx_msr_bitmap_longmode);
6353 out3:
6354         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6355 out2:
6356         free_page((unsigned long)vmx_msr_bitmap_legacy);
6357 out1:
6358         free_page((unsigned long)vmx_io_bitmap_b);
6359 out:
6360         free_page((unsigned long)vmx_io_bitmap_a);
6361
6362     return r;
6363 }
6364
6365 static __exit void hardware_unsetup(void)
6366 {
6367         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6368         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6369         free_page((unsigned long)vmx_msr_bitmap_legacy);
6370         free_page((unsigned long)vmx_msr_bitmap_longmode);
6371         free_page((unsigned long)vmx_io_bitmap_b);
6372         free_page((unsigned long)vmx_io_bitmap_a);
6373         free_page((unsigned long)vmx_vmwrite_bitmap);
6374         free_page((unsigned long)vmx_vmread_bitmap);
6375         if (nested)
6376                 free_page((unsigned long)vmx_msr_bitmap_nested);
6377
6378         free_kvm_area();
6379 }
6380
6381 /*
6382  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6383  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6384  */
6385 static int handle_pause(struct kvm_vcpu *vcpu)
6386 {
6387         if (ple_gap)
6388                 grow_ple_window(vcpu);
6389
6390         skip_emulated_instruction(vcpu);
6391         kvm_vcpu_on_spin(vcpu);
6392
6393         return 1;
6394 }
6395
6396 static int handle_nop(struct kvm_vcpu *vcpu)
6397 {
6398         skip_emulated_instruction(vcpu);
6399         return 1;
6400 }
6401
6402 static int handle_mwait(struct kvm_vcpu *vcpu)
6403 {
6404         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6405         return handle_nop(vcpu);
6406 }
6407
6408 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6409 {
6410         return 1;
6411 }
6412
6413 static int handle_monitor(struct kvm_vcpu *vcpu)
6414 {
6415         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6416         return handle_nop(vcpu);
6417 }
6418
6419 /*
6420  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6421  * We could reuse a single VMCS for all the L2 guests, but we also want the
6422  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6423  * allows keeping them loaded on the processor, and in the future will allow
6424  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6425  * every entry if they never change.
6426  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6427  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6428  *
6429  * The following functions allocate and free a vmcs02 in this pool.
6430  */
6431
6432 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6433 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6434 {
6435         struct vmcs02_list *item;
6436         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6437                 if (item->vmptr == vmx->nested.current_vmptr) {
6438                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6439                         return &item->vmcs02;
6440                 }
6441
6442         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6443                 /* Recycle the least recently used VMCS. */
6444                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6445                                        struct vmcs02_list, list);
6446                 item->vmptr = vmx->nested.current_vmptr;
6447                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6448                 return &item->vmcs02;
6449         }
6450
6451         /* Create a new VMCS */
6452         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6453         if (!item)
6454                 return NULL;
6455         item->vmcs02.vmcs = alloc_vmcs();
6456         if (!item->vmcs02.vmcs) {
6457                 kfree(item);
6458                 return NULL;
6459         }
6460         loaded_vmcs_init(&item->vmcs02);
6461         item->vmptr = vmx->nested.current_vmptr;
6462         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6463         vmx->nested.vmcs02_num++;
6464         return &item->vmcs02;
6465 }
6466
6467 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6468 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6469 {
6470         struct vmcs02_list *item;
6471         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6472                 if (item->vmptr == vmptr) {
6473                         free_loaded_vmcs(&item->vmcs02);
6474                         list_del(&item->list);
6475                         kfree(item);
6476                         vmx->nested.vmcs02_num--;
6477                         return;
6478                 }
6479 }
6480
6481 /*
6482  * Free all VMCSs saved for this vcpu, except the one pointed by
6483  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6484  * must be &vmx->vmcs01.
6485  */
6486 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6487 {
6488         struct vmcs02_list *item, *n;
6489
6490         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6491         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6492                 /*
6493                  * Something will leak if the above WARN triggers.  Better than
6494                  * a use-after-free.
6495                  */
6496                 if (vmx->loaded_vmcs == &item->vmcs02)
6497                         continue;
6498
6499                 free_loaded_vmcs(&item->vmcs02);
6500                 list_del(&item->list);
6501                 kfree(item);
6502                 vmx->nested.vmcs02_num--;
6503         }
6504 }
6505
6506 /*
6507  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6508  * set the success or error code of an emulated VMX instruction, as specified
6509  * by Vol 2B, VMX Instruction Reference, "Conventions".
6510  */
6511 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6512 {
6513         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6514                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6515                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6516 }
6517
6518 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6519 {
6520         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6521                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6522                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6523                         | X86_EFLAGS_CF);
6524 }
6525
6526 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6527                                         u32 vm_instruction_error)
6528 {
6529         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6530                 /*
6531                  * failValid writes the error number to the current VMCS, which
6532                  * can't be done there isn't a current VMCS.
6533                  */
6534                 nested_vmx_failInvalid(vcpu);
6535                 return;
6536         }
6537         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6538                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6539                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6540                         | X86_EFLAGS_ZF);
6541         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6542         /*
6543          * We don't need to force a shadow sync because
6544          * VM_INSTRUCTION_ERROR is not shadowed
6545          */
6546 }
6547
6548 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6549 {
6550         /* TODO: not to reset guest simply here. */
6551         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6552         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6553 }
6554
6555 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6556 {
6557         struct vcpu_vmx *vmx =
6558                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6559
6560         vmx->nested.preemption_timer_expired = true;
6561         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6562         kvm_vcpu_kick(&vmx->vcpu);
6563
6564         return HRTIMER_NORESTART;
6565 }
6566
6567 /*
6568  * Decode the memory-address operand of a vmx instruction, as recorded on an
6569  * exit caused by such an instruction (run by a guest hypervisor).
6570  * On success, returns 0. When the operand is invalid, returns 1 and throws
6571  * #UD or #GP.
6572  */
6573 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6574                                  unsigned long exit_qualification,
6575                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6576 {
6577         gva_t off;
6578         bool exn;
6579         struct kvm_segment s;
6580
6581         /*
6582          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6583          * Execution", on an exit, vmx_instruction_info holds most of the
6584          * addressing components of the operand. Only the displacement part
6585          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6586          * For how an actual address is calculated from all these components,
6587          * refer to Vol. 1, "Operand Addressing".
6588          */
6589         int  scaling = vmx_instruction_info & 3;
6590         int  addr_size = (vmx_instruction_info >> 7) & 7;
6591         bool is_reg = vmx_instruction_info & (1u << 10);
6592         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6593         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6594         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6595         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6596         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6597
6598         if (is_reg) {
6599                 kvm_queue_exception(vcpu, UD_VECTOR);
6600                 return 1;
6601         }
6602
6603         /* Addr = segment_base + offset */
6604         /* offset = base + [index * scale] + displacement */
6605         off = exit_qualification; /* holds the displacement */
6606         if (base_is_valid)
6607                 off += kvm_register_read(vcpu, base_reg);
6608         if (index_is_valid)
6609                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6610         vmx_get_segment(vcpu, &s, seg_reg);
6611         *ret = s.base + off;
6612
6613         if (addr_size == 1) /* 32 bit */
6614                 *ret &= 0xffffffff;
6615
6616         /* Checks for #GP/#SS exceptions. */
6617         exn = false;
6618         if (is_protmode(vcpu)) {
6619                 /* Protected mode: apply checks for segment validity in the
6620                  * following order:
6621                  * - segment type check (#GP(0) may be thrown)
6622                  * - usability check (#GP(0)/#SS(0))
6623                  * - limit check (#GP(0)/#SS(0))
6624                  */
6625                 if (wr)
6626                         /* #GP(0) if the destination operand is located in a
6627                          * read-only data segment or any code segment.
6628                          */
6629                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6630                 else
6631                         /* #GP(0) if the source operand is located in an
6632                          * execute-only code segment
6633                          */
6634                         exn = ((s.type & 0xa) == 8);
6635         }
6636         if (exn) {
6637                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6638                 return 1;
6639         }
6640         if (is_long_mode(vcpu)) {
6641                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6642                  * non-canonical form. This is an only check for long mode.
6643                  */
6644                 exn = is_noncanonical_address(*ret);
6645         } else if (is_protmode(vcpu)) {
6646                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6647                  */
6648                 exn = (s.unusable != 0);
6649                 /* Protected mode: #GP(0)/#SS(0) if the memory
6650                  * operand is outside the segment limit.
6651                  */
6652                 exn = exn || (off + sizeof(u64) > s.limit);
6653         }
6654         if (exn) {
6655                 kvm_queue_exception_e(vcpu,
6656                                       seg_reg == VCPU_SREG_SS ?
6657                                                 SS_VECTOR : GP_VECTOR,
6658                                       0);
6659                 return 1;
6660         }
6661
6662         return 0;
6663 }
6664
6665 /*
6666  * This function performs the various checks including
6667  * - if it's 4KB aligned
6668  * - No bits beyond the physical address width are set
6669  * - Returns 0 on success or else 1
6670  * (Intel SDM Section 30.3)
6671  */
6672 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6673                                   gpa_t *vmpointer)
6674 {
6675         gva_t gva;
6676         gpa_t vmptr;
6677         struct x86_exception e;
6678         struct page *page;
6679         struct vcpu_vmx *vmx = to_vmx(vcpu);
6680         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6681
6682         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6683                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6684                 return 1;
6685
6686         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6687                                 sizeof(vmptr), &e)) {
6688                 kvm_inject_page_fault(vcpu, &e);
6689                 return 1;
6690         }
6691
6692         switch (exit_reason) {
6693         case EXIT_REASON_VMON:
6694                 /*
6695                  * SDM 3: 24.11.5
6696                  * The first 4 bytes of VMXON region contain the supported
6697                  * VMCS revision identifier
6698                  *
6699                  * Note - IA32_VMX_BASIC[48] will never be 1
6700                  * for the nested case;
6701                  * which replaces physical address width with 32
6702                  *
6703                  */
6704                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6705                         nested_vmx_failInvalid(vcpu);
6706                         skip_emulated_instruction(vcpu);
6707                         return 1;
6708                 }
6709
6710                 page = nested_get_page(vcpu, vmptr);
6711                 if (page == NULL ||
6712                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6713                         nested_vmx_failInvalid(vcpu);
6714                         kunmap(page);
6715                         skip_emulated_instruction(vcpu);
6716                         return 1;
6717                 }
6718                 kunmap(page);
6719                 vmx->nested.vmxon_ptr = vmptr;
6720                 break;
6721         case EXIT_REASON_VMCLEAR:
6722                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6723                         nested_vmx_failValid(vcpu,
6724                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6725                         skip_emulated_instruction(vcpu);
6726                         return 1;
6727                 }
6728
6729                 if (vmptr == vmx->nested.vmxon_ptr) {
6730                         nested_vmx_failValid(vcpu,
6731                                              VMXERR_VMCLEAR_VMXON_POINTER);
6732                         skip_emulated_instruction(vcpu);
6733                         return 1;
6734                 }
6735                 break;
6736         case EXIT_REASON_VMPTRLD:
6737                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6738                         nested_vmx_failValid(vcpu,
6739                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6740                         skip_emulated_instruction(vcpu);
6741                         return 1;
6742                 }
6743
6744                 if (vmptr == vmx->nested.vmxon_ptr) {
6745                         nested_vmx_failValid(vcpu,
6746                                              VMXERR_VMCLEAR_VMXON_POINTER);
6747                         skip_emulated_instruction(vcpu);
6748                         return 1;
6749                 }
6750                 break;
6751         default:
6752                 return 1; /* shouldn't happen */
6753         }
6754
6755         if (vmpointer)
6756                 *vmpointer = vmptr;
6757         return 0;
6758 }
6759
6760 /*
6761  * Emulate the VMXON instruction.
6762  * Currently, we just remember that VMX is active, and do not save or even
6763  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6764  * do not currently need to store anything in that guest-allocated memory
6765  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6766  * argument is different from the VMXON pointer (which the spec says they do).
6767  */
6768 static int handle_vmon(struct kvm_vcpu *vcpu)
6769 {
6770         struct kvm_segment cs;
6771         struct vcpu_vmx *vmx = to_vmx(vcpu);
6772         struct vmcs *shadow_vmcs;
6773         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6774                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6775
6776         /* The Intel VMX Instruction Reference lists a bunch of bits that
6777          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6778          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6779          * Otherwise, we should fail with #UD. We test these now:
6780          */
6781         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6782             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6783             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6784                 kvm_queue_exception(vcpu, UD_VECTOR);
6785                 return 1;
6786         }
6787
6788         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6789         if (is_long_mode(vcpu) && !cs.l) {
6790                 kvm_queue_exception(vcpu, UD_VECTOR);
6791                 return 1;
6792         }
6793
6794         if (vmx_get_cpl(vcpu)) {
6795                 kvm_inject_gp(vcpu, 0);
6796                 return 1;
6797         }
6798
6799         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6800                 return 1;
6801
6802         if (vmx->nested.vmxon) {
6803                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6804                 skip_emulated_instruction(vcpu);
6805                 return 1;
6806         }
6807
6808         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6809                         != VMXON_NEEDED_FEATURES) {
6810                 kvm_inject_gp(vcpu, 0);
6811                 return 1;
6812         }
6813
6814         if (enable_shadow_vmcs) {
6815                 shadow_vmcs = alloc_vmcs();
6816                 if (!shadow_vmcs)
6817                         return -ENOMEM;
6818                 /* mark vmcs as shadow */
6819                 shadow_vmcs->revision_id |= (1u << 31);
6820                 /* init shadow vmcs */
6821                 vmcs_clear(shadow_vmcs);
6822                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6823         }
6824
6825         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6826         vmx->nested.vmcs02_num = 0;
6827
6828         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6829                      HRTIMER_MODE_REL);
6830         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6831
6832         vmx->nested.vmxon = true;
6833
6834         skip_emulated_instruction(vcpu);
6835         nested_vmx_succeed(vcpu);
6836         return 1;
6837 }
6838
6839 /*
6840  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6841  * for running VMX instructions (except VMXON, whose prerequisites are
6842  * slightly different). It also specifies what exception to inject otherwise.
6843  */
6844 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6845 {
6846         struct kvm_segment cs;
6847         struct vcpu_vmx *vmx = to_vmx(vcpu);
6848
6849         if (!vmx->nested.vmxon) {
6850                 kvm_queue_exception(vcpu, UD_VECTOR);
6851                 return 0;
6852         }
6853
6854         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6855         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6856             (is_long_mode(vcpu) && !cs.l)) {
6857                 kvm_queue_exception(vcpu, UD_VECTOR);
6858                 return 0;
6859         }
6860
6861         if (vmx_get_cpl(vcpu)) {
6862                 kvm_inject_gp(vcpu, 0);
6863                 return 0;
6864         }
6865
6866         return 1;
6867 }
6868
6869 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6870 {
6871         if (vmx->nested.current_vmptr == -1ull)
6872                 return;
6873
6874         /* current_vmptr and current_vmcs12 are always set/reset together */
6875         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6876                 return;
6877
6878         if (enable_shadow_vmcs) {
6879                 /* copy to memory all shadowed fields in case
6880                    they were modified */
6881                 copy_shadow_to_vmcs12(vmx);
6882                 vmx->nested.sync_shadow_vmcs = false;
6883                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6884                                 SECONDARY_EXEC_SHADOW_VMCS);
6885                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6886         }
6887         vmx->nested.posted_intr_nv = -1;
6888         kunmap(vmx->nested.current_vmcs12_page);
6889         nested_release_page(vmx->nested.current_vmcs12_page);
6890         vmx->nested.current_vmptr = -1ull;
6891         vmx->nested.current_vmcs12 = NULL;
6892 }
6893
6894 /*
6895  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6896  * just stops using VMX.
6897  */
6898 static void free_nested(struct vcpu_vmx *vmx)
6899 {
6900         if (!vmx->nested.vmxon)
6901                 return;
6902
6903         vmx->nested.vmxon = false;
6904         free_vpid(vmx->nested.vpid02);
6905         nested_release_vmcs12(vmx);
6906         if (enable_shadow_vmcs)
6907                 free_vmcs(vmx->nested.current_shadow_vmcs);
6908         /* Unpin physical memory we referred to in current vmcs02 */
6909         if (vmx->nested.apic_access_page) {
6910                 nested_release_page(vmx->nested.apic_access_page);
6911                 vmx->nested.apic_access_page = NULL;
6912         }
6913         if (vmx->nested.virtual_apic_page) {
6914                 nested_release_page(vmx->nested.virtual_apic_page);
6915                 vmx->nested.virtual_apic_page = NULL;
6916         }
6917         if (vmx->nested.pi_desc_page) {
6918                 kunmap(vmx->nested.pi_desc_page);
6919                 nested_release_page(vmx->nested.pi_desc_page);
6920                 vmx->nested.pi_desc_page = NULL;
6921                 vmx->nested.pi_desc = NULL;
6922         }
6923
6924         nested_free_all_saved_vmcss(vmx);
6925 }
6926
6927 /* Emulate the VMXOFF instruction */
6928 static int handle_vmoff(struct kvm_vcpu *vcpu)
6929 {
6930         if (!nested_vmx_check_permission(vcpu))
6931                 return 1;
6932         free_nested(to_vmx(vcpu));
6933         skip_emulated_instruction(vcpu);
6934         nested_vmx_succeed(vcpu);
6935         return 1;
6936 }
6937
6938 /* Emulate the VMCLEAR instruction */
6939 static int handle_vmclear(struct kvm_vcpu *vcpu)
6940 {
6941         struct vcpu_vmx *vmx = to_vmx(vcpu);
6942         gpa_t vmptr;
6943         struct vmcs12 *vmcs12;
6944         struct page *page;
6945
6946         if (!nested_vmx_check_permission(vcpu))
6947                 return 1;
6948
6949         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6950                 return 1;
6951
6952         if (vmptr == vmx->nested.current_vmptr)
6953                 nested_release_vmcs12(vmx);
6954
6955         page = nested_get_page(vcpu, vmptr);
6956         if (page == NULL) {
6957                 /*
6958                  * For accurate processor emulation, VMCLEAR beyond available
6959                  * physical memory should do nothing at all. However, it is
6960                  * possible that a nested vmx bug, not a guest hypervisor bug,
6961                  * resulted in this case, so let's shut down before doing any
6962                  * more damage:
6963                  */
6964                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6965                 return 1;
6966         }
6967         vmcs12 = kmap(page);
6968         vmcs12->launch_state = 0;
6969         kunmap(page);
6970         nested_release_page(page);
6971
6972         nested_free_vmcs02(vmx, vmptr);
6973
6974         skip_emulated_instruction(vcpu);
6975         nested_vmx_succeed(vcpu);
6976         return 1;
6977 }
6978
6979 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6980
6981 /* Emulate the VMLAUNCH instruction */
6982 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6983 {
6984         return nested_vmx_run(vcpu, true);
6985 }
6986
6987 /* Emulate the VMRESUME instruction */
6988 static int handle_vmresume(struct kvm_vcpu *vcpu)
6989 {
6990
6991         return nested_vmx_run(vcpu, false);
6992 }
6993
6994 enum vmcs_field_type {
6995         VMCS_FIELD_TYPE_U16 = 0,
6996         VMCS_FIELD_TYPE_U64 = 1,
6997         VMCS_FIELD_TYPE_U32 = 2,
6998         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6999 };
7000
7001 static inline int vmcs_field_type(unsigned long field)
7002 {
7003         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7004                 return VMCS_FIELD_TYPE_U32;
7005         return (field >> 13) & 0x3 ;
7006 }
7007
7008 static inline int vmcs_field_readonly(unsigned long field)
7009 {
7010         return (((field >> 10) & 0x3) == 1);
7011 }
7012
7013 /*
7014  * Read a vmcs12 field. Since these can have varying lengths and we return
7015  * one type, we chose the biggest type (u64) and zero-extend the return value
7016  * to that size. Note that the caller, handle_vmread, might need to use only
7017  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7018  * 64-bit fields are to be returned).
7019  */
7020 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7021                                   unsigned long field, u64 *ret)
7022 {
7023         short offset = vmcs_field_to_offset(field);
7024         char *p;
7025
7026         if (offset < 0)
7027                 return offset;
7028
7029         p = ((char *)(get_vmcs12(vcpu))) + offset;
7030
7031         switch (vmcs_field_type(field)) {
7032         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7033                 *ret = *((natural_width *)p);
7034                 return 0;
7035         case VMCS_FIELD_TYPE_U16:
7036                 *ret = *((u16 *)p);
7037                 return 0;
7038         case VMCS_FIELD_TYPE_U32:
7039                 *ret = *((u32 *)p);
7040                 return 0;
7041         case VMCS_FIELD_TYPE_U64:
7042                 *ret = *((u64 *)p);
7043                 return 0;
7044         default:
7045                 WARN_ON(1);
7046                 return -ENOENT;
7047         }
7048 }
7049
7050
7051 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7052                                    unsigned long field, u64 field_value){
7053         short offset = vmcs_field_to_offset(field);
7054         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7055         if (offset < 0)
7056                 return offset;
7057
7058         switch (vmcs_field_type(field)) {
7059         case VMCS_FIELD_TYPE_U16:
7060                 *(u16 *)p = field_value;
7061                 return 0;
7062         case VMCS_FIELD_TYPE_U32:
7063                 *(u32 *)p = field_value;
7064                 return 0;
7065         case VMCS_FIELD_TYPE_U64:
7066                 *(u64 *)p = field_value;
7067                 return 0;
7068         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7069                 *(natural_width *)p = field_value;
7070                 return 0;
7071         default:
7072                 WARN_ON(1);
7073                 return -ENOENT;
7074         }
7075
7076 }
7077
7078 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7079 {
7080         int i;
7081         unsigned long field;
7082         u64 field_value;
7083         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7084         const unsigned long *fields = shadow_read_write_fields;
7085         const int num_fields = max_shadow_read_write_fields;
7086
7087         preempt_disable();
7088
7089         vmcs_load(shadow_vmcs);
7090
7091         for (i = 0; i < num_fields; i++) {
7092                 field = fields[i];
7093                 switch (vmcs_field_type(field)) {
7094                 case VMCS_FIELD_TYPE_U16:
7095                         field_value = vmcs_read16(field);
7096                         break;
7097                 case VMCS_FIELD_TYPE_U32:
7098                         field_value = vmcs_read32(field);
7099                         break;
7100                 case VMCS_FIELD_TYPE_U64:
7101                         field_value = vmcs_read64(field);
7102                         break;
7103                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7104                         field_value = vmcs_readl(field);
7105                         break;
7106                 default:
7107                         WARN_ON(1);
7108                         continue;
7109                 }
7110                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7111         }
7112
7113         vmcs_clear(shadow_vmcs);
7114         vmcs_load(vmx->loaded_vmcs->vmcs);
7115
7116         preempt_enable();
7117 }
7118
7119 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7120 {
7121         const unsigned long *fields[] = {
7122                 shadow_read_write_fields,
7123                 shadow_read_only_fields
7124         };
7125         const int max_fields[] = {
7126                 max_shadow_read_write_fields,
7127                 max_shadow_read_only_fields
7128         };
7129         int i, q;
7130         unsigned long field;
7131         u64 field_value = 0;
7132         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7133
7134         vmcs_load(shadow_vmcs);
7135
7136         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7137                 for (i = 0; i < max_fields[q]; i++) {
7138                         field = fields[q][i];
7139                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7140
7141                         switch (vmcs_field_type(field)) {
7142                         case VMCS_FIELD_TYPE_U16:
7143                                 vmcs_write16(field, (u16)field_value);
7144                                 break;
7145                         case VMCS_FIELD_TYPE_U32:
7146                                 vmcs_write32(field, (u32)field_value);
7147                                 break;
7148                         case VMCS_FIELD_TYPE_U64:
7149                                 vmcs_write64(field, (u64)field_value);
7150                                 break;
7151                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7152                                 vmcs_writel(field, (long)field_value);
7153                                 break;
7154                         default:
7155                                 WARN_ON(1);
7156                                 break;
7157                         }
7158                 }
7159         }
7160
7161         vmcs_clear(shadow_vmcs);
7162         vmcs_load(vmx->loaded_vmcs->vmcs);
7163 }
7164
7165 /*
7166  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7167  * used before) all generate the same failure when it is missing.
7168  */
7169 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7170 {
7171         struct vcpu_vmx *vmx = to_vmx(vcpu);
7172         if (vmx->nested.current_vmptr == -1ull) {
7173                 nested_vmx_failInvalid(vcpu);
7174                 skip_emulated_instruction(vcpu);
7175                 return 0;
7176         }
7177         return 1;
7178 }
7179
7180 static int handle_vmread(struct kvm_vcpu *vcpu)
7181 {
7182         unsigned long field;
7183         u64 field_value;
7184         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7185         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7186         gva_t gva = 0;
7187
7188         if (!nested_vmx_check_permission(vcpu) ||
7189             !nested_vmx_check_vmcs12(vcpu))
7190                 return 1;
7191
7192         /* Decode instruction info and find the field to read */
7193         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7194         /* Read the field, zero-extended to a u64 field_value */
7195         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7196                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7197                 skip_emulated_instruction(vcpu);
7198                 return 1;
7199         }
7200         /*
7201          * Now copy part of this value to register or memory, as requested.
7202          * Note that the number of bits actually copied is 32 or 64 depending
7203          * on the guest's mode (32 or 64 bit), not on the given field's length.
7204          */
7205         if (vmx_instruction_info & (1u << 10)) {
7206                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7207                         field_value);
7208         } else {
7209                 if (get_vmx_mem_address(vcpu, exit_qualification,
7210                                 vmx_instruction_info, true, &gva))
7211                         return 1;
7212                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7213                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7214                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7215         }
7216
7217         nested_vmx_succeed(vcpu);
7218         skip_emulated_instruction(vcpu);
7219         return 1;
7220 }
7221
7222
7223 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7224 {
7225         unsigned long field;
7226         gva_t gva;
7227         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7228         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7229         /* The value to write might be 32 or 64 bits, depending on L1's long
7230          * mode, and eventually we need to write that into a field of several
7231          * possible lengths. The code below first zero-extends the value to 64
7232          * bit (field_value), and then copies only the appropriate number of
7233          * bits into the vmcs12 field.
7234          */
7235         u64 field_value = 0;
7236         struct x86_exception e;
7237
7238         if (!nested_vmx_check_permission(vcpu) ||
7239             !nested_vmx_check_vmcs12(vcpu))
7240                 return 1;
7241
7242         if (vmx_instruction_info & (1u << 10))
7243                 field_value = kvm_register_readl(vcpu,
7244                         (((vmx_instruction_info) >> 3) & 0xf));
7245         else {
7246                 if (get_vmx_mem_address(vcpu, exit_qualification,
7247                                 vmx_instruction_info, false, &gva))
7248                         return 1;
7249                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7250                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7251                         kvm_inject_page_fault(vcpu, &e);
7252                         return 1;
7253                 }
7254         }
7255
7256
7257         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7258         if (vmcs_field_readonly(field)) {
7259                 nested_vmx_failValid(vcpu,
7260                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7261                 skip_emulated_instruction(vcpu);
7262                 return 1;
7263         }
7264
7265         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7266                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7267                 skip_emulated_instruction(vcpu);
7268                 return 1;
7269         }
7270
7271         nested_vmx_succeed(vcpu);
7272         skip_emulated_instruction(vcpu);
7273         return 1;
7274 }
7275
7276 /* Emulate the VMPTRLD instruction */
7277 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7278 {
7279         struct vcpu_vmx *vmx = to_vmx(vcpu);
7280         gpa_t vmptr;
7281
7282         if (!nested_vmx_check_permission(vcpu))
7283                 return 1;
7284
7285         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7286                 return 1;
7287
7288         if (vmx->nested.current_vmptr != vmptr) {
7289                 struct vmcs12 *new_vmcs12;
7290                 struct page *page;
7291                 page = nested_get_page(vcpu, vmptr);
7292                 if (page == NULL) {
7293                         nested_vmx_failInvalid(vcpu);
7294                         skip_emulated_instruction(vcpu);
7295                         return 1;
7296                 }
7297                 new_vmcs12 = kmap(page);
7298                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7299                         kunmap(page);
7300                         nested_release_page_clean(page);
7301                         nested_vmx_failValid(vcpu,
7302                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7303                         skip_emulated_instruction(vcpu);
7304                         return 1;
7305                 }
7306
7307                 nested_release_vmcs12(vmx);
7308                 vmx->nested.current_vmptr = vmptr;
7309                 vmx->nested.current_vmcs12 = new_vmcs12;
7310                 vmx->nested.current_vmcs12_page = page;
7311                 if (enable_shadow_vmcs) {
7312                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7313                                       SECONDARY_EXEC_SHADOW_VMCS);
7314                         vmcs_write64(VMCS_LINK_POINTER,
7315                                      __pa(vmx->nested.current_shadow_vmcs));
7316                         vmx->nested.sync_shadow_vmcs = true;
7317                 }
7318         }
7319
7320         nested_vmx_succeed(vcpu);
7321         skip_emulated_instruction(vcpu);
7322         return 1;
7323 }
7324
7325 /* Emulate the VMPTRST instruction */
7326 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7327 {
7328         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7329         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7330         gva_t vmcs_gva;
7331         struct x86_exception e;
7332
7333         if (!nested_vmx_check_permission(vcpu))
7334                 return 1;
7335
7336         if (get_vmx_mem_address(vcpu, exit_qualification,
7337                         vmx_instruction_info, true, &vmcs_gva))
7338                 return 1;
7339         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7340         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7341                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7342                                  sizeof(u64), &e)) {
7343                 kvm_inject_page_fault(vcpu, &e);
7344                 return 1;
7345         }
7346         nested_vmx_succeed(vcpu);
7347         skip_emulated_instruction(vcpu);
7348         return 1;
7349 }
7350
7351 /* Emulate the INVEPT instruction */
7352 static int handle_invept(struct kvm_vcpu *vcpu)
7353 {
7354         struct vcpu_vmx *vmx = to_vmx(vcpu);
7355         u32 vmx_instruction_info, types;
7356         unsigned long type;
7357         gva_t gva;
7358         struct x86_exception e;
7359         struct {
7360                 u64 eptp, gpa;
7361         } operand;
7362
7363         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7364               SECONDARY_EXEC_ENABLE_EPT) ||
7365             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7366                 kvm_queue_exception(vcpu, UD_VECTOR);
7367                 return 1;
7368         }
7369
7370         if (!nested_vmx_check_permission(vcpu))
7371                 return 1;
7372
7373         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7374                 kvm_queue_exception(vcpu, UD_VECTOR);
7375                 return 1;
7376         }
7377
7378         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7379         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7380
7381         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7382
7383         if (!(types & (1UL << type))) {
7384                 nested_vmx_failValid(vcpu,
7385                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7386                 return 1;
7387         }
7388
7389         /* According to the Intel VMX instruction reference, the memory
7390          * operand is read even if it isn't needed (e.g., for type==global)
7391          */
7392         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7393                         vmx_instruction_info, false, &gva))
7394                 return 1;
7395         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7396                                 sizeof(operand), &e)) {
7397                 kvm_inject_page_fault(vcpu, &e);
7398                 return 1;
7399         }
7400
7401         switch (type) {
7402         case VMX_EPT_EXTENT_GLOBAL:
7403                 kvm_mmu_sync_roots(vcpu);
7404                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7405                 nested_vmx_succeed(vcpu);
7406                 break;
7407         default:
7408                 /* Trap single context invalidation invept calls */
7409                 BUG_ON(1);
7410                 break;
7411         }
7412
7413         skip_emulated_instruction(vcpu);
7414         return 1;
7415 }
7416
7417 static int handle_invvpid(struct kvm_vcpu *vcpu)
7418 {
7419         struct vcpu_vmx *vmx = to_vmx(vcpu);
7420         u32 vmx_instruction_info;
7421         unsigned long type, types;
7422         gva_t gva;
7423         struct x86_exception e;
7424         int vpid;
7425
7426         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7427               SECONDARY_EXEC_ENABLE_VPID) ||
7428                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7429                 kvm_queue_exception(vcpu, UD_VECTOR);
7430                 return 1;
7431         }
7432
7433         if (!nested_vmx_check_permission(vcpu))
7434                 return 1;
7435
7436         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7437         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7438
7439         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7440
7441         if (!(types & (1UL << type))) {
7442                 nested_vmx_failValid(vcpu,
7443                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7444                 return 1;
7445         }
7446
7447         /* according to the intel vmx instruction reference, the memory
7448          * operand is read even if it isn't needed (e.g., for type==global)
7449          */
7450         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7451                         vmx_instruction_info, false, &gva))
7452                 return 1;
7453         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7454                                 sizeof(u32), &e)) {
7455                 kvm_inject_page_fault(vcpu, &e);
7456                 return 1;
7457         }
7458
7459         switch (type) {
7460         case VMX_VPID_EXTENT_ALL_CONTEXT:
7461                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7462                 nested_vmx_succeed(vcpu);
7463                 break;
7464         default:
7465                 /* Trap single context invalidation invvpid calls */
7466                 BUG_ON(1);
7467                 break;
7468         }
7469
7470         skip_emulated_instruction(vcpu);
7471         return 1;
7472 }
7473
7474 static int handle_pml_full(struct kvm_vcpu *vcpu)
7475 {
7476         unsigned long exit_qualification;
7477
7478         trace_kvm_pml_full(vcpu->vcpu_id);
7479
7480         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7481
7482         /*
7483          * PML buffer FULL happened while executing iret from NMI,
7484          * "blocked by NMI" bit has to be set before next VM entry.
7485          */
7486         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7487                         cpu_has_virtual_nmis() &&
7488                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7489                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7490                                 GUEST_INTR_STATE_NMI);
7491
7492         /*
7493          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7494          * here.., and there's no userspace involvement needed for PML.
7495          */
7496         return 1;
7497 }
7498
7499 static int handle_pcommit(struct kvm_vcpu *vcpu)
7500 {
7501         /* we never catch pcommit instruct for L1 guest. */
7502         WARN_ON(1);
7503         return 1;
7504 }
7505
7506 /*
7507  * The exit handlers return 1 if the exit was handled fully and guest execution
7508  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7509  * to be done to userspace and return 0.
7510  */
7511 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7512         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7513         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7514         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7515         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7516         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7517         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7518         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7519         [EXIT_REASON_CPUID]                   = handle_cpuid,
7520         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7521         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7522         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7523         [EXIT_REASON_HLT]                     = handle_halt,
7524         [EXIT_REASON_INVD]                    = handle_invd,
7525         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7526         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7527         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7528         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7529         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7530         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7531         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7532         [EXIT_REASON_VMREAD]                  = handle_vmread,
7533         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7534         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7535         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7536         [EXIT_REASON_VMON]                    = handle_vmon,
7537         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7538         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7539         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7540         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7541         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7542         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7543         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7544         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7545         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7546         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7547         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7548         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7549         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7550         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7551         [EXIT_REASON_INVEPT]                  = handle_invept,
7552         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7553         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7554         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7555         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7556         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7557 };
7558
7559 static const int kvm_vmx_max_exit_handlers =
7560         ARRAY_SIZE(kvm_vmx_exit_handlers);
7561
7562 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7563                                        struct vmcs12 *vmcs12)
7564 {
7565         unsigned long exit_qualification;
7566         gpa_t bitmap, last_bitmap;
7567         unsigned int port;
7568         int size;
7569         u8 b;
7570
7571         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7572                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7573
7574         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7575
7576         port = exit_qualification >> 16;
7577         size = (exit_qualification & 7) + 1;
7578
7579         last_bitmap = (gpa_t)-1;
7580         b = -1;
7581
7582         while (size > 0) {
7583                 if (port < 0x8000)
7584                         bitmap = vmcs12->io_bitmap_a;
7585                 else if (port < 0x10000)
7586                         bitmap = vmcs12->io_bitmap_b;
7587                 else
7588                         return true;
7589                 bitmap += (port & 0x7fff) / 8;
7590
7591                 if (last_bitmap != bitmap)
7592                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7593                                 return true;
7594                 if (b & (1 << (port & 7)))
7595                         return true;
7596
7597                 port++;
7598                 size--;
7599                 last_bitmap = bitmap;
7600         }
7601
7602         return false;
7603 }
7604
7605 /*
7606  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7607  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7608  * disinterest in the current event (read or write a specific MSR) by using an
7609  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7610  */
7611 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7612         struct vmcs12 *vmcs12, u32 exit_reason)
7613 {
7614         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7615         gpa_t bitmap;
7616
7617         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7618                 return true;
7619
7620         /*
7621          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7622          * for the four combinations of read/write and low/high MSR numbers.
7623          * First we need to figure out which of the four to use:
7624          */
7625         bitmap = vmcs12->msr_bitmap;
7626         if (exit_reason == EXIT_REASON_MSR_WRITE)
7627                 bitmap += 2048;
7628         if (msr_index >= 0xc0000000) {
7629                 msr_index -= 0xc0000000;
7630                 bitmap += 1024;
7631         }
7632
7633         /* Then read the msr_index'th bit from this bitmap: */
7634         if (msr_index < 1024*8) {
7635                 unsigned char b;
7636                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7637                         return true;
7638                 return 1 & (b >> (msr_index & 7));
7639         } else
7640                 return true; /* let L1 handle the wrong parameter */
7641 }
7642
7643 /*
7644  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7645  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7646  * intercept (via guest_host_mask etc.) the current event.
7647  */
7648 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7649         struct vmcs12 *vmcs12)
7650 {
7651         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7652         int cr = exit_qualification & 15;
7653         int reg = (exit_qualification >> 8) & 15;
7654         unsigned long val = kvm_register_readl(vcpu, reg);
7655
7656         switch ((exit_qualification >> 4) & 3) {
7657         case 0: /* mov to cr */
7658                 switch (cr) {
7659                 case 0:
7660                         if (vmcs12->cr0_guest_host_mask &
7661                             (val ^ vmcs12->cr0_read_shadow))
7662                                 return true;
7663                         break;
7664                 case 3:
7665                         if ((vmcs12->cr3_target_count >= 1 &&
7666                                         vmcs12->cr3_target_value0 == val) ||
7667                                 (vmcs12->cr3_target_count >= 2 &&
7668                                         vmcs12->cr3_target_value1 == val) ||
7669                                 (vmcs12->cr3_target_count >= 3 &&
7670                                         vmcs12->cr3_target_value2 == val) ||
7671                                 (vmcs12->cr3_target_count >= 4 &&
7672                                         vmcs12->cr3_target_value3 == val))
7673                                 return false;
7674                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7675                                 return true;
7676                         break;
7677                 case 4:
7678                         if (vmcs12->cr4_guest_host_mask &
7679                             (vmcs12->cr4_read_shadow ^ val))
7680                                 return true;
7681                         break;
7682                 case 8:
7683                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7684                                 return true;
7685                         break;
7686                 }
7687                 break;
7688         case 2: /* clts */
7689                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7690                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7691                         return true;
7692                 break;
7693         case 1: /* mov from cr */
7694                 switch (cr) {
7695                 case 3:
7696                         if (vmcs12->cpu_based_vm_exec_control &
7697                             CPU_BASED_CR3_STORE_EXITING)
7698                                 return true;
7699                         break;
7700                 case 8:
7701                         if (vmcs12->cpu_based_vm_exec_control &
7702                             CPU_BASED_CR8_STORE_EXITING)
7703                                 return true;
7704                         break;
7705                 }
7706                 break;
7707         case 3: /* lmsw */
7708                 /*
7709                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7710                  * cr0. Other attempted changes are ignored, with no exit.
7711                  */
7712                 if (vmcs12->cr0_guest_host_mask & 0xe &
7713                     (val ^ vmcs12->cr0_read_shadow))
7714                         return true;
7715                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7716                     !(vmcs12->cr0_read_shadow & 0x1) &&
7717                     (val & 0x1))
7718                         return true;
7719                 break;
7720         }
7721         return false;
7722 }
7723
7724 /*
7725  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7726  * should handle it ourselves in L0 (and then continue L2). Only call this
7727  * when in is_guest_mode (L2).
7728  */
7729 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7730 {
7731         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7732         struct vcpu_vmx *vmx = to_vmx(vcpu);
7733         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7734         u32 exit_reason = vmx->exit_reason;
7735
7736         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7737                                 vmcs_readl(EXIT_QUALIFICATION),
7738                                 vmx->idt_vectoring_info,
7739                                 intr_info,
7740                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7741                                 KVM_ISA_VMX);
7742
7743         if (vmx->nested.nested_run_pending)
7744                 return false;
7745
7746         if (unlikely(vmx->fail)) {
7747                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7748                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7749                 return true;
7750         }
7751
7752         switch (exit_reason) {
7753         case EXIT_REASON_EXCEPTION_NMI:
7754                 if (!is_exception(intr_info))
7755                         return false;
7756                 else if (is_page_fault(intr_info))
7757                         return enable_ept;
7758                 else if (is_no_device(intr_info) &&
7759                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7760                         return false;
7761                 else if (is_debug(intr_info) &&
7762                          vcpu->guest_debug &
7763                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7764                         return false;
7765                 else if (is_breakpoint(intr_info) &&
7766                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7767                         return false;
7768                 return vmcs12->exception_bitmap &
7769                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7770         case EXIT_REASON_EXTERNAL_INTERRUPT:
7771                 return false;
7772         case EXIT_REASON_TRIPLE_FAULT:
7773                 return true;
7774         case EXIT_REASON_PENDING_INTERRUPT:
7775                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7776         case EXIT_REASON_NMI_WINDOW:
7777                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7778         case EXIT_REASON_TASK_SWITCH:
7779                 return true;
7780         case EXIT_REASON_CPUID:
7781                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7782                         return false;
7783                 return true;
7784         case EXIT_REASON_HLT:
7785                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7786         case EXIT_REASON_INVD:
7787                 return true;
7788         case EXIT_REASON_INVLPG:
7789                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7790         case EXIT_REASON_RDPMC:
7791                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7792         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7793                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7794         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7795         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7796         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7797         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7798         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7799         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7800                 /*
7801                  * VMX instructions trap unconditionally. This allows L1 to
7802                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7803                  */
7804                 return true;
7805         case EXIT_REASON_CR_ACCESS:
7806                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7807         case EXIT_REASON_DR_ACCESS:
7808                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7809         case EXIT_REASON_IO_INSTRUCTION:
7810                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7811         case EXIT_REASON_MSR_READ:
7812         case EXIT_REASON_MSR_WRITE:
7813                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7814         case EXIT_REASON_INVALID_STATE:
7815                 return true;
7816         case EXIT_REASON_MWAIT_INSTRUCTION:
7817                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7818         case EXIT_REASON_MONITOR_TRAP_FLAG:
7819                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7820         case EXIT_REASON_MONITOR_INSTRUCTION:
7821                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7822         case EXIT_REASON_PAUSE_INSTRUCTION:
7823                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7824                         nested_cpu_has2(vmcs12,
7825                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7826         case EXIT_REASON_MCE_DURING_VMENTRY:
7827                 return false;
7828         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7829                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7830         case EXIT_REASON_APIC_ACCESS:
7831                 return nested_cpu_has2(vmcs12,
7832                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7833         case EXIT_REASON_APIC_WRITE:
7834         case EXIT_REASON_EOI_INDUCED:
7835                 /* apic_write and eoi_induced should exit unconditionally. */
7836                 return true;
7837         case EXIT_REASON_EPT_VIOLATION:
7838                 /*
7839                  * L0 always deals with the EPT violation. If nested EPT is
7840                  * used, and the nested mmu code discovers that the address is
7841                  * missing in the guest EPT table (EPT12), the EPT violation
7842                  * will be injected with nested_ept_inject_page_fault()
7843                  */
7844                 return false;
7845         case EXIT_REASON_EPT_MISCONFIG:
7846                 /*
7847                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7848                  * table (shadow on EPT) or a merged EPT table that L0 built
7849                  * (EPT on EPT). So any problems with the structure of the
7850                  * table is L0's fault.
7851                  */
7852                 return false;
7853         case EXIT_REASON_WBINVD:
7854                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7855         case EXIT_REASON_XSETBV:
7856                 return true;
7857         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7858                 /*
7859                  * This should never happen, since it is not possible to
7860                  * set XSS to a non-zero value---neither in L1 nor in L2.
7861                  * If if it were, XSS would have to be checked against
7862                  * the XSS exit bitmap in vmcs12.
7863                  */
7864                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7865         case EXIT_REASON_PCOMMIT:
7866                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7867         default:
7868                 return true;
7869         }
7870 }
7871
7872 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7873 {
7874         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7875         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7876 }
7877
7878 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7879 {
7880         struct page *pml_pg;
7881
7882         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7883         if (!pml_pg)
7884                 return -ENOMEM;
7885
7886         vmx->pml_pg = pml_pg;
7887
7888         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7889         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7890
7891         return 0;
7892 }
7893
7894 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7895 {
7896         if (vmx->pml_pg) {
7897                 __free_page(vmx->pml_pg);
7898                 vmx->pml_pg = NULL;
7899         }
7900 }
7901
7902 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7903 {
7904         struct vcpu_vmx *vmx = to_vmx(vcpu);
7905         u64 *pml_buf;
7906         u16 pml_idx;
7907
7908         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7909
7910         /* Do nothing if PML buffer is empty */
7911         if (pml_idx == (PML_ENTITY_NUM - 1))
7912                 return;
7913
7914         /* PML index always points to next available PML buffer entity */
7915         if (pml_idx >= PML_ENTITY_NUM)
7916                 pml_idx = 0;
7917         else
7918                 pml_idx++;
7919
7920         pml_buf = page_address(vmx->pml_pg);
7921         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7922                 u64 gpa;
7923
7924                 gpa = pml_buf[pml_idx];
7925                 WARN_ON(gpa & (PAGE_SIZE - 1));
7926                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7927         }
7928
7929         /* reset PML index */
7930         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7931 }
7932
7933 /*
7934  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7935  * Called before reporting dirty_bitmap to userspace.
7936  */
7937 static void kvm_flush_pml_buffers(struct kvm *kvm)
7938 {
7939         int i;
7940         struct kvm_vcpu *vcpu;
7941         /*
7942          * We only need to kick vcpu out of guest mode here, as PML buffer
7943          * is flushed at beginning of all VMEXITs, and it's obvious that only
7944          * vcpus running in guest are possible to have unflushed GPAs in PML
7945          * buffer.
7946          */
7947         kvm_for_each_vcpu(i, vcpu, kvm)
7948                 kvm_vcpu_kick(vcpu);
7949 }
7950
7951 static void vmx_dump_sel(char *name, uint32_t sel)
7952 {
7953         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7954                name, vmcs_read32(sel),
7955                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7956                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7957                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7958 }
7959
7960 static void vmx_dump_dtsel(char *name, uint32_t limit)
7961 {
7962         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7963                name, vmcs_read32(limit),
7964                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7965 }
7966
7967 static void dump_vmcs(void)
7968 {
7969         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7970         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7971         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7972         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7973         u32 secondary_exec_control = 0;
7974         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7975         u64 efer = vmcs_read64(GUEST_IA32_EFER);
7976         int i, n;
7977
7978         if (cpu_has_secondary_exec_ctrls())
7979                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7980
7981         pr_err("*** Guest State ***\n");
7982         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7983                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7984                vmcs_readl(CR0_GUEST_HOST_MASK));
7985         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7986                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7987         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7988         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7989             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7990         {
7991                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
7992                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
7993                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
7994                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
7995         }
7996         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7997                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7998         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7999                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8000         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8001                vmcs_readl(GUEST_SYSENTER_ESP),
8002                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8003         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8004         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8005         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8006         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8007         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8008         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8009         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8010         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8011         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8012         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8013         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8014             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8015                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8016                        efer, vmcs_read64(GUEST_IA32_PAT));
8017         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8018                vmcs_read64(GUEST_IA32_DEBUGCTL),
8019                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8020         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8021                 pr_err("PerfGlobCtl = 0x%016llx\n",
8022                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8023         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8024                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8025         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8026                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8027                vmcs_read32(GUEST_ACTIVITY_STATE));
8028         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8029                 pr_err("InterruptStatus = %04x\n",
8030                        vmcs_read16(GUEST_INTR_STATUS));
8031
8032         pr_err("*** Host State ***\n");
8033         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8034                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8035         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8036                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8037                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8038                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8039                vmcs_read16(HOST_TR_SELECTOR));
8040         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8041                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8042                vmcs_readl(HOST_TR_BASE));
8043         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8044                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8045         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8046                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8047                vmcs_readl(HOST_CR4));
8048         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8049                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8050                vmcs_read32(HOST_IA32_SYSENTER_CS),
8051                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8052         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8053                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8054                        vmcs_read64(HOST_IA32_EFER),
8055                        vmcs_read64(HOST_IA32_PAT));
8056         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8057                 pr_err("PerfGlobCtl = 0x%016llx\n",
8058                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8059
8060         pr_err("*** Control State ***\n");
8061         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8062                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8063         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8064         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8065                vmcs_read32(EXCEPTION_BITMAP),
8066                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8067                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8068         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8069                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8070                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8071                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8072         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8073                vmcs_read32(VM_EXIT_INTR_INFO),
8074                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8075                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8076         pr_err("        reason=%08x qualification=%016lx\n",
8077                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8078         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8079                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8080                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8081         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8082         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8083                 pr_err("TSC Multiplier = 0x%016llx\n",
8084                        vmcs_read64(TSC_MULTIPLIER));
8085         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8086                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8087         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8088                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8089         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8090                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8091         n = vmcs_read32(CR3_TARGET_COUNT);
8092         for (i = 0; i + 1 < n; i += 4)
8093                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8094                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8095                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8096         if (i < n)
8097                 pr_err("CR3 target%u=%016lx\n",
8098                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8099         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8100                 pr_err("PLE Gap=%08x Window=%08x\n",
8101                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8102         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8103                 pr_err("Virtual processor ID = 0x%04x\n",
8104                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8105 }
8106
8107 /*
8108  * The guest has exited.  See if we can fix it or if we need userspace
8109  * assistance.
8110  */
8111 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8112 {
8113         struct vcpu_vmx *vmx = to_vmx(vcpu);
8114         u32 exit_reason = vmx->exit_reason;
8115         u32 vectoring_info = vmx->idt_vectoring_info;
8116
8117         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8118
8119         /*
8120          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8121          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8122          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8123          * mode as if vcpus is in root mode, the PML buffer must has been
8124          * flushed already.
8125          */
8126         if (enable_pml)
8127                 vmx_flush_pml_buffer(vcpu);
8128
8129         /* If guest state is invalid, start emulating */
8130         if (vmx->emulation_required)
8131                 return handle_invalid_guest_state(vcpu);
8132
8133         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8134                 nested_vmx_vmexit(vcpu, exit_reason,
8135                                   vmcs_read32(VM_EXIT_INTR_INFO),
8136                                   vmcs_readl(EXIT_QUALIFICATION));
8137                 return 1;
8138         }
8139
8140         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8141                 dump_vmcs();
8142                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8143                 vcpu->run->fail_entry.hardware_entry_failure_reason
8144                         = exit_reason;
8145                 return 0;
8146         }
8147
8148         if (unlikely(vmx->fail)) {
8149                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8150                 vcpu->run->fail_entry.hardware_entry_failure_reason
8151                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8152                 return 0;
8153         }
8154
8155         /*
8156          * Note:
8157          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8158          * delivery event since it indicates guest is accessing MMIO.
8159          * The vm-exit can be triggered again after return to guest that
8160          * will cause infinite loop.
8161          */
8162         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8163                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8164                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8165                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8166                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8167                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8168                 vcpu->run->internal.ndata = 2;
8169                 vcpu->run->internal.data[0] = vectoring_info;
8170                 vcpu->run->internal.data[1] = exit_reason;
8171                 return 0;
8172         }
8173
8174         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8175             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8176                                         get_vmcs12(vcpu))))) {
8177                 if (vmx_interrupt_allowed(vcpu)) {
8178                         vmx->soft_vnmi_blocked = 0;
8179                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8180                            vcpu->arch.nmi_pending) {
8181                         /*
8182                          * This CPU don't support us in finding the end of an
8183                          * NMI-blocked window if the guest runs with IRQs
8184                          * disabled. So we pull the trigger after 1 s of
8185                          * futile waiting, but inform the user about this.
8186                          */
8187                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8188                                "state on VCPU %d after 1 s timeout\n",
8189                                __func__, vcpu->vcpu_id);
8190                         vmx->soft_vnmi_blocked = 0;
8191                 }
8192         }
8193
8194         if (exit_reason < kvm_vmx_max_exit_handlers
8195             && kvm_vmx_exit_handlers[exit_reason])
8196                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8197         else {
8198                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8199                 kvm_queue_exception(vcpu, UD_VECTOR);
8200                 return 1;
8201         }
8202 }
8203
8204 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8205 {
8206         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8207
8208         if (is_guest_mode(vcpu) &&
8209                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8210                 return;
8211
8212         if (irr == -1 || tpr < irr) {
8213                 vmcs_write32(TPR_THRESHOLD, 0);
8214                 return;
8215         }
8216
8217         vmcs_write32(TPR_THRESHOLD, irr);
8218 }
8219
8220 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8221 {
8222         u32 sec_exec_control;
8223
8224         /*
8225          * There is not point to enable virtualize x2apic without enable
8226          * apicv
8227          */
8228         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8229                                 !kvm_vcpu_apicv_active(vcpu))
8230                 return;
8231
8232         if (!cpu_need_tpr_shadow(vcpu))
8233                 return;
8234
8235         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8236
8237         if (set) {
8238                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8239                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8240         } else {
8241                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8242                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8243         }
8244         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8245
8246         vmx_set_msr_bitmap(vcpu);
8247 }
8248
8249 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8250 {
8251         struct vcpu_vmx *vmx = to_vmx(vcpu);
8252
8253         /*
8254          * Currently we do not handle the nested case where L2 has an
8255          * APIC access page of its own; that page is still pinned.
8256          * Hence, we skip the case where the VCPU is in guest mode _and_
8257          * L1 prepared an APIC access page for L2.
8258          *
8259          * For the case where L1 and L2 share the same APIC access page
8260          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8261          * in the vmcs12), this function will only update either the vmcs01
8262          * or the vmcs02.  If the former, the vmcs02 will be updated by
8263          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8264          * the next L2->L1 exit.
8265          */
8266         if (!is_guest_mode(vcpu) ||
8267             !nested_cpu_has2(vmx->nested.current_vmcs12,
8268                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8269                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8270 }
8271
8272 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8273 {
8274         u16 status;
8275         u8 old;
8276
8277         if (isr == -1)
8278                 isr = 0;
8279
8280         status = vmcs_read16(GUEST_INTR_STATUS);
8281         old = status >> 8;
8282         if (isr != old) {
8283                 status &= 0xff;
8284                 status |= isr << 8;
8285                 vmcs_write16(GUEST_INTR_STATUS, status);
8286         }
8287 }
8288
8289 static void vmx_set_rvi(int vector)
8290 {
8291         u16 status;
8292         u8 old;
8293
8294         if (vector == -1)
8295                 vector = 0;
8296
8297         status = vmcs_read16(GUEST_INTR_STATUS);
8298         old = (u8)status & 0xff;
8299         if ((u8)vector != old) {
8300                 status &= ~0xff;
8301                 status |= (u8)vector;
8302                 vmcs_write16(GUEST_INTR_STATUS, status);
8303         }
8304 }
8305
8306 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8307 {
8308         if (!is_guest_mode(vcpu)) {
8309                 vmx_set_rvi(max_irr);
8310                 return;
8311         }
8312
8313         if (max_irr == -1)
8314                 return;
8315
8316         /*
8317          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8318          * handles it.
8319          */
8320         if (nested_exit_on_intr(vcpu))
8321                 return;
8322
8323         /*
8324          * Else, fall back to pre-APICv interrupt injection since L2
8325          * is run without virtual interrupt delivery.
8326          */
8327         if (!kvm_event_needs_reinjection(vcpu) &&
8328             vmx_interrupt_allowed(vcpu)) {
8329                 kvm_queue_interrupt(vcpu, max_irr, false);
8330                 vmx_inject_irq(vcpu);
8331         }
8332 }
8333
8334 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8335 {
8336         if (!kvm_vcpu_apicv_active(vcpu))
8337                 return;
8338
8339         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8340         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8341         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8342         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8343 }
8344
8345 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8346 {
8347         u32 exit_intr_info;
8348
8349         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8350               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8351                 return;
8352
8353         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8354         exit_intr_info = vmx->exit_intr_info;
8355
8356         /* Handle machine checks before interrupts are enabled */
8357         if (is_machine_check(exit_intr_info))
8358                 kvm_machine_check();
8359
8360         /* We need to handle NMIs before interrupts are enabled */
8361         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8362             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8363                 kvm_before_handle_nmi(&vmx->vcpu);
8364                 asm("int $2");
8365                 kvm_after_handle_nmi(&vmx->vcpu);
8366         }
8367 }
8368
8369 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8370 {
8371         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8372         register void *__sp asm(_ASM_SP);
8373
8374         /*
8375          * If external interrupt exists, IF bit is set in rflags/eflags on the
8376          * interrupt stack frame, and interrupt will be enabled on a return
8377          * from interrupt handler.
8378          */
8379         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8380                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8381                 unsigned int vector;
8382                 unsigned long entry;
8383                 gate_desc *desc;
8384                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8385 #ifdef CONFIG_X86_64
8386                 unsigned long tmp;
8387 #endif
8388
8389                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8390                 desc = (gate_desc *)vmx->host_idt_base + vector;
8391                 entry = gate_offset(*desc);
8392                 asm volatile(
8393 #ifdef CONFIG_X86_64
8394                         "mov %%" _ASM_SP ", %[sp]\n\t"
8395                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8396                         "push $%c[ss]\n\t"
8397                         "push %[sp]\n\t"
8398 #endif
8399                         "pushf\n\t"
8400                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8401                         __ASM_SIZE(push) " $%c[cs]\n\t"
8402                         "call *%[entry]\n\t"
8403                         :
8404 #ifdef CONFIG_X86_64
8405                         [sp]"=&r"(tmp),
8406 #endif
8407                         "+r"(__sp)
8408                         :
8409                         [entry]"r"(entry),
8410                         [ss]"i"(__KERNEL_DS),
8411                         [cs]"i"(__KERNEL_CS)
8412                         );
8413         } else
8414                 local_irq_enable();
8415 }
8416
8417 static bool vmx_has_high_real_mode_segbase(void)
8418 {
8419         return enable_unrestricted_guest || emulate_invalid_guest_state;
8420 }
8421
8422 static bool vmx_mpx_supported(void)
8423 {
8424         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8425                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8426 }
8427
8428 static bool vmx_xsaves_supported(void)
8429 {
8430         return vmcs_config.cpu_based_2nd_exec_ctrl &
8431                 SECONDARY_EXEC_XSAVES;
8432 }
8433
8434 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8435 {
8436         u32 exit_intr_info;
8437         bool unblock_nmi;
8438         u8 vector;
8439         bool idtv_info_valid;
8440
8441         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8442
8443         if (cpu_has_virtual_nmis()) {
8444                 if (vmx->nmi_known_unmasked)
8445                         return;
8446                 /*
8447                  * Can't use vmx->exit_intr_info since we're not sure what
8448                  * the exit reason is.
8449                  */
8450                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8451                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8452                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8453                 /*
8454                  * SDM 3: 27.7.1.2 (September 2008)
8455                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8456                  * a guest IRET fault.
8457                  * SDM 3: 23.2.2 (September 2008)
8458                  * Bit 12 is undefined in any of the following cases:
8459                  *  If the VM exit sets the valid bit in the IDT-vectoring
8460                  *   information field.
8461                  *  If the VM exit is due to a double fault.
8462                  */
8463                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8464                     vector != DF_VECTOR && !idtv_info_valid)
8465                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8466                                       GUEST_INTR_STATE_NMI);
8467                 else
8468                         vmx->nmi_known_unmasked =
8469                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8470                                   & GUEST_INTR_STATE_NMI);
8471         } else if (unlikely(vmx->soft_vnmi_blocked))
8472                 vmx->vnmi_blocked_time +=
8473                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8474 }
8475
8476 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8477                                       u32 idt_vectoring_info,
8478                                       int instr_len_field,
8479                                       int error_code_field)
8480 {
8481         u8 vector;
8482         int type;
8483         bool idtv_info_valid;
8484
8485         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8486
8487         vcpu->arch.nmi_injected = false;
8488         kvm_clear_exception_queue(vcpu);
8489         kvm_clear_interrupt_queue(vcpu);
8490
8491         if (!idtv_info_valid)
8492                 return;
8493
8494         kvm_make_request(KVM_REQ_EVENT, vcpu);
8495
8496         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8497         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8498
8499         switch (type) {
8500         case INTR_TYPE_NMI_INTR:
8501                 vcpu->arch.nmi_injected = true;
8502                 /*
8503                  * SDM 3: 27.7.1.2 (September 2008)
8504                  * Clear bit "block by NMI" before VM entry if a NMI
8505                  * delivery faulted.
8506                  */
8507                 vmx_set_nmi_mask(vcpu, false);
8508                 break;
8509         case INTR_TYPE_SOFT_EXCEPTION:
8510                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8511                 /* fall through */
8512         case INTR_TYPE_HARD_EXCEPTION:
8513                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8514                         u32 err = vmcs_read32(error_code_field);
8515                         kvm_requeue_exception_e(vcpu, vector, err);
8516                 } else
8517                         kvm_requeue_exception(vcpu, vector);
8518                 break;
8519         case INTR_TYPE_SOFT_INTR:
8520                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8521                 /* fall through */
8522         case INTR_TYPE_EXT_INTR:
8523                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8524                 break;
8525         default:
8526                 break;
8527         }
8528 }
8529
8530 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8531 {
8532         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8533                                   VM_EXIT_INSTRUCTION_LEN,
8534                                   IDT_VECTORING_ERROR_CODE);
8535 }
8536
8537 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8538 {
8539         __vmx_complete_interrupts(vcpu,
8540                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8541                                   VM_ENTRY_INSTRUCTION_LEN,
8542                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8543
8544         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8545 }
8546
8547 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8548 {
8549         int i, nr_msrs;
8550         struct perf_guest_switch_msr *msrs;
8551
8552         msrs = perf_guest_get_msrs(&nr_msrs);
8553
8554         if (!msrs)
8555                 return;
8556
8557         for (i = 0; i < nr_msrs; i++)
8558                 if (msrs[i].host == msrs[i].guest)
8559                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8560                 else
8561                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8562                                         msrs[i].host);
8563 }
8564
8565 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8566 {
8567         struct vcpu_vmx *vmx = to_vmx(vcpu);
8568         unsigned long debugctlmsr, cr4;
8569
8570         /* Record the guest's net vcpu time for enforced NMI injections. */
8571         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8572                 vmx->entry_time = ktime_get();
8573
8574         /* Don't enter VMX if guest state is invalid, let the exit handler
8575            start emulation until we arrive back to a valid state */
8576         if (vmx->emulation_required)
8577                 return;
8578
8579         if (vmx->ple_window_dirty) {
8580                 vmx->ple_window_dirty = false;
8581                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8582         }
8583
8584         if (vmx->nested.sync_shadow_vmcs) {
8585                 copy_vmcs12_to_shadow(vmx);
8586                 vmx->nested.sync_shadow_vmcs = false;
8587         }
8588
8589         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8590                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8591         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8592                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8593
8594         cr4 = cr4_read_shadow();
8595         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8596                 vmcs_writel(HOST_CR4, cr4);
8597                 vmx->host_state.vmcs_host_cr4 = cr4;
8598         }
8599
8600         /* When single-stepping over STI and MOV SS, we must clear the
8601          * corresponding interruptibility bits in the guest state. Otherwise
8602          * vmentry fails as it then expects bit 14 (BS) in pending debug
8603          * exceptions being set, but that's not correct for the guest debugging
8604          * case. */
8605         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8606                 vmx_set_interrupt_shadow(vcpu, 0);
8607
8608         atomic_switch_perf_msrs(vmx);
8609         debugctlmsr = get_debugctlmsr();
8610
8611         vmx->__launched = vmx->loaded_vmcs->launched;
8612         asm(
8613                 /* Store host registers */
8614                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8615                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8616                 "push %%" _ASM_CX " \n\t"
8617                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8618                 "je 1f \n\t"
8619                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8620                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8621                 "1: \n\t"
8622                 /* Reload cr2 if changed */
8623                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8624                 "mov %%cr2, %%" _ASM_DX " \n\t"
8625                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8626                 "je 2f \n\t"
8627                 "mov %%" _ASM_AX", %%cr2 \n\t"
8628                 "2: \n\t"
8629                 /* Check if vmlaunch of vmresume is needed */
8630                 "cmpl $0, %c[launched](%0) \n\t"
8631                 /* Load guest registers.  Don't clobber flags. */
8632                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8633                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8634                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8635                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8636                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8637                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8638 #ifdef CONFIG_X86_64
8639                 "mov %c[r8](%0),  %%r8  \n\t"
8640                 "mov %c[r9](%0),  %%r9  \n\t"
8641                 "mov %c[r10](%0), %%r10 \n\t"
8642                 "mov %c[r11](%0), %%r11 \n\t"
8643                 "mov %c[r12](%0), %%r12 \n\t"
8644                 "mov %c[r13](%0), %%r13 \n\t"
8645                 "mov %c[r14](%0), %%r14 \n\t"
8646                 "mov %c[r15](%0), %%r15 \n\t"
8647 #endif
8648                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8649
8650                 /* Enter guest mode */
8651                 "jne 1f \n\t"
8652                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8653                 "jmp 2f \n\t"
8654                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8655                 "2: "
8656                 /* Save guest registers, load host registers, keep flags */
8657                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8658                 "pop %0 \n\t"
8659                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8660                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8661                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8662                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8663                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8664                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8665                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8666 #ifdef CONFIG_X86_64
8667                 "mov %%r8,  %c[r8](%0) \n\t"
8668                 "mov %%r9,  %c[r9](%0) \n\t"
8669                 "mov %%r10, %c[r10](%0) \n\t"
8670                 "mov %%r11, %c[r11](%0) \n\t"
8671                 "mov %%r12, %c[r12](%0) \n\t"
8672                 "mov %%r13, %c[r13](%0) \n\t"
8673                 "mov %%r14, %c[r14](%0) \n\t"
8674                 "mov %%r15, %c[r15](%0) \n\t"
8675 #endif
8676                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8677                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8678
8679                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8680                 "setbe %c[fail](%0) \n\t"
8681                 ".pushsection .rodata \n\t"
8682                 ".global vmx_return \n\t"
8683                 "vmx_return: " _ASM_PTR " 2b \n\t"
8684                 ".popsection"
8685               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8686                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8687                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8688                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8689                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8690                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8691                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8692                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8693                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8694                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8695                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8696 #ifdef CONFIG_X86_64
8697                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8698                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8699                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8700                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8701                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8702                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8703                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8704                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8705 #endif
8706                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8707                 [wordsize]"i"(sizeof(ulong))
8708               : "cc", "memory"
8709 #ifdef CONFIG_X86_64
8710                 , "rax", "rbx", "rdi", "rsi"
8711                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8712 #else
8713                 , "eax", "ebx", "edi", "esi"
8714 #endif
8715               );
8716
8717         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8718         if (debugctlmsr)
8719                 update_debugctlmsr(debugctlmsr);
8720
8721 #ifndef CONFIG_X86_64
8722         /*
8723          * The sysexit path does not restore ds/es, so we must set them to
8724          * a reasonable value ourselves.
8725          *
8726          * We can't defer this to vmx_load_host_state() since that function
8727          * may be executed in interrupt context, which saves and restore segments
8728          * around it, nullifying its effect.
8729          */
8730         loadsegment(ds, __USER_DS);
8731         loadsegment(es, __USER_DS);
8732 #endif
8733
8734         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8735                                   | (1 << VCPU_EXREG_RFLAGS)
8736                                   | (1 << VCPU_EXREG_PDPTR)
8737                                   | (1 << VCPU_EXREG_SEGMENTS)
8738                                   | (1 << VCPU_EXREG_CR3));
8739         vcpu->arch.regs_dirty = 0;
8740
8741         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8742
8743         vmx->loaded_vmcs->launched = 1;
8744
8745         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8746
8747         /*
8748          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8749          * we did not inject a still-pending event to L1 now because of
8750          * nested_run_pending, we need to re-enable this bit.
8751          */
8752         if (vmx->nested.nested_run_pending)
8753                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8754
8755         vmx->nested.nested_run_pending = 0;
8756
8757         vmx_complete_atomic_exit(vmx);
8758         vmx_recover_nmi_blocking(vmx);
8759         vmx_complete_interrupts(vmx);
8760 }
8761
8762 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8763 {
8764         struct vcpu_vmx *vmx = to_vmx(vcpu);
8765         int cpu;
8766
8767         if (vmx->loaded_vmcs == &vmx->vmcs01)
8768                 return;
8769
8770         cpu = get_cpu();
8771         vmx->loaded_vmcs = &vmx->vmcs01;
8772         vmx_vcpu_put(vcpu);
8773         vmx_vcpu_load(vcpu, cpu);
8774         vcpu->cpu = cpu;
8775         put_cpu();
8776 }
8777
8778 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8779 {
8780         struct vcpu_vmx *vmx = to_vmx(vcpu);
8781
8782         if (enable_pml)
8783                 vmx_destroy_pml_buffer(vmx);
8784         free_vpid(vmx->vpid);
8785         leave_guest_mode(vcpu);
8786         vmx_load_vmcs01(vcpu);
8787         free_nested(vmx);
8788         free_loaded_vmcs(vmx->loaded_vmcs);
8789         kfree(vmx->guest_msrs);
8790         kvm_vcpu_uninit(vcpu);
8791         kmem_cache_free(kvm_vcpu_cache, vmx);
8792 }
8793
8794 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8795 {
8796         int err;
8797         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8798         int cpu;
8799
8800         if (!vmx)
8801                 return ERR_PTR(-ENOMEM);
8802
8803         vmx->vpid = allocate_vpid();
8804
8805         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8806         if (err)
8807                 goto free_vcpu;
8808
8809         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8810         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8811                      > PAGE_SIZE);
8812
8813         err = -ENOMEM;
8814         if (!vmx->guest_msrs) {
8815                 goto uninit_vcpu;
8816         }
8817
8818         vmx->loaded_vmcs = &vmx->vmcs01;
8819         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8820         if (!vmx->loaded_vmcs->vmcs)
8821                 goto free_msrs;
8822         if (!vmm_exclusive)
8823                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8824         loaded_vmcs_init(vmx->loaded_vmcs);
8825         if (!vmm_exclusive)
8826                 kvm_cpu_vmxoff();
8827
8828         cpu = get_cpu();
8829         vmx_vcpu_load(&vmx->vcpu, cpu);
8830         vmx->vcpu.cpu = cpu;
8831         err = vmx_vcpu_setup(vmx);
8832         vmx_vcpu_put(&vmx->vcpu);
8833         put_cpu();
8834         if (err)
8835                 goto free_vmcs;
8836         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8837                 err = alloc_apic_access_page(kvm);
8838                 if (err)
8839                         goto free_vmcs;
8840         }
8841
8842         if (enable_ept) {
8843                 if (!kvm->arch.ept_identity_map_addr)
8844                         kvm->arch.ept_identity_map_addr =
8845                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8846                 err = init_rmode_identity_map(kvm);
8847                 if (err)
8848                         goto free_vmcs;
8849         }
8850
8851         if (nested) {
8852                 nested_vmx_setup_ctls_msrs(vmx);
8853                 vmx->nested.vpid02 = allocate_vpid();
8854         }
8855
8856         vmx->nested.posted_intr_nv = -1;
8857         vmx->nested.current_vmptr = -1ull;
8858         vmx->nested.current_vmcs12 = NULL;
8859
8860         /*
8861          * If PML is turned on, failure on enabling PML just results in failure
8862          * of creating the vcpu, therefore we can simplify PML logic (by
8863          * avoiding dealing with cases, such as enabling PML partially on vcpus
8864          * for the guest, etc.
8865          */
8866         if (enable_pml) {
8867                 err = vmx_create_pml_buffer(vmx);
8868                 if (err)
8869                         goto free_vmcs;
8870         }
8871
8872         return &vmx->vcpu;
8873
8874 free_vmcs:
8875         free_vpid(vmx->nested.vpid02);
8876         free_loaded_vmcs(vmx->loaded_vmcs);
8877 free_msrs:
8878         kfree(vmx->guest_msrs);
8879 uninit_vcpu:
8880         kvm_vcpu_uninit(&vmx->vcpu);
8881 free_vcpu:
8882         free_vpid(vmx->vpid);
8883         kmem_cache_free(kvm_vcpu_cache, vmx);
8884         return ERR_PTR(err);
8885 }
8886
8887 static void __init vmx_check_processor_compat(void *rtn)
8888 {
8889         struct vmcs_config vmcs_conf;
8890
8891         *(int *)rtn = 0;
8892         if (setup_vmcs_config(&vmcs_conf) < 0)
8893                 *(int *)rtn = -EIO;
8894         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8895                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8896                                 smp_processor_id());
8897                 *(int *)rtn = -EIO;
8898         }
8899 }
8900
8901 static int get_ept_level(void)
8902 {
8903         return VMX_EPT_DEFAULT_GAW + 1;
8904 }
8905
8906 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8907 {
8908         u8 cache;
8909         u64 ipat = 0;
8910
8911         /* For VT-d and EPT combination
8912          * 1. MMIO: always map as UC
8913          * 2. EPT with VT-d:
8914          *   a. VT-d without snooping control feature: can't guarantee the
8915          *      result, try to trust guest.
8916          *   b. VT-d with snooping control feature: snooping control feature of
8917          *      VT-d engine can guarantee the cache correctness. Just set it
8918          *      to WB to keep consistent with host. So the same as item 3.
8919          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8920          *    consistent with host MTRR
8921          */
8922         if (is_mmio) {
8923                 cache = MTRR_TYPE_UNCACHABLE;
8924                 goto exit;
8925         }
8926
8927         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8928                 ipat = VMX_EPT_IPAT_BIT;
8929                 cache = MTRR_TYPE_WRBACK;
8930                 goto exit;
8931         }
8932
8933         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8934                 ipat = VMX_EPT_IPAT_BIT;
8935                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8936                         cache = MTRR_TYPE_WRBACK;
8937                 else
8938                         cache = MTRR_TYPE_UNCACHABLE;
8939                 goto exit;
8940         }
8941
8942         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8943
8944 exit:
8945         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8946 }
8947
8948 static int vmx_get_lpage_level(void)
8949 {
8950         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8951                 return PT_DIRECTORY_LEVEL;
8952         else
8953                 /* For shadow and EPT supported 1GB page */
8954                 return PT_PDPE_LEVEL;
8955 }
8956
8957 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8958 {
8959         /*
8960          * These bits in the secondary execution controls field
8961          * are dynamic, the others are mostly based on the hypervisor
8962          * architecture and the guest's CPUID.  Do not touch the
8963          * dynamic bits.
8964          */
8965         u32 mask =
8966                 SECONDARY_EXEC_SHADOW_VMCS |
8967                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8968                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8969
8970         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8971
8972         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8973                      (new_ctl & ~mask) | (cur_ctl & mask));
8974 }
8975
8976 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8977 {
8978         struct kvm_cpuid_entry2 *best;
8979         struct vcpu_vmx *vmx = to_vmx(vcpu);
8980         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8981
8982         if (vmx_rdtscp_supported()) {
8983                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8984                 if (!rdtscp_enabled)
8985                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8986
8987                 if (nested) {
8988                         if (rdtscp_enabled)
8989                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8990                                         SECONDARY_EXEC_RDTSCP;
8991                         else
8992                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8993                                         ~SECONDARY_EXEC_RDTSCP;
8994                 }
8995         }
8996
8997         /* Exposing INVPCID only when PCID is exposed */
8998         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8999         if (vmx_invpcid_supported() &&
9000             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9001             !guest_cpuid_has_pcid(vcpu))) {
9002                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9003
9004                 if (best)
9005                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9006         }
9007
9008         if (cpu_has_secondary_exec_ctrls())
9009                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9010
9011         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9012                 if (guest_cpuid_has_pcommit(vcpu))
9013                         vmx->nested.nested_vmx_secondary_ctls_high |=
9014                                 SECONDARY_EXEC_PCOMMIT;
9015                 else
9016                         vmx->nested.nested_vmx_secondary_ctls_high &=
9017                                 ~SECONDARY_EXEC_PCOMMIT;
9018         }
9019 }
9020
9021 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9022 {
9023         if (func == 1 && nested)
9024                 entry->ecx |= bit(X86_FEATURE_VMX);
9025 }
9026
9027 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9028                 struct x86_exception *fault)
9029 {
9030         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9031         u32 exit_reason;
9032
9033         if (fault->error_code & PFERR_RSVD_MASK)
9034                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9035         else
9036                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9037         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9038         vmcs12->guest_physical_address = fault->address;
9039 }
9040
9041 /* Callbacks for nested_ept_init_mmu_context: */
9042
9043 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9044 {
9045         /* return the page table to be shadowed - in our case, EPT12 */
9046         return get_vmcs12(vcpu)->ept_pointer;
9047 }
9048
9049 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9050 {
9051         WARN_ON(mmu_is_nested(vcpu));
9052         kvm_init_shadow_ept_mmu(vcpu,
9053                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9054                         VMX_EPT_EXECUTE_ONLY_BIT);
9055         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9056         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9057         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9058
9059         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9060 }
9061
9062 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9063 {
9064         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9065 }
9066
9067 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9068                                             u16 error_code)
9069 {
9070         bool inequality, bit;
9071
9072         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9073         inequality =
9074                 (error_code & vmcs12->page_fault_error_code_mask) !=
9075                  vmcs12->page_fault_error_code_match;
9076         return inequality ^ bit;
9077 }
9078
9079 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9080                 struct x86_exception *fault)
9081 {
9082         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9083
9084         WARN_ON(!is_guest_mode(vcpu));
9085
9086         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9087                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9088                                   vmcs_read32(VM_EXIT_INTR_INFO),
9089                                   vmcs_readl(EXIT_QUALIFICATION));
9090         else
9091                 kvm_inject_page_fault(vcpu, fault);
9092 }
9093
9094 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9095                                         struct vmcs12 *vmcs12)
9096 {
9097         struct vcpu_vmx *vmx = to_vmx(vcpu);
9098         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9099
9100         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9101                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9102                     vmcs12->apic_access_addr >> maxphyaddr)
9103                         return false;
9104
9105                 /*
9106                  * Translate L1 physical address to host physical
9107                  * address for vmcs02. Keep the page pinned, so this
9108                  * physical address remains valid. We keep a reference
9109                  * to it so we can release it later.
9110                  */
9111                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9112                         nested_release_page(vmx->nested.apic_access_page);
9113                 vmx->nested.apic_access_page =
9114                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9115         }
9116
9117         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9118                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9119                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9120                         return false;
9121
9122                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9123                         nested_release_page(vmx->nested.virtual_apic_page);
9124                 vmx->nested.virtual_apic_page =
9125                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9126
9127                 /*
9128                  * Failing the vm entry is _not_ what the processor does
9129                  * but it's basically the only possibility we have.
9130                  * We could still enter the guest if CR8 load exits are
9131                  * enabled, CR8 store exits are enabled, and virtualize APIC
9132                  * access is disabled; in this case the processor would never
9133                  * use the TPR shadow and we could simply clear the bit from
9134                  * the execution control.  But such a configuration is useless,
9135                  * so let's keep the code simple.
9136                  */
9137                 if (!vmx->nested.virtual_apic_page)
9138                         return false;
9139         }
9140
9141         if (nested_cpu_has_posted_intr(vmcs12)) {
9142                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9143                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9144                         return false;
9145
9146                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9147                         kunmap(vmx->nested.pi_desc_page);
9148                         nested_release_page(vmx->nested.pi_desc_page);
9149                 }
9150                 vmx->nested.pi_desc_page =
9151                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9152                 if (!vmx->nested.pi_desc_page)
9153                         return false;
9154
9155                 vmx->nested.pi_desc =
9156                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9157                 if (!vmx->nested.pi_desc) {
9158                         nested_release_page_clean(vmx->nested.pi_desc_page);
9159                         return false;
9160                 }
9161                 vmx->nested.pi_desc =
9162                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9163                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9164                         (PAGE_SIZE - 1)));
9165         }
9166
9167         return true;
9168 }
9169
9170 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9171 {
9172         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9173         struct vcpu_vmx *vmx = to_vmx(vcpu);
9174
9175         if (vcpu->arch.virtual_tsc_khz == 0)
9176                 return;
9177
9178         /* Make sure short timeouts reliably trigger an immediate vmexit.
9179          * hrtimer_start does not guarantee this. */
9180         if (preemption_timeout <= 1) {
9181                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9182                 return;
9183         }
9184
9185         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9186         preemption_timeout *= 1000000;
9187         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9188         hrtimer_start(&vmx->nested.preemption_timer,
9189                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9190 }
9191
9192 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9193                                                 struct vmcs12 *vmcs12)
9194 {
9195         int maxphyaddr;
9196         u64 addr;
9197
9198         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9199                 return 0;
9200
9201         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9202                 WARN_ON(1);
9203                 return -EINVAL;
9204         }
9205         maxphyaddr = cpuid_maxphyaddr(vcpu);
9206
9207         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9208            ((addr + PAGE_SIZE) >> maxphyaddr))
9209                 return -EINVAL;
9210
9211         return 0;
9212 }
9213
9214 /*
9215  * Merge L0's and L1's MSR bitmap, return false to indicate that
9216  * we do not use the hardware.
9217  */
9218 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9219                                                struct vmcs12 *vmcs12)
9220 {
9221         int msr;
9222         struct page *page;
9223         unsigned long *msr_bitmap;
9224
9225         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9226                 return false;
9227
9228         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9229         if (!page) {
9230                 WARN_ON(1);
9231                 return false;
9232         }
9233         msr_bitmap = (unsigned long *)kmap(page);
9234         if (!msr_bitmap) {
9235                 nested_release_page_clean(page);
9236                 WARN_ON(1);
9237                 return false;
9238         }
9239
9240         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9241                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9242                         for (msr = 0x800; msr <= 0x8ff; msr++)
9243                                 nested_vmx_disable_intercept_for_msr(
9244                                         msr_bitmap,
9245                                         vmx_msr_bitmap_nested,
9246                                         msr, MSR_TYPE_R);
9247                 /* TPR is allowed */
9248                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9249                                 vmx_msr_bitmap_nested,
9250                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9251                                 MSR_TYPE_R | MSR_TYPE_W);
9252                 if (nested_cpu_has_vid(vmcs12)) {
9253                         /* EOI and self-IPI are allowed */
9254                         nested_vmx_disable_intercept_for_msr(
9255                                 msr_bitmap,
9256                                 vmx_msr_bitmap_nested,
9257                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9258                                 MSR_TYPE_W);
9259                         nested_vmx_disable_intercept_for_msr(
9260                                 msr_bitmap,
9261                                 vmx_msr_bitmap_nested,
9262                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9263                                 MSR_TYPE_W);
9264                 }
9265         } else {
9266                 /*
9267                  * Enable reading intercept of all the x2apic
9268                  * MSRs. We should not rely on vmcs12 to do any
9269                  * optimizations here, it may have been modified
9270                  * by L1.
9271                  */
9272                 for (msr = 0x800; msr <= 0x8ff; msr++)
9273                         __vmx_enable_intercept_for_msr(
9274                                 vmx_msr_bitmap_nested,
9275                                 msr,
9276                                 MSR_TYPE_R);
9277
9278                 __vmx_enable_intercept_for_msr(
9279                                 vmx_msr_bitmap_nested,
9280                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9281                                 MSR_TYPE_W);
9282                 __vmx_enable_intercept_for_msr(
9283                                 vmx_msr_bitmap_nested,
9284                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9285                                 MSR_TYPE_W);
9286                 __vmx_enable_intercept_for_msr(
9287                                 vmx_msr_bitmap_nested,
9288                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9289                                 MSR_TYPE_W);
9290         }
9291         kunmap(page);
9292         nested_release_page_clean(page);
9293
9294         return true;
9295 }
9296
9297 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9298                                            struct vmcs12 *vmcs12)
9299 {
9300         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9301             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9302             !nested_cpu_has_vid(vmcs12) &&
9303             !nested_cpu_has_posted_intr(vmcs12))
9304                 return 0;
9305
9306         /*
9307          * If virtualize x2apic mode is enabled,
9308          * virtualize apic access must be disabled.
9309          */
9310         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9311             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9312                 return -EINVAL;
9313
9314         /*
9315          * If virtual interrupt delivery is enabled,
9316          * we must exit on external interrupts.
9317          */
9318         if (nested_cpu_has_vid(vmcs12) &&
9319            !nested_exit_on_intr(vcpu))
9320                 return -EINVAL;
9321
9322         /*
9323          * bits 15:8 should be zero in posted_intr_nv,
9324          * the descriptor address has been already checked
9325          * in nested_get_vmcs12_pages.
9326          */
9327         if (nested_cpu_has_posted_intr(vmcs12) &&
9328            (!nested_cpu_has_vid(vmcs12) ||
9329             !nested_exit_intr_ack_set(vcpu) ||
9330             vmcs12->posted_intr_nv & 0xff00))
9331                 return -EINVAL;
9332
9333         /* tpr shadow is needed by all apicv features. */
9334         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9335                 return -EINVAL;
9336
9337         return 0;
9338 }
9339
9340 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9341                                        unsigned long count_field,
9342                                        unsigned long addr_field)
9343 {
9344         int maxphyaddr;
9345         u64 count, addr;
9346
9347         if (vmcs12_read_any(vcpu, count_field, &count) ||
9348             vmcs12_read_any(vcpu, addr_field, &addr)) {
9349                 WARN_ON(1);
9350                 return -EINVAL;
9351         }
9352         if (count == 0)
9353                 return 0;
9354         maxphyaddr = cpuid_maxphyaddr(vcpu);
9355         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9356             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9357                 pr_warn_ratelimited(
9358                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9359                         addr_field, maxphyaddr, count, addr);
9360                 return -EINVAL;
9361         }
9362         return 0;
9363 }
9364
9365 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9366                                                 struct vmcs12 *vmcs12)
9367 {
9368         if (vmcs12->vm_exit_msr_load_count == 0 &&
9369             vmcs12->vm_exit_msr_store_count == 0 &&
9370             vmcs12->vm_entry_msr_load_count == 0)
9371                 return 0; /* Fast path */
9372         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9373                                         VM_EXIT_MSR_LOAD_ADDR) ||
9374             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9375                                         VM_EXIT_MSR_STORE_ADDR) ||
9376             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9377                                         VM_ENTRY_MSR_LOAD_ADDR))
9378                 return -EINVAL;
9379         return 0;
9380 }
9381
9382 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9383                                        struct vmx_msr_entry *e)
9384 {
9385         /* x2APIC MSR accesses are not allowed */
9386         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9387                 return -EINVAL;
9388         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9389             e->index == MSR_IA32_UCODE_REV)
9390                 return -EINVAL;
9391         if (e->reserved != 0)
9392                 return -EINVAL;
9393         return 0;
9394 }
9395
9396 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9397                                      struct vmx_msr_entry *e)
9398 {
9399         if (e->index == MSR_FS_BASE ||
9400             e->index == MSR_GS_BASE ||
9401             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9402             nested_vmx_msr_check_common(vcpu, e))
9403                 return -EINVAL;
9404         return 0;
9405 }
9406
9407 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9408                                       struct vmx_msr_entry *e)
9409 {
9410         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9411             nested_vmx_msr_check_common(vcpu, e))
9412                 return -EINVAL;
9413         return 0;
9414 }
9415
9416 /*
9417  * Load guest's/host's msr at nested entry/exit.
9418  * return 0 for success, entry index for failure.
9419  */
9420 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9421 {
9422         u32 i;
9423         struct vmx_msr_entry e;
9424         struct msr_data msr;
9425
9426         msr.host_initiated = false;
9427         for (i = 0; i < count; i++) {
9428                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9429                                         &e, sizeof(e))) {
9430                         pr_warn_ratelimited(
9431                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9432                                 __func__, i, gpa + i * sizeof(e));
9433                         goto fail;
9434                 }
9435                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9436                         pr_warn_ratelimited(
9437                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9438                                 __func__, i, e.index, e.reserved);
9439                         goto fail;
9440                 }
9441                 msr.index = e.index;
9442                 msr.data = e.value;
9443                 if (kvm_set_msr(vcpu, &msr)) {
9444                         pr_warn_ratelimited(
9445                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9446                                 __func__, i, e.index, e.value);
9447                         goto fail;
9448                 }
9449         }
9450         return 0;
9451 fail:
9452         return i + 1;
9453 }
9454
9455 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9456 {
9457         u32 i;
9458         struct vmx_msr_entry e;
9459
9460         for (i = 0; i < count; i++) {
9461                 struct msr_data msr_info;
9462                 if (kvm_vcpu_read_guest(vcpu,
9463                                         gpa + i * sizeof(e),
9464                                         &e, 2 * sizeof(u32))) {
9465                         pr_warn_ratelimited(
9466                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9467                                 __func__, i, gpa + i * sizeof(e));
9468                         return -EINVAL;
9469                 }
9470                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9471                         pr_warn_ratelimited(
9472                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9473                                 __func__, i, e.index, e.reserved);
9474                         return -EINVAL;
9475                 }
9476                 msr_info.host_initiated = false;
9477                 msr_info.index = e.index;
9478                 if (kvm_get_msr(vcpu, &msr_info)) {
9479                         pr_warn_ratelimited(
9480                                 "%s cannot read MSR (%u, 0x%x)\n",
9481                                 __func__, i, e.index);
9482                         return -EINVAL;
9483                 }
9484                 if (kvm_vcpu_write_guest(vcpu,
9485                                          gpa + i * sizeof(e) +
9486                                              offsetof(struct vmx_msr_entry, value),
9487                                          &msr_info.data, sizeof(msr_info.data))) {
9488                         pr_warn_ratelimited(
9489                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9490                                 __func__, i, e.index, msr_info.data);
9491                         return -EINVAL;
9492                 }
9493         }
9494         return 0;
9495 }
9496
9497 /*
9498  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9499  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9500  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9501  * guest in a way that will both be appropriate to L1's requests, and our
9502  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9503  * function also has additional necessary side-effects, like setting various
9504  * vcpu->arch fields.
9505  */
9506 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9507 {
9508         struct vcpu_vmx *vmx = to_vmx(vcpu);
9509         u32 exec_control;
9510
9511         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9512         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9513         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9514         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9515         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9516         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9517         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9518         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9519         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9520         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9521         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9522         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9523         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9524         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9525         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9526         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9527         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9528         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9529         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9530         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9531         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9532         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9533         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9534         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9535         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9536         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9537         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9538         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9539         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9540         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9541         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9542         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9543         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9544         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9545         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9546         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9547
9548         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9549                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9550                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9551         } else {
9552                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9553                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9554         }
9555         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9556                 vmcs12->vm_entry_intr_info_field);
9557         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9558                 vmcs12->vm_entry_exception_error_code);
9559         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9560                 vmcs12->vm_entry_instruction_len);
9561         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9562                 vmcs12->guest_interruptibility_info);
9563         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9564         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9565         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9566                 vmcs12->guest_pending_dbg_exceptions);
9567         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9568         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9569
9570         if (nested_cpu_has_xsaves(vmcs12))
9571                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9572         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9573
9574         exec_control = vmcs12->pin_based_vm_exec_control;
9575         exec_control |= vmcs_config.pin_based_exec_ctrl;
9576         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9577
9578         if (nested_cpu_has_posted_intr(vmcs12)) {
9579                 /*
9580                  * Note that we use L0's vector here and in
9581                  * vmx_deliver_nested_posted_interrupt.
9582                  */
9583                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9584                 vmx->nested.pi_pending = false;
9585                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9586                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9587                         page_to_phys(vmx->nested.pi_desc_page) +
9588                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9589                         (PAGE_SIZE - 1)));
9590         } else
9591                 exec_control &= ~PIN_BASED_POSTED_INTR;
9592
9593         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9594
9595         vmx->nested.preemption_timer_expired = false;
9596         if (nested_cpu_has_preemption_timer(vmcs12))
9597                 vmx_start_preemption_timer(vcpu);
9598
9599         /*
9600          * Whether page-faults are trapped is determined by a combination of
9601          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9602          * If enable_ept, L0 doesn't care about page faults and we should
9603          * set all of these to L1's desires. However, if !enable_ept, L0 does
9604          * care about (at least some) page faults, and because it is not easy
9605          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9606          * to exit on each and every L2 page fault. This is done by setting
9607          * MASK=MATCH=0 and (see below) EB.PF=1.
9608          * Note that below we don't need special code to set EB.PF beyond the
9609          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9610          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9611          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9612          *
9613          * A problem with this approach (when !enable_ept) is that L1 may be
9614          * injected with more page faults than it asked for. This could have
9615          * caused problems, but in practice existing hypervisors don't care.
9616          * To fix this, we will need to emulate the PFEC checking (on the L1
9617          * page tables), using walk_addr(), when injecting PFs to L1.
9618          */
9619         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9620                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9621         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9622                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9623
9624         if (cpu_has_secondary_exec_ctrls()) {
9625                 exec_control = vmx_secondary_exec_control(vmx);
9626
9627                 /* Take the following fields only from vmcs12 */
9628                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9629                                   SECONDARY_EXEC_RDTSCP |
9630                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9631                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9632                                   SECONDARY_EXEC_PCOMMIT);
9633                 if (nested_cpu_has(vmcs12,
9634                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9635                         exec_control |= vmcs12->secondary_vm_exec_control;
9636
9637                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9638                         /*
9639                          * If translation failed, no matter: This feature asks
9640                          * to exit when accessing the given address, and if it
9641                          * can never be accessed, this feature won't do
9642                          * anything anyway.
9643                          */
9644                         if (!vmx->nested.apic_access_page)
9645                                 exec_control &=
9646                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9647                         else
9648                                 vmcs_write64(APIC_ACCESS_ADDR,
9649                                   page_to_phys(vmx->nested.apic_access_page));
9650                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9651                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9652                         exec_control |=
9653                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9654                         kvm_vcpu_reload_apic_access_page(vcpu);
9655                 }
9656
9657                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9658                         vmcs_write64(EOI_EXIT_BITMAP0,
9659                                 vmcs12->eoi_exit_bitmap0);
9660                         vmcs_write64(EOI_EXIT_BITMAP1,
9661                                 vmcs12->eoi_exit_bitmap1);
9662                         vmcs_write64(EOI_EXIT_BITMAP2,
9663                                 vmcs12->eoi_exit_bitmap2);
9664                         vmcs_write64(EOI_EXIT_BITMAP3,
9665                                 vmcs12->eoi_exit_bitmap3);
9666                         vmcs_write16(GUEST_INTR_STATUS,
9667                                 vmcs12->guest_intr_status);
9668                 }
9669
9670                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9671         }
9672
9673
9674         /*
9675          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9676          * Some constant fields are set here by vmx_set_constant_host_state().
9677          * Other fields are different per CPU, and will be set later when
9678          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9679          */
9680         vmx_set_constant_host_state(vmx);
9681
9682         /*
9683          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9684          * entry, but only if the current (host) sp changed from the value
9685          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9686          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9687          * here we just force the write to happen on entry.
9688          */
9689         vmx->host_rsp = 0;
9690
9691         exec_control = vmx_exec_control(vmx); /* L0's desires */
9692         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9693         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9694         exec_control &= ~CPU_BASED_TPR_SHADOW;
9695         exec_control |= vmcs12->cpu_based_vm_exec_control;
9696
9697         if (exec_control & CPU_BASED_TPR_SHADOW) {
9698                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9699                                 page_to_phys(vmx->nested.virtual_apic_page));
9700                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9701         }
9702
9703         if (cpu_has_vmx_msr_bitmap() &&
9704             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9705                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9706                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9707         } else
9708                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9709
9710         /*
9711          * Merging of IO bitmap not currently supported.
9712          * Rather, exit every time.
9713          */
9714         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9715         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9716
9717         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9718
9719         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9720          * bitwise-or of what L1 wants to trap for L2, and what we want to
9721          * trap. Note that CR0.TS also needs updating - we do this later.
9722          */
9723         update_exception_bitmap(vcpu);
9724         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9725         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9726
9727         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9728          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9729          * bits are further modified by vmx_set_efer() below.
9730          */
9731         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9732
9733         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9734          * emulated by vmx_set_efer(), below.
9735          */
9736         vm_entry_controls_init(vmx,
9737                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9738                         ~VM_ENTRY_IA32E_MODE) |
9739                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9740
9741         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9742                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9743                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9744         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9745                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9746
9747
9748         set_cr4_guest_host_mask(vmx);
9749
9750         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9751                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9752
9753         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9754                 vmcs_write64(TSC_OFFSET,
9755                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9756         else
9757                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9758
9759         if (enable_vpid) {
9760                 /*
9761                  * There is no direct mapping between vpid02 and vpid12, the
9762                  * vpid02 is per-vCPU for L0 and reused while the value of
9763                  * vpid12 is changed w/ one invvpid during nested vmentry.
9764                  * The vpid12 is allocated by L1 for L2, so it will not
9765                  * influence global bitmap(for vpid01 and vpid02 allocation)
9766                  * even if spawn a lot of nested vCPUs.
9767                  */
9768                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9769                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9770                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9771                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9772                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9773                         }
9774                 } else {
9775                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9776                         vmx_flush_tlb(vcpu);
9777                 }
9778
9779         }
9780
9781         if (nested_cpu_has_ept(vmcs12)) {
9782                 kvm_mmu_unload(vcpu);
9783                 nested_ept_init_mmu_context(vcpu);
9784         }
9785
9786         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9787                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9788         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9789                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9790         else
9791                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9792         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9793         vmx_set_efer(vcpu, vcpu->arch.efer);
9794
9795         /*
9796          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9797          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9798          * The CR0_READ_SHADOW is what L2 should have expected to read given
9799          * the specifications by L1; It's not enough to take
9800          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9801          * have more bits than L1 expected.
9802          */
9803         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9804         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9805
9806         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9807         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9808
9809         /* shadow page tables on either EPT or shadow page tables */
9810         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9811         kvm_mmu_reset_context(vcpu);
9812
9813         if (!enable_ept)
9814                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9815
9816         /*
9817          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9818          */
9819         if (enable_ept) {
9820                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9821                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9822                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9823                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9824         }
9825
9826         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9827         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9828 }
9829
9830 /*
9831  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9832  * for running an L2 nested guest.
9833  */
9834 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9835 {
9836         struct vmcs12 *vmcs12;
9837         struct vcpu_vmx *vmx = to_vmx(vcpu);
9838         int cpu;
9839         struct loaded_vmcs *vmcs02;
9840         bool ia32e;
9841         u32 msr_entry_idx;
9842
9843         if (!nested_vmx_check_permission(vcpu) ||
9844             !nested_vmx_check_vmcs12(vcpu))
9845                 return 1;
9846
9847         skip_emulated_instruction(vcpu);
9848         vmcs12 = get_vmcs12(vcpu);
9849
9850         if (enable_shadow_vmcs)
9851                 copy_shadow_to_vmcs12(vmx);
9852
9853         /*
9854          * The nested entry process starts with enforcing various prerequisites
9855          * on vmcs12 as required by the Intel SDM, and act appropriately when
9856          * they fail: As the SDM explains, some conditions should cause the
9857          * instruction to fail, while others will cause the instruction to seem
9858          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9859          * To speed up the normal (success) code path, we should avoid checking
9860          * for misconfigurations which will anyway be caught by the processor
9861          * when using the merged vmcs02.
9862          */
9863         if (vmcs12->launch_state == launch) {
9864                 nested_vmx_failValid(vcpu,
9865                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9866                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9867                 return 1;
9868         }
9869
9870         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9871             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9872                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9873                 return 1;
9874         }
9875
9876         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9877                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9878                 return 1;
9879         }
9880
9881         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9882                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9883                 return 1;
9884         }
9885
9886         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9887                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9888                 return 1;
9889         }
9890
9891         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9892                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9893                 return 1;
9894         }
9895
9896         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9897                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9898                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9899             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9900                                 vmx->nested.nested_vmx_secondary_ctls_low,
9901                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9902             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9903                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9904                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9905             !vmx_control_verify(vmcs12->vm_exit_controls,
9906                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9907                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9908             !vmx_control_verify(vmcs12->vm_entry_controls,
9909                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9910                                 vmx->nested.nested_vmx_entry_ctls_high))
9911         {
9912                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9913                 return 1;
9914         }
9915
9916         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9917             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9918                 nested_vmx_failValid(vcpu,
9919                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9920                 return 1;
9921         }
9922
9923         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9924             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9925                 nested_vmx_entry_failure(vcpu, vmcs12,
9926                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9927                 return 1;
9928         }
9929         if (vmcs12->vmcs_link_pointer != -1ull) {
9930                 nested_vmx_entry_failure(vcpu, vmcs12,
9931                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9932                 return 1;
9933         }
9934
9935         /*
9936          * If the load IA32_EFER VM-entry control is 1, the following checks
9937          * are performed on the field for the IA32_EFER MSR:
9938          * - Bits reserved in the IA32_EFER MSR must be 0.
9939          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9940          *   the IA-32e mode guest VM-exit control. It must also be identical
9941          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9942          *   CR0.PG) is 1.
9943          */
9944         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9945                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9946                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9947                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9948                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9949                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9950                         nested_vmx_entry_failure(vcpu, vmcs12,
9951                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9952                         return 1;
9953                 }
9954         }
9955
9956         /*
9957          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9958          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9959          * the values of the LMA and LME bits in the field must each be that of
9960          * the host address-space size VM-exit control.
9961          */
9962         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9963                 ia32e = (vmcs12->vm_exit_controls &
9964                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9965                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9966                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9967                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9968                         nested_vmx_entry_failure(vcpu, vmcs12,
9969                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9970                         return 1;
9971                 }
9972         }
9973
9974         /*
9975          * We're finally done with prerequisite checking, and can start with
9976          * the nested entry.
9977          */
9978
9979         vmcs02 = nested_get_current_vmcs02(vmx);
9980         if (!vmcs02)
9981                 return -ENOMEM;
9982
9983         enter_guest_mode(vcpu);
9984
9985         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9986
9987         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9988                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9989
9990         cpu = get_cpu();
9991         vmx->loaded_vmcs = vmcs02;
9992         vmx_vcpu_put(vcpu);
9993         vmx_vcpu_load(vcpu, cpu);
9994         vcpu->cpu = cpu;
9995         put_cpu();
9996
9997         vmx_segment_cache_clear(vmx);
9998
9999         prepare_vmcs02(vcpu, vmcs12);
10000
10001         msr_entry_idx = nested_vmx_load_msr(vcpu,
10002                                             vmcs12->vm_entry_msr_load_addr,
10003                                             vmcs12->vm_entry_msr_load_count);
10004         if (msr_entry_idx) {
10005                 leave_guest_mode(vcpu);
10006                 vmx_load_vmcs01(vcpu);
10007                 nested_vmx_entry_failure(vcpu, vmcs12,
10008                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10009                 return 1;
10010         }
10011
10012         vmcs12->launch_state = 1;
10013
10014         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10015                 return kvm_vcpu_halt(vcpu);
10016
10017         vmx->nested.nested_run_pending = 1;
10018
10019         /*
10020          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10021          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10022          * returned as far as L1 is concerned. It will only return (and set
10023          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10024          */
10025         return 1;
10026 }
10027
10028 /*
10029  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10030  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10031  * This function returns the new value we should put in vmcs12.guest_cr0.
10032  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10033  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10034  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10035  *     didn't trap the bit, because if L1 did, so would L0).
10036  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10037  *     been modified by L2, and L1 knows it. So just leave the old value of
10038  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10039  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10040  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10041  *     changed these bits, and therefore they need to be updated, but L0
10042  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10043  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10044  */
10045 static inline unsigned long
10046 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10047 {
10048         return
10049         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10050         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10051         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10052                         vcpu->arch.cr0_guest_owned_bits));
10053 }
10054
10055 static inline unsigned long
10056 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10057 {
10058         return
10059         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10060         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10061         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10062                         vcpu->arch.cr4_guest_owned_bits));
10063 }
10064
10065 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10066                                        struct vmcs12 *vmcs12)
10067 {
10068         u32 idt_vectoring;
10069         unsigned int nr;
10070
10071         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10072                 nr = vcpu->arch.exception.nr;
10073                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10074
10075                 if (kvm_exception_is_soft(nr)) {
10076                         vmcs12->vm_exit_instruction_len =
10077                                 vcpu->arch.event_exit_inst_len;
10078                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10079                 } else
10080                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10081
10082                 if (vcpu->arch.exception.has_error_code) {
10083                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10084                         vmcs12->idt_vectoring_error_code =
10085                                 vcpu->arch.exception.error_code;
10086                 }
10087
10088                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10089         } else if (vcpu->arch.nmi_injected) {
10090                 vmcs12->idt_vectoring_info_field =
10091                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10092         } else if (vcpu->arch.interrupt.pending) {
10093                 nr = vcpu->arch.interrupt.nr;
10094                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10095
10096                 if (vcpu->arch.interrupt.soft) {
10097                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10098                         vmcs12->vm_entry_instruction_len =
10099                                 vcpu->arch.event_exit_inst_len;
10100                 } else
10101                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10102
10103                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10104         }
10105 }
10106
10107 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10108 {
10109         struct vcpu_vmx *vmx = to_vmx(vcpu);
10110
10111         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10112             vmx->nested.preemption_timer_expired) {
10113                 if (vmx->nested.nested_run_pending)
10114                         return -EBUSY;
10115                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10116                 return 0;
10117         }
10118
10119         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10120                 if (vmx->nested.nested_run_pending ||
10121                     vcpu->arch.interrupt.pending)
10122                         return -EBUSY;
10123                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10124                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10125                                   INTR_INFO_VALID_MASK, 0);
10126                 /*
10127                  * The NMI-triggered VM exit counts as injection:
10128                  * clear this one and block further NMIs.
10129                  */
10130                 vcpu->arch.nmi_pending = 0;
10131                 vmx_set_nmi_mask(vcpu, true);
10132                 return 0;
10133         }
10134
10135         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10136             nested_exit_on_intr(vcpu)) {
10137                 if (vmx->nested.nested_run_pending)
10138                         return -EBUSY;
10139                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10140                 return 0;
10141         }
10142
10143         return vmx_complete_nested_posted_interrupt(vcpu);
10144 }
10145
10146 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10147 {
10148         ktime_t remaining =
10149                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10150         u64 value;
10151
10152         if (ktime_to_ns(remaining) <= 0)
10153                 return 0;
10154
10155         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10156         do_div(value, 1000000);
10157         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10158 }
10159
10160 /*
10161  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10162  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10163  * and this function updates it to reflect the changes to the guest state while
10164  * L2 was running (and perhaps made some exits which were handled directly by L0
10165  * without going back to L1), and to reflect the exit reason.
10166  * Note that we do not have to copy here all VMCS fields, just those that
10167  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10168  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10169  * which already writes to vmcs12 directly.
10170  */
10171 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10172                            u32 exit_reason, u32 exit_intr_info,
10173                            unsigned long exit_qualification)
10174 {
10175         /* update guest state fields: */
10176         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10177         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10178
10179         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10180         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10181         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10182
10183         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10184         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10185         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10186         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10187         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10188         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10189         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10190         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10191         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10192         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10193         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10194         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10195         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10196         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10197         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10198         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10199         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10200         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10201         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10202         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10203         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10204         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10205         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10206         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10207         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10208         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10209         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10210         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10211         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10212         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10213         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10214         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10215         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10216         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10217         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10218         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10219
10220         vmcs12->guest_interruptibility_info =
10221                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10222         vmcs12->guest_pending_dbg_exceptions =
10223                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10224         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10225                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10226         else
10227                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10228
10229         if (nested_cpu_has_preemption_timer(vmcs12)) {
10230                 if (vmcs12->vm_exit_controls &
10231                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10232                         vmcs12->vmx_preemption_timer_value =
10233                                 vmx_get_preemption_timer_value(vcpu);
10234                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10235         }
10236
10237         /*
10238          * In some cases (usually, nested EPT), L2 is allowed to change its
10239          * own CR3 without exiting. If it has changed it, we must keep it.
10240          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10241          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10242          *
10243          * Additionally, restore L2's PDPTR to vmcs12.
10244          */
10245         if (enable_ept) {
10246                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10247                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10248                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10249                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10250                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10251         }
10252
10253         if (nested_cpu_has_vid(vmcs12))
10254                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10255
10256         vmcs12->vm_entry_controls =
10257                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10258                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10259
10260         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10261                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10262                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10263         }
10264
10265         /* TODO: These cannot have changed unless we have MSR bitmaps and
10266          * the relevant bit asks not to trap the change */
10267         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10268                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10269         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10270                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10271         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10272         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10273         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10274         if (vmx_mpx_supported())
10275                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10276         if (nested_cpu_has_xsaves(vmcs12))
10277                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10278
10279         /* update exit information fields: */
10280
10281         vmcs12->vm_exit_reason = exit_reason;
10282         vmcs12->exit_qualification = exit_qualification;
10283
10284         vmcs12->vm_exit_intr_info = exit_intr_info;
10285         if ((vmcs12->vm_exit_intr_info &
10286              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10287             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10288                 vmcs12->vm_exit_intr_error_code =
10289                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10290         vmcs12->idt_vectoring_info_field = 0;
10291         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10292         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10293
10294         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10295                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10296                  * instead of reading the real value. */
10297                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10298
10299                 /*
10300                  * Transfer the event that L0 or L1 may wanted to inject into
10301                  * L2 to IDT_VECTORING_INFO_FIELD.
10302                  */
10303                 vmcs12_save_pending_event(vcpu, vmcs12);
10304         }
10305
10306         /*
10307          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10308          * preserved above and would only end up incorrectly in L1.
10309          */
10310         vcpu->arch.nmi_injected = false;
10311         kvm_clear_exception_queue(vcpu);
10312         kvm_clear_interrupt_queue(vcpu);
10313 }
10314
10315 /*
10316  * A part of what we need to when the nested L2 guest exits and we want to
10317  * run its L1 parent, is to reset L1's guest state to the host state specified
10318  * in vmcs12.
10319  * This function is to be called not only on normal nested exit, but also on
10320  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10321  * Failures During or After Loading Guest State").
10322  * This function should be called when the active VMCS is L1's (vmcs01).
10323  */
10324 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10325                                    struct vmcs12 *vmcs12)
10326 {
10327         struct kvm_segment seg;
10328
10329         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10330                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10331         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10332                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10333         else
10334                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10335         vmx_set_efer(vcpu, vcpu->arch.efer);
10336
10337         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10338         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10339         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10340         /*
10341          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10342          * actually changed, because it depends on the current state of
10343          * fpu_active (which may have changed).
10344          * Note that vmx_set_cr0 refers to efer set above.
10345          */
10346         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10347         /*
10348          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10349          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10350          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10351          */
10352         update_exception_bitmap(vcpu);
10353         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10354         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10355
10356         /*
10357          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10358          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10359          */
10360         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10361         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10362
10363         nested_ept_uninit_mmu_context(vcpu);
10364
10365         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10366         kvm_mmu_reset_context(vcpu);
10367
10368         if (!enable_ept)
10369                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10370
10371         if (enable_vpid) {
10372                 /*
10373                  * Trivially support vpid by letting L2s share their parent
10374                  * L1's vpid. TODO: move to a more elaborate solution, giving
10375                  * each L2 its own vpid and exposing the vpid feature to L1.
10376                  */
10377                 vmx_flush_tlb(vcpu);
10378         }
10379
10380
10381         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10382         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10383         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10384         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10385         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10386
10387         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10388         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10389                 vmcs_write64(GUEST_BNDCFGS, 0);
10390
10391         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10392                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10393                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10394         }
10395         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10396                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10397                         vmcs12->host_ia32_perf_global_ctrl);
10398
10399         /* Set L1 segment info according to Intel SDM
10400             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10401         seg = (struct kvm_segment) {
10402                 .base = 0,
10403                 .limit = 0xFFFFFFFF,
10404                 .selector = vmcs12->host_cs_selector,
10405                 .type = 11,
10406                 .present = 1,
10407                 .s = 1,
10408                 .g = 1
10409         };
10410         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10411                 seg.l = 1;
10412         else
10413                 seg.db = 1;
10414         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10415         seg = (struct kvm_segment) {
10416                 .base = 0,
10417                 .limit = 0xFFFFFFFF,
10418                 .type = 3,
10419                 .present = 1,
10420                 .s = 1,
10421                 .db = 1,
10422                 .g = 1
10423         };
10424         seg.selector = vmcs12->host_ds_selector;
10425         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10426         seg.selector = vmcs12->host_es_selector;
10427         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10428         seg.selector = vmcs12->host_ss_selector;
10429         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10430         seg.selector = vmcs12->host_fs_selector;
10431         seg.base = vmcs12->host_fs_base;
10432         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10433         seg.selector = vmcs12->host_gs_selector;
10434         seg.base = vmcs12->host_gs_base;
10435         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10436         seg = (struct kvm_segment) {
10437                 .base = vmcs12->host_tr_base,
10438                 .limit = 0x67,
10439                 .selector = vmcs12->host_tr_selector,
10440                 .type = 11,
10441                 .present = 1
10442         };
10443         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10444
10445         kvm_set_dr(vcpu, 7, 0x400);
10446         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10447
10448         if (cpu_has_vmx_msr_bitmap())
10449                 vmx_set_msr_bitmap(vcpu);
10450
10451         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10452                                 vmcs12->vm_exit_msr_load_count))
10453                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10454 }
10455
10456 /*
10457  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10458  * and modify vmcs12 to make it see what it would expect to see there if
10459  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10460  */
10461 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10462                               u32 exit_intr_info,
10463                               unsigned long exit_qualification)
10464 {
10465         struct vcpu_vmx *vmx = to_vmx(vcpu);
10466         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10467
10468         /* trying to cancel vmlaunch/vmresume is a bug */
10469         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10470
10471         leave_guest_mode(vcpu);
10472         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10473                        exit_qualification);
10474
10475         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10476                                  vmcs12->vm_exit_msr_store_count))
10477                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10478
10479         vmx_load_vmcs01(vcpu);
10480
10481         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10482             && nested_exit_intr_ack_set(vcpu)) {
10483                 int irq = kvm_cpu_get_interrupt(vcpu);
10484                 WARN_ON(irq < 0);
10485                 vmcs12->vm_exit_intr_info = irq |
10486                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10487         }
10488
10489         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10490                                        vmcs12->exit_qualification,
10491                                        vmcs12->idt_vectoring_info_field,
10492                                        vmcs12->vm_exit_intr_info,
10493                                        vmcs12->vm_exit_intr_error_code,
10494                                        KVM_ISA_VMX);
10495
10496         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10497         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10498         vmx_segment_cache_clear(vmx);
10499
10500         /* if no vmcs02 cache requested, remove the one we used */
10501         if (VMCS02_POOL_SIZE == 0)
10502                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10503
10504         load_vmcs12_host_state(vcpu, vmcs12);
10505
10506         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10507         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10508
10509         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10510         vmx->host_rsp = 0;
10511
10512         /* Unpin physical memory we referred to in vmcs02 */
10513         if (vmx->nested.apic_access_page) {
10514                 nested_release_page(vmx->nested.apic_access_page);
10515                 vmx->nested.apic_access_page = NULL;
10516         }
10517         if (vmx->nested.virtual_apic_page) {
10518                 nested_release_page(vmx->nested.virtual_apic_page);
10519                 vmx->nested.virtual_apic_page = NULL;
10520         }
10521         if (vmx->nested.pi_desc_page) {
10522                 kunmap(vmx->nested.pi_desc_page);
10523                 nested_release_page(vmx->nested.pi_desc_page);
10524                 vmx->nested.pi_desc_page = NULL;
10525                 vmx->nested.pi_desc = NULL;
10526         }
10527
10528         /*
10529          * We are now running in L2, mmu_notifier will force to reload the
10530          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10531          */
10532         kvm_vcpu_reload_apic_access_page(vcpu);
10533
10534         /*
10535          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10536          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10537          * success or failure flag accordingly.
10538          */
10539         if (unlikely(vmx->fail)) {
10540                 vmx->fail = 0;
10541                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10542         } else
10543                 nested_vmx_succeed(vcpu);
10544         if (enable_shadow_vmcs)
10545                 vmx->nested.sync_shadow_vmcs = true;
10546
10547         /* in case we halted in L2 */
10548         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10549 }
10550
10551 /*
10552  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10553  */
10554 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10555 {
10556         if (is_guest_mode(vcpu))
10557                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10558         free_nested(to_vmx(vcpu));
10559 }
10560
10561 /*
10562  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10563  * 23.7 "VM-entry failures during or after loading guest state" (this also
10564  * lists the acceptable exit-reason and exit-qualification parameters).
10565  * It should only be called before L2 actually succeeded to run, and when
10566  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10567  */
10568 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10569                         struct vmcs12 *vmcs12,
10570                         u32 reason, unsigned long qualification)
10571 {
10572         load_vmcs12_host_state(vcpu, vmcs12);
10573         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10574         vmcs12->exit_qualification = qualification;
10575         nested_vmx_succeed(vcpu);
10576         if (enable_shadow_vmcs)
10577                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10578 }
10579
10580 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10581                                struct x86_instruction_info *info,
10582                                enum x86_intercept_stage stage)
10583 {
10584         return X86EMUL_CONTINUE;
10585 }
10586
10587 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10588 {
10589         if (ple_gap)
10590                 shrink_ple_window(vcpu);
10591 }
10592
10593 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10594                                      struct kvm_memory_slot *slot)
10595 {
10596         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10597         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10598 }
10599
10600 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10601                                        struct kvm_memory_slot *slot)
10602 {
10603         kvm_mmu_slot_set_dirty(kvm, slot);
10604 }
10605
10606 static void vmx_flush_log_dirty(struct kvm *kvm)
10607 {
10608         kvm_flush_pml_buffers(kvm);
10609 }
10610
10611 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10612                                            struct kvm_memory_slot *memslot,
10613                                            gfn_t offset, unsigned long mask)
10614 {
10615         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10616 }
10617
10618 /*
10619  * This routine does the following things for vCPU which is going
10620  * to be blocked if VT-d PI is enabled.
10621  * - Store the vCPU to the wakeup list, so when interrupts happen
10622  *   we can find the right vCPU to wake up.
10623  * - Change the Posted-interrupt descriptor as below:
10624  *      'NDST' <-- vcpu->pre_pcpu
10625  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10626  * - If 'ON' is set during this process, which means at least one
10627  *   interrupt is posted for this vCPU, we cannot block it, in
10628  *   this case, return 1, otherwise, return 0.
10629  *
10630  */
10631 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10632 {
10633         unsigned long flags;
10634         unsigned int dest;
10635         struct pi_desc old, new;
10636         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10637
10638         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10639                 !irq_remapping_cap(IRQ_POSTING_CAP))
10640                 return 0;
10641
10642         vcpu->pre_pcpu = vcpu->cpu;
10643         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10644                           vcpu->pre_pcpu), flags);
10645         list_add_tail(&vcpu->blocked_vcpu_list,
10646                       &per_cpu(blocked_vcpu_on_cpu,
10647                       vcpu->pre_pcpu));
10648         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10649                                vcpu->pre_pcpu), flags);
10650
10651         do {
10652                 old.control = new.control = pi_desc->control;
10653
10654                 /*
10655                  * We should not block the vCPU if
10656                  * an interrupt is posted for it.
10657                  */
10658                 if (pi_test_on(pi_desc) == 1) {
10659                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10660                                           vcpu->pre_pcpu), flags);
10661                         list_del(&vcpu->blocked_vcpu_list);
10662                         spin_unlock_irqrestore(
10663                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10664                                         vcpu->pre_pcpu), flags);
10665                         vcpu->pre_pcpu = -1;
10666
10667                         return 1;
10668                 }
10669
10670                 WARN((pi_desc->sn == 1),
10671                      "Warning: SN field of posted-interrupts "
10672                      "is set before blocking\n");
10673
10674                 /*
10675                  * Since vCPU can be preempted during this process,
10676                  * vcpu->cpu could be different with pre_pcpu, we
10677                  * need to set pre_pcpu as the destination of wakeup
10678                  * notification event, then we can find the right vCPU
10679                  * to wakeup in wakeup handler if interrupts happen
10680                  * when the vCPU is in blocked state.
10681                  */
10682                 dest = cpu_physical_id(vcpu->pre_pcpu);
10683
10684                 if (x2apic_enabled())
10685                         new.ndst = dest;
10686                 else
10687                         new.ndst = (dest << 8) & 0xFF00;
10688
10689                 /* set 'NV' to 'wakeup vector' */
10690                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10691         } while (cmpxchg(&pi_desc->control, old.control,
10692                         new.control) != old.control);
10693
10694         return 0;
10695 }
10696
10697 static void vmx_post_block(struct kvm_vcpu *vcpu)
10698 {
10699         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10700         struct pi_desc old, new;
10701         unsigned int dest;
10702         unsigned long flags;
10703
10704         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10705                 !irq_remapping_cap(IRQ_POSTING_CAP))
10706                 return;
10707
10708         do {
10709                 old.control = new.control = pi_desc->control;
10710
10711                 dest = cpu_physical_id(vcpu->cpu);
10712
10713                 if (x2apic_enabled())
10714                         new.ndst = dest;
10715                 else
10716                         new.ndst = (dest << 8) & 0xFF00;
10717
10718                 /* Allow posting non-urgent interrupts */
10719                 new.sn = 0;
10720
10721                 /* set 'NV' to 'notification vector' */
10722                 new.nv = POSTED_INTR_VECTOR;
10723         } while (cmpxchg(&pi_desc->control, old.control,
10724                         new.control) != old.control);
10725
10726         if(vcpu->pre_pcpu != -1) {
10727                 spin_lock_irqsave(
10728                         &per_cpu(blocked_vcpu_on_cpu_lock,
10729                         vcpu->pre_pcpu), flags);
10730                 list_del(&vcpu->blocked_vcpu_list);
10731                 spin_unlock_irqrestore(
10732                         &per_cpu(blocked_vcpu_on_cpu_lock,
10733                         vcpu->pre_pcpu), flags);
10734                 vcpu->pre_pcpu = -1;
10735         }
10736 }
10737
10738 /*
10739  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10740  *
10741  * @kvm: kvm
10742  * @host_irq: host irq of the interrupt
10743  * @guest_irq: gsi of the interrupt
10744  * @set: set or unset PI
10745  * returns 0 on success, < 0 on failure
10746  */
10747 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10748                               uint32_t guest_irq, bool set)
10749 {
10750         struct kvm_kernel_irq_routing_entry *e;
10751         struct kvm_irq_routing_table *irq_rt;
10752         struct kvm_lapic_irq irq;
10753         struct kvm_vcpu *vcpu;
10754         struct vcpu_data vcpu_info;
10755         int idx, ret = -EINVAL;
10756
10757         if (!kvm_arch_has_assigned_device(kvm) ||
10758                 !irq_remapping_cap(IRQ_POSTING_CAP))
10759                 return 0;
10760
10761         idx = srcu_read_lock(&kvm->irq_srcu);
10762         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10763         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10764
10765         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10766                 if (e->type != KVM_IRQ_ROUTING_MSI)
10767                         continue;
10768                 /*
10769                  * VT-d PI cannot support posting multicast/broadcast
10770                  * interrupts to a vCPU, we still use interrupt remapping
10771                  * for these kind of interrupts.
10772                  *
10773                  * For lowest-priority interrupts, we only support
10774                  * those with single CPU as the destination, e.g. user
10775                  * configures the interrupts via /proc/irq or uses
10776                  * irqbalance to make the interrupts single-CPU.
10777                  *
10778                  * We will support full lowest-priority interrupt later.
10779                  */
10780
10781                 kvm_set_msi_irq(e, &irq);
10782                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10783                         /*
10784                          * Make sure the IRTE is in remapped mode if
10785                          * we don't handle it in posted mode.
10786                          */
10787                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10788                         if (ret < 0) {
10789                                 printk(KERN_INFO
10790                                    "failed to back to remapped mode, irq: %u\n",
10791                                    host_irq);
10792                                 goto out;
10793                         }
10794
10795                         continue;
10796                 }
10797
10798                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10799                 vcpu_info.vector = irq.vector;
10800
10801                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10802                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10803
10804                 if (set)
10805                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10806                 else {
10807                         /* suppress notification event before unposting */
10808                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10809                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10810                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10811                 }
10812
10813                 if (ret < 0) {
10814                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10815                                         __func__);
10816                         goto out;
10817                 }
10818         }
10819
10820         ret = 0;
10821 out:
10822         srcu_read_unlock(&kvm->irq_srcu, idx);
10823         return ret;
10824 }
10825
10826 static struct kvm_x86_ops vmx_x86_ops = {
10827         .cpu_has_kvm_support = cpu_has_kvm_support,
10828         .disabled_by_bios = vmx_disabled_by_bios,
10829         .hardware_setup = hardware_setup,
10830         .hardware_unsetup = hardware_unsetup,
10831         .check_processor_compatibility = vmx_check_processor_compat,
10832         .hardware_enable = hardware_enable,
10833         .hardware_disable = hardware_disable,
10834         .cpu_has_accelerated_tpr = report_flexpriority,
10835         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10836
10837         .vcpu_create = vmx_create_vcpu,
10838         .vcpu_free = vmx_free_vcpu,
10839         .vcpu_reset = vmx_vcpu_reset,
10840
10841         .prepare_guest_switch = vmx_save_host_state,
10842         .vcpu_load = vmx_vcpu_load,
10843         .vcpu_put = vmx_vcpu_put,
10844
10845         .update_bp_intercept = update_exception_bitmap,
10846         .get_msr = vmx_get_msr,
10847         .set_msr = vmx_set_msr,
10848         .get_segment_base = vmx_get_segment_base,
10849         .get_segment = vmx_get_segment,
10850         .set_segment = vmx_set_segment,
10851         .get_cpl = vmx_get_cpl,
10852         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10853         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10854         .decache_cr3 = vmx_decache_cr3,
10855         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10856         .set_cr0 = vmx_set_cr0,
10857         .set_cr3 = vmx_set_cr3,
10858         .set_cr4 = vmx_set_cr4,
10859         .set_efer = vmx_set_efer,
10860         .get_idt = vmx_get_idt,
10861         .set_idt = vmx_set_idt,
10862         .get_gdt = vmx_get_gdt,
10863         .set_gdt = vmx_set_gdt,
10864         .get_dr6 = vmx_get_dr6,
10865         .set_dr6 = vmx_set_dr6,
10866         .set_dr7 = vmx_set_dr7,
10867         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10868         .cache_reg = vmx_cache_reg,
10869         .get_rflags = vmx_get_rflags,
10870         .set_rflags = vmx_set_rflags,
10871         .fpu_activate = vmx_fpu_activate,
10872         .fpu_deactivate = vmx_fpu_deactivate,
10873
10874         .tlb_flush = vmx_flush_tlb,
10875
10876         .run = vmx_vcpu_run,
10877         .handle_exit = vmx_handle_exit,
10878         .skip_emulated_instruction = skip_emulated_instruction,
10879         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10880         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10881         .patch_hypercall = vmx_patch_hypercall,
10882         .set_irq = vmx_inject_irq,
10883         .set_nmi = vmx_inject_nmi,
10884         .queue_exception = vmx_queue_exception,
10885         .cancel_injection = vmx_cancel_injection,
10886         .interrupt_allowed = vmx_interrupt_allowed,
10887         .nmi_allowed = vmx_nmi_allowed,
10888         .get_nmi_mask = vmx_get_nmi_mask,
10889         .set_nmi_mask = vmx_set_nmi_mask,
10890         .enable_nmi_window = enable_nmi_window,
10891         .enable_irq_window = enable_irq_window,
10892         .update_cr8_intercept = update_cr8_intercept,
10893         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10894         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10895         .get_enable_apicv = vmx_get_enable_apicv,
10896         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10897         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10898         .hwapic_irr_update = vmx_hwapic_irr_update,
10899         .hwapic_isr_update = vmx_hwapic_isr_update,
10900         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10901         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10902
10903         .set_tss_addr = vmx_set_tss_addr,
10904         .get_tdp_level = get_ept_level,
10905         .get_mt_mask = vmx_get_mt_mask,
10906
10907         .get_exit_info = vmx_get_exit_info,
10908
10909         .get_lpage_level = vmx_get_lpage_level,
10910
10911         .cpuid_update = vmx_cpuid_update,
10912
10913         .rdtscp_supported = vmx_rdtscp_supported,
10914         .invpcid_supported = vmx_invpcid_supported,
10915
10916         .set_supported_cpuid = vmx_set_supported_cpuid,
10917
10918         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10919
10920         .read_tsc_offset = vmx_read_tsc_offset,
10921         .write_tsc_offset = vmx_write_tsc_offset,
10922         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10923         .read_l1_tsc = vmx_read_l1_tsc,
10924
10925         .set_tdp_cr3 = vmx_set_cr3,
10926
10927         .check_intercept = vmx_check_intercept,
10928         .handle_external_intr = vmx_handle_external_intr,
10929         .mpx_supported = vmx_mpx_supported,
10930         .xsaves_supported = vmx_xsaves_supported,
10931
10932         .check_nested_events = vmx_check_nested_events,
10933
10934         .sched_in = vmx_sched_in,
10935
10936         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10937         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10938         .flush_log_dirty = vmx_flush_log_dirty,
10939         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10940
10941         .pre_block = vmx_pre_block,
10942         .post_block = vmx_post_block,
10943
10944         .pmu_ops = &intel_pmu_ops,
10945
10946         .update_pi_irte = vmx_update_pi_irte,
10947 };
10948
10949 static int __init vmx_init(void)
10950 {
10951         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10952                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10953         if (r)
10954                 return r;
10955
10956 #ifdef CONFIG_KEXEC_CORE
10957         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10958                            crash_vmclear_local_loaded_vmcss);
10959 #endif
10960
10961         return 0;
10962 }
10963
10964 static void __exit vmx_exit(void)
10965 {
10966 #ifdef CONFIG_KEXEC_CORE
10967         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10968         synchronize_rcu();
10969 #endif
10970
10971         kvm_exit();
10972 }
10973
10974 module_init(vmx_init)
10975 module_exit(vmx_exit)