2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 #define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
65 static bool __read_mostly enable_vpid = 1;
66 module_param_named(vpid, enable_vpid, bool, 0444);
68 static bool __read_mostly flexpriority_enabled = 1;
69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
71 static bool __read_mostly enable_ept = 1;
72 module_param_named(ept, enable_ept, bool, S_IRUGO);
74 static bool __read_mostly enable_unrestricted_guest = 1;
75 module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
78 static bool __read_mostly enable_ept_ad_bits = 1;
79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
81 static bool __read_mostly emulate_invalid_guest_state = true;
82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
84 static bool __read_mostly vmm_exclusive = 1;
85 module_param(vmm_exclusive, bool, S_IRUGO);
87 static bool __read_mostly fasteoi = 1;
88 module_param(fasteoi, bool, S_IRUGO);
90 static bool __read_mostly enable_apicv = 1;
91 module_param(enable_apicv, bool, S_IRUGO);
93 static bool __read_mostly enable_shadow_vmcs = 1;
94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
100 static bool __read_mostly nested = 0;
101 module_param(nested, bool, S_IRUGO);
103 static u64 __read_mostly host_xss;
105 static bool __read_mostly enable_pml = 1;
106 module_param_named(pml, enable_pml, bool, S_IRUGO);
108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
110 #define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
112 #define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
127 * According to test, this time is usually smaller than 128 cycles.
128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
134 #define KVM_VMX_DEFAULT_PLE_GAP 128
135 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142 module_param(ple_gap, int, S_IRUGO);
144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145 module_param(ple_window, int, S_IRUGO);
147 /* Default doubles per-vcpu window every exit. */
148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149 module_param(ple_window_grow, int, S_IRUGO);
151 /* Default resets per-vcpu window every exit to ple_window. */
152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153 module_param(ple_window_shrink, int, S_IRUGO);
155 /* Default is to compute the maximum so we can never overflow. */
156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158 module_param(ple_window_max, int, S_IRUGO);
160 extern const ulong vmx_return;
162 #define NR_AUTOLOAD_MSRS 8
163 #define VMCS02_POOL_SIZE 1
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
180 struct list_head loaded_vmcss_on_cpu_link;
183 struct shared_msr_entry {
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
202 typedef u64 natural_width;
203 struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
222 u64 posted_intr_desc_addr;
224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
234 u64 guest_ia32_perf_global_ctrl;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
323 u32 guest_ldtr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
341 u16 virtual_processor_id;
343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
351 u16 guest_intr_status;
352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
366 #define VMCS12_REVISION 0x11e57ed0
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
373 #define VMCS12_SIZE 0x1000
375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
377 struct list_head list;
379 struct loaded_vmcs vmcs02;
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
387 /* Has the level1 guest done vmxon? */
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
396 struct vmcs *current_shadow_vmcs;
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
401 bool sync_shadow_vmcs;
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
406 u64 vmcs01_tsc_offset;
407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
413 struct page *apic_access_page;
414 struct page *virtual_apic_page;
415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
419 u64 msr_ia32_feature_control;
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
445 #define POSTED_INTR_ON 0
446 /* Posted-Interrupt Descriptor */
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
471 struct kvm_vcpu vcpu;
472 unsigned long host_rsp;
474 bool nmi_known_unmasked;
476 u32 idt_vectoring_info;
478 struct shared_msr_entry *guest_msrs;
481 unsigned long host_idt_base;
483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
496 struct msr_autoload {
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
503 u16 fs_sel, gs_sel, ldt_sel;
507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
509 u64 msr_host_bndcfgs;
510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
515 struct kvm_segment segs[8];
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
519 struct kvm_save_segment {
527 bool emulation_required;
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
532 s64 vnmi_blocked_time;
537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
543 /* Dynamic PLE window. */
545 bool ple_window_dirty;
547 /* Support for PML */
548 #define PML_ENTITY_NUM 512
552 enum segment_cache_field {
561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
563 return container_of(vcpu, struct vcpu_vmx, vcpu);
566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
572 static unsigned long shadow_read_only_fields[] = {
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
595 static int max_shadow_read_only_fields =
596 ARRAY_SIZE(shadow_read_only_fields);
598 static unsigned long shadow_read_write_fields[] = {
605 GUEST_INTERRUPTIBILITY_INFO,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
628 static int max_shadow_read_write_fields =
629 ARRAY_SIZE(shadow_read_write_fields);
631 static const unsigned short vmcs_field_to_offset_table[] = {
632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
633 FIELD(POSTED_INTR_NV, posted_intr_nv),
634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
660 FIELD64(EPT_POINTER, ept_pointer),
661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
771 static inline short vmcs_field_to_offset(unsigned long field)
773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
779 return vmcs_field_to_offset_table[field];
782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
784 return to_vmx(vcpu)->nested.current_vmcs12;
787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
789 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
790 if (is_error_page(page))
796 static void nested_release_page(struct page *page)
798 kvm_release_page_dirty(page);
801 static void nested_release_page_clean(struct page *page)
803 kvm_release_page_clean(page);
806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
807 static u64 construct_eptp(unsigned long root_hpa);
808 static void kvm_cpu_vmxon(u64 addr);
809 static void kvm_cpu_vmxoff(void);
810 static bool vmx_mpx_supported(void);
811 static bool vmx_xsaves_supported(void);
812 static int vmx_vm_has_apicv(struct kvm *kvm);
813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
823 static int alloc_identity_pagetable(struct kvm *kvm);
825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
834 static unsigned long *vmx_io_bitmap_a;
835 static unsigned long *vmx_io_bitmap_b;
836 static unsigned long *vmx_msr_bitmap_legacy;
837 static unsigned long *vmx_msr_bitmap_longmode;
838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
840 static unsigned long *vmx_msr_bitmap_nested;
841 static unsigned long *vmx_vmread_bitmap;
842 static unsigned long *vmx_vmwrite_bitmap;
844 static bool cpu_has_load_ia32_efer;
845 static bool cpu_has_load_perf_global_ctrl;
847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848 static DEFINE_SPINLOCK(vmx_vpid_lock);
850 static struct vmcs_config {
854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
856 u32 cpu_based_2nd_exec_ctrl;
861 static struct vmx_capability {
866 #define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
874 static const struct kvm_vmx_segment_field {
879 } kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
890 static u64 host_efer;
892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
896 * away by decrementing the array size.
898 static const u32 vmx_msr_index[] = {
900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
905 static inline bool is_page_fault(u32 intr_info)
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
912 static inline bool is_no_device(u32 intr_info)
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
919 static inline bool is_invalid_opcode(u32 intr_info)
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
926 static inline bool is_external_interrupt(u32 intr_info)
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
932 static inline bool is_machine_check(u32 intr_info)
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
939 static inline bool cpu_has_vmx_msr_bitmap(void)
941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
944 static inline bool cpu_has_vmx_tpr_shadow(void)
946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
951 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
954 static inline bool cpu_has_secondary_exec_ctrls(void)
956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
972 static inline bool cpu_has_vmx_apic_register_virt(void)
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
984 static inline bool cpu_has_vmx_posted_intr(void)
986 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
989 static inline bool cpu_has_vmx_apicv(void)
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
996 static inline bool cpu_has_vmx_flexpriority(void)
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1004 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1009 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1014 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1019 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1024 return vmx_capability.ept & VMX_EPT_AD_BIT;
1027 static inline bool cpu_has_vmx_invept_context(void)
1029 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1032 static inline bool cpu_has_vmx_invept_global(void)
1034 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1039 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1044 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1047 static inline bool cpu_has_vmx_ept(void)
1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_ENABLE_EPT;
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1059 static inline bool cpu_has_vmx_ple(void)
1061 return vmcs_config.cpu_based_2nd_exec_ctrl &
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1067 return flexpriority_enabled && irqchip_in_kernel(kvm);
1070 static inline bool cpu_has_vmx_vpid(void)
1072 return vmcs_config.cpu_based_2nd_exec_ctrl &
1073 SECONDARY_EXEC_ENABLE_VPID;
1076 static inline bool cpu_has_vmx_rdtscp(void)
1078 return vmcs_config.cpu_based_2nd_exec_ctrl &
1079 SECONDARY_EXEC_RDTSCP;
1082 static inline bool cpu_has_vmx_invpcid(void)
1084 return vmcs_config.cpu_based_2nd_exec_ctrl &
1085 SECONDARY_EXEC_ENABLE_INVPCID;
1088 static inline bool cpu_has_virtual_nmis(void)
1090 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_WBINVD_EXITING;
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1102 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_SHADOW_VMCS;
1111 static inline bool cpu_has_vmx_pml(void)
1113 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1116 static inline bool report_flexpriority(void)
1118 return flexpriority_enabled;
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1123 return vmcs12->cpu_based_vm_exec_control & bit;
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1128 return (vmcs12->cpu_based_vm_exec_control &
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130 (vmcs12->secondary_vm_exec_control & bit);
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1135 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1140 return vmcs12->pin_based_vm_exec_control &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152 vmx_xsaves_supported();
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1162 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1172 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1175 static inline bool is_exception(u32 intr_info)
1177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1183 unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185 struct vmcs12 *vmcs12,
1186 u32 reason, unsigned long qualification);
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1192 for (i = 0; i < vmx->nmsrs; ++i)
1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1204 } operand = { vpid, 0, gva };
1206 asm volatile (__ex(ASM_VMX_INVVPID)
1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand), "c"(ext) : "cc", "memory");
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1216 } operand = {eptp, gpa};
1218 asm volatile (__ex(ASM_VMX_INVEPT)
1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand), "c" (ext) : "cc", "memory");
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1228 i = __find_msr_index(vmx, msr);
1230 return &vmx->guest_msrs[i];
1234 static void vmcs_clear(struct vmcs *vmcs)
1236 u64 phys_addr = __pa(vmcs);
1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1243 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1249 vmcs_clear(loaded_vmcs->vmcs);
1250 loaded_vmcs->cpu = -1;
1251 loaded_vmcs->launched = 0;
1254 static void vmcs_load(struct vmcs *vmcs)
1256 u64 phys_addr = __pa(vmcs);
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1263 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1275 static inline void crash_enable_local_vmclear(int cpu)
1277 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1280 static inline void crash_disable_local_vmclear(int cpu)
1282 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1285 static inline int crash_local_vmclear_enabled(int cpu)
1287 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1290 static void crash_vmclear_local_loaded_vmcss(void)
1292 int cpu = raw_smp_processor_id();
1293 struct loaded_vmcs *v;
1295 if (!crash_local_vmclear_enabled(cpu))
1298 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299 loaded_vmcss_on_cpu_link)
1300 vmcs_clear(v->vmcs);
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1307 static void __loaded_vmcs_clear(void *arg)
1309 struct loaded_vmcs *loaded_vmcs = arg;
1310 int cpu = raw_smp_processor_id();
1312 if (loaded_vmcs->cpu != cpu)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315 per_cpu(current_vmcs, cpu) = NULL;
1316 crash_disable_local_vmclear(cpu);
1317 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1327 loaded_vmcs_init(loaded_vmcs);
1328 crash_enable_local_vmclear(cpu);
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1333 int cpu = loaded_vmcs->cpu;
1336 smp_call_function_single(cpu,
1337 __loaded_vmcs_clear, loaded_vmcs, 1);
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1349 static inline void vpid_sync_vcpu_global(void)
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1357 if (cpu_has_vmx_invvpid_single())
1358 vpid_sync_vcpu_single(vmx);
1360 vpid_sync_vcpu_global();
1363 static inline void ept_sync_global(void)
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1369 static inline void ept_sync_context(u64 eptp)
1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1381 unsigned long value;
1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384 : "=a"(value) : "d"(field) : "cc");
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1390 return vmcs_readl(field);
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1395 return vmcs_readl(field);
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1400 #ifdef CONFIG_X86_64
1401 return vmcs_readl(field);
1403 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1409 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419 : "=q"(error) : "a"(value), "d"(field) : "cc");
1420 if (unlikely(error))
1421 vmwrite_error(field, value);
1424 static void vmcs_write16(unsigned long field, u16 value)
1426 vmcs_writel(field, value);
1429 static void vmcs_write32(unsigned long field, u32 value)
1431 vmcs_writel(field, value);
1434 static void vmcs_write64(unsigned long field, u64 value)
1436 vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1439 vmcs_writel(field+1, value >> 32);
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1445 vmcs_writel(field, vmcs_readl(field) & ~mask);
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1450 vmcs_writel(field, vmcs_readl(field) | mask);
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1455 vmcs_write32(VM_ENTRY_CONTROLS, val);
1456 vmx->vm_entry_controls_shadow = val;
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1461 if (vmx->vm_entry_controls_shadow != val)
1462 vm_entry_controls_init(vmx, val);
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1467 return vmx->vm_entry_controls_shadow;
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1473 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1478 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1483 vmcs_write32(VM_EXIT_CONTROLS, val);
1484 vmx->vm_exit_controls_shadow = val;
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1489 if (vmx->vm_exit_controls_shadow != val)
1490 vm_exit_controls_init(vmx, val);
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1495 return vmx->vm_exit_controls_shadow;
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1501 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1506 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1511 vmx->segment_cache.bitmask = 0;
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1518 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1520 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522 vmx->segment_cache.bitmask = 0;
1524 ret = vmx->segment_cache.bitmask & mask;
1525 vmx->segment_cache.bitmask |= mask;
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1531 u16 *p = &vmx->segment_cache.seg[seg].selector;
1533 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1540 ulong *p = &vmx->segment_cache.seg[seg].base;
1542 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1549 u32 *p = &vmx->segment_cache.seg[seg].limit;
1551 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1558 u32 *p = &vmx->segment_cache.seg[seg].ar;
1560 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571 if ((vcpu->guest_debug &
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574 eb |= 1u << BP_VECTOR;
1575 if (to_vmx(vcpu)->rmode.vm86_active)
1578 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579 if (vcpu->fpu_active)
1580 eb &= ~(1u << NM_VECTOR);
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1587 if (is_guest_mode(vcpu))
1588 eb |= get_vmcs12(vcpu)->exception_bitmap;
1590 vmcs_write32(EXCEPTION_BITMAP, eb);
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594 unsigned long entry, unsigned long exit)
1596 vm_entry_controls_clearbit(vmx, entry);
1597 vm_exit_controls_clearbit(vmx, exit);
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1603 struct msr_autoload *m = &vmx->msr_autoload;
1607 if (cpu_has_load_ia32_efer) {
1608 clear_atomic_switch_msr_special(vmx,
1609 VM_ENTRY_LOAD_IA32_EFER,
1610 VM_EXIT_LOAD_IA32_EFER);
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
1616 clear_atomic_switch_msr_special(vmx,
1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1631 m->guest[i] = m->guest[m->nr];
1632 m->host[i] = m->host[m->nr];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638 unsigned long entry, unsigned long exit,
1639 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640 u64 guest_val, u64 host_val)
1642 vmcs_write64(guest_val_vmcs, guest_val);
1643 vmcs_write64(host_val_vmcs, host_val);
1644 vm_entry_controls_setbit(vmx, entry);
1645 vm_exit_controls_setbit(vmx, exit);
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649 u64 guest_val, u64 host_val)
1652 struct msr_autoload *m = &vmx->msr_autoload;
1656 if (cpu_has_load_ia32_efer) {
1657 add_atomic_switch_msr_special(vmx,
1658 VM_ENTRY_LOAD_IA32_EFER,
1659 VM_EXIT_LOAD_IA32_EFER,
1662 guest_val, host_val);
1666 case MSR_CORE_PERF_GLOBAL_CTRL:
1667 if (cpu_has_load_perf_global_ctrl) {
1668 add_atomic_switch_msr_special(vmx,
1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 GUEST_IA32_PERF_GLOBAL_CTRL,
1672 HOST_IA32_PERF_GLOBAL_CTRL,
1673 guest_val, host_val);
1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1683 if (i == NR_AUTOLOAD_MSRS) {
1684 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685 "Can't add msr %x\n", msr);
1687 } else if (i == m->nr) {
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1693 m->guest[i].index = msr;
1694 m->guest[i].value = guest_val;
1695 m->host[i].index = msr;
1696 m->host[i].value = host_val;
1699 static void reload_tss(void)
1702 * VT restores TR but not its size. Useless.
1704 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705 struct desc_struct *descs;
1707 descs = (void *)gdt->address;
1708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1717 guest_efer = vmx->vcpu.arch.efer;
1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1723 ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725 ignore_bits |= EFER_LMA | EFER_LME;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer & EFER_LMA)
1728 ignore_bits &= ~(u64)EFER_SCE;
1730 guest_efer &= ~ignore_bits;
1731 guest_efer |= host_efer & ignore_bits;
1732 vmx->guest_msrs[efer_offset].data = guest_efer;
1733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1735 clear_atomic_switch_msr(vmx, MSR_EFER);
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1742 if (cpu_has_load_ia32_efer ||
1743 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744 guest_efer = vmx->vcpu.arch.efer;
1745 if (!(guest_efer & EFER_LMA))
1746 guest_efer &= ~EFER_LME;
1747 if (guest_efer != host_efer)
1748 add_atomic_switch_msr(vmx, MSR_EFER,
1749 guest_efer, host_efer);
1756 static unsigned long segment_base(u16 selector)
1758 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759 struct desc_struct *d;
1760 unsigned long table_base;
1763 if (!(selector & ~3))
1766 table_base = gdt->address;
1768 if (selector & 4) { /* from ldt */
1769 u16 ldt_selector = kvm_read_ldt();
1771 if (!(ldt_selector & ~3))
1774 table_base = segment_base(ldt_selector);
1776 d = (struct desc_struct *)(table_base + (selector & ~7));
1777 v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1785 static inline unsigned long kvm_read_tr_base(void)
1788 asm("str %0" : "=g"(tr));
1789 return segment_base(tr);
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
1797 if (vmx->host_state.loaded)
1800 vmx->host_state.loaded = 1;
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1805 vmx->host_state.ldt_sel = kvm_read_ldt();
1806 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807 savesegment(fs, vmx->host_state.fs_sel);
1808 if (!(vmx->host_state.fs_sel & 7)) {
1809 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810 vmx->host_state.fs_reload_needed = 0;
1812 vmcs_write16(HOST_FS_SELECTOR, 0);
1813 vmx->host_state.fs_reload_needed = 1;
1815 savesegment(gs, vmx->host_state.gs_sel);
1816 if (!(vmx->host_state.gs_sel & 7))
1817 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1819 vmcs_write16(HOST_GS_SELECTOR, 0);
1820 vmx->host_state.gs_ldt_reload_needed = 1;
1823 #ifdef CONFIG_X86_64
1824 savesegment(ds, vmx->host_state.ds_sel);
1825 savesegment(es, vmx->host_state.es_sel);
1828 #ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1832 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1836 #ifdef CONFIG_X86_64
1837 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838 if (is_long_mode(&vmx->vcpu))
1839 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1841 if (boot_cpu_has(X86_FEATURE_MPX))
1842 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843 for (i = 0; i < vmx->save_nmsrs; ++i)
1844 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845 vmx->guest_msrs[i].data,
1846 vmx->guest_msrs[i].mask);
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1851 if (!vmx->host_state.loaded)
1854 ++vmx->vcpu.stat.host_state_reload;
1855 vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx->vcpu))
1858 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1860 if (vmx->host_state.gs_ldt_reload_needed) {
1861 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863 load_gs_index(vmx->host_state.gs_sel);
1865 loadsegment(gs, vmx->host_state.gs_sel);
1868 if (vmx->host_state.fs_reload_needed)
1869 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872 loadsegment(ds, vmx->host_state.ds_sel);
1873 loadsegment(es, vmx->host_state.es_sel);
1877 #ifdef CONFIG_X86_64
1878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1880 if (vmx->host_state.msr_host_bndcfgs)
1881 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1886 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1888 load_gdt(this_cpu_ptr(&host_gdt));
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1894 __vmx_load_host_state(vmx);
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
1905 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1908 kvm_cpu_vmxon(phys_addr);
1909 else if (vmx->loaded_vmcs->cpu != cpu)
1910 loaded_vmcs_clear(vmx->loaded_vmcs);
1912 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914 vmcs_load(vmx->loaded_vmcs->vmcs);
1917 if (vmx->loaded_vmcs->cpu != cpu) {
1918 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919 unsigned long sysenter_esp;
1921 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922 local_irq_disable();
1923 crash_disable_local_vmclear(cpu);
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1932 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933 &per_cpu(loaded_vmcss_on_cpu, cpu));
1934 crash_enable_local_vmclear(cpu);
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1941 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1944 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946 vmx->loaded_vmcs->cpu = cpu;
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1952 __vmx_load_host_state(to_vmx(vcpu));
1953 if (!vmm_exclusive) {
1954 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1964 if (vcpu->fpu_active)
1966 vcpu->fpu_active = 1;
1967 cr0 = vmcs_readl(GUEST_CR0);
1968 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970 vmcs_writel(GUEST_CR0, cr0);
1971 update_exception_bitmap(vcpu);
1972 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973 if (is_guest_mode(vcpu))
1974 vcpu->arch.cr0_guest_owned_bits &=
1975 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1988 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1993 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2002 vmx_decache_cr0_guest_bits(vcpu);
2003 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004 update_exception_bitmap(vcpu);
2005 vcpu->arch.cr0_guest_owned_bits = 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007 if (is_guest_mode(vcpu)) {
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018 (vcpu->arch.cr0 & X86_CR0_TS);
2019 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2021 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2026 unsigned long rflags, save_rflags;
2028 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030 rflags = vmcs_readl(GUEST_RFLAGS);
2031 if (to_vmx(vcpu)->rmode.vm86_active) {
2032 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2036 to_vmx(vcpu)->rflags = rflags;
2038 return to_vmx(vcpu)->rflags;
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2043 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044 to_vmx(vcpu)->rflags = rflags;
2045 if (to_vmx(vcpu)->rmode.vm86_active) {
2046 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2049 vmcs_writel(GUEST_RFLAGS, rflags);
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2054 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2057 if (interruptibility & GUEST_INTR_STATE_STI)
2058 ret |= KVM_X86_SHADOW_INT_STI;
2059 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2067 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068 u32 interruptibility = interruptibility_old;
2070 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2072 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074 else if (mask & KVM_X86_SHADOW_INT_STI)
2075 interruptibility |= GUEST_INTR_STATE_STI;
2077 if ((interruptibility != interruptibility_old))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2085 rip = kvm_rip_read(vcpu);
2086 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087 kvm_rip_write(vcpu, rip);
2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu, 0);
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2101 if (!(vmcs12->exception_bitmap & (1u << nr)))
2104 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105 vmcs_read32(VM_EXIT_INTR_INFO),
2106 vmcs_readl(EXIT_QUALIFICATION));
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111 bool has_error_code, u32 error_code,
2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
2115 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2117 if (!reinject && is_guest_mode(vcpu) &&
2118 nested_vmx_check_exception(vcpu, nr))
2121 if (has_error_code) {
2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2126 if (vmx->rmode.vm86_active) {
2128 if (kvm_exception_is_soft(nr))
2129 inc_eip = vcpu->arch.event_exit_inst_len;
2130 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2135 if (kvm_exception_is_soft(nr)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137 vmx->vcpu.arch.event_exit_inst_len);
2138 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2140 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2145 static bool vmx_rdtscp_supported(void)
2147 return cpu_has_vmx_rdtscp();
2150 static bool vmx_invpcid_supported(void)
2152 return cpu_has_vmx_invpcid() && enable_ept;
2156 * Swap MSR entry in host/guest MSR entry array.
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2160 struct shared_msr_entry tmp;
2162 tmp = vmx->guest_msrs[to];
2163 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164 vmx->guest_msrs[from] = tmp;
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2169 unsigned long *msr_bitmap;
2171 if (is_guest_mode(vcpu))
2172 msr_bitmap = vmx_msr_bitmap_nested;
2173 else if (irqchip_in_kernel(vcpu->kvm) &&
2174 apic_x2apic_mode(vcpu->arch.apic)) {
2175 if (is_long_mode(vcpu))
2176 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2178 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2180 if (is_long_mode(vcpu))
2181 msr_bitmap = vmx_msr_bitmap_longmode;
2183 msr_bitmap = vmx_msr_bitmap_legacy;
2186 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2194 static void setup_msrs(struct vcpu_vmx *vmx)
2196 int save_nmsrs, index;
2199 #ifdef CONFIG_X86_64
2200 if (is_long_mode(&vmx->vcpu)) {
2201 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_LSTAR);
2206 move_msr_up(vmx, index, save_nmsrs++);
2207 index = __find_msr_index(vmx, MSR_CSTAR);
2209 move_msr_up(vmx, index, save_nmsrs++);
2210 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211 if (index >= 0 && vmx->rdtscp_enabled)
2212 move_msr_up(vmx, index, save_nmsrs++);
2214 * MSR_STAR is only needed on long mode guests, and only
2215 * if efer.sce is enabled.
2217 index = __find_msr_index(vmx, MSR_STAR);
2218 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2219 move_msr_up(vmx, index, save_nmsrs++);
2222 index = __find_msr_index(vmx, MSR_EFER);
2223 if (index >= 0 && update_transition_efer(vmx, index))
2224 move_msr_up(vmx, index, save_nmsrs++);
2226 vmx->save_nmsrs = save_nmsrs;
2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx->vcpu);
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2236 static u64 guest_read_tsc(void)
2238 u64 host_tsc, tsc_offset;
2241 tsc_offset = vmcs_read64(TSC_OFFSET);
2242 return host_tsc + tsc_offset;
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2249 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2253 tsc_offset = is_guest_mode(vcpu) ?
2254 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255 vmcs_read64(TSC_OFFSET);
2256 return host_tsc + tsc_offset;
2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
2263 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2268 if (user_tsc_khz > tsc_khz) {
2269 vcpu->arch.tsc_catchup = 1;
2270 vcpu->arch.tsc_always_catchup = 1;
2272 WARN(1, "user requested TSC rate below hardware speed\n");
2275 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2277 return vmcs_read64(TSC_OFFSET);
2281 * writes 'offset' into guest's timestamp counter offset register
2283 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2285 if (is_guest_mode(vcpu)) {
2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
2292 struct vmcs12 *vmcs12;
2293 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12 = get_vmcs12(vcpu);
2296 vmcs_write64(TSC_OFFSET, offset +
2297 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298 vmcs12->tsc_offset : 0));
2300 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301 vmcs_read64(TSC_OFFSET), offset);
2302 vmcs_write64(TSC_OFFSET, offset);
2306 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2308 u64 offset = vmcs_read64(TSC_OFFSET);
2310 vmcs_write64(TSC_OFFSET, offset + adjustment);
2311 if (is_guest_mode(vcpu)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2315 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316 offset + adjustment);
2319 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2321 return target_tsc - native_read_tsc();
2324 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2326 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2336 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2338 return nested && guest_cpuid_has_vmx(vcpu);
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
2351 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2368 /* pin-based controls */
2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2370 vmx->nested.nested_vmx_pinbased_ctls_low,
2371 vmx->nested.nested_vmx_pinbased_ctls_high);
2372 vmx->nested.nested_vmx_pinbased_ctls_low |=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374 vmx->nested.nested_vmx_pinbased_ctls_high &=
2375 PIN_BASED_EXT_INTR_MASK |
2376 PIN_BASED_NMI_EXITING |
2377 PIN_BASED_VIRTUAL_NMIS;
2378 vmx->nested.nested_vmx_pinbased_ctls_high |=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2380 PIN_BASED_VMX_PREEMPTION_TIMER;
2381 if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383 PIN_BASED_POSTED_INTR;
2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2387 vmx->nested.nested_vmx_exit_ctls_low,
2388 vmx->nested.nested_vmx_exit_ctls_high);
2389 vmx->nested.nested_vmx_exit_ctls_low =
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2392 vmx->nested.nested_vmx_exit_ctls_high &=
2393 #ifdef CONFIG_X86_64
2394 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2396 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2397 vmx->nested.nested_vmx_exit_ctls_high |=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2399 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2402 if (vmx_mpx_supported())
2403 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2405 /* We support free control of debug control saving. */
2406 vmx->nested.nested_vmx_true_exit_ctls_low =
2407 vmx->nested.nested_vmx_exit_ctls_low &
2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2412 vmx->nested.nested_vmx_entry_ctls_low,
2413 vmx->nested.nested_vmx_entry_ctls_high);
2414 vmx->nested.nested_vmx_entry_ctls_low =
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416 vmx->nested.nested_vmx_entry_ctls_high &=
2417 #ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE |
2420 VM_ENTRY_LOAD_IA32_PAT;
2421 vmx->nested.nested_vmx_entry_ctls_high |=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2423 if (vmx_mpx_supported())
2424 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2426 /* We support free control of debug control loading. */
2427 vmx->nested.nested_vmx_true_entry_ctls_low =
2428 vmx->nested.nested_vmx_entry_ctls_low &
2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2433 vmx->nested.nested_vmx_procbased_ctls_low,
2434 vmx->nested.nested_vmx_procbased_ctls_high);
2435 vmx->nested.nested_vmx_procbased_ctls_low =
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437 vmx->nested.nested_vmx_procbased_ctls_high &=
2438 CPU_BASED_VIRTUAL_INTR_PENDING |
2439 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2440 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442 CPU_BASED_CR3_STORE_EXITING |
2443 #ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2446 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2448 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2449 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2450 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2457 vmx->nested.nested_vmx_procbased_ctls_high |=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2459 CPU_BASED_USE_MSR_BITMAPS;
2461 /* We support free control of CR3 access interception. */
2462 vmx->nested.nested_vmx_true_procbased_ctls_low =
2463 vmx->nested.nested_vmx_procbased_ctls_low &
2464 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2468 vmx->nested.nested_vmx_secondary_ctls_low,
2469 vmx->nested.nested_vmx_secondary_ctls_high);
2470 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471 vmx->nested.nested_vmx_secondary_ctls_high &=
2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2473 SECONDARY_EXEC_RDTSCP |
2474 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2475 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2477 SECONDARY_EXEC_WBINVD_EXITING |
2478 SECONDARY_EXEC_XSAVES;
2481 /* nested EPT: emulate EPT also to L1 */
2482 vmx->nested.nested_vmx_secondary_ctls_high |=
2483 SECONDARY_EXEC_ENABLE_EPT;
2484 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2485 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2487 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2489 * For nested guests, we don't do anything specific
2490 * for single context invalidation. Hence, only advertise
2491 * support for global context invalidation.
2493 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2495 vmx->nested.nested_vmx_ept_caps = 0;
2497 if (enable_unrestricted_guest)
2498 vmx->nested.nested_vmx_secondary_ctls_high |=
2499 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2501 /* miscellaneous data */
2502 rdmsr(MSR_IA32_VMX_MISC,
2503 vmx->nested.nested_vmx_misc_low,
2504 vmx->nested.nested_vmx_misc_high);
2505 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2506 vmx->nested.nested_vmx_misc_low |=
2507 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2508 VMX_MISC_ACTIVITY_HLT;
2509 vmx->nested.nested_vmx_misc_high = 0;
2512 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2515 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2517 return ((control & high) | low) == control;
2520 static inline u64 vmx_control_msr(u32 low, u32 high)
2522 return low | ((u64)high << 32);
2525 /* Returns 0 on success, non-0 otherwise. */
2526 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2528 struct vcpu_vmx *vmx = to_vmx(vcpu);
2530 switch (msr_index) {
2531 case MSR_IA32_VMX_BASIC:
2533 * This MSR reports some information about VMX support. We
2534 * should return information about the VMX we emulate for the
2535 * guest, and the VMCS structure we give it - not about the
2536 * VMX support of the underlying hardware.
2538 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2539 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2540 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2542 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2543 case MSR_IA32_VMX_PINBASED_CTLS:
2544 *pdata = vmx_control_msr(
2545 vmx->nested.nested_vmx_pinbased_ctls_low,
2546 vmx->nested.nested_vmx_pinbased_ctls_high);
2548 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2549 *pdata = vmx_control_msr(
2550 vmx->nested.nested_vmx_true_procbased_ctls_low,
2551 vmx->nested.nested_vmx_procbased_ctls_high);
2553 case MSR_IA32_VMX_PROCBASED_CTLS:
2554 *pdata = vmx_control_msr(
2555 vmx->nested.nested_vmx_procbased_ctls_low,
2556 vmx->nested.nested_vmx_procbased_ctls_high);
2558 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2559 *pdata = vmx_control_msr(
2560 vmx->nested.nested_vmx_true_exit_ctls_low,
2561 vmx->nested.nested_vmx_exit_ctls_high);
2563 case MSR_IA32_VMX_EXIT_CTLS:
2564 *pdata = vmx_control_msr(
2565 vmx->nested.nested_vmx_exit_ctls_low,
2566 vmx->nested.nested_vmx_exit_ctls_high);
2568 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2569 *pdata = vmx_control_msr(
2570 vmx->nested.nested_vmx_true_entry_ctls_low,
2571 vmx->nested.nested_vmx_entry_ctls_high);
2573 case MSR_IA32_VMX_ENTRY_CTLS:
2574 *pdata = vmx_control_msr(
2575 vmx->nested.nested_vmx_entry_ctls_low,
2576 vmx->nested.nested_vmx_entry_ctls_high);
2578 case MSR_IA32_VMX_MISC:
2579 *pdata = vmx_control_msr(
2580 vmx->nested.nested_vmx_misc_low,
2581 vmx->nested.nested_vmx_misc_high);
2584 * These MSRs specify bits which the guest must keep fixed (on or off)
2585 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586 * We picked the standard core2 setting.
2588 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2590 case MSR_IA32_VMX_CR0_FIXED0:
2591 *pdata = VMXON_CR0_ALWAYSON;
2593 case MSR_IA32_VMX_CR0_FIXED1:
2596 case MSR_IA32_VMX_CR4_FIXED0:
2597 *pdata = VMXON_CR4_ALWAYSON;
2599 case MSR_IA32_VMX_CR4_FIXED1:
2602 case MSR_IA32_VMX_VMCS_ENUM:
2603 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2605 case MSR_IA32_VMX_PROCBASED_CTLS2:
2606 *pdata = vmx_control_msr(
2607 vmx->nested.nested_vmx_secondary_ctls_low,
2608 vmx->nested.nested_vmx_secondary_ctls_high);
2610 case MSR_IA32_VMX_EPT_VPID_CAP:
2611 /* Currently, no nested vpid support */
2612 *pdata = vmx->nested.nested_vmx_ept_caps;
2622 * Reads an msr value (of 'msr_index') into 'pdata'.
2623 * Returns 0 on success, non-0 otherwise.
2624 * Assumes vcpu_load() was already called.
2626 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2629 struct shared_msr_entry *msr;
2632 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2636 switch (msr_index) {
2637 #ifdef CONFIG_X86_64
2639 data = vmcs_readl(GUEST_FS_BASE);
2642 data = vmcs_readl(GUEST_GS_BASE);
2644 case MSR_KERNEL_GS_BASE:
2645 vmx_load_host_state(to_vmx(vcpu));
2646 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2650 return kvm_get_msr_common(vcpu, msr_index, pdata);
2652 data = guest_read_tsc();
2654 case MSR_IA32_SYSENTER_CS:
2655 data = vmcs_read32(GUEST_SYSENTER_CS);
2657 case MSR_IA32_SYSENTER_EIP:
2658 data = vmcs_readl(GUEST_SYSENTER_EIP);
2660 case MSR_IA32_SYSENTER_ESP:
2661 data = vmcs_readl(GUEST_SYSENTER_ESP);
2663 case MSR_IA32_BNDCFGS:
2664 if (!vmx_mpx_supported())
2666 data = vmcs_read64(GUEST_BNDCFGS);
2668 case MSR_IA32_FEATURE_CONTROL:
2669 if (!nested_vmx_allowed(vcpu))
2671 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2673 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2674 if (!nested_vmx_allowed(vcpu))
2676 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2678 if (!vmx_xsaves_supported())
2680 data = vcpu->arch.ia32_xss;
2683 if (!to_vmx(vcpu)->rdtscp_enabled)
2685 /* Otherwise falls through */
2687 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2692 return kvm_get_msr_common(vcpu, msr_index, pdata);
2699 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2702 * Writes msr value into into the appropriate "register".
2703 * Returns 0 on success, non-0 otherwise.
2704 * Assumes vcpu_load() was already called.
2706 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2708 struct vcpu_vmx *vmx = to_vmx(vcpu);
2709 struct shared_msr_entry *msr;
2711 u32 msr_index = msr_info->index;
2712 u64 data = msr_info->data;
2714 switch (msr_index) {
2716 ret = kvm_set_msr_common(vcpu, msr_info);
2718 #ifdef CONFIG_X86_64
2720 vmx_segment_cache_clear(vmx);
2721 vmcs_writel(GUEST_FS_BASE, data);
2724 vmx_segment_cache_clear(vmx);
2725 vmcs_writel(GUEST_GS_BASE, data);
2727 case MSR_KERNEL_GS_BASE:
2728 vmx_load_host_state(vmx);
2729 vmx->msr_guest_kernel_gs_base = data;
2732 case MSR_IA32_SYSENTER_CS:
2733 vmcs_write32(GUEST_SYSENTER_CS, data);
2735 case MSR_IA32_SYSENTER_EIP:
2736 vmcs_writel(GUEST_SYSENTER_EIP, data);
2738 case MSR_IA32_SYSENTER_ESP:
2739 vmcs_writel(GUEST_SYSENTER_ESP, data);
2741 case MSR_IA32_BNDCFGS:
2742 if (!vmx_mpx_supported())
2744 vmcs_write64(GUEST_BNDCFGS, data);
2747 kvm_write_tsc(vcpu, msr_info);
2749 case MSR_IA32_CR_PAT:
2750 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2751 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2753 vmcs_write64(GUEST_IA32_PAT, data);
2754 vcpu->arch.pat = data;
2757 ret = kvm_set_msr_common(vcpu, msr_info);
2759 case MSR_IA32_TSC_ADJUST:
2760 ret = kvm_set_msr_common(vcpu, msr_info);
2762 case MSR_IA32_FEATURE_CONTROL:
2763 if (!nested_vmx_allowed(vcpu) ||
2764 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2765 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2767 vmx->nested.msr_ia32_feature_control = data;
2768 if (msr_info->host_initiated && data == 0)
2769 vmx_leave_nested(vcpu);
2771 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2772 return 1; /* they are read-only */
2774 if (!vmx_xsaves_supported())
2777 * The only supported bit as of Skylake is bit 8, but
2778 * it is not supported on KVM.
2782 vcpu->arch.ia32_xss = data;
2783 if (vcpu->arch.ia32_xss != host_xss)
2784 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2785 vcpu->arch.ia32_xss, host_xss);
2787 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2790 if (!vmx->rdtscp_enabled)
2792 /* Check reserved bit, higher 32 bits should be zero */
2793 if ((data >> 32) != 0)
2795 /* Otherwise falls through */
2797 msr = find_msr_entry(vmx, msr_index);
2799 u64 old_msr_data = msr->data;
2801 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2803 ret = kvm_set_shared_msr(msr->index, msr->data,
2807 msr->data = old_msr_data;
2811 ret = kvm_set_msr_common(vcpu, msr_info);
2817 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2819 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2822 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2825 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2827 case VCPU_EXREG_PDPTR:
2829 ept_save_pdptrs(vcpu);
2836 static __init int cpu_has_kvm_support(void)
2838 return cpu_has_vmx();
2841 static __init int vmx_disabled_by_bios(void)
2845 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2846 if (msr & FEATURE_CONTROL_LOCKED) {
2847 /* launched w/ TXT and VMX disabled */
2848 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2851 /* launched w/o TXT and VMX only enabled w/ TXT */
2852 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2853 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2854 && !tboot_enabled()) {
2855 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2856 "activate TXT before enabling KVM\n");
2859 /* launched w/o TXT and VMX disabled */
2860 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2861 && !tboot_enabled())
2868 static void kvm_cpu_vmxon(u64 addr)
2870 asm volatile (ASM_VMX_VMXON_RAX
2871 : : "a"(&addr), "m"(addr)
2875 static int hardware_enable(void)
2877 int cpu = raw_smp_processor_id();
2878 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2881 if (cr4_read_shadow() & X86_CR4_VMXE)
2884 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2887 * Now we can enable the vmclear operation in kdump
2888 * since the loaded_vmcss_on_cpu list on this cpu
2889 * has been initialized.
2891 * Though the cpu is not in VMX operation now, there
2892 * is no problem to enable the vmclear operation
2893 * for the loaded_vmcss_on_cpu list is empty!
2895 crash_enable_local_vmclear(cpu);
2897 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2899 test_bits = FEATURE_CONTROL_LOCKED;
2900 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2901 if (tboot_enabled())
2902 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2904 if ((old & test_bits) != test_bits) {
2905 /* enable and lock */
2906 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2908 cr4_set_bits(X86_CR4_VMXE);
2910 if (vmm_exclusive) {
2911 kvm_cpu_vmxon(phys_addr);
2915 native_store_gdt(this_cpu_ptr(&host_gdt));
2920 static void vmclear_local_loaded_vmcss(void)
2922 int cpu = raw_smp_processor_id();
2923 struct loaded_vmcs *v, *n;
2925 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2926 loaded_vmcss_on_cpu_link)
2927 __loaded_vmcs_clear(v);
2931 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2934 static void kvm_cpu_vmxoff(void)
2936 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2939 static void hardware_disable(void)
2941 if (vmm_exclusive) {
2942 vmclear_local_loaded_vmcss();
2945 cr4_clear_bits(X86_CR4_VMXE);
2948 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2949 u32 msr, u32 *result)
2951 u32 vmx_msr_low, vmx_msr_high;
2952 u32 ctl = ctl_min | ctl_opt;
2954 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2956 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2957 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2959 /* Ensure minimum (required) set of control bits are supported. */
2967 static __init bool allow_1_setting(u32 msr, u32 ctl)
2969 u32 vmx_msr_low, vmx_msr_high;
2971 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2972 return vmx_msr_high & ctl;
2975 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2977 u32 vmx_msr_low, vmx_msr_high;
2978 u32 min, opt, min2, opt2;
2979 u32 _pin_based_exec_control = 0;
2980 u32 _cpu_based_exec_control = 0;
2981 u32 _cpu_based_2nd_exec_control = 0;
2982 u32 _vmexit_control = 0;
2983 u32 _vmentry_control = 0;
2985 min = CPU_BASED_HLT_EXITING |
2986 #ifdef CONFIG_X86_64
2987 CPU_BASED_CR8_LOAD_EXITING |
2988 CPU_BASED_CR8_STORE_EXITING |
2990 CPU_BASED_CR3_LOAD_EXITING |
2991 CPU_BASED_CR3_STORE_EXITING |
2992 CPU_BASED_USE_IO_BITMAPS |
2993 CPU_BASED_MOV_DR_EXITING |
2994 CPU_BASED_USE_TSC_OFFSETING |
2995 CPU_BASED_MWAIT_EXITING |
2996 CPU_BASED_MONITOR_EXITING |
2997 CPU_BASED_INVLPG_EXITING |
2998 CPU_BASED_RDPMC_EXITING;
3000 opt = CPU_BASED_TPR_SHADOW |
3001 CPU_BASED_USE_MSR_BITMAPS |
3002 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3003 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3004 &_cpu_based_exec_control) < 0)
3006 #ifdef CONFIG_X86_64
3007 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3008 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3009 ~CPU_BASED_CR8_STORE_EXITING;
3011 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3013 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3014 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3015 SECONDARY_EXEC_WBINVD_EXITING |
3016 SECONDARY_EXEC_ENABLE_VPID |
3017 SECONDARY_EXEC_ENABLE_EPT |
3018 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3019 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3020 SECONDARY_EXEC_RDTSCP |
3021 SECONDARY_EXEC_ENABLE_INVPCID |
3022 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3023 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3024 SECONDARY_EXEC_SHADOW_VMCS |
3025 SECONDARY_EXEC_XSAVES |
3026 SECONDARY_EXEC_ENABLE_PML;
3027 if (adjust_vmx_controls(min2, opt2,
3028 MSR_IA32_VMX_PROCBASED_CTLS2,
3029 &_cpu_based_2nd_exec_control) < 0)
3032 #ifndef CONFIG_X86_64
3033 if (!(_cpu_based_2nd_exec_control &
3034 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3035 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3038 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3039 _cpu_based_2nd_exec_control &= ~(
3040 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3041 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3042 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3044 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3045 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3047 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3048 CPU_BASED_CR3_STORE_EXITING |
3049 CPU_BASED_INVLPG_EXITING);
3050 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3051 vmx_capability.ept, vmx_capability.vpid);
3054 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3055 #ifdef CONFIG_X86_64
3056 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3058 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3059 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3060 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3061 &_vmexit_control) < 0)
3064 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3065 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3066 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3067 &_pin_based_exec_control) < 0)
3070 if (!(_cpu_based_2nd_exec_control &
3071 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3072 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3073 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3075 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3076 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3077 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3078 &_vmentry_control) < 0)
3081 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3083 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3084 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3087 #ifdef CONFIG_X86_64
3088 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3089 if (vmx_msr_high & (1u<<16))
3093 /* Require Write-Back (WB) memory type for VMCS accesses. */
3094 if (((vmx_msr_high >> 18) & 15) != 6)
3097 vmcs_conf->size = vmx_msr_high & 0x1fff;
3098 vmcs_conf->order = get_order(vmcs_config.size);
3099 vmcs_conf->revision_id = vmx_msr_low;
3101 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3102 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3103 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3104 vmcs_conf->vmexit_ctrl = _vmexit_control;
3105 vmcs_conf->vmentry_ctrl = _vmentry_control;
3107 cpu_has_load_ia32_efer =
3108 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3109 VM_ENTRY_LOAD_IA32_EFER)
3110 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3111 VM_EXIT_LOAD_IA32_EFER);
3113 cpu_has_load_perf_global_ctrl =
3114 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3115 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3116 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3117 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3120 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3121 * but due to arrata below it can't be used. Workaround is to use
3122 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3124 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3129 * BC86,AAY89,BD102 (model 44)
3133 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3134 switch (boot_cpu_data.x86_model) {
3140 cpu_has_load_perf_global_ctrl = false;
3141 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3142 "does not work properly. Using workaround\n");
3150 rdmsrl(MSR_IA32_XSS, host_xss);
3155 static struct vmcs *alloc_vmcs_cpu(int cpu)
3157 int node = cpu_to_node(cpu);
3161 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3164 vmcs = page_address(pages);
3165 memset(vmcs, 0, vmcs_config.size);
3166 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3170 static struct vmcs *alloc_vmcs(void)
3172 return alloc_vmcs_cpu(raw_smp_processor_id());
3175 static void free_vmcs(struct vmcs *vmcs)
3177 free_pages((unsigned long)vmcs, vmcs_config.order);
3181 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3183 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3185 if (!loaded_vmcs->vmcs)
3187 loaded_vmcs_clear(loaded_vmcs);
3188 free_vmcs(loaded_vmcs->vmcs);
3189 loaded_vmcs->vmcs = NULL;
3192 static void free_kvm_area(void)
3196 for_each_possible_cpu(cpu) {
3197 free_vmcs(per_cpu(vmxarea, cpu));
3198 per_cpu(vmxarea, cpu) = NULL;
3202 static void init_vmcs_shadow_fields(void)
3206 /* No checks for read only fields yet */
3208 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3209 switch (shadow_read_write_fields[i]) {
3211 if (!vmx_mpx_supported())
3219 shadow_read_write_fields[j] =
3220 shadow_read_write_fields[i];
3223 max_shadow_read_write_fields = j;
3225 /* shadowed fields guest access without vmexit */
3226 for (i = 0; i < max_shadow_read_write_fields; i++) {
3227 clear_bit(shadow_read_write_fields[i],
3228 vmx_vmwrite_bitmap);
3229 clear_bit(shadow_read_write_fields[i],
3232 for (i = 0; i < max_shadow_read_only_fields; i++)
3233 clear_bit(shadow_read_only_fields[i],
3237 static __init int alloc_kvm_area(void)
3241 for_each_possible_cpu(cpu) {
3244 vmcs = alloc_vmcs_cpu(cpu);
3250 per_cpu(vmxarea, cpu) = vmcs;
3255 static bool emulation_required(struct kvm_vcpu *vcpu)
3257 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3260 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3261 struct kvm_segment *save)
3263 if (!emulate_invalid_guest_state) {
3265 * CS and SS RPL should be equal during guest entry according
3266 * to VMX spec, but in reality it is not always so. Since vcpu
3267 * is in the middle of the transition from real mode to
3268 * protected mode it is safe to assume that RPL 0 is a good
3271 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3272 save->selector &= ~SEGMENT_RPL_MASK;
3273 save->dpl = save->selector & SEGMENT_RPL_MASK;
3276 vmx_set_segment(vcpu, save, seg);
3279 static void enter_pmode(struct kvm_vcpu *vcpu)
3281 unsigned long flags;
3282 struct vcpu_vmx *vmx = to_vmx(vcpu);
3285 * Update real mode segment cache. It may be not up-to-date if sement
3286 * register was written while vcpu was in a guest mode.
3288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3289 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3290 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3291 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3292 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3293 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3295 vmx->rmode.vm86_active = 0;
3297 vmx_segment_cache_clear(vmx);
3299 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3301 flags = vmcs_readl(GUEST_RFLAGS);
3302 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3303 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3304 vmcs_writel(GUEST_RFLAGS, flags);
3306 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3307 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3309 update_exception_bitmap(vcpu);
3311 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3312 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3313 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3314 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3315 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3316 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3319 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3321 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3322 struct kvm_segment var = *save;
3325 if (seg == VCPU_SREG_CS)
3328 if (!emulate_invalid_guest_state) {
3329 var.selector = var.base >> 4;
3330 var.base = var.base & 0xffff0;
3340 if (save->base & 0xf)
3341 printk_once(KERN_WARNING "kvm: segment base is not "
3342 "paragraph aligned when entering "
3343 "protected mode (seg=%d)", seg);
3346 vmcs_write16(sf->selector, var.selector);
3347 vmcs_write32(sf->base, var.base);
3348 vmcs_write32(sf->limit, var.limit);
3349 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3352 static void enter_rmode(struct kvm_vcpu *vcpu)
3354 unsigned long flags;
3355 struct vcpu_vmx *vmx = to_vmx(vcpu);
3357 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3358 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3359 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3360 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3361 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3362 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3363 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3365 vmx->rmode.vm86_active = 1;
3368 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3369 * vcpu. Warn the user that an update is overdue.
3371 if (!vcpu->kvm->arch.tss_addr)
3372 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3373 "called before entering vcpu\n");
3375 vmx_segment_cache_clear(vmx);
3377 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3378 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3379 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3381 flags = vmcs_readl(GUEST_RFLAGS);
3382 vmx->rmode.save_rflags = flags;
3384 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3386 vmcs_writel(GUEST_RFLAGS, flags);
3387 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3388 update_exception_bitmap(vcpu);
3390 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3391 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3392 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3393 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3394 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3395 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3397 kvm_mmu_reset_context(vcpu);
3400 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3402 struct vcpu_vmx *vmx = to_vmx(vcpu);
3403 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3409 * Force kernel_gs_base reloading before EFER changes, as control
3410 * of this msr depends on is_long_mode().
3412 vmx_load_host_state(to_vmx(vcpu));
3413 vcpu->arch.efer = efer;
3414 if (efer & EFER_LMA) {
3415 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3418 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3420 msr->data = efer & ~EFER_LME;
3425 #ifdef CONFIG_X86_64
3427 static void enter_lmode(struct kvm_vcpu *vcpu)
3431 vmx_segment_cache_clear(to_vmx(vcpu));
3433 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3434 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3435 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3437 vmcs_write32(GUEST_TR_AR_BYTES,
3438 (guest_tr_ar & ~AR_TYPE_MASK)
3439 | AR_TYPE_BUSY_64_TSS);
3441 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3444 static void exit_lmode(struct kvm_vcpu *vcpu)
3446 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3447 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3452 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3454 vpid_sync_context(to_vmx(vcpu));
3456 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3458 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3462 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3464 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3466 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3467 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3470 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3472 if (enable_ept && is_paging(vcpu))
3473 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3474 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3477 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3479 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3481 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3482 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3485 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3487 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3489 if (!test_bit(VCPU_EXREG_PDPTR,
3490 (unsigned long *)&vcpu->arch.regs_dirty))
3493 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3494 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3495 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3496 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3497 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3501 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3503 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3505 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3506 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3507 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3508 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3509 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3512 __set_bit(VCPU_EXREG_PDPTR,
3513 (unsigned long *)&vcpu->arch.regs_avail);
3514 __set_bit(VCPU_EXREG_PDPTR,
3515 (unsigned long *)&vcpu->arch.regs_dirty);
3518 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3520 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3522 struct kvm_vcpu *vcpu)
3524 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3525 vmx_decache_cr3(vcpu);
3526 if (!(cr0 & X86_CR0_PG)) {
3527 /* From paging/starting to nonpaging */
3528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3529 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3530 (CPU_BASED_CR3_LOAD_EXITING |
3531 CPU_BASED_CR3_STORE_EXITING));
3532 vcpu->arch.cr0 = cr0;
3533 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3534 } else if (!is_paging(vcpu)) {
3535 /* From nonpaging to paging */
3536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3537 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3538 ~(CPU_BASED_CR3_LOAD_EXITING |
3539 CPU_BASED_CR3_STORE_EXITING));
3540 vcpu->arch.cr0 = cr0;
3541 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3544 if (!(cr0 & X86_CR0_WP))
3545 *hw_cr0 &= ~X86_CR0_WP;
3548 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3550 struct vcpu_vmx *vmx = to_vmx(vcpu);
3551 unsigned long hw_cr0;
3553 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3554 if (enable_unrestricted_guest)
3555 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3557 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3559 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3562 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3566 #ifdef CONFIG_X86_64
3567 if (vcpu->arch.efer & EFER_LME) {
3568 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3570 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3576 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3578 if (!vcpu->fpu_active)
3579 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3581 vmcs_writel(CR0_READ_SHADOW, cr0);
3582 vmcs_writel(GUEST_CR0, hw_cr0);
3583 vcpu->arch.cr0 = cr0;
3585 /* depends on vcpu->arch.cr0 to be set to a new value */
3586 vmx->emulation_required = emulation_required(vcpu);
3589 static u64 construct_eptp(unsigned long root_hpa)
3593 /* TODO write the value reading from MSR */
3594 eptp = VMX_EPT_DEFAULT_MT |
3595 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3596 if (enable_ept_ad_bits)
3597 eptp |= VMX_EPT_AD_ENABLE_BIT;
3598 eptp |= (root_hpa & PAGE_MASK);
3603 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3605 unsigned long guest_cr3;
3610 eptp = construct_eptp(cr3);
3611 vmcs_write64(EPT_POINTER, eptp);
3612 if (is_paging(vcpu) || is_guest_mode(vcpu))
3613 guest_cr3 = kvm_read_cr3(vcpu);
3615 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3616 ept_load_pdptrs(vcpu);
3619 vmx_flush_tlb(vcpu);
3620 vmcs_writel(GUEST_CR3, guest_cr3);
3623 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3626 * Pass through host's Machine Check Enable value to hw_cr4, which
3627 * is in force while we are in guest mode. Do not let guests control
3628 * this bit, even if host CR4.MCE == 0.
3630 unsigned long hw_cr4 =
3631 (cr4_read_shadow() & X86_CR4_MCE) |
3632 (cr4 & ~X86_CR4_MCE) |
3633 (to_vmx(vcpu)->rmode.vm86_active ?
3634 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3636 if (cr4 & X86_CR4_VMXE) {
3638 * To use VMXON (and later other VMX instructions), a guest
3639 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3640 * So basically the check on whether to allow nested VMX
3643 if (!nested_vmx_allowed(vcpu))
3646 if (to_vmx(vcpu)->nested.vmxon &&
3647 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3650 vcpu->arch.cr4 = cr4;
3652 if (!is_paging(vcpu)) {
3653 hw_cr4 &= ~X86_CR4_PAE;
3654 hw_cr4 |= X86_CR4_PSE;
3656 * SMEP/SMAP is disabled if CPU is in non-paging mode
3657 * in hardware. However KVM always uses paging mode to
3658 * emulate guest non-paging mode with TDP.
3659 * To emulate this behavior, SMEP/SMAP needs to be
3660 * manually disabled when guest switches to non-paging
3663 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3664 } else if (!(cr4 & X86_CR4_PAE)) {
3665 hw_cr4 &= ~X86_CR4_PAE;
3669 vmcs_writel(CR4_READ_SHADOW, cr4);
3670 vmcs_writel(GUEST_CR4, hw_cr4);
3674 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3675 struct kvm_segment *var, int seg)
3677 struct vcpu_vmx *vmx = to_vmx(vcpu);
3680 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3681 *var = vmx->rmode.segs[seg];
3682 if (seg == VCPU_SREG_TR
3683 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3685 var->base = vmx_read_guest_seg_base(vmx, seg);
3686 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3689 var->base = vmx_read_guest_seg_base(vmx, seg);
3690 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3691 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3692 ar = vmx_read_guest_seg_ar(vmx, seg);
3693 var->unusable = (ar >> 16) & 1;
3694 var->type = ar & 15;
3695 var->s = (ar >> 4) & 1;
3696 var->dpl = (ar >> 5) & 3;
3698 * Some userspaces do not preserve unusable property. Since usable
3699 * segment has to be present according to VMX spec we can use present
3700 * property to amend userspace bug by making unusable segment always
3701 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3702 * segment as unusable.
3704 var->present = !var->unusable;
3705 var->avl = (ar >> 12) & 1;
3706 var->l = (ar >> 13) & 1;
3707 var->db = (ar >> 14) & 1;
3708 var->g = (ar >> 15) & 1;
3711 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3713 struct kvm_segment s;
3715 if (to_vmx(vcpu)->rmode.vm86_active) {
3716 vmx_get_segment(vcpu, &s, seg);
3719 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3722 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3726 if (unlikely(vmx->rmode.vm86_active))
3729 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3734 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3738 if (var->unusable || !var->present)
3741 ar = var->type & 15;
3742 ar |= (var->s & 1) << 4;
3743 ar |= (var->dpl & 3) << 5;
3744 ar |= (var->present & 1) << 7;
3745 ar |= (var->avl & 1) << 12;
3746 ar |= (var->l & 1) << 13;
3747 ar |= (var->db & 1) << 14;
3748 ar |= (var->g & 1) << 15;
3754 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3755 struct kvm_segment *var, int seg)
3757 struct vcpu_vmx *vmx = to_vmx(vcpu);
3758 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3760 vmx_segment_cache_clear(vmx);
3762 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3763 vmx->rmode.segs[seg] = *var;
3764 if (seg == VCPU_SREG_TR)
3765 vmcs_write16(sf->selector, var->selector);
3767 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3771 vmcs_writel(sf->base, var->base);
3772 vmcs_write32(sf->limit, var->limit);
3773 vmcs_write16(sf->selector, var->selector);
3776 * Fix the "Accessed" bit in AR field of segment registers for older
3778 * IA32 arch specifies that at the time of processor reset the
3779 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3780 * is setting it to 0 in the userland code. This causes invalid guest
3781 * state vmexit when "unrestricted guest" mode is turned on.
3782 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3783 * tree. Newer qemu binaries with that qemu fix would not need this
3786 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3787 var->type |= 0x1; /* Accessed */
3789 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3792 vmx->emulation_required = emulation_required(vcpu);
3795 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3797 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3799 *db = (ar >> 14) & 1;
3800 *l = (ar >> 13) & 1;
3803 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3805 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3806 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3809 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3811 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3812 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3815 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3817 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3818 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3821 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3823 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3824 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3827 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3829 struct kvm_segment var;
3832 vmx_get_segment(vcpu, &var, seg);
3834 if (seg == VCPU_SREG_CS)
3836 ar = vmx_segment_access_rights(&var);
3838 if (var.base != (var.selector << 4))
3840 if (var.limit != 0xffff)
3848 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3850 struct kvm_segment cs;
3851 unsigned int cs_rpl;
3853 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3854 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3858 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3862 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3863 if (cs.dpl > cs_rpl)
3866 if (cs.dpl != cs_rpl)
3872 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3876 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3878 struct kvm_segment ss;
3879 unsigned int ss_rpl;
3881 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3882 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3886 if (ss.type != 3 && ss.type != 7)
3890 if (ss.dpl != ss_rpl) /* DPL != RPL */
3898 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3900 struct kvm_segment var;
3903 vmx_get_segment(vcpu, &var, seg);
3904 rpl = var.selector & SEGMENT_RPL_MASK;
3912 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3913 if (var.dpl < rpl) /* DPL < RPL */
3917 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3923 static bool tr_valid(struct kvm_vcpu *vcpu)
3925 struct kvm_segment tr;
3927 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3931 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3933 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3941 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3943 struct kvm_segment ldtr;
3945 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3949 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3959 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3961 struct kvm_segment cs, ss;
3963 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3964 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3966 return ((cs.selector & SEGMENT_RPL_MASK) ==
3967 (ss.selector & SEGMENT_RPL_MASK));
3971 * Check if guest state is valid. Returns true if valid, false if
3973 * We assume that registers are always usable
3975 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3977 if (enable_unrestricted_guest)
3980 /* real mode guest state checks */
3981 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3982 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3984 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3986 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3988 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3990 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3992 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3995 /* protected mode guest state checks */
3996 if (!cs_ss_rpl_check(vcpu))
3998 if (!code_segment_valid(vcpu))
4000 if (!stack_segment_valid(vcpu))
4002 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4004 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4006 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4008 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4010 if (!tr_valid(vcpu))
4012 if (!ldtr_valid(vcpu))
4016 * - Add checks on RIP
4017 * - Add checks on RFLAGS
4023 static int init_rmode_tss(struct kvm *kvm)
4029 idx = srcu_read_lock(&kvm->srcu);
4030 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4031 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4034 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4035 r = kvm_write_guest_page(kvm, fn++, &data,
4036 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4039 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4042 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4046 r = kvm_write_guest_page(kvm, fn, &data,
4047 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4050 srcu_read_unlock(&kvm->srcu, idx);
4054 static int init_rmode_identity_map(struct kvm *kvm)
4057 pfn_t identity_map_pfn;
4063 /* Protect kvm->arch.ept_identity_pagetable_done. */
4064 mutex_lock(&kvm->slots_lock);
4066 if (likely(kvm->arch.ept_identity_pagetable_done))
4069 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4071 r = alloc_identity_pagetable(kvm);
4075 idx = srcu_read_lock(&kvm->srcu);
4076 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4079 /* Set up identity-mapping pagetable for EPT in real mode */
4080 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4081 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4082 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4083 r = kvm_write_guest_page(kvm, identity_map_pfn,
4084 &tmp, i * sizeof(tmp), sizeof(tmp));
4088 kvm->arch.ept_identity_pagetable_done = true;
4091 srcu_read_unlock(&kvm->srcu, idx);
4094 mutex_unlock(&kvm->slots_lock);
4098 static void seg_setup(int seg)
4100 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4103 vmcs_write16(sf->selector, 0);
4104 vmcs_writel(sf->base, 0);
4105 vmcs_write32(sf->limit, 0xffff);
4107 if (seg == VCPU_SREG_CS)
4108 ar |= 0x08; /* code segment */
4110 vmcs_write32(sf->ar_bytes, ar);
4113 static int alloc_apic_access_page(struct kvm *kvm)
4116 struct kvm_userspace_memory_region kvm_userspace_mem;
4119 mutex_lock(&kvm->slots_lock);
4120 if (kvm->arch.apic_access_page_done)
4122 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4123 kvm_userspace_mem.flags = 0;
4124 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4125 kvm_userspace_mem.memory_size = PAGE_SIZE;
4126 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4130 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4131 if (is_error_page(page)) {
4137 * Do not pin the page in memory, so that memory hot-unplug
4138 * is able to migrate it.
4141 kvm->arch.apic_access_page_done = true;
4143 mutex_unlock(&kvm->slots_lock);
4147 static int alloc_identity_pagetable(struct kvm *kvm)
4149 /* Called with kvm->slots_lock held. */
4151 struct kvm_userspace_memory_region kvm_userspace_mem;
4154 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4156 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4157 kvm_userspace_mem.flags = 0;
4158 kvm_userspace_mem.guest_phys_addr =
4159 kvm->arch.ept_identity_map_addr;
4160 kvm_userspace_mem.memory_size = PAGE_SIZE;
4161 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4166 static void allocate_vpid(struct vcpu_vmx *vmx)
4173 spin_lock(&vmx_vpid_lock);
4174 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4175 if (vpid < VMX_NR_VPIDS) {
4177 __set_bit(vpid, vmx_vpid_bitmap);
4179 spin_unlock(&vmx_vpid_lock);
4182 static void free_vpid(struct vcpu_vmx *vmx)
4186 spin_lock(&vmx_vpid_lock);
4188 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4189 spin_unlock(&vmx_vpid_lock);
4192 #define MSR_TYPE_R 1
4193 #define MSR_TYPE_W 2
4194 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4197 int f = sizeof(unsigned long);
4199 if (!cpu_has_vmx_msr_bitmap())
4203 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4204 * have the write-low and read-high bitmap offsets the wrong way round.
4205 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4207 if (msr <= 0x1fff) {
4208 if (type & MSR_TYPE_R)
4210 __clear_bit(msr, msr_bitmap + 0x000 / f);
4212 if (type & MSR_TYPE_W)
4214 __clear_bit(msr, msr_bitmap + 0x800 / f);
4216 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4218 if (type & MSR_TYPE_R)
4220 __clear_bit(msr, msr_bitmap + 0x400 / f);
4222 if (type & MSR_TYPE_W)
4224 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4229 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4232 int f = sizeof(unsigned long);
4234 if (!cpu_has_vmx_msr_bitmap())
4238 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4239 * have the write-low and read-high bitmap offsets the wrong way round.
4240 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4242 if (msr <= 0x1fff) {
4243 if (type & MSR_TYPE_R)
4245 __set_bit(msr, msr_bitmap + 0x000 / f);
4247 if (type & MSR_TYPE_W)
4249 __set_bit(msr, msr_bitmap + 0x800 / f);
4251 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4253 if (type & MSR_TYPE_R)
4255 __set_bit(msr, msr_bitmap + 0x400 / f);
4257 if (type & MSR_TYPE_W)
4259 __set_bit(msr, msr_bitmap + 0xc00 / f);
4265 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4266 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4268 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4269 unsigned long *msr_bitmap_nested,
4272 int f = sizeof(unsigned long);
4274 if (!cpu_has_vmx_msr_bitmap()) {
4280 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4281 * have the write-low and read-high bitmap offsets the wrong way round.
4282 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4284 if (msr <= 0x1fff) {
4285 if (type & MSR_TYPE_R &&
4286 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4288 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4290 if (type & MSR_TYPE_W &&
4291 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4293 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4295 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4297 if (type & MSR_TYPE_R &&
4298 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4300 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4302 if (type & MSR_TYPE_W &&
4303 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4305 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4310 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4313 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4314 msr, MSR_TYPE_R | MSR_TYPE_W);
4315 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4316 msr, MSR_TYPE_R | MSR_TYPE_W);
4319 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4321 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4323 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4327 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4329 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4331 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4335 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4337 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4339 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4343 static int vmx_vm_has_apicv(struct kvm *kvm)
4345 return enable_apicv && irqchip_in_kernel(kvm);
4348 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4350 struct vcpu_vmx *vmx = to_vmx(vcpu);
4355 if (vmx->nested.pi_desc &&
4356 vmx->nested.pi_pending) {
4357 vmx->nested.pi_pending = false;
4358 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4361 max_irr = find_last_bit(
4362 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4367 vapic_page = kmap(vmx->nested.virtual_apic_page);
4372 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4373 kunmap(vmx->nested.virtual_apic_page);
4375 status = vmcs_read16(GUEST_INTR_STATUS);
4376 if ((u8)max_irr > ((u8)status & 0xff)) {
4378 status |= (u8)max_irr;
4379 vmcs_write16(GUEST_INTR_STATUS, status);
4385 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4388 if (vcpu->mode == IN_GUEST_MODE) {
4389 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4390 POSTED_INTR_VECTOR);
4397 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4400 struct vcpu_vmx *vmx = to_vmx(vcpu);
4402 if (is_guest_mode(vcpu) &&
4403 vector == vmx->nested.posted_intr_nv) {
4404 /* the PIR and ON have been set by L1. */
4405 kvm_vcpu_trigger_posted_interrupt(vcpu);
4407 * If a posted intr is not recognized by hardware,
4408 * we will accomplish it in the next vmentry.
4410 vmx->nested.pi_pending = true;
4411 kvm_make_request(KVM_REQ_EVENT, vcpu);
4417 * Send interrupt to vcpu via posted interrupt way.
4418 * 1. If target vcpu is running(non-root mode), send posted interrupt
4419 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4420 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4421 * interrupt from PIR in next vmentry.
4423 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4425 struct vcpu_vmx *vmx = to_vmx(vcpu);
4428 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4432 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4435 r = pi_test_and_set_on(&vmx->pi_desc);
4436 kvm_make_request(KVM_REQ_EVENT, vcpu);
4437 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4438 kvm_vcpu_kick(vcpu);
4441 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4443 struct vcpu_vmx *vmx = to_vmx(vcpu);
4445 if (!pi_test_and_clear_on(&vmx->pi_desc))
4448 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4451 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4457 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4458 * will not change in the lifetime of the guest.
4459 * Note that host-state that does change is set elsewhere. E.g., host-state
4460 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4462 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4469 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4470 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4472 /* Save the most likely value for this task's CR4 in the VMCS. */
4473 cr4 = cr4_read_shadow();
4474 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4475 vmx->host_state.vmcs_host_cr4 = cr4;
4477 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4478 #ifdef CONFIG_X86_64
4480 * Load null selectors, so we can avoid reloading them in
4481 * __vmx_load_host_state(), in case userspace uses the null selectors
4482 * too (the expected case).
4484 vmcs_write16(HOST_DS_SELECTOR, 0);
4485 vmcs_write16(HOST_ES_SELECTOR, 0);
4487 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4488 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4490 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4491 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4493 native_store_idt(&dt);
4494 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4495 vmx->host_idt_base = dt.address;
4497 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4499 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4500 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4501 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4502 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4504 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4505 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4506 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4510 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4512 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4514 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4515 if (is_guest_mode(&vmx->vcpu))
4516 vmx->vcpu.arch.cr4_guest_owned_bits &=
4517 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4518 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4521 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4523 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4525 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4526 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4527 return pin_based_exec_ctrl;
4530 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4532 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4534 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4535 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4537 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4538 exec_control &= ~CPU_BASED_TPR_SHADOW;
4539 #ifdef CONFIG_X86_64
4540 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4541 CPU_BASED_CR8_LOAD_EXITING;
4545 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4546 CPU_BASED_CR3_LOAD_EXITING |
4547 CPU_BASED_INVLPG_EXITING;
4548 return exec_control;
4551 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4553 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4554 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4555 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4557 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4559 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4560 enable_unrestricted_guest = 0;
4561 /* Enable INVPCID for non-ept guests may cause performance regression. */
4562 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4564 if (!enable_unrestricted_guest)
4565 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4567 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4568 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4569 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4570 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4571 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4572 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4574 We can NOT enable shadow_vmcs here because we don't have yet
4577 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4578 /* PML is enabled/disabled in creating/destorying vcpu */
4579 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4581 return exec_control;
4584 static void ept_set_mmio_spte_mask(void)
4587 * EPT Misconfigurations can be generated if the value of bits 2:0
4588 * of an EPT paging-structure entry is 110b (write/execute).
4589 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4592 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4595 #define VMX_XSS_EXIT_BITMAP 0
4597 * Sets up the vmcs for emulated real mode.
4599 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4601 #ifdef CONFIG_X86_64
4607 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4608 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4610 if (enable_shadow_vmcs) {
4611 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4612 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4614 if (cpu_has_vmx_msr_bitmap())
4615 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4617 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4620 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4622 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4624 if (cpu_has_secondary_exec_ctrls()) {
4625 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4626 vmx_secondary_exec_control(vmx));
4629 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4630 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4631 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4632 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4633 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4635 vmcs_write16(GUEST_INTR_STATUS, 0);
4637 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4638 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4642 vmcs_write32(PLE_GAP, ple_gap);
4643 vmx->ple_window = ple_window;
4644 vmx->ple_window_dirty = true;
4647 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4648 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4649 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4651 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4652 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4653 vmx_set_constant_host_state(vmx);
4654 #ifdef CONFIG_X86_64
4655 rdmsrl(MSR_FS_BASE, a);
4656 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4657 rdmsrl(MSR_GS_BASE, a);
4658 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4660 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4661 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4664 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4665 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4666 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4667 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4668 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4670 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4671 u32 msr_low, msr_high;
4673 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4674 host_pat = msr_low | ((u64) msr_high << 32);
4675 /* Write the default value follow host pat */
4676 vmcs_write64(GUEST_IA32_PAT, host_pat);
4677 /* Keep arch.pat sync with GUEST_IA32_PAT */
4678 vmx->vcpu.arch.pat = host_pat;
4681 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4682 u32 index = vmx_msr_index[i];
4683 u32 data_low, data_high;
4686 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4688 if (wrmsr_safe(index, data_low, data_high) < 0)
4690 vmx->guest_msrs[j].index = i;
4691 vmx->guest_msrs[j].data = 0;
4692 vmx->guest_msrs[j].mask = -1ull;
4697 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4699 /* 22.2.1, 20.8.1 */
4700 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4702 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4703 set_cr4_guest_host_mask(vmx);
4705 if (vmx_xsaves_supported())
4706 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4711 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4713 struct vcpu_vmx *vmx = to_vmx(vcpu);
4714 struct msr_data apic_base_msr;
4716 vmx->rmode.vm86_active = 0;
4718 vmx->soft_vnmi_blocked = 0;
4720 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4721 kvm_set_cr8(&vmx->vcpu, 0);
4722 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4723 if (kvm_vcpu_is_reset_bsp(&vmx->vcpu))
4724 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4725 apic_base_msr.host_initiated = true;
4726 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4728 vmx_segment_cache_clear(vmx);
4730 seg_setup(VCPU_SREG_CS);
4731 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4732 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4734 seg_setup(VCPU_SREG_DS);
4735 seg_setup(VCPU_SREG_ES);
4736 seg_setup(VCPU_SREG_FS);
4737 seg_setup(VCPU_SREG_GS);
4738 seg_setup(VCPU_SREG_SS);
4740 vmcs_write16(GUEST_TR_SELECTOR, 0);
4741 vmcs_writel(GUEST_TR_BASE, 0);
4742 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4743 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4745 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4746 vmcs_writel(GUEST_LDTR_BASE, 0);
4747 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4748 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4750 vmcs_write32(GUEST_SYSENTER_CS, 0);
4751 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4752 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4754 vmcs_writel(GUEST_RFLAGS, 0x02);
4755 kvm_rip_write(vcpu, 0xfff0);
4757 vmcs_writel(GUEST_GDTR_BASE, 0);
4758 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4760 vmcs_writel(GUEST_IDTR_BASE, 0);
4761 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4763 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4764 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4765 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4767 /* Special registers */
4768 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4772 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4774 if (cpu_has_vmx_tpr_shadow()) {
4775 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4776 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4777 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4778 __pa(vmx->vcpu.arch.apic->regs));
4779 vmcs_write32(TPR_THRESHOLD, 0);
4782 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4784 if (vmx_vm_has_apicv(vcpu->kvm))
4785 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4788 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4790 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4791 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4792 vmx_set_cr4(&vmx->vcpu, 0);
4793 vmx_set_efer(&vmx->vcpu, 0);
4794 vmx_fpu_activate(&vmx->vcpu);
4795 update_exception_bitmap(&vmx->vcpu);
4797 vpid_sync_context(vmx);
4801 * In nested virtualization, check if L1 asked to exit on external interrupts.
4802 * For most existing hypervisors, this will always return true.
4804 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4806 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4807 PIN_BASED_EXT_INTR_MASK;
4811 * In nested virtualization, check if L1 has set
4812 * VM_EXIT_ACK_INTR_ON_EXIT
4814 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4816 return get_vmcs12(vcpu)->vm_exit_controls &
4817 VM_EXIT_ACK_INTR_ON_EXIT;
4820 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4822 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4823 PIN_BASED_NMI_EXITING;
4826 static void enable_irq_window(struct kvm_vcpu *vcpu)
4828 u32 cpu_based_vm_exec_control;
4830 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4831 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4832 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4835 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4837 u32 cpu_based_vm_exec_control;
4839 if (!cpu_has_virtual_nmis() ||
4840 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4841 enable_irq_window(vcpu);
4845 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4846 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4847 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4850 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4852 struct vcpu_vmx *vmx = to_vmx(vcpu);
4854 int irq = vcpu->arch.interrupt.nr;
4856 trace_kvm_inj_virq(irq);
4858 ++vcpu->stat.irq_injections;
4859 if (vmx->rmode.vm86_active) {
4861 if (vcpu->arch.interrupt.soft)
4862 inc_eip = vcpu->arch.event_exit_inst_len;
4863 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4864 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4867 intr = irq | INTR_INFO_VALID_MASK;
4868 if (vcpu->arch.interrupt.soft) {
4869 intr |= INTR_TYPE_SOFT_INTR;
4870 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4871 vmx->vcpu.arch.event_exit_inst_len);
4873 intr |= INTR_TYPE_EXT_INTR;
4874 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4877 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4879 struct vcpu_vmx *vmx = to_vmx(vcpu);
4881 if (is_guest_mode(vcpu))
4884 if (!cpu_has_virtual_nmis()) {
4886 * Tracking the NMI-blocked state in software is built upon
4887 * finding the next open IRQ window. This, in turn, depends on
4888 * well-behaving guests: They have to keep IRQs disabled at
4889 * least as long as the NMI handler runs. Otherwise we may
4890 * cause NMI nesting, maybe breaking the guest. But as this is
4891 * highly unlikely, we can live with the residual risk.
4893 vmx->soft_vnmi_blocked = 1;
4894 vmx->vnmi_blocked_time = 0;
4897 ++vcpu->stat.nmi_injections;
4898 vmx->nmi_known_unmasked = false;
4899 if (vmx->rmode.vm86_active) {
4900 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4901 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4904 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4905 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4908 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4910 if (!cpu_has_virtual_nmis())
4911 return to_vmx(vcpu)->soft_vnmi_blocked;
4912 if (to_vmx(vcpu)->nmi_known_unmasked)
4914 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4917 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4919 struct vcpu_vmx *vmx = to_vmx(vcpu);
4921 if (!cpu_has_virtual_nmis()) {
4922 if (vmx->soft_vnmi_blocked != masked) {
4923 vmx->soft_vnmi_blocked = masked;
4924 vmx->vnmi_blocked_time = 0;
4927 vmx->nmi_known_unmasked = !masked;
4929 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4930 GUEST_INTR_STATE_NMI);
4932 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4933 GUEST_INTR_STATE_NMI);
4937 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4939 if (to_vmx(vcpu)->nested.nested_run_pending)
4942 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4945 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4946 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4947 | GUEST_INTR_STATE_NMI));
4950 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4952 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4953 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4954 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4955 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4958 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4961 struct kvm_userspace_memory_region tss_mem = {
4962 .slot = TSS_PRIVATE_MEMSLOT,
4963 .guest_phys_addr = addr,
4964 .memory_size = PAGE_SIZE * 3,
4968 ret = kvm_set_memory_region(kvm, &tss_mem);
4971 kvm->arch.tss_addr = addr;
4972 return init_rmode_tss(kvm);
4975 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4980 * Update instruction length as we may reinject the exception
4981 * from user space while in guest debugging mode.
4983 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4984 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4985 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4989 if (vcpu->guest_debug &
4990 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5007 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5008 int vec, u32 err_code)
5011 * Instruction with address size override prefix opcode 0x67
5012 * Cause the #SS fault with 0 error code in VM86 mode.
5014 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5015 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5016 if (vcpu->arch.halt_request) {
5017 vcpu->arch.halt_request = 0;
5018 return kvm_vcpu_halt(vcpu);
5026 * Forward all other exceptions that are valid in real mode.
5027 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5028 * the required debugging infrastructure rework.
5030 kvm_queue_exception(vcpu, vec);
5035 * Trigger machine check on the host. We assume all the MSRs are already set up
5036 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5037 * We pass a fake environment to the machine check handler because we want
5038 * the guest to be always treated like user space, no matter what context
5039 * it used internally.
5041 static void kvm_machine_check(void)
5043 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5044 struct pt_regs regs = {
5045 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5046 .flags = X86_EFLAGS_IF,
5049 do_machine_check(®s, 0);
5053 static int handle_machine_check(struct kvm_vcpu *vcpu)
5055 /* already handled by vcpu_run */
5059 static int handle_exception(struct kvm_vcpu *vcpu)
5061 struct vcpu_vmx *vmx = to_vmx(vcpu);
5062 struct kvm_run *kvm_run = vcpu->run;
5063 u32 intr_info, ex_no, error_code;
5064 unsigned long cr2, rip, dr6;
5066 enum emulation_result er;
5068 vect_info = vmx->idt_vectoring_info;
5069 intr_info = vmx->exit_intr_info;
5071 if (is_machine_check(intr_info))
5072 return handle_machine_check(vcpu);
5074 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5075 return 1; /* already handled by vmx_vcpu_run() */
5077 if (is_no_device(intr_info)) {
5078 vmx_fpu_activate(vcpu);
5082 if (is_invalid_opcode(intr_info)) {
5083 if (is_guest_mode(vcpu)) {
5084 kvm_queue_exception(vcpu, UD_VECTOR);
5087 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5088 if (er != EMULATE_DONE)
5089 kvm_queue_exception(vcpu, UD_VECTOR);
5094 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5095 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5098 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5099 * MMIO, it is better to report an internal error.
5100 * See the comments in vmx_handle_exit.
5102 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5103 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5104 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5105 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5106 vcpu->run->internal.ndata = 3;
5107 vcpu->run->internal.data[0] = vect_info;
5108 vcpu->run->internal.data[1] = intr_info;
5109 vcpu->run->internal.data[2] = error_code;
5113 if (is_page_fault(intr_info)) {
5114 /* EPT won't cause page fault directly */
5116 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5117 trace_kvm_page_fault(cr2, error_code);
5119 if (kvm_event_needs_reinjection(vcpu))
5120 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5121 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5124 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5126 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5127 return handle_rmode_exception(vcpu, ex_no, error_code);
5131 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5132 if (!(vcpu->guest_debug &
5133 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5134 vcpu->arch.dr6 &= ~15;
5135 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5136 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5137 skip_emulated_instruction(vcpu);
5139 kvm_queue_exception(vcpu, DB_VECTOR);
5142 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5143 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5147 * Update instruction length as we may reinject #BP from
5148 * user space while in guest debugging mode. Reading it for
5149 * #DB as well causes no harm, it is not used in that case.
5151 vmx->vcpu.arch.event_exit_inst_len =
5152 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5153 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5154 rip = kvm_rip_read(vcpu);
5155 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5156 kvm_run->debug.arch.exception = ex_no;
5159 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5160 kvm_run->ex.exception = ex_no;
5161 kvm_run->ex.error_code = error_code;
5167 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5169 ++vcpu->stat.irq_exits;
5173 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5175 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5179 static int handle_io(struct kvm_vcpu *vcpu)
5181 unsigned long exit_qualification;
5182 int size, in, string;
5185 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5186 string = (exit_qualification & 16) != 0;
5187 in = (exit_qualification & 8) != 0;
5189 ++vcpu->stat.io_exits;
5192 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5194 port = exit_qualification >> 16;
5195 size = (exit_qualification & 7) + 1;
5196 skip_emulated_instruction(vcpu);
5198 return kvm_fast_pio_out(vcpu, size, port);
5202 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5205 * Patch in the VMCALL instruction:
5207 hypercall[0] = 0x0f;
5208 hypercall[1] = 0x01;
5209 hypercall[2] = 0xc1;
5212 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5214 unsigned long always_on = VMXON_CR0_ALWAYSON;
5215 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5217 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5218 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5219 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5220 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5221 return (val & always_on) == always_on;
5224 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5225 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5227 if (is_guest_mode(vcpu)) {
5228 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5229 unsigned long orig_val = val;
5232 * We get here when L2 changed cr0 in a way that did not change
5233 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5234 * but did change L0 shadowed bits. So we first calculate the
5235 * effective cr0 value that L1 would like to write into the
5236 * hardware. It consists of the L2-owned bits from the new
5237 * value combined with the L1-owned bits from L1's guest_cr0.
5239 val = (val & ~vmcs12->cr0_guest_host_mask) |
5240 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5242 if (!nested_cr0_valid(vcpu, val))
5245 if (kvm_set_cr0(vcpu, val))
5247 vmcs_writel(CR0_READ_SHADOW, orig_val);
5250 if (to_vmx(vcpu)->nested.vmxon &&
5251 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5253 return kvm_set_cr0(vcpu, val);
5257 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5259 if (is_guest_mode(vcpu)) {
5260 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5261 unsigned long orig_val = val;
5263 /* analogously to handle_set_cr0 */
5264 val = (val & ~vmcs12->cr4_guest_host_mask) |
5265 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5266 if (kvm_set_cr4(vcpu, val))
5268 vmcs_writel(CR4_READ_SHADOW, orig_val);
5271 return kvm_set_cr4(vcpu, val);
5274 /* called to set cr0 as approriate for clts instruction exit. */
5275 static void handle_clts(struct kvm_vcpu *vcpu)
5277 if (is_guest_mode(vcpu)) {
5279 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5280 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5281 * just pretend it's off (also in arch.cr0 for fpu_activate).
5283 vmcs_writel(CR0_READ_SHADOW,
5284 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5285 vcpu->arch.cr0 &= ~X86_CR0_TS;
5287 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5290 static int handle_cr(struct kvm_vcpu *vcpu)
5292 unsigned long exit_qualification, val;
5297 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5298 cr = exit_qualification & 15;
5299 reg = (exit_qualification >> 8) & 15;
5300 switch ((exit_qualification >> 4) & 3) {
5301 case 0: /* mov to cr */
5302 val = kvm_register_readl(vcpu, reg);
5303 trace_kvm_cr_write(cr, val);
5306 err = handle_set_cr0(vcpu, val);
5307 kvm_complete_insn_gp(vcpu, err);
5310 err = kvm_set_cr3(vcpu, val);
5311 kvm_complete_insn_gp(vcpu, err);
5314 err = handle_set_cr4(vcpu, val);
5315 kvm_complete_insn_gp(vcpu, err);
5318 u8 cr8_prev = kvm_get_cr8(vcpu);
5320 err = kvm_set_cr8(vcpu, cr8);
5321 kvm_complete_insn_gp(vcpu, err);
5322 if (irqchip_in_kernel(vcpu->kvm))
5324 if (cr8_prev <= cr8)
5326 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5333 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5334 skip_emulated_instruction(vcpu);
5335 vmx_fpu_activate(vcpu);
5337 case 1: /*mov from cr*/
5340 val = kvm_read_cr3(vcpu);
5341 kvm_register_write(vcpu, reg, val);
5342 trace_kvm_cr_read(cr, val);
5343 skip_emulated_instruction(vcpu);
5346 val = kvm_get_cr8(vcpu);
5347 kvm_register_write(vcpu, reg, val);
5348 trace_kvm_cr_read(cr, val);
5349 skip_emulated_instruction(vcpu);
5354 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5355 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5356 kvm_lmsw(vcpu, val);
5358 skip_emulated_instruction(vcpu);
5363 vcpu->run->exit_reason = 0;
5364 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5365 (int)(exit_qualification >> 4) & 3, cr);
5369 static int handle_dr(struct kvm_vcpu *vcpu)
5371 unsigned long exit_qualification;
5374 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5375 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5377 /* First, if DR does not exist, trigger UD */
5378 if (!kvm_require_dr(vcpu, dr))
5381 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5382 if (!kvm_require_cpl(vcpu, 0))
5384 dr7 = vmcs_readl(GUEST_DR7);
5387 * As the vm-exit takes precedence over the debug trap, we
5388 * need to emulate the latter, either for the host or the
5389 * guest debugging itself.
5391 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5392 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5393 vcpu->run->debug.arch.dr7 = dr7;
5394 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5395 vcpu->run->debug.arch.exception = DB_VECTOR;
5396 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5399 vcpu->arch.dr6 &= ~15;
5400 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5401 kvm_queue_exception(vcpu, DB_VECTOR);
5406 if (vcpu->guest_debug == 0) {
5407 u32 cpu_based_vm_exec_control;
5409 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5410 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5411 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5414 * No more DR vmexits; force a reload of the debug registers
5415 * and reenter on this instruction. The next vmexit will
5416 * retrieve the full state of the debug registers.
5418 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5422 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5423 if (exit_qualification & TYPE_MOV_FROM_DR) {
5426 if (kvm_get_dr(vcpu, dr, &val))
5428 kvm_register_write(vcpu, reg, val);
5430 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5433 skip_emulated_instruction(vcpu);
5437 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5439 return vcpu->arch.dr6;
5442 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5446 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5448 u32 cpu_based_vm_exec_control;
5450 get_debugreg(vcpu->arch.db[0], 0);
5451 get_debugreg(vcpu->arch.db[1], 1);
5452 get_debugreg(vcpu->arch.db[2], 2);
5453 get_debugreg(vcpu->arch.db[3], 3);
5454 get_debugreg(vcpu->arch.dr6, 6);
5455 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5457 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5459 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5460 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5461 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5464 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5466 vmcs_writel(GUEST_DR7, val);
5469 static int handle_cpuid(struct kvm_vcpu *vcpu)
5471 kvm_emulate_cpuid(vcpu);
5475 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5477 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5480 if (vmx_get_msr(vcpu, ecx, &data)) {
5481 trace_kvm_msr_read_ex(ecx);
5482 kvm_inject_gp(vcpu, 0);
5486 trace_kvm_msr_read(ecx, data);
5488 /* FIXME: handling of bits 32:63 of rax, rdx */
5489 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5490 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5491 skip_emulated_instruction(vcpu);
5495 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5497 struct msr_data msr;
5498 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5499 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5500 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5504 msr.host_initiated = false;
5505 if (kvm_set_msr(vcpu, &msr) != 0) {
5506 trace_kvm_msr_write_ex(ecx, data);
5507 kvm_inject_gp(vcpu, 0);
5511 trace_kvm_msr_write(ecx, data);
5512 skip_emulated_instruction(vcpu);
5516 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5518 kvm_make_request(KVM_REQ_EVENT, vcpu);
5522 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5524 u32 cpu_based_vm_exec_control;
5526 /* clear pending irq */
5527 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5528 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5531 kvm_make_request(KVM_REQ_EVENT, vcpu);
5533 ++vcpu->stat.irq_window_exits;
5536 * If the user space waits to inject interrupts, exit as soon as
5539 if (!irqchip_in_kernel(vcpu->kvm) &&
5540 vcpu->run->request_interrupt_window &&
5541 !kvm_cpu_has_interrupt(vcpu)) {
5542 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5548 static int handle_halt(struct kvm_vcpu *vcpu)
5550 return kvm_emulate_halt(vcpu);
5553 static int handle_vmcall(struct kvm_vcpu *vcpu)
5555 kvm_emulate_hypercall(vcpu);
5559 static int handle_invd(struct kvm_vcpu *vcpu)
5561 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5564 static int handle_invlpg(struct kvm_vcpu *vcpu)
5566 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5568 kvm_mmu_invlpg(vcpu, exit_qualification);
5569 skip_emulated_instruction(vcpu);
5573 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5577 err = kvm_rdpmc(vcpu);
5578 kvm_complete_insn_gp(vcpu, err);
5583 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5585 kvm_emulate_wbinvd(vcpu);
5589 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5591 u64 new_bv = kvm_read_edx_eax(vcpu);
5592 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5594 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5595 skip_emulated_instruction(vcpu);
5599 static int handle_xsaves(struct kvm_vcpu *vcpu)
5601 skip_emulated_instruction(vcpu);
5602 WARN(1, "this should never happen\n");
5606 static int handle_xrstors(struct kvm_vcpu *vcpu)
5608 skip_emulated_instruction(vcpu);
5609 WARN(1, "this should never happen\n");
5613 static int handle_apic_access(struct kvm_vcpu *vcpu)
5615 if (likely(fasteoi)) {
5616 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5617 int access_type, offset;
5619 access_type = exit_qualification & APIC_ACCESS_TYPE;
5620 offset = exit_qualification & APIC_ACCESS_OFFSET;
5622 * Sane guest uses MOV to write EOI, with written value
5623 * not cared. So make a short-circuit here by avoiding
5624 * heavy instruction emulation.
5626 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5627 (offset == APIC_EOI)) {
5628 kvm_lapic_set_eoi(vcpu);
5629 skip_emulated_instruction(vcpu);
5633 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5636 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5638 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5639 int vector = exit_qualification & 0xff;
5641 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5642 kvm_apic_set_eoi_accelerated(vcpu, vector);
5646 static int handle_apic_write(struct kvm_vcpu *vcpu)
5648 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5649 u32 offset = exit_qualification & 0xfff;
5651 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5652 kvm_apic_write_nodecode(vcpu, offset);
5656 static int handle_task_switch(struct kvm_vcpu *vcpu)
5658 struct vcpu_vmx *vmx = to_vmx(vcpu);
5659 unsigned long exit_qualification;
5660 bool has_error_code = false;
5663 int reason, type, idt_v, idt_index;
5665 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5666 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5667 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5669 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5671 reason = (u32)exit_qualification >> 30;
5672 if (reason == TASK_SWITCH_GATE && idt_v) {
5674 case INTR_TYPE_NMI_INTR:
5675 vcpu->arch.nmi_injected = false;
5676 vmx_set_nmi_mask(vcpu, true);
5678 case INTR_TYPE_EXT_INTR:
5679 case INTR_TYPE_SOFT_INTR:
5680 kvm_clear_interrupt_queue(vcpu);
5682 case INTR_TYPE_HARD_EXCEPTION:
5683 if (vmx->idt_vectoring_info &
5684 VECTORING_INFO_DELIVER_CODE_MASK) {
5685 has_error_code = true;
5687 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5690 case INTR_TYPE_SOFT_EXCEPTION:
5691 kvm_clear_exception_queue(vcpu);
5697 tss_selector = exit_qualification;
5699 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5700 type != INTR_TYPE_EXT_INTR &&
5701 type != INTR_TYPE_NMI_INTR))
5702 skip_emulated_instruction(vcpu);
5704 if (kvm_task_switch(vcpu, tss_selector,
5705 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5706 has_error_code, error_code) == EMULATE_FAIL) {
5707 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5708 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5709 vcpu->run->internal.ndata = 0;
5713 /* clear all local breakpoint enable flags */
5714 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5717 * TODO: What about debug traps on tss switch?
5718 * Are we supposed to inject them and update dr6?
5724 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5726 unsigned long exit_qualification;
5731 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5733 gla_validity = (exit_qualification >> 7) & 0x3;
5734 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5735 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5736 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5737 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5738 vmcs_readl(GUEST_LINEAR_ADDRESS));
5739 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5740 (long unsigned int)exit_qualification);
5741 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5742 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5747 * EPT violation happened while executing iret from NMI,
5748 * "blocked by NMI" bit has to be set before next VM entry.
5749 * There are errata that may cause this bit to not be set:
5752 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5753 cpu_has_virtual_nmis() &&
5754 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5755 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5757 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5758 trace_kvm_page_fault(gpa, exit_qualification);
5760 /* It is a write fault? */
5761 error_code = exit_qualification & PFERR_WRITE_MASK;
5762 /* It is a fetch fault? */
5763 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5764 /* ept page table is present? */
5765 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5767 vcpu->arch.exit_qualification = exit_qualification;
5769 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5772 static u64 ept_rsvd_mask(u64 spte, int level)
5777 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5778 mask |= (1ULL << i);
5781 /* bits 7:3 reserved */
5783 else if (spte & (1ULL << 7))
5785 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5786 * level == 1 if the hypervisor is using the ignored bit 7.
5788 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5790 /* bits 6:3 reserved */
5796 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5799 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5801 /* 010b (write-only) */
5802 WARN_ON((spte & 0x7) == 0x2);
5804 /* 110b (write/execute) */
5805 WARN_ON((spte & 0x7) == 0x6);
5807 /* 100b (execute-only) and value not supported by logical processor */
5808 if (!cpu_has_vmx_ept_execute_only())
5809 WARN_ON((spte & 0x7) == 0x4);
5813 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5815 if (rsvd_bits != 0) {
5816 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5817 __func__, rsvd_bits);
5821 /* bits 5:3 are _not_ reserved for large page or leaf page */
5822 if ((rsvd_bits & 0x38) == 0) {
5823 u64 ept_mem_type = (spte & 0x38) >> 3;
5825 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5826 ept_mem_type == 7) {
5827 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5828 __func__, ept_mem_type);
5835 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5838 int nr_sptes, i, ret;
5841 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5842 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5843 skip_emulated_instruction(vcpu);
5847 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5848 if (likely(ret == RET_MMIO_PF_EMULATE))
5849 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5852 if (unlikely(ret == RET_MMIO_PF_INVALID))
5853 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5855 if (unlikely(ret == RET_MMIO_PF_RETRY))
5858 /* It is the real ept misconfig */
5859 printk(KERN_ERR "EPT: Misconfiguration.\n");
5860 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5862 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5864 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5865 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5867 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5868 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5873 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5875 u32 cpu_based_vm_exec_control;
5877 /* clear pending NMI */
5878 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5879 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5880 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5881 ++vcpu->stat.nmi_window_exits;
5882 kvm_make_request(KVM_REQ_EVENT, vcpu);
5887 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5889 struct vcpu_vmx *vmx = to_vmx(vcpu);
5890 enum emulation_result err = EMULATE_DONE;
5893 bool intr_window_requested;
5894 unsigned count = 130;
5896 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5897 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5899 while (vmx->emulation_required && count-- != 0) {
5900 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5901 return handle_interrupt_window(&vmx->vcpu);
5903 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5906 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5908 if (err == EMULATE_USER_EXIT) {
5909 ++vcpu->stat.mmio_exits;
5914 if (err != EMULATE_DONE) {
5915 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5916 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5917 vcpu->run->internal.ndata = 0;
5921 if (vcpu->arch.halt_request) {
5922 vcpu->arch.halt_request = 0;
5923 ret = kvm_vcpu_halt(vcpu);
5927 if (signal_pending(current))
5937 static int __grow_ple_window(int val)
5939 if (ple_window_grow < 1)
5942 val = min(val, ple_window_actual_max);
5944 if (ple_window_grow < ple_window)
5945 val *= ple_window_grow;
5947 val += ple_window_grow;
5952 static int __shrink_ple_window(int val, int modifier, int minimum)
5957 if (modifier < ple_window)
5962 return max(val, minimum);
5965 static void grow_ple_window(struct kvm_vcpu *vcpu)
5967 struct vcpu_vmx *vmx = to_vmx(vcpu);
5968 int old = vmx->ple_window;
5970 vmx->ple_window = __grow_ple_window(old);
5972 if (vmx->ple_window != old)
5973 vmx->ple_window_dirty = true;
5975 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5978 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5980 struct vcpu_vmx *vmx = to_vmx(vcpu);
5981 int old = vmx->ple_window;
5983 vmx->ple_window = __shrink_ple_window(old,
5984 ple_window_shrink, ple_window);
5986 if (vmx->ple_window != old)
5987 vmx->ple_window_dirty = true;
5989 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5993 * ple_window_actual_max is computed to be one grow_ple_window() below
5994 * ple_window_max. (See __grow_ple_window for the reason.)
5995 * This prevents overflows, because ple_window_max is int.
5996 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5998 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6000 static void update_ple_window_actual_max(void)
6002 ple_window_actual_max =
6003 __shrink_ple_window(max(ple_window_max, ple_window),
6004 ple_window_grow, INT_MIN);
6007 static __init int hardware_setup(void)
6009 int r = -ENOMEM, i, msr;
6011 rdmsrl_safe(MSR_EFER, &host_efer);
6013 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6014 kvm_define_shared_msr(i, vmx_msr_index[i]);
6016 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6017 if (!vmx_io_bitmap_a)
6020 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6021 if (!vmx_io_bitmap_b)
6024 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6025 if (!vmx_msr_bitmap_legacy)
6028 vmx_msr_bitmap_legacy_x2apic =
6029 (unsigned long *)__get_free_page(GFP_KERNEL);
6030 if (!vmx_msr_bitmap_legacy_x2apic)
6033 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6034 if (!vmx_msr_bitmap_longmode)
6037 vmx_msr_bitmap_longmode_x2apic =
6038 (unsigned long *)__get_free_page(GFP_KERNEL);
6039 if (!vmx_msr_bitmap_longmode_x2apic)
6043 vmx_msr_bitmap_nested =
6044 (unsigned long *)__get_free_page(GFP_KERNEL);
6045 if (!vmx_msr_bitmap_nested)
6049 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6050 if (!vmx_vmread_bitmap)
6053 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6054 if (!vmx_vmwrite_bitmap)
6057 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6058 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6061 * Allow direct access to the PC debug port (it is often used for I/O
6062 * delays, but the vmexits simply slow things down).
6064 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6065 clear_bit(0x80, vmx_io_bitmap_a);
6067 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6069 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6070 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6072 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6074 if (setup_vmcs_config(&vmcs_config) < 0) {
6079 if (boot_cpu_has(X86_FEATURE_NX))
6080 kvm_enable_efer_bits(EFER_NX);
6082 if (!cpu_has_vmx_vpid())
6084 if (!cpu_has_vmx_shadow_vmcs())
6085 enable_shadow_vmcs = 0;
6086 if (enable_shadow_vmcs)
6087 init_vmcs_shadow_fields();
6089 if (!cpu_has_vmx_ept() ||
6090 !cpu_has_vmx_ept_4levels()) {
6092 enable_unrestricted_guest = 0;
6093 enable_ept_ad_bits = 0;
6096 if (!cpu_has_vmx_ept_ad_bits())
6097 enable_ept_ad_bits = 0;
6099 if (!cpu_has_vmx_unrestricted_guest())
6100 enable_unrestricted_guest = 0;
6102 if (!cpu_has_vmx_flexpriority())
6103 flexpriority_enabled = 0;
6106 * set_apic_access_page_addr() is used to reload apic access
6107 * page upon invalidation. No need to do anything if not
6108 * using the APIC_ACCESS_ADDR VMCS field.
6110 if (!flexpriority_enabled)
6111 kvm_x86_ops->set_apic_access_page_addr = NULL;
6113 if (!cpu_has_vmx_tpr_shadow())
6114 kvm_x86_ops->update_cr8_intercept = NULL;
6116 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6117 kvm_disable_largepages();
6119 if (!cpu_has_vmx_ple())
6122 if (!cpu_has_vmx_apicv())
6126 kvm_x86_ops->update_cr8_intercept = NULL;
6128 kvm_x86_ops->hwapic_irr_update = NULL;
6129 kvm_x86_ops->hwapic_isr_update = NULL;
6130 kvm_x86_ops->deliver_posted_interrupt = NULL;
6131 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6134 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6135 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6136 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6137 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6138 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6139 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6140 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6142 memcpy(vmx_msr_bitmap_legacy_x2apic,
6143 vmx_msr_bitmap_legacy, PAGE_SIZE);
6144 memcpy(vmx_msr_bitmap_longmode_x2apic,
6145 vmx_msr_bitmap_longmode, PAGE_SIZE);
6148 for (msr = 0x800; msr <= 0x8ff; msr++)
6149 vmx_disable_intercept_msr_read_x2apic(msr);
6151 /* According SDM, in x2apic mode, the whole id reg is used.
6152 * But in KVM, it only use the highest eight bits. Need to
6154 vmx_enable_intercept_msr_read_x2apic(0x802);
6156 vmx_enable_intercept_msr_read_x2apic(0x839);
6158 vmx_disable_intercept_msr_write_x2apic(0x808);
6160 vmx_disable_intercept_msr_write_x2apic(0x80b);
6162 vmx_disable_intercept_msr_write_x2apic(0x83f);
6166 kvm_mmu_set_mask_ptes(0ull,
6167 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6168 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6169 0ull, VMX_EPT_EXECUTABLE_MASK);
6170 ept_set_mmio_spte_mask();
6175 update_ple_window_actual_max();
6178 * Only enable PML when hardware supports PML feature, and both EPT
6179 * and EPT A/D bit features are enabled -- PML depends on them to work.
6181 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6185 kvm_x86_ops->slot_enable_log_dirty = NULL;
6186 kvm_x86_ops->slot_disable_log_dirty = NULL;
6187 kvm_x86_ops->flush_log_dirty = NULL;
6188 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6191 return alloc_kvm_area();
6194 free_page((unsigned long)vmx_vmwrite_bitmap);
6196 free_page((unsigned long)vmx_vmread_bitmap);
6199 free_page((unsigned long)vmx_msr_bitmap_nested);
6201 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6203 free_page((unsigned long)vmx_msr_bitmap_longmode);
6205 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6207 free_page((unsigned long)vmx_msr_bitmap_legacy);
6209 free_page((unsigned long)vmx_io_bitmap_b);
6211 free_page((unsigned long)vmx_io_bitmap_a);
6216 static __exit void hardware_unsetup(void)
6218 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6219 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6220 free_page((unsigned long)vmx_msr_bitmap_legacy);
6221 free_page((unsigned long)vmx_msr_bitmap_longmode);
6222 free_page((unsigned long)vmx_io_bitmap_b);
6223 free_page((unsigned long)vmx_io_bitmap_a);
6224 free_page((unsigned long)vmx_vmwrite_bitmap);
6225 free_page((unsigned long)vmx_vmread_bitmap);
6227 free_page((unsigned long)vmx_msr_bitmap_nested);
6233 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6234 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6236 static int handle_pause(struct kvm_vcpu *vcpu)
6239 grow_ple_window(vcpu);
6241 skip_emulated_instruction(vcpu);
6242 kvm_vcpu_on_spin(vcpu);
6247 static int handle_nop(struct kvm_vcpu *vcpu)
6249 skip_emulated_instruction(vcpu);
6253 static int handle_mwait(struct kvm_vcpu *vcpu)
6255 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6256 return handle_nop(vcpu);
6259 static int handle_monitor(struct kvm_vcpu *vcpu)
6261 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6262 return handle_nop(vcpu);
6266 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6267 * We could reuse a single VMCS for all the L2 guests, but we also want the
6268 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6269 * allows keeping them loaded on the processor, and in the future will allow
6270 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6271 * every entry if they never change.
6272 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6273 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6275 * The following functions allocate and free a vmcs02 in this pool.
6278 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6279 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6281 struct vmcs02_list *item;
6282 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6283 if (item->vmptr == vmx->nested.current_vmptr) {
6284 list_move(&item->list, &vmx->nested.vmcs02_pool);
6285 return &item->vmcs02;
6288 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6289 /* Recycle the least recently used VMCS. */
6290 item = list_entry(vmx->nested.vmcs02_pool.prev,
6291 struct vmcs02_list, list);
6292 item->vmptr = vmx->nested.current_vmptr;
6293 list_move(&item->list, &vmx->nested.vmcs02_pool);
6294 return &item->vmcs02;
6297 /* Create a new VMCS */
6298 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6301 item->vmcs02.vmcs = alloc_vmcs();
6302 if (!item->vmcs02.vmcs) {
6306 loaded_vmcs_init(&item->vmcs02);
6307 item->vmptr = vmx->nested.current_vmptr;
6308 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6309 vmx->nested.vmcs02_num++;
6310 return &item->vmcs02;
6313 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6314 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6316 struct vmcs02_list *item;
6317 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6318 if (item->vmptr == vmptr) {
6319 free_loaded_vmcs(&item->vmcs02);
6320 list_del(&item->list);
6322 vmx->nested.vmcs02_num--;
6328 * Free all VMCSs saved for this vcpu, except the one pointed by
6329 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6330 * must be &vmx->vmcs01.
6332 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6334 struct vmcs02_list *item, *n;
6336 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6337 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6339 * Something will leak if the above WARN triggers. Better than
6342 if (vmx->loaded_vmcs == &item->vmcs02)
6345 free_loaded_vmcs(&item->vmcs02);
6346 list_del(&item->list);
6348 vmx->nested.vmcs02_num--;
6353 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6354 * set the success or error code of an emulated VMX instruction, as specified
6355 * by Vol 2B, VMX Instruction Reference, "Conventions".
6357 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6359 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6360 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6361 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6364 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6366 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6367 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6368 X86_EFLAGS_SF | X86_EFLAGS_OF))
6372 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6373 u32 vm_instruction_error)
6375 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6377 * failValid writes the error number to the current VMCS, which
6378 * can't be done there isn't a current VMCS.
6380 nested_vmx_failInvalid(vcpu);
6383 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6384 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6385 X86_EFLAGS_SF | X86_EFLAGS_OF))
6387 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6389 * We don't need to force a shadow sync because
6390 * VM_INSTRUCTION_ERROR is not shadowed
6394 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6396 /* TODO: not to reset guest simply here. */
6397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6398 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6401 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6403 struct vcpu_vmx *vmx =
6404 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6406 vmx->nested.preemption_timer_expired = true;
6407 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6408 kvm_vcpu_kick(&vmx->vcpu);
6410 return HRTIMER_NORESTART;
6414 * Decode the memory-address operand of a vmx instruction, as recorded on an
6415 * exit caused by such an instruction (run by a guest hypervisor).
6416 * On success, returns 0. When the operand is invalid, returns 1 and throws
6419 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6420 unsigned long exit_qualification,
6421 u32 vmx_instruction_info, gva_t *ret)
6424 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6425 * Execution", on an exit, vmx_instruction_info holds most of the
6426 * addressing components of the operand. Only the displacement part
6427 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6428 * For how an actual address is calculated from all these components,
6429 * refer to Vol. 1, "Operand Addressing".
6431 int scaling = vmx_instruction_info & 3;
6432 int addr_size = (vmx_instruction_info >> 7) & 7;
6433 bool is_reg = vmx_instruction_info & (1u << 10);
6434 int seg_reg = (vmx_instruction_info >> 15) & 7;
6435 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6436 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6437 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6438 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6441 kvm_queue_exception(vcpu, UD_VECTOR);
6445 /* Addr = segment_base + offset */
6446 /* offset = base + [index * scale] + displacement */
6447 *ret = vmx_get_segment_base(vcpu, seg_reg);
6449 *ret += kvm_register_read(vcpu, base_reg);
6451 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6452 *ret += exit_qualification; /* holds the displacement */
6454 if (addr_size == 1) /* 32 bit */
6458 * TODO: throw #GP (and return 1) in various cases that the VM*
6459 * instructions require it - e.g., offset beyond segment limit,
6460 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6461 * address, and so on. Currently these are not checked.
6467 * This function performs the various checks including
6468 * - if it's 4KB aligned
6469 * - No bits beyond the physical address width are set
6470 * - Returns 0 on success or else 1
6471 * (Intel SDM Section 30.3)
6473 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6478 struct x86_exception e;
6480 struct vcpu_vmx *vmx = to_vmx(vcpu);
6481 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6483 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6484 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6487 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6488 sizeof(vmptr), &e)) {
6489 kvm_inject_page_fault(vcpu, &e);
6493 switch (exit_reason) {
6494 case EXIT_REASON_VMON:
6497 * The first 4 bytes of VMXON region contain the supported
6498 * VMCS revision identifier
6500 * Note - IA32_VMX_BASIC[48] will never be 1
6501 * for the nested case;
6502 * which replaces physical address width with 32
6505 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6506 nested_vmx_failInvalid(vcpu);
6507 skip_emulated_instruction(vcpu);
6511 page = nested_get_page(vcpu, vmptr);
6513 *(u32 *)kmap(page) != VMCS12_REVISION) {
6514 nested_vmx_failInvalid(vcpu);
6516 skip_emulated_instruction(vcpu);
6520 vmx->nested.vmxon_ptr = vmptr;
6522 case EXIT_REASON_VMCLEAR:
6523 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6524 nested_vmx_failValid(vcpu,
6525 VMXERR_VMCLEAR_INVALID_ADDRESS);
6526 skip_emulated_instruction(vcpu);
6530 if (vmptr == vmx->nested.vmxon_ptr) {
6531 nested_vmx_failValid(vcpu,
6532 VMXERR_VMCLEAR_VMXON_POINTER);
6533 skip_emulated_instruction(vcpu);
6537 case EXIT_REASON_VMPTRLD:
6538 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6539 nested_vmx_failValid(vcpu,
6540 VMXERR_VMPTRLD_INVALID_ADDRESS);
6541 skip_emulated_instruction(vcpu);
6545 if (vmptr == vmx->nested.vmxon_ptr) {
6546 nested_vmx_failValid(vcpu,
6547 VMXERR_VMCLEAR_VMXON_POINTER);
6548 skip_emulated_instruction(vcpu);
6553 return 1; /* shouldn't happen */
6562 * Emulate the VMXON instruction.
6563 * Currently, we just remember that VMX is active, and do not save or even
6564 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6565 * do not currently need to store anything in that guest-allocated memory
6566 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6567 * argument is different from the VMXON pointer (which the spec says they do).
6569 static int handle_vmon(struct kvm_vcpu *vcpu)
6571 struct kvm_segment cs;
6572 struct vcpu_vmx *vmx = to_vmx(vcpu);
6573 struct vmcs *shadow_vmcs;
6574 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6575 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6577 /* The Intel VMX Instruction Reference lists a bunch of bits that
6578 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6579 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6580 * Otherwise, we should fail with #UD. We test these now:
6582 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6583 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6584 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6585 kvm_queue_exception(vcpu, UD_VECTOR);
6589 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6590 if (is_long_mode(vcpu) && !cs.l) {
6591 kvm_queue_exception(vcpu, UD_VECTOR);
6595 if (vmx_get_cpl(vcpu)) {
6596 kvm_inject_gp(vcpu, 0);
6600 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6603 if (vmx->nested.vmxon) {
6604 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6605 skip_emulated_instruction(vcpu);
6609 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6610 != VMXON_NEEDED_FEATURES) {
6611 kvm_inject_gp(vcpu, 0);
6615 if (enable_shadow_vmcs) {
6616 shadow_vmcs = alloc_vmcs();
6619 /* mark vmcs as shadow */
6620 shadow_vmcs->revision_id |= (1u << 31);
6621 /* init shadow vmcs */
6622 vmcs_clear(shadow_vmcs);
6623 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6626 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6627 vmx->nested.vmcs02_num = 0;
6629 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6631 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6633 vmx->nested.vmxon = true;
6635 skip_emulated_instruction(vcpu);
6636 nested_vmx_succeed(vcpu);
6641 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6642 * for running VMX instructions (except VMXON, whose prerequisites are
6643 * slightly different). It also specifies what exception to inject otherwise.
6645 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6647 struct kvm_segment cs;
6648 struct vcpu_vmx *vmx = to_vmx(vcpu);
6650 if (!vmx->nested.vmxon) {
6651 kvm_queue_exception(vcpu, UD_VECTOR);
6655 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6656 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6657 (is_long_mode(vcpu) && !cs.l)) {
6658 kvm_queue_exception(vcpu, UD_VECTOR);
6662 if (vmx_get_cpl(vcpu)) {
6663 kvm_inject_gp(vcpu, 0);
6670 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6673 if (vmx->nested.current_vmptr == -1ull)
6676 /* current_vmptr and current_vmcs12 are always set/reset together */
6677 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6680 if (enable_shadow_vmcs) {
6681 /* copy to memory all shadowed fields in case
6682 they were modified */
6683 copy_shadow_to_vmcs12(vmx);
6684 vmx->nested.sync_shadow_vmcs = false;
6685 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6686 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6687 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6688 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6690 vmx->nested.posted_intr_nv = -1;
6691 kunmap(vmx->nested.current_vmcs12_page);
6692 nested_release_page(vmx->nested.current_vmcs12_page);
6693 vmx->nested.current_vmptr = -1ull;
6694 vmx->nested.current_vmcs12 = NULL;
6698 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6699 * just stops using VMX.
6701 static void free_nested(struct vcpu_vmx *vmx)
6703 if (!vmx->nested.vmxon)
6706 vmx->nested.vmxon = false;
6707 nested_release_vmcs12(vmx);
6708 if (enable_shadow_vmcs)
6709 free_vmcs(vmx->nested.current_shadow_vmcs);
6710 /* Unpin physical memory we referred to in current vmcs02 */
6711 if (vmx->nested.apic_access_page) {
6712 nested_release_page(vmx->nested.apic_access_page);
6713 vmx->nested.apic_access_page = NULL;
6715 if (vmx->nested.virtual_apic_page) {
6716 nested_release_page(vmx->nested.virtual_apic_page);
6717 vmx->nested.virtual_apic_page = NULL;
6719 if (vmx->nested.pi_desc_page) {
6720 kunmap(vmx->nested.pi_desc_page);
6721 nested_release_page(vmx->nested.pi_desc_page);
6722 vmx->nested.pi_desc_page = NULL;
6723 vmx->nested.pi_desc = NULL;
6726 nested_free_all_saved_vmcss(vmx);
6729 /* Emulate the VMXOFF instruction */
6730 static int handle_vmoff(struct kvm_vcpu *vcpu)
6732 if (!nested_vmx_check_permission(vcpu))
6734 free_nested(to_vmx(vcpu));
6735 skip_emulated_instruction(vcpu);
6736 nested_vmx_succeed(vcpu);
6740 /* Emulate the VMCLEAR instruction */
6741 static int handle_vmclear(struct kvm_vcpu *vcpu)
6743 struct vcpu_vmx *vmx = to_vmx(vcpu);
6745 struct vmcs12 *vmcs12;
6748 if (!nested_vmx_check_permission(vcpu))
6751 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6754 if (vmptr == vmx->nested.current_vmptr)
6755 nested_release_vmcs12(vmx);
6757 page = nested_get_page(vcpu, vmptr);
6760 * For accurate processor emulation, VMCLEAR beyond available
6761 * physical memory should do nothing at all. However, it is
6762 * possible that a nested vmx bug, not a guest hypervisor bug,
6763 * resulted in this case, so let's shut down before doing any
6766 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6769 vmcs12 = kmap(page);
6770 vmcs12->launch_state = 0;
6772 nested_release_page(page);
6774 nested_free_vmcs02(vmx, vmptr);
6776 skip_emulated_instruction(vcpu);
6777 nested_vmx_succeed(vcpu);
6781 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6783 /* Emulate the VMLAUNCH instruction */
6784 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6786 return nested_vmx_run(vcpu, true);
6789 /* Emulate the VMRESUME instruction */
6790 static int handle_vmresume(struct kvm_vcpu *vcpu)
6793 return nested_vmx_run(vcpu, false);
6796 enum vmcs_field_type {
6797 VMCS_FIELD_TYPE_U16 = 0,
6798 VMCS_FIELD_TYPE_U64 = 1,
6799 VMCS_FIELD_TYPE_U32 = 2,
6800 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6803 static inline int vmcs_field_type(unsigned long field)
6805 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6806 return VMCS_FIELD_TYPE_U32;
6807 return (field >> 13) & 0x3 ;
6810 static inline int vmcs_field_readonly(unsigned long field)
6812 return (((field >> 10) & 0x3) == 1);
6816 * Read a vmcs12 field. Since these can have varying lengths and we return
6817 * one type, we chose the biggest type (u64) and zero-extend the return value
6818 * to that size. Note that the caller, handle_vmread, might need to use only
6819 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6820 * 64-bit fields are to be returned).
6822 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6823 unsigned long field, u64 *ret)
6825 short offset = vmcs_field_to_offset(field);
6831 p = ((char *)(get_vmcs12(vcpu))) + offset;
6833 switch (vmcs_field_type(field)) {
6834 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6835 *ret = *((natural_width *)p);
6837 case VMCS_FIELD_TYPE_U16:
6840 case VMCS_FIELD_TYPE_U32:
6843 case VMCS_FIELD_TYPE_U64:
6853 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6854 unsigned long field, u64 field_value){
6855 short offset = vmcs_field_to_offset(field);
6856 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6860 switch (vmcs_field_type(field)) {
6861 case VMCS_FIELD_TYPE_U16:
6862 *(u16 *)p = field_value;
6864 case VMCS_FIELD_TYPE_U32:
6865 *(u32 *)p = field_value;
6867 case VMCS_FIELD_TYPE_U64:
6868 *(u64 *)p = field_value;
6870 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6871 *(natural_width *)p = field_value;
6880 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6883 unsigned long field;
6885 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6886 const unsigned long *fields = shadow_read_write_fields;
6887 const int num_fields = max_shadow_read_write_fields;
6891 vmcs_load(shadow_vmcs);
6893 for (i = 0; i < num_fields; i++) {
6895 switch (vmcs_field_type(field)) {
6896 case VMCS_FIELD_TYPE_U16:
6897 field_value = vmcs_read16(field);
6899 case VMCS_FIELD_TYPE_U32:
6900 field_value = vmcs_read32(field);
6902 case VMCS_FIELD_TYPE_U64:
6903 field_value = vmcs_read64(field);
6905 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6906 field_value = vmcs_readl(field);
6912 vmcs12_write_any(&vmx->vcpu, field, field_value);
6915 vmcs_clear(shadow_vmcs);
6916 vmcs_load(vmx->loaded_vmcs->vmcs);
6921 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6923 const unsigned long *fields[] = {
6924 shadow_read_write_fields,
6925 shadow_read_only_fields
6927 const int max_fields[] = {
6928 max_shadow_read_write_fields,
6929 max_shadow_read_only_fields
6932 unsigned long field;
6933 u64 field_value = 0;
6934 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6936 vmcs_load(shadow_vmcs);
6938 for (q = 0; q < ARRAY_SIZE(fields); q++) {
6939 for (i = 0; i < max_fields[q]; i++) {
6940 field = fields[q][i];
6941 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6943 switch (vmcs_field_type(field)) {
6944 case VMCS_FIELD_TYPE_U16:
6945 vmcs_write16(field, (u16)field_value);
6947 case VMCS_FIELD_TYPE_U32:
6948 vmcs_write32(field, (u32)field_value);
6950 case VMCS_FIELD_TYPE_U64:
6951 vmcs_write64(field, (u64)field_value);
6953 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6954 vmcs_writel(field, (long)field_value);
6963 vmcs_clear(shadow_vmcs);
6964 vmcs_load(vmx->loaded_vmcs->vmcs);
6968 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6969 * used before) all generate the same failure when it is missing.
6971 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6973 struct vcpu_vmx *vmx = to_vmx(vcpu);
6974 if (vmx->nested.current_vmptr == -1ull) {
6975 nested_vmx_failInvalid(vcpu);
6976 skip_emulated_instruction(vcpu);
6982 static int handle_vmread(struct kvm_vcpu *vcpu)
6984 unsigned long field;
6986 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6987 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6990 if (!nested_vmx_check_permission(vcpu) ||
6991 !nested_vmx_check_vmcs12(vcpu))
6994 /* Decode instruction info and find the field to read */
6995 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6996 /* Read the field, zero-extended to a u64 field_value */
6997 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6998 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6999 skip_emulated_instruction(vcpu);
7003 * Now copy part of this value to register or memory, as requested.
7004 * Note that the number of bits actually copied is 32 or 64 depending
7005 * on the guest's mode (32 or 64 bit), not on the given field's length.
7007 if (vmx_instruction_info & (1u << 10)) {
7008 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7011 if (get_vmx_mem_address(vcpu, exit_qualification,
7012 vmx_instruction_info, &gva))
7014 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7015 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7016 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7019 nested_vmx_succeed(vcpu);
7020 skip_emulated_instruction(vcpu);
7025 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7027 unsigned long field;
7029 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7030 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7031 /* The value to write might be 32 or 64 bits, depending on L1's long
7032 * mode, and eventually we need to write that into a field of several
7033 * possible lengths. The code below first zero-extends the value to 64
7034 * bit (field_value), and then copies only the approriate number of
7035 * bits into the vmcs12 field.
7037 u64 field_value = 0;
7038 struct x86_exception e;
7040 if (!nested_vmx_check_permission(vcpu) ||
7041 !nested_vmx_check_vmcs12(vcpu))
7044 if (vmx_instruction_info & (1u << 10))
7045 field_value = kvm_register_readl(vcpu,
7046 (((vmx_instruction_info) >> 3) & 0xf));
7048 if (get_vmx_mem_address(vcpu, exit_qualification,
7049 vmx_instruction_info, &gva))
7051 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7052 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7053 kvm_inject_page_fault(vcpu, &e);
7059 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7060 if (vmcs_field_readonly(field)) {
7061 nested_vmx_failValid(vcpu,
7062 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7063 skip_emulated_instruction(vcpu);
7067 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7068 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7069 skip_emulated_instruction(vcpu);
7073 nested_vmx_succeed(vcpu);
7074 skip_emulated_instruction(vcpu);
7078 /* Emulate the VMPTRLD instruction */
7079 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7081 struct vcpu_vmx *vmx = to_vmx(vcpu);
7085 if (!nested_vmx_check_permission(vcpu))
7088 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7091 if (vmx->nested.current_vmptr != vmptr) {
7092 struct vmcs12 *new_vmcs12;
7094 page = nested_get_page(vcpu, vmptr);
7096 nested_vmx_failInvalid(vcpu);
7097 skip_emulated_instruction(vcpu);
7100 new_vmcs12 = kmap(page);
7101 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7103 nested_release_page_clean(page);
7104 nested_vmx_failValid(vcpu,
7105 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7106 skip_emulated_instruction(vcpu);
7110 nested_release_vmcs12(vmx);
7111 vmx->nested.current_vmptr = vmptr;
7112 vmx->nested.current_vmcs12 = new_vmcs12;
7113 vmx->nested.current_vmcs12_page = page;
7114 if (enable_shadow_vmcs) {
7115 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7116 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7117 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7118 vmcs_write64(VMCS_LINK_POINTER,
7119 __pa(vmx->nested.current_shadow_vmcs));
7120 vmx->nested.sync_shadow_vmcs = true;
7124 nested_vmx_succeed(vcpu);
7125 skip_emulated_instruction(vcpu);
7129 /* Emulate the VMPTRST instruction */
7130 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7132 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7133 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7135 struct x86_exception e;
7137 if (!nested_vmx_check_permission(vcpu))
7140 if (get_vmx_mem_address(vcpu, exit_qualification,
7141 vmx_instruction_info, &vmcs_gva))
7143 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7144 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7145 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7147 kvm_inject_page_fault(vcpu, &e);
7150 nested_vmx_succeed(vcpu);
7151 skip_emulated_instruction(vcpu);
7155 /* Emulate the INVEPT instruction */
7156 static int handle_invept(struct kvm_vcpu *vcpu)
7158 struct vcpu_vmx *vmx = to_vmx(vcpu);
7159 u32 vmx_instruction_info, types;
7162 struct x86_exception e;
7167 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7168 SECONDARY_EXEC_ENABLE_EPT) ||
7169 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7170 kvm_queue_exception(vcpu, UD_VECTOR);
7174 if (!nested_vmx_check_permission(vcpu))
7177 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7178 kvm_queue_exception(vcpu, UD_VECTOR);
7182 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7183 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7185 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7187 if (!(types & (1UL << type))) {
7188 nested_vmx_failValid(vcpu,
7189 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7193 /* According to the Intel VMX instruction reference, the memory
7194 * operand is read even if it isn't needed (e.g., for type==global)
7196 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7197 vmx_instruction_info, &gva))
7199 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7200 sizeof(operand), &e)) {
7201 kvm_inject_page_fault(vcpu, &e);
7206 case VMX_EPT_EXTENT_GLOBAL:
7207 kvm_mmu_sync_roots(vcpu);
7208 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7209 nested_vmx_succeed(vcpu);
7212 /* Trap single context invalidation invept calls */
7217 skip_emulated_instruction(vcpu);
7221 static int handle_invvpid(struct kvm_vcpu *vcpu)
7223 kvm_queue_exception(vcpu, UD_VECTOR);
7227 static int handle_pml_full(struct kvm_vcpu *vcpu)
7229 unsigned long exit_qualification;
7231 trace_kvm_pml_full(vcpu->vcpu_id);
7233 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7236 * PML buffer FULL happened while executing iret from NMI,
7237 * "blocked by NMI" bit has to be set before next VM entry.
7239 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7240 cpu_has_virtual_nmis() &&
7241 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7242 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7243 GUEST_INTR_STATE_NMI);
7246 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7247 * here.., and there's no userspace involvement needed for PML.
7253 * The exit handlers return 1 if the exit was handled fully and guest execution
7254 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7255 * to be done to userspace and return 0.
7257 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7258 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7259 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7260 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7261 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7262 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7263 [EXIT_REASON_CR_ACCESS] = handle_cr,
7264 [EXIT_REASON_DR_ACCESS] = handle_dr,
7265 [EXIT_REASON_CPUID] = handle_cpuid,
7266 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7267 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7268 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7269 [EXIT_REASON_HLT] = handle_halt,
7270 [EXIT_REASON_INVD] = handle_invd,
7271 [EXIT_REASON_INVLPG] = handle_invlpg,
7272 [EXIT_REASON_RDPMC] = handle_rdpmc,
7273 [EXIT_REASON_VMCALL] = handle_vmcall,
7274 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7275 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7276 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7277 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7278 [EXIT_REASON_VMREAD] = handle_vmread,
7279 [EXIT_REASON_VMRESUME] = handle_vmresume,
7280 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7281 [EXIT_REASON_VMOFF] = handle_vmoff,
7282 [EXIT_REASON_VMON] = handle_vmon,
7283 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7284 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7285 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7286 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7287 [EXIT_REASON_WBINVD] = handle_wbinvd,
7288 [EXIT_REASON_XSETBV] = handle_xsetbv,
7289 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7290 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7291 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7292 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7293 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7294 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7295 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7296 [EXIT_REASON_INVEPT] = handle_invept,
7297 [EXIT_REASON_INVVPID] = handle_invvpid,
7298 [EXIT_REASON_XSAVES] = handle_xsaves,
7299 [EXIT_REASON_XRSTORS] = handle_xrstors,
7300 [EXIT_REASON_PML_FULL] = handle_pml_full,
7303 static const int kvm_vmx_max_exit_handlers =
7304 ARRAY_SIZE(kvm_vmx_exit_handlers);
7306 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7307 struct vmcs12 *vmcs12)
7309 unsigned long exit_qualification;
7310 gpa_t bitmap, last_bitmap;
7315 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7316 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7318 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7320 port = exit_qualification >> 16;
7321 size = (exit_qualification & 7) + 1;
7323 last_bitmap = (gpa_t)-1;
7328 bitmap = vmcs12->io_bitmap_a;
7329 else if (port < 0x10000)
7330 bitmap = vmcs12->io_bitmap_b;
7333 bitmap += (port & 0x7fff) / 8;
7335 if (last_bitmap != bitmap)
7336 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7338 if (b & (1 << (port & 7)))
7343 last_bitmap = bitmap;
7350 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7351 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7352 * disinterest in the current event (read or write a specific MSR) by using an
7353 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7355 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7356 struct vmcs12 *vmcs12, u32 exit_reason)
7358 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7361 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7365 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7366 * for the four combinations of read/write and low/high MSR numbers.
7367 * First we need to figure out which of the four to use:
7369 bitmap = vmcs12->msr_bitmap;
7370 if (exit_reason == EXIT_REASON_MSR_WRITE)
7372 if (msr_index >= 0xc0000000) {
7373 msr_index -= 0xc0000000;
7377 /* Then read the msr_index'th bit from this bitmap: */
7378 if (msr_index < 1024*8) {
7380 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7382 return 1 & (b >> (msr_index & 7));
7384 return true; /* let L1 handle the wrong parameter */
7388 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7389 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7390 * intercept (via guest_host_mask etc.) the current event.
7392 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7393 struct vmcs12 *vmcs12)
7395 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7396 int cr = exit_qualification & 15;
7397 int reg = (exit_qualification >> 8) & 15;
7398 unsigned long val = kvm_register_readl(vcpu, reg);
7400 switch ((exit_qualification >> 4) & 3) {
7401 case 0: /* mov to cr */
7404 if (vmcs12->cr0_guest_host_mask &
7405 (val ^ vmcs12->cr0_read_shadow))
7409 if ((vmcs12->cr3_target_count >= 1 &&
7410 vmcs12->cr3_target_value0 == val) ||
7411 (vmcs12->cr3_target_count >= 2 &&
7412 vmcs12->cr3_target_value1 == val) ||
7413 (vmcs12->cr3_target_count >= 3 &&
7414 vmcs12->cr3_target_value2 == val) ||
7415 (vmcs12->cr3_target_count >= 4 &&
7416 vmcs12->cr3_target_value3 == val))
7418 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7422 if (vmcs12->cr4_guest_host_mask &
7423 (vmcs12->cr4_read_shadow ^ val))
7427 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7433 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7434 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7437 case 1: /* mov from cr */
7440 if (vmcs12->cpu_based_vm_exec_control &
7441 CPU_BASED_CR3_STORE_EXITING)
7445 if (vmcs12->cpu_based_vm_exec_control &
7446 CPU_BASED_CR8_STORE_EXITING)
7453 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7454 * cr0. Other attempted changes are ignored, with no exit.
7456 if (vmcs12->cr0_guest_host_mask & 0xe &
7457 (val ^ vmcs12->cr0_read_shadow))
7459 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7460 !(vmcs12->cr0_read_shadow & 0x1) &&
7469 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7470 * should handle it ourselves in L0 (and then continue L2). Only call this
7471 * when in is_guest_mode (L2).
7473 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7475 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7476 struct vcpu_vmx *vmx = to_vmx(vcpu);
7477 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7478 u32 exit_reason = vmx->exit_reason;
7480 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7481 vmcs_readl(EXIT_QUALIFICATION),
7482 vmx->idt_vectoring_info,
7484 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7487 if (vmx->nested.nested_run_pending)
7490 if (unlikely(vmx->fail)) {
7491 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7492 vmcs_read32(VM_INSTRUCTION_ERROR));
7496 switch (exit_reason) {
7497 case EXIT_REASON_EXCEPTION_NMI:
7498 if (!is_exception(intr_info))
7500 else if (is_page_fault(intr_info))
7502 else if (is_no_device(intr_info) &&
7503 !(vmcs12->guest_cr0 & X86_CR0_TS))
7505 return vmcs12->exception_bitmap &
7506 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7507 case EXIT_REASON_EXTERNAL_INTERRUPT:
7509 case EXIT_REASON_TRIPLE_FAULT:
7511 case EXIT_REASON_PENDING_INTERRUPT:
7512 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7513 case EXIT_REASON_NMI_WINDOW:
7514 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7515 case EXIT_REASON_TASK_SWITCH:
7517 case EXIT_REASON_CPUID:
7518 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7521 case EXIT_REASON_HLT:
7522 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7523 case EXIT_REASON_INVD:
7525 case EXIT_REASON_INVLPG:
7526 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7527 case EXIT_REASON_RDPMC:
7528 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7529 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7530 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7531 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7532 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7533 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7534 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7535 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7536 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7538 * VMX instructions trap unconditionally. This allows L1 to
7539 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7542 case EXIT_REASON_CR_ACCESS:
7543 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7544 case EXIT_REASON_DR_ACCESS:
7545 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7546 case EXIT_REASON_IO_INSTRUCTION:
7547 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7548 case EXIT_REASON_MSR_READ:
7549 case EXIT_REASON_MSR_WRITE:
7550 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7551 case EXIT_REASON_INVALID_STATE:
7553 case EXIT_REASON_MWAIT_INSTRUCTION:
7554 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7555 case EXIT_REASON_MONITOR_INSTRUCTION:
7556 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7557 case EXIT_REASON_PAUSE_INSTRUCTION:
7558 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7559 nested_cpu_has2(vmcs12,
7560 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7561 case EXIT_REASON_MCE_DURING_VMENTRY:
7563 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7564 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7565 case EXIT_REASON_APIC_ACCESS:
7566 return nested_cpu_has2(vmcs12,
7567 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7568 case EXIT_REASON_APIC_WRITE:
7569 case EXIT_REASON_EOI_INDUCED:
7570 /* apic_write and eoi_induced should exit unconditionally. */
7572 case EXIT_REASON_EPT_VIOLATION:
7574 * L0 always deals with the EPT violation. If nested EPT is
7575 * used, and the nested mmu code discovers that the address is
7576 * missing in the guest EPT table (EPT12), the EPT violation
7577 * will be injected with nested_ept_inject_page_fault()
7580 case EXIT_REASON_EPT_MISCONFIG:
7582 * L2 never uses directly L1's EPT, but rather L0's own EPT
7583 * table (shadow on EPT) or a merged EPT table that L0 built
7584 * (EPT on EPT). So any problems with the structure of the
7585 * table is L0's fault.
7588 case EXIT_REASON_WBINVD:
7589 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7590 case EXIT_REASON_XSETBV:
7592 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7594 * This should never happen, since it is not possible to
7595 * set XSS to a non-zero value---neither in L1 nor in L2.
7596 * If if it were, XSS would have to be checked against
7597 * the XSS exit bitmap in vmcs12.
7599 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7605 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7607 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7608 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7611 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7613 struct page *pml_pg;
7616 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7620 vmx->pml_pg = pml_pg;
7622 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7623 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7625 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7626 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7627 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7632 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7636 ASSERT(vmx->pml_pg);
7637 __free_page(vmx->pml_pg);
7640 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7641 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7642 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7645 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7647 struct kvm *kvm = vmx->vcpu.kvm;
7651 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7653 /* Do nothing if PML buffer is empty */
7654 if (pml_idx == (PML_ENTITY_NUM - 1))
7657 /* PML index always points to next available PML buffer entity */
7658 if (pml_idx >= PML_ENTITY_NUM)
7663 pml_buf = page_address(vmx->pml_pg);
7664 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7667 gpa = pml_buf[pml_idx];
7668 WARN_ON(gpa & (PAGE_SIZE - 1));
7669 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7672 /* reset PML index */
7673 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7677 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7678 * Called before reporting dirty_bitmap to userspace.
7680 static void kvm_flush_pml_buffers(struct kvm *kvm)
7683 struct kvm_vcpu *vcpu;
7685 * We only need to kick vcpu out of guest mode here, as PML buffer
7686 * is flushed at beginning of all VMEXITs, and it's obvious that only
7687 * vcpus running in guest are possible to have unflushed GPAs in PML
7690 kvm_for_each_vcpu(i, vcpu, kvm)
7691 kvm_vcpu_kick(vcpu);
7695 * The guest has exited. See if we can fix it or if we need userspace
7698 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7700 struct vcpu_vmx *vmx = to_vmx(vcpu);
7701 u32 exit_reason = vmx->exit_reason;
7702 u32 vectoring_info = vmx->idt_vectoring_info;
7705 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7706 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7707 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7708 * mode as if vcpus is in root mode, the PML buffer must has been
7712 vmx_flush_pml_buffer(vmx);
7714 /* If guest state is invalid, start emulating */
7715 if (vmx->emulation_required)
7716 return handle_invalid_guest_state(vcpu);
7718 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7719 nested_vmx_vmexit(vcpu, exit_reason,
7720 vmcs_read32(VM_EXIT_INTR_INFO),
7721 vmcs_readl(EXIT_QUALIFICATION));
7725 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7726 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7727 vcpu->run->fail_entry.hardware_entry_failure_reason
7732 if (unlikely(vmx->fail)) {
7733 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7734 vcpu->run->fail_entry.hardware_entry_failure_reason
7735 = vmcs_read32(VM_INSTRUCTION_ERROR);
7741 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7742 * delivery event since it indicates guest is accessing MMIO.
7743 * The vm-exit can be triggered again after return to guest that
7744 * will cause infinite loop.
7746 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7747 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7748 exit_reason != EXIT_REASON_EPT_VIOLATION &&
7749 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7750 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7751 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7752 vcpu->run->internal.ndata = 2;
7753 vcpu->run->internal.data[0] = vectoring_info;
7754 vcpu->run->internal.data[1] = exit_reason;
7758 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7759 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7760 get_vmcs12(vcpu))))) {
7761 if (vmx_interrupt_allowed(vcpu)) {
7762 vmx->soft_vnmi_blocked = 0;
7763 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7764 vcpu->arch.nmi_pending) {
7766 * This CPU don't support us in finding the end of an
7767 * NMI-blocked window if the guest runs with IRQs
7768 * disabled. So we pull the trigger after 1 s of
7769 * futile waiting, but inform the user about this.
7771 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7772 "state on VCPU %d after 1 s timeout\n",
7773 __func__, vcpu->vcpu_id);
7774 vmx->soft_vnmi_blocked = 0;
7778 if (exit_reason < kvm_vmx_max_exit_handlers
7779 && kvm_vmx_exit_handlers[exit_reason])
7780 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7782 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7783 kvm_queue_exception(vcpu, UD_VECTOR);
7788 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7790 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7792 if (is_guest_mode(vcpu) &&
7793 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7796 if (irr == -1 || tpr < irr) {
7797 vmcs_write32(TPR_THRESHOLD, 0);
7801 vmcs_write32(TPR_THRESHOLD, irr);
7804 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7806 u32 sec_exec_control;
7809 * There is not point to enable virtualize x2apic without enable
7812 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7813 !vmx_vm_has_apicv(vcpu->kvm))
7816 if (!vm_need_tpr_shadow(vcpu->kvm))
7819 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7822 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7823 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7825 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7826 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7828 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7830 vmx_set_msr_bitmap(vcpu);
7833 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7835 struct vcpu_vmx *vmx = to_vmx(vcpu);
7838 * Currently we do not handle the nested case where L2 has an
7839 * APIC access page of its own; that page is still pinned.
7840 * Hence, we skip the case where the VCPU is in guest mode _and_
7841 * L1 prepared an APIC access page for L2.
7843 * For the case where L1 and L2 share the same APIC access page
7844 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7845 * in the vmcs12), this function will only update either the vmcs01
7846 * or the vmcs02. If the former, the vmcs02 will be updated by
7847 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7848 * the next L2->L1 exit.
7850 if (!is_guest_mode(vcpu) ||
7851 !nested_cpu_has2(vmx->nested.current_vmcs12,
7852 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7853 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7856 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7864 status = vmcs_read16(GUEST_INTR_STATUS);
7869 vmcs_write16(GUEST_INTR_STATUS, status);
7873 static void vmx_set_rvi(int vector)
7881 status = vmcs_read16(GUEST_INTR_STATUS);
7882 old = (u8)status & 0xff;
7883 if ((u8)vector != old) {
7885 status |= (u8)vector;
7886 vmcs_write16(GUEST_INTR_STATUS, status);
7890 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7892 if (!is_guest_mode(vcpu)) {
7893 vmx_set_rvi(max_irr);
7901 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7904 if (nested_exit_on_intr(vcpu))
7908 * Else, fall back to pre-APICv interrupt injection since L2
7909 * is run without virtual interrupt delivery.
7911 if (!kvm_event_needs_reinjection(vcpu) &&
7912 vmx_interrupt_allowed(vcpu)) {
7913 kvm_queue_interrupt(vcpu, max_irr, false);
7914 vmx_inject_irq(vcpu);
7918 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7920 if (!vmx_vm_has_apicv(vcpu->kvm))
7923 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7924 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7925 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7926 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7929 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7933 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7934 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7937 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7938 exit_intr_info = vmx->exit_intr_info;
7940 /* Handle machine checks before interrupts are enabled */
7941 if (is_machine_check(exit_intr_info))
7942 kvm_machine_check();
7944 /* We need to handle NMIs before interrupts are enabled */
7945 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7946 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7947 kvm_before_handle_nmi(&vmx->vcpu);
7949 kvm_after_handle_nmi(&vmx->vcpu);
7953 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7955 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7958 * If external interrupt exists, IF bit is set in rflags/eflags on the
7959 * interrupt stack frame, and interrupt will be enabled on a return
7960 * from interrupt handler.
7962 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7963 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7964 unsigned int vector;
7965 unsigned long entry;
7967 struct vcpu_vmx *vmx = to_vmx(vcpu);
7968 #ifdef CONFIG_X86_64
7972 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7973 desc = (gate_desc *)vmx->host_idt_base + vector;
7974 entry = gate_offset(*desc);
7976 #ifdef CONFIG_X86_64
7977 "mov %%" _ASM_SP ", %[sp]\n\t"
7978 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7983 "orl $0x200, (%%" _ASM_SP ")\n\t"
7984 __ASM_SIZE(push) " $%c[cs]\n\t"
7985 "call *%[entry]\n\t"
7987 #ifdef CONFIG_X86_64
7992 [ss]"i"(__KERNEL_DS),
7993 [cs]"i"(__KERNEL_CS)
7999 static bool vmx_mpx_supported(void)
8001 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8002 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8005 static bool vmx_xsaves_supported(void)
8007 return vmcs_config.cpu_based_2nd_exec_ctrl &
8008 SECONDARY_EXEC_XSAVES;
8011 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8016 bool idtv_info_valid;
8018 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8020 if (cpu_has_virtual_nmis()) {
8021 if (vmx->nmi_known_unmasked)
8024 * Can't use vmx->exit_intr_info since we're not sure what
8025 * the exit reason is.
8027 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8028 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8029 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8031 * SDM 3: 27.7.1.2 (September 2008)
8032 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8033 * a guest IRET fault.
8034 * SDM 3: 23.2.2 (September 2008)
8035 * Bit 12 is undefined in any of the following cases:
8036 * If the VM exit sets the valid bit in the IDT-vectoring
8037 * information field.
8038 * If the VM exit is due to a double fault.
8040 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8041 vector != DF_VECTOR && !idtv_info_valid)
8042 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8043 GUEST_INTR_STATE_NMI);
8045 vmx->nmi_known_unmasked =
8046 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8047 & GUEST_INTR_STATE_NMI);
8048 } else if (unlikely(vmx->soft_vnmi_blocked))
8049 vmx->vnmi_blocked_time +=
8050 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8053 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8054 u32 idt_vectoring_info,
8055 int instr_len_field,
8056 int error_code_field)
8060 bool idtv_info_valid;
8062 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8064 vcpu->arch.nmi_injected = false;
8065 kvm_clear_exception_queue(vcpu);
8066 kvm_clear_interrupt_queue(vcpu);
8068 if (!idtv_info_valid)
8071 kvm_make_request(KVM_REQ_EVENT, vcpu);
8073 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8074 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8077 case INTR_TYPE_NMI_INTR:
8078 vcpu->arch.nmi_injected = true;
8080 * SDM 3: 27.7.1.2 (September 2008)
8081 * Clear bit "block by NMI" before VM entry if a NMI
8084 vmx_set_nmi_mask(vcpu, false);
8086 case INTR_TYPE_SOFT_EXCEPTION:
8087 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8089 case INTR_TYPE_HARD_EXCEPTION:
8090 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8091 u32 err = vmcs_read32(error_code_field);
8092 kvm_requeue_exception_e(vcpu, vector, err);
8094 kvm_requeue_exception(vcpu, vector);
8096 case INTR_TYPE_SOFT_INTR:
8097 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8099 case INTR_TYPE_EXT_INTR:
8100 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8107 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8109 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8110 VM_EXIT_INSTRUCTION_LEN,
8111 IDT_VECTORING_ERROR_CODE);
8114 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8116 __vmx_complete_interrupts(vcpu,
8117 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8118 VM_ENTRY_INSTRUCTION_LEN,
8119 VM_ENTRY_EXCEPTION_ERROR_CODE);
8121 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8124 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8127 struct perf_guest_switch_msr *msrs;
8129 msrs = perf_guest_get_msrs(&nr_msrs);
8134 for (i = 0; i < nr_msrs; i++)
8135 if (msrs[i].host == msrs[i].guest)
8136 clear_atomic_switch_msr(vmx, msrs[i].msr);
8138 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8142 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8144 struct vcpu_vmx *vmx = to_vmx(vcpu);
8145 unsigned long debugctlmsr, cr4;
8147 /* Record the guest's net vcpu time for enforced NMI injections. */
8148 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8149 vmx->entry_time = ktime_get();
8151 /* Don't enter VMX if guest state is invalid, let the exit handler
8152 start emulation until we arrive back to a valid state */
8153 if (vmx->emulation_required)
8156 if (vmx->ple_window_dirty) {
8157 vmx->ple_window_dirty = false;
8158 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8161 if (vmx->nested.sync_shadow_vmcs) {
8162 copy_vmcs12_to_shadow(vmx);
8163 vmx->nested.sync_shadow_vmcs = false;
8166 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8167 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8168 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8169 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8171 cr4 = cr4_read_shadow();
8172 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8173 vmcs_writel(HOST_CR4, cr4);
8174 vmx->host_state.vmcs_host_cr4 = cr4;
8177 /* When single-stepping over STI and MOV SS, we must clear the
8178 * corresponding interruptibility bits in the guest state. Otherwise
8179 * vmentry fails as it then expects bit 14 (BS) in pending debug
8180 * exceptions being set, but that's not correct for the guest debugging
8182 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8183 vmx_set_interrupt_shadow(vcpu, 0);
8185 atomic_switch_perf_msrs(vmx);
8186 debugctlmsr = get_debugctlmsr();
8188 vmx->__launched = vmx->loaded_vmcs->launched;
8190 /* Store host registers */
8191 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8192 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8193 "push %%" _ASM_CX " \n\t"
8194 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8196 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8197 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8199 /* Reload cr2 if changed */
8200 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8201 "mov %%cr2, %%" _ASM_DX " \n\t"
8202 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8204 "mov %%" _ASM_AX", %%cr2 \n\t"
8206 /* Check if vmlaunch of vmresume is needed */
8207 "cmpl $0, %c[launched](%0) \n\t"
8208 /* Load guest registers. Don't clobber flags. */
8209 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8210 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8211 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8212 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8213 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8214 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8215 #ifdef CONFIG_X86_64
8216 "mov %c[r8](%0), %%r8 \n\t"
8217 "mov %c[r9](%0), %%r9 \n\t"
8218 "mov %c[r10](%0), %%r10 \n\t"
8219 "mov %c[r11](%0), %%r11 \n\t"
8220 "mov %c[r12](%0), %%r12 \n\t"
8221 "mov %c[r13](%0), %%r13 \n\t"
8222 "mov %c[r14](%0), %%r14 \n\t"
8223 "mov %c[r15](%0), %%r15 \n\t"
8225 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8227 /* Enter guest mode */
8229 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8231 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8233 /* Save guest registers, load host registers, keep flags */
8234 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8236 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8237 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8238 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8239 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8240 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8241 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8242 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8243 #ifdef CONFIG_X86_64
8244 "mov %%r8, %c[r8](%0) \n\t"
8245 "mov %%r9, %c[r9](%0) \n\t"
8246 "mov %%r10, %c[r10](%0) \n\t"
8247 "mov %%r11, %c[r11](%0) \n\t"
8248 "mov %%r12, %c[r12](%0) \n\t"
8249 "mov %%r13, %c[r13](%0) \n\t"
8250 "mov %%r14, %c[r14](%0) \n\t"
8251 "mov %%r15, %c[r15](%0) \n\t"
8253 "mov %%cr2, %%" _ASM_AX " \n\t"
8254 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8256 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8257 "setbe %c[fail](%0) \n\t"
8258 ".pushsection .rodata \n\t"
8259 ".global vmx_return \n\t"
8260 "vmx_return: " _ASM_PTR " 2b \n\t"
8262 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8263 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8264 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8265 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8266 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8267 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8268 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8269 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8270 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8271 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8272 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8273 #ifdef CONFIG_X86_64
8274 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8275 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8276 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8277 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8278 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8279 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8280 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8281 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8283 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8284 [wordsize]"i"(sizeof(ulong))
8286 #ifdef CONFIG_X86_64
8287 , "rax", "rbx", "rdi", "rsi"
8288 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8290 , "eax", "ebx", "edi", "esi"
8294 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8296 update_debugctlmsr(debugctlmsr);
8298 #ifndef CONFIG_X86_64
8300 * The sysexit path does not restore ds/es, so we must set them to
8301 * a reasonable value ourselves.
8303 * We can't defer this to vmx_load_host_state() since that function
8304 * may be executed in interrupt context, which saves and restore segments
8305 * around it, nullifying its effect.
8307 loadsegment(ds, __USER_DS);
8308 loadsegment(es, __USER_DS);
8311 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8312 | (1 << VCPU_EXREG_RFLAGS)
8313 | (1 << VCPU_EXREG_PDPTR)
8314 | (1 << VCPU_EXREG_SEGMENTS)
8315 | (1 << VCPU_EXREG_CR3));
8316 vcpu->arch.regs_dirty = 0;
8318 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8320 vmx->loaded_vmcs->launched = 1;
8322 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8323 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8326 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8327 * we did not inject a still-pending event to L1 now because of
8328 * nested_run_pending, we need to re-enable this bit.
8330 if (vmx->nested.nested_run_pending)
8331 kvm_make_request(KVM_REQ_EVENT, vcpu);
8333 vmx->nested.nested_run_pending = 0;
8335 vmx_complete_atomic_exit(vmx);
8336 vmx_recover_nmi_blocking(vmx);
8337 vmx_complete_interrupts(vmx);
8340 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8342 struct vcpu_vmx *vmx = to_vmx(vcpu);
8345 if (vmx->loaded_vmcs == &vmx->vmcs01)
8349 vmx->loaded_vmcs = &vmx->vmcs01;
8351 vmx_vcpu_load(vcpu, cpu);
8356 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8358 struct vcpu_vmx *vmx = to_vmx(vcpu);
8361 vmx_disable_pml(vmx);
8363 leave_guest_mode(vcpu);
8364 vmx_load_vmcs01(vcpu);
8366 free_loaded_vmcs(vmx->loaded_vmcs);
8367 kfree(vmx->guest_msrs);
8368 kvm_vcpu_uninit(vcpu);
8369 kmem_cache_free(kvm_vcpu_cache, vmx);
8372 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8375 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8379 return ERR_PTR(-ENOMEM);
8383 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8387 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8388 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8392 if (!vmx->guest_msrs) {
8396 vmx->loaded_vmcs = &vmx->vmcs01;
8397 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8398 if (!vmx->loaded_vmcs->vmcs)
8401 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8402 loaded_vmcs_init(vmx->loaded_vmcs);
8407 vmx_vcpu_load(&vmx->vcpu, cpu);
8408 vmx->vcpu.cpu = cpu;
8409 err = vmx_vcpu_setup(vmx);
8410 vmx_vcpu_put(&vmx->vcpu);
8414 if (vm_need_virtualize_apic_accesses(kvm)) {
8415 err = alloc_apic_access_page(kvm);
8421 if (!kvm->arch.ept_identity_map_addr)
8422 kvm->arch.ept_identity_map_addr =
8423 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8424 err = init_rmode_identity_map(kvm);
8430 nested_vmx_setup_ctls_msrs(vmx);
8432 vmx->nested.posted_intr_nv = -1;
8433 vmx->nested.current_vmptr = -1ull;
8434 vmx->nested.current_vmcs12 = NULL;
8437 * If PML is turned on, failure on enabling PML just results in failure
8438 * of creating the vcpu, therefore we can simplify PML logic (by
8439 * avoiding dealing with cases, such as enabling PML partially on vcpus
8440 * for the guest, etc.
8443 err = vmx_enable_pml(vmx);
8451 free_loaded_vmcs(vmx->loaded_vmcs);
8453 kfree(vmx->guest_msrs);
8455 kvm_vcpu_uninit(&vmx->vcpu);
8458 kmem_cache_free(kvm_vcpu_cache, vmx);
8459 return ERR_PTR(err);
8462 static void __init vmx_check_processor_compat(void *rtn)
8464 struct vmcs_config vmcs_conf;
8467 if (setup_vmcs_config(&vmcs_conf) < 0)
8469 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8470 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8471 smp_processor_id());
8476 static int get_ept_level(void)
8478 return VMX_EPT_DEFAULT_GAW + 1;
8481 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8485 /* For VT-d and EPT combination
8486 * 1. MMIO: always map as UC
8488 * a. VT-d without snooping control feature: can't guarantee the
8489 * result, try to trust guest.
8490 * b. VT-d with snooping control feature: snooping control feature of
8491 * VT-d engine can guarantee the cache correctness. Just set it
8492 * to WB to keep consistent with host. So the same as item 3.
8493 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8494 * consistent with host MTRR
8497 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8498 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8499 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8500 VMX_EPT_MT_EPTE_SHIFT;
8502 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8508 static int vmx_get_lpage_level(void)
8510 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8511 return PT_DIRECTORY_LEVEL;
8513 /* For shadow and EPT supported 1GB page */
8514 return PT_PDPE_LEVEL;
8517 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8519 struct kvm_cpuid_entry2 *best;
8520 struct vcpu_vmx *vmx = to_vmx(vcpu);
8523 vmx->rdtscp_enabled = false;
8524 if (vmx_rdtscp_supported()) {
8525 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8526 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8527 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8528 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8529 vmx->rdtscp_enabled = true;
8531 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8532 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8536 if (nested && !vmx->rdtscp_enabled)
8537 vmx->nested.nested_vmx_secondary_ctls_high &=
8538 ~SECONDARY_EXEC_RDTSCP;
8541 /* Exposing INVPCID only when PCID is exposed */
8542 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8543 if (vmx_invpcid_supported() &&
8544 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8545 guest_cpuid_has_pcid(vcpu)) {
8546 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8547 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8548 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8551 if (cpu_has_secondary_exec_ctrls()) {
8552 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8553 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8554 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8558 best->ebx &= ~bit(X86_FEATURE_INVPCID);
8562 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8564 if (func == 1 && nested)
8565 entry->ecx |= bit(X86_FEATURE_VMX);
8568 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8569 struct x86_exception *fault)
8571 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8574 if (fault->error_code & PFERR_RSVD_MASK)
8575 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8577 exit_reason = EXIT_REASON_EPT_VIOLATION;
8578 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8579 vmcs12->guest_physical_address = fault->address;
8582 /* Callbacks for nested_ept_init_mmu_context: */
8584 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8586 /* return the page table to be shadowed - in our case, EPT12 */
8587 return get_vmcs12(vcpu)->ept_pointer;
8590 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8592 WARN_ON(mmu_is_nested(vcpu));
8593 kvm_init_shadow_ept_mmu(vcpu,
8594 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8595 VMX_EPT_EXECUTE_ONLY_BIT);
8596 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8597 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8598 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8600 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
8603 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8605 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8608 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8611 bool inequality, bit;
8613 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8615 (error_code & vmcs12->page_fault_error_code_mask) !=
8616 vmcs12->page_fault_error_code_match;
8617 return inequality ^ bit;
8620 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8621 struct x86_exception *fault)
8623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8625 WARN_ON(!is_guest_mode(vcpu));
8627 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8628 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8629 vmcs_read32(VM_EXIT_INTR_INFO),
8630 vmcs_readl(EXIT_QUALIFICATION));
8632 kvm_inject_page_fault(vcpu, fault);
8635 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8636 struct vmcs12 *vmcs12)
8638 struct vcpu_vmx *vmx = to_vmx(vcpu);
8639 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8641 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8642 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8643 vmcs12->apic_access_addr >> maxphyaddr)
8647 * Translate L1 physical address to host physical
8648 * address for vmcs02. Keep the page pinned, so this
8649 * physical address remains valid. We keep a reference
8650 * to it so we can release it later.
8652 if (vmx->nested.apic_access_page) /* shouldn't happen */
8653 nested_release_page(vmx->nested.apic_access_page);
8654 vmx->nested.apic_access_page =
8655 nested_get_page(vcpu, vmcs12->apic_access_addr);
8658 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8659 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8660 vmcs12->virtual_apic_page_addr >> maxphyaddr)
8663 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8664 nested_release_page(vmx->nested.virtual_apic_page);
8665 vmx->nested.virtual_apic_page =
8666 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8669 * Failing the vm entry is _not_ what the processor does
8670 * but it's basically the only possibility we have.
8671 * We could still enter the guest if CR8 load exits are
8672 * enabled, CR8 store exits are enabled, and virtualize APIC
8673 * access is disabled; in this case the processor would never
8674 * use the TPR shadow and we could simply clear the bit from
8675 * the execution control. But such a configuration is useless,
8676 * so let's keep the code simple.
8678 if (!vmx->nested.virtual_apic_page)
8682 if (nested_cpu_has_posted_intr(vmcs12)) {
8683 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8684 vmcs12->posted_intr_desc_addr >> maxphyaddr)
8687 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8688 kunmap(vmx->nested.pi_desc_page);
8689 nested_release_page(vmx->nested.pi_desc_page);
8691 vmx->nested.pi_desc_page =
8692 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8693 if (!vmx->nested.pi_desc_page)
8696 vmx->nested.pi_desc =
8697 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8698 if (!vmx->nested.pi_desc) {
8699 nested_release_page_clean(vmx->nested.pi_desc_page);
8702 vmx->nested.pi_desc =
8703 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8704 (unsigned long)(vmcs12->posted_intr_desc_addr &
8711 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8713 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8714 struct vcpu_vmx *vmx = to_vmx(vcpu);
8716 if (vcpu->arch.virtual_tsc_khz == 0)
8719 /* Make sure short timeouts reliably trigger an immediate vmexit.
8720 * hrtimer_start does not guarantee this. */
8721 if (preemption_timeout <= 1) {
8722 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8726 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8727 preemption_timeout *= 1000000;
8728 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8729 hrtimer_start(&vmx->nested.preemption_timer,
8730 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8733 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8734 struct vmcs12 *vmcs12)
8739 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8742 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8746 maxphyaddr = cpuid_maxphyaddr(vcpu);
8748 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8749 ((addr + PAGE_SIZE) >> maxphyaddr))
8756 * Merge L0's and L1's MSR bitmap, return false to indicate that
8757 * we do not use the hardware.
8759 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8760 struct vmcs12 *vmcs12)
8764 unsigned long *msr_bitmap;
8766 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8769 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8774 msr_bitmap = (unsigned long *)kmap(page);
8776 nested_release_page_clean(page);
8781 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8782 if (nested_cpu_has_apic_reg_virt(vmcs12))
8783 for (msr = 0x800; msr <= 0x8ff; msr++)
8784 nested_vmx_disable_intercept_for_msr(
8786 vmx_msr_bitmap_nested,
8788 /* TPR is allowed */
8789 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8790 vmx_msr_bitmap_nested,
8791 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8792 MSR_TYPE_R | MSR_TYPE_W);
8793 if (nested_cpu_has_vid(vmcs12)) {
8794 /* EOI and self-IPI are allowed */
8795 nested_vmx_disable_intercept_for_msr(
8797 vmx_msr_bitmap_nested,
8798 APIC_BASE_MSR + (APIC_EOI >> 4),
8800 nested_vmx_disable_intercept_for_msr(
8802 vmx_msr_bitmap_nested,
8803 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8808 * Enable reading intercept of all the x2apic
8809 * MSRs. We should not rely on vmcs12 to do any
8810 * optimizations here, it may have been modified
8813 for (msr = 0x800; msr <= 0x8ff; msr++)
8814 __vmx_enable_intercept_for_msr(
8815 vmx_msr_bitmap_nested,
8819 __vmx_enable_intercept_for_msr(
8820 vmx_msr_bitmap_nested,
8821 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8823 __vmx_enable_intercept_for_msr(
8824 vmx_msr_bitmap_nested,
8825 APIC_BASE_MSR + (APIC_EOI >> 4),
8827 __vmx_enable_intercept_for_msr(
8828 vmx_msr_bitmap_nested,
8829 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8833 nested_release_page_clean(page);
8838 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8839 struct vmcs12 *vmcs12)
8841 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8842 !nested_cpu_has_apic_reg_virt(vmcs12) &&
8843 !nested_cpu_has_vid(vmcs12) &&
8844 !nested_cpu_has_posted_intr(vmcs12))
8848 * If virtualize x2apic mode is enabled,
8849 * virtualize apic access must be disabled.
8851 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8852 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8856 * If virtual interrupt delivery is enabled,
8857 * we must exit on external interrupts.
8859 if (nested_cpu_has_vid(vmcs12) &&
8860 !nested_exit_on_intr(vcpu))
8864 * bits 15:8 should be zero in posted_intr_nv,
8865 * the descriptor address has been already checked
8866 * in nested_get_vmcs12_pages.
8868 if (nested_cpu_has_posted_intr(vmcs12) &&
8869 (!nested_cpu_has_vid(vmcs12) ||
8870 !nested_exit_intr_ack_set(vcpu) ||
8871 vmcs12->posted_intr_nv & 0xff00))
8874 /* tpr shadow is needed by all apicv features. */
8875 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8881 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8882 unsigned long count_field,
8883 unsigned long addr_field)
8888 if (vmcs12_read_any(vcpu, count_field, &count) ||
8889 vmcs12_read_any(vcpu, addr_field, &addr)) {
8895 maxphyaddr = cpuid_maxphyaddr(vcpu);
8896 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8897 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8898 pr_warn_ratelimited(
8899 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8900 addr_field, maxphyaddr, count, addr);
8906 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8907 struct vmcs12 *vmcs12)
8909 if (vmcs12->vm_exit_msr_load_count == 0 &&
8910 vmcs12->vm_exit_msr_store_count == 0 &&
8911 vmcs12->vm_entry_msr_load_count == 0)
8912 return 0; /* Fast path */
8913 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8914 VM_EXIT_MSR_LOAD_ADDR) ||
8915 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8916 VM_EXIT_MSR_STORE_ADDR) ||
8917 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8918 VM_ENTRY_MSR_LOAD_ADDR))
8923 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8924 struct vmx_msr_entry *e)
8926 /* x2APIC MSR accesses are not allowed */
8927 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8929 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8930 e->index == MSR_IA32_UCODE_REV)
8932 if (e->reserved != 0)
8937 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8938 struct vmx_msr_entry *e)
8940 if (e->index == MSR_FS_BASE ||
8941 e->index == MSR_GS_BASE ||
8942 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8943 nested_vmx_msr_check_common(vcpu, e))
8948 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8949 struct vmx_msr_entry *e)
8951 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8952 nested_vmx_msr_check_common(vcpu, e))
8958 * Load guest's/host's msr at nested entry/exit.
8959 * return 0 for success, entry index for failure.
8961 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8964 struct vmx_msr_entry e;
8965 struct msr_data msr;
8967 msr.host_initiated = false;
8968 for (i = 0; i < count; i++) {
8969 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8971 pr_warn_ratelimited(
8972 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8973 __func__, i, gpa + i * sizeof(e));
8976 if (nested_vmx_load_msr_check(vcpu, &e)) {
8977 pr_warn_ratelimited(
8978 "%s check failed (%u, 0x%x, 0x%x)\n",
8979 __func__, i, e.index, e.reserved);
8982 msr.index = e.index;
8984 if (kvm_set_msr(vcpu, &msr)) {
8985 pr_warn_ratelimited(
8986 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8987 __func__, i, e.index, e.value);
8996 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8999 struct vmx_msr_entry e;
9001 for (i = 0; i < count; i++) {
9002 if (kvm_read_guest(vcpu->kvm,
9003 gpa + i * sizeof(e),
9004 &e, 2 * sizeof(u32))) {
9005 pr_warn_ratelimited(
9006 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9007 __func__, i, gpa + i * sizeof(e));
9010 if (nested_vmx_store_msr_check(vcpu, &e)) {
9011 pr_warn_ratelimited(
9012 "%s check failed (%u, 0x%x, 0x%x)\n",
9013 __func__, i, e.index, e.reserved);
9016 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9017 pr_warn_ratelimited(
9018 "%s cannot read MSR (%u, 0x%x)\n",
9019 __func__, i, e.index);
9022 if (kvm_write_guest(vcpu->kvm,
9023 gpa + i * sizeof(e) +
9024 offsetof(struct vmx_msr_entry, value),
9025 &e.value, sizeof(e.value))) {
9026 pr_warn_ratelimited(
9027 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9028 __func__, i, e.index, e.value);
9036 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9037 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9038 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9039 * guest in a way that will both be appropriate to L1's requests, and our
9040 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9041 * function also has additional necessary side-effects, like setting various
9042 * vcpu->arch fields.
9044 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9046 struct vcpu_vmx *vmx = to_vmx(vcpu);
9049 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9050 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9051 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9052 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9053 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9054 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9055 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9056 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9057 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9058 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9059 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9060 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9061 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9062 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9063 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9064 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9065 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9066 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9067 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9068 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9069 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9070 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9071 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9072 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9073 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9074 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9075 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9076 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9077 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9078 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9079 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9080 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9081 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9082 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9083 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9084 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9086 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9087 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9088 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9090 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9091 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9093 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9094 vmcs12->vm_entry_intr_info_field);
9095 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9096 vmcs12->vm_entry_exception_error_code);
9097 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9098 vmcs12->vm_entry_instruction_len);
9099 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9100 vmcs12->guest_interruptibility_info);
9101 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9102 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9103 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9104 vmcs12->guest_pending_dbg_exceptions);
9105 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9106 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9108 if (nested_cpu_has_xsaves(vmcs12))
9109 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9110 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9112 exec_control = vmcs12->pin_based_vm_exec_control;
9113 exec_control |= vmcs_config.pin_based_exec_ctrl;
9114 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9116 if (nested_cpu_has_posted_intr(vmcs12)) {
9118 * Note that we use L0's vector here and in
9119 * vmx_deliver_nested_posted_interrupt.
9121 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9122 vmx->nested.pi_pending = false;
9123 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9124 vmcs_write64(POSTED_INTR_DESC_ADDR,
9125 page_to_phys(vmx->nested.pi_desc_page) +
9126 (unsigned long)(vmcs12->posted_intr_desc_addr &
9129 exec_control &= ~PIN_BASED_POSTED_INTR;
9131 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9133 vmx->nested.preemption_timer_expired = false;
9134 if (nested_cpu_has_preemption_timer(vmcs12))
9135 vmx_start_preemption_timer(vcpu);
9138 * Whether page-faults are trapped is determined by a combination of
9139 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9140 * If enable_ept, L0 doesn't care about page faults and we should
9141 * set all of these to L1's desires. However, if !enable_ept, L0 does
9142 * care about (at least some) page faults, and because it is not easy
9143 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9144 * to exit on each and every L2 page fault. This is done by setting
9145 * MASK=MATCH=0 and (see below) EB.PF=1.
9146 * Note that below we don't need special code to set EB.PF beyond the
9147 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9148 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9149 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9151 * A problem with this approach (when !enable_ept) is that L1 may be
9152 * injected with more page faults than it asked for. This could have
9153 * caused problems, but in practice existing hypervisors don't care.
9154 * To fix this, we will need to emulate the PFEC checking (on the L1
9155 * page tables), using walk_addr(), when injecting PFs to L1.
9157 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9158 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9159 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9160 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9162 if (cpu_has_secondary_exec_ctrls()) {
9163 exec_control = vmx_secondary_exec_control(vmx);
9164 if (!vmx->rdtscp_enabled)
9165 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9166 /* Take the following fields only from vmcs12 */
9167 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9168 SECONDARY_EXEC_RDTSCP |
9169 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9170 SECONDARY_EXEC_APIC_REGISTER_VIRT);
9171 if (nested_cpu_has(vmcs12,
9172 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9173 exec_control |= vmcs12->secondary_vm_exec_control;
9175 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9177 * If translation failed, no matter: This feature asks
9178 * to exit when accessing the given address, and if it
9179 * can never be accessed, this feature won't do
9182 if (!vmx->nested.apic_access_page)
9184 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9186 vmcs_write64(APIC_ACCESS_ADDR,
9187 page_to_phys(vmx->nested.apic_access_page));
9188 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9189 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9191 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9192 kvm_vcpu_reload_apic_access_page(vcpu);
9195 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9196 vmcs_write64(EOI_EXIT_BITMAP0,
9197 vmcs12->eoi_exit_bitmap0);
9198 vmcs_write64(EOI_EXIT_BITMAP1,
9199 vmcs12->eoi_exit_bitmap1);
9200 vmcs_write64(EOI_EXIT_BITMAP2,
9201 vmcs12->eoi_exit_bitmap2);
9202 vmcs_write64(EOI_EXIT_BITMAP3,
9203 vmcs12->eoi_exit_bitmap3);
9204 vmcs_write16(GUEST_INTR_STATUS,
9205 vmcs12->guest_intr_status);
9208 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9213 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9214 * Some constant fields are set here by vmx_set_constant_host_state().
9215 * Other fields are different per CPU, and will be set later when
9216 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9218 vmx_set_constant_host_state(vmx);
9221 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9222 * entry, but only if the current (host) sp changed from the value
9223 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9224 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9225 * here we just force the write to happen on entry.
9229 exec_control = vmx_exec_control(vmx); /* L0's desires */
9230 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9231 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9232 exec_control &= ~CPU_BASED_TPR_SHADOW;
9233 exec_control |= vmcs12->cpu_based_vm_exec_control;
9235 if (exec_control & CPU_BASED_TPR_SHADOW) {
9236 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9237 page_to_phys(vmx->nested.virtual_apic_page));
9238 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9241 if (cpu_has_vmx_msr_bitmap() &&
9242 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9243 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9244 /* MSR_BITMAP will be set by following vmx_set_efer. */
9246 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9249 * Merging of IO bitmap not currently supported.
9250 * Rather, exit every time.
9252 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9253 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9255 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9257 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9258 * bitwise-or of what L1 wants to trap for L2, and what we want to
9259 * trap. Note that CR0.TS also needs updating - we do this later.
9261 update_exception_bitmap(vcpu);
9262 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9263 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9265 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9266 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9267 * bits are further modified by vmx_set_efer() below.
9269 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9271 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9272 * emulated by vmx_set_efer(), below.
9274 vm_entry_controls_init(vmx,
9275 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9276 ~VM_ENTRY_IA32E_MODE) |
9277 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9279 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9280 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9281 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9282 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9283 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9286 set_cr4_guest_host_mask(vmx);
9288 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9289 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9291 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9292 vmcs_write64(TSC_OFFSET,
9293 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9295 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9299 * Trivially support vpid by letting L2s share their parent
9300 * L1's vpid. TODO: move to a more elaborate solution, giving
9301 * each L2 its own vpid and exposing the vpid feature to L1.
9303 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9304 vmx_flush_tlb(vcpu);
9307 if (nested_cpu_has_ept(vmcs12)) {
9308 kvm_mmu_unload(vcpu);
9309 nested_ept_init_mmu_context(vcpu);
9312 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9313 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9314 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9315 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9317 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9318 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9319 vmx_set_efer(vcpu, vcpu->arch.efer);
9322 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9323 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9324 * The CR0_READ_SHADOW is what L2 should have expected to read given
9325 * the specifications by L1; It's not enough to take
9326 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9327 * have more bits than L1 expected.
9329 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9330 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9332 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9333 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9335 /* shadow page tables on either EPT or shadow page tables */
9336 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9337 kvm_mmu_reset_context(vcpu);
9340 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9343 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9346 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9347 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9348 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9349 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9352 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9353 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9357 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9358 * for running an L2 nested guest.
9360 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9362 struct vmcs12 *vmcs12;
9363 struct vcpu_vmx *vmx = to_vmx(vcpu);
9365 struct loaded_vmcs *vmcs02;
9369 if (!nested_vmx_check_permission(vcpu) ||
9370 !nested_vmx_check_vmcs12(vcpu))
9373 skip_emulated_instruction(vcpu);
9374 vmcs12 = get_vmcs12(vcpu);
9376 if (enable_shadow_vmcs)
9377 copy_shadow_to_vmcs12(vmx);
9380 * The nested entry process starts with enforcing various prerequisites
9381 * on vmcs12 as required by the Intel SDM, and act appropriately when
9382 * they fail: As the SDM explains, some conditions should cause the
9383 * instruction to fail, while others will cause the instruction to seem
9384 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9385 * To speed up the normal (success) code path, we should avoid checking
9386 * for misconfigurations which will anyway be caught by the processor
9387 * when using the merged vmcs02.
9389 if (vmcs12->launch_state == launch) {
9390 nested_vmx_failValid(vcpu,
9391 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9392 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9396 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9397 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9398 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9402 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9403 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9407 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9408 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9412 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9413 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9417 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9418 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9422 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9423 vmx->nested.nested_vmx_true_procbased_ctls_low,
9424 vmx->nested.nested_vmx_procbased_ctls_high) ||
9425 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9426 vmx->nested.nested_vmx_secondary_ctls_low,
9427 vmx->nested.nested_vmx_secondary_ctls_high) ||
9428 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9429 vmx->nested.nested_vmx_pinbased_ctls_low,
9430 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9431 !vmx_control_verify(vmcs12->vm_exit_controls,
9432 vmx->nested.nested_vmx_true_exit_ctls_low,
9433 vmx->nested.nested_vmx_exit_ctls_high) ||
9434 !vmx_control_verify(vmcs12->vm_entry_controls,
9435 vmx->nested.nested_vmx_true_entry_ctls_low,
9436 vmx->nested.nested_vmx_entry_ctls_high))
9438 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9442 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9443 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9444 nested_vmx_failValid(vcpu,
9445 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9449 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9450 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9451 nested_vmx_entry_failure(vcpu, vmcs12,
9452 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9455 if (vmcs12->vmcs_link_pointer != -1ull) {
9456 nested_vmx_entry_failure(vcpu, vmcs12,
9457 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9462 * If the load IA32_EFER VM-entry control is 1, the following checks
9463 * are performed on the field for the IA32_EFER MSR:
9464 * - Bits reserved in the IA32_EFER MSR must be 0.
9465 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9466 * the IA-32e mode guest VM-exit control. It must also be identical
9467 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9470 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9471 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9472 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9473 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9474 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9475 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9476 nested_vmx_entry_failure(vcpu, vmcs12,
9477 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9483 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9484 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9485 * the values of the LMA and LME bits in the field must each be that of
9486 * the host address-space size VM-exit control.
9488 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9489 ia32e = (vmcs12->vm_exit_controls &
9490 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9491 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9492 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9493 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9494 nested_vmx_entry_failure(vcpu, vmcs12,
9495 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9501 * We're finally done with prerequisite checking, and can start with
9505 vmcs02 = nested_get_current_vmcs02(vmx);
9509 enter_guest_mode(vcpu);
9511 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9513 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9514 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9517 vmx->loaded_vmcs = vmcs02;
9519 vmx_vcpu_load(vcpu, cpu);
9523 vmx_segment_cache_clear(vmx);
9525 prepare_vmcs02(vcpu, vmcs12);
9527 msr_entry_idx = nested_vmx_load_msr(vcpu,
9528 vmcs12->vm_entry_msr_load_addr,
9529 vmcs12->vm_entry_msr_load_count);
9530 if (msr_entry_idx) {
9531 leave_guest_mode(vcpu);
9532 vmx_load_vmcs01(vcpu);
9533 nested_vmx_entry_failure(vcpu, vmcs12,
9534 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9538 vmcs12->launch_state = 1;
9540 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9541 return kvm_vcpu_halt(vcpu);
9543 vmx->nested.nested_run_pending = 1;
9546 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9547 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9548 * returned as far as L1 is concerned. It will only return (and set
9549 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9555 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9556 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9557 * This function returns the new value we should put in vmcs12.guest_cr0.
9558 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9559 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9560 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9561 * didn't trap the bit, because if L1 did, so would L0).
9562 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9563 * been modified by L2, and L1 knows it. So just leave the old value of
9564 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9565 * isn't relevant, because if L0 traps this bit it can set it to anything.
9566 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9567 * changed these bits, and therefore they need to be updated, but L0
9568 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9569 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9571 static inline unsigned long
9572 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9575 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9576 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9577 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9578 vcpu->arch.cr0_guest_owned_bits));
9581 static inline unsigned long
9582 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9585 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9586 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9587 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9588 vcpu->arch.cr4_guest_owned_bits));
9591 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9592 struct vmcs12 *vmcs12)
9597 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9598 nr = vcpu->arch.exception.nr;
9599 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9601 if (kvm_exception_is_soft(nr)) {
9602 vmcs12->vm_exit_instruction_len =
9603 vcpu->arch.event_exit_inst_len;
9604 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9606 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9608 if (vcpu->arch.exception.has_error_code) {
9609 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9610 vmcs12->idt_vectoring_error_code =
9611 vcpu->arch.exception.error_code;
9614 vmcs12->idt_vectoring_info_field = idt_vectoring;
9615 } else if (vcpu->arch.nmi_injected) {
9616 vmcs12->idt_vectoring_info_field =
9617 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9618 } else if (vcpu->arch.interrupt.pending) {
9619 nr = vcpu->arch.interrupt.nr;
9620 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9622 if (vcpu->arch.interrupt.soft) {
9623 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9624 vmcs12->vm_entry_instruction_len =
9625 vcpu->arch.event_exit_inst_len;
9627 idt_vectoring |= INTR_TYPE_EXT_INTR;
9629 vmcs12->idt_vectoring_info_field = idt_vectoring;
9633 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9635 struct vcpu_vmx *vmx = to_vmx(vcpu);
9637 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9638 vmx->nested.preemption_timer_expired) {
9639 if (vmx->nested.nested_run_pending)
9641 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9645 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9646 if (vmx->nested.nested_run_pending ||
9647 vcpu->arch.interrupt.pending)
9649 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9650 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9651 INTR_INFO_VALID_MASK, 0);
9653 * The NMI-triggered VM exit counts as injection:
9654 * clear this one and block further NMIs.
9656 vcpu->arch.nmi_pending = 0;
9657 vmx_set_nmi_mask(vcpu, true);
9661 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9662 nested_exit_on_intr(vcpu)) {
9663 if (vmx->nested.nested_run_pending)
9665 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9669 return vmx_complete_nested_posted_interrupt(vcpu);
9672 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9675 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9678 if (ktime_to_ns(remaining) <= 0)
9681 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9682 do_div(value, 1000000);
9683 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9687 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9688 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9689 * and this function updates it to reflect the changes to the guest state while
9690 * L2 was running (and perhaps made some exits which were handled directly by L0
9691 * without going back to L1), and to reflect the exit reason.
9692 * Note that we do not have to copy here all VMCS fields, just those that
9693 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9694 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9695 * which already writes to vmcs12 directly.
9697 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9698 u32 exit_reason, u32 exit_intr_info,
9699 unsigned long exit_qualification)
9701 /* update guest state fields: */
9702 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9703 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9705 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9706 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9707 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9709 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9710 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9711 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9712 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9713 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9714 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9715 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9716 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9717 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9718 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9719 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9720 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9721 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9722 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9723 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9724 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9725 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9726 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9727 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9728 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9729 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9730 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9731 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9732 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9733 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9734 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9735 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9736 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9737 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9738 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9739 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9740 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9741 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9742 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9743 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9744 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9746 vmcs12->guest_interruptibility_info =
9747 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9748 vmcs12->guest_pending_dbg_exceptions =
9749 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9750 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9751 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9753 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9755 if (nested_cpu_has_preemption_timer(vmcs12)) {
9756 if (vmcs12->vm_exit_controls &
9757 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9758 vmcs12->vmx_preemption_timer_value =
9759 vmx_get_preemption_timer_value(vcpu);
9760 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9764 * In some cases (usually, nested EPT), L2 is allowed to change its
9765 * own CR3 without exiting. If it has changed it, we must keep it.
9766 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9767 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9769 * Additionally, restore L2's PDPTR to vmcs12.
9772 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9773 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9774 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9775 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9776 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9779 if (nested_cpu_has_vid(vmcs12))
9780 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9782 vmcs12->vm_entry_controls =
9783 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9784 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9786 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9787 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9788 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9791 /* TODO: These cannot have changed unless we have MSR bitmaps and
9792 * the relevant bit asks not to trap the change */
9793 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9794 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9795 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9796 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9797 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9798 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9799 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9800 if (vmx_mpx_supported())
9801 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9802 if (nested_cpu_has_xsaves(vmcs12))
9803 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9805 /* update exit information fields: */
9807 vmcs12->vm_exit_reason = exit_reason;
9808 vmcs12->exit_qualification = exit_qualification;
9810 vmcs12->vm_exit_intr_info = exit_intr_info;
9811 if ((vmcs12->vm_exit_intr_info &
9812 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9813 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9814 vmcs12->vm_exit_intr_error_code =
9815 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9816 vmcs12->idt_vectoring_info_field = 0;
9817 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9818 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9820 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9821 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9822 * instead of reading the real value. */
9823 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9826 * Transfer the event that L0 or L1 may wanted to inject into
9827 * L2 to IDT_VECTORING_INFO_FIELD.
9829 vmcs12_save_pending_event(vcpu, vmcs12);
9833 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9834 * preserved above and would only end up incorrectly in L1.
9836 vcpu->arch.nmi_injected = false;
9837 kvm_clear_exception_queue(vcpu);
9838 kvm_clear_interrupt_queue(vcpu);
9842 * A part of what we need to when the nested L2 guest exits and we want to
9843 * run its L1 parent, is to reset L1's guest state to the host state specified
9845 * This function is to be called not only on normal nested exit, but also on
9846 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9847 * Failures During or After Loading Guest State").
9848 * This function should be called when the active VMCS is L1's (vmcs01).
9850 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9851 struct vmcs12 *vmcs12)
9853 struct kvm_segment seg;
9855 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9856 vcpu->arch.efer = vmcs12->host_ia32_efer;
9857 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9858 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9860 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9861 vmx_set_efer(vcpu, vcpu->arch.efer);
9863 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9864 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9865 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9867 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9868 * actually changed, because it depends on the current state of
9869 * fpu_active (which may have changed).
9870 * Note that vmx_set_cr0 refers to efer set above.
9872 vmx_set_cr0(vcpu, vmcs12->host_cr0);
9874 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9875 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9876 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9878 update_exception_bitmap(vcpu);
9879 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9880 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9883 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9884 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9886 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9887 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9889 nested_ept_uninit_mmu_context(vcpu);
9891 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9892 kvm_mmu_reset_context(vcpu);
9895 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9899 * Trivially support vpid by letting L2s share their parent
9900 * L1's vpid. TODO: move to a more elaborate solution, giving
9901 * each L2 its own vpid and exposing the vpid feature to L1.
9903 vmx_flush_tlb(vcpu);
9907 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9908 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9909 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9910 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9911 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9913 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9914 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9915 vmcs_write64(GUEST_BNDCFGS, 0);
9917 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9918 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9919 vcpu->arch.pat = vmcs12->host_ia32_pat;
9921 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9922 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9923 vmcs12->host_ia32_perf_global_ctrl);
9925 /* Set L1 segment info according to Intel SDM
9926 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9927 seg = (struct kvm_segment) {
9929 .limit = 0xFFFFFFFF,
9930 .selector = vmcs12->host_cs_selector,
9936 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9940 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9941 seg = (struct kvm_segment) {
9943 .limit = 0xFFFFFFFF,
9950 seg.selector = vmcs12->host_ds_selector;
9951 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9952 seg.selector = vmcs12->host_es_selector;
9953 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9954 seg.selector = vmcs12->host_ss_selector;
9955 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9956 seg.selector = vmcs12->host_fs_selector;
9957 seg.base = vmcs12->host_fs_base;
9958 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9959 seg.selector = vmcs12->host_gs_selector;
9960 seg.base = vmcs12->host_gs_base;
9961 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9962 seg = (struct kvm_segment) {
9963 .base = vmcs12->host_tr_base,
9965 .selector = vmcs12->host_tr_selector,
9969 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9971 kvm_set_dr(vcpu, 7, 0x400);
9972 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9974 if (cpu_has_vmx_msr_bitmap())
9975 vmx_set_msr_bitmap(vcpu);
9977 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9978 vmcs12->vm_exit_msr_load_count))
9979 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9983 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9984 * and modify vmcs12 to make it see what it would expect to see there if
9985 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9987 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9989 unsigned long exit_qualification)
9991 struct vcpu_vmx *vmx = to_vmx(vcpu);
9992 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9994 /* trying to cancel vmlaunch/vmresume is a bug */
9995 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9997 leave_guest_mode(vcpu);
9998 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9999 exit_qualification);
10001 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10002 vmcs12->vm_exit_msr_store_count))
10003 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10005 vmx_load_vmcs01(vcpu);
10007 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10008 && nested_exit_intr_ack_set(vcpu)) {
10009 int irq = kvm_cpu_get_interrupt(vcpu);
10011 vmcs12->vm_exit_intr_info = irq |
10012 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10015 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10016 vmcs12->exit_qualification,
10017 vmcs12->idt_vectoring_info_field,
10018 vmcs12->vm_exit_intr_info,
10019 vmcs12->vm_exit_intr_error_code,
10022 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10023 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10024 vmx_segment_cache_clear(vmx);
10026 /* if no vmcs02 cache requested, remove the one we used */
10027 if (VMCS02_POOL_SIZE == 0)
10028 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10030 load_vmcs12_host_state(vcpu, vmcs12);
10032 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10033 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10035 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10038 /* Unpin physical memory we referred to in vmcs02 */
10039 if (vmx->nested.apic_access_page) {
10040 nested_release_page(vmx->nested.apic_access_page);
10041 vmx->nested.apic_access_page = NULL;
10043 if (vmx->nested.virtual_apic_page) {
10044 nested_release_page(vmx->nested.virtual_apic_page);
10045 vmx->nested.virtual_apic_page = NULL;
10047 if (vmx->nested.pi_desc_page) {
10048 kunmap(vmx->nested.pi_desc_page);
10049 nested_release_page(vmx->nested.pi_desc_page);
10050 vmx->nested.pi_desc_page = NULL;
10051 vmx->nested.pi_desc = NULL;
10055 * We are now running in L2, mmu_notifier will force to reload the
10056 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10058 kvm_vcpu_reload_apic_access_page(vcpu);
10061 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10062 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10063 * success or failure flag accordingly.
10065 if (unlikely(vmx->fail)) {
10067 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10069 nested_vmx_succeed(vcpu);
10070 if (enable_shadow_vmcs)
10071 vmx->nested.sync_shadow_vmcs = true;
10073 /* in case we halted in L2 */
10074 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10078 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10080 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10082 if (is_guest_mode(vcpu))
10083 nested_vmx_vmexit(vcpu, -1, 0, 0);
10084 free_nested(to_vmx(vcpu));
10088 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10089 * 23.7 "VM-entry failures during or after loading guest state" (this also
10090 * lists the acceptable exit-reason and exit-qualification parameters).
10091 * It should only be called before L2 actually succeeded to run, and when
10092 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10094 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10095 struct vmcs12 *vmcs12,
10096 u32 reason, unsigned long qualification)
10098 load_vmcs12_host_state(vcpu, vmcs12);
10099 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10100 vmcs12->exit_qualification = qualification;
10101 nested_vmx_succeed(vcpu);
10102 if (enable_shadow_vmcs)
10103 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10106 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10107 struct x86_instruction_info *info,
10108 enum x86_intercept_stage stage)
10110 return X86EMUL_CONTINUE;
10113 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10116 shrink_ple_window(vcpu);
10119 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10120 struct kvm_memory_slot *slot)
10122 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10123 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10126 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10127 struct kvm_memory_slot *slot)
10129 kvm_mmu_slot_set_dirty(kvm, slot);
10132 static void vmx_flush_log_dirty(struct kvm *kvm)
10134 kvm_flush_pml_buffers(kvm);
10137 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10138 struct kvm_memory_slot *memslot,
10139 gfn_t offset, unsigned long mask)
10141 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10144 static struct kvm_x86_ops vmx_x86_ops = {
10145 .cpu_has_kvm_support = cpu_has_kvm_support,
10146 .disabled_by_bios = vmx_disabled_by_bios,
10147 .hardware_setup = hardware_setup,
10148 .hardware_unsetup = hardware_unsetup,
10149 .check_processor_compatibility = vmx_check_processor_compat,
10150 .hardware_enable = hardware_enable,
10151 .hardware_disable = hardware_disable,
10152 .cpu_has_accelerated_tpr = report_flexpriority,
10154 .vcpu_create = vmx_create_vcpu,
10155 .vcpu_free = vmx_free_vcpu,
10156 .vcpu_reset = vmx_vcpu_reset,
10158 .prepare_guest_switch = vmx_save_host_state,
10159 .vcpu_load = vmx_vcpu_load,
10160 .vcpu_put = vmx_vcpu_put,
10162 .update_db_bp_intercept = update_exception_bitmap,
10163 .get_msr = vmx_get_msr,
10164 .set_msr = vmx_set_msr,
10165 .get_segment_base = vmx_get_segment_base,
10166 .get_segment = vmx_get_segment,
10167 .set_segment = vmx_set_segment,
10168 .get_cpl = vmx_get_cpl,
10169 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10170 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10171 .decache_cr3 = vmx_decache_cr3,
10172 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10173 .set_cr0 = vmx_set_cr0,
10174 .set_cr3 = vmx_set_cr3,
10175 .set_cr4 = vmx_set_cr4,
10176 .set_efer = vmx_set_efer,
10177 .get_idt = vmx_get_idt,
10178 .set_idt = vmx_set_idt,
10179 .get_gdt = vmx_get_gdt,
10180 .set_gdt = vmx_set_gdt,
10181 .get_dr6 = vmx_get_dr6,
10182 .set_dr6 = vmx_set_dr6,
10183 .set_dr7 = vmx_set_dr7,
10184 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10185 .cache_reg = vmx_cache_reg,
10186 .get_rflags = vmx_get_rflags,
10187 .set_rflags = vmx_set_rflags,
10188 .fpu_deactivate = vmx_fpu_deactivate,
10190 .tlb_flush = vmx_flush_tlb,
10192 .run = vmx_vcpu_run,
10193 .handle_exit = vmx_handle_exit,
10194 .skip_emulated_instruction = skip_emulated_instruction,
10195 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10196 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10197 .patch_hypercall = vmx_patch_hypercall,
10198 .set_irq = vmx_inject_irq,
10199 .set_nmi = vmx_inject_nmi,
10200 .queue_exception = vmx_queue_exception,
10201 .cancel_injection = vmx_cancel_injection,
10202 .interrupt_allowed = vmx_interrupt_allowed,
10203 .nmi_allowed = vmx_nmi_allowed,
10204 .get_nmi_mask = vmx_get_nmi_mask,
10205 .set_nmi_mask = vmx_set_nmi_mask,
10206 .enable_nmi_window = enable_nmi_window,
10207 .enable_irq_window = enable_irq_window,
10208 .update_cr8_intercept = update_cr8_intercept,
10209 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10210 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10211 .vm_has_apicv = vmx_vm_has_apicv,
10212 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10213 .hwapic_irr_update = vmx_hwapic_irr_update,
10214 .hwapic_isr_update = vmx_hwapic_isr_update,
10215 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10216 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10218 .set_tss_addr = vmx_set_tss_addr,
10219 .get_tdp_level = get_ept_level,
10220 .get_mt_mask = vmx_get_mt_mask,
10222 .get_exit_info = vmx_get_exit_info,
10224 .get_lpage_level = vmx_get_lpage_level,
10226 .cpuid_update = vmx_cpuid_update,
10228 .rdtscp_supported = vmx_rdtscp_supported,
10229 .invpcid_supported = vmx_invpcid_supported,
10231 .set_supported_cpuid = vmx_set_supported_cpuid,
10233 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10235 .set_tsc_khz = vmx_set_tsc_khz,
10236 .read_tsc_offset = vmx_read_tsc_offset,
10237 .write_tsc_offset = vmx_write_tsc_offset,
10238 .adjust_tsc_offset = vmx_adjust_tsc_offset,
10239 .compute_tsc_offset = vmx_compute_tsc_offset,
10240 .read_l1_tsc = vmx_read_l1_tsc,
10242 .set_tdp_cr3 = vmx_set_cr3,
10244 .check_intercept = vmx_check_intercept,
10245 .handle_external_intr = vmx_handle_external_intr,
10246 .mpx_supported = vmx_mpx_supported,
10247 .xsaves_supported = vmx_xsaves_supported,
10249 .check_nested_events = vmx_check_nested_events,
10251 .sched_in = vmx_sched_in,
10253 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10254 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10255 .flush_log_dirty = vmx_flush_log_dirty,
10256 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10259 static int __init vmx_init(void)
10261 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10262 __alignof__(struct vcpu_vmx), THIS_MODULE);
10266 #ifdef CONFIG_KEXEC
10267 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10268 crash_vmclear_local_loaded_vmcss);
10274 static void __exit vmx_exit(void)
10276 #ifdef CONFIG_KEXEC
10277 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10284 module_init(vmx_init)
10285 module_exit(vmx_exit)