arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49
  50 #include "trace.h"
  51
  52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  53 #define __ex_clear(x, reg) \
  54         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  55
  56 MODULE_AUTHOR("Qumranet");
  57 MODULE_LICENSE("GPL");
  58
  59 static const struct x86_cpu_id vmx_cpu_id[] = {
  60         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  61         {}
  62 };
  63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  64
  65 static bool __read_mostly enable_vpid = 1;
  66 module_param_named(vpid, enable_vpid, bool, 0444);
  67
  68 static bool __read_mostly flexpriority_enabled = 1;
  69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_ept = 1;
  72 module_param_named(ept, enable_ept, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_unrestricted_guest = 1;
  75 module_param_named(unrestricted_guest,
  76                         enable_unrestricted_guest, bool, S_IRUGO);
  77
  78 static bool __read_mostly enable_ept_ad_bits = 1;
  79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  80
  81 static bool __read_mostly emulate_invalid_guest_state = true;
  82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  83
  84 static bool __read_mostly vmm_exclusive = 1;
  85 module_param(vmm_exclusive, bool, S_IRUGO);
  86
  87 static bool __read_mostly fasteoi = 1;
  88 module_param(fasteoi, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_apicv = 1;
  91 module_param(enable_apicv, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_shadow_vmcs = 1;
  94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  95 /*
  96  * If nested=1, nested virtualization is supported, i.e., guests may use
  97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  98  * use VMX instructions.
  99  */
 100 static bool __read_mostly nested = 0;
 101 module_param(nested, bool, S_IRUGO);
 102
 103 static u64 __read_mostly host_xss;
 104
 105 static bool __read_mostly enable_pml = 1;
 106 module_param_named(pml, enable_pml, bool, S_IRUGO);
 107
 108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 110 #define KVM_VM_CR0_ALWAYS_ON                                            \
 111         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 112 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 113         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 114          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 115
 116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 118
 119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 120
 121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 122
 123 /*
 124  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 125  * ple_gap:    upper bound on the amount of time between two successive
 126  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 127  *             According to test, this time is usually smaller than 128 cycles.
 128  * ple_window: upper bound on the amount of time a guest is allowed to execute
 129  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 130  *             less than 2^12 cycles
 131  * Time is measured based on a counter that runs at the same rate as the TSC,
 132  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 133  */
 134 #define KVM_VMX_DEFAULT_PLE_GAP           128
 135 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 139                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 140
 141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 142 module_param(ple_gap, int, S_IRUGO);
 143
 144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 145 module_param(ple_window, int, S_IRUGO);
 146
 147 /* Default doubles per-vcpu window every exit. */
 148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 149 module_param(ple_window_grow, int, S_IRUGO);
 150
 151 /* Default resets per-vcpu window every exit to ple_window. */
 152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 153 module_param(ple_window_shrink, int, S_IRUGO);
 154
 155 /* Default is to compute the maximum so we can never overflow. */
 156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 157 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 158 module_param(ple_window_max, int, S_IRUGO);
 159
 160 extern const ulong vmx_return;
 161
 162 #define NR_AUTOLOAD_MSRS 8
 163 #define VMCS02_POOL_SIZE 1
 164
 165 struct vmcs {
 166         u32 revision_id;
 167         u32 abort;
 168         char data[0];
 169 };
 170
 171 /*
 172  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 173  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 174  * loaded on this CPU (so we can clear them if the CPU goes down).
 175  */
 176 struct loaded_vmcs {
 177         struct vmcs *vmcs;
 178         int cpu;
 179         int launched;
 180         struct list_head loaded_vmcss_on_cpu_link;
 181 };
 182
 183 struct shared_msr_entry {
 184         unsigned index;
 185         u64 data;
 186         u64 mask;
 187 };
 188
 189 /*
 190  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 191  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 192  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 193  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 194  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 195  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 196  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 197  * underlying hardware which will be used to run L2.
 198  * This structure is packed to ensure that its layout is identical across
 199  * machines (necessary for live migration).
 200  * If there are changes in this struct, VMCS12_REVISION must be changed.
 201  */
 202 typedef u64 natural_width;
 203 struct __packed vmcs12 {
 204         /* According to the Intel spec, a VMCS region must start with the
 205          * following two fields. Then follow implementation-specific data.
 206          */
 207         u32 revision_id;
 208         u32 abort;
 209
 210         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 211         u32 padding[7]; /* room for future expansion */
 212
 213         u64 io_bitmap_a;
 214         u64 io_bitmap_b;
 215         u64 msr_bitmap;
 216         u64 vm_exit_msr_store_addr;
 217         u64 vm_exit_msr_load_addr;
 218         u64 vm_entry_msr_load_addr;
 219         u64 tsc_offset;
 220         u64 virtual_apic_page_addr;
 221         u64 apic_access_addr;
 222         u64 posted_intr_desc_addr;
 223         u64 ept_pointer;
 224         u64 eoi_exit_bitmap0;
 225         u64 eoi_exit_bitmap1;
 226         u64 eoi_exit_bitmap2;
 227         u64 eoi_exit_bitmap3;
 228         u64 xss_exit_bitmap;
 229         u64 guest_physical_address;
 230         u64 vmcs_link_pointer;
 231         u64 guest_ia32_debugctl;
 232         u64 guest_ia32_pat;
 233         u64 guest_ia32_efer;
 234         u64 guest_ia32_perf_global_ctrl;
 235         u64 guest_pdptr0;
 236         u64 guest_pdptr1;
 237         u64 guest_pdptr2;
 238         u64 guest_pdptr3;
 239         u64 guest_bndcfgs;
 240         u64 host_ia32_pat;
 241         u64 host_ia32_efer;
 242         u64 host_ia32_perf_global_ctrl;
 243         u64 padding64[8]; /* room for future expansion */
 244         /*
 245          * To allow migration of L1 (complete with its L2 guests) between
 246          * machines of different natural widths (32 or 64 bit), we cannot have
 247          * unsigned long fields with no explict size. We use u64 (aliased
 248          * natural_width) instead. Luckily, x86 is little-endian.
 249          */
 250         natural_width cr0_guest_host_mask;
 251         natural_width cr4_guest_host_mask;
 252         natural_width cr0_read_shadow;
 253         natural_width cr4_read_shadow;
 254         natural_width cr3_target_value0;
 255         natural_width cr3_target_value1;
 256         natural_width cr3_target_value2;
 257         natural_width cr3_target_value3;
 258         natural_width exit_qualification;
 259         natural_width guest_linear_address;
 260         natural_width guest_cr0;
 261         natural_width guest_cr3;
 262         natural_width guest_cr4;
 263         natural_width guest_es_base;
 264         natural_width guest_cs_base;
 265         natural_width guest_ss_base;
 266         natural_width guest_ds_base;
 267         natural_width guest_fs_base;
 268         natural_width guest_gs_base;
 269         natural_width guest_ldtr_base;
 270         natural_width guest_tr_base;
 271         natural_width guest_gdtr_base;
 272         natural_width guest_idtr_base;
 273         natural_width guest_dr7;
 274         natural_width guest_rsp;
 275         natural_width guest_rip;
 276         natural_width guest_rflags;
 277         natural_width guest_pending_dbg_exceptions;
 278         natural_width guest_sysenter_esp;
 279         natural_width guest_sysenter_eip;
 280         natural_width host_cr0;
 281         natural_width host_cr3;
 282         natural_width host_cr4;
 283         natural_width host_fs_base;
 284         natural_width host_gs_base;
 285         natural_width host_tr_base;
 286         natural_width host_gdtr_base;
 287         natural_width host_idtr_base;
 288         natural_width host_ia32_sysenter_esp;
 289         natural_width host_ia32_sysenter_eip;
 290         natural_width host_rsp;
 291         natural_width host_rip;
 292         natural_width paddingl[8]; /* room for future expansion */
 293         u32 pin_based_vm_exec_control;
 294         u32 cpu_based_vm_exec_control;
 295         u32 exception_bitmap;
 296         u32 page_fault_error_code_mask;
 297         u32 page_fault_error_code_match;
 298         u32 cr3_target_count;
 299         u32 vm_exit_controls;
 300         u32 vm_exit_msr_store_count;
 301         u32 vm_exit_msr_load_count;
 302         u32 vm_entry_controls;
 303         u32 vm_entry_msr_load_count;
 304         u32 vm_entry_intr_info_field;
 305         u32 vm_entry_exception_error_code;
 306         u32 vm_entry_instruction_len;
 307         u32 tpr_threshold;
 308         u32 secondary_vm_exec_control;
 309         u32 vm_instruction_error;
 310         u32 vm_exit_reason;
 311         u32 vm_exit_intr_info;
 312         u32 vm_exit_intr_error_code;
 313         u32 idt_vectoring_info_field;
 314         u32 idt_vectoring_error_code;
 315         u32 vm_exit_instruction_len;
 316         u32 vmx_instruction_info;
 317         u32 guest_es_limit;
 318         u32 guest_cs_limit;
 319         u32 guest_ss_limit;
 320         u32 guest_ds_limit;
 321         u32 guest_fs_limit;
 322         u32 guest_gs_limit;
 323         u32 guest_ldtr_limit;
 324         u32 guest_tr_limit;
 325         u32 guest_gdtr_limit;
 326         u32 guest_idtr_limit;
 327         u32 guest_es_ar_bytes;
 328         u32 guest_cs_ar_bytes;
 329         u32 guest_ss_ar_bytes;
 330         u32 guest_ds_ar_bytes;
 331         u32 guest_fs_ar_bytes;
 332         u32 guest_gs_ar_bytes;
 333         u32 guest_ldtr_ar_bytes;
 334         u32 guest_tr_ar_bytes;
 335         u32 guest_interruptibility_info;
 336         u32 guest_activity_state;
 337         u32 guest_sysenter_cs;
 338         u32 host_ia32_sysenter_cs;
 339         u32 vmx_preemption_timer_value;
 340         u32 padding32[7]; /* room for future expansion */
 341         u16 virtual_processor_id;
 342         u16 posted_intr_nv;
 343         u16 guest_es_selector;
 344         u16 guest_cs_selector;
 345         u16 guest_ss_selector;
 346         u16 guest_ds_selector;
 347         u16 guest_fs_selector;
 348         u16 guest_gs_selector;
 349         u16 guest_ldtr_selector;
 350         u16 guest_tr_selector;
 351         u16 guest_intr_status;
 352         u16 host_es_selector;
 353         u16 host_cs_selector;
 354         u16 host_ss_selector;
 355         u16 host_ds_selector;
 356         u16 host_fs_selector;
 357         u16 host_gs_selector;
 358         u16 host_tr_selector;
 359 };
 360
 361 /*
 362  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 363  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 364  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 365  */
 366 #define VMCS12_REVISION 0x11e57ed0
 367
 368 /*
 369  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 370  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 371  * current implementation, 4K are reserved to avoid future complications.
 372  */
 373 #define VMCS12_SIZE 0x1000
 374
 375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 376 struct vmcs02_list {
 377         struct list_head list;
 378         gpa_t vmptr;
 379         struct loaded_vmcs vmcs02;
 380 };
 381
 382 /*
 383  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 384  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 385  */
 386 struct nested_vmx {
 387         /* Has the level1 guest done vmxon? */
 388         bool vmxon;
 389         gpa_t vmxon_ptr;
 390
 391         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 392         gpa_t current_vmptr;
 393         /* The host-usable pointer to the above */
 394         struct page *current_vmcs12_page;
 395         struct vmcs12 *current_vmcs12;
 396         struct vmcs *current_shadow_vmcs;
 397         /*
 398          * Indicates if the shadow vmcs must be updated with the
 399          * data hold by vmcs12
 400          */
 401         bool sync_shadow_vmcs;
 402
 403         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 404         struct list_head vmcs02_pool;
 405         int vmcs02_num;
 406         u64 vmcs01_tsc_offset;
 407         /* L2 must run next, and mustn't decide to exit to L1. */
 408         bool nested_run_pending;
 409         /*
 410          * Guest pages referred to in vmcs02 with host-physical pointers, so
 411          * we must keep them pinned while L2 runs.
 412          */
 413         struct page *apic_access_page;
 414         struct page *virtual_apic_page;
 415         struct page *pi_desc_page;
 416         struct pi_desc *pi_desc;
 417         bool pi_pending;
 418         u16 posted_intr_nv;
 419         u64 msr_ia32_feature_control;
 420
 421         struct hrtimer preemption_timer;
 422         bool preemption_timer_expired;
 423
 424         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 425         u64 vmcs01_debugctl;
 426
 427         u32 nested_vmx_procbased_ctls_low;
 428         u32 nested_vmx_procbased_ctls_high;
 429         u32 nested_vmx_true_procbased_ctls_low;
 430         u32 nested_vmx_secondary_ctls_low;
 431         u32 nested_vmx_secondary_ctls_high;
 432         u32 nested_vmx_pinbased_ctls_low;
 433         u32 nested_vmx_pinbased_ctls_high;
 434         u32 nested_vmx_exit_ctls_low;
 435         u32 nested_vmx_exit_ctls_high;
 436         u32 nested_vmx_true_exit_ctls_low;
 437         u32 nested_vmx_entry_ctls_low;
 438         u32 nested_vmx_entry_ctls_high;
 439         u32 nested_vmx_true_entry_ctls_low;
 440         u32 nested_vmx_misc_low;
 441         u32 nested_vmx_misc_high;
 442         u32 nested_vmx_ept_caps;
 443 };
 444
 445 #define POSTED_INTR_ON  0
 446 /* Posted-Interrupt Descriptor */
 447 struct pi_desc {
 448         u32 pir[8];     /* Posted interrupt requested */
 449         u32 control;    /* bit 0 of control is outstanding notification bit */
 450         u32 rsvd[7];
 451 } __aligned(64);
 452
 453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 454 {
 455         return test_and_set_bit(POSTED_INTR_ON,
 456                         (unsigned long *)&pi_desc->control);
 457 }
 458
 459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 460 {
 461         return test_and_clear_bit(POSTED_INTR_ON,
 462                         (unsigned long *)&pi_desc->control);
 463 }
 464
 465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 466 {
 467         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 468 }
 469
 470 struct vcpu_vmx {
 471         struct kvm_vcpu       vcpu;
 472         unsigned long         host_rsp;
 473         u8                    fail;
 474         bool                  nmi_known_unmasked;
 475         u32                   exit_intr_info;
 476         u32                   idt_vectoring_info;
 477         ulong                 rflags;
 478         struct shared_msr_entry *guest_msrs;
 479         int                   nmsrs;
 480         int                   save_nmsrs;
 481         unsigned long         host_idt_base;
 482 #ifdef CONFIG_X86_64
 483         u64                   msr_host_kernel_gs_base;
 484         u64                   msr_guest_kernel_gs_base;
 485 #endif
 486         u32 vm_entry_controls_shadow;
 487         u32 vm_exit_controls_shadow;
 488         /*
 489          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 490          * non-nested (L1) guest, it always points to vmcs01. For a nested
 491          * guest (L2), it points to a different VMCS.
 492          */
 493         struct loaded_vmcs    vmcs01;
 494         struct loaded_vmcs   *loaded_vmcs;
 495         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 496         struct msr_autoload {
 497                 unsigned nr;
 498                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 499                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 500         } msr_autoload;
 501         struct {
 502                 int           loaded;
 503                 u16           fs_sel, gs_sel, ldt_sel;
 504 #ifdef CONFIG_X86_64
 505                 u16           ds_sel, es_sel;
 506 #endif
 507                 int           gs_ldt_reload_needed;
 508                 int           fs_reload_needed;
 509                 u64           msr_host_bndcfgs;
 510                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 511         } host_state;
 512         struct {
 513                 int vm86_active;
 514                 ulong save_rflags;
 515                 struct kvm_segment segs[8];
 516         } rmode;
 517         struct {
 518                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 519                 struct kvm_save_segment {
 520                         u16 selector;
 521                         unsigned long base;
 522                         u32 limit;
 523                         u32 ar;
 524                 } seg[8];
 525         } segment_cache;
 526         int vpid;
 527         bool emulation_required;
 528
 529         /* Support for vnmi-less CPUs */
 530         int soft_vnmi_blocked;
 531         ktime_t entry_time;
 532         s64 vnmi_blocked_time;
 533         u32 exit_reason;
 534
 535         bool rdtscp_enabled;
 536
 537         /* Posted interrupt descriptor */
 538         struct pi_desc pi_desc;
 539
 540         /* Support for a guest hypervisor (nested VMX) */
 541         struct nested_vmx nested;
 542
 543         /* Dynamic PLE window. */
 544         int ple_window;
 545         bool ple_window_dirty;
 546
 547         /* Support for PML */
 548 #define PML_ENTITY_NUM          512
 549         struct page *pml_pg;
 550 };
 551
 552 enum segment_cache_field {
 553         SEG_FIELD_SEL = 0,
 554         SEG_FIELD_BASE = 1,
 555         SEG_FIELD_LIMIT = 2,
 556         SEG_FIELD_AR = 3,
 557
 558         SEG_FIELD_NR = 4
 559 };
 560
 561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 562 {
 563         return container_of(vcpu, struct vcpu_vmx, vcpu);
 564 }
 565
 566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 567 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 568 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 569                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 570
 571
 572 static unsigned long shadow_read_only_fields[] = {
 573         /*
 574          * We do NOT shadow fields that are modified when L0
 575          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 576          * VMXON...) executed by L1.
 577          * For example, VM_INSTRUCTION_ERROR is read
 578          * by L1 if a vmx instruction fails (part of the error path).
 579          * Note the code assumes this logic. If for some reason
 580          * we start shadowing these fields then we need to
 581          * force a shadow sync when L0 emulates vmx instructions
 582          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 583          * by nested_vmx_failValid)
 584          */
 585         VM_EXIT_REASON,
 586         VM_EXIT_INTR_INFO,
 587         VM_EXIT_INSTRUCTION_LEN,
 588         IDT_VECTORING_INFO_FIELD,
 589         IDT_VECTORING_ERROR_CODE,
 590         VM_EXIT_INTR_ERROR_CODE,
 591         EXIT_QUALIFICATION,
 592         GUEST_LINEAR_ADDRESS,
 593         GUEST_PHYSICAL_ADDRESS
 594 };
 595 static int max_shadow_read_only_fields =
 596         ARRAY_SIZE(shadow_read_only_fields);
 597
 598 static unsigned long shadow_read_write_fields[] = {
 599         TPR_THRESHOLD,
 600         GUEST_RIP,
 601         GUEST_RSP,
 602         GUEST_CR0,
 603         GUEST_CR3,
 604         GUEST_CR4,
 605         GUEST_INTERRUPTIBILITY_INFO,
 606         GUEST_RFLAGS,
 607         GUEST_CS_SELECTOR,
 608         GUEST_CS_AR_BYTES,
 609         GUEST_CS_LIMIT,
 610         GUEST_CS_BASE,
 611         GUEST_ES_BASE,
 612         GUEST_BNDCFGS,
 613         CR0_GUEST_HOST_MASK,
 614         CR0_READ_SHADOW,
 615         CR4_READ_SHADOW,
 616         TSC_OFFSET,
 617         EXCEPTION_BITMAP,
 618         CPU_BASED_VM_EXEC_CONTROL,
 619         VM_ENTRY_EXCEPTION_ERROR_CODE,
 620         VM_ENTRY_INTR_INFO_FIELD,
 621         VM_ENTRY_INSTRUCTION_LEN,
 622         VM_ENTRY_EXCEPTION_ERROR_CODE,
 623         HOST_FS_BASE,
 624         HOST_GS_BASE,
 625         HOST_FS_SELECTOR,
 626         HOST_GS_SELECTOR
 627 };
 628 static int max_shadow_read_write_fields =
 629         ARRAY_SIZE(shadow_read_write_fields);
 630
 631 static const unsigned short vmcs_field_to_offset_table[] = {
 632         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 633         FIELD(POSTED_INTR_NV, posted_intr_nv),
 634         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 635         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 636         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 637         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 638         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 639         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 640         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 641         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 642         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 643         FIELD(HOST_ES_SELECTOR, host_es_selector),
 644         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 645         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 646         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 647         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 648         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 649         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 650         FIELD64(IO_BITMAP_A, io_bitmap_a),
 651         FIELD64(IO_BITMAP_B, io_bitmap_b),
 652         FIELD64(MSR_BITMAP, msr_bitmap),
 653         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 654         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 655         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 656         FIELD64(TSC_OFFSET, tsc_offset),
 657         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 658         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 659         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 660         FIELD64(EPT_POINTER, ept_pointer),
 661         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 662         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 663         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 664         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 665         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 666         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 667         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 668         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 669         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 670         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 671         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 672         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 673         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 674         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 675         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 676         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 677         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 678         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 679         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 680         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 681         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 682         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 683         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 684         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 685         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 686         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 687         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 688         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 689         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 690         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 691         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 692         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 693         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 694         FIELD(TPR_THRESHOLD, tpr_threshold),
 695         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 696         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 697         FIELD(VM_EXIT_REASON, vm_exit_reason),
 698         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 699         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 700         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 701         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 702         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 703         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 704         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 705         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 706         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 707         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 708         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 709         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 710         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 711         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 712         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 713         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 714         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 715         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 716         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 717         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 718         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 719         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 720         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 721         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 722         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 723         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 724         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 725         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 726         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 727         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 728         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 729         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 730         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 731         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 732         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 733         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 734         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 735         FIELD(EXIT_QUALIFICATION, exit_qualification),
 736         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 737         FIELD(GUEST_CR0, guest_cr0),
 738         FIELD(GUEST_CR3, guest_cr3),
 739         FIELD(GUEST_CR4, guest_cr4),
 740         FIELD(GUEST_ES_BASE, guest_es_base),
 741         FIELD(GUEST_CS_BASE, guest_cs_base),
 742         FIELD(GUEST_SS_BASE, guest_ss_base),
 743         FIELD(GUEST_DS_BASE, guest_ds_base),
 744         FIELD(GUEST_FS_BASE, guest_fs_base),
 745         FIELD(GUEST_GS_BASE, guest_gs_base),
 746         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 747         FIELD(GUEST_TR_BASE, guest_tr_base),
 748         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 749         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 750         FIELD(GUEST_DR7, guest_dr7),
 751         FIELD(GUEST_RSP, guest_rsp),
 752         FIELD(GUEST_RIP, guest_rip),
 753         FIELD(GUEST_RFLAGS, guest_rflags),
 754         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 755         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 756         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 757         FIELD(HOST_CR0, host_cr0),
 758         FIELD(HOST_CR3, host_cr3),
 759         FIELD(HOST_CR4, host_cr4),
 760         FIELD(HOST_FS_BASE, host_fs_base),
 761         FIELD(HOST_GS_BASE, host_gs_base),
 762         FIELD(HOST_TR_BASE, host_tr_base),
 763         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 764         FIELD(HOST_IDTR_BASE, host_idtr_base),
 765         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 766         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 767         FIELD(HOST_RSP, host_rsp),
 768         FIELD(HOST_RIP, host_rip),
 769 };
 770
 771 static inline short vmcs_field_to_offset(unsigned long field)
 772 {
 773         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 774
 775         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 776             vmcs_field_to_offset_table[field] == 0)
 777                 return -ENOENT;
 778
 779         return vmcs_field_to_offset_table[field];
 780 }
 781
 782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 783 {
 784         return to_vmx(vcpu)->nested.current_vmcs12;
 785 }
 786
 787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 788 {
 789         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 790         if (is_error_page(page))
 791                 return NULL;
 792
 793         return page;
 794 }
 795
 796 static void nested_release_page(struct page *page)
 797 {
 798         kvm_release_page_dirty(page);
 799 }
 800
 801 static void nested_release_page_clean(struct page *page)
 802 {
 803         kvm_release_page_clean(page);
 804 }
 805
 806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 807 static u64 construct_eptp(unsigned long root_hpa);
 808 static void kvm_cpu_vmxon(u64 addr);
 809 static void kvm_cpu_vmxoff(void);
 810 static bool vmx_mpx_supported(void);
 811 static bool vmx_xsaves_supported(void);
 812 static int vmx_vm_has_apicv(struct kvm *kvm);
 813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 815                             struct kvm_segment *var, int seg);
 816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 817                             struct kvm_segment *var, int seg);
 818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 823 static int alloc_identity_pagetable(struct kvm *kvm);
 824
 825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 827 /*
 828  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 829  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 830  */
 831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 833
 834 static unsigned long *vmx_io_bitmap_a;
 835 static unsigned long *vmx_io_bitmap_b;
 836 static unsigned long *vmx_msr_bitmap_legacy;
 837 static unsigned long *vmx_msr_bitmap_longmode;
 838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 840 static unsigned long *vmx_msr_bitmap_nested;
 841 static unsigned long *vmx_vmread_bitmap;
 842 static unsigned long *vmx_vmwrite_bitmap;
 843
 844 static bool cpu_has_load_ia32_efer;
 845 static bool cpu_has_load_perf_global_ctrl;
 846
 847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 848 static DEFINE_SPINLOCK(vmx_vpid_lock);
 849
 850 static struct vmcs_config {
 851         int size;
 852         int order;
 853         u32 revision_id;
 854         u32 pin_based_exec_ctrl;
 855         u32 cpu_based_exec_ctrl;
 856         u32 cpu_based_2nd_exec_ctrl;
 857         u32 vmexit_ctrl;
 858         u32 vmentry_ctrl;
 859 } vmcs_config;
 860
 861 static struct vmx_capability {
 862         u32 ept;
 863         u32 vpid;
 864 } vmx_capability;
 865
 866 #define VMX_SEGMENT_FIELD(seg)                                  \
 867         [VCPU_SREG_##seg] = {                                   \
 868                 .selector = GUEST_##seg##_SELECTOR,             \
 869                 .base = GUEST_##seg##_BASE,                     \
 870                 .limit = GUEST_##seg##_LIMIT,                   \
 871                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 872         }
 873
 874 static const struct kvm_vmx_segment_field {
 875         unsigned selector;
 876         unsigned base;
 877         unsigned limit;
 878         unsigned ar_bytes;
 879 } kvm_vmx_segment_fields[] = {
 880         VMX_SEGMENT_FIELD(CS),
 881         VMX_SEGMENT_FIELD(DS),
 882         VMX_SEGMENT_FIELD(ES),
 883         VMX_SEGMENT_FIELD(FS),
 884         VMX_SEGMENT_FIELD(GS),
 885         VMX_SEGMENT_FIELD(SS),
 886         VMX_SEGMENT_FIELD(TR),
 887         VMX_SEGMENT_FIELD(LDTR),
 888 };
 889
 890 static u64 host_efer;
 891
 892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 893
 894 /*
 895  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 896  * away by decrementing the array size.
 897  */
 898 static const u32 vmx_msr_index[] = {
 899 #ifdef CONFIG_X86_64
 900         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 901 #endif
 902         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 903 };
 904
 905 static inline bool is_page_fault(u32 intr_info)
 906 {
 907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 908                              INTR_INFO_VALID_MASK)) ==
 909                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 910 }
 911
 912 static inline bool is_no_device(u32 intr_info)
 913 {
 914         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 915                              INTR_INFO_VALID_MASK)) ==
 916                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 917 }
 918
 919 static inline bool is_invalid_opcode(u32 intr_info)
 920 {
 921         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 922                              INTR_INFO_VALID_MASK)) ==
 923                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 924 }
 925
 926 static inline bool is_external_interrupt(u32 intr_info)
 927 {
 928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 929                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 930 }
 931
 932 static inline bool is_machine_check(u32 intr_info)
 933 {
 934         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 935                              INTR_INFO_VALID_MASK)) ==
 936                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 937 }
 938
 939 static inline bool cpu_has_vmx_msr_bitmap(void)
 940 {
 941         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 942 }
 943
 944 static inline bool cpu_has_vmx_tpr_shadow(void)
 945 {
 946         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 947 }
 948
 949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 950 {
 951         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 952 }
 953
 954 static inline bool cpu_has_secondary_exec_ctrls(void)
 955 {
 956         return vmcs_config.cpu_based_exec_ctrl &
 957                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 958 }
 959
 960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 961 {
 962         return vmcs_config.cpu_based_2nd_exec_ctrl &
 963                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 964 }
 965
 966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 967 {
 968         return vmcs_config.cpu_based_2nd_exec_ctrl &
 969                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 970 }
 971
 972 static inline bool cpu_has_vmx_apic_register_virt(void)
 973 {
 974         return vmcs_config.cpu_based_2nd_exec_ctrl &
 975                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 976 }
 977
 978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 979 {
 980         return vmcs_config.cpu_based_2nd_exec_ctrl &
 981                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 982 }
 983
 984 static inline bool cpu_has_vmx_posted_intr(void)
 985 {
 986         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 987 }
 988
 989 static inline bool cpu_has_vmx_apicv(void)
 990 {
 991         return cpu_has_vmx_apic_register_virt() &&
 992                 cpu_has_vmx_virtual_intr_delivery() &&
 993                 cpu_has_vmx_posted_intr();
 994 }
 995
 996 static inline bool cpu_has_vmx_flexpriority(void)
 997 {
 998         return cpu_has_vmx_tpr_shadow() &&
 999                 cpu_has_vmx_virtualize_apic_accesses();
1000 }
1001
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 {
1004         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 {
1009         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1010 }
1011
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 {
1014         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1015 }
1016
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1018 {
1019         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020 }
1021
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 {
1024         return vmx_capability.ept & VMX_EPT_AD_BIT;
1025 }
1026
1027 static inline bool cpu_has_vmx_invept_context(void)
1028 {
1029         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1030 }
1031
1032 static inline bool cpu_has_vmx_invept_global(void)
1033 {
1034         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1035 }
1036
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1038 {
1039         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040 }
1041
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1043 {
1044         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045 }
1046
1047 static inline bool cpu_has_vmx_ept(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_ENABLE_EPT;
1051 }
1052
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057 }
1058
1059 static inline bool cpu_has_vmx_ple(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063 }
1064
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 {
1067         return flexpriority_enabled && irqchip_in_kernel(kvm);
1068 }
1069
1070 static inline bool cpu_has_vmx_vpid(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_ENABLE_VPID;
1074 }
1075
1076 static inline bool cpu_has_vmx_rdtscp(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_RDTSCP;
1080 }
1081
1082 static inline bool cpu_has_vmx_invpcid(void)
1083 {
1084         return vmcs_config.cpu_based_2nd_exec_ctrl &
1085                 SECONDARY_EXEC_ENABLE_INVPCID;
1086 }
1087
1088 static inline bool cpu_has_virtual_nmis(void)
1089 {
1090         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_WBINVD_EXITING;
1097 }
1098
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1100 {
1101         u64 vmx_msr;
1102         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103         /* check if the cpu supports writing r/o exit information fields */
1104         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105                 return false;
1106
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_SHADOW_VMCS;
1109 }
1110
1111 static inline bool cpu_has_vmx_pml(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114 }
1115
1116 static inline bool report_flexpriority(void)
1117 {
1118         return flexpriority_enabled;
1119 }
1120
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 {
1123         return vmcs12->cpu_based_vm_exec_control & bit;
1124 }
1125
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 {
1128         return (vmcs12->cpu_based_vm_exec_control &
1129                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130                 (vmcs12->secondary_vm_exec_control & bit);
1131 }
1132
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 {
1135         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136 }
1137
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 {
1140         return vmcs12->pin_based_vm_exec_control &
1141                 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 {
1146         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147 }
1148
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 {
1151         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152                 vmx_xsaves_supported();
1153 }
1154
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 {
1157         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158 }
1159
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 {
1162         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163 }
1164
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 {
1167         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168 }
1169
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 {
1172         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173 }
1174
1175 static inline bool is_exception(u32 intr_info)
1176 {
1177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179 }
1180
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182                               u32 exit_intr_info,
1183                               unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185                         struct vmcs12 *vmcs12,
1186                         u32 reason, unsigned long qualification);
1187
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1189 {
1190         int i;
1191
1192         for (i = 0; i < vmx->nmsrs; ++i)
1193                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1194                         return i;
1195         return -1;
1196 }
1197
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199 {
1200     struct {
1201         u64 vpid : 16;
1202         u64 rsvd : 48;
1203         u64 gva;
1204     } operand = { vpid, 0, gva };
1205
1206     asm volatile (__ex(ASM_VMX_INVVPID)
1207                   /* CF==1 or ZF==1 --> rc = -1 */
1208                   "; ja 1f ; ud2 ; 1:"
1209                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1210 }
1211
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213 {
1214         struct {
1215                 u64 eptp, gpa;
1216         } operand = {eptp, gpa};
1217
1218         asm volatile (__ex(ASM_VMX_INVEPT)
1219                         /* CF==1 or ZF==1 --> rc = -1 */
1220                         "; ja 1f ; ud2 ; 1:\n"
1221                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1222 }
1223
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1225 {
1226         int i;
1227
1228         i = __find_msr_index(vmx, msr);
1229         if (i >= 0)
1230                 return &vmx->guest_msrs[i];
1231         return NULL;
1232 }
1233
1234 static void vmcs_clear(struct vmcs *vmcs)
1235 {
1236         u64 phys_addr = __pa(vmcs);
1237         u8 error;
1238
1239         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1241                       : "cc", "memory");
1242         if (error)
1243                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244                        vmcs, phys_addr);
1245 }
1246
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 {
1249         vmcs_clear(loaded_vmcs->vmcs);
1250         loaded_vmcs->cpu = -1;
1251         loaded_vmcs->launched = 0;
1252 }
1253
1254 static void vmcs_load(struct vmcs *vmcs)
1255 {
1256         u64 phys_addr = __pa(vmcs);
1257         u8 error;
1258
1259         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1261                         : "cc", "memory");
1262         if (error)
1263                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1264                        vmcs, phys_addr);
1265 }
1266
1267 #ifdef CONFIG_KEXEC
1268 /*
1269  * This bitmap is used to indicate whether the vmclear
1270  * operation is enabled on all cpus. All disabled by
1271  * default.
1272  */
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275 static inline void crash_enable_local_vmclear(int cpu)
1276 {
1277         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278 }
1279
1280 static inline void crash_disable_local_vmclear(int cpu)
1281 {
1282         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283 }
1284
1285 static inline int crash_local_vmclear_enabled(int cpu)
1286 {
1287         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288 }
1289
1290 static void crash_vmclear_local_loaded_vmcss(void)
1291 {
1292         int cpu = raw_smp_processor_id();
1293         struct loaded_vmcs *v;
1294
1295         if (!crash_local_vmclear_enabled(cpu))
1296                 return;
1297
1298         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299                             loaded_vmcss_on_cpu_link)
1300                 vmcs_clear(v->vmcs);
1301 }
1302 #else
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1306
1307 static void __loaded_vmcs_clear(void *arg)
1308 {
1309         struct loaded_vmcs *loaded_vmcs = arg;
1310         int cpu = raw_smp_processor_id();
1311
1312         if (loaded_vmcs->cpu != cpu)
1313                 return; /* vcpu migration can race with cpu offline */
1314         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315                 per_cpu(current_vmcs, cpu) = NULL;
1316         crash_disable_local_vmclear(cpu);
1317         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1318
1319         /*
1320          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321          * is before setting loaded_vmcs->vcpu to -1 which is done in
1322          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323          * then adds the vmcs into percpu list before it is deleted.
1324          */
1325         smp_wmb();
1326
1327         loaded_vmcs_init(loaded_vmcs);
1328         crash_enable_local_vmclear(cpu);
1329 }
1330
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         int cpu = loaded_vmcs->cpu;
1334
1335         if (cpu != -1)
1336                 smp_call_function_single(cpu,
1337                          __loaded_vmcs_clear, loaded_vmcs, 1);
1338 }
1339
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1341 {
1342         if (vmx->vpid == 0)
1343                 return;
1344
1345         if (cpu_has_vmx_invvpid_single())
1346                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1347 }
1348
1349 static inline void vpid_sync_vcpu_global(void)
1350 {
1351         if (cpu_has_vmx_invvpid_global())
1352                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353 }
1354
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 {
1357         if (cpu_has_vmx_invvpid_single())
1358                 vpid_sync_vcpu_single(vmx);
1359         else
1360                 vpid_sync_vcpu_global();
1361 }
1362
1363 static inline void ept_sync_global(void)
1364 {
1365         if (cpu_has_vmx_invept_global())
1366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367 }
1368
1369 static inline void ept_sync_context(u64 eptp)
1370 {
1371         if (enable_ept) {
1372                 if (cpu_has_vmx_invept_context())
1373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374                 else
1375                         ept_sync_global();
1376         }
1377 }
1378
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 {
1381         unsigned long value;
1382
1383         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384                       : "=a"(value) : "d"(field) : "cc");
1385         return value;
1386 }
1387
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1389 {
1390         return vmcs_readl(field);
1391 }
1392
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1394 {
1395         return vmcs_readl(field);
1396 }
1397
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1399 {
1400 #ifdef CONFIG_X86_64
1401         return vmcs_readl(field);
1402 #else
1403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404 #endif
1405 }
1406
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 {
1409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411         dump_stack();
1412 }
1413
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1415 {
1416         u8 error;
1417
1418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1420         if (unlikely(error))
1421                 vmwrite_error(field, value);
1422 }
1423
1424 static void vmcs_write16(unsigned long field, u16 value)
1425 {
1426         vmcs_writel(field, value);
1427 }
1428
1429 static void vmcs_write32(unsigned long field, u32 value)
1430 {
1431         vmcs_writel(field, value);
1432 }
1433
1434 static void vmcs_write64(unsigned long field, u64 value)
1435 {
1436         vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1438         asm volatile ("");
1439         vmcs_writel(field+1, value >> 32);
1440 #endif
1441 }
1442
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 {
1445         vmcs_writel(field, vmcs_readl(field) & ~mask);
1446 }
1447
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 {
1450         vmcs_writel(field, vmcs_readl(field) | mask);
1451 }
1452
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 {
1455         vmcs_write32(VM_ENTRY_CONTROLS, val);
1456         vmx->vm_entry_controls_shadow = val;
1457 }
1458
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 {
1461         if (vmx->vm_entry_controls_shadow != val)
1462                 vm_entry_controls_init(vmx, val);
1463 }
1464
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 {
1467         return vmx->vm_entry_controls_shadow;
1468 }
1469
1470
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 {
1473         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474 }
1475
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 {
1478         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479 }
1480
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 {
1483         vmcs_write32(VM_EXIT_CONTROLS, val);
1484         vmx->vm_exit_controls_shadow = val;
1485 }
1486
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 {
1489         if (vmx->vm_exit_controls_shadow != val)
1490                 vm_exit_controls_init(vmx, val);
1491 }
1492
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 {
1495         return vmx->vm_exit_controls_shadow;
1496 }
1497
1498
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 {
1501         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502 }
1503
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 {
1506         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507 }
1508
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 {
1511         vmx->segment_cache.bitmask = 0;
1512 }
1513
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515                                        unsigned field)
1516 {
1517         bool ret;
1518         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522                 vmx->segment_cache.bitmask = 0;
1523         }
1524         ret = vmx->segment_cache.bitmask & mask;
1525         vmx->segment_cache.bitmask |= mask;
1526         return ret;
1527 }
1528
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 {
1531         u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535         return *p;
1536 }
1537
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 {
1540         ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544         return *p;
1545 }
1546
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 {
1549         u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553         return *p;
1554 }
1555
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 {
1558         u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562         return *p;
1563 }
1564
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566 {
1567         u32 eb;
1568
1569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571         if ((vcpu->guest_debug &
1572              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574                 eb |= 1u << BP_VECTOR;
1575         if (to_vmx(vcpu)->rmode.vm86_active)
1576                 eb = ~0;
1577         if (enable_ept)
1578                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579         if (vcpu->fpu_active)
1580                 eb &= ~(1u << NM_VECTOR);
1581
1582         /* When we are running a nested L2 guest and L1 specified for it a
1583          * certain exception bitmap, we must trap the same exceptions and pass
1584          * them to L1. When running L2, we will only handle the exceptions
1585          * specified above if L1 did not want them.
1586          */
1587         if (is_guest_mode(vcpu))
1588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
1590         vmcs_write32(EXCEPTION_BITMAP, eb);
1591 }
1592
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594                 unsigned long entry, unsigned long exit)
1595 {
1596         vm_entry_controls_clearbit(vmx, entry);
1597         vm_exit_controls_clearbit(vmx, exit);
1598 }
1599
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601 {
1602         unsigned i;
1603         struct msr_autoload *m = &vmx->msr_autoload;
1604
1605         switch (msr) {
1606         case MSR_EFER:
1607                 if (cpu_has_load_ia32_efer) {
1608                         clear_atomic_switch_msr_special(vmx,
1609                                         VM_ENTRY_LOAD_IA32_EFER,
1610                                         VM_EXIT_LOAD_IA32_EFER);
1611                         return;
1612                 }
1613                 break;
1614         case MSR_CORE_PERF_GLOBAL_CTRL:
1615                 if (cpu_has_load_perf_global_ctrl) {
1616                         clear_atomic_switch_msr_special(vmx,
1617                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619                         return;
1620                 }
1621                 break;
1622         }
1623
1624         for (i = 0; i < m->nr; ++i)
1625                 if (m->guest[i].index == msr)
1626                         break;
1627
1628         if (i == m->nr)
1629                 return;
1630         --m->nr;
1631         m->guest[i] = m->guest[m->nr];
1632         m->host[i] = m->host[m->nr];
1633         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635 }
1636
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638                 unsigned long entry, unsigned long exit,
1639                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640                 u64 guest_val, u64 host_val)
1641 {
1642         vmcs_write64(guest_val_vmcs, guest_val);
1643         vmcs_write64(host_val_vmcs, host_val);
1644         vm_entry_controls_setbit(vmx, entry);
1645         vm_exit_controls_setbit(vmx, exit);
1646 }
1647
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649                                   u64 guest_val, u64 host_val)
1650 {
1651         unsigned i;
1652         struct msr_autoload *m = &vmx->msr_autoload;
1653
1654         switch (msr) {
1655         case MSR_EFER:
1656                 if (cpu_has_load_ia32_efer) {
1657                         add_atomic_switch_msr_special(vmx,
1658                                         VM_ENTRY_LOAD_IA32_EFER,
1659                                         VM_EXIT_LOAD_IA32_EFER,
1660                                         GUEST_IA32_EFER,
1661                                         HOST_IA32_EFER,
1662                                         guest_val, host_val);
1663                         return;
1664                 }
1665                 break;
1666         case MSR_CORE_PERF_GLOBAL_CTRL:
1667                 if (cpu_has_load_perf_global_ctrl) {
1668                         add_atomic_switch_msr_special(vmx,
1669                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1672                                         HOST_IA32_PERF_GLOBAL_CTRL,
1673                                         guest_val, host_val);
1674                         return;
1675                 }
1676                 break;
1677         }
1678
1679         for (i = 0; i < m->nr; ++i)
1680                 if (m->guest[i].index == msr)
1681                         break;
1682
1683         if (i == NR_AUTOLOAD_MSRS) {
1684                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685                                 "Can't add msr %x\n", msr);
1686                 return;
1687         } else if (i == m->nr) {
1688                 ++m->nr;
1689                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691         }
1692
1693         m->guest[i].index = msr;
1694         m->guest[i].value = guest_val;
1695         m->host[i].index = msr;
1696         m->host[i].value = host_val;
1697 }
1698
1699 static void reload_tss(void)
1700 {
1701         /*
1702          * VT restores TR but not its size.  Useless.
1703          */
1704         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705         struct desc_struct *descs;
1706
1707         descs = (void *)gdt->address;
1708         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709         load_TR_desc();
1710 }
1711
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1713 {
1714         u64 guest_efer;
1715         u64 ignore_bits;
1716
1717         guest_efer = vmx->vcpu.arch.efer;
1718
1719         /*
1720          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1721          * outside long mode
1722          */
1723         ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725         ignore_bits |= EFER_LMA | EFER_LME;
1726         /* SCE is meaningful only in long mode on Intel */
1727         if (guest_efer & EFER_LMA)
1728                 ignore_bits &= ~(u64)EFER_SCE;
1729 #endif
1730         guest_efer &= ~ignore_bits;
1731         guest_efer |= host_efer & ignore_bits;
1732         vmx->guest_msrs[efer_offset].data = guest_efer;
1733         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734
1735         clear_atomic_switch_msr(vmx, MSR_EFER);
1736
1737         /*
1738          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739          * On CPUs that support "load IA32_EFER", always switch EFER
1740          * atomically, since it's faster than switching it manually.
1741          */
1742         if (cpu_has_load_ia32_efer ||
1743             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744                 guest_efer = vmx->vcpu.arch.efer;
1745                 if (!(guest_efer & EFER_LMA))
1746                         guest_efer &= ~EFER_LME;
1747                 if (guest_efer != host_efer)
1748                         add_atomic_switch_msr(vmx, MSR_EFER,
1749                                               guest_efer, host_efer);
1750                 return false;
1751         }
1752
1753         return true;
1754 }
1755
1756 static unsigned long segment_base(u16 selector)
1757 {
1758         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759         struct desc_struct *d;
1760         unsigned long table_base;
1761         unsigned long v;
1762
1763         if (!(selector & ~3))
1764                 return 0;
1765
1766         table_base = gdt->address;
1767
1768         if (selector & 4) {           /* from ldt */
1769                 u16 ldt_selector = kvm_read_ldt();
1770
1771                 if (!(ldt_selector & ~3))
1772                         return 0;
1773
1774                 table_base = segment_base(ldt_selector);
1775         }
1776         d = (struct desc_struct *)(table_base + (selector & ~7));
1777         v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781 #endif
1782         return v;
1783 }
1784
1785 static inline unsigned long kvm_read_tr_base(void)
1786 {
1787         u16 tr;
1788         asm("str %0" : "=g"(tr));
1789         return segment_base(tr);
1790 }
1791
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         int i;
1796
1797         if (vmx->host_state.loaded)
1798                 return;
1799
1800         vmx->host_state.loaded = 1;
1801         /*
1802          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1803          * allow segment selectors with cpl > 0 or ti == 1.
1804          */
1805         vmx->host_state.ldt_sel = kvm_read_ldt();
1806         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807         savesegment(fs, vmx->host_state.fs_sel);
1808         if (!(vmx->host_state.fs_sel & 7)) {
1809                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810                 vmx->host_state.fs_reload_needed = 0;
1811         } else {
1812                 vmcs_write16(HOST_FS_SELECTOR, 0);
1813                 vmx->host_state.fs_reload_needed = 1;
1814         }
1815         savesegment(gs, vmx->host_state.gs_sel);
1816         if (!(vmx->host_state.gs_sel & 7))
1817                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818         else {
1819                 vmcs_write16(HOST_GS_SELECTOR, 0);
1820                 vmx->host_state.gs_ldt_reload_needed = 1;
1821         }
1822
1823 #ifdef CONFIG_X86_64
1824         savesegment(ds, vmx->host_state.ds_sel);
1825         savesegment(es, vmx->host_state.es_sel);
1826 #endif
1827
1828 #ifdef CONFIG_X86_64
1829         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 #else
1832         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1834 #endif
1835
1836 #ifdef CONFIG_X86_64
1837         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838         if (is_long_mode(&vmx->vcpu))
1839                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 #endif
1841         if (boot_cpu_has(X86_FEATURE_MPX))
1842                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843         for (i = 0; i < vmx->save_nmsrs; ++i)
1844                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845                                    vmx->guest_msrs[i].data,
1846                                    vmx->guest_msrs[i].mask);
1847 }
1848
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 {
1851         if (!vmx->host_state.loaded)
1852                 return;
1853
1854         ++vmx->vcpu.stat.host_state_reload;
1855         vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857         if (is_long_mode(&vmx->vcpu))
1858                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 #endif
1860         if (vmx->host_state.gs_ldt_reload_needed) {
1861                 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863                 load_gs_index(vmx->host_state.gs_sel);
1864 #else
1865                 loadsegment(gs, vmx->host_state.gs_sel);
1866 #endif
1867         }
1868         if (vmx->host_state.fs_reload_needed)
1869                 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872                 loadsegment(ds, vmx->host_state.ds_sel);
1873                 loadsegment(es, vmx->host_state.es_sel);
1874         }
1875 #endif
1876         reload_tss();
1877 #ifdef CONFIG_X86_64
1878         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 #endif
1880         if (vmx->host_state.msr_host_bndcfgs)
1881                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882         /*
1883          * If the FPU is not active (through the host task or
1884          * the guest vcpu), then restore the cr0.TS bit.
1885          */
1886         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887                 stts();
1888         load_gdt(this_cpu_ptr(&host_gdt));
1889 }
1890
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892 {
1893         preempt_disable();
1894         __vmx_load_host_state(vmx);
1895         preempt_enable();
1896 }
1897
1898 /*
1899  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900  * vcpu mutex is already taken.
1901  */
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 {
1904         struct vcpu_vmx *vmx = to_vmx(vcpu);
1905         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1906
1907         if (!vmm_exclusive)
1908                 kvm_cpu_vmxon(phys_addr);
1909         else if (vmx->loaded_vmcs->cpu != cpu)
1910                 loaded_vmcs_clear(vmx->loaded_vmcs);
1911
1912         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914                 vmcs_load(vmx->loaded_vmcs->vmcs);
1915         }
1916
1917         if (vmx->loaded_vmcs->cpu != cpu) {
1918                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919                 unsigned long sysenter_esp;
1920
1921                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922                 local_irq_disable();
1923                 crash_disable_local_vmclear(cpu);
1924
1925                 /*
1926                  * Read loaded_vmcs->cpu should be before fetching
1927                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928                  * See the comments in __loaded_vmcs_clear().
1929                  */
1930                 smp_rmb();
1931
1932                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1934                 crash_enable_local_vmclear(cpu);
1935                 local_irq_enable();
1936
1937                 /*
1938                  * Linux uses per-cpu TSS and GDT, so set these when switching
1939                  * processors.
1940                  */
1941                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1943
1944                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946                 vmx->loaded_vmcs->cpu = cpu;
1947         }
1948 }
1949
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 {
1952         __vmx_load_host_state(to_vmx(vcpu));
1953         if (!vmm_exclusive) {
1954                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955                 vcpu->cpu = -1;
1956                 kvm_cpu_vmxoff();
1957         }
1958 }
1959
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961 {
1962         ulong cr0;
1963
1964         if (vcpu->fpu_active)
1965                 return;
1966         vcpu->fpu_active = 1;
1967         cr0 = vmcs_readl(GUEST_CR0);
1968         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970         vmcs_writel(GUEST_CR0, cr0);
1971         update_exception_bitmap(vcpu);
1972         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973         if (is_guest_mode(vcpu))
1974                 vcpu->arch.cr0_guest_owned_bits &=
1975                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1977 }
1978
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
1981 /*
1982  * Return the cr0 value that a nested guest would read. This is a combination
1983  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984  * its hypervisor (cr0_read_shadow).
1985  */
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 {
1988         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 }
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 {
1993         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995 }
1996
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 {
1999         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000          * set this *before* calling this function.
2001          */
2002         vmx_decache_cr0_guest_bits(vcpu);
2003         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004         update_exception_bitmap(vcpu);
2005         vcpu->arch.cr0_guest_owned_bits = 0;
2006         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007         if (is_guest_mode(vcpu)) {
2008                 /*
2009                  * L1's specified read shadow might not contain the TS bit,
2010                  * so now that we turned on shadowing of this bit, we need to
2011                  * set this bit of the shadow. Like in nested_vmx_run we need
2012                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013                  * up-to-date here because we just decached cr0.TS (and we'll
2014                  * only update vmcs12->guest_cr0 on nested exit).
2015                  */
2016                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018                         (vcpu->arch.cr0 & X86_CR0_TS);
2019                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020         } else
2021                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2022 }
2023
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 {
2026         unsigned long rflags, save_rflags;
2027
2028         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030                 rflags = vmcs_readl(GUEST_RFLAGS);
2031                 if (to_vmx(vcpu)->rmode.vm86_active) {
2032                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035                 }
2036                 to_vmx(vcpu)->rflags = rflags;
2037         }
2038         return to_vmx(vcpu)->rflags;
2039 }
2040
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 {
2043         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044         to_vmx(vcpu)->rflags = rflags;
2045         if (to_vmx(vcpu)->rmode.vm86_active) {
2046                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048         }
2049         vmcs_writel(GUEST_RFLAGS, rflags);
2050 }
2051
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 {
2054         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055         int ret = 0;
2056
2057         if (interruptibility & GUEST_INTR_STATE_STI)
2058                 ret |= KVM_X86_SHADOW_INT_STI;
2059         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2061
2062         return ret;
2063 }
2064
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 {
2067         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068         u32 interruptibility = interruptibility_old;
2069
2070         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
2072         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074         else if (mask & KVM_X86_SHADOW_INT_STI)
2075                 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077         if ((interruptibility != interruptibility_old))
2078                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079 }
2080
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long rip;
2084
2085         rip = kvm_rip_read(vcpu);
2086         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087         kvm_rip_write(vcpu, rip);
2088
2089         /* skipping an emulated instruction also counts */
2090         vmx_set_interrupt_shadow(vcpu, 0);
2091 }
2092
2093 /*
2094  * KVM wants to inject page-faults which it got to the guest. This function
2095  * checks whether in a nested guest, we need to inject them to L1 or L2.
2096  */
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 {
2099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
2101         if (!(vmcs12->exception_bitmap & (1u << nr)))
2102                 return 0;
2103
2104         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105                           vmcs_read32(VM_EXIT_INTR_INFO),
2106                           vmcs_readl(EXIT_QUALIFICATION));
2107         return 1;
2108 }
2109
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111                                 bool has_error_code, u32 error_code,
2112                                 bool reinject)
2113 {
2114         struct vcpu_vmx *vmx = to_vmx(vcpu);
2115         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116
2117         if (!reinject && is_guest_mode(vcpu) &&
2118             nested_vmx_check_exception(vcpu, nr))
2119                 return;
2120
2121         if (has_error_code) {
2122                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124         }
2125
2126         if (vmx->rmode.vm86_active) {
2127                 int inc_eip = 0;
2128                 if (kvm_exception_is_soft(nr))
2129                         inc_eip = vcpu->arch.event_exit_inst_len;
2130                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2132                 return;
2133         }
2134
2135         if (kvm_exception_is_soft(nr)) {
2136                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137                              vmx->vcpu.arch.event_exit_inst_len);
2138                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139         } else
2140                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2143 }
2144
2145 static bool vmx_rdtscp_supported(void)
2146 {
2147         return cpu_has_vmx_rdtscp();
2148 }
2149
2150 static bool vmx_invpcid_supported(void)
2151 {
2152         return cpu_has_vmx_invpcid() && enable_ept;
2153 }
2154
2155 /*
2156  * Swap MSR entry in host/guest MSR entry array.
2157  */
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 {
2160         struct shared_msr_entry tmp;
2161
2162         tmp = vmx->guest_msrs[to];
2163         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164         vmx->guest_msrs[from] = tmp;
2165 }
2166
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 {
2169         unsigned long *msr_bitmap;
2170
2171         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2172                 if (is_long_mode(vcpu))
2173                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2174                 else
2175                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2176         } else {
2177                 if (is_long_mode(vcpu))
2178                         msr_bitmap = vmx_msr_bitmap_longmode;
2179                 else
2180                         msr_bitmap = vmx_msr_bitmap_legacy;
2181         }
2182
2183         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2184 }
2185
2186 /*
2187  * Set up the vmcs to automatically save and restore system
2188  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2189  * mode, as fiddling with msrs is very expensive.
2190  */
2191 static void setup_msrs(struct vcpu_vmx *vmx)
2192 {
2193         int save_nmsrs, index;
2194
2195         save_nmsrs = 0;
2196 #ifdef CONFIG_X86_64
2197         if (is_long_mode(&vmx->vcpu)) {
2198                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2199                 if (index >= 0)
2200                         move_msr_up(vmx, index, save_nmsrs++);
2201                 index = __find_msr_index(vmx, MSR_LSTAR);
2202                 if (index >= 0)
2203                         move_msr_up(vmx, index, save_nmsrs++);
2204                 index = __find_msr_index(vmx, MSR_CSTAR);
2205                 if (index >= 0)
2206                         move_msr_up(vmx, index, save_nmsrs++);
2207                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2208                 if (index >= 0 && vmx->rdtscp_enabled)
2209                         move_msr_up(vmx, index, save_nmsrs++);
2210                 /*
2211                  * MSR_STAR is only needed on long mode guests, and only
2212                  * if efer.sce is enabled.
2213                  */
2214                 index = __find_msr_index(vmx, MSR_STAR);
2215                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2216                         move_msr_up(vmx, index, save_nmsrs++);
2217         }
2218 #endif
2219         index = __find_msr_index(vmx, MSR_EFER);
2220         if (index >= 0 && update_transition_efer(vmx, index))
2221                 move_msr_up(vmx, index, save_nmsrs++);
2222
2223         vmx->save_nmsrs = save_nmsrs;
2224
2225         if (cpu_has_vmx_msr_bitmap())
2226                 vmx_set_msr_bitmap(&vmx->vcpu);
2227 }
2228
2229 /*
2230  * reads and returns guest's timestamp counter "register"
2231  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2232  */
2233 static u64 guest_read_tsc(void)
2234 {
2235         u64 host_tsc, tsc_offset;
2236
2237         rdtscll(host_tsc);
2238         tsc_offset = vmcs_read64(TSC_OFFSET);
2239         return host_tsc + tsc_offset;
2240 }
2241
2242 /*
2243  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2244  * counter, even if a nested guest (L2) is currently running.
2245  */
2246 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2247 {
2248         u64 tsc_offset;
2249
2250         tsc_offset = is_guest_mode(vcpu) ?
2251                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2252                 vmcs_read64(TSC_OFFSET);
2253         return host_tsc + tsc_offset;
2254 }
2255
2256 /*
2257  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2258  * software catchup for faster rates on slower CPUs.
2259  */
2260 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2261 {
2262         if (!scale)
2263                 return;
2264
2265         if (user_tsc_khz > tsc_khz) {
2266                 vcpu->arch.tsc_catchup = 1;
2267                 vcpu->arch.tsc_always_catchup = 1;
2268         } else
2269                 WARN(1, "user requested TSC rate below hardware speed\n");
2270 }
2271
2272 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2273 {
2274         return vmcs_read64(TSC_OFFSET);
2275 }
2276
2277 /*
2278  * writes 'offset' into guest's timestamp counter offset register
2279  */
2280 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2281 {
2282         if (is_guest_mode(vcpu)) {
2283                 /*
2284                  * We're here if L1 chose not to trap WRMSR to TSC. According
2285                  * to the spec, this should set L1's TSC; The offset that L1
2286                  * set for L2 remains unchanged, and still needs to be added
2287                  * to the newly set TSC to get L2's TSC.
2288                  */
2289                 struct vmcs12 *vmcs12;
2290                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2291                 /* recalculate vmcs02.TSC_OFFSET: */
2292                 vmcs12 = get_vmcs12(vcpu);
2293                 vmcs_write64(TSC_OFFSET, offset +
2294                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2295                          vmcs12->tsc_offset : 0));
2296         } else {
2297                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2298                                            vmcs_read64(TSC_OFFSET), offset);
2299                 vmcs_write64(TSC_OFFSET, offset);
2300         }
2301 }
2302
2303 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2304 {
2305         u64 offset = vmcs_read64(TSC_OFFSET);
2306
2307         vmcs_write64(TSC_OFFSET, offset + adjustment);
2308         if (is_guest_mode(vcpu)) {
2309                 /* Even when running L2, the adjustment needs to apply to L1 */
2310                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2311         } else
2312                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2313                                            offset + adjustment);
2314 }
2315
2316 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2317 {
2318         return target_tsc - native_read_tsc();
2319 }
2320
2321 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2322 {
2323         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2324         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2325 }
2326
2327 /*
2328  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2329  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2330  * all guests if the "nested" module option is off, and can also be disabled
2331  * for a single guest by disabling its VMX cpuid bit.
2332  */
2333 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2334 {
2335         return nested && guest_cpuid_has_vmx(vcpu);
2336 }
2337
2338 /*
2339  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2340  * returned for the various VMX controls MSRs when nested VMX is enabled.
2341  * The same values should also be used to verify that vmcs12 control fields are
2342  * valid during nested entry from L1 to L2.
2343  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2344  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2345  * bit in the high half is on if the corresponding bit in the control field
2346  * may be on. See also vmx_control_verify().
2347  */
2348 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2349 {
2350         /*
2351          * Note that as a general rule, the high half of the MSRs (bits in
2352          * the control fields which may be 1) should be initialized by the
2353          * intersection of the underlying hardware's MSR (i.e., features which
2354          * can be supported) and the list of features we want to expose -
2355          * because they are known to be properly supported in our code.
2356          * Also, usually, the low half of the MSRs (bits which must be 1) can
2357          * be set to 0, meaning that L1 may turn off any of these bits. The
2358          * reason is that if one of these bits is necessary, it will appear
2359          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2360          * fields of vmcs01 and vmcs02, will turn these bits off - and
2361          * nested_vmx_exit_handled() will not pass related exits to L1.
2362          * These rules have exceptions below.
2363          */
2364
2365         /* pin-based controls */
2366         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2367                 vmx->nested.nested_vmx_pinbased_ctls_low,
2368                 vmx->nested.nested_vmx_pinbased_ctls_high);
2369         vmx->nested.nested_vmx_pinbased_ctls_low |=
2370                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2371         vmx->nested.nested_vmx_pinbased_ctls_high &=
2372                 PIN_BASED_EXT_INTR_MASK |
2373                 PIN_BASED_NMI_EXITING |
2374                 PIN_BASED_VIRTUAL_NMIS;
2375         vmx->nested.nested_vmx_pinbased_ctls_high |=
2376                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2377                 PIN_BASED_VMX_PREEMPTION_TIMER;
2378         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2379                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2380                         PIN_BASED_POSTED_INTR;
2381
2382         /* exit controls */
2383         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2384                 vmx->nested.nested_vmx_exit_ctls_low,
2385                 vmx->nested.nested_vmx_exit_ctls_high);
2386         vmx->nested.nested_vmx_exit_ctls_low =
2387                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2388
2389         vmx->nested.nested_vmx_exit_ctls_high &=
2390 #ifdef CONFIG_X86_64
2391                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2392 #endif
2393                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2394         vmx->nested.nested_vmx_exit_ctls_high |=
2395                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2396                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2397                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2398
2399         if (vmx_mpx_supported())
2400                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2401
2402         /* We support free control of debug control saving. */
2403         vmx->nested.nested_vmx_true_exit_ctls_low =
2404                 vmx->nested.nested_vmx_exit_ctls_low &
2405                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2406
2407         /* entry controls */
2408         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2409                 vmx->nested.nested_vmx_entry_ctls_low,
2410                 vmx->nested.nested_vmx_entry_ctls_high);
2411         vmx->nested.nested_vmx_entry_ctls_low =
2412                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2413         vmx->nested.nested_vmx_entry_ctls_high &=
2414 #ifdef CONFIG_X86_64
2415                 VM_ENTRY_IA32E_MODE |
2416 #endif
2417                 VM_ENTRY_LOAD_IA32_PAT;
2418         vmx->nested.nested_vmx_entry_ctls_high |=
2419                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2420         if (vmx_mpx_supported())
2421                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2422
2423         /* We support free control of debug control loading. */
2424         vmx->nested.nested_vmx_true_entry_ctls_low =
2425                 vmx->nested.nested_vmx_entry_ctls_low &
2426                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2427
2428         /* cpu-based controls */
2429         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2430                 vmx->nested.nested_vmx_procbased_ctls_low,
2431                 vmx->nested.nested_vmx_procbased_ctls_high);
2432         vmx->nested.nested_vmx_procbased_ctls_low =
2433                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2434         vmx->nested.nested_vmx_procbased_ctls_high &=
2435                 CPU_BASED_VIRTUAL_INTR_PENDING |
2436                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2437                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2438                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2439                 CPU_BASED_CR3_STORE_EXITING |
2440 #ifdef CONFIG_X86_64
2441                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2442 #endif
2443                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2444                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2445                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2446                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2447                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2448         /*
2449          * We can allow some features even when not supported by the
2450          * hardware. For example, L1 can specify an MSR bitmap - and we
2451          * can use it to avoid exits to L1 - even when L0 runs L2
2452          * without MSR bitmaps.
2453          */
2454         vmx->nested.nested_vmx_procbased_ctls_high |=
2455                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2456                 CPU_BASED_USE_MSR_BITMAPS;
2457
2458         /* We support free control of CR3 access interception. */
2459         vmx->nested.nested_vmx_true_procbased_ctls_low =
2460                 vmx->nested.nested_vmx_procbased_ctls_low &
2461                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2462
2463         /* secondary cpu-based controls */
2464         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2465                 vmx->nested.nested_vmx_secondary_ctls_low,
2466                 vmx->nested.nested_vmx_secondary_ctls_high);
2467         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2468         vmx->nested.nested_vmx_secondary_ctls_high &=
2469                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2470                 SECONDARY_EXEC_RDTSCP |
2471                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2472                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2473                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2474                 SECONDARY_EXEC_WBINVD_EXITING |
2475                 SECONDARY_EXEC_XSAVES;
2476
2477         if (enable_ept) {
2478                 /* nested EPT: emulate EPT also to L1 */
2479                 vmx->nested.nested_vmx_secondary_ctls_high |=
2480                         SECONDARY_EXEC_ENABLE_EPT |
2481                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2482                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2483                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2484                          VMX_EPT_INVEPT_BIT;
2485                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2486                 /*
2487                  * For nested guests, we don't do anything specific
2488                  * for single context invalidation. Hence, only advertise
2489                  * support for global context invalidation.
2490                  */
2491                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2492         } else
2493                 vmx->nested.nested_vmx_ept_caps = 0;
2494
2495         /* miscellaneous data */
2496         rdmsr(MSR_IA32_VMX_MISC,
2497                 vmx->nested.nested_vmx_misc_low,
2498                 vmx->nested.nested_vmx_misc_high);
2499         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2500         vmx->nested.nested_vmx_misc_low |=
2501                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2502                 VMX_MISC_ACTIVITY_HLT;
2503         vmx->nested.nested_vmx_misc_high = 0;
2504 }
2505
2506 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2507 {
2508         /*
2509          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2510          */
2511         return ((control & high) | low) == control;
2512 }
2513
2514 static inline u64 vmx_control_msr(u32 low, u32 high)
2515 {
2516         return low | ((u64)high << 32);
2517 }
2518
2519 /* Returns 0 on success, non-0 otherwise. */
2520 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2521 {
2522         struct vcpu_vmx *vmx = to_vmx(vcpu);
2523
2524         switch (msr_index) {
2525         case MSR_IA32_VMX_BASIC:
2526                 /*
2527                  * This MSR reports some information about VMX support. We
2528                  * should return information about the VMX we emulate for the
2529                  * guest, and the VMCS structure we give it - not about the
2530                  * VMX support of the underlying hardware.
2531                  */
2532                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2533                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2534                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2535                 break;
2536         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2537         case MSR_IA32_VMX_PINBASED_CTLS:
2538                 *pdata = vmx_control_msr(
2539                         vmx->nested.nested_vmx_pinbased_ctls_low,
2540                         vmx->nested.nested_vmx_pinbased_ctls_high);
2541                 break;
2542         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2543                 *pdata = vmx_control_msr(
2544                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2545                         vmx->nested.nested_vmx_procbased_ctls_high);
2546                 break;
2547         case MSR_IA32_VMX_PROCBASED_CTLS:
2548                 *pdata = vmx_control_msr(
2549                         vmx->nested.nested_vmx_procbased_ctls_low,
2550                         vmx->nested.nested_vmx_procbased_ctls_high);
2551                 break;
2552         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2553                 *pdata = vmx_control_msr(
2554                         vmx->nested.nested_vmx_true_exit_ctls_low,
2555                         vmx->nested.nested_vmx_exit_ctls_high);
2556                 break;
2557         case MSR_IA32_VMX_EXIT_CTLS:
2558                 *pdata = vmx_control_msr(
2559                         vmx->nested.nested_vmx_exit_ctls_low,
2560                         vmx->nested.nested_vmx_exit_ctls_high);
2561                 break;
2562         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2563                 *pdata = vmx_control_msr(
2564                         vmx->nested.nested_vmx_true_entry_ctls_low,
2565                         vmx->nested.nested_vmx_entry_ctls_high);
2566                 break;
2567         case MSR_IA32_VMX_ENTRY_CTLS:
2568                 *pdata = vmx_control_msr(
2569                         vmx->nested.nested_vmx_entry_ctls_low,
2570                         vmx->nested.nested_vmx_entry_ctls_high);
2571                 break;
2572         case MSR_IA32_VMX_MISC:
2573                 *pdata = vmx_control_msr(
2574                         vmx->nested.nested_vmx_misc_low,
2575                         vmx->nested.nested_vmx_misc_high);
2576                 break;
2577         /*
2578          * These MSRs specify bits which the guest must keep fixed (on or off)
2579          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2580          * We picked the standard core2 setting.
2581          */
2582 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2583 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2584         case MSR_IA32_VMX_CR0_FIXED0:
2585                 *pdata = VMXON_CR0_ALWAYSON;
2586                 break;
2587         case MSR_IA32_VMX_CR0_FIXED1:
2588                 *pdata = -1ULL;
2589                 break;
2590         case MSR_IA32_VMX_CR4_FIXED0:
2591                 *pdata = VMXON_CR4_ALWAYSON;
2592                 break;
2593         case MSR_IA32_VMX_CR4_FIXED1:
2594                 *pdata = -1ULL;
2595                 break;
2596         case MSR_IA32_VMX_VMCS_ENUM:
2597                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2598                 break;
2599         case MSR_IA32_VMX_PROCBASED_CTLS2:
2600                 *pdata = vmx_control_msr(
2601                         vmx->nested.nested_vmx_secondary_ctls_low,
2602                         vmx->nested.nested_vmx_secondary_ctls_high);
2603                 break;
2604         case MSR_IA32_VMX_EPT_VPID_CAP:
2605                 /* Currently, no nested vpid support */
2606                 *pdata = vmx->nested.nested_vmx_ept_caps;
2607                 break;
2608         default:
2609                 return 1;
2610         }
2611
2612         return 0;
2613 }
2614
2615 /*
2616  * Reads an msr value (of 'msr_index') into 'pdata'.
2617  * Returns 0 on success, non-0 otherwise.
2618  * Assumes vcpu_load() was already called.
2619  */
2620 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2621 {
2622         u64 data;
2623         struct shared_msr_entry *msr;
2624
2625         if (!pdata) {
2626                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2627                 return -EINVAL;
2628         }
2629
2630         switch (msr_index) {
2631 #ifdef CONFIG_X86_64
2632         case MSR_FS_BASE:
2633                 data = vmcs_readl(GUEST_FS_BASE);
2634                 break;
2635         case MSR_GS_BASE:
2636                 data = vmcs_readl(GUEST_GS_BASE);
2637                 break;
2638         case MSR_KERNEL_GS_BASE:
2639                 vmx_load_host_state(to_vmx(vcpu));
2640                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2641                 break;
2642 #endif
2643         case MSR_EFER:
2644                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2645         case MSR_IA32_TSC:
2646                 data = guest_read_tsc();
2647                 break;
2648         case MSR_IA32_SYSENTER_CS:
2649                 data = vmcs_read32(GUEST_SYSENTER_CS);
2650                 break;
2651         case MSR_IA32_SYSENTER_EIP:
2652                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2653                 break;
2654         case MSR_IA32_SYSENTER_ESP:
2655                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2656                 break;
2657         case MSR_IA32_BNDCFGS:
2658                 if (!vmx_mpx_supported())
2659                         return 1;
2660                 data = vmcs_read64(GUEST_BNDCFGS);
2661                 break;
2662         case MSR_IA32_FEATURE_CONTROL:
2663                 if (!nested_vmx_allowed(vcpu))
2664                         return 1;
2665                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2666                 break;
2667         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2668                 if (!nested_vmx_allowed(vcpu))
2669                         return 1;
2670                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2671         case MSR_IA32_XSS:
2672                 if (!vmx_xsaves_supported())
2673                         return 1;
2674                 data = vcpu->arch.ia32_xss;
2675                 break;
2676         case MSR_TSC_AUX:
2677                 if (!to_vmx(vcpu)->rdtscp_enabled)
2678                         return 1;
2679                 /* Otherwise falls through */
2680         default:
2681                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2682                 if (msr) {
2683                         data = msr->data;
2684                         break;
2685                 }
2686                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2687         }
2688
2689         *pdata = data;
2690         return 0;
2691 }
2692
2693 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2694
2695 /*
2696  * Writes msr value into into the appropriate "register".
2697  * Returns 0 on success, non-0 otherwise.
2698  * Assumes vcpu_load() was already called.
2699  */
2700 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2701 {
2702         struct vcpu_vmx *vmx = to_vmx(vcpu);
2703         struct shared_msr_entry *msr;
2704         int ret = 0;
2705         u32 msr_index = msr_info->index;
2706         u64 data = msr_info->data;
2707
2708         switch (msr_index) {
2709         case MSR_EFER:
2710                 ret = kvm_set_msr_common(vcpu, msr_info);
2711                 break;
2712 #ifdef CONFIG_X86_64
2713         case MSR_FS_BASE:
2714                 vmx_segment_cache_clear(vmx);
2715                 vmcs_writel(GUEST_FS_BASE, data);
2716                 break;
2717         case MSR_GS_BASE:
2718                 vmx_segment_cache_clear(vmx);
2719                 vmcs_writel(GUEST_GS_BASE, data);
2720                 break;
2721         case MSR_KERNEL_GS_BASE:
2722                 vmx_load_host_state(vmx);
2723                 vmx->msr_guest_kernel_gs_base = data;
2724                 break;
2725 #endif
2726         case MSR_IA32_SYSENTER_CS:
2727                 vmcs_write32(GUEST_SYSENTER_CS, data);
2728                 break;
2729         case MSR_IA32_SYSENTER_EIP:
2730                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2731                 break;
2732         case MSR_IA32_SYSENTER_ESP:
2733                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2734                 break;
2735         case MSR_IA32_BNDCFGS:
2736                 if (!vmx_mpx_supported())
2737                         return 1;
2738                 vmcs_write64(GUEST_BNDCFGS, data);
2739                 break;
2740         case MSR_IA32_TSC:
2741                 kvm_write_tsc(vcpu, msr_info);
2742                 break;
2743         case MSR_IA32_CR_PAT:
2744                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2745                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2746                                 return 1;
2747                         vmcs_write64(GUEST_IA32_PAT, data);
2748                         vcpu->arch.pat = data;
2749                         break;
2750                 }
2751                 ret = kvm_set_msr_common(vcpu, msr_info);
2752                 break;
2753         case MSR_IA32_TSC_ADJUST:
2754                 ret = kvm_set_msr_common(vcpu, msr_info);
2755                 break;
2756         case MSR_IA32_FEATURE_CONTROL:
2757                 if (!nested_vmx_allowed(vcpu) ||
2758                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2759                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2760                         return 1;
2761                 vmx->nested.msr_ia32_feature_control = data;
2762                 if (msr_info->host_initiated && data == 0)
2763                         vmx_leave_nested(vcpu);
2764                 break;
2765         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2766                 return 1; /* they are read-only */
2767         case MSR_IA32_XSS:
2768                 if (!vmx_xsaves_supported())
2769                         return 1;
2770                 /*
2771                  * The only supported bit as of Skylake is bit 8, but
2772                  * it is not supported on KVM.
2773                  */
2774                 if (data != 0)
2775                         return 1;
2776                 vcpu->arch.ia32_xss = data;
2777                 if (vcpu->arch.ia32_xss != host_xss)
2778                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2779                                 vcpu->arch.ia32_xss, host_xss);
2780                 else
2781                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2782                 break;
2783         case MSR_TSC_AUX:
2784                 if (!vmx->rdtscp_enabled)
2785                         return 1;
2786                 /* Check reserved bit, higher 32 bits should be zero */
2787                 if ((data >> 32) != 0)
2788                         return 1;
2789                 /* Otherwise falls through */
2790         default:
2791                 msr = find_msr_entry(vmx, msr_index);
2792                 if (msr) {
2793                         u64 old_msr_data = msr->data;
2794                         msr->data = data;
2795                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2796                                 preempt_disable();
2797                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2798                                                          msr->mask);
2799                                 preempt_enable();
2800                                 if (ret)
2801                                         msr->data = old_msr_data;
2802                         }
2803                         break;
2804                 }
2805                 ret = kvm_set_msr_common(vcpu, msr_info);
2806         }
2807
2808         return ret;
2809 }
2810
2811 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2812 {
2813         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2814         switch (reg) {
2815         case VCPU_REGS_RSP:
2816                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2817                 break;
2818         case VCPU_REGS_RIP:
2819                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2820                 break;
2821         case VCPU_EXREG_PDPTR:
2822                 if (enable_ept)
2823                         ept_save_pdptrs(vcpu);
2824                 break;
2825         default:
2826                 break;
2827         }
2828 }
2829
2830 static __init int cpu_has_kvm_support(void)
2831 {
2832         return cpu_has_vmx();
2833 }
2834
2835 static __init int vmx_disabled_by_bios(void)
2836 {
2837         u64 msr;
2838
2839         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2840         if (msr & FEATURE_CONTROL_LOCKED) {
2841                 /* launched w/ TXT and VMX disabled */
2842                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2843                         && tboot_enabled())
2844                         return 1;
2845                 /* launched w/o TXT and VMX only enabled w/ TXT */
2846                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2847                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2848                         && !tboot_enabled()) {
2849                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2850                                 "activate TXT before enabling KVM\n");
2851                         return 1;
2852                 }
2853                 /* launched w/o TXT and VMX disabled */
2854                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2855                         && !tboot_enabled())
2856                         return 1;
2857         }
2858
2859         return 0;
2860 }
2861
2862 static void kvm_cpu_vmxon(u64 addr)
2863 {
2864         asm volatile (ASM_VMX_VMXON_RAX
2865                         : : "a"(&addr), "m"(addr)
2866                         : "memory", "cc");
2867 }
2868
2869 static int hardware_enable(void)
2870 {
2871         int cpu = raw_smp_processor_id();
2872         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2873         u64 old, test_bits;
2874
2875         if (cr4_read_shadow() & X86_CR4_VMXE)
2876                 return -EBUSY;
2877
2878         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2879
2880         /*
2881          * Now we can enable the vmclear operation in kdump
2882          * since the loaded_vmcss_on_cpu list on this cpu
2883          * has been initialized.
2884          *
2885          * Though the cpu is not in VMX operation now, there
2886          * is no problem to enable the vmclear operation
2887          * for the loaded_vmcss_on_cpu list is empty!
2888          */
2889         crash_enable_local_vmclear(cpu);
2890
2891         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2892
2893         test_bits = FEATURE_CONTROL_LOCKED;
2894         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2895         if (tboot_enabled())
2896                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2897
2898         if ((old & test_bits) != test_bits) {
2899                 /* enable and lock */
2900                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2901         }
2902         cr4_set_bits(X86_CR4_VMXE);
2903
2904         if (vmm_exclusive) {
2905                 kvm_cpu_vmxon(phys_addr);
2906                 ept_sync_global();
2907         }
2908
2909         native_store_gdt(this_cpu_ptr(&host_gdt));
2910
2911         return 0;
2912 }
2913
2914 static void vmclear_local_loaded_vmcss(void)
2915 {
2916         int cpu = raw_smp_processor_id();
2917         struct loaded_vmcs *v, *n;
2918
2919         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2920                                  loaded_vmcss_on_cpu_link)
2921                 __loaded_vmcs_clear(v);
2922 }
2923
2924
2925 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2926  * tricks.
2927  */
2928 static void kvm_cpu_vmxoff(void)
2929 {
2930         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2931 }
2932
2933 static void hardware_disable(void)
2934 {
2935         if (vmm_exclusive) {
2936                 vmclear_local_loaded_vmcss();
2937                 kvm_cpu_vmxoff();
2938         }
2939         cr4_clear_bits(X86_CR4_VMXE);
2940 }
2941
2942 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2943                                       u32 msr, u32 *result)
2944 {
2945         u32 vmx_msr_low, vmx_msr_high;
2946         u32 ctl = ctl_min | ctl_opt;
2947
2948         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2949
2950         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2951         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2952
2953         /* Ensure minimum (required) set of control bits are supported. */
2954         if (ctl_min & ~ctl)
2955                 return -EIO;
2956
2957         *result = ctl;
2958         return 0;
2959 }
2960
2961 static __init bool allow_1_setting(u32 msr, u32 ctl)
2962 {
2963         u32 vmx_msr_low, vmx_msr_high;
2964
2965         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2966         return vmx_msr_high & ctl;
2967 }
2968
2969 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2970 {
2971         u32 vmx_msr_low, vmx_msr_high;
2972         u32 min, opt, min2, opt2;
2973         u32 _pin_based_exec_control = 0;
2974         u32 _cpu_based_exec_control = 0;
2975         u32 _cpu_based_2nd_exec_control = 0;
2976         u32 _vmexit_control = 0;
2977         u32 _vmentry_control = 0;
2978
2979         min = CPU_BASED_HLT_EXITING |
2980 #ifdef CONFIG_X86_64
2981               CPU_BASED_CR8_LOAD_EXITING |
2982               CPU_BASED_CR8_STORE_EXITING |
2983 #endif
2984               CPU_BASED_CR3_LOAD_EXITING |
2985               CPU_BASED_CR3_STORE_EXITING |
2986               CPU_BASED_USE_IO_BITMAPS |
2987               CPU_BASED_MOV_DR_EXITING |
2988               CPU_BASED_USE_TSC_OFFSETING |
2989               CPU_BASED_MWAIT_EXITING |
2990               CPU_BASED_MONITOR_EXITING |
2991               CPU_BASED_INVLPG_EXITING |
2992               CPU_BASED_RDPMC_EXITING;
2993
2994         opt = CPU_BASED_TPR_SHADOW |
2995               CPU_BASED_USE_MSR_BITMAPS |
2996               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2997         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2998                                 &_cpu_based_exec_control) < 0)
2999                 return -EIO;
3000 #ifdef CONFIG_X86_64
3001         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3002                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3003                                            ~CPU_BASED_CR8_STORE_EXITING;
3004 #endif
3005         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3006                 min2 = 0;
3007                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3008                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3009                         SECONDARY_EXEC_WBINVD_EXITING |
3010                         SECONDARY_EXEC_ENABLE_VPID |
3011                         SECONDARY_EXEC_ENABLE_EPT |
3012                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3013                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3014                         SECONDARY_EXEC_RDTSCP |
3015                         SECONDARY_EXEC_ENABLE_INVPCID |
3016                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3017                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3018                         SECONDARY_EXEC_SHADOW_VMCS |
3019                         SECONDARY_EXEC_XSAVES |
3020                         SECONDARY_EXEC_ENABLE_PML;
3021                 if (adjust_vmx_controls(min2, opt2,
3022                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3023                                         &_cpu_based_2nd_exec_control) < 0)
3024                         return -EIO;
3025         }
3026 #ifndef CONFIG_X86_64
3027         if (!(_cpu_based_2nd_exec_control &
3028                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3029                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3030 #endif
3031
3032         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3033                 _cpu_based_2nd_exec_control &= ~(
3034                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3035                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3036                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3037
3038         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3039                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3040                    enabled */
3041                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3042                                              CPU_BASED_CR3_STORE_EXITING |
3043                                              CPU_BASED_INVLPG_EXITING);
3044                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3045                       vmx_capability.ept, vmx_capability.vpid);
3046         }
3047
3048         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3049 #ifdef CONFIG_X86_64
3050         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3051 #endif
3052         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3053                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3054         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3055                                 &_vmexit_control) < 0)
3056                 return -EIO;
3057
3058         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3059         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3060         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3061                                 &_pin_based_exec_control) < 0)
3062                 return -EIO;
3063
3064         if (!(_cpu_based_2nd_exec_control &
3065                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3066                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3067                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3068
3069         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3070         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3071         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3072                                 &_vmentry_control) < 0)
3073                 return -EIO;
3074
3075         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3076
3077         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3078         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3079                 return -EIO;
3080
3081 #ifdef CONFIG_X86_64
3082         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3083         if (vmx_msr_high & (1u<<16))
3084                 return -EIO;
3085 #endif
3086
3087         /* Require Write-Back (WB) memory type for VMCS accesses. */
3088         if (((vmx_msr_high >> 18) & 15) != 6)
3089                 return -EIO;
3090
3091         vmcs_conf->size = vmx_msr_high & 0x1fff;
3092         vmcs_conf->order = get_order(vmcs_config.size);
3093         vmcs_conf->revision_id = vmx_msr_low;
3094
3095         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3096         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3097         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3098         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3099         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3100
3101         cpu_has_load_ia32_efer =
3102                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3103                                 VM_ENTRY_LOAD_IA32_EFER)
3104                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3105                                    VM_EXIT_LOAD_IA32_EFER);
3106
3107         cpu_has_load_perf_global_ctrl =
3108                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3109                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3110                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3111                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3112
3113         /*
3114          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3115          * but due to arrata below it can't be used. Workaround is to use
3116          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3117          *
3118          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3119          *
3120          * AAK155             (model 26)
3121          * AAP115             (model 30)
3122          * AAT100             (model 37)
3123          * BC86,AAY89,BD102   (model 44)
3124          * BA97               (model 46)
3125          *
3126          */
3127         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3128                 switch (boot_cpu_data.x86_model) {
3129                 case 26:
3130                 case 30:
3131                 case 37:
3132                 case 44:
3133                 case 46:
3134                         cpu_has_load_perf_global_ctrl = false;
3135                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3136                                         "does not work properly. Using workaround\n");
3137                         break;
3138                 default:
3139                         break;
3140                 }
3141         }
3142
3143         if (cpu_has_xsaves)
3144                 rdmsrl(MSR_IA32_XSS, host_xss);
3145
3146         return 0;
3147 }
3148
3149 static struct vmcs *alloc_vmcs_cpu(int cpu)
3150 {
3151         int node = cpu_to_node(cpu);
3152         struct page *pages;
3153         struct vmcs *vmcs;
3154
3155         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3156         if (!pages)
3157                 return NULL;
3158         vmcs = page_address(pages);
3159         memset(vmcs, 0, vmcs_config.size);
3160         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3161         return vmcs;
3162 }
3163
3164 static struct vmcs *alloc_vmcs(void)
3165 {
3166         return alloc_vmcs_cpu(raw_smp_processor_id());
3167 }
3168
3169 static void free_vmcs(struct vmcs *vmcs)
3170 {
3171         free_pages((unsigned long)vmcs, vmcs_config.order);
3172 }
3173
3174 /*
3175  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3176  */
3177 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3178 {
3179         if (!loaded_vmcs->vmcs)
3180                 return;
3181         loaded_vmcs_clear(loaded_vmcs);
3182         free_vmcs(loaded_vmcs->vmcs);
3183         loaded_vmcs->vmcs = NULL;
3184 }
3185
3186 static void free_kvm_area(void)
3187 {
3188         int cpu;
3189
3190         for_each_possible_cpu(cpu) {
3191                 free_vmcs(per_cpu(vmxarea, cpu));
3192                 per_cpu(vmxarea, cpu) = NULL;
3193         }
3194 }
3195
3196 static void init_vmcs_shadow_fields(void)
3197 {
3198         int i, j;
3199
3200         /* No checks for read only fields yet */
3201
3202         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3203                 switch (shadow_read_write_fields[i]) {
3204                 case GUEST_BNDCFGS:
3205                         if (!vmx_mpx_supported())
3206                                 continue;
3207                         break;
3208                 default:
3209                         break;
3210                 }
3211
3212                 if (j < i)
3213                         shadow_read_write_fields[j] =
3214                                 shadow_read_write_fields[i];
3215                 j++;
3216         }
3217         max_shadow_read_write_fields = j;
3218
3219         /* shadowed fields guest access without vmexit */
3220         for (i = 0; i < max_shadow_read_write_fields; i++) {
3221                 clear_bit(shadow_read_write_fields[i],
3222                           vmx_vmwrite_bitmap);
3223                 clear_bit(shadow_read_write_fields[i],
3224                           vmx_vmread_bitmap);
3225         }
3226         for (i = 0; i < max_shadow_read_only_fields; i++)
3227                 clear_bit(shadow_read_only_fields[i],
3228                           vmx_vmread_bitmap);
3229 }
3230
3231 static __init int alloc_kvm_area(void)
3232 {
3233         int cpu;
3234
3235         for_each_possible_cpu(cpu) {
3236                 struct vmcs *vmcs;
3237
3238                 vmcs = alloc_vmcs_cpu(cpu);
3239                 if (!vmcs) {
3240                         free_kvm_area();
3241                         return -ENOMEM;
3242                 }
3243
3244                 per_cpu(vmxarea, cpu) = vmcs;
3245         }
3246         return 0;
3247 }
3248
3249 static bool emulation_required(struct kvm_vcpu *vcpu)
3250 {
3251         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3252 }
3253
3254 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3255                 struct kvm_segment *save)
3256 {
3257         if (!emulate_invalid_guest_state) {
3258                 /*
3259                  * CS and SS RPL should be equal during guest entry according
3260                  * to VMX spec, but in reality it is not always so. Since vcpu
3261                  * is in the middle of the transition from real mode to
3262                  * protected mode it is safe to assume that RPL 0 is a good
3263                  * default value.
3264                  */
3265                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3266                         save->selector &= ~SELECTOR_RPL_MASK;
3267                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3268                 save->s = 1;
3269         }
3270         vmx_set_segment(vcpu, save, seg);
3271 }
3272
3273 static void enter_pmode(struct kvm_vcpu *vcpu)
3274 {
3275         unsigned long flags;
3276         struct vcpu_vmx *vmx = to_vmx(vcpu);
3277
3278         /*
3279          * Update real mode segment cache. It may be not up-to-date if sement
3280          * register was written while vcpu was in a guest mode.
3281          */
3282         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3283         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3284         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3285         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3286         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3287         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3288
3289         vmx->rmode.vm86_active = 0;
3290
3291         vmx_segment_cache_clear(vmx);
3292
3293         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3294
3295         flags = vmcs_readl(GUEST_RFLAGS);
3296         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3297         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3298         vmcs_writel(GUEST_RFLAGS, flags);
3299
3300         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3301                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3302
3303         update_exception_bitmap(vcpu);
3304
3305         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3306         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3307         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3308         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3309         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3310         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3311 }
3312
3313 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3314 {
3315         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3316         struct kvm_segment var = *save;
3317
3318         var.dpl = 0x3;
3319         if (seg == VCPU_SREG_CS)
3320                 var.type = 0x3;
3321
3322         if (!emulate_invalid_guest_state) {
3323                 var.selector = var.base >> 4;
3324                 var.base = var.base & 0xffff0;
3325                 var.limit = 0xffff;
3326                 var.g = 0;
3327                 var.db = 0;
3328                 var.present = 1;
3329                 var.s = 1;
3330                 var.l = 0;
3331                 var.unusable = 0;
3332                 var.type = 0x3;
3333                 var.avl = 0;
3334                 if (save->base & 0xf)
3335                         printk_once(KERN_WARNING "kvm: segment base is not "
3336                                         "paragraph aligned when entering "
3337                                         "protected mode (seg=%d)", seg);
3338         }
3339
3340         vmcs_write16(sf->selector, var.selector);
3341         vmcs_write32(sf->base, var.base);
3342         vmcs_write32(sf->limit, var.limit);
3343         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3344 }
3345
3346 static void enter_rmode(struct kvm_vcpu *vcpu)
3347 {
3348         unsigned long flags;
3349         struct vcpu_vmx *vmx = to_vmx(vcpu);
3350
3351         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3352         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3353         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3354         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3355         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3356         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3357         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3358
3359         vmx->rmode.vm86_active = 1;
3360
3361         /*
3362          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3363          * vcpu. Warn the user that an update is overdue.
3364          */
3365         if (!vcpu->kvm->arch.tss_addr)
3366                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3367                              "called before entering vcpu\n");
3368
3369         vmx_segment_cache_clear(vmx);
3370
3371         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3372         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3373         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3374
3375         flags = vmcs_readl(GUEST_RFLAGS);
3376         vmx->rmode.save_rflags = flags;
3377
3378         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3379
3380         vmcs_writel(GUEST_RFLAGS, flags);
3381         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3382         update_exception_bitmap(vcpu);
3383
3384         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3385         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3386         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3387         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3388         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3389         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3390
3391         kvm_mmu_reset_context(vcpu);
3392 }
3393
3394 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3395 {
3396         struct vcpu_vmx *vmx = to_vmx(vcpu);
3397         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3398
3399         if (!msr)
3400                 return;
3401
3402         /*
3403          * Force kernel_gs_base reloading before EFER changes, as control
3404          * of this msr depends on is_long_mode().
3405          */
3406         vmx_load_host_state(to_vmx(vcpu));
3407         vcpu->arch.efer = efer;
3408         if (efer & EFER_LMA) {
3409                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3410                 msr->data = efer;
3411         } else {
3412                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3413
3414                 msr->data = efer & ~EFER_LME;
3415         }
3416         setup_msrs(vmx);
3417 }
3418
3419 #ifdef CONFIG_X86_64
3420
3421 static void enter_lmode(struct kvm_vcpu *vcpu)
3422 {
3423         u32 guest_tr_ar;
3424
3425         vmx_segment_cache_clear(to_vmx(vcpu));
3426
3427         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3428         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3429                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3430                                      __func__);
3431                 vmcs_write32(GUEST_TR_AR_BYTES,
3432                              (guest_tr_ar & ~AR_TYPE_MASK)
3433                              | AR_TYPE_BUSY_64_TSS);
3434         }
3435         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3436 }
3437
3438 static void exit_lmode(struct kvm_vcpu *vcpu)
3439 {
3440         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3441         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3442 }
3443
3444 #endif
3445
3446 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3447 {
3448         vpid_sync_context(to_vmx(vcpu));
3449         if (enable_ept) {
3450                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3451                         return;
3452                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3453         }
3454 }
3455
3456 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3457 {
3458         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3459
3460         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3461         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3462 }
3463
3464 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3465 {
3466         if (enable_ept && is_paging(vcpu))
3467                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3468         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3469 }
3470
3471 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3472 {
3473         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3474
3475         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3476         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3477 }
3478
3479 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3480 {
3481         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3482
3483         if (!test_bit(VCPU_EXREG_PDPTR,
3484                       (unsigned long *)&vcpu->arch.regs_dirty))
3485                 return;
3486
3487         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3488                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3489                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3490                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3491                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3492         }
3493 }
3494
3495 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3496 {
3497         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3498
3499         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3500                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3501                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3502                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3503                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3504         }
3505
3506         __set_bit(VCPU_EXREG_PDPTR,
3507                   (unsigned long *)&vcpu->arch.regs_avail);
3508         __set_bit(VCPU_EXREG_PDPTR,
3509                   (unsigned long *)&vcpu->arch.regs_dirty);
3510 }
3511
3512 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3513
3514 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3515                                         unsigned long cr0,
3516                                         struct kvm_vcpu *vcpu)
3517 {
3518         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3519                 vmx_decache_cr3(vcpu);
3520         if (!(cr0 & X86_CR0_PG)) {
3521                 /* From paging/starting to nonpaging */
3522                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3523                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3524                              (CPU_BASED_CR3_LOAD_EXITING |
3525                               CPU_BASED_CR3_STORE_EXITING));
3526                 vcpu->arch.cr0 = cr0;
3527                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3528         } else if (!is_paging(vcpu)) {
3529                 /* From nonpaging to paging */
3530                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3531                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3532                              ~(CPU_BASED_CR3_LOAD_EXITING |
3533                                CPU_BASED_CR3_STORE_EXITING));
3534                 vcpu->arch.cr0 = cr0;
3535                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3536         }
3537
3538         if (!(cr0 & X86_CR0_WP))
3539                 *hw_cr0 &= ~X86_CR0_WP;
3540 }
3541
3542 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3543 {
3544         struct vcpu_vmx *vmx = to_vmx(vcpu);
3545         unsigned long hw_cr0;
3546
3547         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3548         if (enable_unrestricted_guest)
3549                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3550         else {
3551                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3552
3553                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3554                         enter_pmode(vcpu);
3555
3556                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3557                         enter_rmode(vcpu);
3558         }
3559
3560 #ifdef CONFIG_X86_64
3561         if (vcpu->arch.efer & EFER_LME) {
3562                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3563                         enter_lmode(vcpu);
3564                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3565                         exit_lmode(vcpu);
3566         }
3567 #endif
3568
3569         if (enable_ept)
3570                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3571
3572         if (!vcpu->fpu_active)
3573                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3574
3575         vmcs_writel(CR0_READ_SHADOW, cr0);
3576         vmcs_writel(GUEST_CR0, hw_cr0);
3577         vcpu->arch.cr0 = cr0;
3578
3579         /* depends on vcpu->arch.cr0 to be set to a new value */
3580         vmx->emulation_required = emulation_required(vcpu);
3581 }
3582
3583 static u64 construct_eptp(unsigned long root_hpa)
3584 {
3585         u64 eptp;
3586
3587         /* TODO write the value reading from MSR */
3588         eptp = VMX_EPT_DEFAULT_MT |
3589                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3590         if (enable_ept_ad_bits)
3591                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3592         eptp |= (root_hpa & PAGE_MASK);
3593
3594         return eptp;
3595 }
3596
3597 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3598 {
3599         unsigned long guest_cr3;
3600         u64 eptp;
3601
3602         guest_cr3 = cr3;
3603         if (enable_ept) {
3604                 eptp = construct_eptp(cr3);
3605                 vmcs_write64(EPT_POINTER, eptp);
3606                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3607                         guest_cr3 = kvm_read_cr3(vcpu);
3608                 else
3609                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3610                 ept_load_pdptrs(vcpu);
3611         }
3612
3613         vmx_flush_tlb(vcpu);
3614         vmcs_writel(GUEST_CR3, guest_cr3);
3615 }
3616
3617 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3618 {
3619         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3620                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3621
3622         if (cr4 & X86_CR4_VMXE) {
3623                 /*
3624                  * To use VMXON (and later other VMX instructions), a guest
3625                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3626                  * So basically the check on whether to allow nested VMX
3627                  * is here.
3628                  */
3629                 if (!nested_vmx_allowed(vcpu))
3630                         return 1;
3631         }
3632         if (to_vmx(vcpu)->nested.vmxon &&
3633             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3634                 return 1;
3635
3636         vcpu->arch.cr4 = cr4;
3637         if (enable_ept) {
3638                 if (!is_paging(vcpu)) {
3639                         hw_cr4 &= ~X86_CR4_PAE;
3640                         hw_cr4 |= X86_CR4_PSE;
3641                         /*
3642                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3643                          * in hardware. However KVM always uses paging mode to
3644                          * emulate guest non-paging mode with TDP.
3645                          * To emulate this behavior, SMEP/SMAP needs to be
3646                          * manually disabled when guest switches to non-paging
3647                          * mode.
3648                          */
3649                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3650                 } else if (!(cr4 & X86_CR4_PAE)) {
3651                         hw_cr4 &= ~X86_CR4_PAE;
3652                 }
3653         }
3654
3655         vmcs_writel(CR4_READ_SHADOW, cr4);
3656         vmcs_writel(GUEST_CR4, hw_cr4);
3657         return 0;
3658 }
3659
3660 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3661                             struct kvm_segment *var, int seg)
3662 {
3663         struct vcpu_vmx *vmx = to_vmx(vcpu);
3664         u32 ar;
3665
3666         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3667                 *var = vmx->rmode.segs[seg];
3668                 if (seg == VCPU_SREG_TR
3669                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3670                         return;
3671                 var->base = vmx_read_guest_seg_base(vmx, seg);
3672                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3673                 return;
3674         }
3675         var->base = vmx_read_guest_seg_base(vmx, seg);
3676         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3677         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3678         ar = vmx_read_guest_seg_ar(vmx, seg);
3679         var->unusable = (ar >> 16) & 1;
3680         var->type = ar & 15;
3681         var->s = (ar >> 4) & 1;
3682         var->dpl = (ar >> 5) & 3;
3683         /*
3684          * Some userspaces do not preserve unusable property. Since usable
3685          * segment has to be present according to VMX spec we can use present
3686          * property to amend userspace bug by making unusable segment always
3687          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3688          * segment as unusable.
3689          */
3690         var->present = !var->unusable;
3691         var->avl = (ar >> 12) & 1;
3692         var->l = (ar >> 13) & 1;
3693         var->db = (ar >> 14) & 1;
3694         var->g = (ar >> 15) & 1;
3695 }
3696
3697 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3698 {
3699         struct kvm_segment s;
3700
3701         if (to_vmx(vcpu)->rmode.vm86_active) {
3702                 vmx_get_segment(vcpu, &s, seg);
3703                 return s.base;
3704         }
3705         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3706 }
3707
3708 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3709 {
3710         struct vcpu_vmx *vmx = to_vmx(vcpu);
3711
3712         if (unlikely(vmx->rmode.vm86_active))
3713                 return 0;
3714         else {
3715                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3716                 return AR_DPL(ar);
3717         }
3718 }
3719
3720 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3721 {
3722         u32 ar;
3723
3724         if (var->unusable || !var->present)
3725                 ar = 1 << 16;
3726         else {
3727                 ar = var->type & 15;
3728                 ar |= (var->s & 1) << 4;
3729                 ar |= (var->dpl & 3) << 5;
3730                 ar |= (var->present & 1) << 7;
3731                 ar |= (var->avl & 1) << 12;
3732                 ar |= (var->l & 1) << 13;
3733                 ar |= (var->db & 1) << 14;
3734                 ar |= (var->g & 1) << 15;
3735         }
3736
3737         return ar;
3738 }
3739
3740 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3741                             struct kvm_segment *var, int seg)
3742 {
3743         struct vcpu_vmx *vmx = to_vmx(vcpu);
3744         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3745
3746         vmx_segment_cache_clear(vmx);
3747
3748         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3749                 vmx->rmode.segs[seg] = *var;
3750                 if (seg == VCPU_SREG_TR)
3751                         vmcs_write16(sf->selector, var->selector);
3752                 else if (var->s)
3753                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3754                 goto out;
3755         }
3756
3757         vmcs_writel(sf->base, var->base);
3758         vmcs_write32(sf->limit, var->limit);
3759         vmcs_write16(sf->selector, var->selector);
3760
3761         /*
3762          *   Fix the "Accessed" bit in AR field of segment registers for older
3763          * qemu binaries.
3764          *   IA32 arch specifies that at the time of processor reset the
3765          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3766          * is setting it to 0 in the userland code. This causes invalid guest
3767          * state vmexit when "unrestricted guest" mode is turned on.
3768          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3769          * tree. Newer qemu binaries with that qemu fix would not need this
3770          * kvm hack.
3771          */
3772         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3773                 var->type |= 0x1; /* Accessed */
3774
3775         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3776
3777 out:
3778         vmx->emulation_required = emulation_required(vcpu);
3779 }
3780
3781 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3782 {
3783         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3784
3785         *db = (ar >> 14) & 1;
3786         *l = (ar >> 13) & 1;
3787 }
3788
3789 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3790 {
3791         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3792         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3793 }
3794
3795 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3796 {
3797         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3798         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3799 }
3800
3801 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3802 {
3803         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3804         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3805 }
3806
3807 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3808 {
3809         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3810         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3811 }
3812
3813 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3814 {
3815         struct kvm_segment var;
3816         u32 ar;
3817
3818         vmx_get_segment(vcpu, &var, seg);
3819         var.dpl = 0x3;
3820         if (seg == VCPU_SREG_CS)
3821                 var.type = 0x3;
3822         ar = vmx_segment_access_rights(&var);
3823
3824         if (var.base != (var.selector << 4))
3825                 return false;
3826         if (var.limit != 0xffff)
3827                 return false;
3828         if (ar != 0xf3)
3829                 return false;
3830
3831         return true;
3832 }
3833
3834 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3835 {
3836         struct kvm_segment cs;
3837         unsigned int cs_rpl;
3838
3839         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3840         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3841
3842         if (cs.unusable)
3843                 return false;
3844         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3845                 return false;
3846         if (!cs.s)
3847                 return false;
3848         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3849                 if (cs.dpl > cs_rpl)
3850                         return false;
3851         } else {
3852                 if (cs.dpl != cs_rpl)
3853                         return false;
3854         }
3855         if (!cs.present)
3856                 return false;
3857
3858         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3859         return true;
3860 }
3861
3862 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3863 {
3864         struct kvm_segment ss;
3865         unsigned int ss_rpl;
3866
3867         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3868         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3869
3870         if (ss.unusable)
3871                 return true;
3872         if (ss.type != 3 && ss.type != 7)
3873                 return false;
3874         if (!ss.s)
3875                 return false;
3876         if (ss.dpl != ss_rpl) /* DPL != RPL */
3877                 return false;
3878         if (!ss.present)
3879                 return false;
3880
3881         return true;
3882 }
3883
3884 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3885 {
3886         struct kvm_segment var;
3887         unsigned int rpl;
3888
3889         vmx_get_segment(vcpu, &var, seg);
3890         rpl = var.selector & SELECTOR_RPL_MASK;
3891
3892         if (var.unusable)
3893                 return true;
3894         if (!var.s)
3895                 return false;
3896         if (!var.present)
3897                 return false;
3898         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3899                 if (var.dpl < rpl) /* DPL < RPL */
3900                         return false;
3901         }
3902
3903         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3904          * rights flags
3905          */
3906         return true;
3907 }
3908
3909 static bool tr_valid(struct kvm_vcpu *vcpu)
3910 {
3911         struct kvm_segment tr;
3912
3913         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3914
3915         if (tr.unusable)
3916                 return false;
3917         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3918                 return false;
3919         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3920                 return false;
3921         if (!tr.present)
3922                 return false;
3923
3924         return true;
3925 }
3926
3927 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3928 {
3929         struct kvm_segment ldtr;
3930
3931         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3932
3933         if (ldtr.unusable)
3934                 return true;
3935         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3936                 return false;
3937         if (ldtr.type != 2)
3938                 return false;
3939         if (!ldtr.present)
3940                 return false;
3941
3942         return true;
3943 }
3944
3945 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3946 {
3947         struct kvm_segment cs, ss;
3948
3949         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3950         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3951
3952         return ((cs.selector & SELECTOR_RPL_MASK) ==
3953                  (ss.selector & SELECTOR_RPL_MASK));
3954 }
3955
3956 /*
3957  * Check if guest state is valid. Returns true if valid, false if
3958  * not.
3959  * We assume that registers are always usable
3960  */
3961 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3962 {
3963         if (enable_unrestricted_guest)
3964                 return true;
3965
3966         /* real mode guest state checks */
3967         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3968                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3969                         return false;
3970                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3971                         return false;
3972                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3973                         return false;
3974                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3975                         return false;
3976                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3977                         return false;
3978                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3979                         return false;
3980         } else {
3981         /* protected mode guest state checks */
3982                 if (!cs_ss_rpl_check(vcpu))
3983                         return false;
3984                 if (!code_segment_valid(vcpu))
3985                         return false;
3986                 if (!stack_segment_valid(vcpu))
3987                         return false;
3988                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3989                         return false;
3990                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3991                         return false;
3992                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3993                         return false;
3994                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3995                         return false;
3996                 if (!tr_valid(vcpu))
3997                         return false;
3998                 if (!ldtr_valid(vcpu))
3999                         return false;
4000         }
4001         /* TODO:
4002          * - Add checks on RIP
4003          * - Add checks on RFLAGS
4004          */
4005
4006         return true;
4007 }
4008
4009 static int init_rmode_tss(struct kvm *kvm)
4010 {
4011         gfn_t fn;
4012         u16 data = 0;
4013         int idx, r;
4014
4015         idx = srcu_read_lock(&kvm->srcu);
4016         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4017         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4018         if (r < 0)
4019                 goto out;
4020         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4021         r = kvm_write_guest_page(kvm, fn++, &data,
4022                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4023         if (r < 0)
4024                 goto out;
4025         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4026         if (r < 0)
4027                 goto out;
4028         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4029         if (r < 0)
4030                 goto out;
4031         data = ~0;
4032         r = kvm_write_guest_page(kvm, fn, &data,
4033                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4034                                  sizeof(u8));
4035 out:
4036         srcu_read_unlock(&kvm->srcu, idx);
4037         return r;
4038 }
4039
4040 static int init_rmode_identity_map(struct kvm *kvm)
4041 {
4042         int i, idx, r = 0;
4043         pfn_t identity_map_pfn;
4044         u32 tmp;
4045
4046         if (!enable_ept)
4047                 return 0;
4048
4049         /* Protect kvm->arch.ept_identity_pagetable_done. */
4050         mutex_lock(&kvm->slots_lock);
4051
4052         if (likely(kvm->arch.ept_identity_pagetable_done))
4053                 goto out2;
4054
4055         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4056
4057         r = alloc_identity_pagetable(kvm);
4058         if (r < 0)
4059                 goto out2;
4060
4061         idx = srcu_read_lock(&kvm->srcu);
4062         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4063         if (r < 0)
4064                 goto out;
4065         /* Set up identity-mapping pagetable for EPT in real mode */
4066         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4067                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4068                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4069                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4070                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4071                 if (r < 0)
4072                         goto out;
4073         }
4074         kvm->arch.ept_identity_pagetable_done = true;
4075
4076 out:
4077         srcu_read_unlock(&kvm->srcu, idx);
4078
4079 out2:
4080         mutex_unlock(&kvm->slots_lock);
4081         return r;
4082 }
4083
4084 static void seg_setup(int seg)
4085 {
4086         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4087         unsigned int ar;
4088
4089         vmcs_write16(sf->selector, 0);
4090         vmcs_writel(sf->base, 0);
4091         vmcs_write32(sf->limit, 0xffff);
4092         ar = 0x93;
4093         if (seg == VCPU_SREG_CS)
4094                 ar |= 0x08; /* code segment */
4095
4096         vmcs_write32(sf->ar_bytes, ar);
4097 }
4098
4099 static int alloc_apic_access_page(struct kvm *kvm)
4100 {
4101         struct page *page;
4102         struct kvm_userspace_memory_region kvm_userspace_mem;
4103         int r = 0;
4104
4105         mutex_lock(&kvm->slots_lock);
4106         if (kvm->arch.apic_access_page_done)
4107                 goto out;
4108         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4109         kvm_userspace_mem.flags = 0;
4110         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4111         kvm_userspace_mem.memory_size = PAGE_SIZE;
4112         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4113         if (r)
4114                 goto out;
4115
4116         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4117         if (is_error_page(page)) {
4118                 r = -EFAULT;
4119                 goto out;
4120         }
4121
4122         /*
4123          * Do not pin the page in memory, so that memory hot-unplug
4124          * is able to migrate it.
4125          */
4126         put_page(page);
4127         kvm->arch.apic_access_page_done = true;
4128 out:
4129         mutex_unlock(&kvm->slots_lock);
4130         return r;
4131 }
4132
4133 static int alloc_identity_pagetable(struct kvm *kvm)
4134 {
4135         /* Called with kvm->slots_lock held. */
4136
4137         struct kvm_userspace_memory_region kvm_userspace_mem;
4138         int r = 0;
4139
4140         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4141
4142         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4143         kvm_userspace_mem.flags = 0;
4144         kvm_userspace_mem.guest_phys_addr =
4145                 kvm->arch.ept_identity_map_addr;
4146         kvm_userspace_mem.memory_size = PAGE_SIZE;
4147         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4148
4149         return r;
4150 }
4151
4152 static void allocate_vpid(struct vcpu_vmx *vmx)
4153 {
4154         int vpid;
4155
4156         vmx->vpid = 0;
4157         if (!enable_vpid)
4158                 return;
4159         spin_lock(&vmx_vpid_lock);
4160         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4161         if (vpid < VMX_NR_VPIDS) {
4162                 vmx->vpid = vpid;
4163                 __set_bit(vpid, vmx_vpid_bitmap);
4164         }
4165         spin_unlock(&vmx_vpid_lock);
4166 }
4167
4168 static void free_vpid(struct vcpu_vmx *vmx)
4169 {
4170         if (!enable_vpid)
4171                 return;
4172         spin_lock(&vmx_vpid_lock);
4173         if (vmx->vpid != 0)
4174                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4175         spin_unlock(&vmx_vpid_lock);
4176 }
4177
4178 #define MSR_TYPE_R      1
4179 #define MSR_TYPE_W      2
4180 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4181                                                 u32 msr, int type)
4182 {
4183         int f = sizeof(unsigned long);
4184
4185         if (!cpu_has_vmx_msr_bitmap())
4186                 return;
4187
4188         /*
4189          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4190          * have the write-low and read-high bitmap offsets the wrong way round.
4191          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4192          */
4193         if (msr <= 0x1fff) {
4194                 if (type & MSR_TYPE_R)
4195                         /* read-low */
4196                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4197
4198                 if (type & MSR_TYPE_W)
4199                         /* write-low */
4200                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4201
4202         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4203                 msr &= 0x1fff;
4204                 if (type & MSR_TYPE_R)
4205                         /* read-high */
4206                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4207
4208                 if (type & MSR_TYPE_W)
4209                         /* write-high */
4210                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4211
4212         }
4213 }
4214
4215 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4216                                                 u32 msr, int type)
4217 {
4218         int f = sizeof(unsigned long);
4219
4220         if (!cpu_has_vmx_msr_bitmap())
4221                 return;
4222
4223         /*
4224          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4225          * have the write-low and read-high bitmap offsets the wrong way round.
4226          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4227          */
4228         if (msr <= 0x1fff) {
4229                 if (type & MSR_TYPE_R)
4230                         /* read-low */
4231                         __set_bit(msr, msr_bitmap + 0x000 / f);
4232
4233                 if (type & MSR_TYPE_W)
4234                         /* write-low */
4235                         __set_bit(msr, msr_bitmap + 0x800 / f);
4236
4237         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4238                 msr &= 0x1fff;
4239                 if (type & MSR_TYPE_R)
4240                         /* read-high */
4241                         __set_bit(msr, msr_bitmap + 0x400 / f);
4242
4243                 if (type & MSR_TYPE_W)
4244                         /* write-high */
4245                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4246
4247         }
4248 }
4249
4250 /*
4251  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4252  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4253  */
4254 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4255                                                unsigned long *msr_bitmap_nested,
4256                                                u32 msr, int type)
4257 {
4258         int f = sizeof(unsigned long);
4259
4260         if (!cpu_has_vmx_msr_bitmap()) {
4261                 WARN_ON(1);
4262                 return;
4263         }
4264
4265         /*
4266          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4267          * have the write-low and read-high bitmap offsets the wrong way round.
4268          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4269          */
4270         if (msr <= 0x1fff) {
4271                 if (type & MSR_TYPE_R &&
4272                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4273                         /* read-low */
4274                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4275
4276                 if (type & MSR_TYPE_W &&
4277                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4278                         /* write-low */
4279                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4280
4281         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4282                 msr &= 0x1fff;
4283                 if (type & MSR_TYPE_R &&
4284                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4285                         /* read-high */
4286                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4287
4288                 if (type & MSR_TYPE_W &&
4289                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4290                         /* write-high */
4291                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4292
4293         }
4294 }
4295
4296 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4297 {
4298         if (!longmode_only)
4299                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4300                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4301         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4302                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4303 }
4304
4305 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4306 {
4307         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4308                         msr, MSR_TYPE_R);
4309         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4310                         msr, MSR_TYPE_R);
4311 }
4312
4313 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4314 {
4315         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4316                         msr, MSR_TYPE_R);
4317         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4318                         msr, MSR_TYPE_R);
4319 }
4320
4321 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4322 {
4323         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4324                         msr, MSR_TYPE_W);
4325         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4326                         msr, MSR_TYPE_W);
4327 }
4328
4329 static int vmx_vm_has_apicv(struct kvm *kvm)
4330 {
4331         return enable_apicv && irqchip_in_kernel(kvm);
4332 }
4333
4334 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4335 {
4336         struct vcpu_vmx *vmx = to_vmx(vcpu);
4337         int max_irr;
4338         void *vapic_page;
4339         u16 status;
4340
4341         if (vmx->nested.pi_desc &&
4342             vmx->nested.pi_pending) {
4343                 vmx->nested.pi_pending = false;
4344                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4345                         return 0;
4346
4347                 max_irr = find_last_bit(
4348                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4349
4350                 if (max_irr == 256)
4351                         return 0;
4352
4353                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4354                 if (!vapic_page) {
4355                         WARN_ON(1);
4356                         return -ENOMEM;
4357                 }
4358                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4359                 kunmap(vmx->nested.virtual_apic_page);
4360
4361                 status = vmcs_read16(GUEST_INTR_STATUS);
4362                 if ((u8)max_irr > ((u8)status & 0xff)) {
4363                         status &= ~0xff;
4364                         status |= (u8)max_irr;
4365                         vmcs_write16(GUEST_INTR_STATUS, status);
4366                 }
4367         }
4368         return 0;
4369 }
4370
4371 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4372 {
4373 #ifdef CONFIG_SMP
4374         if (vcpu->mode == IN_GUEST_MODE) {
4375                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4376                                 POSTED_INTR_VECTOR);
4377                 return true;
4378         }
4379 #endif
4380         return false;
4381 }
4382
4383 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4384                                                 int vector)
4385 {
4386         struct vcpu_vmx *vmx = to_vmx(vcpu);
4387
4388         if (is_guest_mode(vcpu) &&
4389             vector == vmx->nested.posted_intr_nv) {
4390                 /* the PIR and ON have been set by L1. */
4391                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4392                 /*
4393                  * If a posted intr is not recognized by hardware,
4394                  * we will accomplish it in the next vmentry.
4395                  */
4396                 vmx->nested.pi_pending = true;
4397                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4398                 return 0;
4399         }
4400         return -1;
4401 }
4402 /*
4403  * Send interrupt to vcpu via posted interrupt way.
4404  * 1. If target vcpu is running(non-root mode), send posted interrupt
4405  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4406  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4407  * interrupt from PIR in next vmentry.
4408  */
4409 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4410 {
4411         struct vcpu_vmx *vmx = to_vmx(vcpu);
4412         int r;
4413
4414         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4415         if (!r)
4416                 return;
4417
4418         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4419                 return;
4420
4421         r = pi_test_and_set_on(&vmx->pi_desc);
4422         kvm_make_request(KVM_REQ_EVENT, vcpu);
4423         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4424                 kvm_vcpu_kick(vcpu);
4425 }
4426
4427 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4428 {
4429         struct vcpu_vmx *vmx = to_vmx(vcpu);
4430
4431         if (!pi_test_and_clear_on(&vmx->pi_desc))
4432                 return;
4433
4434         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4435 }
4436
4437 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4438 {
4439         return;
4440 }
4441
4442 /*
4443  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4444  * will not change in the lifetime of the guest.
4445  * Note that host-state that does change is set elsewhere. E.g., host-state
4446  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4447  */
4448 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4449 {
4450         u32 low32, high32;
4451         unsigned long tmpl;
4452         struct desc_ptr dt;
4453         unsigned long cr4;
4454
4455         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4456         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4457
4458         /* Save the most likely value for this task's CR4 in the VMCS. */
4459         cr4 = cr4_read_shadow();
4460         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4461         vmx->host_state.vmcs_host_cr4 = cr4;
4462
4463         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4464 #ifdef CONFIG_X86_64
4465         /*
4466          * Load null selectors, so we can avoid reloading them in
4467          * __vmx_load_host_state(), in case userspace uses the null selectors
4468          * too (the expected case).
4469          */
4470         vmcs_write16(HOST_DS_SELECTOR, 0);
4471         vmcs_write16(HOST_ES_SELECTOR, 0);
4472 #else
4473         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4474         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4475 #endif
4476         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4477         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4478
4479         native_store_idt(&dt);
4480         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4481         vmx->host_idt_base = dt.address;
4482
4483         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4484
4485         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4486         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4487         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4488         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4489
4490         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4491                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4492                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4493         }
4494 }
4495
4496 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4497 {
4498         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4499         if (enable_ept)
4500                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4501         if (is_guest_mode(&vmx->vcpu))
4502                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4503                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4504         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4505 }
4506
4507 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4508 {
4509         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4510
4511         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4512                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4513         return pin_based_exec_ctrl;
4514 }
4515
4516 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4517 {
4518         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4519
4520         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4521                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4522
4523         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4524                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4525 #ifdef CONFIG_X86_64
4526                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4527                                 CPU_BASED_CR8_LOAD_EXITING;
4528 #endif
4529         }
4530         if (!enable_ept)
4531                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4532                                 CPU_BASED_CR3_LOAD_EXITING  |
4533                                 CPU_BASED_INVLPG_EXITING;
4534         return exec_control;
4535 }
4536
4537 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4538 {
4539         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4540         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4541                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4542         if (vmx->vpid == 0)
4543                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4544         if (!enable_ept) {
4545                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4546                 enable_unrestricted_guest = 0;
4547                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4548                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4549         }
4550         if (!enable_unrestricted_guest)
4551                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4552         if (!ple_gap)
4553                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4554         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4555                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4556                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4557         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4558         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4559            (handle_vmptrld).
4560            We can NOT enable shadow_vmcs here because we don't have yet
4561            a current VMCS12
4562         */
4563         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4564         /* PML is enabled/disabled in creating/destorying vcpu */
4565         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4566
4567         return exec_control;
4568 }
4569
4570 static void ept_set_mmio_spte_mask(void)
4571 {
4572         /*
4573          * EPT Misconfigurations can be generated if the value of bits 2:0
4574          * of an EPT paging-structure entry is 110b (write/execute).
4575          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4576          * spte.
4577          */
4578         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4579 }
4580
4581 #define VMX_XSS_EXIT_BITMAP 0
4582 /*
4583  * Sets up the vmcs for emulated real mode.
4584  */
4585 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4586 {
4587 #ifdef CONFIG_X86_64
4588         unsigned long a;
4589 #endif
4590         int i;
4591
4592         /* I/O */
4593         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4594         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4595
4596         if (enable_shadow_vmcs) {
4597                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4598                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4599         }
4600         if (cpu_has_vmx_msr_bitmap())
4601                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4602
4603         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4604
4605         /* Control */
4606         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4607
4608         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4609
4610         if (cpu_has_secondary_exec_ctrls()) {
4611                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4612                                 vmx_secondary_exec_control(vmx));
4613         }
4614
4615         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4616                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4617                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4618                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4619                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4620
4621                 vmcs_write16(GUEST_INTR_STATUS, 0);
4622
4623                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4624                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4625         }
4626
4627         if (ple_gap) {
4628                 vmcs_write32(PLE_GAP, ple_gap);
4629                 vmx->ple_window = ple_window;
4630                 vmx->ple_window_dirty = true;
4631         }
4632
4633         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4634         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4635         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4636
4637         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4638         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4639         vmx_set_constant_host_state(vmx);
4640 #ifdef CONFIG_X86_64
4641         rdmsrl(MSR_FS_BASE, a);
4642         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4643         rdmsrl(MSR_GS_BASE, a);
4644         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4645 #else
4646         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4647         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4648 #endif
4649
4650         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4651         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4652         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4653         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4654         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4655
4656         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4657                 u32 msr_low, msr_high;
4658                 u64 host_pat;
4659                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4660                 host_pat = msr_low | ((u64) msr_high << 32);
4661                 /* Write the default value follow host pat */
4662                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4663                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4664                 vmx->vcpu.arch.pat = host_pat;
4665         }
4666
4667         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4668                 u32 index = vmx_msr_index[i];
4669                 u32 data_low, data_high;
4670                 int j = vmx->nmsrs;
4671
4672                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4673                         continue;
4674                 if (wrmsr_safe(index, data_low, data_high) < 0)
4675                         continue;
4676                 vmx->guest_msrs[j].index = i;
4677                 vmx->guest_msrs[j].data = 0;
4678                 vmx->guest_msrs[j].mask = -1ull;
4679                 ++vmx->nmsrs;
4680         }
4681
4682
4683         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4684
4685         /* 22.2.1, 20.8.1 */
4686         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4687
4688         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4689         set_cr4_guest_host_mask(vmx);
4690
4691         if (vmx_xsaves_supported())
4692                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4693
4694         return 0;
4695 }
4696
4697 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4698 {
4699         struct vcpu_vmx *vmx = to_vmx(vcpu);
4700         struct msr_data apic_base_msr;
4701
4702         vmx->rmode.vm86_active = 0;
4703
4704         vmx->soft_vnmi_blocked = 0;
4705
4706         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4707         kvm_set_cr8(&vmx->vcpu, 0);
4708         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4709         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4710                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4711         apic_base_msr.host_initiated = true;
4712         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4713
4714         vmx_segment_cache_clear(vmx);
4715
4716         seg_setup(VCPU_SREG_CS);
4717         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4718         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4719
4720         seg_setup(VCPU_SREG_DS);
4721         seg_setup(VCPU_SREG_ES);
4722         seg_setup(VCPU_SREG_FS);
4723         seg_setup(VCPU_SREG_GS);
4724         seg_setup(VCPU_SREG_SS);
4725
4726         vmcs_write16(GUEST_TR_SELECTOR, 0);
4727         vmcs_writel(GUEST_TR_BASE, 0);
4728         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4729         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4730
4731         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4732         vmcs_writel(GUEST_LDTR_BASE, 0);
4733         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4734         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4735
4736         vmcs_write32(GUEST_SYSENTER_CS, 0);
4737         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4738         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4739
4740         vmcs_writel(GUEST_RFLAGS, 0x02);
4741         kvm_rip_write(vcpu, 0xfff0);
4742
4743         vmcs_writel(GUEST_GDTR_BASE, 0);
4744         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4745
4746         vmcs_writel(GUEST_IDTR_BASE, 0);
4747         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4748
4749         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4750         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4751         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4752
4753         /* Special registers */
4754         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4755
4756         setup_msrs(vmx);
4757
4758         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4759
4760         if (cpu_has_vmx_tpr_shadow()) {
4761                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4762                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4763                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4764                                      __pa(vmx->vcpu.arch.apic->regs));
4765                 vmcs_write32(TPR_THRESHOLD, 0);
4766         }
4767
4768         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4769
4770         if (vmx_vm_has_apicv(vcpu->kvm))
4771                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4772
4773         if (vmx->vpid != 0)
4774                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4775
4776         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4777         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4778         vmx_set_cr4(&vmx->vcpu, 0);
4779         vmx_set_efer(&vmx->vcpu, 0);
4780         vmx_fpu_activate(&vmx->vcpu);
4781         update_exception_bitmap(&vmx->vcpu);
4782
4783         vpid_sync_context(vmx);
4784 }
4785
4786 /*
4787  * In nested virtualization, check if L1 asked to exit on external interrupts.
4788  * For most existing hypervisors, this will always return true.
4789  */
4790 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4791 {
4792         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4793                 PIN_BASED_EXT_INTR_MASK;
4794 }
4795
4796 /*
4797  * In nested virtualization, check if L1 has set
4798  * VM_EXIT_ACK_INTR_ON_EXIT
4799  */
4800 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4801 {
4802         return get_vmcs12(vcpu)->vm_exit_controls &
4803                 VM_EXIT_ACK_INTR_ON_EXIT;
4804 }
4805
4806 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4807 {
4808         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4809                 PIN_BASED_NMI_EXITING;
4810 }
4811
4812 static void enable_irq_window(struct kvm_vcpu *vcpu)
4813 {
4814         u32 cpu_based_vm_exec_control;
4815
4816         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4817         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4818         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4819 }
4820
4821 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4822 {
4823         u32 cpu_based_vm_exec_control;
4824
4825         if (!cpu_has_virtual_nmis() ||
4826             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4827                 enable_irq_window(vcpu);
4828                 return;
4829         }
4830
4831         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4832         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4833         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4834 }
4835
4836 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4837 {
4838         struct vcpu_vmx *vmx = to_vmx(vcpu);
4839         uint32_t intr;
4840         int irq = vcpu->arch.interrupt.nr;
4841
4842         trace_kvm_inj_virq(irq);
4843
4844         ++vcpu->stat.irq_injections;
4845         if (vmx->rmode.vm86_active) {
4846                 int inc_eip = 0;
4847                 if (vcpu->arch.interrupt.soft)
4848                         inc_eip = vcpu->arch.event_exit_inst_len;
4849                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4850                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4851                 return;
4852         }
4853         intr = irq | INTR_INFO_VALID_MASK;
4854         if (vcpu->arch.interrupt.soft) {
4855                 intr |= INTR_TYPE_SOFT_INTR;
4856                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4857                              vmx->vcpu.arch.event_exit_inst_len);
4858         } else
4859                 intr |= INTR_TYPE_EXT_INTR;
4860         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4861 }
4862
4863 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4864 {
4865         struct vcpu_vmx *vmx = to_vmx(vcpu);
4866
4867         if (is_guest_mode(vcpu))
4868                 return;
4869
4870         if (!cpu_has_virtual_nmis()) {
4871                 /*
4872                  * Tracking the NMI-blocked state in software is built upon
4873                  * finding the next open IRQ window. This, in turn, depends on
4874                  * well-behaving guests: They have to keep IRQs disabled at
4875                  * least as long as the NMI handler runs. Otherwise we may
4876                  * cause NMI nesting, maybe breaking the guest. But as this is
4877                  * highly unlikely, we can live with the residual risk.
4878                  */
4879                 vmx->soft_vnmi_blocked = 1;
4880                 vmx->vnmi_blocked_time = 0;
4881         }
4882
4883         ++vcpu->stat.nmi_injections;
4884         vmx->nmi_known_unmasked = false;
4885         if (vmx->rmode.vm86_active) {
4886                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4887                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4888                 return;
4889         }
4890         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4891                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4892 }
4893
4894 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4895 {
4896         if (!cpu_has_virtual_nmis())
4897                 return to_vmx(vcpu)->soft_vnmi_blocked;
4898         if (to_vmx(vcpu)->nmi_known_unmasked)
4899                 return false;
4900         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4901 }
4902
4903 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4904 {
4905         struct vcpu_vmx *vmx = to_vmx(vcpu);
4906
4907         if (!cpu_has_virtual_nmis()) {
4908                 if (vmx->soft_vnmi_blocked != masked) {
4909                         vmx->soft_vnmi_blocked = masked;
4910                         vmx->vnmi_blocked_time = 0;
4911                 }
4912         } else {
4913                 vmx->nmi_known_unmasked = !masked;
4914                 if (masked)
4915                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4916                                       GUEST_INTR_STATE_NMI);
4917                 else
4918                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4919                                         GUEST_INTR_STATE_NMI);
4920         }
4921 }
4922
4923 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4924 {
4925         if (to_vmx(vcpu)->nested.nested_run_pending)
4926                 return 0;
4927
4928         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4929                 return 0;
4930
4931         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4932                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4933                    | GUEST_INTR_STATE_NMI));
4934 }
4935
4936 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4937 {
4938         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4939                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4940                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4941                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4942 }
4943
4944 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4945 {
4946         int ret;
4947         struct kvm_userspace_memory_region tss_mem = {
4948                 .slot = TSS_PRIVATE_MEMSLOT,
4949                 .guest_phys_addr = addr,
4950                 .memory_size = PAGE_SIZE * 3,
4951                 .flags = 0,
4952         };
4953
4954         ret = kvm_set_memory_region(kvm, &tss_mem);
4955         if (ret)
4956                 return ret;
4957         kvm->arch.tss_addr = addr;
4958         return init_rmode_tss(kvm);
4959 }
4960
4961 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4962 {
4963         switch (vec) {
4964         case BP_VECTOR:
4965                 /*
4966                  * Update instruction length as we may reinject the exception
4967                  * from user space while in guest debugging mode.
4968                  */
4969                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4970                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4971                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4972                         return false;
4973                 /* fall through */
4974         case DB_VECTOR:
4975                 if (vcpu->guest_debug &
4976                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4977                         return false;
4978                 /* fall through */
4979         case DE_VECTOR:
4980         case OF_VECTOR:
4981         case BR_VECTOR:
4982         case UD_VECTOR:
4983         case DF_VECTOR:
4984         case SS_VECTOR:
4985         case GP_VECTOR:
4986         case MF_VECTOR:
4987                 return true;
4988         break;
4989         }
4990         return false;
4991 }
4992
4993 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4994                                   int vec, u32 err_code)
4995 {
4996         /*
4997          * Instruction with address size override prefix opcode 0x67
4998          * Cause the #SS fault with 0 error code in VM86 mode.
4999          */
5000         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5001                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5002                         if (vcpu->arch.halt_request) {
5003                                 vcpu->arch.halt_request = 0;
5004                                 return kvm_vcpu_halt(vcpu);
5005                         }
5006                         return 1;
5007                 }
5008                 return 0;
5009         }
5010
5011         /*
5012          * Forward all other exceptions that are valid in real mode.
5013          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5014          *        the required debugging infrastructure rework.
5015          */
5016         kvm_queue_exception(vcpu, vec);
5017         return 1;
5018 }
5019
5020 /*
5021  * Trigger machine check on the host. We assume all the MSRs are already set up
5022  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5023  * We pass a fake environment to the machine check handler because we want
5024  * the guest to be always treated like user space, no matter what context
5025  * it used internally.
5026  */
5027 static void kvm_machine_check(void)
5028 {
5029 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5030         struct pt_regs regs = {
5031                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5032                 .flags = X86_EFLAGS_IF,
5033         };
5034
5035         do_machine_check(&regs, 0);
5036 #endif
5037 }
5038
5039 static int handle_machine_check(struct kvm_vcpu *vcpu)
5040 {
5041         /* already handled by vcpu_run */
5042         return 1;
5043 }
5044
5045 static int handle_exception(struct kvm_vcpu *vcpu)
5046 {
5047         struct vcpu_vmx *vmx = to_vmx(vcpu);
5048         struct kvm_run *kvm_run = vcpu->run;
5049         u32 intr_info, ex_no, error_code;
5050         unsigned long cr2, rip, dr6;
5051         u32 vect_info;
5052         enum emulation_result er;
5053
5054         vect_info = vmx->idt_vectoring_info;
5055         intr_info = vmx->exit_intr_info;
5056
5057         if (is_machine_check(intr_info))
5058                 return handle_machine_check(vcpu);
5059
5060         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5061                 return 1;  /* already handled by vmx_vcpu_run() */
5062
5063         if (is_no_device(intr_info)) {
5064                 vmx_fpu_activate(vcpu);
5065                 return 1;
5066         }
5067
5068         if (is_invalid_opcode(intr_info)) {
5069                 if (is_guest_mode(vcpu)) {
5070                         kvm_queue_exception(vcpu, UD_VECTOR);
5071                         return 1;
5072                 }
5073                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5074                 if (er != EMULATE_DONE)
5075                         kvm_queue_exception(vcpu, UD_VECTOR);
5076                 return 1;
5077         }
5078
5079         error_code = 0;
5080         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5081                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5082
5083         /*
5084          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5085          * MMIO, it is better to report an internal error.
5086          * See the comments in vmx_handle_exit.
5087          */
5088         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5089             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5090                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5091                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5092                 vcpu->run->internal.ndata = 2;
5093                 vcpu->run->internal.data[0] = vect_info;
5094                 vcpu->run->internal.data[1] = intr_info;
5095                 return 0;
5096         }
5097
5098         if (is_page_fault(intr_info)) {
5099                 /* EPT won't cause page fault directly */
5100                 BUG_ON(enable_ept);
5101                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5102                 trace_kvm_page_fault(cr2, error_code);
5103
5104                 if (kvm_event_needs_reinjection(vcpu))
5105                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5106                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5107         }
5108
5109         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5110
5111         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5112                 return handle_rmode_exception(vcpu, ex_no, error_code);
5113
5114         switch (ex_no) {
5115         case DB_VECTOR:
5116                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5117                 if (!(vcpu->guest_debug &
5118                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5119                         vcpu->arch.dr6 &= ~15;
5120                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5121                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5122                                 skip_emulated_instruction(vcpu);
5123
5124                         kvm_queue_exception(vcpu, DB_VECTOR);
5125                         return 1;
5126                 }
5127                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5128                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5129                 /* fall through */
5130         case BP_VECTOR:
5131                 /*
5132                  * Update instruction length as we may reinject #BP from
5133                  * user space while in guest debugging mode. Reading it for
5134                  * #DB as well causes no harm, it is not used in that case.
5135                  */
5136                 vmx->vcpu.arch.event_exit_inst_len =
5137                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5138                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5139                 rip = kvm_rip_read(vcpu);
5140                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5141                 kvm_run->debug.arch.exception = ex_no;
5142                 break;
5143         default:
5144                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5145                 kvm_run->ex.exception = ex_no;
5146                 kvm_run->ex.error_code = error_code;
5147                 break;
5148         }
5149         return 0;
5150 }
5151
5152 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5153 {
5154         ++vcpu->stat.irq_exits;
5155         return 1;
5156 }
5157
5158 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5159 {
5160         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5161         return 0;
5162 }
5163
5164 static int handle_io(struct kvm_vcpu *vcpu)
5165 {
5166         unsigned long exit_qualification;
5167         int size, in, string;
5168         unsigned port;
5169
5170         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5171         string = (exit_qualification & 16) != 0;
5172         in = (exit_qualification & 8) != 0;
5173
5174         ++vcpu->stat.io_exits;
5175
5176         if (string || in)
5177                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5178
5179         port = exit_qualification >> 16;
5180         size = (exit_qualification & 7) + 1;
5181         skip_emulated_instruction(vcpu);
5182
5183         return kvm_fast_pio_out(vcpu, size, port);
5184 }
5185
5186 static void
5187 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5188 {
5189         /*
5190          * Patch in the VMCALL instruction:
5191          */
5192         hypercall[0] = 0x0f;
5193         hypercall[1] = 0x01;
5194         hypercall[2] = 0xc1;
5195 }
5196
5197 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5198 {
5199         unsigned long always_on = VMXON_CR0_ALWAYSON;
5200         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5201
5202         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5203                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5204             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5205                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5206         return (val & always_on) == always_on;
5207 }
5208
5209 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5210 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5211 {
5212         if (is_guest_mode(vcpu)) {
5213                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5214                 unsigned long orig_val = val;
5215
5216                 /*
5217                  * We get here when L2 changed cr0 in a way that did not change
5218                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5219                  * but did change L0 shadowed bits. So we first calculate the
5220                  * effective cr0 value that L1 would like to write into the
5221                  * hardware. It consists of the L2-owned bits from the new
5222                  * value combined with the L1-owned bits from L1's guest_cr0.
5223                  */
5224                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5225                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5226
5227                 if (!nested_cr0_valid(vcpu, val))
5228                         return 1;
5229
5230                 if (kvm_set_cr0(vcpu, val))
5231                         return 1;
5232                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5233                 return 0;
5234         } else {
5235                 if (to_vmx(vcpu)->nested.vmxon &&
5236                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5237                         return 1;
5238                 return kvm_set_cr0(vcpu, val);
5239         }
5240 }
5241
5242 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5243 {
5244         if (is_guest_mode(vcpu)) {
5245                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5246                 unsigned long orig_val = val;
5247
5248                 /* analogously to handle_set_cr0 */
5249                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5250                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5251                 if (kvm_set_cr4(vcpu, val))
5252                         return 1;
5253                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5254                 return 0;
5255         } else
5256                 return kvm_set_cr4(vcpu, val);
5257 }
5258
5259 /* called to set cr0 as approriate for clts instruction exit. */
5260 static void handle_clts(struct kvm_vcpu *vcpu)
5261 {
5262         if (is_guest_mode(vcpu)) {
5263                 /*
5264                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5265                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5266                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5267                  */
5268                 vmcs_writel(CR0_READ_SHADOW,
5269                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5270                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5271         } else
5272                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5273 }
5274
5275 static int handle_cr(struct kvm_vcpu *vcpu)
5276 {
5277         unsigned long exit_qualification, val;
5278         int cr;
5279         int reg;
5280         int err;
5281
5282         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5283         cr = exit_qualification & 15;
5284         reg = (exit_qualification >> 8) & 15;
5285         switch ((exit_qualification >> 4) & 3) {
5286         case 0: /* mov to cr */
5287                 val = kvm_register_readl(vcpu, reg);
5288                 trace_kvm_cr_write(cr, val);
5289                 switch (cr) {
5290                 case 0:
5291                         err = handle_set_cr0(vcpu, val);
5292                         kvm_complete_insn_gp(vcpu, err);
5293                         return 1;
5294                 case 3:
5295                         err = kvm_set_cr3(vcpu, val);
5296                         kvm_complete_insn_gp(vcpu, err);
5297                         return 1;
5298                 case 4:
5299                         err = handle_set_cr4(vcpu, val);
5300                         kvm_complete_insn_gp(vcpu, err);
5301                         return 1;
5302                 case 8: {
5303                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5304                                 u8 cr8 = (u8)val;
5305                                 err = kvm_set_cr8(vcpu, cr8);
5306                                 kvm_complete_insn_gp(vcpu, err);
5307                                 if (irqchip_in_kernel(vcpu->kvm))
5308                                         return 1;
5309                                 if (cr8_prev <= cr8)
5310                                         return 1;
5311                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5312                                 return 0;
5313                         }
5314                 }
5315                 break;
5316         case 2: /* clts */
5317                 handle_clts(vcpu);
5318                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5319                 skip_emulated_instruction(vcpu);
5320                 vmx_fpu_activate(vcpu);
5321                 return 1;
5322         case 1: /*mov from cr*/
5323                 switch (cr) {
5324                 case 3:
5325                         val = kvm_read_cr3(vcpu);
5326                         kvm_register_write(vcpu, reg, val);
5327                         trace_kvm_cr_read(cr, val);
5328                         skip_emulated_instruction(vcpu);
5329                         return 1;
5330                 case 8:
5331                         val = kvm_get_cr8(vcpu);
5332                         kvm_register_write(vcpu, reg, val);
5333                         trace_kvm_cr_read(cr, val);
5334                         skip_emulated_instruction(vcpu);
5335                         return 1;
5336                 }
5337                 break;
5338         case 3: /* lmsw */
5339                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5340                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5341                 kvm_lmsw(vcpu, val);
5342
5343                 skip_emulated_instruction(vcpu);
5344                 return 1;
5345         default:
5346                 break;
5347         }
5348         vcpu->run->exit_reason = 0;
5349         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5350                (int)(exit_qualification >> 4) & 3, cr);
5351         return 0;
5352 }
5353
5354 static int handle_dr(struct kvm_vcpu *vcpu)
5355 {
5356         unsigned long exit_qualification;
5357         int dr, dr7, reg;
5358
5359         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5360         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5361
5362         /* First, if DR does not exist, trigger UD */
5363         if (!kvm_require_dr(vcpu, dr))
5364                 return 1;
5365
5366         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5367         if (!kvm_require_cpl(vcpu, 0))
5368                 return 1;
5369         dr7 = vmcs_readl(GUEST_DR7);
5370         if (dr7 & DR7_GD) {
5371                 /*
5372                  * As the vm-exit takes precedence over the debug trap, we
5373                  * need to emulate the latter, either for the host or the
5374                  * guest debugging itself.
5375                  */
5376                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5377                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5378                         vcpu->run->debug.arch.dr7 = dr7;
5379                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5380                         vcpu->run->debug.arch.exception = DB_VECTOR;
5381                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5382                         return 0;
5383                 } else {
5384                         vcpu->arch.dr6 &= ~15;
5385                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5386                         kvm_queue_exception(vcpu, DB_VECTOR);
5387                         return 1;
5388                 }
5389         }
5390
5391         if (vcpu->guest_debug == 0) {
5392                 u32 cpu_based_vm_exec_control;
5393
5394                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5395                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5396                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5397
5398                 /*
5399                  * No more DR vmexits; force a reload of the debug registers
5400                  * and reenter on this instruction.  The next vmexit will
5401                  * retrieve the full state of the debug registers.
5402                  */
5403                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5404                 return 1;
5405         }
5406
5407         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5408         if (exit_qualification & TYPE_MOV_FROM_DR) {
5409                 unsigned long val;
5410
5411                 if (kvm_get_dr(vcpu, dr, &val))
5412                         return 1;
5413                 kvm_register_write(vcpu, reg, val);
5414         } else
5415                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5416                         return 1;
5417
5418         skip_emulated_instruction(vcpu);
5419         return 1;
5420 }
5421
5422 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5423 {
5424         return vcpu->arch.dr6;
5425 }
5426
5427 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5428 {
5429 }
5430
5431 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5432 {
5433         u32 cpu_based_vm_exec_control;
5434
5435         get_debugreg(vcpu->arch.db[0], 0);
5436         get_debugreg(vcpu->arch.db[1], 1);
5437         get_debugreg(vcpu->arch.db[2], 2);
5438         get_debugreg(vcpu->arch.db[3], 3);
5439         get_debugreg(vcpu->arch.dr6, 6);
5440         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5441
5442         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5443
5444         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5445         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5446         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5447 }
5448
5449 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5450 {
5451         vmcs_writel(GUEST_DR7, val);
5452 }
5453
5454 static int handle_cpuid(struct kvm_vcpu *vcpu)
5455 {
5456         kvm_emulate_cpuid(vcpu);
5457         return 1;
5458 }
5459
5460 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5461 {
5462         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5463         u64 data;
5464
5465         if (vmx_get_msr(vcpu, ecx, &data)) {
5466                 trace_kvm_msr_read_ex(ecx);
5467                 kvm_inject_gp(vcpu, 0);
5468                 return 1;
5469         }
5470
5471         trace_kvm_msr_read(ecx, data);
5472
5473         /* FIXME: handling of bits 32:63 of rax, rdx */
5474         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5475         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5476         skip_emulated_instruction(vcpu);
5477         return 1;
5478 }
5479
5480 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5481 {
5482         struct msr_data msr;
5483         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5484         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5485                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5486
5487         msr.data = data;
5488         msr.index = ecx;
5489         msr.host_initiated = false;
5490         if (kvm_set_msr(vcpu, &msr) != 0) {
5491                 trace_kvm_msr_write_ex(ecx, data);
5492                 kvm_inject_gp(vcpu, 0);
5493                 return 1;
5494         }
5495
5496         trace_kvm_msr_write(ecx, data);
5497         skip_emulated_instruction(vcpu);
5498         return 1;
5499 }
5500
5501 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5502 {
5503         kvm_make_request(KVM_REQ_EVENT, vcpu);
5504         return 1;
5505 }
5506
5507 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5508 {
5509         u32 cpu_based_vm_exec_control;
5510
5511         /* clear pending irq */
5512         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5513         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5514         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5515
5516         kvm_make_request(KVM_REQ_EVENT, vcpu);
5517
5518         ++vcpu->stat.irq_window_exits;
5519
5520         /*
5521          * If the user space waits to inject interrupts, exit as soon as
5522          * possible
5523          */
5524         if (!irqchip_in_kernel(vcpu->kvm) &&
5525             vcpu->run->request_interrupt_window &&
5526             !kvm_cpu_has_interrupt(vcpu)) {
5527                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5528                 return 0;
5529         }
5530         return 1;
5531 }
5532
5533 static int handle_halt(struct kvm_vcpu *vcpu)
5534 {
5535         return kvm_emulate_halt(vcpu);
5536 }
5537
5538 static int handle_vmcall(struct kvm_vcpu *vcpu)
5539 {
5540         kvm_emulate_hypercall(vcpu);
5541         return 1;
5542 }
5543
5544 static int handle_invd(struct kvm_vcpu *vcpu)
5545 {
5546         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5547 }
5548
5549 static int handle_invlpg(struct kvm_vcpu *vcpu)
5550 {
5551         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5552
5553         kvm_mmu_invlpg(vcpu, exit_qualification);
5554         skip_emulated_instruction(vcpu);
5555         return 1;
5556 }
5557
5558 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5559 {
5560         int err;
5561
5562         err = kvm_rdpmc(vcpu);
5563         kvm_complete_insn_gp(vcpu, err);
5564
5565         return 1;
5566 }
5567
5568 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5569 {
5570         kvm_emulate_wbinvd(vcpu);
5571         return 1;
5572 }
5573
5574 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5575 {
5576         u64 new_bv = kvm_read_edx_eax(vcpu);
5577         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5578
5579         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5580                 skip_emulated_instruction(vcpu);
5581         return 1;
5582 }
5583
5584 static int handle_xsaves(struct kvm_vcpu *vcpu)
5585 {
5586         skip_emulated_instruction(vcpu);
5587         WARN(1, "this should never happen\n");
5588         return 1;
5589 }
5590
5591 static int handle_xrstors(struct kvm_vcpu *vcpu)
5592 {
5593         skip_emulated_instruction(vcpu);
5594         WARN(1, "this should never happen\n");
5595         return 1;
5596 }
5597
5598 static int handle_apic_access(struct kvm_vcpu *vcpu)
5599 {
5600         if (likely(fasteoi)) {
5601                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5602                 int access_type, offset;
5603
5604                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5605                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5606                 /*
5607                  * Sane guest uses MOV to write EOI, with written value
5608                  * not cared. So make a short-circuit here by avoiding
5609                  * heavy instruction emulation.
5610                  */
5611                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5612                     (offset == APIC_EOI)) {
5613                         kvm_lapic_set_eoi(vcpu);
5614                         skip_emulated_instruction(vcpu);
5615                         return 1;
5616                 }
5617         }
5618         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5619 }
5620
5621 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5622 {
5623         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5624         int vector = exit_qualification & 0xff;
5625
5626         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5627         kvm_apic_set_eoi_accelerated(vcpu, vector);
5628         return 1;
5629 }
5630
5631 static int handle_apic_write(struct kvm_vcpu *vcpu)
5632 {
5633         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5634         u32 offset = exit_qualification & 0xfff;
5635
5636         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5637         kvm_apic_write_nodecode(vcpu, offset);
5638         return 1;
5639 }
5640
5641 static int handle_task_switch(struct kvm_vcpu *vcpu)
5642 {
5643         struct vcpu_vmx *vmx = to_vmx(vcpu);
5644         unsigned long exit_qualification;
5645         bool has_error_code = false;
5646         u32 error_code = 0;
5647         u16 tss_selector;
5648         int reason, type, idt_v, idt_index;
5649
5650         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5651         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5652         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5653
5654         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5655
5656         reason = (u32)exit_qualification >> 30;
5657         if (reason == TASK_SWITCH_GATE && idt_v) {
5658                 switch (type) {
5659                 case INTR_TYPE_NMI_INTR:
5660                         vcpu->arch.nmi_injected = false;
5661                         vmx_set_nmi_mask(vcpu, true);
5662                         break;
5663                 case INTR_TYPE_EXT_INTR:
5664                 case INTR_TYPE_SOFT_INTR:
5665                         kvm_clear_interrupt_queue(vcpu);
5666                         break;
5667                 case INTR_TYPE_HARD_EXCEPTION:
5668                         if (vmx->idt_vectoring_info &
5669                             VECTORING_INFO_DELIVER_CODE_MASK) {
5670                                 has_error_code = true;
5671                                 error_code =
5672                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5673                         }
5674                         /* fall through */
5675                 case INTR_TYPE_SOFT_EXCEPTION:
5676                         kvm_clear_exception_queue(vcpu);
5677                         break;
5678                 default:
5679                         break;
5680                 }
5681         }
5682         tss_selector = exit_qualification;
5683
5684         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5685                        type != INTR_TYPE_EXT_INTR &&
5686                        type != INTR_TYPE_NMI_INTR))
5687                 skip_emulated_instruction(vcpu);
5688
5689         if (kvm_task_switch(vcpu, tss_selector,
5690                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5691                             has_error_code, error_code) == EMULATE_FAIL) {
5692                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5693                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5694                 vcpu->run->internal.ndata = 0;
5695                 return 0;
5696         }
5697
5698         /* clear all local breakpoint enable flags */
5699         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5700
5701         /*
5702          * TODO: What about debug traps on tss switch?
5703          *       Are we supposed to inject them and update dr6?
5704          */
5705
5706         return 1;
5707 }
5708
5709 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5710 {
5711         unsigned long exit_qualification;
5712         gpa_t gpa;
5713         u32 error_code;
5714         int gla_validity;
5715
5716         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5717
5718         gla_validity = (exit_qualification >> 7) & 0x3;
5719         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5720                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5721                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5722                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5723                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5724                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5725                         (long unsigned int)exit_qualification);
5726                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5727                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5728                 return 0;
5729         }
5730
5731         /*
5732          * EPT violation happened while executing iret from NMI,
5733          * "blocked by NMI" bit has to be set before next VM entry.
5734          * There are errata that may cause this bit to not be set:
5735          * AAK134, BY25.
5736          */
5737         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5738                         cpu_has_virtual_nmis() &&
5739                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5740                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5741
5742         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5743         trace_kvm_page_fault(gpa, exit_qualification);
5744
5745         /* It is a write fault? */
5746         error_code = exit_qualification & PFERR_WRITE_MASK;
5747         /* It is a fetch fault? */
5748         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5749         /* ept page table is present? */
5750         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5751
5752         vcpu->arch.exit_qualification = exit_qualification;
5753
5754         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5755 }
5756
5757 static u64 ept_rsvd_mask(u64 spte, int level)
5758 {
5759         int i;
5760         u64 mask = 0;
5761
5762         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5763                 mask |= (1ULL << i);
5764
5765         if (level == 4)
5766                 /* bits 7:3 reserved */
5767                 mask |= 0xf8;
5768         else if (spte & (1ULL << 7))
5769                 /*
5770                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5771                  * level == 1 if the hypervisor is using the ignored bit 7.
5772                  */
5773                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5774         else if (level > 1)
5775                 /* bits 6:3 reserved */
5776                 mask |= 0x78;
5777
5778         return mask;
5779 }
5780
5781 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5782                                        int level)
5783 {
5784         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5785
5786         /* 010b (write-only) */
5787         WARN_ON((spte & 0x7) == 0x2);
5788
5789         /* 110b (write/execute) */
5790         WARN_ON((spte & 0x7) == 0x6);
5791
5792         /* 100b (execute-only) and value not supported by logical processor */
5793         if (!cpu_has_vmx_ept_execute_only())
5794                 WARN_ON((spte & 0x7) == 0x4);
5795
5796         /* not 000b */
5797         if ((spte & 0x7)) {
5798                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5799
5800                 if (rsvd_bits != 0) {
5801                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5802                                          __func__, rsvd_bits);
5803                         WARN_ON(1);
5804                 }
5805
5806                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5807                 if ((rsvd_bits & 0x38) == 0) {
5808                         u64 ept_mem_type = (spte & 0x38) >> 3;
5809
5810                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5811                             ept_mem_type == 7) {
5812                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5813                                                 __func__, ept_mem_type);
5814                                 WARN_ON(1);
5815                         }
5816                 }
5817         }
5818 }
5819
5820 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5821 {
5822         u64 sptes[4];
5823         int nr_sptes, i, ret;
5824         gpa_t gpa;
5825
5826         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5827         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5828                 skip_emulated_instruction(vcpu);
5829                 return 1;
5830         }
5831
5832         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5833         if (likely(ret == RET_MMIO_PF_EMULATE))
5834                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5835                                               EMULATE_DONE;
5836
5837         if (unlikely(ret == RET_MMIO_PF_INVALID))
5838                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5839
5840         if (unlikely(ret == RET_MMIO_PF_RETRY))
5841                 return 1;
5842
5843         /* It is the real ept misconfig */
5844         printk(KERN_ERR "EPT: Misconfiguration.\n");
5845         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5846
5847         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5848
5849         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5850                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5851
5852         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5853         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5854
5855         return 0;
5856 }
5857
5858 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5859 {
5860         u32 cpu_based_vm_exec_control;
5861
5862         /* clear pending NMI */
5863         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5864         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5865         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5866         ++vcpu->stat.nmi_window_exits;
5867         kvm_make_request(KVM_REQ_EVENT, vcpu);
5868
5869         return 1;
5870 }
5871
5872 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5873 {
5874         struct vcpu_vmx *vmx = to_vmx(vcpu);
5875         enum emulation_result err = EMULATE_DONE;
5876         int ret = 1;
5877         u32 cpu_exec_ctrl;
5878         bool intr_window_requested;
5879         unsigned count = 130;
5880
5881         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5882         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5883
5884         while (vmx->emulation_required && count-- != 0) {
5885                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5886                         return handle_interrupt_window(&vmx->vcpu);
5887
5888                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5889                         return 1;
5890
5891                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5892
5893                 if (err == EMULATE_USER_EXIT) {
5894                         ++vcpu->stat.mmio_exits;
5895                         ret = 0;
5896                         goto out;
5897                 }
5898
5899                 if (err != EMULATE_DONE) {
5900                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5901                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5902                         vcpu->run->internal.ndata = 0;
5903                         return 0;
5904                 }
5905
5906                 if (vcpu->arch.halt_request) {
5907                         vcpu->arch.halt_request = 0;
5908                         ret = kvm_vcpu_halt(vcpu);
5909                         goto out;
5910                 }
5911
5912                 if (signal_pending(current))
5913                         goto out;
5914                 if (need_resched())
5915                         schedule();
5916         }
5917
5918 out:
5919         return ret;
5920 }
5921
5922 static int __grow_ple_window(int val)
5923 {
5924         if (ple_window_grow < 1)
5925                 return ple_window;
5926
5927         val = min(val, ple_window_actual_max);
5928
5929         if (ple_window_grow < ple_window)
5930                 val *= ple_window_grow;
5931         else
5932                 val += ple_window_grow;
5933
5934         return val;
5935 }
5936
5937 static int __shrink_ple_window(int val, int modifier, int minimum)
5938 {
5939         if (modifier < 1)
5940                 return ple_window;
5941
5942         if (modifier < ple_window)
5943                 val /= modifier;
5944         else
5945                 val -= modifier;
5946
5947         return max(val, minimum);
5948 }
5949
5950 static void grow_ple_window(struct kvm_vcpu *vcpu)
5951 {
5952         struct vcpu_vmx *vmx = to_vmx(vcpu);
5953         int old = vmx->ple_window;
5954
5955         vmx->ple_window = __grow_ple_window(old);
5956
5957         if (vmx->ple_window != old)
5958                 vmx->ple_window_dirty = true;
5959
5960         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5961 }
5962
5963 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5964 {
5965         struct vcpu_vmx *vmx = to_vmx(vcpu);
5966         int old = vmx->ple_window;
5967
5968         vmx->ple_window = __shrink_ple_window(old,
5969                                               ple_window_shrink, ple_window);
5970
5971         if (vmx->ple_window != old)
5972                 vmx->ple_window_dirty = true;
5973
5974         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5975 }
5976
5977 /*
5978  * ple_window_actual_max is computed to be one grow_ple_window() below
5979  * ple_window_max. (See __grow_ple_window for the reason.)
5980  * This prevents overflows, because ple_window_max is int.
5981  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5982  * this process.
5983  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5984  */
5985 static void update_ple_window_actual_max(void)
5986 {
5987         ple_window_actual_max =
5988                         __shrink_ple_window(max(ple_window_max, ple_window),
5989                                             ple_window_grow, INT_MIN);
5990 }
5991
5992 static __init int hardware_setup(void)
5993 {
5994         int r = -ENOMEM, i, msr;
5995
5996         rdmsrl_safe(MSR_EFER, &host_efer);
5997
5998         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5999                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6000
6001         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6002         if (!vmx_io_bitmap_a)
6003                 return r;
6004
6005         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6006         if (!vmx_io_bitmap_b)
6007                 goto out;
6008
6009         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6010         if (!vmx_msr_bitmap_legacy)
6011                 goto out1;
6012
6013         vmx_msr_bitmap_legacy_x2apic =
6014                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6015         if (!vmx_msr_bitmap_legacy_x2apic)
6016                 goto out2;
6017
6018         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6019         if (!vmx_msr_bitmap_longmode)
6020                 goto out3;
6021
6022         vmx_msr_bitmap_longmode_x2apic =
6023                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6024         if (!vmx_msr_bitmap_longmode_x2apic)
6025                 goto out4;
6026
6027         if (nested) {
6028                 vmx_msr_bitmap_nested =
6029                         (unsigned long *)__get_free_page(GFP_KERNEL);
6030                 if (!vmx_msr_bitmap_nested)
6031                         goto out5;
6032         }
6033
6034         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6035         if (!vmx_vmread_bitmap)
6036                 goto out6;
6037
6038         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6039         if (!vmx_vmwrite_bitmap)
6040                 goto out7;
6041
6042         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6043         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6044
6045         /*
6046          * Allow direct access to the PC debug port (it is often used for I/O
6047          * delays, but the vmexits simply slow things down).
6048          */
6049         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6050         clear_bit(0x80, vmx_io_bitmap_a);
6051
6052         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6053
6054         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6055         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6056         if (nested)
6057                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6058
6059         if (setup_vmcs_config(&vmcs_config) < 0) {
6060                 r = -EIO;
6061                 goto out8;
6062         }
6063
6064         if (boot_cpu_has(X86_FEATURE_NX))
6065                 kvm_enable_efer_bits(EFER_NX);
6066
6067         if (!cpu_has_vmx_vpid())
6068                 enable_vpid = 0;
6069         if (!cpu_has_vmx_shadow_vmcs())
6070                 enable_shadow_vmcs = 0;
6071         if (enable_shadow_vmcs)
6072                 init_vmcs_shadow_fields();
6073
6074         if (!cpu_has_vmx_ept() ||
6075             !cpu_has_vmx_ept_4levels()) {
6076                 enable_ept = 0;
6077                 enable_unrestricted_guest = 0;
6078                 enable_ept_ad_bits = 0;
6079         }
6080
6081         if (!cpu_has_vmx_ept_ad_bits())
6082                 enable_ept_ad_bits = 0;
6083
6084         if (!cpu_has_vmx_unrestricted_guest())
6085                 enable_unrestricted_guest = 0;
6086
6087         if (!cpu_has_vmx_flexpriority())
6088                 flexpriority_enabled = 0;
6089
6090         /*
6091          * set_apic_access_page_addr() is used to reload apic access
6092          * page upon invalidation.  No need to do anything if not
6093          * using the APIC_ACCESS_ADDR VMCS field.
6094          */
6095         if (!flexpriority_enabled)
6096                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6097
6098         if (!cpu_has_vmx_tpr_shadow())
6099                 kvm_x86_ops->update_cr8_intercept = NULL;
6100
6101         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6102                 kvm_disable_largepages();
6103
6104         if (!cpu_has_vmx_ple())
6105                 ple_gap = 0;
6106
6107         if (!cpu_has_vmx_apicv())
6108                 enable_apicv = 0;
6109
6110         if (enable_apicv)
6111                 kvm_x86_ops->update_cr8_intercept = NULL;
6112         else {
6113                 kvm_x86_ops->hwapic_irr_update = NULL;
6114                 kvm_x86_ops->hwapic_isr_update = NULL;
6115                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6116                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6117         }
6118
6119         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6120         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6121         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6122         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6123         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6124         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6125         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6126
6127         memcpy(vmx_msr_bitmap_legacy_x2apic,
6128                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6129         memcpy(vmx_msr_bitmap_longmode_x2apic,
6130                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6131
6132         if (enable_apicv) {
6133                 for (msr = 0x800; msr <= 0x8ff; msr++)
6134                         vmx_disable_intercept_msr_read_x2apic(msr);
6135
6136                 /* According SDM, in x2apic mode, the whole id reg is used.
6137                  * But in KVM, it only use the highest eight bits. Need to
6138                  * intercept it */
6139                 vmx_enable_intercept_msr_read_x2apic(0x802);
6140                 /* TMCCT */
6141                 vmx_enable_intercept_msr_read_x2apic(0x839);
6142                 /* TPR */
6143                 vmx_disable_intercept_msr_write_x2apic(0x808);
6144                 /* EOI */
6145                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6146                 /* SELF-IPI */
6147                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6148         }
6149
6150         if (enable_ept) {
6151                 kvm_mmu_set_mask_ptes(0ull,
6152                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6153                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6154                         0ull, VMX_EPT_EXECUTABLE_MASK);
6155                 ept_set_mmio_spte_mask();
6156                 kvm_enable_tdp();
6157         } else
6158                 kvm_disable_tdp();
6159
6160         update_ple_window_actual_max();
6161
6162         /*
6163          * Only enable PML when hardware supports PML feature, and both EPT
6164          * and EPT A/D bit features are enabled -- PML depends on them to work.
6165          */
6166         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6167                 enable_pml = 0;
6168
6169         if (!enable_pml) {
6170                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6171                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6172                 kvm_x86_ops->flush_log_dirty = NULL;
6173                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6174         }
6175
6176         return alloc_kvm_area();
6177
6178 out8:
6179         free_page((unsigned long)vmx_vmwrite_bitmap);
6180 out7:
6181         free_page((unsigned long)vmx_vmread_bitmap);
6182 out6:
6183         if (nested)
6184                 free_page((unsigned long)vmx_msr_bitmap_nested);
6185 out5:
6186         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6187 out4:
6188         free_page((unsigned long)vmx_msr_bitmap_longmode);
6189 out3:
6190         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6191 out2:
6192         free_page((unsigned long)vmx_msr_bitmap_legacy);
6193 out1:
6194         free_page((unsigned long)vmx_io_bitmap_b);
6195 out:
6196         free_page((unsigned long)vmx_io_bitmap_a);
6197
6198     return r;
6199 }
6200
6201 static __exit void hardware_unsetup(void)
6202 {
6203         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6204         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6205         free_page((unsigned long)vmx_msr_bitmap_legacy);
6206         free_page((unsigned long)vmx_msr_bitmap_longmode);
6207         free_page((unsigned long)vmx_io_bitmap_b);
6208         free_page((unsigned long)vmx_io_bitmap_a);
6209         free_page((unsigned long)vmx_vmwrite_bitmap);
6210         free_page((unsigned long)vmx_vmread_bitmap);
6211         if (nested)
6212                 free_page((unsigned long)vmx_msr_bitmap_nested);
6213
6214         free_kvm_area();
6215 }
6216
6217 /*
6218  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6219  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6220  */
6221 static int handle_pause(struct kvm_vcpu *vcpu)
6222 {
6223         if (ple_gap)
6224                 grow_ple_window(vcpu);
6225
6226         skip_emulated_instruction(vcpu);
6227         kvm_vcpu_on_spin(vcpu);
6228
6229         return 1;
6230 }
6231
6232 static int handle_nop(struct kvm_vcpu *vcpu)
6233 {
6234         skip_emulated_instruction(vcpu);
6235         return 1;
6236 }
6237
6238 static int handle_mwait(struct kvm_vcpu *vcpu)
6239 {
6240         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6241         return handle_nop(vcpu);
6242 }
6243
6244 static int handle_monitor(struct kvm_vcpu *vcpu)
6245 {
6246         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6247         return handle_nop(vcpu);
6248 }
6249
6250 /*
6251  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6252  * We could reuse a single VMCS for all the L2 guests, but we also want the
6253  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6254  * allows keeping them loaded on the processor, and in the future will allow
6255  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6256  * every entry if they never change.
6257  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6258  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6259  *
6260  * The following functions allocate and free a vmcs02 in this pool.
6261  */
6262
6263 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6264 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6265 {
6266         struct vmcs02_list *item;
6267         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6268                 if (item->vmptr == vmx->nested.current_vmptr) {
6269                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6270                         return &item->vmcs02;
6271                 }
6272
6273         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6274                 /* Recycle the least recently used VMCS. */
6275                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6276                         struct vmcs02_list, list);
6277                 item->vmptr = vmx->nested.current_vmptr;
6278                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6279                 return &item->vmcs02;
6280         }
6281
6282         /* Create a new VMCS */
6283         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6284         if (!item)
6285                 return NULL;
6286         item->vmcs02.vmcs = alloc_vmcs();
6287         if (!item->vmcs02.vmcs) {
6288                 kfree(item);
6289                 return NULL;
6290         }
6291         loaded_vmcs_init(&item->vmcs02);
6292         item->vmptr = vmx->nested.current_vmptr;
6293         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6294         vmx->nested.vmcs02_num++;
6295         return &item->vmcs02;
6296 }
6297
6298 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6299 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6300 {
6301         struct vmcs02_list *item;
6302         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6303                 if (item->vmptr == vmptr) {
6304                         free_loaded_vmcs(&item->vmcs02);
6305                         list_del(&item->list);
6306                         kfree(item);
6307                         vmx->nested.vmcs02_num--;
6308                         return;
6309                 }
6310 }
6311
6312 /*
6313  * Free all VMCSs saved for this vcpu, except the one pointed by
6314  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6315  * must be &vmx->vmcs01.
6316  */
6317 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6318 {
6319         struct vmcs02_list *item, *n;
6320
6321         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6322         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6323                 /*
6324                  * Something will leak if the above WARN triggers.  Better than
6325                  * a use-after-free.
6326                  */
6327                 if (vmx->loaded_vmcs == &item->vmcs02)
6328                         continue;
6329
6330                 free_loaded_vmcs(&item->vmcs02);
6331                 list_del(&item->list);
6332                 kfree(item);
6333                 vmx->nested.vmcs02_num--;
6334         }
6335 }
6336
6337 /*
6338  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6339  * set the success or error code of an emulated VMX instruction, as specified
6340  * by Vol 2B, VMX Instruction Reference, "Conventions".
6341  */
6342 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6343 {
6344         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6345                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6346                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6347 }
6348
6349 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6350 {
6351         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6352                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6353                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6354                         | X86_EFLAGS_CF);
6355 }
6356
6357 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6358                                         u32 vm_instruction_error)
6359 {
6360         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6361                 /*
6362                  * failValid writes the error number to the current VMCS, which
6363                  * can't be done there isn't a current VMCS.
6364                  */
6365                 nested_vmx_failInvalid(vcpu);
6366                 return;
6367         }
6368         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6369                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6370                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6371                         | X86_EFLAGS_ZF);
6372         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6373         /*
6374          * We don't need to force a shadow sync because
6375          * VM_INSTRUCTION_ERROR is not shadowed
6376          */
6377 }
6378
6379 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6380 {
6381         /* TODO: not to reset guest simply here. */
6382         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6383         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6384 }
6385
6386 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6387 {
6388         struct vcpu_vmx *vmx =
6389                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6390
6391         vmx->nested.preemption_timer_expired = true;
6392         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6393         kvm_vcpu_kick(&vmx->vcpu);
6394
6395         return HRTIMER_NORESTART;
6396 }
6397
6398 /*
6399  * Decode the memory-address operand of a vmx instruction, as recorded on an
6400  * exit caused by such an instruction (run by a guest hypervisor).
6401  * On success, returns 0. When the operand is invalid, returns 1 and throws
6402  * #UD or #GP.
6403  */
6404 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6405                                  unsigned long exit_qualification,
6406                                  u32 vmx_instruction_info, gva_t *ret)
6407 {
6408         /*
6409          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6410          * Execution", on an exit, vmx_instruction_info holds most of the
6411          * addressing components of the operand. Only the displacement part
6412          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6413          * For how an actual address is calculated from all these components,
6414          * refer to Vol. 1, "Operand Addressing".
6415          */
6416         int  scaling = vmx_instruction_info & 3;
6417         int  addr_size = (vmx_instruction_info >> 7) & 7;
6418         bool is_reg = vmx_instruction_info & (1u << 10);
6419         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6420         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6421         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6422         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6423         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6424
6425         if (is_reg) {
6426                 kvm_queue_exception(vcpu, UD_VECTOR);
6427                 return 1;
6428         }
6429
6430         /* Addr = segment_base + offset */
6431         /* offset = base + [index * scale] + displacement */
6432         *ret = vmx_get_segment_base(vcpu, seg_reg);
6433         if (base_is_valid)
6434                 *ret += kvm_register_read(vcpu, base_reg);
6435         if (index_is_valid)
6436                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6437         *ret += exit_qualification; /* holds the displacement */
6438
6439         if (addr_size == 1) /* 32 bit */
6440                 *ret &= 0xffffffff;
6441
6442         /*
6443          * TODO: throw #GP (and return 1) in various cases that the VM*
6444          * instructions require it - e.g., offset beyond segment limit,
6445          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6446          * address, and so on. Currently these are not checked.
6447          */
6448         return 0;
6449 }
6450
6451 /*
6452  * This function performs the various checks including
6453  * - if it's 4KB aligned
6454  * - No bits beyond the physical address width are set
6455  * - Returns 0 on success or else 1
6456  * (Intel SDM Section 30.3)
6457  */
6458 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6459                                   gpa_t *vmpointer)
6460 {
6461         gva_t gva;
6462         gpa_t vmptr;
6463         struct x86_exception e;
6464         struct page *page;
6465         struct vcpu_vmx *vmx = to_vmx(vcpu);
6466         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6467
6468         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6469                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6470                 return 1;
6471
6472         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6473                                 sizeof(vmptr), &e)) {
6474                 kvm_inject_page_fault(vcpu, &e);
6475                 return 1;
6476         }
6477
6478         switch (exit_reason) {
6479         case EXIT_REASON_VMON:
6480                 /*
6481                  * SDM 3: 24.11.5
6482                  * The first 4 bytes of VMXON region contain the supported
6483                  * VMCS revision identifier
6484                  *
6485                  * Note - IA32_VMX_BASIC[48] will never be 1
6486                  * for the nested case;
6487                  * which replaces physical address width with 32
6488                  *
6489                  */
6490                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6491                         nested_vmx_failInvalid(vcpu);
6492                         skip_emulated_instruction(vcpu);
6493                         return 1;
6494                 }
6495
6496                 page = nested_get_page(vcpu, vmptr);
6497                 if (page == NULL ||
6498                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6499                         nested_vmx_failInvalid(vcpu);
6500                         kunmap(page);
6501                         skip_emulated_instruction(vcpu);
6502                         return 1;
6503                 }
6504                 kunmap(page);
6505                 vmx->nested.vmxon_ptr = vmptr;
6506                 break;
6507         case EXIT_REASON_VMCLEAR:
6508                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6509                         nested_vmx_failValid(vcpu,
6510                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6511                         skip_emulated_instruction(vcpu);
6512                         return 1;
6513                 }
6514
6515                 if (vmptr == vmx->nested.vmxon_ptr) {
6516                         nested_vmx_failValid(vcpu,
6517                                              VMXERR_VMCLEAR_VMXON_POINTER);
6518                         skip_emulated_instruction(vcpu);
6519                         return 1;
6520                 }
6521                 break;
6522         case EXIT_REASON_VMPTRLD:
6523                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6524                         nested_vmx_failValid(vcpu,
6525                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6526                         skip_emulated_instruction(vcpu);
6527                         return 1;
6528                 }
6529
6530                 if (vmptr == vmx->nested.vmxon_ptr) {
6531                         nested_vmx_failValid(vcpu,
6532                                              VMXERR_VMCLEAR_VMXON_POINTER);
6533                         skip_emulated_instruction(vcpu);
6534                         return 1;
6535                 }
6536                 break;
6537         default:
6538                 return 1; /* shouldn't happen */
6539         }
6540
6541         if (vmpointer)
6542                 *vmpointer = vmptr;
6543         return 0;
6544 }
6545
6546 /*
6547  * Emulate the VMXON instruction.
6548  * Currently, we just remember that VMX is active, and do not save or even
6549  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6550  * do not currently need to store anything in that guest-allocated memory
6551  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6552  * argument is different from the VMXON pointer (which the spec says they do).
6553  */
6554 static int handle_vmon(struct kvm_vcpu *vcpu)
6555 {
6556         struct kvm_segment cs;
6557         struct vcpu_vmx *vmx = to_vmx(vcpu);
6558         struct vmcs *shadow_vmcs;
6559         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6560                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6561
6562         /* The Intel VMX Instruction Reference lists a bunch of bits that
6563          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6564          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6565          * Otherwise, we should fail with #UD. We test these now:
6566          */
6567         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6568             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6569             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6570                 kvm_queue_exception(vcpu, UD_VECTOR);
6571                 return 1;
6572         }
6573
6574         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6575         if (is_long_mode(vcpu) && !cs.l) {
6576                 kvm_queue_exception(vcpu, UD_VECTOR);
6577                 return 1;
6578         }
6579
6580         if (vmx_get_cpl(vcpu)) {
6581                 kvm_inject_gp(vcpu, 0);
6582                 return 1;
6583         }
6584
6585         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6586                 return 1;
6587
6588         if (vmx->nested.vmxon) {
6589                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6590                 skip_emulated_instruction(vcpu);
6591                 return 1;
6592         }
6593
6594         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6595                         != VMXON_NEEDED_FEATURES) {
6596                 kvm_inject_gp(vcpu, 0);
6597                 return 1;
6598         }
6599
6600         if (enable_shadow_vmcs) {
6601                 shadow_vmcs = alloc_vmcs();
6602                 if (!shadow_vmcs)
6603                         return -ENOMEM;
6604                 /* mark vmcs as shadow */
6605                 shadow_vmcs->revision_id |= (1u << 31);
6606                 /* init shadow vmcs */
6607                 vmcs_clear(shadow_vmcs);
6608                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6609         }
6610
6611         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6612         vmx->nested.vmcs02_num = 0;
6613
6614         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6615                      HRTIMER_MODE_REL);
6616         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6617
6618         vmx->nested.vmxon = true;
6619
6620         skip_emulated_instruction(vcpu);
6621         nested_vmx_succeed(vcpu);
6622         return 1;
6623 }
6624
6625 /*
6626  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6627  * for running VMX instructions (except VMXON, whose prerequisites are
6628  * slightly different). It also specifies what exception to inject otherwise.
6629  */
6630 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6631 {
6632         struct kvm_segment cs;
6633         struct vcpu_vmx *vmx = to_vmx(vcpu);
6634
6635         if (!vmx->nested.vmxon) {
6636                 kvm_queue_exception(vcpu, UD_VECTOR);
6637                 return 0;
6638         }
6639
6640         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6641         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6642             (is_long_mode(vcpu) && !cs.l)) {
6643                 kvm_queue_exception(vcpu, UD_VECTOR);
6644                 return 0;
6645         }
6646
6647         if (vmx_get_cpl(vcpu)) {
6648                 kvm_inject_gp(vcpu, 0);
6649                 return 0;
6650         }
6651
6652         return 1;
6653 }
6654
6655 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6656 {
6657         u32 exec_control;
6658         if (vmx->nested.current_vmptr == -1ull)
6659                 return;
6660
6661         /* current_vmptr and current_vmcs12 are always set/reset together */
6662         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6663                 return;
6664
6665         if (enable_shadow_vmcs) {
6666                 /* copy to memory all shadowed fields in case
6667                    they were modified */
6668                 copy_shadow_to_vmcs12(vmx);
6669                 vmx->nested.sync_shadow_vmcs = false;
6670                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6671                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6672                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6673                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6674         }
6675         vmx->nested.posted_intr_nv = -1;
6676         kunmap(vmx->nested.current_vmcs12_page);
6677         nested_release_page(vmx->nested.current_vmcs12_page);
6678         vmx->nested.current_vmptr = -1ull;
6679         vmx->nested.current_vmcs12 = NULL;
6680 }
6681
6682 /*
6683  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6684  * just stops using VMX.
6685  */
6686 static void free_nested(struct vcpu_vmx *vmx)
6687 {
6688         if (!vmx->nested.vmxon)
6689                 return;
6690
6691         vmx->nested.vmxon = false;
6692         nested_release_vmcs12(vmx);
6693         if (enable_shadow_vmcs)
6694                 free_vmcs(vmx->nested.current_shadow_vmcs);
6695         /* Unpin physical memory we referred to in current vmcs02 */
6696         if (vmx->nested.apic_access_page) {
6697                 nested_release_page(vmx->nested.apic_access_page);
6698                 vmx->nested.apic_access_page = NULL;
6699         }
6700         if (vmx->nested.virtual_apic_page) {
6701                 nested_release_page(vmx->nested.virtual_apic_page);
6702                 vmx->nested.virtual_apic_page = NULL;
6703         }
6704         if (vmx->nested.pi_desc_page) {
6705                 kunmap(vmx->nested.pi_desc_page);
6706                 nested_release_page(vmx->nested.pi_desc_page);
6707                 vmx->nested.pi_desc_page = NULL;
6708                 vmx->nested.pi_desc = NULL;
6709         }
6710
6711         nested_free_all_saved_vmcss(vmx);
6712 }
6713
6714 /* Emulate the VMXOFF instruction */
6715 static int handle_vmoff(struct kvm_vcpu *vcpu)
6716 {
6717         if (!nested_vmx_check_permission(vcpu))
6718                 return 1;
6719         free_nested(to_vmx(vcpu));
6720         skip_emulated_instruction(vcpu);
6721         nested_vmx_succeed(vcpu);
6722         return 1;
6723 }
6724
6725 /* Emulate the VMCLEAR instruction */
6726 static int handle_vmclear(struct kvm_vcpu *vcpu)
6727 {
6728         struct vcpu_vmx *vmx = to_vmx(vcpu);
6729         gpa_t vmptr;
6730         struct vmcs12 *vmcs12;
6731         struct page *page;
6732
6733         if (!nested_vmx_check_permission(vcpu))
6734                 return 1;
6735
6736         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6737                 return 1;
6738
6739         if (vmptr == vmx->nested.current_vmptr)
6740                 nested_release_vmcs12(vmx);
6741
6742         page = nested_get_page(vcpu, vmptr);
6743         if (page == NULL) {
6744                 /*
6745                  * For accurate processor emulation, VMCLEAR beyond available
6746                  * physical memory should do nothing at all. However, it is
6747                  * possible that a nested vmx bug, not a guest hypervisor bug,
6748                  * resulted in this case, so let's shut down before doing any
6749                  * more damage:
6750                  */
6751                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6752                 return 1;
6753         }
6754         vmcs12 = kmap(page);
6755         vmcs12->launch_state = 0;
6756         kunmap(page);
6757         nested_release_page(page);
6758
6759         nested_free_vmcs02(vmx, vmptr);
6760
6761         skip_emulated_instruction(vcpu);
6762         nested_vmx_succeed(vcpu);
6763         return 1;
6764 }
6765
6766 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6767
6768 /* Emulate the VMLAUNCH instruction */
6769 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6770 {
6771         return nested_vmx_run(vcpu, true);
6772 }
6773
6774 /* Emulate the VMRESUME instruction */
6775 static int handle_vmresume(struct kvm_vcpu *vcpu)
6776 {
6777
6778         return nested_vmx_run(vcpu, false);
6779 }
6780
6781 enum vmcs_field_type {
6782         VMCS_FIELD_TYPE_U16 = 0,
6783         VMCS_FIELD_TYPE_U64 = 1,
6784         VMCS_FIELD_TYPE_U32 = 2,
6785         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6786 };
6787
6788 static inline int vmcs_field_type(unsigned long field)
6789 {
6790         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6791                 return VMCS_FIELD_TYPE_U32;
6792         return (field >> 13) & 0x3 ;
6793 }
6794
6795 static inline int vmcs_field_readonly(unsigned long field)
6796 {
6797         return (((field >> 10) & 0x3) == 1);
6798 }
6799
6800 /*
6801  * Read a vmcs12 field. Since these can have varying lengths and we return
6802  * one type, we chose the biggest type (u64) and zero-extend the return value
6803  * to that size. Note that the caller, handle_vmread, might need to use only
6804  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6805  * 64-bit fields are to be returned).
6806  */
6807 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6808                                   unsigned long field, u64 *ret)
6809 {
6810         short offset = vmcs_field_to_offset(field);
6811         char *p;
6812
6813         if (offset < 0)
6814                 return offset;
6815
6816         p = ((char *)(get_vmcs12(vcpu))) + offset;
6817
6818         switch (vmcs_field_type(field)) {
6819         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6820                 *ret = *((natural_width *)p);
6821                 return 0;
6822         case VMCS_FIELD_TYPE_U16:
6823                 *ret = *((u16 *)p);
6824                 return 0;
6825         case VMCS_FIELD_TYPE_U32:
6826                 *ret = *((u32 *)p);
6827                 return 0;
6828         case VMCS_FIELD_TYPE_U64:
6829                 *ret = *((u64 *)p);
6830                 return 0;
6831         default:
6832                 WARN_ON(1);
6833                 return -ENOENT;
6834         }
6835 }
6836
6837
6838 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6839                                    unsigned long field, u64 field_value){
6840         short offset = vmcs_field_to_offset(field);
6841         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6842         if (offset < 0)
6843                 return offset;
6844
6845         switch (vmcs_field_type(field)) {
6846         case VMCS_FIELD_TYPE_U16:
6847                 *(u16 *)p = field_value;
6848                 return 0;
6849         case VMCS_FIELD_TYPE_U32:
6850                 *(u32 *)p = field_value;
6851                 return 0;
6852         case VMCS_FIELD_TYPE_U64:
6853                 *(u64 *)p = field_value;
6854                 return 0;
6855         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6856                 *(natural_width *)p = field_value;
6857                 return 0;
6858         default:
6859                 WARN_ON(1);
6860                 return -ENOENT;
6861         }
6862
6863 }
6864
6865 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6866 {
6867         int i;
6868         unsigned long field;
6869         u64 field_value;
6870         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6871         const unsigned long *fields = shadow_read_write_fields;
6872         const int num_fields = max_shadow_read_write_fields;
6873
6874         preempt_disable();
6875
6876         vmcs_load(shadow_vmcs);
6877
6878         for (i = 0; i < num_fields; i++) {
6879                 field = fields[i];
6880                 switch (vmcs_field_type(field)) {
6881                 case VMCS_FIELD_TYPE_U16:
6882                         field_value = vmcs_read16(field);
6883                         break;
6884                 case VMCS_FIELD_TYPE_U32:
6885                         field_value = vmcs_read32(field);
6886                         break;
6887                 case VMCS_FIELD_TYPE_U64:
6888                         field_value = vmcs_read64(field);
6889                         break;
6890                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6891                         field_value = vmcs_readl(field);
6892                         break;
6893                 default:
6894                         WARN_ON(1);
6895                         continue;
6896                 }
6897                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6898         }
6899
6900         vmcs_clear(shadow_vmcs);
6901         vmcs_load(vmx->loaded_vmcs->vmcs);
6902
6903         preempt_enable();
6904 }
6905
6906 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6907 {
6908         const unsigned long *fields[] = {
6909                 shadow_read_write_fields,
6910                 shadow_read_only_fields
6911         };
6912         const int max_fields[] = {
6913                 max_shadow_read_write_fields,
6914                 max_shadow_read_only_fields
6915         };
6916         int i, q;
6917         unsigned long field;
6918         u64 field_value = 0;
6919         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6920
6921         vmcs_load(shadow_vmcs);
6922
6923         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6924                 for (i = 0; i < max_fields[q]; i++) {
6925                         field = fields[q][i];
6926                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6927
6928                         switch (vmcs_field_type(field)) {
6929                         case VMCS_FIELD_TYPE_U16:
6930                                 vmcs_write16(field, (u16)field_value);
6931                                 break;
6932                         case VMCS_FIELD_TYPE_U32:
6933                                 vmcs_write32(field, (u32)field_value);
6934                                 break;
6935                         case VMCS_FIELD_TYPE_U64:
6936                                 vmcs_write64(field, (u64)field_value);
6937                                 break;
6938                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6939                                 vmcs_writel(field, (long)field_value);
6940                                 break;
6941                         default:
6942                                 WARN_ON(1);
6943                                 break;
6944                         }
6945                 }
6946         }
6947
6948         vmcs_clear(shadow_vmcs);
6949         vmcs_load(vmx->loaded_vmcs->vmcs);
6950 }
6951
6952 /*
6953  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6954  * used before) all generate the same failure when it is missing.
6955  */
6956 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6957 {
6958         struct vcpu_vmx *vmx = to_vmx(vcpu);
6959         if (vmx->nested.current_vmptr == -1ull) {
6960                 nested_vmx_failInvalid(vcpu);
6961                 skip_emulated_instruction(vcpu);
6962                 return 0;
6963         }
6964         return 1;
6965 }
6966
6967 static int handle_vmread(struct kvm_vcpu *vcpu)
6968 {
6969         unsigned long field;
6970         u64 field_value;
6971         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6972         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6973         gva_t gva = 0;
6974
6975         if (!nested_vmx_check_permission(vcpu) ||
6976             !nested_vmx_check_vmcs12(vcpu))
6977                 return 1;
6978
6979         /* Decode instruction info and find the field to read */
6980         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6981         /* Read the field, zero-extended to a u64 field_value */
6982         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6983                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6984                 skip_emulated_instruction(vcpu);
6985                 return 1;
6986         }
6987         /*
6988          * Now copy part of this value to register or memory, as requested.
6989          * Note that the number of bits actually copied is 32 or 64 depending
6990          * on the guest's mode (32 or 64 bit), not on the given field's length.
6991          */
6992         if (vmx_instruction_info & (1u << 10)) {
6993                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6994                         field_value);
6995         } else {
6996                 if (get_vmx_mem_address(vcpu, exit_qualification,
6997                                 vmx_instruction_info, &gva))
6998                         return 1;
6999                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7000                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7001                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7002         }
7003
7004         nested_vmx_succeed(vcpu);
7005         skip_emulated_instruction(vcpu);
7006         return 1;
7007 }
7008
7009
7010 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7011 {
7012         unsigned long field;
7013         gva_t gva;
7014         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7015         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7016         /* The value to write might be 32 or 64 bits, depending on L1's long
7017          * mode, and eventually we need to write that into a field of several
7018          * possible lengths. The code below first zero-extends the value to 64
7019          * bit (field_value), and then copies only the approriate number of
7020          * bits into the vmcs12 field.
7021          */
7022         u64 field_value = 0;
7023         struct x86_exception e;
7024
7025         if (!nested_vmx_check_permission(vcpu) ||
7026             !nested_vmx_check_vmcs12(vcpu))
7027                 return 1;
7028
7029         if (vmx_instruction_info & (1u << 10))
7030                 field_value = kvm_register_readl(vcpu,
7031                         (((vmx_instruction_info) >> 3) & 0xf));
7032         else {
7033                 if (get_vmx_mem_address(vcpu, exit_qualification,
7034                                 vmx_instruction_info, &gva))
7035                         return 1;
7036                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7037                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7038                         kvm_inject_page_fault(vcpu, &e);
7039                         return 1;
7040                 }
7041         }
7042
7043
7044         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7045         if (vmcs_field_readonly(field)) {
7046                 nested_vmx_failValid(vcpu,
7047                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7048                 skip_emulated_instruction(vcpu);
7049                 return 1;
7050         }
7051
7052         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7053                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7054                 skip_emulated_instruction(vcpu);
7055                 return 1;
7056         }
7057
7058         nested_vmx_succeed(vcpu);
7059         skip_emulated_instruction(vcpu);
7060         return 1;
7061 }
7062
7063 /* Emulate the VMPTRLD instruction */
7064 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7065 {
7066         struct vcpu_vmx *vmx = to_vmx(vcpu);
7067         gpa_t vmptr;
7068         u32 exec_control;
7069
7070         if (!nested_vmx_check_permission(vcpu))
7071                 return 1;
7072
7073         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7074                 return 1;
7075
7076         if (vmx->nested.current_vmptr != vmptr) {
7077                 struct vmcs12 *new_vmcs12;
7078                 struct page *page;
7079                 page = nested_get_page(vcpu, vmptr);
7080                 if (page == NULL) {
7081                         nested_vmx_failInvalid(vcpu);
7082                         skip_emulated_instruction(vcpu);
7083                         return 1;
7084                 }
7085                 new_vmcs12 = kmap(page);
7086                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7087                         kunmap(page);
7088                         nested_release_page_clean(page);
7089                         nested_vmx_failValid(vcpu,
7090                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7091                         skip_emulated_instruction(vcpu);
7092                         return 1;
7093                 }
7094
7095                 nested_release_vmcs12(vmx);
7096                 vmx->nested.current_vmptr = vmptr;
7097                 vmx->nested.current_vmcs12 = new_vmcs12;
7098                 vmx->nested.current_vmcs12_page = page;
7099                 if (enable_shadow_vmcs) {
7100                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7101                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7102                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7103                         vmcs_write64(VMCS_LINK_POINTER,
7104                                      __pa(vmx->nested.current_shadow_vmcs));
7105                         vmx->nested.sync_shadow_vmcs = true;
7106                 }
7107         }
7108
7109         nested_vmx_succeed(vcpu);
7110         skip_emulated_instruction(vcpu);
7111         return 1;
7112 }
7113
7114 /* Emulate the VMPTRST instruction */
7115 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7116 {
7117         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7118         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7119         gva_t vmcs_gva;
7120         struct x86_exception e;
7121
7122         if (!nested_vmx_check_permission(vcpu))
7123                 return 1;
7124
7125         if (get_vmx_mem_address(vcpu, exit_qualification,
7126                         vmx_instruction_info, &vmcs_gva))
7127                 return 1;
7128         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7129         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7130                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7131                                  sizeof(u64), &e)) {
7132                 kvm_inject_page_fault(vcpu, &e);
7133                 return 1;
7134         }
7135         nested_vmx_succeed(vcpu);
7136         skip_emulated_instruction(vcpu);
7137         return 1;
7138 }
7139
7140 /* Emulate the INVEPT instruction */
7141 static int handle_invept(struct kvm_vcpu *vcpu)
7142 {
7143         struct vcpu_vmx *vmx = to_vmx(vcpu);
7144         u32 vmx_instruction_info, types;
7145         unsigned long type;
7146         gva_t gva;
7147         struct x86_exception e;
7148         struct {
7149                 u64 eptp, gpa;
7150         } operand;
7151
7152         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7153               SECONDARY_EXEC_ENABLE_EPT) ||
7154             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7155                 kvm_queue_exception(vcpu, UD_VECTOR);
7156                 return 1;
7157         }
7158
7159         if (!nested_vmx_check_permission(vcpu))
7160                 return 1;
7161
7162         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7163                 kvm_queue_exception(vcpu, UD_VECTOR);
7164                 return 1;
7165         }
7166
7167         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7168         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7169
7170         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7171
7172         if (!(types & (1UL << type))) {
7173                 nested_vmx_failValid(vcpu,
7174                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7175                 return 1;
7176         }
7177
7178         /* According to the Intel VMX instruction reference, the memory
7179          * operand is read even if it isn't needed (e.g., for type==global)
7180          */
7181         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7182                         vmx_instruction_info, &gva))
7183                 return 1;
7184         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7185                                 sizeof(operand), &e)) {
7186                 kvm_inject_page_fault(vcpu, &e);
7187                 return 1;
7188         }
7189
7190         switch (type) {
7191         case VMX_EPT_EXTENT_GLOBAL:
7192                 kvm_mmu_sync_roots(vcpu);
7193                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7194                 nested_vmx_succeed(vcpu);
7195                 break;
7196         default:
7197                 /* Trap single context invalidation invept calls */
7198                 BUG_ON(1);
7199                 break;
7200         }
7201
7202         skip_emulated_instruction(vcpu);
7203         return 1;
7204 }
7205
7206 static int handle_invvpid(struct kvm_vcpu *vcpu)
7207 {
7208         kvm_queue_exception(vcpu, UD_VECTOR);
7209         return 1;
7210 }
7211
7212 static int handle_pml_full(struct kvm_vcpu *vcpu)
7213 {
7214         unsigned long exit_qualification;
7215
7216         trace_kvm_pml_full(vcpu->vcpu_id);
7217
7218         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7219
7220         /*
7221          * PML buffer FULL happened while executing iret from NMI,
7222          * "blocked by NMI" bit has to be set before next VM entry.
7223          */
7224         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7225                         cpu_has_virtual_nmis() &&
7226                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7227                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7228                                 GUEST_INTR_STATE_NMI);
7229
7230         /*
7231          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7232          * here.., and there's no userspace involvement needed for PML.
7233          */
7234         return 1;
7235 }
7236
7237 /*
7238  * The exit handlers return 1 if the exit was handled fully and guest execution
7239  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7240  * to be done to userspace and return 0.
7241  */
7242 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7243         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7244         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7245         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7246         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7247         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7248         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7249         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7250         [EXIT_REASON_CPUID]                   = handle_cpuid,
7251         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7252         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7253         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7254         [EXIT_REASON_HLT]                     = handle_halt,
7255         [EXIT_REASON_INVD]                    = handle_invd,
7256         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7257         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7258         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7259         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7260         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7261         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7262         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7263         [EXIT_REASON_VMREAD]                  = handle_vmread,
7264         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7265         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7266         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7267         [EXIT_REASON_VMON]                    = handle_vmon,
7268         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7269         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7270         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7271         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7272         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7273         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7274         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7275         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7276         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7277         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7278         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7279         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7280         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7281         [EXIT_REASON_INVEPT]                  = handle_invept,
7282         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7283         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7284         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7285         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7286 };
7287
7288 static const int kvm_vmx_max_exit_handlers =
7289         ARRAY_SIZE(kvm_vmx_exit_handlers);
7290
7291 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7292                                        struct vmcs12 *vmcs12)
7293 {
7294         unsigned long exit_qualification;
7295         gpa_t bitmap, last_bitmap;
7296         unsigned int port;
7297         int size;
7298         u8 b;
7299
7300         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7301                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7302
7303         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7304
7305         port = exit_qualification >> 16;
7306         size = (exit_qualification & 7) + 1;
7307
7308         last_bitmap = (gpa_t)-1;
7309         b = -1;
7310
7311         while (size > 0) {
7312                 if (port < 0x8000)
7313                         bitmap = vmcs12->io_bitmap_a;
7314                 else if (port < 0x10000)
7315                         bitmap = vmcs12->io_bitmap_b;
7316                 else
7317                         return 1;
7318                 bitmap += (port & 0x7fff) / 8;
7319
7320                 if (last_bitmap != bitmap)
7321                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7322                                 return 1;
7323                 if (b & (1 << (port & 7)))
7324                         return 1;
7325
7326                 port++;
7327                 size--;
7328                 last_bitmap = bitmap;
7329         }
7330
7331         return 0;
7332 }
7333
7334 /*
7335  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7336  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7337  * disinterest in the current event (read or write a specific MSR) by using an
7338  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7339  */
7340 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7341         struct vmcs12 *vmcs12, u32 exit_reason)
7342 {
7343         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7344         gpa_t bitmap;
7345
7346         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7347                 return 1;
7348
7349         /*
7350          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7351          * for the four combinations of read/write and low/high MSR numbers.
7352          * First we need to figure out which of the four to use:
7353          */
7354         bitmap = vmcs12->msr_bitmap;
7355         if (exit_reason == EXIT_REASON_MSR_WRITE)
7356                 bitmap += 2048;
7357         if (msr_index >= 0xc0000000) {
7358                 msr_index -= 0xc0000000;
7359                 bitmap += 1024;
7360         }
7361
7362         /* Then read the msr_index'th bit from this bitmap: */
7363         if (msr_index < 1024*8) {
7364                 unsigned char b;
7365                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7366                         return 1;
7367                 return 1 & (b >> (msr_index & 7));
7368         } else
7369                 return 1; /* let L1 handle the wrong parameter */
7370 }
7371
7372 /*
7373  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7374  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7375  * intercept (via guest_host_mask etc.) the current event.
7376  */
7377 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7378         struct vmcs12 *vmcs12)
7379 {
7380         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7381         int cr = exit_qualification & 15;
7382         int reg = (exit_qualification >> 8) & 15;
7383         unsigned long val = kvm_register_readl(vcpu, reg);
7384
7385         switch ((exit_qualification >> 4) & 3) {
7386         case 0: /* mov to cr */
7387                 switch (cr) {
7388                 case 0:
7389                         if (vmcs12->cr0_guest_host_mask &
7390                             (val ^ vmcs12->cr0_read_shadow))
7391                                 return 1;
7392                         break;
7393                 case 3:
7394                         if ((vmcs12->cr3_target_count >= 1 &&
7395                                         vmcs12->cr3_target_value0 == val) ||
7396                                 (vmcs12->cr3_target_count >= 2 &&
7397                                         vmcs12->cr3_target_value1 == val) ||
7398                                 (vmcs12->cr3_target_count >= 3 &&
7399                                         vmcs12->cr3_target_value2 == val) ||
7400                                 (vmcs12->cr3_target_count >= 4 &&
7401                                         vmcs12->cr3_target_value3 == val))
7402                                 return 0;
7403                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7404                                 return 1;
7405                         break;
7406                 case 4:
7407                         if (vmcs12->cr4_guest_host_mask &
7408                             (vmcs12->cr4_read_shadow ^ val))
7409                                 return 1;
7410                         break;
7411                 case 8:
7412                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7413                                 return 1;
7414                         break;
7415                 }
7416                 break;
7417         case 2: /* clts */
7418                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7419                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7420                         return 1;
7421                 break;
7422         case 1: /* mov from cr */
7423                 switch (cr) {
7424                 case 3:
7425                         if (vmcs12->cpu_based_vm_exec_control &
7426                             CPU_BASED_CR3_STORE_EXITING)
7427                                 return 1;
7428                         break;
7429                 case 8:
7430                         if (vmcs12->cpu_based_vm_exec_control &
7431                             CPU_BASED_CR8_STORE_EXITING)
7432                                 return 1;
7433                         break;
7434                 }
7435                 break;
7436         case 3: /* lmsw */
7437                 /*
7438                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7439                  * cr0. Other attempted changes are ignored, with no exit.
7440                  */
7441                 if (vmcs12->cr0_guest_host_mask & 0xe &
7442                     (val ^ vmcs12->cr0_read_shadow))
7443                         return 1;
7444                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7445                     !(vmcs12->cr0_read_shadow & 0x1) &&
7446                     (val & 0x1))
7447                         return 1;
7448                 break;
7449         }
7450         return 0;
7451 }
7452
7453 /*
7454  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7455  * should handle it ourselves in L0 (and then continue L2). Only call this
7456  * when in is_guest_mode (L2).
7457  */
7458 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7459 {
7460         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7461         struct vcpu_vmx *vmx = to_vmx(vcpu);
7462         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7463         u32 exit_reason = vmx->exit_reason;
7464
7465         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7466                                 vmcs_readl(EXIT_QUALIFICATION),
7467                                 vmx->idt_vectoring_info,
7468                                 intr_info,
7469                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7470                                 KVM_ISA_VMX);
7471
7472         if (vmx->nested.nested_run_pending)
7473                 return 0;
7474
7475         if (unlikely(vmx->fail)) {
7476                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7477                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7478                 return 1;
7479         }
7480
7481         switch (exit_reason) {
7482         case EXIT_REASON_EXCEPTION_NMI:
7483                 if (!is_exception(intr_info))
7484                         return 0;
7485                 else if (is_page_fault(intr_info))
7486                         return enable_ept;
7487                 else if (is_no_device(intr_info) &&
7488                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7489                         return 0;
7490                 return vmcs12->exception_bitmap &
7491                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7492         case EXIT_REASON_EXTERNAL_INTERRUPT:
7493                 return 0;
7494         case EXIT_REASON_TRIPLE_FAULT:
7495                 return 1;
7496         case EXIT_REASON_PENDING_INTERRUPT:
7497                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7498         case EXIT_REASON_NMI_WINDOW:
7499                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7500         case EXIT_REASON_TASK_SWITCH:
7501                 return 1;
7502         case EXIT_REASON_CPUID:
7503                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7504                         return 0;
7505                 return 1;
7506         case EXIT_REASON_HLT:
7507                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7508         case EXIT_REASON_INVD:
7509                 return 1;
7510         case EXIT_REASON_INVLPG:
7511                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7512         case EXIT_REASON_RDPMC:
7513                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7514         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7515                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7516         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7517         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7518         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7519         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7520         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7521         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7522                 /*
7523                  * VMX instructions trap unconditionally. This allows L1 to
7524                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7525                  */
7526                 return 1;
7527         case EXIT_REASON_CR_ACCESS:
7528                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7529         case EXIT_REASON_DR_ACCESS:
7530                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7531         case EXIT_REASON_IO_INSTRUCTION:
7532                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7533         case EXIT_REASON_MSR_READ:
7534         case EXIT_REASON_MSR_WRITE:
7535                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7536         case EXIT_REASON_INVALID_STATE:
7537                 return 1;
7538         case EXIT_REASON_MWAIT_INSTRUCTION:
7539                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7540         case EXIT_REASON_MONITOR_INSTRUCTION:
7541                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7542         case EXIT_REASON_PAUSE_INSTRUCTION:
7543                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7544                         nested_cpu_has2(vmcs12,
7545                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7546         case EXIT_REASON_MCE_DURING_VMENTRY:
7547                 return 0;
7548         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7549                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7550         case EXIT_REASON_APIC_ACCESS:
7551                 return nested_cpu_has2(vmcs12,
7552                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7553         case EXIT_REASON_APIC_WRITE:
7554         case EXIT_REASON_EOI_INDUCED:
7555                 /* apic_write and eoi_induced should exit unconditionally. */
7556                 return 1;
7557         case EXIT_REASON_EPT_VIOLATION:
7558                 /*
7559                  * L0 always deals with the EPT violation. If nested EPT is
7560                  * used, and the nested mmu code discovers that the address is
7561                  * missing in the guest EPT table (EPT12), the EPT violation
7562                  * will be injected with nested_ept_inject_page_fault()
7563                  */
7564                 return 0;
7565         case EXIT_REASON_EPT_MISCONFIG:
7566                 /*
7567                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7568                  * table (shadow on EPT) or a merged EPT table that L0 built
7569                  * (EPT on EPT). So any problems with the structure of the
7570                  * table is L0's fault.
7571                  */
7572                 return 0;
7573         case EXIT_REASON_WBINVD:
7574                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7575         case EXIT_REASON_XSETBV:
7576                 return 1;
7577         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7578                 /*
7579                  * This should never happen, since it is not possible to
7580                  * set XSS to a non-zero value---neither in L1 nor in L2.
7581                  * If if it were, XSS would have to be checked against
7582                  * the XSS exit bitmap in vmcs12.
7583                  */
7584                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7585         default:
7586                 return 1;
7587         }
7588 }
7589
7590 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7591 {
7592         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7593         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7594 }
7595
7596 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7597 {
7598         struct page *pml_pg;
7599         u32 exec_control;
7600
7601         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7602         if (!pml_pg)
7603                 return -ENOMEM;
7604
7605         vmx->pml_pg = pml_pg;
7606
7607         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7608         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7609
7610         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7611         exec_control |= SECONDARY_EXEC_ENABLE_PML;
7612         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7613
7614         return 0;
7615 }
7616
7617 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7618 {
7619         u32 exec_control;
7620
7621         ASSERT(vmx->pml_pg);
7622         __free_page(vmx->pml_pg);
7623         vmx->pml_pg = NULL;
7624
7625         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7626         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7627         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7628 }
7629
7630 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7631 {
7632         struct kvm *kvm = vmx->vcpu.kvm;
7633         u64 *pml_buf;
7634         u16 pml_idx;
7635
7636         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7637
7638         /* Do nothing if PML buffer is empty */
7639         if (pml_idx == (PML_ENTITY_NUM - 1))
7640                 return;
7641
7642         /* PML index always points to next available PML buffer entity */
7643         if (pml_idx >= PML_ENTITY_NUM)
7644                 pml_idx = 0;
7645         else
7646                 pml_idx++;
7647
7648         pml_buf = page_address(vmx->pml_pg);
7649         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7650                 u64 gpa;
7651
7652                 gpa = pml_buf[pml_idx];
7653                 WARN_ON(gpa & (PAGE_SIZE - 1));
7654                 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7655         }
7656
7657         /* reset PML index */
7658         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7659 }
7660
7661 /*
7662  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7663  * Called before reporting dirty_bitmap to userspace.
7664  */
7665 static void kvm_flush_pml_buffers(struct kvm *kvm)
7666 {
7667         int i;
7668         struct kvm_vcpu *vcpu;
7669         /*
7670          * We only need to kick vcpu out of guest mode here, as PML buffer
7671          * is flushed at beginning of all VMEXITs, and it's obvious that only
7672          * vcpus running in guest are possible to have unflushed GPAs in PML
7673          * buffer.
7674          */
7675         kvm_for_each_vcpu(i, vcpu, kvm)
7676                 kvm_vcpu_kick(vcpu);
7677 }
7678
7679 /*
7680  * The guest has exited.  See if we can fix it or if we need userspace
7681  * assistance.
7682  */
7683 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7684 {
7685         struct vcpu_vmx *vmx = to_vmx(vcpu);
7686         u32 exit_reason = vmx->exit_reason;
7687         u32 vectoring_info = vmx->idt_vectoring_info;
7688
7689         /*
7690          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7691          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7692          * querying dirty_bitmap, we only need to kick all vcpus out of guest
7693          * mode as if vcpus is in root mode, the PML buffer must has been
7694          * flushed already.
7695          */
7696         if (enable_pml)
7697                 vmx_flush_pml_buffer(vmx);
7698
7699         /* If guest state is invalid, start emulating */
7700         if (vmx->emulation_required)
7701                 return handle_invalid_guest_state(vcpu);
7702
7703         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7704                 nested_vmx_vmexit(vcpu, exit_reason,
7705                                   vmcs_read32(VM_EXIT_INTR_INFO),
7706                                   vmcs_readl(EXIT_QUALIFICATION));
7707                 return 1;
7708         }
7709
7710         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7711                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7712                 vcpu->run->fail_entry.hardware_entry_failure_reason
7713                         = exit_reason;
7714                 return 0;
7715         }
7716
7717         if (unlikely(vmx->fail)) {
7718                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7719                 vcpu->run->fail_entry.hardware_entry_failure_reason
7720                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7721                 return 0;
7722         }
7723
7724         /*
7725          * Note:
7726          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7727          * delivery event since it indicates guest is accessing MMIO.
7728          * The vm-exit can be triggered again after return to guest that
7729          * will cause infinite loop.
7730          */
7731         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7732                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7733                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7734                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7735                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7736                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7737                 vcpu->run->internal.ndata = 2;
7738                 vcpu->run->internal.data[0] = vectoring_info;
7739                 vcpu->run->internal.data[1] = exit_reason;
7740                 return 0;
7741         }
7742
7743         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7744             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7745                                         get_vmcs12(vcpu))))) {
7746                 if (vmx_interrupt_allowed(vcpu)) {
7747                         vmx->soft_vnmi_blocked = 0;
7748                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7749                            vcpu->arch.nmi_pending) {
7750                         /*
7751                          * This CPU don't support us in finding the end of an
7752                          * NMI-blocked window if the guest runs with IRQs
7753                          * disabled. So we pull the trigger after 1 s of
7754                          * futile waiting, but inform the user about this.
7755                          */
7756                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7757                                "state on VCPU %d after 1 s timeout\n",
7758                                __func__, vcpu->vcpu_id);
7759                         vmx->soft_vnmi_blocked = 0;
7760                 }
7761         }
7762
7763         if (exit_reason < kvm_vmx_max_exit_handlers
7764             && kvm_vmx_exit_handlers[exit_reason])
7765                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7766         else {
7767                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7768                 kvm_queue_exception(vcpu, UD_VECTOR);
7769                 return 1;
7770         }
7771 }
7772
7773 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7774 {
7775         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7776
7777         if (is_guest_mode(vcpu) &&
7778                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7779                 return;
7780
7781         if (irr == -1 || tpr < irr) {
7782                 vmcs_write32(TPR_THRESHOLD, 0);
7783                 return;
7784         }
7785
7786         vmcs_write32(TPR_THRESHOLD, irr);
7787 }
7788
7789 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7790 {
7791         u32 sec_exec_control;
7792
7793         /*
7794          * There is not point to enable virtualize x2apic without enable
7795          * apicv
7796          */
7797         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7798                                 !vmx_vm_has_apicv(vcpu->kvm))
7799                 return;
7800
7801         if (!vm_need_tpr_shadow(vcpu->kvm))
7802                 return;
7803
7804         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7805
7806         if (set) {
7807                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7808                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7809         } else {
7810                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7811                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7812         }
7813         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7814
7815         vmx_set_msr_bitmap(vcpu);
7816 }
7817
7818 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7819 {
7820         struct vcpu_vmx *vmx = to_vmx(vcpu);
7821
7822         /*
7823          * Currently we do not handle the nested case where L2 has an
7824          * APIC access page of its own; that page is still pinned.
7825          * Hence, we skip the case where the VCPU is in guest mode _and_
7826          * L1 prepared an APIC access page for L2.
7827          *
7828          * For the case where L1 and L2 share the same APIC access page
7829          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7830          * in the vmcs12), this function will only update either the vmcs01
7831          * or the vmcs02.  If the former, the vmcs02 will be updated by
7832          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7833          * the next L2->L1 exit.
7834          */
7835         if (!is_guest_mode(vcpu) ||
7836             !nested_cpu_has2(vmx->nested.current_vmcs12,
7837                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7838                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7839 }
7840
7841 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7842 {
7843         u16 status;
7844         u8 old;
7845
7846         if (isr == -1)
7847                 isr = 0;
7848
7849         status = vmcs_read16(GUEST_INTR_STATUS);
7850         old = status >> 8;
7851         if (isr != old) {
7852                 status &= 0xff;
7853                 status |= isr << 8;
7854                 vmcs_write16(GUEST_INTR_STATUS, status);
7855         }
7856 }
7857
7858 static void vmx_set_rvi(int vector)
7859 {
7860         u16 status;
7861         u8 old;
7862
7863         if (vector == -1)
7864                 vector = 0;
7865
7866         status = vmcs_read16(GUEST_INTR_STATUS);
7867         old = (u8)status & 0xff;
7868         if ((u8)vector != old) {
7869                 status &= ~0xff;
7870                 status |= (u8)vector;
7871                 vmcs_write16(GUEST_INTR_STATUS, status);
7872         }
7873 }
7874
7875 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7876 {
7877         if (!is_guest_mode(vcpu)) {
7878                 vmx_set_rvi(max_irr);
7879                 return;
7880         }
7881
7882         if (max_irr == -1)
7883                 return;
7884
7885         /*
7886          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7887          * handles it.
7888          */
7889         if (nested_exit_on_intr(vcpu))
7890                 return;
7891
7892         /*
7893          * Else, fall back to pre-APICv interrupt injection since L2
7894          * is run without virtual interrupt delivery.
7895          */
7896         if (!kvm_event_needs_reinjection(vcpu) &&
7897             vmx_interrupt_allowed(vcpu)) {
7898                 kvm_queue_interrupt(vcpu, max_irr, false);
7899                 vmx_inject_irq(vcpu);
7900         }
7901 }
7902
7903 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7904 {
7905         if (!vmx_vm_has_apicv(vcpu->kvm))
7906                 return;
7907
7908         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7909         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7910         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7911         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7912 }
7913
7914 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7915 {
7916         u32 exit_intr_info;
7917
7918         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7919               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7920                 return;
7921
7922         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7923         exit_intr_info = vmx->exit_intr_info;
7924
7925         /* Handle machine checks before interrupts are enabled */
7926         if (is_machine_check(exit_intr_info))
7927                 kvm_machine_check();
7928
7929         /* We need to handle NMIs before interrupts are enabled */
7930         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7931             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7932                 kvm_before_handle_nmi(&vmx->vcpu);
7933                 asm("int $2");
7934                 kvm_after_handle_nmi(&vmx->vcpu);
7935         }
7936 }
7937
7938 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7939 {
7940         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7941
7942         /*
7943          * If external interrupt exists, IF bit is set in rflags/eflags on the
7944          * interrupt stack frame, and interrupt will be enabled on a return
7945          * from interrupt handler.
7946          */
7947         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7948                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7949                 unsigned int vector;
7950                 unsigned long entry;
7951                 gate_desc *desc;
7952                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7953 #ifdef CONFIG_X86_64
7954                 unsigned long tmp;
7955 #endif
7956
7957                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7958                 desc = (gate_desc *)vmx->host_idt_base + vector;
7959                 entry = gate_offset(*desc);
7960                 asm volatile(
7961 #ifdef CONFIG_X86_64
7962                         "mov %%" _ASM_SP ", %[sp]\n\t"
7963                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7964                         "push $%c[ss]\n\t"
7965                         "push %[sp]\n\t"
7966 #endif
7967                         "pushf\n\t"
7968                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7969                         __ASM_SIZE(push) " $%c[cs]\n\t"
7970                         "call *%[entry]\n\t"
7971                         :
7972 #ifdef CONFIG_X86_64
7973                         [sp]"=&r"(tmp)
7974 #endif
7975                         :
7976                         [entry]"r"(entry),
7977                         [ss]"i"(__KERNEL_DS),
7978                         [cs]"i"(__KERNEL_CS)
7979                         );
7980         } else
7981                 local_irq_enable();
7982 }
7983
7984 static bool vmx_mpx_supported(void)
7985 {
7986         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7987                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7988 }
7989
7990 static bool vmx_xsaves_supported(void)
7991 {
7992         return vmcs_config.cpu_based_2nd_exec_ctrl &
7993                 SECONDARY_EXEC_XSAVES;
7994 }
7995
7996 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7997 {
7998         u32 exit_intr_info;
7999         bool unblock_nmi;
8000         u8 vector;
8001         bool idtv_info_valid;
8002
8003         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8004
8005         if (cpu_has_virtual_nmis()) {
8006                 if (vmx->nmi_known_unmasked)
8007                         return;
8008                 /*
8009                  * Can't use vmx->exit_intr_info since we're not sure what
8010                  * the exit reason is.
8011                  */
8012                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8013                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8014                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8015                 /*
8016                  * SDM 3: 27.7.1.2 (September 2008)
8017                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8018                  * a guest IRET fault.
8019                  * SDM 3: 23.2.2 (September 2008)
8020                  * Bit 12 is undefined in any of the following cases:
8021                  *  If the VM exit sets the valid bit in the IDT-vectoring
8022                  *   information field.
8023                  *  If the VM exit is due to a double fault.
8024                  */
8025                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8026                     vector != DF_VECTOR && !idtv_info_valid)
8027                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8028                                       GUEST_INTR_STATE_NMI);
8029                 else
8030                         vmx->nmi_known_unmasked =
8031                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8032                                   & GUEST_INTR_STATE_NMI);
8033         } else if (unlikely(vmx->soft_vnmi_blocked))
8034                 vmx->vnmi_blocked_time +=
8035                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8036 }
8037
8038 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8039                                       u32 idt_vectoring_info,
8040                                       int instr_len_field,
8041                                       int error_code_field)
8042 {
8043         u8 vector;
8044         int type;
8045         bool idtv_info_valid;
8046
8047         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8048
8049         vcpu->arch.nmi_injected = false;
8050         kvm_clear_exception_queue(vcpu);
8051         kvm_clear_interrupt_queue(vcpu);
8052
8053         if (!idtv_info_valid)
8054                 return;
8055
8056         kvm_make_request(KVM_REQ_EVENT, vcpu);
8057
8058         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8059         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8060
8061         switch (type) {
8062         case INTR_TYPE_NMI_INTR:
8063                 vcpu->arch.nmi_injected = true;
8064                 /*
8065                  * SDM 3: 27.7.1.2 (September 2008)
8066                  * Clear bit "block by NMI" before VM entry if a NMI
8067                  * delivery faulted.
8068                  */
8069                 vmx_set_nmi_mask(vcpu, false);
8070                 break;
8071         case INTR_TYPE_SOFT_EXCEPTION:
8072                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8073                 /* fall through */
8074         case INTR_TYPE_HARD_EXCEPTION:
8075                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8076                         u32 err = vmcs_read32(error_code_field);
8077                         kvm_requeue_exception_e(vcpu, vector, err);
8078                 } else
8079                         kvm_requeue_exception(vcpu, vector);
8080                 break;
8081         case INTR_TYPE_SOFT_INTR:
8082                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8083                 /* fall through */
8084         case INTR_TYPE_EXT_INTR:
8085                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8086                 break;
8087         default:
8088                 break;
8089         }
8090 }
8091
8092 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8093 {
8094         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8095                                   VM_EXIT_INSTRUCTION_LEN,
8096                                   IDT_VECTORING_ERROR_CODE);
8097 }
8098
8099 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8100 {
8101         __vmx_complete_interrupts(vcpu,
8102                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8103                                   VM_ENTRY_INSTRUCTION_LEN,
8104                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8105
8106         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8107 }
8108
8109 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8110 {
8111         int i, nr_msrs;
8112         struct perf_guest_switch_msr *msrs;
8113
8114         msrs = perf_guest_get_msrs(&nr_msrs);
8115
8116         if (!msrs)
8117                 return;
8118
8119         for (i = 0; i < nr_msrs; i++)
8120                 if (msrs[i].host == msrs[i].guest)
8121                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8122                 else
8123                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8124                                         msrs[i].host);
8125 }
8126
8127 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8128 {
8129         struct vcpu_vmx *vmx = to_vmx(vcpu);
8130         unsigned long debugctlmsr, cr4;
8131
8132         /* Record the guest's net vcpu time for enforced NMI injections. */
8133         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8134                 vmx->entry_time = ktime_get();
8135
8136         /* Don't enter VMX if guest state is invalid, let the exit handler
8137            start emulation until we arrive back to a valid state */
8138         if (vmx->emulation_required)
8139                 return;
8140
8141         if (vmx->ple_window_dirty) {
8142                 vmx->ple_window_dirty = false;
8143                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8144         }
8145
8146         if (vmx->nested.sync_shadow_vmcs) {
8147                 copy_vmcs12_to_shadow(vmx);
8148                 vmx->nested.sync_shadow_vmcs = false;
8149         }
8150
8151         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8152                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8153         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8154                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8155
8156         cr4 = cr4_read_shadow();
8157         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8158                 vmcs_writel(HOST_CR4, cr4);
8159                 vmx->host_state.vmcs_host_cr4 = cr4;
8160         }
8161
8162         /* When single-stepping over STI and MOV SS, we must clear the
8163          * corresponding interruptibility bits in the guest state. Otherwise
8164          * vmentry fails as it then expects bit 14 (BS) in pending debug
8165          * exceptions being set, but that's not correct for the guest debugging
8166          * case. */
8167         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8168                 vmx_set_interrupt_shadow(vcpu, 0);
8169
8170         atomic_switch_perf_msrs(vmx);
8171         debugctlmsr = get_debugctlmsr();
8172
8173         vmx->__launched = vmx->loaded_vmcs->launched;
8174         asm(
8175                 /* Store host registers */
8176                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8177                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8178                 "push %%" _ASM_CX " \n\t"
8179                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8180                 "je 1f \n\t"
8181                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8182                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8183                 "1: \n\t"
8184                 /* Reload cr2 if changed */
8185                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8186                 "mov %%cr2, %%" _ASM_DX " \n\t"
8187                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8188                 "je 2f \n\t"
8189                 "mov %%" _ASM_AX", %%cr2 \n\t"
8190                 "2: \n\t"
8191                 /* Check if vmlaunch of vmresume is needed */
8192                 "cmpl $0, %c[launched](%0) \n\t"
8193                 /* Load guest registers.  Don't clobber flags. */
8194                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8195                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8196                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8197                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8198                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8199                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8200 #ifdef CONFIG_X86_64
8201                 "mov %c[r8](%0),  %%r8  \n\t"
8202                 "mov %c[r9](%0),  %%r9  \n\t"
8203                 "mov %c[r10](%0), %%r10 \n\t"
8204                 "mov %c[r11](%0), %%r11 \n\t"
8205                 "mov %c[r12](%0), %%r12 \n\t"
8206                 "mov %c[r13](%0), %%r13 \n\t"
8207                 "mov %c[r14](%0), %%r14 \n\t"
8208                 "mov %c[r15](%0), %%r15 \n\t"
8209 #endif
8210                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8211
8212                 /* Enter guest mode */
8213                 "jne 1f \n\t"
8214                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8215                 "jmp 2f \n\t"
8216                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8217                 "2: "
8218                 /* Save guest registers, load host registers, keep flags */
8219                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8220                 "pop %0 \n\t"
8221                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8222                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8223                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8224                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8225                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8226                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8227                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8228 #ifdef CONFIG_X86_64
8229                 "mov %%r8,  %c[r8](%0) \n\t"
8230                 "mov %%r9,  %c[r9](%0) \n\t"
8231                 "mov %%r10, %c[r10](%0) \n\t"
8232                 "mov %%r11, %c[r11](%0) \n\t"
8233                 "mov %%r12, %c[r12](%0) \n\t"
8234                 "mov %%r13, %c[r13](%0) \n\t"
8235                 "mov %%r14, %c[r14](%0) \n\t"
8236                 "mov %%r15, %c[r15](%0) \n\t"
8237 #endif
8238                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8239                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8240
8241                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8242                 "setbe %c[fail](%0) \n\t"
8243                 ".pushsection .rodata \n\t"
8244                 ".global vmx_return \n\t"
8245                 "vmx_return: " _ASM_PTR " 2b \n\t"
8246                 ".popsection"
8247               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8248                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8249                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8250                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8251                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8252                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8253                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8254                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8255                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8256                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8257                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8258 #ifdef CONFIG_X86_64
8259                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8260                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8261                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8262                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8263                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8264                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8265                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8266                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8267 #endif
8268                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8269                 [wordsize]"i"(sizeof(ulong))
8270               : "cc", "memory"
8271 #ifdef CONFIG_X86_64
8272                 , "rax", "rbx", "rdi", "rsi"
8273                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8274 #else
8275                 , "eax", "ebx", "edi", "esi"
8276 #endif
8277               );
8278
8279         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8280         if (debugctlmsr)
8281                 update_debugctlmsr(debugctlmsr);
8282
8283 #ifndef CONFIG_X86_64
8284         /*
8285          * The sysexit path does not restore ds/es, so we must set them to
8286          * a reasonable value ourselves.
8287          *
8288          * We can't defer this to vmx_load_host_state() since that function
8289          * may be executed in interrupt context, which saves and restore segments
8290          * around it, nullifying its effect.
8291          */
8292         loadsegment(ds, __USER_DS);
8293         loadsegment(es, __USER_DS);
8294 #endif
8295
8296         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8297                                   | (1 << VCPU_EXREG_RFLAGS)
8298                                   | (1 << VCPU_EXREG_PDPTR)
8299                                   | (1 << VCPU_EXREG_SEGMENTS)
8300                                   | (1 << VCPU_EXREG_CR3));
8301         vcpu->arch.regs_dirty = 0;
8302
8303         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8304
8305         vmx->loaded_vmcs->launched = 1;
8306
8307         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8308         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8309
8310         /*
8311          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8312          * we did not inject a still-pending event to L1 now because of
8313          * nested_run_pending, we need to re-enable this bit.
8314          */
8315         if (vmx->nested.nested_run_pending)
8316                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8317
8318         vmx->nested.nested_run_pending = 0;
8319
8320         vmx_complete_atomic_exit(vmx);
8321         vmx_recover_nmi_blocking(vmx);
8322         vmx_complete_interrupts(vmx);
8323 }
8324
8325 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8326 {
8327         struct vcpu_vmx *vmx = to_vmx(vcpu);
8328         int cpu;
8329
8330         if (vmx->loaded_vmcs == &vmx->vmcs01)
8331                 return;
8332
8333         cpu = get_cpu();
8334         vmx->loaded_vmcs = &vmx->vmcs01;
8335         vmx_vcpu_put(vcpu);
8336         vmx_vcpu_load(vcpu, cpu);
8337         vcpu->cpu = cpu;
8338         put_cpu();
8339 }
8340
8341 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8342 {
8343         struct vcpu_vmx *vmx = to_vmx(vcpu);
8344
8345         if (enable_pml)
8346                 vmx_disable_pml(vmx);
8347         free_vpid(vmx);
8348         leave_guest_mode(vcpu);
8349         vmx_load_vmcs01(vcpu);
8350         free_nested(vmx);
8351         free_loaded_vmcs(vmx->loaded_vmcs);
8352         kfree(vmx->guest_msrs);
8353         kvm_vcpu_uninit(vcpu);
8354         kmem_cache_free(kvm_vcpu_cache, vmx);
8355 }
8356
8357 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8358 {
8359         int err;
8360         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8361         int cpu;
8362
8363         if (!vmx)
8364                 return ERR_PTR(-ENOMEM);
8365
8366         allocate_vpid(vmx);
8367
8368         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8369         if (err)
8370                 goto free_vcpu;
8371
8372         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8373         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8374                      > PAGE_SIZE);
8375
8376         err = -ENOMEM;
8377         if (!vmx->guest_msrs) {
8378                 goto uninit_vcpu;
8379         }
8380
8381         vmx->loaded_vmcs = &vmx->vmcs01;
8382         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8383         if (!vmx->loaded_vmcs->vmcs)
8384                 goto free_msrs;
8385         if (!vmm_exclusive)
8386                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8387         loaded_vmcs_init(vmx->loaded_vmcs);
8388         if (!vmm_exclusive)
8389                 kvm_cpu_vmxoff();
8390
8391         cpu = get_cpu();
8392         vmx_vcpu_load(&vmx->vcpu, cpu);
8393         vmx->vcpu.cpu = cpu;
8394         err = vmx_vcpu_setup(vmx);
8395         vmx_vcpu_put(&vmx->vcpu);
8396         put_cpu();
8397         if (err)
8398                 goto free_vmcs;
8399         if (vm_need_virtualize_apic_accesses(kvm)) {
8400                 err = alloc_apic_access_page(kvm);
8401                 if (err)
8402                         goto free_vmcs;
8403         }
8404
8405         if (enable_ept) {
8406                 if (!kvm->arch.ept_identity_map_addr)
8407                         kvm->arch.ept_identity_map_addr =
8408                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8409                 err = init_rmode_identity_map(kvm);
8410                 if (err)
8411                         goto free_vmcs;
8412         }
8413
8414         if (nested)
8415                 nested_vmx_setup_ctls_msrs(vmx);
8416
8417         vmx->nested.posted_intr_nv = -1;
8418         vmx->nested.current_vmptr = -1ull;
8419         vmx->nested.current_vmcs12 = NULL;
8420
8421         /*
8422          * If PML is turned on, failure on enabling PML just results in failure
8423          * of creating the vcpu, therefore we can simplify PML logic (by
8424          * avoiding dealing with cases, such as enabling PML partially on vcpus
8425          * for the guest, etc.
8426          */
8427         if (enable_pml) {
8428                 err = vmx_enable_pml(vmx);
8429                 if (err)
8430                         goto free_vmcs;
8431         }
8432
8433         return &vmx->vcpu;
8434
8435 free_vmcs:
8436         free_loaded_vmcs(vmx->loaded_vmcs);
8437 free_msrs:
8438         kfree(vmx->guest_msrs);
8439 uninit_vcpu:
8440         kvm_vcpu_uninit(&vmx->vcpu);
8441 free_vcpu:
8442         free_vpid(vmx);
8443         kmem_cache_free(kvm_vcpu_cache, vmx);
8444         return ERR_PTR(err);
8445 }
8446
8447 static void __init vmx_check_processor_compat(void *rtn)
8448 {
8449         struct vmcs_config vmcs_conf;
8450
8451         *(int *)rtn = 0;
8452         if (setup_vmcs_config(&vmcs_conf) < 0)
8453                 *(int *)rtn = -EIO;
8454         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8455                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8456                                 smp_processor_id());
8457                 *(int *)rtn = -EIO;
8458         }
8459 }
8460
8461 static int get_ept_level(void)
8462 {
8463         return VMX_EPT_DEFAULT_GAW + 1;
8464 }
8465
8466 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8467 {
8468         u64 ret;
8469
8470         /* For VT-d and EPT combination
8471          * 1. MMIO: always map as UC
8472          * 2. EPT with VT-d:
8473          *   a. VT-d without snooping control feature: can't guarantee the
8474          *      result, try to trust guest.
8475          *   b. VT-d with snooping control feature: snooping control feature of
8476          *      VT-d engine can guarantee the cache correctness. Just set it
8477          *      to WB to keep consistent with host. So the same as item 3.
8478          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8479          *    consistent with host MTRR
8480          */
8481         if (is_mmio)
8482                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8483         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8484                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8485                       VMX_EPT_MT_EPTE_SHIFT;
8486         else
8487                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8488                         | VMX_EPT_IPAT_BIT;
8489
8490         return ret;
8491 }
8492
8493 static int vmx_get_lpage_level(void)
8494 {
8495         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8496                 return PT_DIRECTORY_LEVEL;
8497         else
8498                 /* For shadow and EPT supported 1GB page */
8499                 return PT_PDPE_LEVEL;
8500 }
8501
8502 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8503 {
8504         struct kvm_cpuid_entry2 *best;
8505         struct vcpu_vmx *vmx = to_vmx(vcpu);
8506         u32 exec_control;
8507
8508         vmx->rdtscp_enabled = false;
8509         if (vmx_rdtscp_supported()) {
8510                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8511                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8512                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8513                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8514                                 vmx->rdtscp_enabled = true;
8515                         else {
8516                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8517                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8518                                                 exec_control);
8519                         }
8520                 }
8521                 if (nested && !vmx->rdtscp_enabled)
8522                         vmx->nested.nested_vmx_secondary_ctls_high &=
8523                                 ~SECONDARY_EXEC_RDTSCP;
8524         }
8525
8526         /* Exposing INVPCID only when PCID is exposed */
8527         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8528         if (vmx_invpcid_supported() &&
8529             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8530             guest_cpuid_has_pcid(vcpu)) {
8531                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8532                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8533                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8534                              exec_control);
8535         } else {
8536                 if (cpu_has_secondary_exec_ctrls()) {
8537                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8538                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8539                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8540                                      exec_control);
8541                 }
8542                 if (best)
8543                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8544         }
8545 }
8546
8547 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8548 {
8549         if (func == 1 && nested)
8550                 entry->ecx |= bit(X86_FEATURE_VMX);
8551 }
8552
8553 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8554                 struct x86_exception *fault)
8555 {
8556         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8557         u32 exit_reason;
8558
8559         if (fault->error_code & PFERR_RSVD_MASK)
8560                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8561         else
8562                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8563         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8564         vmcs12->guest_physical_address = fault->address;
8565 }
8566
8567 /* Callbacks for nested_ept_init_mmu_context: */
8568
8569 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8570 {
8571         /* return the page table to be shadowed - in our case, EPT12 */
8572         return get_vmcs12(vcpu)->ept_pointer;
8573 }
8574
8575 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8576 {
8577         WARN_ON(mmu_is_nested(vcpu));
8578         kvm_init_shadow_ept_mmu(vcpu,
8579                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8580                         VMX_EPT_EXECUTE_ONLY_BIT);
8581         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8582         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8583         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8584
8585         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8586 }
8587
8588 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8589 {
8590         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8591 }
8592
8593 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8594                                             u16 error_code)
8595 {
8596         bool inequality, bit;
8597
8598         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8599         inequality =
8600                 (error_code & vmcs12->page_fault_error_code_mask) !=
8601                  vmcs12->page_fault_error_code_match;
8602         return inequality ^ bit;
8603 }
8604
8605 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8606                 struct x86_exception *fault)
8607 {
8608         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8609
8610         WARN_ON(!is_guest_mode(vcpu));
8611
8612         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8613                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8614                                   vmcs_read32(VM_EXIT_INTR_INFO),
8615                                   vmcs_readl(EXIT_QUALIFICATION));
8616         else
8617                 kvm_inject_page_fault(vcpu, fault);
8618 }
8619
8620 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8621                                         struct vmcs12 *vmcs12)
8622 {
8623         struct vcpu_vmx *vmx = to_vmx(vcpu);
8624
8625         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8626                 /* TODO: Also verify bits beyond physical address width are 0 */
8627                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
8628                         return false;
8629
8630                 /*
8631                  * Translate L1 physical address to host physical
8632                  * address for vmcs02. Keep the page pinned, so this
8633                  * physical address remains valid. We keep a reference
8634                  * to it so we can release it later.
8635                  */
8636                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8637                         nested_release_page(vmx->nested.apic_access_page);
8638                 vmx->nested.apic_access_page =
8639                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8640         }
8641
8642         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8643                 /* TODO: Also verify bits beyond physical address width are 0 */
8644                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8645                         return false;
8646
8647                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8648                         nested_release_page(vmx->nested.virtual_apic_page);
8649                 vmx->nested.virtual_apic_page =
8650                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8651
8652                 /*
8653                  * Failing the vm entry is _not_ what the processor does
8654                  * but it's basically the only possibility we have.
8655                  * We could still enter the guest if CR8 load exits are
8656                  * enabled, CR8 store exits are enabled, and virtualize APIC
8657                  * access is disabled; in this case the processor would never
8658                  * use the TPR shadow and we could simply clear the bit from
8659                  * the execution control.  But such a configuration is useless,
8660                  * so let's keep the code simple.
8661                  */
8662                 if (!vmx->nested.virtual_apic_page)
8663                         return false;
8664         }
8665
8666         if (nested_cpu_has_posted_intr(vmcs12)) {
8667                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64))
8668                         return false;
8669
8670                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8671                         kunmap(vmx->nested.pi_desc_page);
8672                         nested_release_page(vmx->nested.pi_desc_page);
8673                 }
8674                 vmx->nested.pi_desc_page =
8675                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8676                 if (!vmx->nested.pi_desc_page)
8677                         return false;
8678
8679                 vmx->nested.pi_desc =
8680                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8681                 if (!vmx->nested.pi_desc) {
8682                         nested_release_page_clean(vmx->nested.pi_desc_page);
8683                         return false;
8684                 }
8685                 vmx->nested.pi_desc =
8686                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
8687                         (unsigned long)(vmcs12->posted_intr_desc_addr &
8688                         (PAGE_SIZE - 1)));
8689         }
8690
8691         return true;
8692 }
8693
8694 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8695 {
8696         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8697         struct vcpu_vmx *vmx = to_vmx(vcpu);
8698
8699         if (vcpu->arch.virtual_tsc_khz == 0)
8700                 return;
8701
8702         /* Make sure short timeouts reliably trigger an immediate vmexit.
8703          * hrtimer_start does not guarantee this. */
8704         if (preemption_timeout <= 1) {
8705                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8706                 return;
8707         }
8708
8709         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8710         preemption_timeout *= 1000000;
8711         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8712         hrtimer_start(&vmx->nested.preemption_timer,
8713                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8714 }
8715
8716 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8717                                                 struct vmcs12 *vmcs12)
8718 {
8719         int maxphyaddr;
8720         u64 addr;
8721
8722         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8723                 return 0;
8724
8725         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8726                 WARN_ON(1);
8727                 return -EINVAL;
8728         }
8729         maxphyaddr = cpuid_maxphyaddr(vcpu);
8730
8731         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8732            ((addr + PAGE_SIZE) >> maxphyaddr))
8733                 return -EINVAL;
8734
8735         return 0;
8736 }
8737
8738 /*
8739  * Merge L0's and L1's MSR bitmap, return false to indicate that
8740  * we do not use the hardware.
8741  */
8742 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8743                                                struct vmcs12 *vmcs12)
8744 {
8745         int msr;
8746         struct page *page;
8747         unsigned long *msr_bitmap;
8748
8749         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8750                 return false;
8751
8752         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8753         if (!page) {
8754                 WARN_ON(1);
8755                 return false;
8756         }
8757         msr_bitmap = (unsigned long *)kmap(page);
8758         if (!msr_bitmap) {
8759                 nested_release_page_clean(page);
8760                 WARN_ON(1);
8761                 return false;
8762         }
8763
8764         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8765                 if (nested_cpu_has_apic_reg_virt(vmcs12))
8766                         for (msr = 0x800; msr <= 0x8ff; msr++)
8767                                 nested_vmx_disable_intercept_for_msr(
8768                                         msr_bitmap,
8769                                         vmx_msr_bitmap_nested,
8770                                         msr, MSR_TYPE_R);
8771                 /* TPR is allowed */
8772                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8773                                 vmx_msr_bitmap_nested,
8774                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8775                                 MSR_TYPE_R | MSR_TYPE_W);
8776                 if (nested_cpu_has_vid(vmcs12)) {
8777                         /* EOI and self-IPI are allowed */
8778                         nested_vmx_disable_intercept_for_msr(
8779                                 msr_bitmap,
8780                                 vmx_msr_bitmap_nested,
8781                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8782                                 MSR_TYPE_W);
8783                         nested_vmx_disable_intercept_for_msr(
8784                                 msr_bitmap,
8785                                 vmx_msr_bitmap_nested,
8786                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8787                                 MSR_TYPE_W);
8788                 }
8789         } else {
8790                 /*
8791                  * Enable reading intercept of all the x2apic
8792                  * MSRs. We should not rely on vmcs12 to do any
8793                  * optimizations here, it may have been modified
8794                  * by L1.
8795                  */
8796                 for (msr = 0x800; msr <= 0x8ff; msr++)
8797                         __vmx_enable_intercept_for_msr(
8798                                 vmx_msr_bitmap_nested,
8799                                 msr,
8800                                 MSR_TYPE_R);
8801
8802                 __vmx_enable_intercept_for_msr(
8803                                 vmx_msr_bitmap_nested,
8804                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8805                                 MSR_TYPE_W);
8806                 __vmx_enable_intercept_for_msr(
8807                                 vmx_msr_bitmap_nested,
8808                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8809                                 MSR_TYPE_W);
8810                 __vmx_enable_intercept_for_msr(
8811                                 vmx_msr_bitmap_nested,
8812                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8813                                 MSR_TYPE_W);
8814         }
8815         kunmap(page);
8816         nested_release_page_clean(page);
8817
8818         return true;
8819 }
8820
8821 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8822                                            struct vmcs12 *vmcs12)
8823 {
8824         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8825             !nested_cpu_has_apic_reg_virt(vmcs12) &&
8826             !nested_cpu_has_vid(vmcs12) &&
8827             !nested_cpu_has_posted_intr(vmcs12))
8828                 return 0;
8829
8830         /*
8831          * If virtualize x2apic mode is enabled,
8832          * virtualize apic access must be disabled.
8833          */
8834         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8835             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8836                 return -EINVAL;
8837
8838         /*
8839          * If virtual interrupt delivery is enabled,
8840          * we must exit on external interrupts.
8841          */
8842         if (nested_cpu_has_vid(vmcs12) &&
8843            !nested_exit_on_intr(vcpu))
8844                 return -EINVAL;
8845
8846         /*
8847          * bits 15:8 should be zero in posted_intr_nv,
8848          * the descriptor address has been already checked
8849          * in nested_get_vmcs12_pages.
8850          */
8851         if (nested_cpu_has_posted_intr(vmcs12) &&
8852            (!nested_cpu_has_vid(vmcs12) ||
8853             !nested_exit_intr_ack_set(vcpu) ||
8854             vmcs12->posted_intr_nv & 0xff00))
8855                 return -EINVAL;
8856
8857         /* tpr shadow is needed by all apicv features. */
8858         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8859                 return -EINVAL;
8860
8861         return 0;
8862 }
8863
8864 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8865                                        unsigned long count_field,
8866                                        unsigned long addr_field,
8867                                        int maxphyaddr)
8868 {
8869         u64 count, addr;
8870
8871         if (vmcs12_read_any(vcpu, count_field, &count) ||
8872             vmcs12_read_any(vcpu, addr_field, &addr)) {
8873                 WARN_ON(1);
8874                 return -EINVAL;
8875         }
8876         if (count == 0)
8877                 return 0;
8878         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8879             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8880                 pr_warn_ratelimited(
8881                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8882                         addr_field, maxphyaddr, count, addr);
8883                 return -EINVAL;
8884         }
8885         return 0;
8886 }
8887
8888 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8889                                                 struct vmcs12 *vmcs12)
8890 {
8891         int maxphyaddr;
8892
8893         if (vmcs12->vm_exit_msr_load_count == 0 &&
8894             vmcs12->vm_exit_msr_store_count == 0 &&
8895             vmcs12->vm_entry_msr_load_count == 0)
8896                 return 0; /* Fast path */
8897         maxphyaddr = cpuid_maxphyaddr(vcpu);
8898         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8899                                         VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8900             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8901                                         VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8902             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8903                                         VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8904                 return -EINVAL;
8905         return 0;
8906 }
8907
8908 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8909                                        struct vmx_msr_entry *e)
8910 {
8911         /* x2APIC MSR accesses are not allowed */
8912         if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8913                 return -EINVAL;
8914         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8915             e->index == MSR_IA32_UCODE_REV)
8916                 return -EINVAL;
8917         if (e->reserved != 0)
8918                 return -EINVAL;
8919         return 0;
8920 }
8921
8922 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8923                                      struct vmx_msr_entry *e)
8924 {
8925         if (e->index == MSR_FS_BASE ||
8926             e->index == MSR_GS_BASE ||
8927             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8928             nested_vmx_msr_check_common(vcpu, e))
8929                 return -EINVAL;
8930         return 0;
8931 }
8932
8933 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8934                                       struct vmx_msr_entry *e)
8935 {
8936         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8937             nested_vmx_msr_check_common(vcpu, e))
8938                 return -EINVAL;
8939         return 0;
8940 }
8941
8942 /*
8943  * Load guest's/host's msr at nested entry/exit.
8944  * return 0 for success, entry index for failure.
8945  */
8946 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8947 {
8948         u32 i;
8949         struct vmx_msr_entry e;
8950         struct msr_data msr;
8951
8952         msr.host_initiated = false;
8953         for (i = 0; i < count; i++) {
8954                 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8955                                    &e, sizeof(e))) {
8956                         pr_warn_ratelimited(
8957                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8958                                 __func__, i, gpa + i * sizeof(e));
8959                         goto fail;
8960                 }
8961                 if (nested_vmx_load_msr_check(vcpu, &e)) {
8962                         pr_warn_ratelimited(
8963                                 "%s check failed (%u, 0x%x, 0x%x)\n",
8964                                 __func__, i, e.index, e.reserved);
8965                         goto fail;
8966                 }
8967                 msr.index = e.index;
8968                 msr.data = e.value;
8969                 if (kvm_set_msr(vcpu, &msr)) {
8970                         pr_warn_ratelimited(
8971                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8972                                 __func__, i, e.index, e.value);
8973                         goto fail;
8974                 }
8975         }
8976         return 0;
8977 fail:
8978         return i + 1;
8979 }
8980
8981 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8982 {
8983         u32 i;
8984         struct vmx_msr_entry e;
8985
8986         for (i = 0; i < count; i++) {
8987                 if (kvm_read_guest(vcpu->kvm,
8988                                    gpa + i * sizeof(e),
8989                                    &e, 2 * sizeof(u32))) {
8990                         pr_warn_ratelimited(
8991                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8992                                 __func__, i, gpa + i * sizeof(e));
8993                         return -EINVAL;
8994                 }
8995                 if (nested_vmx_store_msr_check(vcpu, &e)) {
8996                         pr_warn_ratelimited(
8997                                 "%s check failed (%u, 0x%x, 0x%x)\n",
8998                                 __func__, i, e.index, e.reserved);
8999                         return -EINVAL;
9000                 }
9001                 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9002                         pr_warn_ratelimited(
9003                                 "%s cannot read MSR (%u, 0x%x)\n",
9004                                 __func__, i, e.index);
9005                         return -EINVAL;
9006                 }
9007                 if (kvm_write_guest(vcpu->kvm,
9008                                     gpa + i * sizeof(e) +
9009                                         offsetof(struct vmx_msr_entry, value),
9010                                     &e.value, sizeof(e.value))) {
9011                         pr_warn_ratelimited(
9012                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9013                                 __func__, i, e.index, e.value);
9014                         return -EINVAL;
9015                 }
9016         }
9017         return 0;
9018 }
9019
9020 /*
9021  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9022  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9023  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9024  * guest in a way that will both be appropriate to L1's requests, and our
9025  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9026  * function also has additional necessary side-effects, like setting various
9027  * vcpu->arch fields.
9028  */
9029 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9030 {
9031         struct vcpu_vmx *vmx = to_vmx(vcpu);
9032         u32 exec_control;
9033
9034         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9035         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9036         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9037         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9038         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9039         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9040         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9041         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9042         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9043         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9044         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9045         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9046         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9047         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9048         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9049         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9050         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9051         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9052         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9053         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9054         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9055         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9056         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9057         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9058         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9059         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9060         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9061         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9062         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9063         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9064         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9065         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9066         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9067         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9068         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9069         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9070
9071         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9072                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9073                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9074         } else {
9075                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9076                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9077         }
9078         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9079                 vmcs12->vm_entry_intr_info_field);
9080         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9081                 vmcs12->vm_entry_exception_error_code);
9082         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9083                 vmcs12->vm_entry_instruction_len);
9084         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9085                 vmcs12->guest_interruptibility_info);
9086         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9087         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9088         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9089                 vmcs12->guest_pending_dbg_exceptions);
9090         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9091         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9092
9093         if (nested_cpu_has_xsaves(vmcs12))
9094                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9095         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9096
9097         exec_control = vmcs12->pin_based_vm_exec_control;
9098         exec_control |= vmcs_config.pin_based_exec_ctrl;
9099         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9100
9101         if (nested_cpu_has_posted_intr(vmcs12)) {
9102                 /*
9103                  * Note that we use L0's vector here and in
9104                  * vmx_deliver_nested_posted_interrupt.
9105                  */
9106                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9107                 vmx->nested.pi_pending = false;
9108                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9109                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9110                         page_to_phys(vmx->nested.pi_desc_page) +
9111                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9112                         (PAGE_SIZE - 1)));
9113         } else
9114                 exec_control &= ~PIN_BASED_POSTED_INTR;
9115
9116         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9117
9118         vmx->nested.preemption_timer_expired = false;
9119         if (nested_cpu_has_preemption_timer(vmcs12))
9120                 vmx_start_preemption_timer(vcpu);
9121
9122         /*
9123          * Whether page-faults are trapped is determined by a combination of
9124          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9125          * If enable_ept, L0 doesn't care about page faults and we should
9126          * set all of these to L1's desires. However, if !enable_ept, L0 does
9127          * care about (at least some) page faults, and because it is not easy
9128          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9129          * to exit on each and every L2 page fault. This is done by setting
9130          * MASK=MATCH=0 and (see below) EB.PF=1.
9131          * Note that below we don't need special code to set EB.PF beyond the
9132          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9133          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9134          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9135          *
9136          * A problem with this approach (when !enable_ept) is that L1 may be
9137          * injected with more page faults than it asked for. This could have
9138          * caused problems, but in practice existing hypervisors don't care.
9139          * To fix this, we will need to emulate the PFEC checking (on the L1
9140          * page tables), using walk_addr(), when injecting PFs to L1.
9141          */
9142         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9143                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9144         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9145                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9146
9147         if (cpu_has_secondary_exec_ctrls()) {
9148                 exec_control = vmx_secondary_exec_control(vmx);
9149                 if (!vmx->rdtscp_enabled)
9150                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
9151                 /* Take the following fields only from vmcs12 */
9152                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9153                                   SECONDARY_EXEC_RDTSCP |
9154                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9155                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9156                 if (nested_cpu_has(vmcs12,
9157                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9158                         exec_control |= vmcs12->secondary_vm_exec_control;
9159
9160                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9161                         /*
9162                          * If translation failed, no matter: This feature asks
9163                          * to exit when accessing the given address, and if it
9164                          * can never be accessed, this feature won't do
9165                          * anything anyway.
9166                          */
9167                         if (!vmx->nested.apic_access_page)
9168                                 exec_control &=
9169                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9170                         else
9171                                 vmcs_write64(APIC_ACCESS_ADDR,
9172                                   page_to_phys(vmx->nested.apic_access_page));
9173                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9174                             (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9175                         exec_control |=
9176                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9177                         kvm_vcpu_reload_apic_access_page(vcpu);
9178                 }
9179
9180                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9181                         vmcs_write64(EOI_EXIT_BITMAP0,
9182                                 vmcs12->eoi_exit_bitmap0);
9183                         vmcs_write64(EOI_EXIT_BITMAP1,
9184                                 vmcs12->eoi_exit_bitmap1);
9185                         vmcs_write64(EOI_EXIT_BITMAP2,
9186                                 vmcs12->eoi_exit_bitmap2);
9187                         vmcs_write64(EOI_EXIT_BITMAP3,
9188                                 vmcs12->eoi_exit_bitmap3);
9189                         vmcs_write16(GUEST_INTR_STATUS,
9190                                 vmcs12->guest_intr_status);
9191                 }
9192
9193                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9194         }
9195
9196
9197         /*
9198          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9199          * Some constant fields are set here by vmx_set_constant_host_state().
9200          * Other fields are different per CPU, and will be set later when
9201          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9202          */
9203         vmx_set_constant_host_state(vmx);
9204
9205         /*
9206          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9207          * entry, but only if the current (host) sp changed from the value
9208          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9209          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9210          * here we just force the write to happen on entry.
9211          */
9212         vmx->host_rsp = 0;
9213
9214         exec_control = vmx_exec_control(vmx); /* L0's desires */
9215         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9216         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9217         exec_control &= ~CPU_BASED_TPR_SHADOW;
9218         exec_control |= vmcs12->cpu_based_vm_exec_control;
9219
9220         if (exec_control & CPU_BASED_TPR_SHADOW) {
9221                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9222                                 page_to_phys(vmx->nested.virtual_apic_page));
9223                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9224         }
9225
9226         if (cpu_has_vmx_msr_bitmap() &&
9227             exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9228             nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) {
9229                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_nested));
9230         } else
9231                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9232
9233         /*
9234          * Merging of IO bitmap not currently supported.
9235          * Rather, exit every time.
9236          */
9237         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9238         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9239
9240         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9241
9242         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9243          * bitwise-or of what L1 wants to trap for L2, and what we want to
9244          * trap. Note that CR0.TS also needs updating - we do this later.
9245          */
9246         update_exception_bitmap(vcpu);
9247         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9248         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9249
9250         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9251          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9252          * bits are further modified by vmx_set_efer() below.
9253          */
9254         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9255
9256         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9257          * emulated by vmx_set_efer(), below.
9258          */
9259         vm_entry_controls_init(vmx,
9260                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9261                         ~VM_ENTRY_IA32E_MODE) |
9262                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9263
9264         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9265                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9266                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9267         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9268                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9269
9270
9271         set_cr4_guest_host_mask(vmx);
9272
9273         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9274                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9275
9276         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9277                 vmcs_write64(TSC_OFFSET,
9278                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9279         else
9280                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9281
9282         if (enable_vpid) {
9283                 /*
9284                  * Trivially support vpid by letting L2s share their parent
9285                  * L1's vpid. TODO: move to a more elaborate solution, giving
9286                  * each L2 its own vpid and exposing the vpid feature to L1.
9287                  */
9288                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9289                 vmx_flush_tlb(vcpu);
9290         }
9291
9292         if (nested_cpu_has_ept(vmcs12)) {
9293                 kvm_mmu_unload(vcpu);
9294                 nested_ept_init_mmu_context(vcpu);
9295         }
9296
9297         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9298                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9299         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9300                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9301         else
9302                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9303         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9304         vmx_set_efer(vcpu, vcpu->arch.efer);
9305
9306         /*
9307          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9308          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9309          * The CR0_READ_SHADOW is what L2 should have expected to read given
9310          * the specifications by L1; It's not enough to take
9311          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9312          * have more bits than L1 expected.
9313          */
9314         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9315         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9316
9317         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9318         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9319
9320         /* shadow page tables on either EPT or shadow page tables */
9321         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9322         kvm_mmu_reset_context(vcpu);
9323
9324         if (!enable_ept)
9325                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9326
9327         /*
9328          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9329          */
9330         if (enable_ept) {
9331                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9332                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9333                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9334                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9335         }
9336
9337         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9338         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9339 }
9340
9341 /*
9342  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9343  * for running an L2 nested guest.
9344  */
9345 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9346 {
9347         struct vmcs12 *vmcs12;
9348         struct vcpu_vmx *vmx = to_vmx(vcpu);
9349         int cpu;
9350         struct loaded_vmcs *vmcs02;
9351         bool ia32e;
9352         u32 msr_entry_idx;
9353
9354         if (!nested_vmx_check_permission(vcpu) ||
9355             !nested_vmx_check_vmcs12(vcpu))
9356                 return 1;
9357
9358         skip_emulated_instruction(vcpu);
9359         vmcs12 = get_vmcs12(vcpu);
9360
9361         if (enable_shadow_vmcs)
9362                 copy_shadow_to_vmcs12(vmx);
9363
9364         /*
9365          * The nested entry process starts with enforcing various prerequisites
9366          * on vmcs12 as required by the Intel SDM, and act appropriately when
9367          * they fail: As the SDM explains, some conditions should cause the
9368          * instruction to fail, while others will cause the instruction to seem
9369          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9370          * To speed up the normal (success) code path, we should avoid checking
9371          * for misconfigurations which will anyway be caught by the processor
9372          * when using the merged vmcs02.
9373          */
9374         if (vmcs12->launch_state == launch) {
9375                 nested_vmx_failValid(vcpu,
9376                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9377                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9378                 return 1;
9379         }
9380
9381         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9382             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9383                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9384                 return 1;
9385         }
9386
9387         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9388                 /*TODO: Also verify bits beyond physical address width are 0*/
9389                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9390                 return 1;
9391         }
9392
9393         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9394                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9395                 return 1;
9396         }
9397
9398         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9399                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9400                 return 1;
9401         }
9402
9403         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9404                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9405                 return 1;
9406         }
9407
9408         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9409                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9410                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9411             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9412                                 vmx->nested.nested_vmx_secondary_ctls_low,
9413                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9414             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9415                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9416                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9417             !vmx_control_verify(vmcs12->vm_exit_controls,
9418                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9419                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9420             !vmx_control_verify(vmcs12->vm_entry_controls,
9421                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9422                                 vmx->nested.nested_vmx_entry_ctls_high))
9423         {
9424                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9425                 return 1;
9426         }
9427
9428         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9429             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9430                 nested_vmx_failValid(vcpu,
9431                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9432                 return 1;
9433         }
9434
9435         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9436             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9437                 nested_vmx_entry_failure(vcpu, vmcs12,
9438                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9439                 return 1;
9440         }
9441         if (vmcs12->vmcs_link_pointer != -1ull) {
9442                 nested_vmx_entry_failure(vcpu, vmcs12,
9443                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9444                 return 1;
9445         }
9446
9447         /*
9448          * If the load IA32_EFER VM-entry control is 1, the following checks
9449          * are performed on the field for the IA32_EFER MSR:
9450          * - Bits reserved in the IA32_EFER MSR must be 0.
9451          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9452          *   the IA-32e mode guest VM-exit control. It must also be identical
9453          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9454          *   CR0.PG) is 1.
9455          */
9456         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9457                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9458                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9459                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9460                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9461                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9462                         nested_vmx_entry_failure(vcpu, vmcs12,
9463                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9464                         return 1;
9465                 }
9466         }
9467
9468         /*
9469          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9470          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9471          * the values of the LMA and LME bits in the field must each be that of
9472          * the host address-space size VM-exit control.
9473          */
9474         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9475                 ia32e = (vmcs12->vm_exit_controls &
9476                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9477                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9478                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9479                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9480                         nested_vmx_entry_failure(vcpu, vmcs12,
9481                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9482                         return 1;
9483                 }
9484         }
9485
9486         /*
9487          * We're finally done with prerequisite checking, and can start with
9488          * the nested entry.
9489          */
9490
9491         vmcs02 = nested_get_current_vmcs02(vmx);
9492         if (!vmcs02)
9493                 return -ENOMEM;
9494
9495         enter_guest_mode(vcpu);
9496
9497         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9498
9499         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9500                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9501
9502         cpu = get_cpu();
9503         vmx->loaded_vmcs = vmcs02;
9504         vmx_vcpu_put(vcpu);
9505         vmx_vcpu_load(vcpu, cpu);
9506         vcpu->cpu = cpu;
9507         put_cpu();
9508
9509         vmx_segment_cache_clear(vmx);
9510
9511         prepare_vmcs02(vcpu, vmcs12);
9512
9513         msr_entry_idx = nested_vmx_load_msr(vcpu,
9514                                             vmcs12->vm_entry_msr_load_addr,
9515                                             vmcs12->vm_entry_msr_load_count);
9516         if (msr_entry_idx) {
9517                 leave_guest_mode(vcpu);
9518                 vmx_load_vmcs01(vcpu);
9519                 nested_vmx_entry_failure(vcpu, vmcs12,
9520                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9521                 return 1;
9522         }
9523
9524         vmcs12->launch_state = 1;
9525
9526         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9527                 return kvm_vcpu_halt(vcpu);
9528
9529         vmx->nested.nested_run_pending = 1;
9530
9531         /*
9532          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9533          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9534          * returned as far as L1 is concerned. It will only return (and set
9535          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9536          */
9537         return 1;
9538 }
9539
9540 /*
9541  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9542  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9543  * This function returns the new value we should put in vmcs12.guest_cr0.
9544  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9545  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9546  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9547  *     didn't trap the bit, because if L1 did, so would L0).
9548  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9549  *     been modified by L2, and L1 knows it. So just leave the old value of
9550  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9551  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9552  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9553  *     changed these bits, and therefore they need to be updated, but L0
9554  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9555  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9556  */
9557 static inline unsigned long
9558 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9559 {
9560         return
9561         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9562         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9563         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9564                         vcpu->arch.cr0_guest_owned_bits));
9565 }
9566
9567 static inline unsigned long
9568 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9569 {
9570         return
9571         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9572         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9573         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9574                         vcpu->arch.cr4_guest_owned_bits));
9575 }
9576
9577 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9578                                        struct vmcs12 *vmcs12)
9579 {
9580         u32 idt_vectoring;
9581         unsigned int nr;
9582
9583         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9584                 nr = vcpu->arch.exception.nr;
9585                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9586
9587                 if (kvm_exception_is_soft(nr)) {
9588                         vmcs12->vm_exit_instruction_len =
9589                                 vcpu->arch.event_exit_inst_len;
9590                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9591                 } else
9592                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9593
9594                 if (vcpu->arch.exception.has_error_code) {
9595                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9596                         vmcs12->idt_vectoring_error_code =
9597                                 vcpu->arch.exception.error_code;
9598                 }
9599
9600                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9601         } else if (vcpu->arch.nmi_injected) {
9602                 vmcs12->idt_vectoring_info_field =
9603                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9604         } else if (vcpu->arch.interrupt.pending) {
9605                 nr = vcpu->arch.interrupt.nr;
9606                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9607
9608                 if (vcpu->arch.interrupt.soft) {
9609                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
9610                         vmcs12->vm_entry_instruction_len =
9611                                 vcpu->arch.event_exit_inst_len;
9612                 } else
9613                         idt_vectoring |= INTR_TYPE_EXT_INTR;
9614
9615                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9616         }
9617 }
9618
9619 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9620 {
9621         struct vcpu_vmx *vmx = to_vmx(vcpu);
9622
9623         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9624             vmx->nested.preemption_timer_expired) {
9625                 if (vmx->nested.nested_run_pending)
9626                         return -EBUSY;
9627                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9628                 return 0;
9629         }
9630
9631         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9632                 if (vmx->nested.nested_run_pending ||
9633                     vcpu->arch.interrupt.pending)
9634                         return -EBUSY;
9635                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9636                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
9637                                   INTR_INFO_VALID_MASK, 0);
9638                 /*
9639                  * The NMI-triggered VM exit counts as injection:
9640                  * clear this one and block further NMIs.
9641                  */
9642                 vcpu->arch.nmi_pending = 0;
9643                 vmx_set_nmi_mask(vcpu, true);
9644                 return 0;
9645         }
9646
9647         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9648             nested_exit_on_intr(vcpu)) {
9649                 if (vmx->nested.nested_run_pending)
9650                         return -EBUSY;
9651                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9652                 return 0;
9653         }
9654
9655         return vmx_complete_nested_posted_interrupt(vcpu);
9656 }
9657
9658 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9659 {
9660         ktime_t remaining =
9661                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9662         u64 value;
9663
9664         if (ktime_to_ns(remaining) <= 0)
9665                 return 0;
9666
9667         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9668         do_div(value, 1000000);
9669         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9670 }
9671
9672 /*
9673  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9674  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9675  * and this function updates it to reflect the changes to the guest state while
9676  * L2 was running (and perhaps made some exits which were handled directly by L0
9677  * without going back to L1), and to reflect the exit reason.
9678  * Note that we do not have to copy here all VMCS fields, just those that
9679  * could have changed by the L2 guest or the exit - i.e., the guest-state and
9680  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9681  * which already writes to vmcs12 directly.
9682  */
9683 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9684                            u32 exit_reason, u32 exit_intr_info,
9685                            unsigned long exit_qualification)
9686 {
9687         /* update guest state fields: */
9688         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9689         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9690
9691         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9692         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9693         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9694
9695         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9696         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9697         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9698         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9699         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9700         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9701         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9702         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9703         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9704         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9705         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9706         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9707         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9708         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9709         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9710         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9711         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9712         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9713         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9714         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9715         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9716         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9717         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9718         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9719         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9720         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9721         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9722         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9723         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9724         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9725         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9726         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9727         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9728         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9729         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9730         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9731
9732         vmcs12->guest_interruptibility_info =
9733                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9734         vmcs12->guest_pending_dbg_exceptions =
9735                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9736         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9737                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9738         else
9739                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9740
9741         if (nested_cpu_has_preemption_timer(vmcs12)) {
9742                 if (vmcs12->vm_exit_controls &
9743                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9744                         vmcs12->vmx_preemption_timer_value =
9745                                 vmx_get_preemption_timer_value(vcpu);
9746                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9747         }
9748
9749         /*
9750          * In some cases (usually, nested EPT), L2 is allowed to change its
9751          * own CR3 without exiting. If it has changed it, we must keep it.
9752          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9753          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9754          *
9755          * Additionally, restore L2's PDPTR to vmcs12.
9756          */
9757         if (enable_ept) {
9758                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9759                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9760                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9761                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9762                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9763         }
9764
9765         if (nested_cpu_has_vid(vmcs12))
9766                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9767
9768         vmcs12->vm_entry_controls =
9769                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9770                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9771
9772         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9773                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9774                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9775         }
9776
9777         /* TODO: These cannot have changed unless we have MSR bitmaps and
9778          * the relevant bit asks not to trap the change */
9779         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9780                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9781         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9782                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9783         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9784         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9785         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9786         if (vmx_mpx_supported())
9787                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9788         if (nested_cpu_has_xsaves(vmcs12))
9789                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9790
9791         /* update exit information fields: */
9792
9793         vmcs12->vm_exit_reason = exit_reason;
9794         vmcs12->exit_qualification = exit_qualification;
9795
9796         vmcs12->vm_exit_intr_info = exit_intr_info;
9797         if ((vmcs12->vm_exit_intr_info &
9798              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9799             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9800                 vmcs12->vm_exit_intr_error_code =
9801                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9802         vmcs12->idt_vectoring_info_field = 0;
9803         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9804         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9805
9806         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9807                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9808                  * instead of reading the real value. */
9809                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9810
9811                 /*
9812                  * Transfer the event that L0 or L1 may wanted to inject into
9813                  * L2 to IDT_VECTORING_INFO_FIELD.
9814                  */
9815                 vmcs12_save_pending_event(vcpu, vmcs12);
9816         }
9817
9818         /*
9819          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9820          * preserved above and would only end up incorrectly in L1.
9821          */
9822         vcpu->arch.nmi_injected = false;
9823         kvm_clear_exception_queue(vcpu);
9824         kvm_clear_interrupt_queue(vcpu);
9825 }
9826
9827 /*
9828  * A part of what we need to when the nested L2 guest exits and we want to
9829  * run its L1 parent, is to reset L1's guest state to the host state specified
9830  * in vmcs12.
9831  * This function is to be called not only on normal nested exit, but also on
9832  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9833  * Failures During or After Loading Guest State").
9834  * This function should be called when the active VMCS is L1's (vmcs01).
9835  */
9836 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9837                                    struct vmcs12 *vmcs12)
9838 {
9839         struct kvm_segment seg;
9840
9841         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9842                 vcpu->arch.efer = vmcs12->host_ia32_efer;
9843         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9844                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9845         else
9846                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9847         vmx_set_efer(vcpu, vcpu->arch.efer);
9848
9849         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9850         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9851         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9852         /*
9853          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9854          * actually changed, because it depends on the current state of
9855          * fpu_active (which may have changed).
9856          * Note that vmx_set_cr0 refers to efer set above.
9857          */
9858         vmx_set_cr0(vcpu, vmcs12->host_cr0);
9859         /*
9860          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9861          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9862          * but we also need to update cr0_guest_host_mask and exception_bitmap.
9863          */
9864         update_exception_bitmap(vcpu);
9865         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9866         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9867
9868         /*
9869          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9870          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9871          */
9872         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9873         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9874
9875         nested_ept_uninit_mmu_context(vcpu);
9876
9877         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9878         kvm_mmu_reset_context(vcpu);
9879
9880         if (!enable_ept)
9881                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9882
9883         if (enable_vpid) {
9884                 /*
9885                  * Trivially support vpid by letting L2s share their parent
9886                  * L1's vpid. TODO: move to a more elaborate solution, giving
9887                  * each L2 its own vpid and exposing the vpid feature to L1.
9888                  */
9889                 vmx_flush_tlb(vcpu);
9890         }
9891
9892
9893         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9894         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9895         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9896         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9897         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9898
9899         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9900         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9901                 vmcs_write64(GUEST_BNDCFGS, 0);
9902
9903         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9904                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9905                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9906         }
9907         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9908                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9909                         vmcs12->host_ia32_perf_global_ctrl);
9910
9911         /* Set L1 segment info according to Intel SDM
9912             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9913         seg = (struct kvm_segment) {
9914                 .base = 0,
9915                 .limit = 0xFFFFFFFF,
9916                 .selector = vmcs12->host_cs_selector,
9917                 .type = 11,
9918                 .present = 1,
9919                 .s = 1,
9920                 .g = 1
9921         };
9922         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9923                 seg.l = 1;
9924         else
9925                 seg.db = 1;
9926         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9927         seg = (struct kvm_segment) {
9928                 .base = 0,
9929                 .limit = 0xFFFFFFFF,
9930                 .type = 3,
9931                 .present = 1,
9932                 .s = 1,
9933                 .db = 1,
9934                 .g = 1
9935         };
9936         seg.selector = vmcs12->host_ds_selector;
9937         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9938         seg.selector = vmcs12->host_es_selector;
9939         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9940         seg.selector = vmcs12->host_ss_selector;
9941         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9942         seg.selector = vmcs12->host_fs_selector;
9943         seg.base = vmcs12->host_fs_base;
9944         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9945         seg.selector = vmcs12->host_gs_selector;
9946         seg.base = vmcs12->host_gs_base;
9947         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9948         seg = (struct kvm_segment) {
9949                 .base = vmcs12->host_tr_base,
9950                 .limit = 0x67,
9951                 .selector = vmcs12->host_tr_selector,
9952                 .type = 11,
9953                 .present = 1
9954         };
9955         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9956
9957         kvm_set_dr(vcpu, 7, 0x400);
9958         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9959
9960         if (cpu_has_vmx_msr_bitmap())
9961                 vmx_set_msr_bitmap(vcpu);
9962
9963         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9964                                 vmcs12->vm_exit_msr_load_count))
9965                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9966 }
9967
9968 /*
9969  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9970  * and modify vmcs12 to make it see what it would expect to see there if
9971  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9972  */
9973 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9974                               u32 exit_intr_info,
9975                               unsigned long exit_qualification)
9976 {
9977         struct vcpu_vmx *vmx = to_vmx(vcpu);
9978         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9979
9980         /* trying to cancel vmlaunch/vmresume is a bug */
9981         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9982
9983         leave_guest_mode(vcpu);
9984         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9985                        exit_qualification);
9986
9987         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9988                                  vmcs12->vm_exit_msr_store_count))
9989                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9990
9991         vmx_load_vmcs01(vcpu);
9992
9993         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9994             && nested_exit_intr_ack_set(vcpu)) {
9995                 int irq = kvm_cpu_get_interrupt(vcpu);
9996                 WARN_ON(irq < 0);
9997                 vmcs12->vm_exit_intr_info = irq |
9998                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9999         }
10000
10001         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10002                                        vmcs12->exit_qualification,
10003                                        vmcs12->idt_vectoring_info_field,
10004                                        vmcs12->vm_exit_intr_info,
10005                                        vmcs12->vm_exit_intr_error_code,
10006                                        KVM_ISA_VMX);
10007
10008         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10009         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10010         vmx_segment_cache_clear(vmx);
10011
10012         /* if no vmcs02 cache requested, remove the one we used */
10013         if (VMCS02_POOL_SIZE == 0)
10014                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10015
10016         load_vmcs12_host_state(vcpu, vmcs12);
10017
10018         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10019         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10020
10021         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10022         vmx->host_rsp = 0;
10023
10024         /* Unpin physical memory we referred to in vmcs02 */
10025         if (vmx->nested.apic_access_page) {
10026                 nested_release_page(vmx->nested.apic_access_page);
10027                 vmx->nested.apic_access_page = NULL;
10028         }
10029         if (vmx->nested.virtual_apic_page) {
10030                 nested_release_page(vmx->nested.virtual_apic_page);
10031                 vmx->nested.virtual_apic_page = NULL;
10032         }
10033         if (vmx->nested.pi_desc_page) {
10034                 kunmap(vmx->nested.pi_desc_page);
10035                 nested_release_page(vmx->nested.pi_desc_page);
10036                 vmx->nested.pi_desc_page = NULL;
10037                 vmx->nested.pi_desc = NULL;
10038         }
10039
10040         /*
10041          * We are now running in L2, mmu_notifier will force to reload the
10042          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10043          */
10044         kvm_vcpu_reload_apic_access_page(vcpu);
10045
10046         /*
10047          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10048          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10049          * success or failure flag accordingly.
10050          */
10051         if (unlikely(vmx->fail)) {
10052                 vmx->fail = 0;
10053                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10054         } else
10055                 nested_vmx_succeed(vcpu);
10056         if (enable_shadow_vmcs)
10057                 vmx->nested.sync_shadow_vmcs = true;
10058
10059         /* in case we halted in L2 */
10060         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10061 }
10062
10063 /*
10064  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10065  */
10066 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10067 {
10068         if (is_guest_mode(vcpu))
10069                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10070         free_nested(to_vmx(vcpu));
10071 }
10072
10073 /*
10074  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10075  * 23.7 "VM-entry failures during or after loading guest state" (this also
10076  * lists the acceptable exit-reason and exit-qualification parameters).
10077  * It should only be called before L2 actually succeeded to run, and when
10078  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10079  */
10080 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10081                         struct vmcs12 *vmcs12,
10082                         u32 reason, unsigned long qualification)
10083 {
10084         load_vmcs12_host_state(vcpu, vmcs12);
10085         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10086         vmcs12->exit_qualification = qualification;
10087         nested_vmx_succeed(vcpu);
10088         if (enable_shadow_vmcs)
10089                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10090 }
10091
10092 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10093                                struct x86_instruction_info *info,
10094                                enum x86_intercept_stage stage)
10095 {
10096         return X86EMUL_CONTINUE;
10097 }
10098
10099 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10100 {
10101         if (ple_gap)
10102                 shrink_ple_window(vcpu);
10103 }
10104
10105 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10106                                      struct kvm_memory_slot *slot)
10107 {
10108         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10109         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10110 }
10111
10112 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10113                                        struct kvm_memory_slot *slot)
10114 {
10115         kvm_mmu_slot_set_dirty(kvm, slot);
10116 }
10117
10118 static void vmx_flush_log_dirty(struct kvm *kvm)
10119 {
10120         kvm_flush_pml_buffers(kvm);
10121 }
10122
10123 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10124                                            struct kvm_memory_slot *memslot,
10125                                            gfn_t offset, unsigned long mask)
10126 {
10127         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10128 }
10129
10130 static struct kvm_x86_ops vmx_x86_ops = {
10131         .cpu_has_kvm_support = cpu_has_kvm_support,
10132         .disabled_by_bios = vmx_disabled_by_bios,
10133         .hardware_setup = hardware_setup,
10134         .hardware_unsetup = hardware_unsetup,
10135         .check_processor_compatibility = vmx_check_processor_compat,
10136         .hardware_enable = hardware_enable,
10137         .hardware_disable = hardware_disable,
10138         .cpu_has_accelerated_tpr = report_flexpriority,
10139
10140         .vcpu_create = vmx_create_vcpu,
10141         .vcpu_free = vmx_free_vcpu,
10142         .vcpu_reset = vmx_vcpu_reset,
10143
10144         .prepare_guest_switch = vmx_save_host_state,
10145         .vcpu_load = vmx_vcpu_load,
10146         .vcpu_put = vmx_vcpu_put,
10147
10148         .update_db_bp_intercept = update_exception_bitmap,
10149         .get_msr = vmx_get_msr,
10150         .set_msr = vmx_set_msr,
10151         .get_segment_base = vmx_get_segment_base,
10152         .get_segment = vmx_get_segment,
10153         .set_segment = vmx_set_segment,
10154         .get_cpl = vmx_get_cpl,
10155         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10156         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10157         .decache_cr3 = vmx_decache_cr3,
10158         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10159         .set_cr0 = vmx_set_cr0,
10160         .set_cr3 = vmx_set_cr3,
10161         .set_cr4 = vmx_set_cr4,
10162         .set_efer = vmx_set_efer,
10163         .get_idt = vmx_get_idt,
10164         .set_idt = vmx_set_idt,
10165         .get_gdt = vmx_get_gdt,
10166         .set_gdt = vmx_set_gdt,
10167         .get_dr6 = vmx_get_dr6,
10168         .set_dr6 = vmx_set_dr6,
10169         .set_dr7 = vmx_set_dr7,
10170         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10171         .cache_reg = vmx_cache_reg,
10172         .get_rflags = vmx_get_rflags,
10173         .set_rflags = vmx_set_rflags,
10174         .fpu_deactivate = vmx_fpu_deactivate,
10175
10176         .tlb_flush = vmx_flush_tlb,
10177
10178         .run = vmx_vcpu_run,
10179         .handle_exit = vmx_handle_exit,
10180         .skip_emulated_instruction = skip_emulated_instruction,
10181         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10182         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10183         .patch_hypercall = vmx_patch_hypercall,
10184         .set_irq = vmx_inject_irq,
10185         .set_nmi = vmx_inject_nmi,
10186         .queue_exception = vmx_queue_exception,
10187         .cancel_injection = vmx_cancel_injection,
10188         .interrupt_allowed = vmx_interrupt_allowed,
10189         .nmi_allowed = vmx_nmi_allowed,
10190         .get_nmi_mask = vmx_get_nmi_mask,
10191         .set_nmi_mask = vmx_set_nmi_mask,
10192         .enable_nmi_window = enable_nmi_window,
10193         .enable_irq_window = enable_irq_window,
10194         .update_cr8_intercept = update_cr8_intercept,
10195         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10196         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10197         .vm_has_apicv = vmx_vm_has_apicv,
10198         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10199         .hwapic_irr_update = vmx_hwapic_irr_update,
10200         .hwapic_isr_update = vmx_hwapic_isr_update,
10201         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10202         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10203
10204         .set_tss_addr = vmx_set_tss_addr,
10205         .get_tdp_level = get_ept_level,
10206         .get_mt_mask = vmx_get_mt_mask,
10207
10208         .get_exit_info = vmx_get_exit_info,
10209
10210         .get_lpage_level = vmx_get_lpage_level,
10211
10212         .cpuid_update = vmx_cpuid_update,
10213
10214         .rdtscp_supported = vmx_rdtscp_supported,
10215         .invpcid_supported = vmx_invpcid_supported,
10216
10217         .set_supported_cpuid = vmx_set_supported_cpuid,
10218
10219         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10220
10221         .set_tsc_khz = vmx_set_tsc_khz,
10222         .read_tsc_offset = vmx_read_tsc_offset,
10223         .write_tsc_offset = vmx_write_tsc_offset,
10224         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10225         .compute_tsc_offset = vmx_compute_tsc_offset,
10226         .read_l1_tsc = vmx_read_l1_tsc,
10227
10228         .set_tdp_cr3 = vmx_set_cr3,
10229
10230         .check_intercept = vmx_check_intercept,
10231         .handle_external_intr = vmx_handle_external_intr,
10232         .mpx_supported = vmx_mpx_supported,
10233         .xsaves_supported = vmx_xsaves_supported,
10234
10235         .check_nested_events = vmx_check_nested_events,
10236
10237         .sched_in = vmx_sched_in,
10238
10239         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10240         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10241         .flush_log_dirty = vmx_flush_log_dirty,
10242         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10243 };
10244
10245 static int __init vmx_init(void)
10246 {
10247         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10248                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10249         if (r)
10250                 return r;
10251
10252 #ifdef CONFIG_KEXEC
10253         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10254                            crash_vmclear_local_loaded_vmcss);
10255 #endif
10256
10257         return 0;
10258 }
10259
10260 static void __exit vmx_exit(void)
10261 {
10262 #ifdef CONFIG_KEXEC
10263         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10264         synchronize_rcu();
10265 #endif
10266
10267         kvm_exit();
10268 }
10269
10270 module_init(vmx_init)
10271 module_exit(vmx_exit)