arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         u32 exit_reason;
 619
 620         /* Posted interrupt descriptor */
 621         struct pi_desc pi_desc;
 622
 623         /* Support for a guest hypervisor (nested VMX) */
 624         struct nested_vmx nested;
 625
 626         /* Dynamic PLE window. */
 627         int ple_window;
 628         bool ple_window_dirty;
 629
 630         /* Support for PML */
 631 #define PML_ENTITY_NUM          512
 632         struct page *pml_pg;
 633
 634         /* apic deadline value in host tsc */
 635         u64 hv_deadline_tsc;
 636
 637         u64 current_tsc_ratio;
 638
 639         bool guest_pkru_valid;
 640         u32 guest_pkru;
 641         u32 host_pkru;
 642
 643         /*
 644          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 645          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 646          * in msr_ia32_feature_control_valid_bits.
 647          */
 648         u64 msr_ia32_feature_control;
 649         u64 msr_ia32_feature_control_valid_bits;
 650 };
 651
 652 enum segment_cache_field {
 653         SEG_FIELD_SEL = 0,
 654         SEG_FIELD_BASE = 1,
 655         SEG_FIELD_LIMIT = 2,
 656         SEG_FIELD_AR = 3,
 657
 658         SEG_FIELD_NR = 4
 659 };
 660
 661 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 662 {
 663         return container_of(vcpu, struct vcpu_vmx, vcpu);
 664 }
 665
 666 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 667 {
 668         return &(to_vmx(vcpu)->pi_desc);
 669 }
 670
 671 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 672 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 673 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 674                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 675
 676
 677 static unsigned long shadow_read_only_fields[] = {
 678         /*
 679          * We do NOT shadow fields that are modified when L0
 680          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 681          * VMXON...) executed by L1.
 682          * For example, VM_INSTRUCTION_ERROR is read
 683          * by L1 if a vmx instruction fails (part of the error path).
 684          * Note the code assumes this logic. If for some reason
 685          * we start shadowing these fields then we need to
 686          * force a shadow sync when L0 emulates vmx instructions
 687          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 688          * by nested_vmx_failValid)
 689          */
 690         VM_EXIT_REASON,
 691         VM_EXIT_INTR_INFO,
 692         VM_EXIT_INSTRUCTION_LEN,
 693         IDT_VECTORING_INFO_FIELD,
 694         IDT_VECTORING_ERROR_CODE,
 695         VM_EXIT_INTR_ERROR_CODE,
 696         EXIT_QUALIFICATION,
 697         GUEST_LINEAR_ADDRESS,
 698         GUEST_PHYSICAL_ADDRESS
 699 };
 700 static int max_shadow_read_only_fields =
 701         ARRAY_SIZE(shadow_read_only_fields);
 702
 703 static unsigned long shadow_read_write_fields[] = {
 704         TPR_THRESHOLD,
 705         GUEST_RIP,
 706         GUEST_RSP,
 707         GUEST_CR0,
 708         GUEST_CR3,
 709         GUEST_CR4,
 710         GUEST_INTERRUPTIBILITY_INFO,
 711         GUEST_RFLAGS,
 712         GUEST_CS_SELECTOR,
 713         GUEST_CS_AR_BYTES,
 714         GUEST_CS_LIMIT,
 715         GUEST_CS_BASE,
 716         GUEST_ES_BASE,
 717         GUEST_BNDCFGS,
 718         CR0_GUEST_HOST_MASK,
 719         CR0_READ_SHADOW,
 720         CR4_READ_SHADOW,
 721         TSC_OFFSET,
 722         EXCEPTION_BITMAP,
 723         CPU_BASED_VM_EXEC_CONTROL,
 724         VM_ENTRY_EXCEPTION_ERROR_CODE,
 725         VM_ENTRY_INTR_INFO_FIELD,
 726         VM_ENTRY_INSTRUCTION_LEN,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         HOST_FS_BASE,
 729         HOST_GS_BASE,
 730         HOST_FS_SELECTOR,
 731         HOST_GS_SELECTOR
 732 };
 733 static int max_shadow_read_write_fields =
 734         ARRAY_SIZE(shadow_read_write_fields);
 735
 736 static const unsigned short vmcs_field_to_offset_table[] = {
 737         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 738         FIELD(POSTED_INTR_NV, posted_intr_nv),
 739         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 740         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 741         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 742         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 743         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 744         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 745         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 746         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 747         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 748         FIELD(HOST_ES_SELECTOR, host_es_selector),
 749         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 750         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 751         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 752         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 753         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 754         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 755         FIELD64(IO_BITMAP_A, io_bitmap_a),
 756         FIELD64(IO_BITMAP_B, io_bitmap_b),
 757         FIELD64(MSR_BITMAP, msr_bitmap),
 758         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 759         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 760         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 761         FIELD64(TSC_OFFSET, tsc_offset),
 762         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 763         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 764         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 765         FIELD64(EPT_POINTER, ept_pointer),
 766         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 767         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 768         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 769         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 770         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 771         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 772         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 773         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 774         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 775         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 776         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 777         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 778         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 779         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 780         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 781         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 782         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 783         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 784         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 785         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 786         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 787         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 788         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 789         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 790         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 791         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 792         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 793         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 794         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 795         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 796         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 797         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 798         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 799         FIELD(TPR_THRESHOLD, tpr_threshold),
 800         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 801         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 802         FIELD(VM_EXIT_REASON, vm_exit_reason),
 803         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 804         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 805         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 806         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 807         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 808         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 809         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 810         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 811         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 812         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 813         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 814         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 815         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 816         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 817         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 818         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 819         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 820         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 821         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 822         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 823         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 824         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 825         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 826         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 827         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 828         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 829         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 830         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 831         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 832         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 833         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 834         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 835         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 836         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 837         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 838         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 839         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 840         FIELD(EXIT_QUALIFICATION, exit_qualification),
 841         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 842         FIELD(GUEST_CR0, guest_cr0),
 843         FIELD(GUEST_CR3, guest_cr3),
 844         FIELD(GUEST_CR4, guest_cr4),
 845         FIELD(GUEST_ES_BASE, guest_es_base),
 846         FIELD(GUEST_CS_BASE, guest_cs_base),
 847         FIELD(GUEST_SS_BASE, guest_ss_base),
 848         FIELD(GUEST_DS_BASE, guest_ds_base),
 849         FIELD(GUEST_FS_BASE, guest_fs_base),
 850         FIELD(GUEST_GS_BASE, guest_gs_base),
 851         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 852         FIELD(GUEST_TR_BASE, guest_tr_base),
 853         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 854         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 855         FIELD(GUEST_DR7, guest_dr7),
 856         FIELD(GUEST_RSP, guest_rsp),
 857         FIELD(GUEST_RIP, guest_rip),
 858         FIELD(GUEST_RFLAGS, guest_rflags),
 859         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 860         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 861         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 862         FIELD(HOST_CR0, host_cr0),
 863         FIELD(HOST_CR3, host_cr3),
 864         FIELD(HOST_CR4, host_cr4),
 865         FIELD(HOST_FS_BASE, host_fs_base),
 866         FIELD(HOST_GS_BASE, host_gs_base),
 867         FIELD(HOST_TR_BASE, host_tr_base),
 868         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 869         FIELD(HOST_IDTR_BASE, host_idtr_base),
 870         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 871         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 872         FIELD(HOST_RSP, host_rsp),
 873         FIELD(HOST_RIP, host_rip),
 874 };
 875
 876 static inline short vmcs_field_to_offset(unsigned long field)
 877 {
 878         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 879
 880         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 881             vmcs_field_to_offset_table[field] == 0)
 882                 return -ENOENT;
 883
 884         return vmcs_field_to_offset_table[field];
 885 }
 886
 887 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 888 {
 889         return to_vmx(vcpu)->nested.cached_vmcs12;
 890 }
 891
 892 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 893 {
 894         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 895         if (is_error_page(page))
 896                 return NULL;
 897
 898         return page;
 899 }
 900
 901 static void nested_release_page(struct page *page)
 902 {
 903         kvm_release_page_dirty(page);
 904 }
 905
 906 static void nested_release_page_clean(struct page *page)
 907 {
 908         kvm_release_page_clean(page);
 909 }
 910
 911 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 912 static u64 construct_eptp(unsigned long root_hpa);
 913 static void kvm_cpu_vmxon(u64 addr);
 914 static void kvm_cpu_vmxoff(void);
 915 static bool vmx_xsaves_supported(void);
 916 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 917 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 918                             struct kvm_segment *var, int seg);
 919 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 920                             struct kvm_segment *var, int seg);
 921 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 922 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 923 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 924 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 925 static int alloc_identity_pagetable(struct kvm *kvm);
 926
 927 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 928 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 929 /*
 930  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 931  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 932  */
 933 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 934 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 935
 936 /*
 937  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 938  * can find which vCPU should be waken up.
 939  */
 940 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 941 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 942
 943 enum {
 944         VMX_IO_BITMAP_A,
 945         VMX_IO_BITMAP_B,
 946         VMX_MSR_BITMAP_LEGACY,
 947         VMX_MSR_BITMAP_LONGMODE,
 948         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 949         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 950         VMX_MSR_BITMAP_LEGACY_X2APIC,
 951         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 952         VMX_VMREAD_BITMAP,
 953         VMX_VMWRITE_BITMAP,
 954         VMX_BITMAP_NR
 955 };
 956
 957 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 958
 959 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 960 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 961 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 962 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 963 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 964 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 965 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 966 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 967 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 968 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 969
 970 static bool cpu_has_load_ia32_efer;
 971 static bool cpu_has_load_perf_global_ctrl;
 972
 973 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 974 static DEFINE_SPINLOCK(vmx_vpid_lock);
 975
 976 static struct vmcs_config {
 977         int size;
 978         int order;
 979         u32 basic_cap;
 980         u32 revision_id;
 981         u32 pin_based_exec_ctrl;
 982         u32 cpu_based_exec_ctrl;
 983         u32 cpu_based_2nd_exec_ctrl;
 984         u32 vmexit_ctrl;
 985         u32 vmentry_ctrl;
 986 } vmcs_config;
 987
 988 static struct vmx_capability {
 989         u32 ept;
 990         u32 vpid;
 991 } vmx_capability;
 992
 993 #define VMX_SEGMENT_FIELD(seg)                                  \
 994         [VCPU_SREG_##seg] = {                                   \
 995                 .selector = GUEST_##seg##_SELECTOR,             \
 996                 .base = GUEST_##seg##_BASE,                     \
 997                 .limit = GUEST_##seg##_LIMIT,                   \
 998                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 999         }
1000
1001 static const struct kvm_vmx_segment_field {
1002         unsigned selector;
1003         unsigned base;
1004         unsigned limit;
1005         unsigned ar_bytes;
1006 } kvm_vmx_segment_fields[] = {
1007         VMX_SEGMENT_FIELD(CS),
1008         VMX_SEGMENT_FIELD(DS),
1009         VMX_SEGMENT_FIELD(ES),
1010         VMX_SEGMENT_FIELD(FS),
1011         VMX_SEGMENT_FIELD(GS),
1012         VMX_SEGMENT_FIELD(SS),
1013         VMX_SEGMENT_FIELD(TR),
1014         VMX_SEGMENT_FIELD(LDTR),
1015 };
1016
1017 static u64 host_efer;
1018
1019 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1020
1021 /*
1022  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1023  * away by decrementing the array size.
1024  */
1025 static const u32 vmx_msr_index[] = {
1026 #ifdef CONFIG_X86_64
1027         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1028 #endif
1029         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1030 };
1031
1032 static inline bool is_exception_n(u32 intr_info, u8 vector)
1033 {
1034         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1035                              INTR_INFO_VALID_MASK)) ==
1036                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1037 }
1038
1039 static inline bool is_debug(u32 intr_info)
1040 {
1041         return is_exception_n(intr_info, DB_VECTOR);
1042 }
1043
1044 static inline bool is_breakpoint(u32 intr_info)
1045 {
1046         return is_exception_n(intr_info, BP_VECTOR);
1047 }
1048
1049 static inline bool is_page_fault(u32 intr_info)
1050 {
1051         return is_exception_n(intr_info, PF_VECTOR);
1052 }
1053
1054 static inline bool is_no_device(u32 intr_info)
1055 {
1056         return is_exception_n(intr_info, NM_VECTOR);
1057 }
1058
1059 static inline bool is_invalid_opcode(u32 intr_info)
1060 {
1061         return is_exception_n(intr_info, UD_VECTOR);
1062 }
1063
1064 static inline bool is_external_interrupt(u32 intr_info)
1065 {
1066         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1067                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1068 }
1069
1070 static inline bool is_machine_check(u32 intr_info)
1071 {
1072         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1073                              INTR_INFO_VALID_MASK)) ==
1074                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1075 }
1076
1077 static inline bool cpu_has_vmx_msr_bitmap(void)
1078 {
1079         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1080 }
1081
1082 static inline bool cpu_has_vmx_tpr_shadow(void)
1083 {
1084         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1085 }
1086
1087 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1088 {
1089         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1090 }
1091
1092 static inline bool cpu_has_secondary_exec_ctrls(void)
1093 {
1094         return vmcs_config.cpu_based_exec_ctrl &
1095                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1096 }
1097
1098 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1099 {
1100         return vmcs_config.cpu_based_2nd_exec_ctrl &
1101                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1102 }
1103
1104 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1105 {
1106         return vmcs_config.cpu_based_2nd_exec_ctrl &
1107                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1108 }
1109
1110 static inline bool cpu_has_vmx_apic_register_virt(void)
1111 {
1112         return vmcs_config.cpu_based_2nd_exec_ctrl &
1113                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1114 }
1115
1116 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1117 {
1118         return vmcs_config.cpu_based_2nd_exec_ctrl &
1119                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1120 }
1121
1122 /*
1123  * Comment's format: document - errata name - stepping - processor name.
1124  * Refer from
1125  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1126  */
1127 static u32 vmx_preemption_cpu_tfms[] = {
1128 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1129 0x000206E6,
1130 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1131 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1132 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1133 0x00020652,
1134 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1135 0x00020655,
1136 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1137 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1138 /*
1139  * 320767.pdf - AAP86  - B1 -
1140  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1141  */
1142 0x000106E5,
1143 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1144 0x000106A0,
1145 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1146 0x000106A1,
1147 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1148 0x000106A4,
1149  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1150  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1151  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1152 0x000106A5,
1153 };
1154
1155 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1156 {
1157         u32 eax = cpuid_eax(0x00000001), i;
1158
1159         /* Clear the reserved bits */
1160         eax &= ~(0x3U << 14 | 0xfU << 28);
1161         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1162                 if (eax == vmx_preemption_cpu_tfms[i])
1163                         return true;
1164
1165         return false;
1166 }
1167
1168 static inline bool cpu_has_vmx_preemption_timer(void)
1169 {
1170         return vmcs_config.pin_based_exec_ctrl &
1171                 PIN_BASED_VMX_PREEMPTION_TIMER;
1172 }
1173
1174 static inline bool cpu_has_vmx_posted_intr(void)
1175 {
1176         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1177                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1178 }
1179
1180 static inline bool cpu_has_vmx_apicv(void)
1181 {
1182         return cpu_has_vmx_apic_register_virt() &&
1183                 cpu_has_vmx_virtual_intr_delivery() &&
1184                 cpu_has_vmx_posted_intr();
1185 }
1186
1187 static inline bool cpu_has_vmx_flexpriority(void)
1188 {
1189         return cpu_has_vmx_tpr_shadow() &&
1190                 cpu_has_vmx_virtualize_apic_accesses();
1191 }
1192
1193 static inline bool cpu_has_vmx_ept_execute_only(void)
1194 {
1195         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept_2m_page(void)
1199 {
1200         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1201 }
1202
1203 static inline bool cpu_has_vmx_ept_1g_page(void)
1204 {
1205         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_ept_4levels(void)
1209 {
1210         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_ept_ad_bits(void)
1214 {
1215         return vmx_capability.ept & VMX_EPT_AD_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_invept_context(void)
1219 {
1220         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_invept_global(void)
1224 {
1225         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1226 }
1227
1228 static inline bool cpu_has_vmx_invvpid_single(void)
1229 {
1230         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1231 }
1232
1233 static inline bool cpu_has_vmx_invvpid_global(void)
1234 {
1235         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1236 }
1237
1238 static inline bool cpu_has_vmx_invvpid(void)
1239 {
1240         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1241 }
1242
1243 static inline bool cpu_has_vmx_ept(void)
1244 {
1245         return vmcs_config.cpu_based_2nd_exec_ctrl &
1246                 SECONDARY_EXEC_ENABLE_EPT;
1247 }
1248
1249 static inline bool cpu_has_vmx_unrestricted_guest(void)
1250 {
1251         return vmcs_config.cpu_based_2nd_exec_ctrl &
1252                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1253 }
1254
1255 static inline bool cpu_has_vmx_ple(void)
1256 {
1257         return vmcs_config.cpu_based_2nd_exec_ctrl &
1258                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1259 }
1260
1261 static inline bool cpu_has_vmx_basic_inout(void)
1262 {
1263         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1264 }
1265
1266 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1267 {
1268         return flexpriority_enabled && lapic_in_kernel(vcpu);
1269 }
1270
1271 static inline bool cpu_has_vmx_vpid(void)
1272 {
1273         return vmcs_config.cpu_based_2nd_exec_ctrl &
1274                 SECONDARY_EXEC_ENABLE_VPID;
1275 }
1276
1277 static inline bool cpu_has_vmx_rdtscp(void)
1278 {
1279         return vmcs_config.cpu_based_2nd_exec_ctrl &
1280                 SECONDARY_EXEC_RDTSCP;
1281 }
1282
1283 static inline bool cpu_has_vmx_invpcid(void)
1284 {
1285         return vmcs_config.cpu_based_2nd_exec_ctrl &
1286                 SECONDARY_EXEC_ENABLE_INVPCID;
1287 }
1288
1289 static inline bool cpu_has_vmx_wbinvd_exit(void)
1290 {
1291         return vmcs_config.cpu_based_2nd_exec_ctrl &
1292                 SECONDARY_EXEC_WBINVD_EXITING;
1293 }
1294
1295 static inline bool cpu_has_vmx_shadow_vmcs(void)
1296 {
1297         u64 vmx_msr;
1298         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1299         /* check if the cpu supports writing r/o exit information fields */
1300         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1301                 return false;
1302
1303         return vmcs_config.cpu_based_2nd_exec_ctrl &
1304                 SECONDARY_EXEC_SHADOW_VMCS;
1305 }
1306
1307 static inline bool cpu_has_vmx_pml(void)
1308 {
1309         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1310 }
1311
1312 static inline bool cpu_has_vmx_tsc_scaling(void)
1313 {
1314         return vmcs_config.cpu_based_2nd_exec_ctrl &
1315                 SECONDARY_EXEC_TSC_SCALING;
1316 }
1317
1318 static inline bool report_flexpriority(void)
1319 {
1320         return flexpriority_enabled;
1321 }
1322
1323 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1324 {
1325         return vmcs12->cpu_based_vm_exec_control & bit;
1326 }
1327
1328 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1329 {
1330         return (vmcs12->cpu_based_vm_exec_control &
1331                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1332                 (vmcs12->secondary_vm_exec_control & bit);
1333 }
1334
1335 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1336 {
1337         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1338 }
1339
1340 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1341 {
1342         return vmcs12->pin_based_vm_exec_control &
1343                 PIN_BASED_VMX_PREEMPTION_TIMER;
1344 }
1345
1346 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1347 {
1348         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1349 }
1350
1351 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1352 {
1353         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1354                 vmx_xsaves_supported();
1355 }
1356
1357 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1358 {
1359         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1360 }
1361
1362 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1363 {
1364         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1365 }
1366
1367 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1368 {
1369         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1370 }
1371
1372 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1373 {
1374         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1375 }
1376
1377 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1378 {
1379         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1380 }
1381
1382 static inline bool is_nmi(u32 intr_info)
1383 {
1384         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1385                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1386 }
1387
1388 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1389                               u32 exit_intr_info,
1390                               unsigned long exit_qualification);
1391 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1392                         struct vmcs12 *vmcs12,
1393                         u32 reason, unsigned long qualification);
1394
1395 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1396 {
1397         int i;
1398
1399         for (i = 0; i < vmx->nmsrs; ++i)
1400                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1401                         return i;
1402         return -1;
1403 }
1404
1405 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1406 {
1407     struct {
1408         u64 vpid : 16;
1409         u64 rsvd : 48;
1410         u64 gva;
1411     } operand = { vpid, 0, gva };
1412
1413     asm volatile (__ex(ASM_VMX_INVVPID)
1414                   /* CF==1 or ZF==1 --> rc = -1 */
1415                   "; ja 1f ; ud2 ; 1:"
1416                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1417 }
1418
1419 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1420 {
1421         struct {
1422                 u64 eptp, gpa;
1423         } operand = {eptp, gpa};
1424
1425         asm volatile (__ex(ASM_VMX_INVEPT)
1426                         /* CF==1 or ZF==1 --> rc = -1 */
1427                         "; ja 1f ; ud2 ; 1:\n"
1428                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1429 }
1430
1431 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1432 {
1433         int i;
1434
1435         i = __find_msr_index(vmx, msr);
1436         if (i >= 0)
1437                 return &vmx->guest_msrs[i];
1438         return NULL;
1439 }
1440
1441 static void vmcs_clear(struct vmcs *vmcs)
1442 {
1443         u64 phys_addr = __pa(vmcs);
1444         u8 error;
1445
1446         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1447                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1448                       : "cc", "memory");
1449         if (error)
1450                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1451                        vmcs, phys_addr);
1452 }
1453
1454 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1455 {
1456         vmcs_clear(loaded_vmcs->vmcs);
1457         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1458                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1459         loaded_vmcs->cpu = -1;
1460         loaded_vmcs->launched = 0;
1461 }
1462
1463 static void vmcs_load(struct vmcs *vmcs)
1464 {
1465         u64 phys_addr = __pa(vmcs);
1466         u8 error;
1467
1468         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1469                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1470                         : "cc", "memory");
1471         if (error)
1472                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1473                        vmcs, phys_addr);
1474 }
1475
1476 #ifdef CONFIG_KEXEC_CORE
1477 /*
1478  * This bitmap is used to indicate whether the vmclear
1479  * operation is enabled on all cpus. All disabled by
1480  * default.
1481  */
1482 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1483
1484 static inline void crash_enable_local_vmclear(int cpu)
1485 {
1486         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1487 }
1488
1489 static inline void crash_disable_local_vmclear(int cpu)
1490 {
1491         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1492 }
1493
1494 static inline int crash_local_vmclear_enabled(int cpu)
1495 {
1496         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1497 }
1498
1499 static void crash_vmclear_local_loaded_vmcss(void)
1500 {
1501         int cpu = raw_smp_processor_id();
1502         struct loaded_vmcs *v;
1503
1504         if (!crash_local_vmclear_enabled(cpu))
1505                 return;
1506
1507         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1508                             loaded_vmcss_on_cpu_link)
1509                 vmcs_clear(v->vmcs);
1510 }
1511 #else
1512 static inline void crash_enable_local_vmclear(int cpu) { }
1513 static inline void crash_disable_local_vmclear(int cpu) { }
1514 #endif /* CONFIG_KEXEC_CORE */
1515
1516 static void __loaded_vmcs_clear(void *arg)
1517 {
1518         struct loaded_vmcs *loaded_vmcs = arg;
1519         int cpu = raw_smp_processor_id();
1520
1521         if (loaded_vmcs->cpu != cpu)
1522                 return; /* vcpu migration can race with cpu offline */
1523         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1524                 per_cpu(current_vmcs, cpu) = NULL;
1525         crash_disable_local_vmclear(cpu);
1526         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1527
1528         /*
1529          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1530          * is before setting loaded_vmcs->vcpu to -1 which is done in
1531          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1532          * then adds the vmcs into percpu list before it is deleted.
1533          */
1534         smp_wmb();
1535
1536         loaded_vmcs_init(loaded_vmcs);
1537         crash_enable_local_vmclear(cpu);
1538 }
1539
1540 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1541 {
1542         int cpu = loaded_vmcs->cpu;
1543
1544         if (cpu != -1)
1545                 smp_call_function_single(cpu,
1546                          __loaded_vmcs_clear, loaded_vmcs, 1);
1547 }
1548
1549 static inline void vpid_sync_vcpu_single(int vpid)
1550 {
1551         if (vpid == 0)
1552                 return;
1553
1554         if (cpu_has_vmx_invvpid_single())
1555                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1556 }
1557
1558 static inline void vpid_sync_vcpu_global(void)
1559 {
1560         if (cpu_has_vmx_invvpid_global())
1561                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1562 }
1563
1564 static inline void vpid_sync_context(int vpid)
1565 {
1566         if (cpu_has_vmx_invvpid_single())
1567                 vpid_sync_vcpu_single(vpid);
1568         else
1569                 vpid_sync_vcpu_global();
1570 }
1571
1572 static inline void ept_sync_global(void)
1573 {
1574         if (cpu_has_vmx_invept_global())
1575                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1576 }
1577
1578 static inline void ept_sync_context(u64 eptp)
1579 {
1580         if (enable_ept) {
1581                 if (cpu_has_vmx_invept_context())
1582                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1583                 else
1584                         ept_sync_global();
1585         }
1586 }
1587
1588 static __always_inline void vmcs_check16(unsigned long field)
1589 {
1590         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1591                          "16-bit accessor invalid for 64-bit field");
1592         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1593                          "16-bit accessor invalid for 64-bit high field");
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1595                          "16-bit accessor invalid for 32-bit high field");
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1597                          "16-bit accessor invalid for natural width field");
1598 }
1599
1600 static __always_inline void vmcs_check32(unsigned long field)
1601 {
1602         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1603                          "32-bit accessor invalid for 16-bit field");
1604         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1605                          "32-bit accessor invalid for natural width field");
1606 }
1607
1608 static __always_inline void vmcs_check64(unsigned long field)
1609 {
1610         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1611                          "64-bit accessor invalid for 16-bit field");
1612         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1613                          "64-bit accessor invalid for 64-bit high field");
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1615                          "64-bit accessor invalid for 32-bit field");
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1617                          "64-bit accessor invalid for natural width field");
1618 }
1619
1620 static __always_inline void vmcs_checkl(unsigned long field)
1621 {
1622         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1623                          "Natural width accessor invalid for 16-bit field");
1624         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1625                          "Natural width accessor invalid for 64-bit field");
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1627                          "Natural width accessor invalid for 64-bit high field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1629                          "Natural width accessor invalid for 32-bit field");
1630 }
1631
1632 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1633 {
1634         unsigned long value;
1635
1636         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1637                       : "=a"(value) : "d"(field) : "cc");
1638         return value;
1639 }
1640
1641 static __always_inline u16 vmcs_read16(unsigned long field)
1642 {
1643         vmcs_check16(field);
1644         return __vmcs_readl(field);
1645 }
1646
1647 static __always_inline u32 vmcs_read32(unsigned long field)
1648 {
1649         vmcs_check32(field);
1650         return __vmcs_readl(field);
1651 }
1652
1653 static __always_inline u64 vmcs_read64(unsigned long field)
1654 {
1655         vmcs_check64(field);
1656 #ifdef CONFIG_X86_64
1657         return __vmcs_readl(field);
1658 #else
1659         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1660 #endif
1661 }
1662
1663 static __always_inline unsigned long vmcs_readl(unsigned long field)
1664 {
1665         vmcs_checkl(field);
1666         return __vmcs_readl(field);
1667 }
1668
1669 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1670 {
1671         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1672                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1673         dump_stack();
1674 }
1675
1676 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1677 {
1678         u8 error;
1679
1680         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1681                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1682         if (unlikely(error))
1683                 vmwrite_error(field, value);
1684 }
1685
1686 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1687 {
1688         vmcs_check16(field);
1689         __vmcs_writel(field, value);
1690 }
1691
1692 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1693 {
1694         vmcs_check32(field);
1695         __vmcs_writel(field, value);
1696 }
1697
1698 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1699 {
1700         vmcs_check64(field);
1701         __vmcs_writel(field, value);
1702 #ifndef CONFIG_X86_64
1703         asm volatile ("");
1704         __vmcs_writel(field+1, value >> 32);
1705 #endif
1706 }
1707
1708 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1709 {
1710         vmcs_checkl(field);
1711         __vmcs_writel(field, value);
1712 }
1713
1714 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1715 {
1716         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1717                          "vmcs_clear_bits does not support 64-bit fields");
1718         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1719 }
1720
1721 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1722 {
1723         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1724                          "vmcs_set_bits does not support 64-bit fields");
1725         __vmcs_writel(field, __vmcs_readl(field) | mask);
1726 }
1727
1728 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1729 {
1730         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1731 }
1732
1733 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1734 {
1735         vmcs_write32(VM_ENTRY_CONTROLS, val);
1736         vmx->vm_entry_controls_shadow = val;
1737 }
1738
1739 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1740 {
1741         if (vmx->vm_entry_controls_shadow != val)
1742                 vm_entry_controls_init(vmx, val);
1743 }
1744
1745 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1746 {
1747         return vmx->vm_entry_controls_shadow;
1748 }
1749
1750
1751 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1752 {
1753         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1754 }
1755
1756 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1757 {
1758         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1759 }
1760
1761 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1762 {
1763         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1764 }
1765
1766 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1767 {
1768         vmcs_write32(VM_EXIT_CONTROLS, val);
1769         vmx->vm_exit_controls_shadow = val;
1770 }
1771
1772 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1773 {
1774         if (vmx->vm_exit_controls_shadow != val)
1775                 vm_exit_controls_init(vmx, val);
1776 }
1777
1778 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1779 {
1780         return vmx->vm_exit_controls_shadow;
1781 }
1782
1783
1784 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1785 {
1786         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1787 }
1788
1789 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1790 {
1791         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1792 }
1793
1794 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1795 {
1796         vmx->segment_cache.bitmask = 0;
1797 }
1798
1799 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1800                                        unsigned field)
1801 {
1802         bool ret;
1803         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1804
1805         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1806                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1807                 vmx->segment_cache.bitmask = 0;
1808         }
1809         ret = vmx->segment_cache.bitmask & mask;
1810         vmx->segment_cache.bitmask |= mask;
1811         return ret;
1812 }
1813
1814 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1815 {
1816         u16 *p = &vmx->segment_cache.seg[seg].selector;
1817
1818         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1819                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1820         return *p;
1821 }
1822
1823 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1824 {
1825         ulong *p = &vmx->segment_cache.seg[seg].base;
1826
1827         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1828                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1829         return *p;
1830 }
1831
1832 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1833 {
1834         u32 *p = &vmx->segment_cache.seg[seg].limit;
1835
1836         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1837                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1838         return *p;
1839 }
1840
1841 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1842 {
1843         u32 *p = &vmx->segment_cache.seg[seg].ar;
1844
1845         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1846                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1847         return *p;
1848 }
1849
1850 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1851 {
1852         u32 eb;
1853
1854         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1855              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1856         if ((vcpu->guest_debug &
1857              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1858             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1859                 eb |= 1u << BP_VECTOR;
1860         if (to_vmx(vcpu)->rmode.vm86_active)
1861                 eb = ~0;
1862         if (enable_ept)
1863                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1864
1865         /* When we are running a nested L2 guest and L1 specified for it a
1866          * certain exception bitmap, we must trap the same exceptions and pass
1867          * them to L1. When running L2, we will only handle the exceptions
1868          * specified above if L1 did not want them.
1869          */
1870         if (is_guest_mode(vcpu))
1871                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1872
1873         vmcs_write32(EXCEPTION_BITMAP, eb);
1874 }
1875
1876 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1877                 unsigned long entry, unsigned long exit)
1878 {
1879         vm_entry_controls_clearbit(vmx, entry);
1880         vm_exit_controls_clearbit(vmx, exit);
1881 }
1882
1883 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1884 {
1885         unsigned i;
1886         struct msr_autoload *m = &vmx->msr_autoload;
1887
1888         switch (msr) {
1889         case MSR_EFER:
1890                 if (cpu_has_load_ia32_efer) {
1891                         clear_atomic_switch_msr_special(vmx,
1892                                         VM_ENTRY_LOAD_IA32_EFER,
1893                                         VM_EXIT_LOAD_IA32_EFER);
1894                         return;
1895                 }
1896                 break;
1897         case MSR_CORE_PERF_GLOBAL_CTRL:
1898                 if (cpu_has_load_perf_global_ctrl) {
1899                         clear_atomic_switch_msr_special(vmx,
1900                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1901                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1902                         return;
1903                 }
1904                 break;
1905         }
1906
1907         for (i = 0; i < m->nr; ++i)
1908                 if (m->guest[i].index == msr)
1909                         break;
1910
1911         if (i == m->nr)
1912                 return;
1913         --m->nr;
1914         m->guest[i] = m->guest[m->nr];
1915         m->host[i] = m->host[m->nr];
1916         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1917         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1918 }
1919
1920 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1921                 unsigned long entry, unsigned long exit,
1922                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1923                 u64 guest_val, u64 host_val)
1924 {
1925         vmcs_write64(guest_val_vmcs, guest_val);
1926         vmcs_write64(host_val_vmcs, host_val);
1927         vm_entry_controls_setbit(vmx, entry);
1928         vm_exit_controls_setbit(vmx, exit);
1929 }
1930
1931 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1932                                   u64 guest_val, u64 host_val)
1933 {
1934         unsigned i;
1935         struct msr_autoload *m = &vmx->msr_autoload;
1936
1937         switch (msr) {
1938         case MSR_EFER:
1939                 if (cpu_has_load_ia32_efer) {
1940                         add_atomic_switch_msr_special(vmx,
1941                                         VM_ENTRY_LOAD_IA32_EFER,
1942                                         VM_EXIT_LOAD_IA32_EFER,
1943                                         GUEST_IA32_EFER,
1944                                         HOST_IA32_EFER,
1945                                         guest_val, host_val);
1946                         return;
1947                 }
1948                 break;
1949         case MSR_CORE_PERF_GLOBAL_CTRL:
1950                 if (cpu_has_load_perf_global_ctrl) {
1951                         add_atomic_switch_msr_special(vmx,
1952                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1953                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1954                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1955                                         HOST_IA32_PERF_GLOBAL_CTRL,
1956                                         guest_val, host_val);
1957                         return;
1958                 }
1959                 break;
1960         case MSR_IA32_PEBS_ENABLE:
1961                 /* PEBS needs a quiescent period after being disabled (to write
1962                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1963                  * provide that period, so a CPU could write host's record into
1964                  * guest's memory.
1965                  */
1966                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1967         }
1968
1969         for (i = 0; i < m->nr; ++i)
1970                 if (m->guest[i].index == msr)
1971                         break;
1972
1973         if (i == NR_AUTOLOAD_MSRS) {
1974                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1975                                 "Can't add msr %x\n", msr);
1976                 return;
1977         } else if (i == m->nr) {
1978                 ++m->nr;
1979                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1980                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1981         }
1982
1983         m->guest[i].index = msr;
1984         m->guest[i].value = guest_val;
1985         m->host[i].index = msr;
1986         m->host[i].value = host_val;
1987 }
1988
1989 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1990 {
1991         u64 guest_efer = vmx->vcpu.arch.efer;
1992         u64 ignore_bits = 0;
1993
1994         if (!enable_ept) {
1995                 /*
1996                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1997                  * host CPUID is more efficient than testing guest CPUID
1998                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1999                  */
2000                 if (boot_cpu_has(X86_FEATURE_SMEP))
2001                         guest_efer |= EFER_NX;
2002                 else if (!(guest_efer & EFER_NX))
2003                         ignore_bits |= EFER_NX;
2004         }
2005
2006         /*
2007          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2008          */
2009         ignore_bits |= EFER_SCE;
2010 #ifdef CONFIG_X86_64
2011         ignore_bits |= EFER_LMA | EFER_LME;
2012         /* SCE is meaningful only in long mode on Intel */
2013         if (guest_efer & EFER_LMA)
2014                 ignore_bits &= ~(u64)EFER_SCE;
2015 #endif
2016
2017         clear_atomic_switch_msr(vmx, MSR_EFER);
2018
2019         /*
2020          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2021          * On CPUs that support "load IA32_EFER", always switch EFER
2022          * atomically, since it's faster than switching it manually.
2023          */
2024         if (cpu_has_load_ia32_efer ||
2025             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2026                 if (!(guest_efer & EFER_LMA))
2027                         guest_efer &= ~EFER_LME;
2028                 if (guest_efer != host_efer)
2029                         add_atomic_switch_msr(vmx, MSR_EFER,
2030                                               guest_efer, host_efer);
2031                 return false;
2032         } else {
2033                 guest_efer &= ~ignore_bits;
2034                 guest_efer |= host_efer & ignore_bits;
2035
2036                 vmx->guest_msrs[efer_offset].data = guest_efer;
2037                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2038
2039                 return true;
2040         }
2041 }
2042
2043 #ifdef CONFIG_X86_32
2044 /*
2045  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2046  * VMCS rather than the segment table.  KVM uses this helper to figure
2047  * out the current bases to poke them into the VMCS before entry.
2048  */
2049 static unsigned long segment_base(u16 selector)
2050 {
2051         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2052         struct desc_struct *table;
2053         unsigned long v;
2054
2055         if (!(selector & ~SEGMENT_RPL_MASK))
2056                 return 0;
2057
2058         table = (struct desc_struct *)gdt->address;
2059
2060         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2061                 u16 ldt_selector = kvm_read_ldt();
2062
2063                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2064                         return 0;
2065
2066                 table = (struct desc_struct *)segment_base(ldt_selector);
2067         }
2068         v = get_desc_base(&table[selector >> 3]);
2069         return v;
2070 }
2071 #endif
2072
2073 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2074 {
2075         struct vcpu_vmx *vmx = to_vmx(vcpu);
2076         int i;
2077
2078         if (vmx->host_state.loaded)
2079                 return;
2080
2081         vmx->host_state.loaded = 1;
2082         /*
2083          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2084          * allow segment selectors with cpl > 0 or ti == 1.
2085          */
2086         vmx->host_state.ldt_sel = kvm_read_ldt();
2087         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2088         savesegment(fs, vmx->host_state.fs_sel);
2089         if (!(vmx->host_state.fs_sel & 7)) {
2090                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2091                 vmx->host_state.fs_reload_needed = 0;
2092         } else {
2093                 vmcs_write16(HOST_FS_SELECTOR, 0);
2094                 vmx->host_state.fs_reload_needed = 1;
2095         }
2096         savesegment(gs, vmx->host_state.gs_sel);
2097         if (!(vmx->host_state.gs_sel & 7))
2098                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2099         else {
2100                 vmcs_write16(HOST_GS_SELECTOR, 0);
2101                 vmx->host_state.gs_ldt_reload_needed = 1;
2102         }
2103
2104 #ifdef CONFIG_X86_64
2105         savesegment(ds, vmx->host_state.ds_sel);
2106         savesegment(es, vmx->host_state.es_sel);
2107 #endif
2108
2109 #ifdef CONFIG_X86_64
2110         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2111         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2112 #else
2113         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2114         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2115 #endif
2116
2117 #ifdef CONFIG_X86_64
2118         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2119         if (is_long_mode(&vmx->vcpu))
2120                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2121 #endif
2122         if (boot_cpu_has(X86_FEATURE_MPX))
2123                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2124         for (i = 0; i < vmx->save_nmsrs; ++i)
2125                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2126                                    vmx->guest_msrs[i].data,
2127                                    vmx->guest_msrs[i].mask);
2128 }
2129
2130 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2131 {
2132         if (!vmx->host_state.loaded)
2133                 return;
2134
2135         ++vmx->vcpu.stat.host_state_reload;
2136         vmx->host_state.loaded = 0;
2137 #ifdef CONFIG_X86_64
2138         if (is_long_mode(&vmx->vcpu))
2139                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2140 #endif
2141         if (vmx->host_state.gs_ldt_reload_needed) {
2142                 kvm_load_ldt(vmx->host_state.ldt_sel);
2143 #ifdef CONFIG_X86_64
2144                 load_gs_index(vmx->host_state.gs_sel);
2145 #else
2146                 loadsegment(gs, vmx->host_state.gs_sel);
2147 #endif
2148         }
2149         if (vmx->host_state.fs_reload_needed)
2150                 loadsegment(fs, vmx->host_state.fs_sel);
2151 #ifdef CONFIG_X86_64
2152         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2153                 loadsegment(ds, vmx->host_state.ds_sel);
2154                 loadsegment(es, vmx->host_state.es_sel);
2155         }
2156 #endif
2157         invalidate_tss_limit();
2158 #ifdef CONFIG_X86_64
2159         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2160 #endif
2161         if (vmx->host_state.msr_host_bndcfgs)
2162                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2163         load_gdt(this_cpu_ptr(&host_gdt));
2164 }
2165
2166 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2167 {
2168         preempt_disable();
2169         __vmx_load_host_state(vmx);
2170         preempt_enable();
2171 }
2172
2173 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2174 {
2175         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2176         struct pi_desc old, new;
2177         unsigned int dest;
2178
2179         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2180                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2181                 !kvm_vcpu_apicv_active(vcpu))
2182                 return;
2183
2184         do {
2185                 old.control = new.control = pi_desc->control;
2186
2187                 /*
2188                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2189                  * are two possible cases:
2190                  * 1. After running 'pre_block', context switch
2191                  *    happened. For this case, 'sn' was set in
2192                  *    vmx_vcpu_put(), so we need to clear it here.
2193                  * 2. After running 'pre_block', we were blocked,
2194                  *    and woken up by some other guy. For this case,
2195                  *    we don't need to do anything, 'pi_post_block'
2196                  *    will do everything for us. However, we cannot
2197                  *    check whether it is case #1 or case #2 here
2198                  *    (maybe, not needed), so we also clear sn here,
2199                  *    I think it is not a big deal.
2200                  */
2201                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2202                         if (vcpu->cpu != cpu) {
2203                                 dest = cpu_physical_id(cpu);
2204
2205                                 if (x2apic_enabled())
2206                                         new.ndst = dest;
2207                                 else
2208                                         new.ndst = (dest << 8) & 0xFF00;
2209                         }
2210
2211                         /* set 'NV' to 'notification vector' */
2212                         new.nv = POSTED_INTR_VECTOR;
2213                 }
2214
2215                 /* Allow posting non-urgent interrupts */
2216                 new.sn = 0;
2217         } while (cmpxchg(&pi_desc->control, old.control,
2218                         new.control) != old.control);
2219 }
2220
2221 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2222 {
2223         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2224         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2225 }
2226
2227 /*
2228  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2229  * vcpu mutex is already taken.
2230  */
2231 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2232 {
2233         struct vcpu_vmx *vmx = to_vmx(vcpu);
2234         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2235         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2236
2237         if (!vmm_exclusive)
2238                 kvm_cpu_vmxon(phys_addr);
2239         else if (!already_loaded)
2240                 loaded_vmcs_clear(vmx->loaded_vmcs);
2241
2242         if (!already_loaded) {
2243                 local_irq_disable();
2244                 crash_disable_local_vmclear(cpu);
2245
2246                 /*
2247                  * Read loaded_vmcs->cpu should be before fetching
2248                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2249                  * See the comments in __loaded_vmcs_clear().
2250                  */
2251                 smp_rmb();
2252
2253                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2254                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2255                 crash_enable_local_vmclear(cpu);
2256                 local_irq_enable();
2257         }
2258
2259         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2260                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2261                 vmcs_load(vmx->loaded_vmcs->vmcs);
2262         }
2263
2264         if (!already_loaded) {
2265                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2266                 unsigned long sysenter_esp;
2267
2268                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2269
2270                 /*
2271                  * Linux uses per-cpu TSS and GDT, so set these when switching
2272                  * processors.  See 22.2.4.
2273                  */
2274                 vmcs_writel(HOST_TR_BASE,
2275                             (unsigned long)this_cpu_ptr(&cpu_tss));
2276                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2277
2278                 /*
2279                  * VM exits change the host TR limit to 0x67 after a VM
2280                  * exit.  This is okay, since 0x67 covers everything except
2281                  * the IO bitmap and have have code to handle the IO bitmap
2282                  * being lost after a VM exit.
2283                  */
2284                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2285
2286                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2287                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2288
2289                 vmx->loaded_vmcs->cpu = cpu;
2290         }
2291
2292         /* Setup TSC multiplier */
2293         if (kvm_has_tsc_control &&
2294             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2295                 decache_tsc_multiplier(vmx);
2296
2297         vmx_vcpu_pi_load(vcpu, cpu);
2298         vmx->host_pkru = read_pkru();
2299 }
2300
2301 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2302 {
2303         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2304
2305         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2306                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2307                 !kvm_vcpu_apicv_active(vcpu))
2308                 return;
2309
2310         /* Set SN when the vCPU is preempted */
2311         if (vcpu->preempted)
2312                 pi_set_sn(pi_desc);
2313 }
2314
2315 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2316 {
2317         vmx_vcpu_pi_put(vcpu);
2318
2319         __vmx_load_host_state(to_vmx(vcpu));
2320         if (!vmm_exclusive) {
2321                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2322                 vcpu->cpu = -1;
2323                 kvm_cpu_vmxoff();
2324         }
2325 }
2326
2327 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2328
2329 /*
2330  * Return the cr0 value that a nested guest would read. This is a combination
2331  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2332  * its hypervisor (cr0_read_shadow).
2333  */
2334 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2335 {
2336         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2337                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2338 }
2339 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2340 {
2341         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2342                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2343 }
2344
2345 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2346 {
2347         unsigned long rflags, save_rflags;
2348
2349         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2350                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2351                 rflags = vmcs_readl(GUEST_RFLAGS);
2352                 if (to_vmx(vcpu)->rmode.vm86_active) {
2353                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2354                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2355                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2356                 }
2357                 to_vmx(vcpu)->rflags = rflags;
2358         }
2359         return to_vmx(vcpu)->rflags;
2360 }
2361
2362 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2363 {
2364         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2365         to_vmx(vcpu)->rflags = rflags;
2366         if (to_vmx(vcpu)->rmode.vm86_active) {
2367                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2368                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2369         }
2370         vmcs_writel(GUEST_RFLAGS, rflags);
2371 }
2372
2373 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2374 {
2375         return to_vmx(vcpu)->guest_pkru;
2376 }
2377
2378 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2379 {
2380         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2381         int ret = 0;
2382
2383         if (interruptibility & GUEST_INTR_STATE_STI)
2384                 ret |= KVM_X86_SHADOW_INT_STI;
2385         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2386                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2387
2388         return ret;
2389 }
2390
2391 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2392 {
2393         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2394         u32 interruptibility = interruptibility_old;
2395
2396         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2397
2398         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2399                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2400         else if (mask & KVM_X86_SHADOW_INT_STI)
2401                 interruptibility |= GUEST_INTR_STATE_STI;
2402
2403         if ((interruptibility != interruptibility_old))
2404                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2405 }
2406
2407 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2408 {
2409         unsigned long rip;
2410
2411         rip = kvm_rip_read(vcpu);
2412         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2413         kvm_rip_write(vcpu, rip);
2414
2415         /* skipping an emulated instruction also counts */
2416         vmx_set_interrupt_shadow(vcpu, 0);
2417 }
2418
2419 /*
2420  * KVM wants to inject page-faults which it got to the guest. This function
2421  * checks whether in a nested guest, we need to inject them to L1 or L2.
2422  */
2423 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2424 {
2425         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2426
2427         if (!(vmcs12->exception_bitmap & (1u << nr)))
2428                 return 0;
2429
2430         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2431                           vmcs_read32(VM_EXIT_INTR_INFO),
2432                           vmcs_readl(EXIT_QUALIFICATION));
2433         return 1;
2434 }
2435
2436 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2437                                 bool has_error_code, u32 error_code,
2438                                 bool reinject)
2439 {
2440         struct vcpu_vmx *vmx = to_vmx(vcpu);
2441         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2442
2443         if (!reinject && is_guest_mode(vcpu) &&
2444             nested_vmx_check_exception(vcpu, nr))
2445                 return;
2446
2447         if (has_error_code) {
2448                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2449                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2450         }
2451
2452         if (vmx->rmode.vm86_active) {
2453                 int inc_eip = 0;
2454                 if (kvm_exception_is_soft(nr))
2455                         inc_eip = vcpu->arch.event_exit_inst_len;
2456                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2457                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2458                 return;
2459         }
2460
2461         if (kvm_exception_is_soft(nr)) {
2462                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2463                              vmx->vcpu.arch.event_exit_inst_len);
2464                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2465         } else
2466                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2467
2468         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2469 }
2470
2471 static bool vmx_rdtscp_supported(void)
2472 {
2473         return cpu_has_vmx_rdtscp();
2474 }
2475
2476 static bool vmx_invpcid_supported(void)
2477 {
2478         return cpu_has_vmx_invpcid() && enable_ept;
2479 }
2480
2481 /*
2482  * Swap MSR entry in host/guest MSR entry array.
2483  */
2484 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2485 {
2486         struct shared_msr_entry tmp;
2487
2488         tmp = vmx->guest_msrs[to];
2489         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2490         vmx->guest_msrs[from] = tmp;
2491 }
2492
2493 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2494 {
2495         unsigned long *msr_bitmap;
2496
2497         if (is_guest_mode(vcpu))
2498                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2499         else if (cpu_has_secondary_exec_ctrls() &&
2500                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2501                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2502                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2503                         if (is_long_mode(vcpu))
2504                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2505                         else
2506                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2507                 } else {
2508                         if (is_long_mode(vcpu))
2509                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2510                         else
2511                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2512                 }
2513         } else {
2514                 if (is_long_mode(vcpu))
2515                         msr_bitmap = vmx_msr_bitmap_longmode;
2516                 else
2517                         msr_bitmap = vmx_msr_bitmap_legacy;
2518         }
2519
2520         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2521 }
2522
2523 /*
2524  * Set up the vmcs to automatically save and restore system
2525  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2526  * mode, as fiddling with msrs is very expensive.
2527  */
2528 static void setup_msrs(struct vcpu_vmx *vmx)
2529 {
2530         int save_nmsrs, index;
2531
2532         save_nmsrs = 0;
2533 #ifdef CONFIG_X86_64
2534         if (is_long_mode(&vmx->vcpu)) {
2535                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2536                 if (index >= 0)
2537                         move_msr_up(vmx, index, save_nmsrs++);
2538                 index = __find_msr_index(vmx, MSR_LSTAR);
2539                 if (index >= 0)
2540                         move_msr_up(vmx, index, save_nmsrs++);
2541                 index = __find_msr_index(vmx, MSR_CSTAR);
2542                 if (index >= 0)
2543                         move_msr_up(vmx, index, save_nmsrs++);
2544                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2545                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2546                         move_msr_up(vmx, index, save_nmsrs++);
2547                 /*
2548                  * MSR_STAR is only needed on long mode guests, and only
2549                  * if efer.sce is enabled.
2550                  */
2551                 index = __find_msr_index(vmx, MSR_STAR);
2552                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2553                         move_msr_up(vmx, index, save_nmsrs++);
2554         }
2555 #endif
2556         index = __find_msr_index(vmx, MSR_EFER);
2557         if (index >= 0 && update_transition_efer(vmx, index))
2558                 move_msr_up(vmx, index, save_nmsrs++);
2559
2560         vmx->save_nmsrs = save_nmsrs;
2561
2562         if (cpu_has_vmx_msr_bitmap())
2563                 vmx_set_msr_bitmap(&vmx->vcpu);
2564 }
2565
2566 /*
2567  * reads and returns guest's timestamp counter "register"
2568  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2569  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2570  */
2571 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2572 {
2573         u64 host_tsc, tsc_offset;
2574
2575         host_tsc = rdtsc();
2576         tsc_offset = vmcs_read64(TSC_OFFSET);
2577         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2578 }
2579
2580 /*
2581  * writes 'offset' into guest's timestamp counter offset register
2582  */
2583 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2584 {
2585         if (is_guest_mode(vcpu)) {
2586                 /*
2587                  * We're here if L1 chose not to trap WRMSR to TSC. According
2588                  * to the spec, this should set L1's TSC; The offset that L1
2589                  * set for L2 remains unchanged, and still needs to be added
2590                  * to the newly set TSC to get L2's TSC.
2591                  */
2592                 struct vmcs12 *vmcs12;
2593                 /* recalculate vmcs02.TSC_OFFSET: */
2594                 vmcs12 = get_vmcs12(vcpu);
2595                 vmcs_write64(TSC_OFFSET, offset +
2596                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2597                          vmcs12->tsc_offset : 0));
2598         } else {
2599                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2600                                            vmcs_read64(TSC_OFFSET), offset);
2601                 vmcs_write64(TSC_OFFSET, offset);
2602         }
2603 }
2604
2605 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2606 {
2607         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2608         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2609 }
2610
2611 /*
2612  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2613  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2614  * all guests if the "nested" module option is off, and can also be disabled
2615  * for a single guest by disabling its VMX cpuid bit.
2616  */
2617 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2618 {
2619         return nested && guest_cpuid_has_vmx(vcpu);
2620 }
2621
2622 /*
2623  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2624  * returned for the various VMX controls MSRs when nested VMX is enabled.
2625  * The same values should also be used to verify that vmcs12 control fields are
2626  * valid during nested entry from L1 to L2.
2627  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2628  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2629  * bit in the high half is on if the corresponding bit in the control field
2630  * may be on. See also vmx_control_verify().
2631  */
2632 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2633 {
2634         /*
2635          * Note that as a general rule, the high half of the MSRs (bits in
2636          * the control fields which may be 1) should be initialized by the
2637          * intersection of the underlying hardware's MSR (i.e., features which
2638          * can be supported) and the list of features we want to expose -
2639          * because they are known to be properly supported in our code.
2640          * Also, usually, the low half of the MSRs (bits which must be 1) can
2641          * be set to 0, meaning that L1 may turn off any of these bits. The
2642          * reason is that if one of these bits is necessary, it will appear
2643          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2644          * fields of vmcs01 and vmcs02, will turn these bits off - and
2645          * nested_vmx_exit_handled() will not pass related exits to L1.
2646          * These rules have exceptions below.
2647          */
2648
2649         /* pin-based controls */
2650         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2651                 vmx->nested.nested_vmx_pinbased_ctls_low,
2652                 vmx->nested.nested_vmx_pinbased_ctls_high);
2653         vmx->nested.nested_vmx_pinbased_ctls_low |=
2654                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2655         vmx->nested.nested_vmx_pinbased_ctls_high &=
2656                 PIN_BASED_EXT_INTR_MASK |
2657                 PIN_BASED_NMI_EXITING |
2658                 PIN_BASED_VIRTUAL_NMIS;
2659         vmx->nested.nested_vmx_pinbased_ctls_high |=
2660                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2661                 PIN_BASED_VMX_PREEMPTION_TIMER;
2662         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2663                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2664                         PIN_BASED_POSTED_INTR;
2665
2666         /* exit controls */
2667         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2668                 vmx->nested.nested_vmx_exit_ctls_low,
2669                 vmx->nested.nested_vmx_exit_ctls_high);
2670         vmx->nested.nested_vmx_exit_ctls_low =
2671                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2672
2673         vmx->nested.nested_vmx_exit_ctls_high &=
2674 #ifdef CONFIG_X86_64
2675                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2676 #endif
2677                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2678         vmx->nested.nested_vmx_exit_ctls_high |=
2679                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2680                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2681                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2682
2683         if (kvm_mpx_supported())
2684                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2685
2686         /* We support free control of debug control saving. */
2687         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2688
2689         /* entry controls */
2690         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2691                 vmx->nested.nested_vmx_entry_ctls_low,
2692                 vmx->nested.nested_vmx_entry_ctls_high);
2693         vmx->nested.nested_vmx_entry_ctls_low =
2694                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2695         vmx->nested.nested_vmx_entry_ctls_high &=
2696 #ifdef CONFIG_X86_64
2697                 VM_ENTRY_IA32E_MODE |
2698 #endif
2699                 VM_ENTRY_LOAD_IA32_PAT;
2700         vmx->nested.nested_vmx_entry_ctls_high |=
2701                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2702         if (kvm_mpx_supported())
2703                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2704
2705         /* We support free control of debug control loading. */
2706         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2707
2708         /* cpu-based controls */
2709         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2710                 vmx->nested.nested_vmx_procbased_ctls_low,
2711                 vmx->nested.nested_vmx_procbased_ctls_high);
2712         vmx->nested.nested_vmx_procbased_ctls_low =
2713                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2714         vmx->nested.nested_vmx_procbased_ctls_high &=
2715                 CPU_BASED_VIRTUAL_INTR_PENDING |
2716                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2717                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2718                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2719                 CPU_BASED_CR3_STORE_EXITING |
2720 #ifdef CONFIG_X86_64
2721                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2722 #endif
2723                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2724                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2725                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2726                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2727                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2728         /*
2729          * We can allow some features even when not supported by the
2730          * hardware. For example, L1 can specify an MSR bitmap - and we
2731          * can use it to avoid exits to L1 - even when L0 runs L2
2732          * without MSR bitmaps.
2733          */
2734         vmx->nested.nested_vmx_procbased_ctls_high |=
2735                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2736                 CPU_BASED_USE_MSR_BITMAPS;
2737
2738         /* We support free control of CR3 access interception. */
2739         vmx->nested.nested_vmx_procbased_ctls_low &=
2740                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2741
2742         /* secondary cpu-based controls */
2743         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2744                 vmx->nested.nested_vmx_secondary_ctls_low,
2745                 vmx->nested.nested_vmx_secondary_ctls_high);
2746         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2747         vmx->nested.nested_vmx_secondary_ctls_high &=
2748                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2749                 SECONDARY_EXEC_RDTSCP |
2750                 SECONDARY_EXEC_DESC |
2751                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2752                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2753                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2754                 SECONDARY_EXEC_WBINVD_EXITING |
2755                 SECONDARY_EXEC_XSAVES;
2756
2757         if (enable_ept) {
2758                 /* nested EPT: emulate EPT also to L1 */
2759                 vmx->nested.nested_vmx_secondary_ctls_high |=
2760                         SECONDARY_EXEC_ENABLE_EPT;
2761                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2762                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2763                          VMX_EPT_INVEPT_BIT;
2764                 if (cpu_has_vmx_ept_execute_only())
2765                         vmx->nested.nested_vmx_ept_caps |=
2766                                 VMX_EPT_EXECUTE_ONLY_BIT;
2767                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2768                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2769                         VMX_EPT_EXTENT_CONTEXT_BIT;
2770         } else
2771                 vmx->nested.nested_vmx_ept_caps = 0;
2772
2773         /*
2774          * Old versions of KVM use the single-context version without
2775          * checking for support, so declare that it is supported even
2776          * though it is treated as global context.  The alternative is
2777          * not failing the single-context invvpid, and it is worse.
2778          */
2779         if (enable_vpid) {
2780                 vmx->nested.nested_vmx_secondary_ctls_high |=
2781                         SECONDARY_EXEC_ENABLE_VPID;
2782                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2783                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2784         } else
2785                 vmx->nested.nested_vmx_vpid_caps = 0;
2786
2787         if (enable_unrestricted_guest)
2788                 vmx->nested.nested_vmx_secondary_ctls_high |=
2789                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2790
2791         /* miscellaneous data */
2792         rdmsr(MSR_IA32_VMX_MISC,
2793                 vmx->nested.nested_vmx_misc_low,
2794                 vmx->nested.nested_vmx_misc_high);
2795         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2796         vmx->nested.nested_vmx_misc_low |=
2797                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2798                 VMX_MISC_ACTIVITY_HLT;
2799         vmx->nested.nested_vmx_misc_high = 0;
2800
2801         /*
2802          * This MSR reports some information about VMX support. We
2803          * should return information about the VMX we emulate for the
2804          * guest, and the VMCS structure we give it - not about the
2805          * VMX support of the underlying hardware.
2806          */
2807         vmx->nested.nested_vmx_basic =
2808                 VMCS12_REVISION |
2809                 VMX_BASIC_TRUE_CTLS |
2810                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2811                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2812
2813         if (cpu_has_vmx_basic_inout())
2814                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2815
2816         /*
2817          * These MSRs specify bits which the guest must keep fixed on
2818          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2819          * We picked the standard core2 setting.
2820          */
2821 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2822 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2823         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2824         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2825
2826         /* These MSRs specify bits which the guest must keep fixed off. */
2827         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2828         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2829
2830         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2831         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2832 }
2833
2834 /*
2835  * if fixed0[i] == 1: val[i] must be 1
2836  * if fixed1[i] == 0: val[i] must be 0
2837  */
2838 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2839 {
2840         return ((val & fixed1) | fixed0) == val;
2841 }
2842
2843 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2844 {
2845         return fixed_bits_valid(control, low, high);
2846 }
2847
2848 static inline u64 vmx_control_msr(u32 low, u32 high)
2849 {
2850         return low | ((u64)high << 32);
2851 }
2852
2853 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2854 {
2855         superset &= mask;
2856         subset &= mask;
2857
2858         return (superset | subset) == superset;
2859 }
2860
2861 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2862 {
2863         const u64 feature_and_reserved =
2864                 /* feature (except bit 48; see below) */
2865                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2866                 /* reserved */
2867                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2868         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2869
2870         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2871                 return -EINVAL;
2872
2873         /*
2874          * KVM does not emulate a version of VMX that constrains physical
2875          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2876          */
2877         if (data & BIT_ULL(48))
2878                 return -EINVAL;
2879
2880         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2881             vmx_basic_vmcs_revision_id(data))
2882                 return -EINVAL;
2883
2884         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2885                 return -EINVAL;
2886
2887         vmx->nested.nested_vmx_basic = data;
2888         return 0;
2889 }
2890
2891 static int
2892 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2893 {
2894         u64 supported;
2895         u32 *lowp, *highp;
2896
2897         switch (msr_index) {
2898         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2899                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2900                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2901                 break;
2902         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2903                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2904                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2905                 break;
2906         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2907                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2908                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2909                 break;
2910         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2911                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2912                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2913                 break;
2914         case MSR_IA32_VMX_PROCBASED_CTLS2:
2915                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2916                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2917                 break;
2918         default:
2919                 BUG();
2920         }
2921
2922         supported = vmx_control_msr(*lowp, *highp);
2923
2924         /* Check must-be-1 bits are still 1. */
2925         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2926                 return -EINVAL;
2927
2928         /* Check must-be-0 bits are still 0. */
2929         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2930                 return -EINVAL;
2931
2932         *lowp = data;
2933         *highp = data >> 32;
2934         return 0;
2935 }
2936
2937 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2938 {
2939         const u64 feature_and_reserved_bits =
2940                 /* feature */
2941                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2942                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2943                 /* reserved */
2944                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2945         u64 vmx_misc;
2946
2947         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2948                                    vmx->nested.nested_vmx_misc_high);
2949
2950         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2951                 return -EINVAL;
2952
2953         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2954              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2955             vmx_misc_preemption_timer_rate(data) !=
2956             vmx_misc_preemption_timer_rate(vmx_misc))
2957                 return -EINVAL;
2958
2959         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2960                 return -EINVAL;
2961
2962         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2963                 return -EINVAL;
2964
2965         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2966                 return -EINVAL;
2967
2968         vmx->nested.nested_vmx_misc_low = data;
2969         vmx->nested.nested_vmx_misc_high = data >> 32;
2970         return 0;
2971 }
2972
2973 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2974 {
2975         u64 vmx_ept_vpid_cap;
2976
2977         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2978                                            vmx->nested.nested_vmx_vpid_caps);
2979
2980         /* Every bit is either reserved or a feature bit. */
2981         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2982                 return -EINVAL;
2983
2984         vmx->nested.nested_vmx_ept_caps = data;
2985         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2986         return 0;
2987 }
2988
2989 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2990 {
2991         u64 *msr;
2992
2993         switch (msr_index) {
2994         case MSR_IA32_VMX_CR0_FIXED0:
2995                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
2996                 break;
2997         case MSR_IA32_VMX_CR4_FIXED0:
2998                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
2999                 break;
3000         default:
3001                 BUG();
3002         }
3003
3004         /*
3005          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3006          * must be 1 in the restored value.
3007          */
3008         if (!is_bitwise_subset(data, *msr, -1ULL))
3009                 return -EINVAL;
3010
3011         *msr = data;
3012         return 0;
3013 }
3014
3015 /*
3016  * Called when userspace is restoring VMX MSRs.
3017  *
3018  * Returns 0 on success, non-0 otherwise.
3019  */
3020 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3021 {
3022         struct vcpu_vmx *vmx = to_vmx(vcpu);
3023
3024         switch (msr_index) {
3025         case MSR_IA32_VMX_BASIC:
3026                 return vmx_restore_vmx_basic(vmx, data);
3027         case MSR_IA32_VMX_PINBASED_CTLS:
3028         case MSR_IA32_VMX_PROCBASED_CTLS:
3029         case MSR_IA32_VMX_EXIT_CTLS:
3030         case MSR_IA32_VMX_ENTRY_CTLS:
3031                 /*
3032                  * The "non-true" VMX capability MSRs are generated from the
3033                  * "true" MSRs, so we do not support restoring them directly.
3034                  *
3035                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3036                  * should restore the "true" MSRs with the must-be-1 bits
3037                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3038                  * DEFAULT SETTINGS".
3039                  */
3040                 return -EINVAL;
3041         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3042         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3043         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3044         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3045         case MSR_IA32_VMX_PROCBASED_CTLS2:
3046                 return vmx_restore_control_msr(vmx, msr_index, data);
3047         case MSR_IA32_VMX_MISC:
3048                 return vmx_restore_vmx_misc(vmx, data);
3049         case MSR_IA32_VMX_CR0_FIXED0:
3050         case MSR_IA32_VMX_CR4_FIXED0:
3051                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3052         case MSR_IA32_VMX_CR0_FIXED1:
3053         case MSR_IA32_VMX_CR4_FIXED1:
3054                 /*
3055                  * These MSRs are generated based on the vCPU's CPUID, so we
3056                  * do not support restoring them directly.
3057                  */
3058                 return -EINVAL;
3059         case MSR_IA32_VMX_EPT_VPID_CAP:
3060                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3061         case MSR_IA32_VMX_VMCS_ENUM:
3062                 vmx->nested.nested_vmx_vmcs_enum = data;
3063                 return 0;
3064         default:
3065                 /*
3066                  * The rest of the VMX capability MSRs do not support restore.
3067                  */
3068                 return -EINVAL;
3069         }
3070 }
3071
3072 /* Returns 0 on success, non-0 otherwise. */
3073 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3074 {
3075         struct vcpu_vmx *vmx = to_vmx(vcpu);
3076
3077         switch (msr_index) {
3078         case MSR_IA32_VMX_BASIC:
3079                 *pdata = vmx->nested.nested_vmx_basic;
3080                 break;
3081         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3082         case MSR_IA32_VMX_PINBASED_CTLS:
3083                 *pdata = vmx_control_msr(
3084                         vmx->nested.nested_vmx_pinbased_ctls_low,
3085                         vmx->nested.nested_vmx_pinbased_ctls_high);
3086                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3087                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3088                 break;
3089         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3090         case MSR_IA32_VMX_PROCBASED_CTLS:
3091                 *pdata = vmx_control_msr(
3092                         vmx->nested.nested_vmx_procbased_ctls_low,
3093                         vmx->nested.nested_vmx_procbased_ctls_high);
3094                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3095                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3096                 break;
3097         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3098         case MSR_IA32_VMX_EXIT_CTLS:
3099                 *pdata = vmx_control_msr(
3100                         vmx->nested.nested_vmx_exit_ctls_low,
3101                         vmx->nested.nested_vmx_exit_ctls_high);
3102                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3103                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3104                 break;
3105         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3106         case MSR_IA32_VMX_ENTRY_CTLS:
3107                 *pdata = vmx_control_msr(
3108                         vmx->nested.nested_vmx_entry_ctls_low,
3109                         vmx->nested.nested_vmx_entry_ctls_high);
3110                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3111                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3112                 break;
3113         case MSR_IA32_VMX_MISC:
3114                 *pdata = vmx_control_msr(
3115                         vmx->nested.nested_vmx_misc_low,
3116                         vmx->nested.nested_vmx_misc_high);
3117                 break;
3118         case MSR_IA32_VMX_CR0_FIXED0:
3119                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3120                 break;
3121         case MSR_IA32_VMX_CR0_FIXED1:
3122                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3123                 break;
3124         case MSR_IA32_VMX_CR4_FIXED0:
3125                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3126                 break;
3127         case MSR_IA32_VMX_CR4_FIXED1:
3128                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3129                 break;
3130         case MSR_IA32_VMX_VMCS_ENUM:
3131                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3132                 break;
3133         case MSR_IA32_VMX_PROCBASED_CTLS2:
3134                 *pdata = vmx_control_msr(
3135                         vmx->nested.nested_vmx_secondary_ctls_low,
3136                         vmx->nested.nested_vmx_secondary_ctls_high);
3137                 break;
3138         case MSR_IA32_VMX_EPT_VPID_CAP:
3139                 *pdata = vmx->nested.nested_vmx_ept_caps |
3140                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3141                 break;
3142         default:
3143                 return 1;
3144         }
3145
3146         return 0;
3147 }
3148
3149 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3150                                                  uint64_t val)
3151 {
3152         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3153
3154         return !(val & ~valid_bits);
3155 }
3156
3157 /*
3158  * Reads an msr value (of 'msr_index') into 'pdata'.
3159  * Returns 0 on success, non-0 otherwise.
3160  * Assumes vcpu_load() was already called.
3161  */
3162 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3163 {
3164         struct shared_msr_entry *msr;
3165
3166         switch (msr_info->index) {
3167 #ifdef CONFIG_X86_64
3168         case MSR_FS_BASE:
3169                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3170                 break;
3171         case MSR_GS_BASE:
3172                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3173                 break;
3174         case MSR_KERNEL_GS_BASE:
3175                 vmx_load_host_state(to_vmx(vcpu));
3176                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3177                 break;
3178 #endif
3179         case MSR_EFER:
3180                 return kvm_get_msr_common(vcpu, msr_info);
3181         case MSR_IA32_TSC:
3182                 msr_info->data = guest_read_tsc(vcpu);
3183                 break;
3184         case MSR_IA32_SYSENTER_CS:
3185                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3186                 break;
3187         case MSR_IA32_SYSENTER_EIP:
3188                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3189                 break;
3190         case MSR_IA32_SYSENTER_ESP:
3191                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3192                 break;
3193         case MSR_IA32_BNDCFGS:
3194                 if (!kvm_mpx_supported())
3195                         return 1;
3196                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3197                 break;
3198         case MSR_IA32_MCG_EXT_CTL:
3199                 if (!msr_info->host_initiated &&
3200                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3201                       FEATURE_CONTROL_LMCE))
3202                         return 1;
3203                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3204                 break;
3205         case MSR_IA32_FEATURE_CONTROL:
3206                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3207                 break;
3208         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3209                 if (!nested_vmx_allowed(vcpu))
3210                         return 1;
3211                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3212         case MSR_IA32_XSS:
3213                 if (!vmx_xsaves_supported())
3214                         return 1;
3215                 msr_info->data = vcpu->arch.ia32_xss;
3216                 break;
3217         case MSR_TSC_AUX:
3218                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3219                         return 1;
3220                 /* Otherwise falls through */
3221         default:
3222                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3223                 if (msr) {
3224                         msr_info->data = msr->data;
3225                         break;
3226                 }
3227                 return kvm_get_msr_common(vcpu, msr_info);
3228         }
3229
3230         return 0;
3231 }
3232
3233 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3234
3235 /*
3236  * Writes msr value into into the appropriate "register".
3237  * Returns 0 on success, non-0 otherwise.
3238  * Assumes vcpu_load() was already called.
3239  */
3240 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3241 {
3242         struct vcpu_vmx *vmx = to_vmx(vcpu);
3243         struct shared_msr_entry *msr;
3244         int ret = 0;
3245         u32 msr_index = msr_info->index;
3246         u64 data = msr_info->data;
3247
3248         switch (msr_index) {
3249         case MSR_EFER:
3250                 ret = kvm_set_msr_common(vcpu, msr_info);
3251                 break;
3252 #ifdef CONFIG_X86_64
3253         case MSR_FS_BASE:
3254                 vmx_segment_cache_clear(vmx);
3255                 vmcs_writel(GUEST_FS_BASE, data);
3256                 break;
3257         case MSR_GS_BASE:
3258                 vmx_segment_cache_clear(vmx);
3259                 vmcs_writel(GUEST_GS_BASE, data);
3260                 break;
3261         case MSR_KERNEL_GS_BASE:
3262                 vmx_load_host_state(vmx);
3263                 vmx->msr_guest_kernel_gs_base = data;
3264                 break;
3265 #endif
3266         case MSR_IA32_SYSENTER_CS:
3267                 vmcs_write32(GUEST_SYSENTER_CS, data);
3268                 break;
3269         case MSR_IA32_SYSENTER_EIP:
3270                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3271                 break;
3272         case MSR_IA32_SYSENTER_ESP:
3273                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3274                 break;
3275         case MSR_IA32_BNDCFGS:
3276                 if (!kvm_mpx_supported())
3277                         return 1;
3278                 vmcs_write64(GUEST_BNDCFGS, data);
3279                 break;
3280         case MSR_IA32_TSC:
3281                 kvm_write_tsc(vcpu, msr_info);
3282                 break;
3283         case MSR_IA32_CR_PAT:
3284                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3285                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3286                                 return 1;
3287                         vmcs_write64(GUEST_IA32_PAT, data);
3288                         vcpu->arch.pat = data;
3289                         break;
3290                 }
3291                 ret = kvm_set_msr_common(vcpu, msr_info);
3292                 break;
3293         case MSR_IA32_TSC_ADJUST:
3294                 ret = kvm_set_msr_common(vcpu, msr_info);
3295                 break;
3296         case MSR_IA32_MCG_EXT_CTL:
3297                 if ((!msr_info->host_initiated &&
3298                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3299                        FEATURE_CONTROL_LMCE)) ||
3300                     (data & ~MCG_EXT_CTL_LMCE_EN))
3301                         return 1;
3302                 vcpu->arch.mcg_ext_ctl = data;
3303                 break;
3304         case MSR_IA32_FEATURE_CONTROL:
3305                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3306                     (to_vmx(vcpu)->msr_ia32_feature_control &
3307                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3308                         return 1;
3309                 vmx->msr_ia32_feature_control = data;
3310                 if (msr_info->host_initiated && data == 0)
3311                         vmx_leave_nested(vcpu);
3312                 break;
3313         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3314                 if (!msr_info->host_initiated)
3315                         return 1; /* they are read-only */
3316                 if (!nested_vmx_allowed(vcpu))
3317                         return 1;
3318                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3319         case MSR_IA32_XSS:
3320                 if (!vmx_xsaves_supported())
3321                         return 1;
3322                 /*
3323                  * The only supported bit as of Skylake is bit 8, but
3324                  * it is not supported on KVM.
3325                  */
3326                 if (data != 0)
3327                         return 1;
3328                 vcpu->arch.ia32_xss = data;
3329                 if (vcpu->arch.ia32_xss != host_xss)
3330                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3331                                 vcpu->arch.ia32_xss, host_xss);
3332                 else
3333                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3334                 break;
3335         case MSR_TSC_AUX:
3336                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3337                         return 1;
3338                 /* Check reserved bit, higher 32 bits should be zero */
3339                 if ((data >> 32) != 0)
3340                         return 1;
3341                 /* Otherwise falls through */
3342         default:
3343                 msr = find_msr_entry(vmx, msr_index);
3344                 if (msr) {
3345                         u64 old_msr_data = msr->data;
3346                         msr->data = data;
3347                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3348                                 preempt_disable();
3349                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3350                                                          msr->mask);
3351                                 preempt_enable();
3352                                 if (ret)
3353                                         msr->data = old_msr_data;
3354                         }
3355                         break;
3356                 }
3357                 ret = kvm_set_msr_common(vcpu, msr_info);
3358         }
3359
3360         return ret;
3361 }
3362
3363 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3364 {
3365         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3366         switch (reg) {
3367         case VCPU_REGS_RSP:
3368                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3369                 break;
3370         case VCPU_REGS_RIP:
3371                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3372                 break;
3373         case VCPU_EXREG_PDPTR:
3374                 if (enable_ept)
3375                         ept_save_pdptrs(vcpu);
3376                 break;
3377         default:
3378                 break;
3379         }
3380 }
3381
3382 static __init int cpu_has_kvm_support(void)
3383 {
3384         return cpu_has_vmx();
3385 }
3386
3387 static __init int vmx_disabled_by_bios(void)
3388 {
3389         u64 msr;
3390
3391         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3392         if (msr & FEATURE_CONTROL_LOCKED) {
3393                 /* launched w/ TXT and VMX disabled */
3394                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3395                         && tboot_enabled())
3396                         return 1;
3397                 /* launched w/o TXT and VMX only enabled w/ TXT */
3398                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3399                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3400                         && !tboot_enabled()) {
3401                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3402                                 "activate TXT before enabling KVM\n");
3403                         return 1;
3404                 }
3405                 /* launched w/o TXT and VMX disabled */
3406                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3407                         && !tboot_enabled())
3408                         return 1;
3409         }
3410
3411         return 0;
3412 }
3413
3414 static void kvm_cpu_vmxon(u64 addr)
3415 {
3416         intel_pt_handle_vmx(1);
3417
3418         asm volatile (ASM_VMX_VMXON_RAX
3419                         : : "a"(&addr), "m"(addr)
3420                         : "memory", "cc");
3421 }
3422
3423 static int hardware_enable(void)
3424 {
3425         int cpu = raw_smp_processor_id();
3426         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3427         u64 old, test_bits;
3428
3429         if (cr4_read_shadow() & X86_CR4_VMXE)
3430                 return -EBUSY;
3431
3432         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3433         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3434         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3435
3436         /*
3437          * Now we can enable the vmclear operation in kdump
3438          * since the loaded_vmcss_on_cpu list on this cpu
3439          * has been initialized.
3440          *
3441          * Though the cpu is not in VMX operation now, there
3442          * is no problem to enable the vmclear operation
3443          * for the loaded_vmcss_on_cpu list is empty!
3444          */
3445         crash_enable_local_vmclear(cpu);
3446
3447         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3448
3449         test_bits = FEATURE_CONTROL_LOCKED;
3450         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3451         if (tboot_enabled())
3452                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3453
3454         if ((old & test_bits) != test_bits) {
3455                 /* enable and lock */
3456                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3457         }
3458         cr4_set_bits(X86_CR4_VMXE);
3459
3460         if (vmm_exclusive) {
3461                 kvm_cpu_vmxon(phys_addr);
3462                 ept_sync_global();
3463         }
3464
3465         native_store_gdt(this_cpu_ptr(&host_gdt));
3466
3467         return 0;
3468 }
3469
3470 static void vmclear_local_loaded_vmcss(void)
3471 {
3472         int cpu = raw_smp_processor_id();
3473         struct loaded_vmcs *v, *n;
3474
3475         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3476                                  loaded_vmcss_on_cpu_link)
3477                 __loaded_vmcs_clear(v);
3478 }
3479
3480
3481 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3482  * tricks.
3483  */
3484 static void kvm_cpu_vmxoff(void)
3485 {
3486         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3487
3488         intel_pt_handle_vmx(0);
3489 }
3490
3491 static void hardware_disable(void)
3492 {
3493         if (vmm_exclusive) {
3494                 vmclear_local_loaded_vmcss();
3495                 kvm_cpu_vmxoff();
3496         }
3497         cr4_clear_bits(X86_CR4_VMXE);
3498 }
3499
3500 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3501                                       u32 msr, u32 *result)
3502 {
3503         u32 vmx_msr_low, vmx_msr_high;
3504         u32 ctl = ctl_min | ctl_opt;
3505
3506         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3507
3508         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3509         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3510
3511         /* Ensure minimum (required) set of control bits are supported. */
3512         if (ctl_min & ~ctl)
3513                 return -EIO;
3514
3515         *result = ctl;
3516         return 0;
3517 }
3518
3519 static __init bool allow_1_setting(u32 msr, u32 ctl)
3520 {
3521         u32 vmx_msr_low, vmx_msr_high;
3522
3523         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3524         return vmx_msr_high & ctl;
3525 }
3526
3527 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3528 {
3529         u32 vmx_msr_low, vmx_msr_high;
3530         u32 min, opt, min2, opt2;
3531         u32 _pin_based_exec_control = 0;
3532         u32 _cpu_based_exec_control = 0;
3533         u32 _cpu_based_2nd_exec_control = 0;
3534         u32 _vmexit_control = 0;
3535         u32 _vmentry_control = 0;
3536
3537         min = CPU_BASED_HLT_EXITING |
3538 #ifdef CONFIG_X86_64
3539               CPU_BASED_CR8_LOAD_EXITING |
3540               CPU_BASED_CR8_STORE_EXITING |
3541 #endif
3542               CPU_BASED_CR3_LOAD_EXITING |
3543               CPU_BASED_CR3_STORE_EXITING |
3544               CPU_BASED_USE_IO_BITMAPS |
3545               CPU_BASED_MOV_DR_EXITING |
3546               CPU_BASED_USE_TSC_OFFSETING |
3547               CPU_BASED_MWAIT_EXITING |
3548               CPU_BASED_MONITOR_EXITING |
3549               CPU_BASED_INVLPG_EXITING |
3550               CPU_BASED_RDPMC_EXITING;
3551
3552         opt = CPU_BASED_TPR_SHADOW |
3553               CPU_BASED_USE_MSR_BITMAPS |
3554               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3555         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3556                                 &_cpu_based_exec_control) < 0)
3557                 return -EIO;
3558 #ifdef CONFIG_X86_64
3559         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3560                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3561                                            ~CPU_BASED_CR8_STORE_EXITING;
3562 #endif
3563         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3564                 min2 = 0;
3565                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3566                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3567                         SECONDARY_EXEC_WBINVD_EXITING |
3568                         SECONDARY_EXEC_ENABLE_VPID |
3569                         SECONDARY_EXEC_ENABLE_EPT |
3570                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3571                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3572                         SECONDARY_EXEC_RDTSCP |
3573                         SECONDARY_EXEC_ENABLE_INVPCID |
3574                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3575                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3576                         SECONDARY_EXEC_SHADOW_VMCS |
3577                         SECONDARY_EXEC_XSAVES |
3578                         SECONDARY_EXEC_ENABLE_PML |
3579                         SECONDARY_EXEC_TSC_SCALING;
3580                 if (adjust_vmx_controls(min2, opt2,
3581                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3582                                         &_cpu_based_2nd_exec_control) < 0)
3583                         return -EIO;
3584         }
3585 #ifndef CONFIG_X86_64
3586         if (!(_cpu_based_2nd_exec_control &
3587                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3588                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3589 #endif
3590
3591         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3592                 _cpu_based_2nd_exec_control &= ~(
3593                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3594                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3595                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3596
3597         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3598                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3599                    enabled */
3600                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3601                                              CPU_BASED_CR3_STORE_EXITING |
3602                                              CPU_BASED_INVLPG_EXITING);
3603                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3604                       vmx_capability.ept, vmx_capability.vpid);
3605         }
3606
3607         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3608 #ifdef CONFIG_X86_64
3609         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3610 #endif
3611         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3612                 VM_EXIT_CLEAR_BNDCFGS;
3613         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3614                                 &_vmexit_control) < 0)
3615                 return -EIO;
3616
3617         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3618                 PIN_BASED_VIRTUAL_NMIS;
3619         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3620         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3621                                 &_pin_based_exec_control) < 0)
3622                 return -EIO;
3623
3624         if (cpu_has_broken_vmx_preemption_timer())
3625                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3626         if (!(_cpu_based_2nd_exec_control &
3627                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3628                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3629
3630         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3631         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3632         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3633                                 &_vmentry_control) < 0)
3634                 return -EIO;
3635
3636         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3637
3638         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3639         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3640                 return -EIO;
3641
3642 #ifdef CONFIG_X86_64
3643         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3644         if (vmx_msr_high & (1u<<16))
3645                 return -EIO;
3646 #endif
3647
3648         /* Require Write-Back (WB) memory type for VMCS accesses. */
3649         if (((vmx_msr_high >> 18) & 15) != 6)
3650                 return -EIO;
3651
3652         vmcs_conf->size = vmx_msr_high & 0x1fff;
3653         vmcs_conf->order = get_order(vmcs_conf->size);
3654         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3655         vmcs_conf->revision_id = vmx_msr_low;
3656
3657         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3658         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3659         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3660         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3661         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3662
3663         cpu_has_load_ia32_efer =
3664                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3665                                 VM_ENTRY_LOAD_IA32_EFER)
3666                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3667                                    VM_EXIT_LOAD_IA32_EFER);
3668
3669         cpu_has_load_perf_global_ctrl =
3670                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3671                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3672                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3673                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3674
3675         /*
3676          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3677          * but due to errata below it can't be used. Workaround is to use
3678          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3679          *
3680          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3681          *
3682          * AAK155             (model 26)
3683          * AAP115             (model 30)
3684          * AAT100             (model 37)
3685          * BC86,AAY89,BD102   (model 44)
3686          * BA97               (model 46)
3687          *
3688          */
3689         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3690                 switch (boot_cpu_data.x86_model) {
3691                 case 26:
3692                 case 30:
3693                 case 37:
3694                 case 44:
3695                 case 46:
3696                         cpu_has_load_perf_global_ctrl = false;
3697                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3698                                         "does not work properly. Using workaround\n");
3699                         break;
3700                 default:
3701                         break;
3702                 }
3703         }
3704
3705         if (boot_cpu_has(X86_FEATURE_XSAVES))
3706                 rdmsrl(MSR_IA32_XSS, host_xss);
3707
3708         return 0;
3709 }
3710
3711 static struct vmcs *alloc_vmcs_cpu(int cpu)
3712 {
3713         int node = cpu_to_node(cpu);
3714         struct page *pages;
3715         struct vmcs *vmcs;
3716
3717         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3718         if (!pages)
3719                 return NULL;
3720         vmcs = page_address(pages);
3721         memset(vmcs, 0, vmcs_config.size);
3722         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3723         return vmcs;
3724 }
3725
3726 static struct vmcs *alloc_vmcs(void)
3727 {
3728         return alloc_vmcs_cpu(raw_smp_processor_id());
3729 }
3730
3731 static void free_vmcs(struct vmcs *vmcs)
3732 {
3733         free_pages((unsigned long)vmcs, vmcs_config.order);
3734 }
3735
3736 /*
3737  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3738  */
3739 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3740 {
3741         if (!loaded_vmcs->vmcs)
3742                 return;
3743         loaded_vmcs_clear(loaded_vmcs);
3744         free_vmcs(loaded_vmcs->vmcs);
3745         loaded_vmcs->vmcs = NULL;
3746         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3747 }
3748
3749 static void free_kvm_area(void)
3750 {
3751         int cpu;
3752
3753         for_each_possible_cpu(cpu) {
3754                 free_vmcs(per_cpu(vmxarea, cpu));
3755                 per_cpu(vmxarea, cpu) = NULL;
3756         }
3757 }
3758
3759 static void init_vmcs_shadow_fields(void)
3760 {
3761         int i, j;
3762
3763         /* No checks for read only fields yet */
3764
3765         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3766                 switch (shadow_read_write_fields[i]) {
3767                 case GUEST_BNDCFGS:
3768                         if (!kvm_mpx_supported())
3769                                 continue;
3770                         break;
3771                 default:
3772                         break;
3773                 }
3774
3775                 if (j < i)
3776                         shadow_read_write_fields[j] =
3777                                 shadow_read_write_fields[i];
3778                 j++;
3779         }
3780         max_shadow_read_write_fields = j;
3781
3782         /* shadowed fields guest access without vmexit */
3783         for (i = 0; i < max_shadow_read_write_fields; i++) {
3784                 clear_bit(shadow_read_write_fields[i],
3785                           vmx_vmwrite_bitmap);
3786                 clear_bit(shadow_read_write_fields[i],
3787                           vmx_vmread_bitmap);
3788         }
3789         for (i = 0; i < max_shadow_read_only_fields; i++)
3790                 clear_bit(shadow_read_only_fields[i],
3791                           vmx_vmread_bitmap);
3792 }
3793
3794 static __init int alloc_kvm_area(void)
3795 {
3796         int cpu;
3797
3798         for_each_possible_cpu(cpu) {
3799                 struct vmcs *vmcs;
3800
3801                 vmcs = alloc_vmcs_cpu(cpu);
3802                 if (!vmcs) {
3803                         free_kvm_area();
3804                         return -ENOMEM;
3805                 }
3806
3807                 per_cpu(vmxarea, cpu) = vmcs;
3808         }
3809         return 0;
3810 }
3811
3812 static bool emulation_required(struct kvm_vcpu *vcpu)
3813 {
3814         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3815 }
3816
3817 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3818                 struct kvm_segment *save)
3819 {
3820         if (!emulate_invalid_guest_state) {
3821                 /*
3822                  * CS and SS RPL should be equal during guest entry according
3823                  * to VMX spec, but in reality it is not always so. Since vcpu
3824                  * is in the middle of the transition from real mode to
3825                  * protected mode it is safe to assume that RPL 0 is a good
3826                  * default value.
3827                  */
3828                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3829                         save->selector &= ~SEGMENT_RPL_MASK;
3830                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3831                 save->s = 1;
3832         }
3833         vmx_set_segment(vcpu, save, seg);
3834 }
3835
3836 static void enter_pmode(struct kvm_vcpu *vcpu)
3837 {
3838         unsigned long flags;
3839         struct vcpu_vmx *vmx = to_vmx(vcpu);
3840
3841         /*
3842          * Update real mode segment cache. It may be not up-to-date if sement
3843          * register was written while vcpu was in a guest mode.
3844          */
3845         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3846         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3847         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3848         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3849         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3850         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3851
3852         vmx->rmode.vm86_active = 0;
3853
3854         vmx_segment_cache_clear(vmx);
3855
3856         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3857
3858         flags = vmcs_readl(GUEST_RFLAGS);
3859         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3860         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3861         vmcs_writel(GUEST_RFLAGS, flags);
3862
3863         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3864                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3865
3866         update_exception_bitmap(vcpu);
3867
3868         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3869         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3870         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3871         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3872         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3873         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3874 }
3875
3876 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3877 {
3878         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3879         struct kvm_segment var = *save;
3880
3881         var.dpl = 0x3;
3882         if (seg == VCPU_SREG_CS)
3883                 var.type = 0x3;
3884
3885         if (!emulate_invalid_guest_state) {
3886                 var.selector = var.base >> 4;
3887                 var.base = var.base & 0xffff0;
3888                 var.limit = 0xffff;
3889                 var.g = 0;
3890                 var.db = 0;
3891                 var.present = 1;
3892                 var.s = 1;
3893                 var.l = 0;
3894                 var.unusable = 0;
3895                 var.type = 0x3;
3896                 var.avl = 0;
3897                 if (save->base & 0xf)
3898                         printk_once(KERN_WARNING "kvm: segment base is not "
3899                                         "paragraph aligned when entering "
3900                                         "protected mode (seg=%d)", seg);
3901         }
3902
3903         vmcs_write16(sf->selector, var.selector);
3904         vmcs_writel(sf->base, var.base);
3905         vmcs_write32(sf->limit, var.limit);
3906         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3907 }
3908
3909 static void enter_rmode(struct kvm_vcpu *vcpu)
3910 {
3911         unsigned long flags;
3912         struct vcpu_vmx *vmx = to_vmx(vcpu);
3913
3914         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3915         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3916         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3917         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3918         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3919         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3920         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3921
3922         vmx->rmode.vm86_active = 1;
3923
3924         /*
3925          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3926          * vcpu. Warn the user that an update is overdue.
3927          */
3928         if (!vcpu->kvm->arch.tss_addr)
3929                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3930                              "called before entering vcpu\n");
3931
3932         vmx_segment_cache_clear(vmx);
3933
3934         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3935         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3936         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3937
3938         flags = vmcs_readl(GUEST_RFLAGS);
3939         vmx->rmode.save_rflags = flags;
3940
3941         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3942
3943         vmcs_writel(GUEST_RFLAGS, flags);
3944         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3945         update_exception_bitmap(vcpu);
3946
3947         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3948         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3949         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3950         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3951         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3952         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3953
3954         kvm_mmu_reset_context(vcpu);
3955 }
3956
3957 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3958 {
3959         struct vcpu_vmx *vmx = to_vmx(vcpu);
3960         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3961
3962         if (!msr)
3963                 return;
3964
3965         /*
3966          * Force kernel_gs_base reloading before EFER changes, as control
3967          * of this msr depends on is_long_mode().
3968          */
3969         vmx_load_host_state(to_vmx(vcpu));
3970         vcpu->arch.efer = efer;
3971         if (efer & EFER_LMA) {
3972                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3973                 msr->data = efer;
3974         } else {
3975                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3976
3977                 msr->data = efer & ~EFER_LME;
3978         }
3979         setup_msrs(vmx);
3980 }
3981
3982 #ifdef CONFIG_X86_64
3983
3984 static void enter_lmode(struct kvm_vcpu *vcpu)
3985 {
3986         u32 guest_tr_ar;
3987
3988         vmx_segment_cache_clear(to_vmx(vcpu));
3989
3990         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3991         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3992                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3993                                      __func__);
3994                 vmcs_write32(GUEST_TR_AR_BYTES,
3995                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3996                              | VMX_AR_TYPE_BUSY_64_TSS);
3997         }
3998         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3999 }
4000
4001 static void exit_lmode(struct kvm_vcpu *vcpu)
4002 {
4003         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4004         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4005 }
4006
4007 #endif
4008
4009 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4010 {
4011         if (enable_ept) {
4012                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4013                         return;
4014                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4015         } else {
4016                 vpid_sync_context(vpid);
4017         }
4018 }
4019
4020 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4021 {
4022         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4023 }
4024
4025 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4026 {
4027         if (enable_ept)
4028                 vmx_flush_tlb(vcpu);
4029 }
4030
4031 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4032 {
4033         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4034
4035         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4036         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4037 }
4038
4039 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4040 {
4041         if (enable_ept && is_paging(vcpu))
4042                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4043         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4044 }
4045
4046 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4047 {
4048         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4049
4050         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4051         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4052 }
4053
4054 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4055 {
4056         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4057
4058         if (!test_bit(VCPU_EXREG_PDPTR,
4059                       (unsigned long *)&vcpu->arch.regs_dirty))
4060                 return;
4061
4062         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4063                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4064                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4065                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4066                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4067         }
4068 }
4069
4070 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4071 {
4072         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4073
4074         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4075                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4076                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4077                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4078                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4079         }
4080
4081         __set_bit(VCPU_EXREG_PDPTR,
4082                   (unsigned long *)&vcpu->arch.regs_avail);
4083         __set_bit(VCPU_EXREG_PDPTR,
4084                   (unsigned long *)&vcpu->arch.regs_dirty);
4085 }
4086
4087 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4088 {
4089         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4090         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4091         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4092
4093         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4094                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4095             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4096                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4097
4098         return fixed_bits_valid(val, fixed0, fixed1);
4099 }
4100
4101 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4102 {
4103         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4104         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4105
4106         return fixed_bits_valid(val, fixed0, fixed1);
4107 }
4108
4109 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4110 {
4111         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4112         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4113
4114         return fixed_bits_valid(val, fixed0, fixed1);
4115 }
4116
4117 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4118 #define nested_guest_cr4_valid  nested_cr4_valid
4119 #define nested_host_cr4_valid   nested_cr4_valid
4120
4121 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4122
4123 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4124                                         unsigned long cr0,
4125                                         struct kvm_vcpu *vcpu)
4126 {
4127         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4128                 vmx_decache_cr3(vcpu);
4129         if (!(cr0 & X86_CR0_PG)) {
4130                 /* From paging/starting to nonpaging */
4131                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4132                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4133                              (CPU_BASED_CR3_LOAD_EXITING |
4134                               CPU_BASED_CR3_STORE_EXITING));
4135                 vcpu->arch.cr0 = cr0;
4136                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4137         } else if (!is_paging(vcpu)) {
4138                 /* From nonpaging to paging */
4139                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4140                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4141                              ~(CPU_BASED_CR3_LOAD_EXITING |
4142                                CPU_BASED_CR3_STORE_EXITING));
4143                 vcpu->arch.cr0 = cr0;
4144                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4145         }
4146
4147         if (!(cr0 & X86_CR0_WP))
4148                 *hw_cr0 &= ~X86_CR0_WP;
4149 }
4150
4151 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4152 {
4153         struct vcpu_vmx *vmx = to_vmx(vcpu);
4154         unsigned long hw_cr0;
4155
4156         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4157         if (enable_unrestricted_guest)
4158                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4159         else {
4160                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4161
4162                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4163                         enter_pmode(vcpu);
4164
4165                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4166                         enter_rmode(vcpu);
4167         }
4168
4169 #ifdef CONFIG_X86_64
4170         if (vcpu->arch.efer & EFER_LME) {
4171                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4172                         enter_lmode(vcpu);
4173                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4174                         exit_lmode(vcpu);
4175         }
4176 #endif
4177
4178         if (enable_ept)
4179                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4180
4181         vmcs_writel(CR0_READ_SHADOW, cr0);
4182         vmcs_writel(GUEST_CR0, hw_cr0);
4183         vcpu->arch.cr0 = cr0;
4184
4185         /* depends on vcpu->arch.cr0 to be set to a new value */
4186         vmx->emulation_required = emulation_required(vcpu);
4187 }
4188
4189 static u64 construct_eptp(unsigned long root_hpa)
4190 {
4191         u64 eptp;
4192
4193         /* TODO write the value reading from MSR */
4194         eptp = VMX_EPT_DEFAULT_MT |
4195                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4196         if (enable_ept_ad_bits)
4197                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4198         eptp |= (root_hpa & PAGE_MASK);
4199
4200         return eptp;
4201 }
4202
4203 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4204 {
4205         unsigned long guest_cr3;
4206         u64 eptp;
4207
4208         guest_cr3 = cr3;
4209         if (enable_ept) {
4210                 eptp = construct_eptp(cr3);
4211                 vmcs_write64(EPT_POINTER, eptp);
4212                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4213                         guest_cr3 = kvm_read_cr3(vcpu);
4214                 else
4215                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4216                 ept_load_pdptrs(vcpu);
4217         }
4218
4219         vmx_flush_tlb(vcpu);
4220         vmcs_writel(GUEST_CR3, guest_cr3);
4221 }
4222
4223 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4224 {
4225         /*
4226          * Pass through host's Machine Check Enable value to hw_cr4, which
4227          * is in force while we are in guest mode.  Do not let guests control
4228          * this bit, even if host CR4.MCE == 0.
4229          */
4230         unsigned long hw_cr4 =
4231                 (cr4_read_shadow() & X86_CR4_MCE) |
4232                 (cr4 & ~X86_CR4_MCE) |
4233                 (to_vmx(vcpu)->rmode.vm86_active ?
4234                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4235
4236         if (cr4 & X86_CR4_VMXE) {
4237                 /*
4238                  * To use VMXON (and later other VMX instructions), a guest
4239                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4240                  * So basically the check on whether to allow nested VMX
4241                  * is here.
4242                  */
4243                 if (!nested_vmx_allowed(vcpu))
4244                         return 1;
4245         }
4246
4247         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4248                 return 1;
4249
4250         vcpu->arch.cr4 = cr4;
4251         if (enable_ept) {
4252                 if (!is_paging(vcpu)) {
4253                         hw_cr4 &= ~X86_CR4_PAE;
4254                         hw_cr4 |= X86_CR4_PSE;
4255                 } else if (!(cr4 & X86_CR4_PAE)) {
4256                         hw_cr4 &= ~X86_CR4_PAE;
4257                 }
4258         }
4259
4260         if (!enable_unrestricted_guest && !is_paging(vcpu))
4261                 /*
4262                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4263                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4264                  * to be manually disabled when guest switches to non-paging
4265                  * mode.
4266                  *
4267                  * If !enable_unrestricted_guest, the CPU is always running
4268                  * with CR0.PG=1 and CR4 needs to be modified.
4269                  * If enable_unrestricted_guest, the CPU automatically
4270                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4271                  */
4272                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4273
4274         vmcs_writel(CR4_READ_SHADOW, cr4);
4275         vmcs_writel(GUEST_CR4, hw_cr4);
4276         return 0;
4277 }
4278
4279 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4280                             struct kvm_segment *var, int seg)
4281 {
4282         struct vcpu_vmx *vmx = to_vmx(vcpu);
4283         u32 ar;
4284
4285         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4286                 *var = vmx->rmode.segs[seg];
4287                 if (seg == VCPU_SREG_TR
4288                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4289                         return;
4290                 var->base = vmx_read_guest_seg_base(vmx, seg);
4291                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4292                 return;
4293         }
4294         var->base = vmx_read_guest_seg_base(vmx, seg);
4295         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4296         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4297         ar = vmx_read_guest_seg_ar(vmx, seg);
4298         var->unusable = (ar >> 16) & 1;
4299         var->type = ar & 15;
4300         var->s = (ar >> 4) & 1;
4301         var->dpl = (ar >> 5) & 3;
4302         /*
4303          * Some userspaces do not preserve unusable property. Since usable
4304          * segment has to be present according to VMX spec we can use present
4305          * property to amend userspace bug by making unusable segment always
4306          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4307          * segment as unusable.
4308          */
4309         var->present = !var->unusable;
4310         var->avl = (ar >> 12) & 1;
4311         var->l = (ar >> 13) & 1;
4312         var->db = (ar >> 14) & 1;
4313         var->g = (ar >> 15) & 1;
4314 }
4315
4316 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4317 {
4318         struct kvm_segment s;
4319
4320         if (to_vmx(vcpu)->rmode.vm86_active) {
4321                 vmx_get_segment(vcpu, &s, seg);
4322                 return s.base;
4323         }
4324         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4325 }
4326
4327 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4328 {
4329         struct vcpu_vmx *vmx = to_vmx(vcpu);
4330
4331         if (unlikely(vmx->rmode.vm86_active))
4332                 return 0;
4333         else {
4334                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4335                 return VMX_AR_DPL(ar);
4336         }
4337 }
4338
4339 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4340 {
4341         u32 ar;
4342
4343         if (var->unusable || !var->present)
4344                 ar = 1 << 16;
4345         else {
4346                 ar = var->type & 15;
4347                 ar |= (var->s & 1) << 4;
4348                 ar |= (var->dpl & 3) << 5;
4349                 ar |= (var->present & 1) << 7;
4350                 ar |= (var->avl & 1) << 12;
4351                 ar |= (var->l & 1) << 13;
4352                 ar |= (var->db & 1) << 14;
4353                 ar |= (var->g & 1) << 15;
4354         }
4355
4356         return ar;
4357 }
4358
4359 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4360                             struct kvm_segment *var, int seg)
4361 {
4362         struct vcpu_vmx *vmx = to_vmx(vcpu);
4363         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4364
4365         vmx_segment_cache_clear(vmx);
4366
4367         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4368                 vmx->rmode.segs[seg] = *var;
4369                 if (seg == VCPU_SREG_TR)
4370                         vmcs_write16(sf->selector, var->selector);
4371                 else if (var->s)
4372                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4373                 goto out;
4374         }
4375
4376         vmcs_writel(sf->base, var->base);
4377         vmcs_write32(sf->limit, var->limit);
4378         vmcs_write16(sf->selector, var->selector);
4379
4380         /*
4381          *   Fix the "Accessed" bit in AR field of segment registers for older
4382          * qemu binaries.
4383          *   IA32 arch specifies that at the time of processor reset the
4384          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4385          * is setting it to 0 in the userland code. This causes invalid guest
4386          * state vmexit when "unrestricted guest" mode is turned on.
4387          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4388          * tree. Newer qemu binaries with that qemu fix would not need this
4389          * kvm hack.
4390          */
4391         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4392                 var->type |= 0x1; /* Accessed */
4393
4394         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4395
4396 out:
4397         vmx->emulation_required = emulation_required(vcpu);
4398 }
4399
4400 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4401 {
4402         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4403
4404         *db = (ar >> 14) & 1;
4405         *l = (ar >> 13) & 1;
4406 }
4407
4408 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4409 {
4410         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4411         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4412 }
4413
4414 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4415 {
4416         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4417         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4418 }
4419
4420 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4421 {
4422         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4423         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4424 }
4425
4426 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4427 {
4428         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4429         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4430 }
4431
4432 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4433 {
4434         struct kvm_segment var;
4435         u32 ar;
4436
4437         vmx_get_segment(vcpu, &var, seg);
4438         var.dpl = 0x3;
4439         if (seg == VCPU_SREG_CS)
4440                 var.type = 0x3;
4441         ar = vmx_segment_access_rights(&var);
4442
4443         if (var.base != (var.selector << 4))
4444                 return false;
4445         if (var.limit != 0xffff)
4446                 return false;
4447         if (ar != 0xf3)
4448                 return false;
4449
4450         return true;
4451 }
4452
4453 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4454 {
4455         struct kvm_segment cs;
4456         unsigned int cs_rpl;
4457
4458         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4459         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4460
4461         if (cs.unusable)
4462                 return false;
4463         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4464                 return false;
4465         if (!cs.s)
4466                 return false;
4467         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4468                 if (cs.dpl > cs_rpl)
4469                         return false;
4470         } else {
4471                 if (cs.dpl != cs_rpl)
4472                         return false;
4473         }
4474         if (!cs.present)
4475                 return false;
4476
4477         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4478         return true;
4479 }
4480
4481 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4482 {
4483         struct kvm_segment ss;
4484         unsigned int ss_rpl;
4485
4486         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4487         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4488
4489         if (ss.unusable)
4490                 return true;
4491         if (ss.type != 3 && ss.type != 7)
4492                 return false;
4493         if (!ss.s)
4494                 return false;
4495         if (ss.dpl != ss_rpl) /* DPL != RPL */
4496                 return false;
4497         if (!ss.present)
4498                 return false;
4499
4500         return true;
4501 }
4502
4503 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4504 {
4505         struct kvm_segment var;
4506         unsigned int rpl;
4507
4508         vmx_get_segment(vcpu, &var, seg);
4509         rpl = var.selector & SEGMENT_RPL_MASK;
4510
4511         if (var.unusable)
4512                 return true;
4513         if (!var.s)
4514                 return false;
4515         if (!var.present)
4516                 return false;
4517         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4518                 if (var.dpl < rpl) /* DPL < RPL */
4519                         return false;
4520         }
4521
4522         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4523          * rights flags
4524          */
4525         return true;
4526 }
4527
4528 static bool tr_valid(struct kvm_vcpu *vcpu)
4529 {
4530         struct kvm_segment tr;
4531
4532         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4533
4534         if (tr.unusable)
4535                 return false;
4536         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4537                 return false;
4538         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4539                 return false;
4540         if (!tr.present)
4541                 return false;
4542
4543         return true;
4544 }
4545
4546 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4547 {
4548         struct kvm_segment ldtr;
4549
4550         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4551
4552         if (ldtr.unusable)
4553                 return true;
4554         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4555                 return false;
4556         if (ldtr.type != 2)
4557                 return false;
4558         if (!ldtr.present)
4559                 return false;
4560
4561         return true;
4562 }
4563
4564 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4565 {
4566         struct kvm_segment cs, ss;
4567
4568         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4569         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4570
4571         return ((cs.selector & SEGMENT_RPL_MASK) ==
4572                  (ss.selector & SEGMENT_RPL_MASK));
4573 }
4574
4575 /*
4576  * Check if guest state is valid. Returns true if valid, false if
4577  * not.
4578  * We assume that registers are always usable
4579  */
4580 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4581 {
4582         if (enable_unrestricted_guest)
4583                 return true;
4584
4585         /* real mode guest state checks */
4586         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4587                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4588                         return false;
4589                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4590                         return false;
4591                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4592                         return false;
4593                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4594                         return false;
4595                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4596                         return false;
4597                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4598                         return false;
4599         } else {
4600         /* protected mode guest state checks */
4601                 if (!cs_ss_rpl_check(vcpu))
4602                         return false;
4603                 if (!code_segment_valid(vcpu))
4604                         return false;
4605                 if (!stack_segment_valid(vcpu))
4606                         return false;
4607                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4608                         return false;
4609                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4610                         return false;
4611                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4612                         return false;
4613                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4614                         return false;
4615                 if (!tr_valid(vcpu))
4616                         return false;
4617                 if (!ldtr_valid(vcpu))
4618                         return false;
4619         }
4620         /* TODO:
4621          * - Add checks on RIP
4622          * - Add checks on RFLAGS
4623          */
4624
4625         return true;
4626 }
4627
4628 static int init_rmode_tss(struct kvm *kvm)
4629 {
4630         gfn_t fn;
4631         u16 data = 0;
4632         int idx, r;
4633
4634         idx = srcu_read_lock(&kvm->srcu);
4635         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4636         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4637         if (r < 0)
4638                 goto out;
4639         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4640         r = kvm_write_guest_page(kvm, fn++, &data,
4641                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4642         if (r < 0)
4643                 goto out;
4644         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4645         if (r < 0)
4646                 goto out;
4647         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4648         if (r < 0)
4649                 goto out;
4650         data = ~0;
4651         r = kvm_write_guest_page(kvm, fn, &data,
4652                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4653                                  sizeof(u8));
4654 out:
4655         srcu_read_unlock(&kvm->srcu, idx);
4656         return r;
4657 }
4658
4659 static int init_rmode_identity_map(struct kvm *kvm)
4660 {
4661         int i, idx, r = 0;
4662         kvm_pfn_t identity_map_pfn;
4663         u32 tmp;
4664
4665         if (!enable_ept)
4666                 return 0;
4667
4668         /* Protect kvm->arch.ept_identity_pagetable_done. */
4669         mutex_lock(&kvm->slots_lock);
4670
4671         if (likely(kvm->arch.ept_identity_pagetable_done))
4672                 goto out2;
4673
4674         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4675
4676         r = alloc_identity_pagetable(kvm);
4677         if (r < 0)
4678                 goto out2;
4679
4680         idx = srcu_read_lock(&kvm->srcu);
4681         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4682         if (r < 0)
4683                 goto out;
4684         /* Set up identity-mapping pagetable for EPT in real mode */
4685         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4686                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4687                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4688                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4689                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4690                 if (r < 0)
4691                         goto out;
4692         }
4693         kvm->arch.ept_identity_pagetable_done = true;
4694
4695 out:
4696         srcu_read_unlock(&kvm->srcu, idx);
4697
4698 out2:
4699         mutex_unlock(&kvm->slots_lock);
4700         return r;
4701 }
4702
4703 static void seg_setup(int seg)
4704 {
4705         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4706         unsigned int ar;
4707
4708         vmcs_write16(sf->selector, 0);
4709         vmcs_writel(sf->base, 0);
4710         vmcs_write32(sf->limit, 0xffff);
4711         ar = 0x93;
4712         if (seg == VCPU_SREG_CS)
4713                 ar |= 0x08; /* code segment */
4714
4715         vmcs_write32(sf->ar_bytes, ar);
4716 }
4717
4718 static int alloc_apic_access_page(struct kvm *kvm)
4719 {
4720         struct page *page;
4721         int r = 0;
4722
4723         mutex_lock(&kvm->slots_lock);
4724         if (kvm->arch.apic_access_page_done)
4725                 goto out;
4726         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4727                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4728         if (r)
4729                 goto out;
4730
4731         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4732         if (is_error_page(page)) {
4733                 r = -EFAULT;
4734                 goto out;
4735         }
4736
4737         /*
4738          * Do not pin the page in memory, so that memory hot-unplug
4739          * is able to migrate it.
4740          */
4741         put_page(page);
4742         kvm->arch.apic_access_page_done = true;
4743 out:
4744         mutex_unlock(&kvm->slots_lock);
4745         return r;
4746 }
4747
4748 static int alloc_identity_pagetable(struct kvm *kvm)
4749 {
4750         /* Called with kvm->slots_lock held. */
4751
4752         int r = 0;
4753
4754         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4755
4756         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4757                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4758
4759         return r;
4760 }
4761
4762 static int allocate_vpid(void)
4763 {
4764         int vpid;
4765
4766         if (!enable_vpid)
4767                 return 0;
4768         spin_lock(&vmx_vpid_lock);
4769         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4770         if (vpid < VMX_NR_VPIDS)
4771                 __set_bit(vpid, vmx_vpid_bitmap);
4772         else
4773                 vpid = 0;
4774         spin_unlock(&vmx_vpid_lock);
4775         return vpid;
4776 }
4777
4778 static void free_vpid(int vpid)
4779 {
4780         if (!enable_vpid || vpid == 0)
4781                 return;
4782         spin_lock(&vmx_vpid_lock);
4783         __clear_bit(vpid, vmx_vpid_bitmap);
4784         spin_unlock(&vmx_vpid_lock);
4785 }
4786
4787 #define MSR_TYPE_R      1
4788 #define MSR_TYPE_W      2
4789 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4790                                                 u32 msr, int type)
4791 {
4792         int f = sizeof(unsigned long);
4793
4794         if (!cpu_has_vmx_msr_bitmap())
4795                 return;
4796
4797         /*
4798          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4799          * have the write-low and read-high bitmap offsets the wrong way round.
4800          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4801          */
4802         if (msr <= 0x1fff) {
4803                 if (type & MSR_TYPE_R)
4804                         /* read-low */
4805                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4806
4807                 if (type & MSR_TYPE_W)
4808                         /* write-low */
4809                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4810
4811         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4812                 msr &= 0x1fff;
4813                 if (type & MSR_TYPE_R)
4814                         /* read-high */
4815                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4816
4817                 if (type & MSR_TYPE_W)
4818                         /* write-high */
4819                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4820
4821         }
4822 }
4823
4824 /*
4825  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4826  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4827  */
4828 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4829                                                unsigned long *msr_bitmap_nested,
4830                                                u32 msr, int type)
4831 {
4832         int f = sizeof(unsigned long);
4833
4834         if (!cpu_has_vmx_msr_bitmap()) {
4835                 WARN_ON(1);
4836                 return;
4837         }
4838
4839         /*
4840          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4841          * have the write-low and read-high bitmap offsets the wrong way round.
4842          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4843          */
4844         if (msr <= 0x1fff) {
4845                 if (type & MSR_TYPE_R &&
4846                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4847                         /* read-low */
4848                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4849
4850                 if (type & MSR_TYPE_W &&
4851                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4852                         /* write-low */
4853                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4854
4855         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4856                 msr &= 0x1fff;
4857                 if (type & MSR_TYPE_R &&
4858                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4859                         /* read-high */
4860                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4861
4862                 if (type & MSR_TYPE_W &&
4863                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4864                         /* write-high */
4865                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4866
4867         }
4868 }
4869
4870 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4871 {
4872         if (!longmode_only)
4873                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4874                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4875         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4876                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4877 }
4878
4879 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4880 {
4881         if (apicv_active) {
4882                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4883                                 msr, type);
4884                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4885                                 msr, type);
4886         } else {
4887                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4888                                 msr, type);
4889                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4890                                 msr, type);
4891         }
4892 }
4893
4894 static bool vmx_get_enable_apicv(void)
4895 {
4896         return enable_apicv;
4897 }
4898
4899 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4900 {
4901         struct vcpu_vmx *vmx = to_vmx(vcpu);
4902         int max_irr;
4903         void *vapic_page;
4904         u16 status;
4905
4906         if (vmx->nested.pi_desc &&
4907             vmx->nested.pi_pending) {
4908                 vmx->nested.pi_pending = false;
4909                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4910                         return;
4911
4912                 max_irr = find_last_bit(
4913                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4914
4915                 if (max_irr == 256)
4916                         return;
4917
4918                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4919                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4920                 kunmap(vmx->nested.virtual_apic_page);
4921
4922                 status = vmcs_read16(GUEST_INTR_STATUS);
4923                 if ((u8)max_irr > ((u8)status & 0xff)) {
4924                         status &= ~0xff;
4925                         status |= (u8)max_irr;
4926                         vmcs_write16(GUEST_INTR_STATUS, status);
4927                 }
4928         }
4929 }
4930
4931 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4932 {
4933 #ifdef CONFIG_SMP
4934         if (vcpu->mode == IN_GUEST_MODE) {
4935                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4936
4937                 /*
4938                  * Currently, we don't support urgent interrupt,
4939                  * all interrupts are recognized as non-urgent
4940                  * interrupt, so we cannot post interrupts when
4941                  * 'SN' is set.
4942                  *
4943                  * If the vcpu is in guest mode, it means it is
4944                  * running instead of being scheduled out and
4945                  * waiting in the run queue, and that's the only
4946                  * case when 'SN' is set currently, warning if
4947                  * 'SN' is set.
4948                  */
4949                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4950
4951                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4952                                 POSTED_INTR_VECTOR);
4953                 return true;
4954         }
4955 #endif
4956         return false;
4957 }
4958
4959 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4960                                                 int vector)
4961 {
4962         struct vcpu_vmx *vmx = to_vmx(vcpu);
4963
4964         if (is_guest_mode(vcpu) &&
4965             vector == vmx->nested.posted_intr_nv) {
4966                 /* the PIR and ON have been set by L1. */
4967                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4968                 /*
4969                  * If a posted intr is not recognized by hardware,
4970                  * we will accomplish it in the next vmentry.
4971                  */
4972                 vmx->nested.pi_pending = true;
4973                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4974                 return 0;
4975         }
4976         return -1;
4977 }
4978 /*
4979  * Send interrupt to vcpu via posted interrupt way.
4980  * 1. If target vcpu is running(non-root mode), send posted interrupt
4981  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4982  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4983  * interrupt from PIR in next vmentry.
4984  */
4985 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4986 {
4987         struct vcpu_vmx *vmx = to_vmx(vcpu);
4988         int r;
4989
4990         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4991         if (!r)
4992                 return;
4993
4994         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4995                 return;
4996
4997         /* If a previous notification has sent the IPI, nothing to do.  */
4998         if (pi_test_and_set_on(&vmx->pi_desc))
4999                 return;
5000
5001         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5002                 kvm_vcpu_kick(vcpu);
5003 }
5004
5005 /*
5006  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5007  * will not change in the lifetime of the guest.
5008  * Note that host-state that does change is set elsewhere. E.g., host-state
5009  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5010  */
5011 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5012 {
5013         u32 low32, high32;
5014         unsigned long tmpl;
5015         struct desc_ptr dt;
5016         unsigned long cr0, cr4;
5017
5018         cr0 = read_cr0();
5019         WARN_ON(cr0 & X86_CR0_TS);
5020         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5021         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5022
5023         /* Save the most likely value for this task's CR4 in the VMCS. */
5024         cr4 = cr4_read_shadow();
5025         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5026         vmx->host_state.vmcs_host_cr4 = cr4;
5027
5028         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5029 #ifdef CONFIG_X86_64
5030         /*
5031          * Load null selectors, so we can avoid reloading them in
5032          * __vmx_load_host_state(), in case userspace uses the null selectors
5033          * too (the expected case).
5034          */
5035         vmcs_write16(HOST_DS_SELECTOR, 0);
5036         vmcs_write16(HOST_ES_SELECTOR, 0);
5037 #else
5038         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5039         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5040 #endif
5041         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5042         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5043
5044         native_store_idt(&dt);
5045         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5046         vmx->host_idt_base = dt.address;
5047
5048         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5049
5050         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5051         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5052         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5053         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5054
5055         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5056                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5057                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5058         }
5059 }
5060
5061 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5062 {
5063         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5064         if (enable_ept)
5065                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5066         if (is_guest_mode(&vmx->vcpu))
5067                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5068                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5069         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5070 }
5071
5072 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5073 {
5074         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5075
5076         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5077                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5078         /* Enable the preemption timer dynamically */
5079         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5080         return pin_based_exec_ctrl;
5081 }
5082
5083 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5084 {
5085         struct vcpu_vmx *vmx = to_vmx(vcpu);
5086
5087         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5088         if (cpu_has_secondary_exec_ctrls()) {
5089                 if (kvm_vcpu_apicv_active(vcpu))
5090                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5091                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5092                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5093                 else
5094                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5095                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5096                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5097         }
5098
5099         if (cpu_has_vmx_msr_bitmap())
5100                 vmx_set_msr_bitmap(vcpu);
5101 }
5102
5103 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5104 {
5105         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5106
5107         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5108                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5109
5110         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5111                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5112 #ifdef CONFIG_X86_64
5113                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5114                                 CPU_BASED_CR8_LOAD_EXITING;
5115 #endif
5116         }
5117         if (!enable_ept)
5118                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5119                                 CPU_BASED_CR3_LOAD_EXITING  |
5120                                 CPU_BASED_INVLPG_EXITING;
5121         return exec_control;
5122 }
5123
5124 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5125 {
5126         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5127         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5128                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5129         if (vmx->vpid == 0)
5130                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5131         if (!enable_ept) {
5132                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5133                 enable_unrestricted_guest = 0;
5134                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5135                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5136         }
5137         if (!enable_unrestricted_guest)
5138                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5139         if (!ple_gap)
5140                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5141         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5142                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5143                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5144         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5145         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5146            (handle_vmptrld).
5147            We can NOT enable shadow_vmcs here because we don't have yet
5148            a current VMCS12
5149         */
5150         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5151
5152         if (!enable_pml)
5153                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5154
5155         return exec_control;
5156 }
5157
5158 static void ept_set_mmio_spte_mask(void)
5159 {
5160         /*
5161          * EPT Misconfigurations can be generated if the value of bits 2:0
5162          * of an EPT paging-structure entry is 110b (write/execute).
5163          */
5164         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5165 }
5166
5167 #define VMX_XSS_EXIT_BITMAP 0
5168 /*
5169  * Sets up the vmcs for emulated real mode.
5170  */
5171 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5172 {
5173 #ifdef CONFIG_X86_64
5174         unsigned long a;
5175 #endif
5176         int i;
5177
5178         /* I/O */
5179         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5180         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5181
5182         if (enable_shadow_vmcs) {
5183                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5184                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5185         }
5186         if (cpu_has_vmx_msr_bitmap())
5187                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5188
5189         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5190
5191         /* Control */
5192         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5193         vmx->hv_deadline_tsc = -1;
5194
5195         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5196
5197         if (cpu_has_secondary_exec_ctrls()) {
5198                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5199                                 vmx_secondary_exec_control(vmx));
5200         }
5201
5202         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5203                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5204                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5205                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5206                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5207
5208                 vmcs_write16(GUEST_INTR_STATUS, 0);
5209
5210                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5211                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5212         }
5213
5214         if (ple_gap) {
5215                 vmcs_write32(PLE_GAP, ple_gap);
5216                 vmx->ple_window = ple_window;
5217                 vmx->ple_window_dirty = true;
5218         }
5219
5220         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5221         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5222         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5223
5224         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5225         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5226         vmx_set_constant_host_state(vmx);
5227 #ifdef CONFIG_X86_64
5228         rdmsrl(MSR_FS_BASE, a);
5229         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5230         rdmsrl(MSR_GS_BASE, a);
5231         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5232 #else
5233         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5234         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5235 #endif
5236
5237         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5238         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5239         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5240         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5241         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5242
5243         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5244                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5245
5246         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5247                 u32 index = vmx_msr_index[i];
5248                 u32 data_low, data_high;
5249                 int j = vmx->nmsrs;
5250
5251                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5252                         continue;
5253                 if (wrmsr_safe(index, data_low, data_high) < 0)
5254                         continue;
5255                 vmx->guest_msrs[j].index = i;
5256                 vmx->guest_msrs[j].data = 0;
5257                 vmx->guest_msrs[j].mask = -1ull;
5258                 ++vmx->nmsrs;
5259         }
5260
5261
5262         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5263
5264         /* 22.2.1, 20.8.1 */
5265         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5266
5267         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5268         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5269
5270         set_cr4_guest_host_mask(vmx);
5271
5272         if (vmx_xsaves_supported())
5273                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5274
5275         if (enable_pml) {
5276                 ASSERT(vmx->pml_pg);
5277                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5278                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5279         }
5280
5281         return 0;
5282 }
5283
5284 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5285 {
5286         struct vcpu_vmx *vmx = to_vmx(vcpu);
5287         struct msr_data apic_base_msr;
5288         u64 cr0;
5289
5290         vmx->rmode.vm86_active = 0;
5291
5292         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5293         kvm_set_cr8(vcpu, 0);
5294
5295         if (!init_event) {
5296                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5297                                      MSR_IA32_APICBASE_ENABLE;
5298                 if (kvm_vcpu_is_reset_bsp(vcpu))
5299                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5300                 apic_base_msr.host_initiated = true;
5301                 kvm_set_apic_base(vcpu, &apic_base_msr);
5302         }
5303
5304         vmx_segment_cache_clear(vmx);
5305
5306         seg_setup(VCPU_SREG_CS);
5307         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5308         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5309
5310         seg_setup(VCPU_SREG_DS);
5311         seg_setup(VCPU_SREG_ES);
5312         seg_setup(VCPU_SREG_FS);
5313         seg_setup(VCPU_SREG_GS);
5314         seg_setup(VCPU_SREG_SS);
5315
5316         vmcs_write16(GUEST_TR_SELECTOR, 0);
5317         vmcs_writel(GUEST_TR_BASE, 0);
5318         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5319         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5320
5321         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5322         vmcs_writel(GUEST_LDTR_BASE, 0);
5323         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5324         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5325
5326         if (!init_event) {
5327                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5328                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5329                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5330                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5331         }
5332
5333         vmcs_writel(GUEST_RFLAGS, 0x02);
5334         kvm_rip_write(vcpu, 0xfff0);
5335
5336         vmcs_writel(GUEST_GDTR_BASE, 0);
5337         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5338
5339         vmcs_writel(GUEST_IDTR_BASE, 0);
5340         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5341
5342         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5343         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5344         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5345
5346         setup_msrs(vmx);
5347
5348         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5349
5350         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5351                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5352                 if (cpu_need_tpr_shadow(vcpu))
5353                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5354                                      __pa(vcpu->arch.apic->regs));
5355                 vmcs_write32(TPR_THRESHOLD, 0);
5356         }
5357
5358         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5359
5360         if (kvm_vcpu_apicv_active(vcpu))
5361                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5362
5363         if (vmx->vpid != 0)
5364                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5365
5366         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5367         vmx->vcpu.arch.cr0 = cr0;
5368         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5369         vmx_set_cr4(vcpu, 0);
5370         vmx_set_efer(vcpu, 0);
5371
5372         update_exception_bitmap(vcpu);
5373
5374         vpid_sync_context(vmx->vpid);
5375 }
5376
5377 /*
5378  * In nested virtualization, check if L1 asked to exit on external interrupts.
5379  * For most existing hypervisors, this will always return true.
5380  */
5381 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5382 {
5383         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5384                 PIN_BASED_EXT_INTR_MASK;
5385 }
5386
5387 /*
5388  * In nested virtualization, check if L1 has set
5389  * VM_EXIT_ACK_INTR_ON_EXIT
5390  */
5391 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5392 {
5393         return get_vmcs12(vcpu)->vm_exit_controls &
5394                 VM_EXIT_ACK_INTR_ON_EXIT;
5395 }
5396
5397 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5398 {
5399         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5400                 PIN_BASED_NMI_EXITING;
5401 }
5402
5403 static void enable_irq_window(struct kvm_vcpu *vcpu)
5404 {
5405         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5406                       CPU_BASED_VIRTUAL_INTR_PENDING);
5407 }
5408
5409 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5410 {
5411         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5412                 enable_irq_window(vcpu);
5413                 return;
5414         }
5415
5416         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5417                       CPU_BASED_VIRTUAL_NMI_PENDING);
5418 }
5419
5420 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5421 {
5422         struct vcpu_vmx *vmx = to_vmx(vcpu);
5423         uint32_t intr;
5424         int irq = vcpu->arch.interrupt.nr;
5425
5426         trace_kvm_inj_virq(irq);
5427
5428         ++vcpu->stat.irq_injections;
5429         if (vmx->rmode.vm86_active) {
5430                 int inc_eip = 0;
5431                 if (vcpu->arch.interrupt.soft)
5432                         inc_eip = vcpu->arch.event_exit_inst_len;
5433                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5434                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5435                 return;
5436         }
5437         intr = irq | INTR_INFO_VALID_MASK;
5438         if (vcpu->arch.interrupt.soft) {
5439                 intr |= INTR_TYPE_SOFT_INTR;
5440                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5441                              vmx->vcpu.arch.event_exit_inst_len);
5442         } else
5443                 intr |= INTR_TYPE_EXT_INTR;
5444         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5445 }
5446
5447 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5448 {
5449         struct vcpu_vmx *vmx = to_vmx(vcpu);
5450
5451         if (!is_guest_mode(vcpu)) {
5452                 ++vcpu->stat.nmi_injections;
5453                 vmx->nmi_known_unmasked = false;
5454         }
5455
5456         if (vmx->rmode.vm86_active) {
5457                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5458                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5459                 return;
5460         }
5461
5462         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5463                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5464 }
5465
5466 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5467 {
5468         if (to_vmx(vcpu)->nmi_known_unmasked)
5469                 return false;
5470         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5471 }
5472
5473 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5474 {
5475         struct vcpu_vmx *vmx = to_vmx(vcpu);
5476
5477         vmx->nmi_known_unmasked = !masked;
5478         if (masked)
5479                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5480                               GUEST_INTR_STATE_NMI);
5481         else
5482                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5483                                 GUEST_INTR_STATE_NMI);
5484 }
5485
5486 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5487 {
5488         if (to_vmx(vcpu)->nested.nested_run_pending)
5489                 return 0;
5490
5491         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5492                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5493                    | GUEST_INTR_STATE_NMI));
5494 }
5495
5496 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5497 {
5498         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5499                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5500                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5501                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5502 }
5503
5504 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5505 {
5506         int ret;
5507
5508         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5509                                     PAGE_SIZE * 3);
5510         if (ret)
5511                 return ret;
5512         kvm->arch.tss_addr = addr;
5513         return init_rmode_tss(kvm);
5514 }
5515
5516 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5517 {
5518         switch (vec) {
5519         case BP_VECTOR:
5520                 /*
5521                  * Update instruction length as we may reinject the exception
5522                  * from user space while in guest debugging mode.
5523                  */
5524                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5525                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5526                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5527                         return false;
5528                 /* fall through */
5529         case DB_VECTOR:
5530                 if (vcpu->guest_debug &
5531                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5532                         return false;
5533                 /* fall through */
5534         case DE_VECTOR:
5535         case OF_VECTOR:
5536         case BR_VECTOR:
5537         case UD_VECTOR:
5538         case DF_VECTOR:
5539         case SS_VECTOR:
5540         case GP_VECTOR:
5541         case MF_VECTOR:
5542                 return true;
5543         break;
5544         }
5545         return false;
5546 }
5547
5548 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5549                                   int vec, u32 err_code)
5550 {
5551         /*
5552          * Instruction with address size override prefix opcode 0x67
5553          * Cause the #SS fault with 0 error code in VM86 mode.
5554          */
5555         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5556                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5557                         if (vcpu->arch.halt_request) {
5558                                 vcpu->arch.halt_request = 0;
5559                                 return kvm_vcpu_halt(vcpu);
5560                         }
5561                         return 1;
5562                 }
5563                 return 0;
5564         }
5565
5566         /*
5567          * Forward all other exceptions that are valid in real mode.
5568          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5569          *        the required debugging infrastructure rework.
5570          */
5571         kvm_queue_exception(vcpu, vec);
5572         return 1;
5573 }
5574
5575 /*
5576  * Trigger machine check on the host. We assume all the MSRs are already set up
5577  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5578  * We pass a fake environment to the machine check handler because we want
5579  * the guest to be always treated like user space, no matter what context
5580  * it used internally.
5581  */
5582 static void kvm_machine_check(void)
5583 {
5584 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5585         struct pt_regs regs = {
5586                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5587                 .flags = X86_EFLAGS_IF,
5588         };
5589
5590         do_machine_check(&regs, 0);
5591 #endif
5592 }
5593
5594 static int handle_machine_check(struct kvm_vcpu *vcpu)
5595 {
5596         /* already handled by vcpu_run */
5597         return 1;
5598 }
5599
5600 static int handle_exception(struct kvm_vcpu *vcpu)
5601 {
5602         struct vcpu_vmx *vmx = to_vmx(vcpu);
5603         struct kvm_run *kvm_run = vcpu->run;
5604         u32 intr_info, ex_no, error_code;
5605         unsigned long cr2, rip, dr6;
5606         u32 vect_info;
5607         enum emulation_result er;
5608
5609         vect_info = vmx->idt_vectoring_info;
5610         intr_info = vmx->exit_intr_info;
5611
5612         if (is_machine_check(intr_info))
5613                 return handle_machine_check(vcpu);
5614
5615         if (is_nmi(intr_info))
5616                 return 1;  /* already handled by vmx_vcpu_run() */
5617
5618         if (is_invalid_opcode(intr_info)) {
5619                 if (is_guest_mode(vcpu)) {
5620                         kvm_queue_exception(vcpu, UD_VECTOR);
5621                         return 1;
5622                 }
5623                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5624                 if (er != EMULATE_DONE)
5625                         kvm_queue_exception(vcpu, UD_VECTOR);
5626                 return 1;
5627         }
5628
5629         error_code = 0;
5630         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5631                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5632
5633         /*
5634          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5635          * MMIO, it is better to report an internal error.
5636          * See the comments in vmx_handle_exit.
5637          */
5638         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5639             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5640                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5641                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5642                 vcpu->run->internal.ndata = 3;
5643                 vcpu->run->internal.data[0] = vect_info;
5644                 vcpu->run->internal.data[1] = intr_info;
5645                 vcpu->run->internal.data[2] = error_code;
5646                 return 0;
5647         }
5648
5649         if (is_page_fault(intr_info)) {
5650                 /* EPT won't cause page fault directly */
5651                 BUG_ON(enable_ept);
5652                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5653                 trace_kvm_page_fault(cr2, error_code);
5654
5655                 if (kvm_event_needs_reinjection(vcpu))
5656                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5657                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5658         }
5659
5660         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5661
5662         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5663                 return handle_rmode_exception(vcpu, ex_no, error_code);
5664
5665         switch (ex_no) {
5666         case AC_VECTOR:
5667                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5668                 return 1;
5669         case DB_VECTOR:
5670                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5671                 if (!(vcpu->guest_debug &
5672                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5673                         vcpu->arch.dr6 &= ~15;
5674                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5675                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5676                                 skip_emulated_instruction(vcpu);
5677
5678                         kvm_queue_exception(vcpu, DB_VECTOR);
5679                         return 1;
5680                 }
5681                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5682                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5683                 /* fall through */
5684         case BP_VECTOR:
5685                 /*
5686                  * Update instruction length as we may reinject #BP from
5687                  * user space while in guest debugging mode. Reading it for
5688                  * #DB as well causes no harm, it is not used in that case.
5689                  */
5690                 vmx->vcpu.arch.event_exit_inst_len =
5691                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5692                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5693                 rip = kvm_rip_read(vcpu);
5694                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5695                 kvm_run->debug.arch.exception = ex_no;
5696                 break;
5697         default:
5698                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5699                 kvm_run->ex.exception = ex_no;
5700                 kvm_run->ex.error_code = error_code;
5701                 break;
5702         }
5703         return 0;
5704 }
5705
5706 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5707 {
5708         ++vcpu->stat.irq_exits;
5709         return 1;
5710 }
5711
5712 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5713 {
5714         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5715         return 0;
5716 }
5717
5718 static int handle_io(struct kvm_vcpu *vcpu)
5719 {
5720         unsigned long exit_qualification;
5721         int size, in, string, ret;
5722         unsigned port;
5723
5724         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5725         string = (exit_qualification & 16) != 0;
5726         in = (exit_qualification & 8) != 0;
5727
5728         ++vcpu->stat.io_exits;
5729
5730         if (string || in)
5731                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5732
5733         port = exit_qualification >> 16;
5734         size = (exit_qualification & 7) + 1;
5735
5736         ret = kvm_skip_emulated_instruction(vcpu);
5737
5738         /*
5739          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5740          * KVM_EXIT_DEBUG here.
5741          */
5742         return kvm_fast_pio_out(vcpu, size, port) && ret;
5743 }
5744
5745 static void
5746 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5747 {
5748         /*
5749          * Patch in the VMCALL instruction:
5750          */
5751         hypercall[0] = 0x0f;
5752         hypercall[1] = 0x01;
5753         hypercall[2] = 0xc1;
5754 }
5755
5756 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5757 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5758 {
5759         if (is_guest_mode(vcpu)) {
5760                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5761                 unsigned long orig_val = val;
5762
5763                 /*
5764                  * We get here when L2 changed cr0 in a way that did not change
5765                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5766                  * but did change L0 shadowed bits. So we first calculate the
5767                  * effective cr0 value that L1 would like to write into the
5768                  * hardware. It consists of the L2-owned bits from the new
5769                  * value combined with the L1-owned bits from L1's guest_cr0.
5770                  */
5771                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5772                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5773
5774                 if (!nested_guest_cr0_valid(vcpu, val))
5775                         return 1;
5776
5777                 if (kvm_set_cr0(vcpu, val))
5778                         return 1;
5779                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5780                 return 0;
5781         } else {
5782                 if (to_vmx(vcpu)->nested.vmxon &&
5783                     !nested_host_cr0_valid(vcpu, val))
5784                         return 1;
5785
5786                 return kvm_set_cr0(vcpu, val);
5787         }
5788 }
5789
5790 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5791 {
5792         if (is_guest_mode(vcpu)) {
5793                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5794                 unsigned long orig_val = val;
5795
5796                 /* analogously to handle_set_cr0 */
5797                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5798                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5799                 if (kvm_set_cr4(vcpu, val))
5800                         return 1;
5801                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5802                 return 0;
5803         } else
5804                 return kvm_set_cr4(vcpu, val);
5805 }
5806
5807 static int handle_cr(struct kvm_vcpu *vcpu)
5808 {
5809         unsigned long exit_qualification, val;
5810         int cr;
5811         int reg;
5812         int err;
5813         int ret;
5814
5815         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5816         cr = exit_qualification & 15;
5817         reg = (exit_qualification >> 8) & 15;
5818         switch ((exit_qualification >> 4) & 3) {
5819         case 0: /* mov to cr */
5820                 val = kvm_register_readl(vcpu, reg);
5821                 trace_kvm_cr_write(cr, val);
5822                 switch (cr) {
5823                 case 0:
5824                         err = handle_set_cr0(vcpu, val);
5825                         return kvm_complete_insn_gp(vcpu, err);
5826                 case 3:
5827                         err = kvm_set_cr3(vcpu, val);
5828                         return kvm_complete_insn_gp(vcpu, err);
5829                 case 4:
5830                         err = handle_set_cr4(vcpu, val);
5831                         return kvm_complete_insn_gp(vcpu, err);
5832                 case 8: {
5833                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5834                                 u8 cr8 = (u8)val;
5835                                 err = kvm_set_cr8(vcpu, cr8);
5836                                 ret = kvm_complete_insn_gp(vcpu, err);
5837                                 if (lapic_in_kernel(vcpu))
5838                                         return ret;
5839                                 if (cr8_prev <= cr8)
5840                                         return ret;
5841                                 /*
5842                                  * TODO: we might be squashing a
5843                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5844                                  * KVM_EXIT_DEBUG here.
5845                                  */
5846                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5847                                 return 0;
5848                         }
5849                 }
5850                 break;
5851         case 2: /* clts */
5852                 WARN_ONCE(1, "Guest should always own CR0.TS");
5853                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5854                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5855                 return kvm_skip_emulated_instruction(vcpu);
5856         case 1: /*mov from cr*/
5857                 switch (cr) {
5858                 case 3:
5859                         val = kvm_read_cr3(vcpu);
5860                         kvm_register_write(vcpu, reg, val);
5861                         trace_kvm_cr_read(cr, val);
5862                         return kvm_skip_emulated_instruction(vcpu);
5863                 case 8:
5864                         val = kvm_get_cr8(vcpu);
5865                         kvm_register_write(vcpu, reg, val);
5866                         trace_kvm_cr_read(cr, val);
5867                         return kvm_skip_emulated_instruction(vcpu);
5868                 }
5869                 break;
5870         case 3: /* lmsw */
5871                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5872                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5873                 kvm_lmsw(vcpu, val);
5874
5875                 return kvm_skip_emulated_instruction(vcpu);
5876         default:
5877                 break;
5878         }
5879         vcpu->run->exit_reason = 0;
5880         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5881                (int)(exit_qualification >> 4) & 3, cr);
5882         return 0;
5883 }
5884
5885 static int handle_dr(struct kvm_vcpu *vcpu)
5886 {
5887         unsigned long exit_qualification;
5888         int dr, dr7, reg;
5889
5890         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5891         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5892
5893         /* First, if DR does not exist, trigger UD */
5894         if (!kvm_require_dr(vcpu, dr))
5895                 return 1;
5896
5897         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5898         if (!kvm_require_cpl(vcpu, 0))
5899                 return 1;
5900         dr7 = vmcs_readl(GUEST_DR7);
5901         if (dr7 & DR7_GD) {
5902                 /*
5903                  * As the vm-exit takes precedence over the debug trap, we
5904                  * need to emulate the latter, either for the host or the
5905                  * guest debugging itself.
5906                  */
5907                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5908                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5909                         vcpu->run->debug.arch.dr7 = dr7;
5910                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5911                         vcpu->run->debug.arch.exception = DB_VECTOR;
5912                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5913                         return 0;
5914                 } else {
5915                         vcpu->arch.dr6 &= ~15;
5916                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5917                         kvm_queue_exception(vcpu, DB_VECTOR);
5918                         return 1;
5919                 }
5920         }
5921
5922         if (vcpu->guest_debug == 0) {
5923                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5924                                 CPU_BASED_MOV_DR_EXITING);
5925
5926                 /*
5927                  * No more DR vmexits; force a reload of the debug registers
5928                  * and reenter on this instruction.  The next vmexit will
5929                  * retrieve the full state of the debug registers.
5930                  */
5931                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5932                 return 1;
5933         }
5934
5935         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5936         if (exit_qualification & TYPE_MOV_FROM_DR) {
5937                 unsigned long val;
5938
5939                 if (kvm_get_dr(vcpu, dr, &val))
5940                         return 1;
5941                 kvm_register_write(vcpu, reg, val);
5942         } else
5943                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5944                         return 1;
5945
5946         return kvm_skip_emulated_instruction(vcpu);
5947 }
5948
5949 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5950 {
5951         return vcpu->arch.dr6;
5952 }
5953
5954 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5955 {
5956 }
5957
5958 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5959 {
5960         get_debugreg(vcpu->arch.db[0], 0);
5961         get_debugreg(vcpu->arch.db[1], 1);
5962         get_debugreg(vcpu->arch.db[2], 2);
5963         get_debugreg(vcpu->arch.db[3], 3);
5964         get_debugreg(vcpu->arch.dr6, 6);
5965         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5966
5967         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5968         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5969 }
5970
5971 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5972 {
5973         vmcs_writel(GUEST_DR7, val);
5974 }
5975
5976 static int handle_cpuid(struct kvm_vcpu *vcpu)
5977 {
5978         return kvm_emulate_cpuid(vcpu);
5979 }
5980
5981 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5982 {
5983         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5984         struct msr_data msr_info;
5985
5986         msr_info.index = ecx;
5987         msr_info.host_initiated = false;
5988         if (vmx_get_msr(vcpu, &msr_info)) {
5989                 trace_kvm_msr_read_ex(ecx);
5990                 kvm_inject_gp(vcpu, 0);
5991                 return 1;
5992         }
5993
5994         trace_kvm_msr_read(ecx, msr_info.data);
5995
5996         /* FIXME: handling of bits 32:63 of rax, rdx */
5997         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5998         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5999         return kvm_skip_emulated_instruction(vcpu);
6000 }
6001
6002 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6003 {
6004         struct msr_data msr;
6005         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6006         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6007                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6008
6009         msr.data = data;
6010         msr.index = ecx;
6011         msr.host_initiated = false;
6012         if (kvm_set_msr(vcpu, &msr) != 0) {
6013                 trace_kvm_msr_write_ex(ecx, data);
6014                 kvm_inject_gp(vcpu, 0);
6015                 return 1;
6016         }
6017
6018         trace_kvm_msr_write(ecx, data);
6019         return kvm_skip_emulated_instruction(vcpu);
6020 }
6021
6022 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6023 {
6024         kvm_apic_update_ppr(vcpu);
6025         return 1;
6026 }
6027
6028 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6029 {
6030         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6031                         CPU_BASED_VIRTUAL_INTR_PENDING);
6032
6033         kvm_make_request(KVM_REQ_EVENT, vcpu);
6034
6035         ++vcpu->stat.irq_window_exits;
6036         return 1;
6037 }
6038
6039 static int handle_halt(struct kvm_vcpu *vcpu)
6040 {
6041         return kvm_emulate_halt(vcpu);
6042 }
6043
6044 static int handle_vmcall(struct kvm_vcpu *vcpu)
6045 {
6046         return kvm_emulate_hypercall(vcpu);
6047 }
6048
6049 static int handle_invd(struct kvm_vcpu *vcpu)
6050 {
6051         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6052 }
6053
6054 static int handle_invlpg(struct kvm_vcpu *vcpu)
6055 {
6056         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6057
6058         kvm_mmu_invlpg(vcpu, exit_qualification);
6059         return kvm_skip_emulated_instruction(vcpu);
6060 }
6061
6062 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6063 {
6064         int err;
6065
6066         err = kvm_rdpmc(vcpu);
6067         return kvm_complete_insn_gp(vcpu, err);
6068 }
6069
6070 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6071 {
6072         return kvm_emulate_wbinvd(vcpu);
6073 }
6074
6075 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6076 {
6077         u64 new_bv = kvm_read_edx_eax(vcpu);
6078         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6079
6080         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6081                 return kvm_skip_emulated_instruction(vcpu);
6082         return 1;
6083 }
6084
6085 static int handle_xsaves(struct kvm_vcpu *vcpu)
6086 {
6087         kvm_skip_emulated_instruction(vcpu);
6088         WARN(1, "this should never happen\n");
6089         return 1;
6090 }
6091
6092 static int handle_xrstors(struct kvm_vcpu *vcpu)
6093 {
6094         kvm_skip_emulated_instruction(vcpu);
6095         WARN(1, "this should never happen\n");
6096         return 1;
6097 }
6098
6099 static int handle_apic_access(struct kvm_vcpu *vcpu)
6100 {
6101         if (likely(fasteoi)) {
6102                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6103                 int access_type, offset;
6104
6105                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6106                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6107                 /*
6108                  * Sane guest uses MOV to write EOI, with written value
6109                  * not cared. So make a short-circuit here by avoiding
6110                  * heavy instruction emulation.
6111                  */
6112                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6113                     (offset == APIC_EOI)) {
6114                         kvm_lapic_set_eoi(vcpu);
6115                         return kvm_skip_emulated_instruction(vcpu);
6116                 }
6117         }
6118         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6119 }
6120
6121 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6122 {
6123         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6124         int vector = exit_qualification & 0xff;
6125
6126         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6127         kvm_apic_set_eoi_accelerated(vcpu, vector);
6128         return 1;
6129 }
6130
6131 static int handle_apic_write(struct kvm_vcpu *vcpu)
6132 {
6133         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6134         u32 offset = exit_qualification & 0xfff;
6135
6136         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6137         kvm_apic_write_nodecode(vcpu, offset);
6138         return 1;
6139 }
6140
6141 static int handle_task_switch(struct kvm_vcpu *vcpu)
6142 {
6143         struct vcpu_vmx *vmx = to_vmx(vcpu);
6144         unsigned long exit_qualification;
6145         bool has_error_code = false;
6146         u32 error_code = 0;
6147         u16 tss_selector;
6148         int reason, type, idt_v, idt_index;
6149
6150         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6151         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6152         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6153
6154         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6155
6156         reason = (u32)exit_qualification >> 30;
6157         if (reason == TASK_SWITCH_GATE && idt_v) {
6158                 switch (type) {
6159                 case INTR_TYPE_NMI_INTR:
6160                         vcpu->arch.nmi_injected = false;
6161                         vmx_set_nmi_mask(vcpu, true);
6162                         break;
6163                 case INTR_TYPE_EXT_INTR:
6164                 case INTR_TYPE_SOFT_INTR:
6165                         kvm_clear_interrupt_queue(vcpu);
6166                         break;
6167                 case INTR_TYPE_HARD_EXCEPTION:
6168                         if (vmx->idt_vectoring_info &
6169                             VECTORING_INFO_DELIVER_CODE_MASK) {
6170                                 has_error_code = true;
6171                                 error_code =
6172                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6173                         }
6174                         /* fall through */
6175                 case INTR_TYPE_SOFT_EXCEPTION:
6176                         kvm_clear_exception_queue(vcpu);
6177                         break;
6178                 default:
6179                         break;
6180                 }
6181         }
6182         tss_selector = exit_qualification;
6183
6184         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6185                        type != INTR_TYPE_EXT_INTR &&
6186                        type != INTR_TYPE_NMI_INTR))
6187                 skip_emulated_instruction(vcpu);
6188
6189         if (kvm_task_switch(vcpu, tss_selector,
6190                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6191                             has_error_code, error_code) == EMULATE_FAIL) {
6192                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6193                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6194                 vcpu->run->internal.ndata = 0;
6195                 return 0;
6196         }
6197
6198         /*
6199          * TODO: What about debug traps on tss switch?
6200          *       Are we supposed to inject them and update dr6?
6201          */
6202
6203         return 1;
6204 }
6205
6206 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6207 {
6208         unsigned long exit_qualification;
6209         gpa_t gpa;
6210         u32 error_code;
6211         int gla_validity;
6212
6213         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6214
6215         gla_validity = (exit_qualification >> 7) & 0x3;
6216         if (gla_validity == 0x2) {
6217                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6218                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6219                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6220                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6221                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6222                         (long unsigned int)exit_qualification);
6223                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6224                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6225                 return 0;
6226         }
6227
6228         /*
6229          * EPT violation happened while executing iret from NMI,
6230          * "blocked by NMI" bit has to be set before next VM entry.
6231          * There are errata that may cause this bit to not be set:
6232          * AAK134, BY25.
6233          */
6234         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6235                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6236                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6237
6238         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6239         trace_kvm_page_fault(gpa, exit_qualification);
6240
6241         /* Is it a read fault? */
6242         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6243                      ? PFERR_USER_MASK : 0;
6244         /* Is it a write fault? */
6245         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6246                       ? PFERR_WRITE_MASK : 0;
6247         /* Is it a fetch fault? */
6248         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6249                       ? PFERR_FETCH_MASK : 0;
6250         /* ept page table entry is present? */
6251         error_code |= (exit_qualification &
6252                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6253                         EPT_VIOLATION_EXECUTABLE))
6254                       ? PFERR_PRESENT_MASK : 0;
6255
6256         vcpu->arch.gpa_available = true;
6257         vcpu->arch.exit_qualification = exit_qualification;
6258
6259         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6260 }
6261
6262 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6263 {
6264         int ret;
6265         gpa_t gpa;
6266
6267         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6268         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6269                 trace_kvm_fast_mmio(gpa);
6270                 return kvm_skip_emulated_instruction(vcpu);
6271         }
6272
6273         ret = handle_mmio_page_fault(vcpu, gpa, true);
6274         vcpu->arch.gpa_available = true;
6275         if (likely(ret == RET_MMIO_PF_EMULATE))
6276                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6277                                               EMULATE_DONE;
6278
6279         if (unlikely(ret == RET_MMIO_PF_INVALID))
6280                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6281
6282         if (unlikely(ret == RET_MMIO_PF_RETRY))
6283                 return 1;
6284
6285         /* It is the real ept misconfig */
6286         WARN_ON(1);
6287
6288         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6289         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6290
6291         return 0;
6292 }
6293
6294 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6295 {
6296         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6297                         CPU_BASED_VIRTUAL_NMI_PENDING);
6298         ++vcpu->stat.nmi_window_exits;
6299         kvm_make_request(KVM_REQ_EVENT, vcpu);
6300
6301         return 1;
6302 }
6303
6304 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6305 {
6306         struct vcpu_vmx *vmx = to_vmx(vcpu);
6307         enum emulation_result err = EMULATE_DONE;
6308         int ret = 1;
6309         u32 cpu_exec_ctrl;
6310         bool intr_window_requested;
6311         unsigned count = 130;
6312
6313         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6314         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6315
6316         while (vmx->emulation_required && count-- != 0) {
6317                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6318                         return handle_interrupt_window(&vmx->vcpu);
6319
6320                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6321                         return 1;
6322
6323                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6324
6325                 if (err == EMULATE_USER_EXIT) {
6326                         ++vcpu->stat.mmio_exits;
6327                         ret = 0;
6328                         goto out;
6329                 }
6330
6331                 if (err != EMULATE_DONE) {
6332                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6333                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6334                         vcpu->run->internal.ndata = 0;
6335                         return 0;
6336                 }
6337
6338                 if (vcpu->arch.halt_request) {
6339                         vcpu->arch.halt_request = 0;
6340                         ret = kvm_vcpu_halt(vcpu);
6341                         goto out;
6342                 }
6343
6344                 if (signal_pending(current))
6345                         goto out;
6346                 if (need_resched())
6347                         schedule();
6348         }
6349
6350 out:
6351         return ret;
6352 }
6353
6354 static int __grow_ple_window(int val)
6355 {
6356         if (ple_window_grow < 1)
6357                 return ple_window;
6358
6359         val = min(val, ple_window_actual_max);
6360
6361         if (ple_window_grow < ple_window)
6362                 val *= ple_window_grow;
6363         else
6364                 val += ple_window_grow;
6365
6366         return val;
6367 }
6368
6369 static int __shrink_ple_window(int val, int modifier, int minimum)
6370 {
6371         if (modifier < 1)
6372                 return ple_window;
6373
6374         if (modifier < ple_window)
6375                 val /= modifier;
6376         else
6377                 val -= modifier;
6378
6379         return max(val, minimum);
6380 }
6381
6382 static void grow_ple_window(struct kvm_vcpu *vcpu)
6383 {
6384         struct vcpu_vmx *vmx = to_vmx(vcpu);
6385         int old = vmx->ple_window;
6386
6387         vmx->ple_window = __grow_ple_window(old);
6388
6389         if (vmx->ple_window != old)
6390                 vmx->ple_window_dirty = true;
6391
6392         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6393 }
6394
6395 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6396 {
6397         struct vcpu_vmx *vmx = to_vmx(vcpu);
6398         int old = vmx->ple_window;
6399
6400         vmx->ple_window = __shrink_ple_window(old,
6401                                               ple_window_shrink, ple_window);
6402
6403         if (vmx->ple_window != old)
6404                 vmx->ple_window_dirty = true;
6405
6406         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6407 }
6408
6409 /*
6410  * ple_window_actual_max is computed to be one grow_ple_window() below
6411  * ple_window_max. (See __grow_ple_window for the reason.)
6412  * This prevents overflows, because ple_window_max is int.
6413  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6414  * this process.
6415  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6416  */
6417 static void update_ple_window_actual_max(void)
6418 {
6419         ple_window_actual_max =
6420                         __shrink_ple_window(max(ple_window_max, ple_window),
6421                                             ple_window_grow, INT_MIN);
6422 }
6423
6424 /*
6425  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6426  */
6427 static void wakeup_handler(void)
6428 {
6429         struct kvm_vcpu *vcpu;
6430         int cpu = smp_processor_id();
6431
6432         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6433         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6434                         blocked_vcpu_list) {
6435                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6436
6437                 if (pi_test_on(pi_desc) == 1)
6438                         kvm_vcpu_kick(vcpu);
6439         }
6440         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6441 }
6442
6443 void vmx_enable_tdp(void)
6444 {
6445         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6446                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6447                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6448                 0ull, VMX_EPT_EXECUTABLE_MASK,
6449                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6450                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6451
6452         ept_set_mmio_spte_mask();
6453         kvm_enable_tdp();
6454 }
6455
6456 static __init int hardware_setup(void)
6457 {
6458         int r = -ENOMEM, i, msr;
6459
6460         rdmsrl_safe(MSR_EFER, &host_efer);
6461
6462         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6463                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6464
6465         for (i = 0; i < VMX_BITMAP_NR; i++) {
6466                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6467                 if (!vmx_bitmap[i])
6468                         goto out;
6469         }
6470
6471         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6472         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6473         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6474
6475         /*
6476          * Allow direct access to the PC debug port (it is often used for I/O
6477          * delays, but the vmexits simply slow things down).
6478          */
6479         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6480         clear_bit(0x80, vmx_io_bitmap_a);
6481
6482         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6483
6484         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6485         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6486
6487         if (setup_vmcs_config(&vmcs_config) < 0) {
6488                 r = -EIO;
6489                 goto out;
6490         }
6491
6492         if (boot_cpu_has(X86_FEATURE_NX))
6493                 kvm_enable_efer_bits(EFER_NX);
6494
6495         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6496                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6497                 enable_vpid = 0;
6498
6499         if (!cpu_has_vmx_shadow_vmcs())
6500                 enable_shadow_vmcs = 0;
6501         if (enable_shadow_vmcs)
6502                 init_vmcs_shadow_fields();
6503
6504         if (!cpu_has_vmx_ept() ||
6505             !cpu_has_vmx_ept_4levels()) {
6506                 enable_ept = 0;
6507                 enable_unrestricted_guest = 0;
6508                 enable_ept_ad_bits = 0;
6509         }
6510
6511         if (!cpu_has_vmx_ept_ad_bits())
6512                 enable_ept_ad_bits = 0;
6513
6514         if (!cpu_has_vmx_unrestricted_guest())
6515                 enable_unrestricted_guest = 0;
6516
6517         if (!cpu_has_vmx_flexpriority())
6518                 flexpriority_enabled = 0;
6519
6520         /*
6521          * set_apic_access_page_addr() is used to reload apic access
6522          * page upon invalidation.  No need to do anything if not
6523          * using the APIC_ACCESS_ADDR VMCS field.
6524          */
6525         if (!flexpriority_enabled)
6526                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6527
6528         if (!cpu_has_vmx_tpr_shadow())
6529                 kvm_x86_ops->update_cr8_intercept = NULL;
6530
6531         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6532                 kvm_disable_largepages();
6533
6534         if (!cpu_has_vmx_ple())
6535                 ple_gap = 0;
6536
6537         if (!cpu_has_vmx_apicv()) {
6538                 enable_apicv = 0;
6539                 kvm_x86_ops->sync_pir_to_irr = NULL;
6540         }
6541
6542         if (cpu_has_vmx_tsc_scaling()) {
6543                 kvm_has_tsc_control = true;
6544                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6545                 kvm_tsc_scaling_ratio_frac_bits = 48;
6546         }
6547
6548         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6549         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6550         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6551         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6552         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6553         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6554         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6555
6556         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6557                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6558         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6559                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6560         memcpy(vmx_msr_bitmap_legacy_x2apic,
6561                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6562         memcpy(vmx_msr_bitmap_longmode_x2apic,
6563                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6564
6565         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6566
6567         for (msr = 0x800; msr <= 0x8ff; msr++) {
6568                 if (msr == 0x839 /* TMCCT */)
6569                         continue;
6570                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6571         }
6572
6573         /*
6574          * TPR reads and writes can be virtualized even if virtual interrupt
6575          * delivery is not in use.
6576          */
6577         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6578         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6579
6580         /* EOI */
6581         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6582         /* SELF-IPI */
6583         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6584
6585         if (enable_ept)
6586                 vmx_enable_tdp();
6587         else
6588                 kvm_disable_tdp();
6589
6590         update_ple_window_actual_max();
6591
6592         /*
6593          * Only enable PML when hardware supports PML feature, and both EPT
6594          * and EPT A/D bit features are enabled -- PML depends on them to work.
6595          */
6596         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6597                 enable_pml = 0;
6598
6599         if (!enable_pml) {
6600                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6601                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6602                 kvm_x86_ops->flush_log_dirty = NULL;
6603                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6604         }
6605
6606         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6607                 u64 vmx_msr;
6608
6609                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6610                 cpu_preemption_timer_multi =
6611                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6612         } else {
6613                 kvm_x86_ops->set_hv_timer = NULL;
6614                 kvm_x86_ops->cancel_hv_timer = NULL;
6615         }
6616
6617         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6618
6619         kvm_mce_cap_supported |= MCG_LMCE_P;
6620
6621         return alloc_kvm_area();
6622
6623 out:
6624         for (i = 0; i < VMX_BITMAP_NR; i++)
6625                 free_page((unsigned long)vmx_bitmap[i]);
6626
6627     return r;
6628 }
6629
6630 static __exit void hardware_unsetup(void)
6631 {
6632         int i;
6633
6634         for (i = 0; i < VMX_BITMAP_NR; i++)
6635                 free_page((unsigned long)vmx_bitmap[i]);
6636
6637         free_kvm_area();
6638 }
6639
6640 /*
6641  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6642  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6643  */
6644 static int handle_pause(struct kvm_vcpu *vcpu)
6645 {
6646         if (ple_gap)
6647                 grow_ple_window(vcpu);
6648
6649         kvm_vcpu_on_spin(vcpu);
6650         return kvm_skip_emulated_instruction(vcpu);
6651 }
6652
6653 static int handle_nop(struct kvm_vcpu *vcpu)
6654 {
6655         return kvm_skip_emulated_instruction(vcpu);
6656 }
6657
6658 static int handle_mwait(struct kvm_vcpu *vcpu)
6659 {
6660         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6661         return handle_nop(vcpu);
6662 }
6663
6664 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6665 {
6666         return 1;
6667 }
6668
6669 static int handle_monitor(struct kvm_vcpu *vcpu)
6670 {
6671         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6672         return handle_nop(vcpu);
6673 }
6674
6675 /*
6676  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6677  * We could reuse a single VMCS for all the L2 guests, but we also want the
6678  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6679  * allows keeping them loaded on the processor, and in the future will allow
6680  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6681  * every entry if they never change.
6682  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6683  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6684  *
6685  * The following functions allocate and free a vmcs02 in this pool.
6686  */
6687
6688 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6689 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6690 {
6691         struct vmcs02_list *item;
6692         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6693                 if (item->vmptr == vmx->nested.current_vmptr) {
6694                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6695                         return &item->vmcs02;
6696                 }
6697
6698         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6699                 /* Recycle the least recently used VMCS. */
6700                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6701                                        struct vmcs02_list, list);
6702                 item->vmptr = vmx->nested.current_vmptr;
6703                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6704                 return &item->vmcs02;
6705         }
6706
6707         /* Create a new VMCS */
6708         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6709         if (!item)
6710                 return NULL;
6711         item->vmcs02.vmcs = alloc_vmcs();
6712         item->vmcs02.shadow_vmcs = NULL;
6713         if (!item->vmcs02.vmcs) {
6714                 kfree(item);
6715                 return NULL;
6716         }
6717         loaded_vmcs_init(&item->vmcs02);
6718         item->vmptr = vmx->nested.current_vmptr;
6719         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6720         vmx->nested.vmcs02_num++;
6721         return &item->vmcs02;
6722 }
6723
6724 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6725 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6726 {
6727         struct vmcs02_list *item;
6728         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6729                 if (item->vmptr == vmptr) {
6730                         free_loaded_vmcs(&item->vmcs02);
6731                         list_del(&item->list);
6732                         kfree(item);
6733                         vmx->nested.vmcs02_num--;
6734                         return;
6735                 }
6736 }
6737
6738 /*
6739  * Free all VMCSs saved for this vcpu, except the one pointed by
6740  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6741  * must be &vmx->vmcs01.
6742  */
6743 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6744 {
6745         struct vmcs02_list *item, *n;
6746
6747         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6748         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6749                 /*
6750                  * Something will leak if the above WARN triggers.  Better than
6751                  * a use-after-free.
6752                  */
6753                 if (vmx->loaded_vmcs == &item->vmcs02)
6754                         continue;
6755
6756                 free_loaded_vmcs(&item->vmcs02);
6757                 list_del(&item->list);
6758                 kfree(item);
6759                 vmx->nested.vmcs02_num--;
6760         }
6761 }
6762
6763 /*
6764  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6765  * set the success or error code of an emulated VMX instruction, as specified
6766  * by Vol 2B, VMX Instruction Reference, "Conventions".
6767  */
6768 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6769 {
6770         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6771                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6772                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6773 }
6774
6775 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6776 {
6777         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6778                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6779                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6780                         | X86_EFLAGS_CF);
6781 }
6782
6783 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6784                                         u32 vm_instruction_error)
6785 {
6786         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6787                 /*
6788                  * failValid writes the error number to the current VMCS, which
6789                  * can't be done there isn't a current VMCS.
6790                  */
6791                 nested_vmx_failInvalid(vcpu);
6792                 return;
6793         }
6794         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6795                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6796                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6797                         | X86_EFLAGS_ZF);
6798         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6799         /*
6800          * We don't need to force a shadow sync because
6801          * VM_INSTRUCTION_ERROR is not shadowed
6802          */
6803 }
6804
6805 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6806 {
6807         /* TODO: not to reset guest simply here. */
6808         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6809         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6810 }
6811
6812 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6813 {
6814         struct vcpu_vmx *vmx =
6815                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6816
6817         vmx->nested.preemption_timer_expired = true;
6818         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6819         kvm_vcpu_kick(&vmx->vcpu);
6820
6821         return HRTIMER_NORESTART;
6822 }
6823
6824 /*
6825  * Decode the memory-address operand of a vmx instruction, as recorded on an
6826  * exit caused by such an instruction (run by a guest hypervisor).
6827  * On success, returns 0. When the operand is invalid, returns 1 and throws
6828  * #UD or #GP.
6829  */
6830 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6831                                  unsigned long exit_qualification,
6832                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6833 {
6834         gva_t off;
6835         bool exn;
6836         struct kvm_segment s;
6837
6838         /*
6839          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6840          * Execution", on an exit, vmx_instruction_info holds most of the
6841          * addressing components of the operand. Only the displacement part
6842          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6843          * For how an actual address is calculated from all these components,
6844          * refer to Vol. 1, "Operand Addressing".
6845          */
6846         int  scaling = vmx_instruction_info & 3;
6847         int  addr_size = (vmx_instruction_info >> 7) & 7;
6848         bool is_reg = vmx_instruction_info & (1u << 10);
6849         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6850         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6851         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6852         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6853         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6854
6855         if (is_reg) {
6856                 kvm_queue_exception(vcpu, UD_VECTOR);
6857                 return 1;
6858         }
6859
6860         /* Addr = segment_base + offset */
6861         /* offset = base + [index * scale] + displacement */
6862         off = exit_qualification; /* holds the displacement */
6863         if (base_is_valid)
6864                 off += kvm_register_read(vcpu, base_reg);
6865         if (index_is_valid)
6866                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6867         vmx_get_segment(vcpu, &s, seg_reg);
6868         *ret = s.base + off;
6869
6870         if (addr_size == 1) /* 32 bit */
6871                 *ret &= 0xffffffff;
6872
6873         /* Checks for #GP/#SS exceptions. */
6874         exn = false;
6875         if (is_long_mode(vcpu)) {
6876                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6877                  * non-canonical form. This is the only check on the memory
6878                  * destination for long mode!
6879                  */
6880                 exn = is_noncanonical_address(*ret);
6881         } else if (is_protmode(vcpu)) {
6882                 /* Protected mode: apply checks for segment validity in the
6883                  * following order:
6884                  * - segment type check (#GP(0) may be thrown)
6885                  * - usability check (#GP(0)/#SS(0))
6886                  * - limit check (#GP(0)/#SS(0))
6887                  */
6888                 if (wr)
6889                         /* #GP(0) if the destination operand is located in a
6890                          * read-only data segment or any code segment.
6891                          */
6892                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6893                 else
6894                         /* #GP(0) if the source operand is located in an
6895                          * execute-only code segment
6896                          */
6897                         exn = ((s.type & 0xa) == 8);
6898                 if (exn) {
6899                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6900                         return 1;
6901                 }
6902                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6903                  */
6904                 exn = (s.unusable != 0);
6905                 /* Protected mode: #GP(0)/#SS(0) if the memory
6906                  * operand is outside the segment limit.
6907                  */
6908                 exn = exn || (off + sizeof(u64) > s.limit);
6909         }
6910         if (exn) {
6911                 kvm_queue_exception_e(vcpu,
6912                                       seg_reg == VCPU_SREG_SS ?
6913                                                 SS_VECTOR : GP_VECTOR,
6914                                       0);
6915                 return 1;
6916         }
6917
6918         return 0;
6919 }
6920
6921 /*
6922  * This function performs the various checks including
6923  * - if it's 4KB aligned
6924  * - No bits beyond the physical address width are set
6925  * - Returns 0 on success or else 1
6926  * (Intel SDM Section 30.3)
6927  */
6928 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6929                                   gpa_t *vmpointer)
6930 {
6931         gva_t gva;
6932         gpa_t vmptr;
6933         struct x86_exception e;
6934         struct page *page;
6935         struct vcpu_vmx *vmx = to_vmx(vcpu);
6936         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6937
6938         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6939                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6940                 return 1;
6941
6942         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6943                                 sizeof(vmptr), &e)) {
6944                 kvm_inject_page_fault(vcpu, &e);
6945                 return 1;
6946         }
6947
6948         switch (exit_reason) {
6949         case EXIT_REASON_VMON:
6950                 /*
6951                  * SDM 3: 24.11.5
6952                  * The first 4 bytes of VMXON region contain the supported
6953                  * VMCS revision identifier
6954                  *
6955                  * Note - IA32_VMX_BASIC[48] will never be 1
6956                  * for the nested case;
6957                  * which replaces physical address width with 32
6958                  *
6959                  */
6960                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6961                         nested_vmx_failInvalid(vcpu);
6962                         return kvm_skip_emulated_instruction(vcpu);
6963                 }
6964
6965                 page = nested_get_page(vcpu, vmptr);
6966                 if (page == NULL) {
6967                         nested_vmx_failInvalid(vcpu);
6968                         return kvm_skip_emulated_instruction(vcpu);
6969                 }
6970                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6971                         kunmap(page);
6972                         nested_release_page_clean(page);
6973                         nested_vmx_failInvalid(vcpu);
6974                         return kvm_skip_emulated_instruction(vcpu);
6975                 }
6976                 kunmap(page);
6977                 nested_release_page_clean(page);
6978                 vmx->nested.vmxon_ptr = vmptr;
6979                 break;
6980         case EXIT_REASON_VMCLEAR:
6981                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6982                         nested_vmx_failValid(vcpu,
6983                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6984                         return kvm_skip_emulated_instruction(vcpu);
6985                 }
6986
6987                 if (vmptr == vmx->nested.vmxon_ptr) {
6988                         nested_vmx_failValid(vcpu,
6989                                              VMXERR_VMCLEAR_VMXON_POINTER);
6990                         return kvm_skip_emulated_instruction(vcpu);
6991                 }
6992                 break;
6993         case EXIT_REASON_VMPTRLD:
6994                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6995                         nested_vmx_failValid(vcpu,
6996                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6997                         return kvm_skip_emulated_instruction(vcpu);
6998                 }
6999
7000                 if (vmptr == vmx->nested.vmxon_ptr) {
7001                         nested_vmx_failValid(vcpu,
7002                                              VMXERR_VMPTRLD_VMXON_POINTER);
7003                         return kvm_skip_emulated_instruction(vcpu);
7004                 }
7005                 break;
7006         default:
7007                 return 1; /* shouldn't happen */
7008         }
7009
7010         if (vmpointer)
7011                 *vmpointer = vmptr;
7012         return 0;
7013 }
7014
7015 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7016 {
7017         struct vcpu_vmx *vmx = to_vmx(vcpu);
7018         struct vmcs *shadow_vmcs;
7019
7020         if (cpu_has_vmx_msr_bitmap()) {
7021                 vmx->nested.msr_bitmap =
7022                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7023                 if (!vmx->nested.msr_bitmap)
7024                         goto out_msr_bitmap;
7025         }
7026
7027         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7028         if (!vmx->nested.cached_vmcs12)
7029                 goto out_cached_vmcs12;
7030
7031         if (enable_shadow_vmcs) {
7032                 shadow_vmcs = alloc_vmcs();
7033                 if (!shadow_vmcs)
7034                         goto out_shadow_vmcs;
7035                 /* mark vmcs as shadow */
7036                 shadow_vmcs->revision_id |= (1u << 31);
7037                 /* init shadow vmcs */
7038                 vmcs_clear(shadow_vmcs);
7039                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7040         }
7041
7042         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7043         vmx->nested.vmcs02_num = 0;
7044
7045         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7046                      HRTIMER_MODE_REL_PINNED);
7047         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7048
7049         vmx->nested.vmxon = true;
7050         return 0;
7051
7052 out_shadow_vmcs:
7053         kfree(vmx->nested.cached_vmcs12);
7054
7055 out_cached_vmcs12:
7056         free_page((unsigned long)vmx->nested.msr_bitmap);
7057
7058 out_msr_bitmap:
7059         return -ENOMEM;
7060 }
7061
7062 /*
7063  * Emulate the VMXON instruction.
7064  * Currently, we just remember that VMX is active, and do not save or even
7065  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7066  * do not currently need to store anything in that guest-allocated memory
7067  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7068  * argument is different from the VMXON pointer (which the spec says they do).
7069  */
7070 static int handle_vmon(struct kvm_vcpu *vcpu)
7071 {
7072         int ret;
7073         struct kvm_segment cs;
7074         struct vcpu_vmx *vmx = to_vmx(vcpu);
7075         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7076                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7077
7078         /* The Intel VMX Instruction Reference lists a bunch of bits that
7079          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7080          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7081          * Otherwise, we should fail with #UD. We test these now:
7082          */
7083         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7084             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7085             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7086                 kvm_queue_exception(vcpu, UD_VECTOR);
7087                 return 1;
7088         }
7089
7090         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7091         if (is_long_mode(vcpu) && !cs.l) {
7092                 kvm_queue_exception(vcpu, UD_VECTOR);
7093                 return 1;
7094         }
7095
7096         if (vmx_get_cpl(vcpu)) {
7097                 kvm_inject_gp(vcpu, 0);
7098                 return 1;
7099         }
7100
7101         if (vmx->nested.vmxon) {
7102                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7103                 return kvm_skip_emulated_instruction(vcpu);
7104         }
7105
7106         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7107                         != VMXON_NEEDED_FEATURES) {
7108                 kvm_inject_gp(vcpu, 0);
7109                 return 1;
7110         }
7111
7112         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7113                 return 1;
7114
7115         ret = enter_vmx_operation(vcpu);
7116         if (ret)
7117                 return ret;
7118
7119         nested_vmx_succeed(vcpu);
7120         return kvm_skip_emulated_instruction(vcpu);
7121 }
7122
7123 /*
7124  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7125  * for running VMX instructions (except VMXON, whose prerequisites are
7126  * slightly different). It also specifies what exception to inject otherwise.
7127  */
7128 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7129 {
7130         struct kvm_segment cs;
7131         struct vcpu_vmx *vmx = to_vmx(vcpu);
7132
7133         if (!vmx->nested.vmxon) {
7134                 kvm_queue_exception(vcpu, UD_VECTOR);
7135                 return 0;
7136         }
7137
7138         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7139         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7140             (is_long_mode(vcpu) && !cs.l)) {
7141                 kvm_queue_exception(vcpu, UD_VECTOR);
7142                 return 0;
7143         }
7144
7145         if (vmx_get_cpl(vcpu)) {
7146                 kvm_inject_gp(vcpu, 0);
7147                 return 0;
7148         }
7149
7150         return 1;
7151 }
7152
7153 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7154 {
7155         if (vmx->nested.current_vmptr == -1ull)
7156                 return;
7157
7158         /* current_vmptr and current_vmcs12 are always set/reset together */
7159         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7160                 return;
7161
7162         if (enable_shadow_vmcs) {
7163                 /* copy to memory all shadowed fields in case
7164                    they were modified */
7165                 copy_shadow_to_vmcs12(vmx);
7166                 vmx->nested.sync_shadow_vmcs = false;
7167                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7168                                 SECONDARY_EXEC_SHADOW_VMCS);
7169                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7170         }
7171         vmx->nested.posted_intr_nv = -1;
7172
7173         /* Flush VMCS12 to guest memory */
7174         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7175                VMCS12_SIZE);
7176
7177         kunmap(vmx->nested.current_vmcs12_page);
7178         nested_release_page(vmx->nested.current_vmcs12_page);
7179         vmx->nested.current_vmptr = -1ull;
7180         vmx->nested.current_vmcs12 = NULL;
7181 }
7182
7183 /*
7184  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7185  * just stops using VMX.
7186  */
7187 static void free_nested(struct vcpu_vmx *vmx)
7188 {
7189         if (!vmx->nested.vmxon)
7190                 return;
7191
7192         vmx->nested.vmxon = false;
7193         free_vpid(vmx->nested.vpid02);
7194         nested_release_vmcs12(vmx);
7195         if (vmx->nested.msr_bitmap) {
7196                 free_page((unsigned long)vmx->nested.msr_bitmap);
7197                 vmx->nested.msr_bitmap = NULL;
7198         }
7199         if (enable_shadow_vmcs) {
7200                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7201                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7202                 vmx->vmcs01.shadow_vmcs = NULL;
7203         }
7204         kfree(vmx->nested.cached_vmcs12);
7205         /* Unpin physical memory we referred to in current vmcs02 */
7206         if (vmx->nested.apic_access_page) {
7207                 nested_release_page(vmx->nested.apic_access_page);
7208                 vmx->nested.apic_access_page = NULL;
7209         }
7210         if (vmx->nested.virtual_apic_page) {
7211                 nested_release_page(vmx->nested.virtual_apic_page);
7212                 vmx->nested.virtual_apic_page = NULL;
7213         }
7214         if (vmx->nested.pi_desc_page) {
7215                 kunmap(vmx->nested.pi_desc_page);
7216                 nested_release_page(vmx->nested.pi_desc_page);
7217                 vmx->nested.pi_desc_page = NULL;
7218                 vmx->nested.pi_desc = NULL;
7219         }
7220
7221         nested_free_all_saved_vmcss(vmx);
7222 }
7223
7224 /* Emulate the VMXOFF instruction */
7225 static int handle_vmoff(struct kvm_vcpu *vcpu)
7226 {
7227         if (!nested_vmx_check_permission(vcpu))
7228                 return 1;
7229         free_nested(to_vmx(vcpu));
7230         nested_vmx_succeed(vcpu);
7231         return kvm_skip_emulated_instruction(vcpu);
7232 }
7233
7234 /* Emulate the VMCLEAR instruction */
7235 static int handle_vmclear(struct kvm_vcpu *vcpu)
7236 {
7237         struct vcpu_vmx *vmx = to_vmx(vcpu);
7238         u32 zero = 0;
7239         gpa_t vmptr;
7240
7241         if (!nested_vmx_check_permission(vcpu))
7242                 return 1;
7243
7244         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7245                 return 1;
7246
7247         if (vmptr == vmx->nested.current_vmptr)
7248                 nested_release_vmcs12(vmx);
7249
7250         kvm_vcpu_write_guest(vcpu,
7251                         vmptr + offsetof(struct vmcs12, launch_state),
7252                         &zero, sizeof(zero));
7253
7254         nested_free_vmcs02(vmx, vmptr);
7255
7256         nested_vmx_succeed(vcpu);
7257         return kvm_skip_emulated_instruction(vcpu);
7258 }
7259
7260 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7261
7262 /* Emulate the VMLAUNCH instruction */
7263 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7264 {
7265         return nested_vmx_run(vcpu, true);
7266 }
7267
7268 /* Emulate the VMRESUME instruction */
7269 static int handle_vmresume(struct kvm_vcpu *vcpu)
7270 {
7271
7272         return nested_vmx_run(vcpu, false);
7273 }
7274
7275 enum vmcs_field_type {
7276         VMCS_FIELD_TYPE_U16 = 0,
7277         VMCS_FIELD_TYPE_U64 = 1,
7278         VMCS_FIELD_TYPE_U32 = 2,
7279         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7280 };
7281
7282 static inline int vmcs_field_type(unsigned long field)
7283 {
7284         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7285                 return VMCS_FIELD_TYPE_U32;
7286         return (field >> 13) & 0x3 ;
7287 }
7288
7289 static inline int vmcs_field_readonly(unsigned long field)
7290 {
7291         return (((field >> 10) & 0x3) == 1);
7292 }
7293
7294 /*
7295  * Read a vmcs12 field. Since these can have varying lengths and we return
7296  * one type, we chose the biggest type (u64) and zero-extend the return value
7297  * to that size. Note that the caller, handle_vmread, might need to use only
7298  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7299  * 64-bit fields are to be returned).
7300  */
7301 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7302                                   unsigned long field, u64 *ret)
7303 {
7304         short offset = vmcs_field_to_offset(field);
7305         char *p;
7306
7307         if (offset < 0)
7308                 return offset;
7309
7310         p = ((char *)(get_vmcs12(vcpu))) + offset;
7311
7312         switch (vmcs_field_type(field)) {
7313         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7314                 *ret = *((natural_width *)p);
7315                 return 0;
7316         case VMCS_FIELD_TYPE_U16:
7317                 *ret = *((u16 *)p);
7318                 return 0;
7319         case VMCS_FIELD_TYPE_U32:
7320                 *ret = *((u32 *)p);
7321                 return 0;
7322         case VMCS_FIELD_TYPE_U64:
7323                 *ret = *((u64 *)p);
7324                 return 0;
7325         default:
7326                 WARN_ON(1);
7327                 return -ENOENT;
7328         }
7329 }
7330
7331
7332 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7333                                    unsigned long field, u64 field_value){
7334         short offset = vmcs_field_to_offset(field);
7335         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7336         if (offset < 0)
7337                 return offset;
7338
7339         switch (vmcs_field_type(field)) {
7340         case VMCS_FIELD_TYPE_U16:
7341                 *(u16 *)p = field_value;
7342                 return 0;
7343         case VMCS_FIELD_TYPE_U32:
7344                 *(u32 *)p = field_value;
7345                 return 0;
7346         case VMCS_FIELD_TYPE_U64:
7347                 *(u64 *)p = field_value;
7348                 return 0;
7349         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7350                 *(natural_width *)p = field_value;
7351                 return 0;
7352         default:
7353                 WARN_ON(1);
7354                 return -ENOENT;
7355         }
7356
7357 }
7358
7359 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7360 {
7361         int i;
7362         unsigned long field;
7363         u64 field_value;
7364         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7365         const unsigned long *fields = shadow_read_write_fields;
7366         const int num_fields = max_shadow_read_write_fields;
7367
7368         preempt_disable();
7369
7370         vmcs_load(shadow_vmcs);
7371
7372         for (i = 0; i < num_fields; i++) {
7373                 field = fields[i];
7374                 switch (vmcs_field_type(field)) {
7375                 case VMCS_FIELD_TYPE_U16:
7376                         field_value = vmcs_read16(field);
7377                         break;
7378                 case VMCS_FIELD_TYPE_U32:
7379                         field_value = vmcs_read32(field);
7380                         break;
7381                 case VMCS_FIELD_TYPE_U64:
7382                         field_value = vmcs_read64(field);
7383                         break;
7384                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7385                         field_value = vmcs_readl(field);
7386                         break;
7387                 default:
7388                         WARN_ON(1);
7389                         continue;
7390                 }
7391                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7392         }
7393
7394         vmcs_clear(shadow_vmcs);
7395         vmcs_load(vmx->loaded_vmcs->vmcs);
7396
7397         preempt_enable();
7398 }
7399
7400 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7401 {
7402         const unsigned long *fields[] = {
7403                 shadow_read_write_fields,
7404                 shadow_read_only_fields
7405         };
7406         const int max_fields[] = {
7407                 max_shadow_read_write_fields,
7408                 max_shadow_read_only_fields
7409         };
7410         int i, q;
7411         unsigned long field;
7412         u64 field_value = 0;
7413         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7414
7415         vmcs_load(shadow_vmcs);
7416
7417         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7418                 for (i = 0; i < max_fields[q]; i++) {
7419                         field = fields[q][i];
7420                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7421
7422                         switch (vmcs_field_type(field)) {
7423                         case VMCS_FIELD_TYPE_U16:
7424                                 vmcs_write16(field, (u16)field_value);
7425                                 break;
7426                         case VMCS_FIELD_TYPE_U32:
7427                                 vmcs_write32(field, (u32)field_value);
7428                                 break;
7429                         case VMCS_FIELD_TYPE_U64:
7430                                 vmcs_write64(field, (u64)field_value);
7431                                 break;
7432                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7433                                 vmcs_writel(field, (long)field_value);
7434                                 break;
7435                         default:
7436                                 WARN_ON(1);
7437                                 break;
7438                         }
7439                 }
7440         }
7441
7442         vmcs_clear(shadow_vmcs);
7443         vmcs_load(vmx->loaded_vmcs->vmcs);
7444 }
7445
7446 /*
7447  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7448  * used before) all generate the same failure when it is missing.
7449  */
7450 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7451 {
7452         struct vcpu_vmx *vmx = to_vmx(vcpu);
7453         if (vmx->nested.current_vmptr == -1ull) {
7454                 nested_vmx_failInvalid(vcpu);
7455                 return 0;
7456         }
7457         return 1;
7458 }
7459
7460 static int handle_vmread(struct kvm_vcpu *vcpu)
7461 {
7462         unsigned long field;
7463         u64 field_value;
7464         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7465         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7466         gva_t gva = 0;
7467
7468         if (!nested_vmx_check_permission(vcpu))
7469                 return 1;
7470
7471         if (!nested_vmx_check_vmcs12(vcpu))
7472                 return kvm_skip_emulated_instruction(vcpu);
7473
7474         /* Decode instruction info and find the field to read */
7475         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7476         /* Read the field, zero-extended to a u64 field_value */
7477         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7478                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7479                 return kvm_skip_emulated_instruction(vcpu);
7480         }
7481         /*
7482          * Now copy part of this value to register or memory, as requested.
7483          * Note that the number of bits actually copied is 32 or 64 depending
7484          * on the guest's mode (32 or 64 bit), not on the given field's length.
7485          */
7486         if (vmx_instruction_info & (1u << 10)) {
7487                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7488                         field_value);
7489         } else {
7490                 if (get_vmx_mem_address(vcpu, exit_qualification,
7491                                 vmx_instruction_info, true, &gva))
7492                         return 1;
7493                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7494                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7495                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7496         }
7497
7498         nested_vmx_succeed(vcpu);
7499         return kvm_skip_emulated_instruction(vcpu);
7500 }
7501
7502
7503 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7504 {
7505         unsigned long field;
7506         gva_t gva;
7507         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7508         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7509         /* The value to write might be 32 or 64 bits, depending on L1's long
7510          * mode, and eventually we need to write that into a field of several
7511          * possible lengths. The code below first zero-extends the value to 64
7512          * bit (field_value), and then copies only the appropriate number of
7513          * bits into the vmcs12 field.
7514          */
7515         u64 field_value = 0;
7516         struct x86_exception e;
7517
7518         if (!nested_vmx_check_permission(vcpu))
7519                 return 1;
7520
7521         if (!nested_vmx_check_vmcs12(vcpu))
7522                 return kvm_skip_emulated_instruction(vcpu);
7523
7524         if (vmx_instruction_info & (1u << 10))
7525                 field_value = kvm_register_readl(vcpu,
7526                         (((vmx_instruction_info) >> 3) & 0xf));
7527         else {
7528                 if (get_vmx_mem_address(vcpu, exit_qualification,
7529                                 vmx_instruction_info, false, &gva))
7530                         return 1;
7531                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7532                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7533                         kvm_inject_page_fault(vcpu, &e);
7534                         return 1;
7535                 }
7536         }
7537
7538
7539         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7540         if (vmcs_field_readonly(field)) {
7541                 nested_vmx_failValid(vcpu,
7542                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7543                 return kvm_skip_emulated_instruction(vcpu);
7544         }
7545
7546         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7547                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7548                 return kvm_skip_emulated_instruction(vcpu);
7549         }
7550
7551         nested_vmx_succeed(vcpu);
7552         return kvm_skip_emulated_instruction(vcpu);
7553 }
7554
7555 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7556 {
7557         vmx->nested.current_vmptr = vmptr;
7558         if (enable_shadow_vmcs) {
7559                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7560                               SECONDARY_EXEC_SHADOW_VMCS);
7561                 vmcs_write64(VMCS_LINK_POINTER,
7562                              __pa(vmx->vmcs01.shadow_vmcs));
7563                 vmx->nested.sync_shadow_vmcs = true;
7564         }
7565 }
7566
7567 /* Emulate the VMPTRLD instruction */
7568 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7569 {
7570         struct vcpu_vmx *vmx = to_vmx(vcpu);
7571         gpa_t vmptr;
7572
7573         if (!nested_vmx_check_permission(vcpu))
7574                 return 1;
7575
7576         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7577                 return 1;
7578
7579         if (vmx->nested.current_vmptr != vmptr) {
7580                 struct vmcs12 *new_vmcs12;
7581                 struct page *page;
7582                 page = nested_get_page(vcpu, vmptr);
7583                 if (page == NULL) {
7584                         nested_vmx_failInvalid(vcpu);
7585                         return kvm_skip_emulated_instruction(vcpu);
7586                 }
7587                 new_vmcs12 = kmap(page);
7588                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7589                         kunmap(page);
7590                         nested_release_page_clean(page);
7591                         nested_vmx_failValid(vcpu,
7592                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7593                         return kvm_skip_emulated_instruction(vcpu);
7594                 }
7595
7596                 nested_release_vmcs12(vmx);
7597                 vmx->nested.current_vmcs12 = new_vmcs12;
7598                 vmx->nested.current_vmcs12_page = page;
7599                 /*
7600                  * Load VMCS12 from guest memory since it is not already
7601                  * cached.
7602                  */
7603                 memcpy(vmx->nested.cached_vmcs12,
7604                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7605                 set_current_vmptr(vmx, vmptr);
7606         }
7607
7608         nested_vmx_succeed(vcpu);
7609         return kvm_skip_emulated_instruction(vcpu);
7610 }
7611
7612 /* Emulate the VMPTRST instruction */
7613 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7614 {
7615         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7616         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7617         gva_t vmcs_gva;
7618         struct x86_exception e;
7619
7620         if (!nested_vmx_check_permission(vcpu))
7621                 return 1;
7622
7623         if (get_vmx_mem_address(vcpu, exit_qualification,
7624                         vmx_instruction_info, true, &vmcs_gva))
7625                 return 1;
7626         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7627         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7628                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7629                                  sizeof(u64), &e)) {
7630                 kvm_inject_page_fault(vcpu, &e);
7631                 return 1;
7632         }
7633         nested_vmx_succeed(vcpu);
7634         return kvm_skip_emulated_instruction(vcpu);
7635 }
7636
7637 /* Emulate the INVEPT instruction */
7638 static int handle_invept(struct kvm_vcpu *vcpu)
7639 {
7640         struct vcpu_vmx *vmx = to_vmx(vcpu);
7641         u32 vmx_instruction_info, types;
7642         unsigned long type;
7643         gva_t gva;
7644         struct x86_exception e;
7645         struct {
7646                 u64 eptp, gpa;
7647         } operand;
7648
7649         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7650               SECONDARY_EXEC_ENABLE_EPT) ||
7651             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7652                 kvm_queue_exception(vcpu, UD_VECTOR);
7653                 return 1;
7654         }
7655
7656         if (!nested_vmx_check_permission(vcpu))
7657                 return 1;
7658
7659         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7660                 kvm_queue_exception(vcpu, UD_VECTOR);
7661                 return 1;
7662         }
7663
7664         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7665         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7666
7667         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7668
7669         if (type >= 32 || !(types & (1 << type))) {
7670                 nested_vmx_failValid(vcpu,
7671                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7672                 return kvm_skip_emulated_instruction(vcpu);
7673         }
7674
7675         /* According to the Intel VMX instruction reference, the memory
7676          * operand is read even if it isn't needed (e.g., for type==global)
7677          */
7678         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7679                         vmx_instruction_info, false, &gva))
7680                 return 1;
7681         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7682                                 sizeof(operand), &e)) {
7683                 kvm_inject_page_fault(vcpu, &e);
7684                 return 1;
7685         }
7686
7687         switch (type) {
7688         case VMX_EPT_EXTENT_GLOBAL:
7689         /*
7690          * TODO: track mappings and invalidate
7691          * single context requests appropriately
7692          */
7693         case VMX_EPT_EXTENT_CONTEXT:
7694                 kvm_mmu_sync_roots(vcpu);
7695                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7696                 nested_vmx_succeed(vcpu);
7697                 break;
7698         default:
7699                 BUG_ON(1);
7700                 break;
7701         }
7702
7703         return kvm_skip_emulated_instruction(vcpu);
7704 }
7705
7706 static int handle_invvpid(struct kvm_vcpu *vcpu)
7707 {
7708         struct vcpu_vmx *vmx = to_vmx(vcpu);
7709         u32 vmx_instruction_info;
7710         unsigned long type, types;
7711         gva_t gva;
7712         struct x86_exception e;
7713         int vpid;
7714
7715         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7716               SECONDARY_EXEC_ENABLE_VPID) ||
7717                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7718                 kvm_queue_exception(vcpu, UD_VECTOR);
7719                 return 1;
7720         }
7721
7722         if (!nested_vmx_check_permission(vcpu))
7723                 return 1;
7724
7725         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7726         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7727
7728         types = (vmx->nested.nested_vmx_vpid_caps &
7729                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7730
7731         if (type >= 32 || !(types & (1 << type))) {
7732                 nested_vmx_failValid(vcpu,
7733                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7734                 return kvm_skip_emulated_instruction(vcpu);
7735         }
7736
7737         /* according to the intel vmx instruction reference, the memory
7738          * operand is read even if it isn't needed (e.g., for type==global)
7739          */
7740         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7741                         vmx_instruction_info, false, &gva))
7742                 return 1;
7743         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7744                                 sizeof(u32), &e)) {
7745                 kvm_inject_page_fault(vcpu, &e);
7746                 return 1;
7747         }
7748
7749         switch (type) {
7750         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7751         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7752         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7753                 if (!vpid) {
7754                         nested_vmx_failValid(vcpu,
7755                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7756                         return kvm_skip_emulated_instruction(vcpu);
7757                 }
7758                 break;
7759         case VMX_VPID_EXTENT_ALL_CONTEXT:
7760                 break;
7761         default:
7762                 WARN_ON_ONCE(1);
7763                 return kvm_skip_emulated_instruction(vcpu);
7764         }
7765
7766         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7767         nested_vmx_succeed(vcpu);
7768
7769         return kvm_skip_emulated_instruction(vcpu);
7770 }
7771
7772 static int handle_pml_full(struct kvm_vcpu *vcpu)
7773 {
7774         unsigned long exit_qualification;
7775
7776         trace_kvm_pml_full(vcpu->vcpu_id);
7777
7778         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7779
7780         /*
7781          * PML buffer FULL happened while executing iret from NMI,
7782          * "blocked by NMI" bit has to be set before next VM entry.
7783          */
7784         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7785                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7786                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7787                                 GUEST_INTR_STATE_NMI);
7788
7789         /*
7790          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7791          * here.., and there's no userspace involvement needed for PML.
7792          */
7793         return 1;
7794 }
7795
7796 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7797 {
7798         kvm_lapic_expired_hv_timer(vcpu);
7799         return 1;
7800 }
7801
7802 /*
7803  * The exit handlers return 1 if the exit was handled fully and guest execution
7804  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7805  * to be done to userspace and return 0.
7806  */
7807 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7808         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7809         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7810         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7811         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7812         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7813         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7814         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7815         [EXIT_REASON_CPUID]                   = handle_cpuid,
7816         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7817         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7818         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7819         [EXIT_REASON_HLT]                     = handle_halt,
7820         [EXIT_REASON_INVD]                    = handle_invd,
7821         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7822         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7823         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7824         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7825         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7826         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7827         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7828         [EXIT_REASON_VMREAD]                  = handle_vmread,
7829         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7830         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7831         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7832         [EXIT_REASON_VMON]                    = handle_vmon,
7833         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7834         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7835         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7836         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7837         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7838         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7839         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7840         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7841         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7842         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7843         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7844         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7845         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7846         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7847         [EXIT_REASON_INVEPT]                  = handle_invept,
7848         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7849         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7850         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7851         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7852         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7853 };
7854
7855 static const int kvm_vmx_max_exit_handlers =
7856         ARRAY_SIZE(kvm_vmx_exit_handlers);
7857
7858 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7859                                        struct vmcs12 *vmcs12)
7860 {
7861         unsigned long exit_qualification;
7862         gpa_t bitmap, last_bitmap;
7863         unsigned int port;
7864         int size;
7865         u8 b;
7866
7867         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7868                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7869
7870         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7871
7872         port = exit_qualification >> 16;
7873         size = (exit_qualification & 7) + 1;
7874
7875         last_bitmap = (gpa_t)-1;
7876         b = -1;
7877
7878         while (size > 0) {
7879                 if (port < 0x8000)
7880                         bitmap = vmcs12->io_bitmap_a;
7881                 else if (port < 0x10000)
7882                         bitmap = vmcs12->io_bitmap_b;
7883                 else
7884                         return true;
7885                 bitmap += (port & 0x7fff) / 8;
7886
7887                 if (last_bitmap != bitmap)
7888                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7889                                 return true;
7890                 if (b & (1 << (port & 7)))
7891                         return true;
7892
7893                 port++;
7894                 size--;
7895                 last_bitmap = bitmap;
7896         }
7897
7898         return false;
7899 }
7900
7901 /*
7902  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7903  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7904  * disinterest in the current event (read or write a specific MSR) by using an
7905  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7906  */
7907 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7908         struct vmcs12 *vmcs12, u32 exit_reason)
7909 {
7910         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7911         gpa_t bitmap;
7912
7913         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7914                 return true;
7915
7916         /*
7917          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7918          * for the four combinations of read/write and low/high MSR numbers.
7919          * First we need to figure out which of the four to use:
7920          */
7921         bitmap = vmcs12->msr_bitmap;
7922         if (exit_reason == EXIT_REASON_MSR_WRITE)
7923                 bitmap += 2048;
7924         if (msr_index >= 0xc0000000) {
7925                 msr_index -= 0xc0000000;
7926                 bitmap += 1024;
7927         }
7928
7929         /* Then read the msr_index'th bit from this bitmap: */
7930         if (msr_index < 1024*8) {
7931                 unsigned char b;
7932                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7933                         return true;
7934                 return 1 & (b >> (msr_index & 7));
7935         } else
7936                 return true; /* let L1 handle the wrong parameter */
7937 }
7938
7939 /*
7940  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7941  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7942  * intercept (via guest_host_mask etc.) the current event.
7943  */
7944 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7945         struct vmcs12 *vmcs12)
7946 {
7947         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7948         int cr = exit_qualification & 15;
7949         int reg = (exit_qualification >> 8) & 15;
7950         unsigned long val = kvm_register_readl(vcpu, reg);
7951
7952         switch ((exit_qualification >> 4) & 3) {
7953         case 0: /* mov to cr */
7954                 switch (cr) {
7955                 case 0:
7956                         if (vmcs12->cr0_guest_host_mask &
7957                             (val ^ vmcs12->cr0_read_shadow))
7958                                 return true;
7959                         break;
7960                 case 3:
7961                         if ((vmcs12->cr3_target_count >= 1 &&
7962                                         vmcs12->cr3_target_value0 == val) ||
7963                                 (vmcs12->cr3_target_count >= 2 &&
7964                                         vmcs12->cr3_target_value1 == val) ||
7965                                 (vmcs12->cr3_target_count >= 3 &&
7966                                         vmcs12->cr3_target_value2 == val) ||
7967                                 (vmcs12->cr3_target_count >= 4 &&
7968                                         vmcs12->cr3_target_value3 == val))
7969                                 return false;
7970                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7971                                 return true;
7972                         break;
7973                 case 4:
7974                         if (vmcs12->cr4_guest_host_mask &
7975                             (vmcs12->cr4_read_shadow ^ val))
7976                                 return true;
7977                         break;
7978                 case 8:
7979                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7980                                 return true;
7981                         break;
7982                 }
7983                 break;
7984         case 2: /* clts */
7985                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7986                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7987                         return true;
7988                 break;
7989         case 1: /* mov from cr */
7990                 switch (cr) {
7991                 case 3:
7992                         if (vmcs12->cpu_based_vm_exec_control &
7993                             CPU_BASED_CR3_STORE_EXITING)
7994                                 return true;
7995                         break;
7996                 case 8:
7997                         if (vmcs12->cpu_based_vm_exec_control &
7998                             CPU_BASED_CR8_STORE_EXITING)
7999                                 return true;
8000                         break;
8001                 }
8002                 break;
8003         case 3: /* lmsw */
8004                 /*
8005                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8006                  * cr0. Other attempted changes are ignored, with no exit.
8007                  */
8008                 if (vmcs12->cr0_guest_host_mask & 0xe &
8009                     (val ^ vmcs12->cr0_read_shadow))
8010                         return true;
8011                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8012                     !(vmcs12->cr0_read_shadow & 0x1) &&
8013                     (val & 0x1))
8014                         return true;
8015                 break;
8016         }
8017         return false;
8018 }
8019
8020 /*
8021  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8022  * should handle it ourselves in L0 (and then continue L2). Only call this
8023  * when in is_guest_mode (L2).
8024  */
8025 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8026 {
8027         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8028         struct vcpu_vmx *vmx = to_vmx(vcpu);
8029         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8030         u32 exit_reason = vmx->exit_reason;
8031
8032         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8033                                 vmcs_readl(EXIT_QUALIFICATION),
8034                                 vmx->idt_vectoring_info,
8035                                 intr_info,
8036                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8037                                 KVM_ISA_VMX);
8038
8039         if (vmx->nested.nested_run_pending)
8040                 return false;
8041
8042         if (unlikely(vmx->fail)) {
8043                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8044                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8045                 return true;
8046         }
8047
8048         switch (exit_reason) {
8049         case EXIT_REASON_EXCEPTION_NMI:
8050                 if (is_nmi(intr_info))
8051                         return false;
8052                 else if (is_page_fault(intr_info))
8053                         return enable_ept;
8054                 else if (is_no_device(intr_info) &&
8055                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8056                         return false;
8057                 else if (is_debug(intr_info) &&
8058                          vcpu->guest_debug &
8059                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8060                         return false;
8061                 else if (is_breakpoint(intr_info) &&
8062                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8063                         return false;
8064                 return vmcs12->exception_bitmap &
8065                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8066         case EXIT_REASON_EXTERNAL_INTERRUPT:
8067                 return false;
8068         case EXIT_REASON_TRIPLE_FAULT:
8069                 return true;
8070         case EXIT_REASON_PENDING_INTERRUPT:
8071                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8072         case EXIT_REASON_NMI_WINDOW:
8073                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8074         case EXIT_REASON_TASK_SWITCH:
8075                 return true;
8076         case EXIT_REASON_CPUID:
8077                 return true;
8078         case EXIT_REASON_HLT:
8079                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8080         case EXIT_REASON_INVD:
8081                 return true;
8082         case EXIT_REASON_INVLPG:
8083                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8084         case EXIT_REASON_RDPMC:
8085                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8086         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8087                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8088         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8089         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8090         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8091         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8092         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8093         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8094                 /*
8095                  * VMX instructions trap unconditionally. This allows L1 to
8096                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8097                  */
8098                 return true;
8099         case EXIT_REASON_CR_ACCESS:
8100                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8101         case EXIT_REASON_DR_ACCESS:
8102                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8103         case EXIT_REASON_IO_INSTRUCTION:
8104                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8105         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8106                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8107         case EXIT_REASON_MSR_READ:
8108         case EXIT_REASON_MSR_WRITE:
8109                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8110         case EXIT_REASON_INVALID_STATE:
8111                 return true;
8112         case EXIT_REASON_MWAIT_INSTRUCTION:
8113                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8114         case EXIT_REASON_MONITOR_TRAP_FLAG:
8115                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8116         case EXIT_REASON_MONITOR_INSTRUCTION:
8117                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8118         case EXIT_REASON_PAUSE_INSTRUCTION:
8119                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8120                         nested_cpu_has2(vmcs12,
8121                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8122         case EXIT_REASON_MCE_DURING_VMENTRY:
8123                 return false;
8124         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8125                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8126         case EXIT_REASON_APIC_ACCESS:
8127                 return nested_cpu_has2(vmcs12,
8128                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8129         case EXIT_REASON_APIC_WRITE:
8130         case EXIT_REASON_EOI_INDUCED:
8131                 /* apic_write and eoi_induced should exit unconditionally. */
8132                 return true;
8133         case EXIT_REASON_EPT_VIOLATION:
8134                 /*
8135                  * L0 always deals with the EPT violation. If nested EPT is
8136                  * used, and the nested mmu code discovers that the address is
8137                  * missing in the guest EPT table (EPT12), the EPT violation
8138                  * will be injected with nested_ept_inject_page_fault()
8139                  */
8140                 return false;
8141         case EXIT_REASON_EPT_MISCONFIG:
8142                 /*
8143                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8144                  * table (shadow on EPT) or a merged EPT table that L0 built
8145                  * (EPT on EPT). So any problems with the structure of the
8146                  * table is L0's fault.
8147                  */
8148                 return false;
8149         case EXIT_REASON_WBINVD:
8150                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8151         case EXIT_REASON_XSETBV:
8152                 return true;
8153         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8154                 /*
8155                  * This should never happen, since it is not possible to
8156                  * set XSS to a non-zero value---neither in L1 nor in L2.
8157                  * If if it were, XSS would have to be checked against
8158                  * the XSS exit bitmap in vmcs12.
8159                  */
8160                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8161         case EXIT_REASON_PREEMPTION_TIMER:
8162                 return false;
8163         default:
8164                 return true;
8165         }
8166 }
8167
8168 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8169 {
8170         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8171         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8172 }
8173
8174 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8175 {
8176         if (vmx->pml_pg) {
8177                 __free_page(vmx->pml_pg);
8178                 vmx->pml_pg = NULL;
8179         }
8180 }
8181
8182 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8183 {
8184         struct vcpu_vmx *vmx = to_vmx(vcpu);
8185         u64 *pml_buf;
8186         u16 pml_idx;
8187
8188         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8189
8190         /* Do nothing if PML buffer is empty */
8191         if (pml_idx == (PML_ENTITY_NUM - 1))
8192                 return;
8193
8194         /* PML index always points to next available PML buffer entity */
8195         if (pml_idx >= PML_ENTITY_NUM)
8196                 pml_idx = 0;
8197         else
8198                 pml_idx++;
8199
8200         pml_buf = page_address(vmx->pml_pg);
8201         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8202                 u64 gpa;
8203
8204                 gpa = pml_buf[pml_idx];
8205                 WARN_ON(gpa & (PAGE_SIZE - 1));
8206                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8207         }
8208
8209         /* reset PML index */
8210         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8211 }
8212
8213 /*
8214  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8215  * Called before reporting dirty_bitmap to userspace.
8216  */
8217 static void kvm_flush_pml_buffers(struct kvm *kvm)
8218 {
8219         int i;
8220         struct kvm_vcpu *vcpu;
8221         /*
8222          * We only need to kick vcpu out of guest mode here, as PML buffer
8223          * is flushed at beginning of all VMEXITs, and it's obvious that only
8224          * vcpus running in guest are possible to have unflushed GPAs in PML
8225          * buffer.
8226          */
8227         kvm_for_each_vcpu(i, vcpu, kvm)
8228                 kvm_vcpu_kick(vcpu);
8229 }
8230
8231 static void vmx_dump_sel(char *name, uint32_t sel)
8232 {
8233         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8234                name, vmcs_read16(sel),
8235                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8236                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8237                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8238 }
8239
8240 static void vmx_dump_dtsel(char *name, uint32_t limit)
8241 {
8242         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8243                name, vmcs_read32(limit),
8244                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8245 }
8246
8247 static void dump_vmcs(void)
8248 {
8249         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8250         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8251         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8252         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8253         u32 secondary_exec_control = 0;
8254         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8255         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8256         int i, n;
8257
8258         if (cpu_has_secondary_exec_ctrls())
8259                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8260
8261         pr_err("*** Guest State ***\n");
8262         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8263                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8264                vmcs_readl(CR0_GUEST_HOST_MASK));
8265         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8266                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8267         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8268         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8269             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8270         {
8271                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8272                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8273                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8274                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8275         }
8276         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8277                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8278         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8279                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8280         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8281                vmcs_readl(GUEST_SYSENTER_ESP),
8282                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8283         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8284         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8285         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8286         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8287         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8288         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8289         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8290         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8291         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8292         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8293         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8294             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8295                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8296                        efer, vmcs_read64(GUEST_IA32_PAT));
8297         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8298                vmcs_read64(GUEST_IA32_DEBUGCTL),
8299                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8300         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8301                 pr_err("PerfGlobCtl = 0x%016llx\n",
8302                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8303         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8304                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8305         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8306                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8307                vmcs_read32(GUEST_ACTIVITY_STATE));
8308         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8309                 pr_err("InterruptStatus = %04x\n",
8310                        vmcs_read16(GUEST_INTR_STATUS));
8311
8312         pr_err("*** Host State ***\n");
8313         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8314                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8315         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8316                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8317                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8318                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8319                vmcs_read16(HOST_TR_SELECTOR));
8320         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8321                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8322                vmcs_readl(HOST_TR_BASE));
8323         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8324                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8325         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8326                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8327                vmcs_readl(HOST_CR4));
8328         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8329                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8330                vmcs_read32(HOST_IA32_SYSENTER_CS),
8331                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8332         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8333                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8334                        vmcs_read64(HOST_IA32_EFER),
8335                        vmcs_read64(HOST_IA32_PAT));
8336         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8337                 pr_err("PerfGlobCtl = 0x%016llx\n",
8338                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8339
8340         pr_err("*** Control State ***\n");
8341         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8342                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8343         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8344         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8345                vmcs_read32(EXCEPTION_BITMAP),
8346                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8347                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8348         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8349                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8350                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8351                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8352         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8353                vmcs_read32(VM_EXIT_INTR_INFO),
8354                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8355                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8356         pr_err("        reason=%08x qualification=%016lx\n",
8357                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8358         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8359                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8360                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8361         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8362         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8363                 pr_err("TSC Multiplier = 0x%016llx\n",
8364                        vmcs_read64(TSC_MULTIPLIER));
8365         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8366                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8367         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8368                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8369         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8370                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8371         n = vmcs_read32(CR3_TARGET_COUNT);
8372         for (i = 0; i + 1 < n; i += 4)
8373                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8374                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8375                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8376         if (i < n)
8377                 pr_err("CR3 target%u=%016lx\n",
8378                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8379         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8380                 pr_err("PLE Gap=%08x Window=%08x\n",
8381                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8382         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8383                 pr_err("Virtual processor ID = 0x%04x\n",
8384                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8385 }
8386
8387 /*
8388  * The guest has exited.  See if we can fix it or if we need userspace
8389  * assistance.
8390  */
8391 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8392 {
8393         struct vcpu_vmx *vmx = to_vmx(vcpu);
8394         u32 exit_reason = vmx->exit_reason;
8395         u32 vectoring_info = vmx->idt_vectoring_info;
8396
8397         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8398         vcpu->arch.gpa_available = false;
8399
8400         /*
8401          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8402          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8403          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8404          * mode as if vcpus is in root mode, the PML buffer must has been
8405          * flushed already.
8406          */
8407         if (enable_pml)
8408                 vmx_flush_pml_buffer(vcpu);
8409
8410         /* If guest state is invalid, start emulating */
8411         if (vmx->emulation_required)
8412                 return handle_invalid_guest_state(vcpu);
8413
8414         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8415                 nested_vmx_vmexit(vcpu, exit_reason,
8416                                   vmcs_read32(VM_EXIT_INTR_INFO),
8417                                   vmcs_readl(EXIT_QUALIFICATION));
8418                 return 1;
8419         }
8420
8421         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8422                 dump_vmcs();
8423                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8424                 vcpu->run->fail_entry.hardware_entry_failure_reason
8425                         = exit_reason;
8426                 return 0;
8427         }
8428
8429         if (unlikely(vmx->fail)) {
8430                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8431                 vcpu->run->fail_entry.hardware_entry_failure_reason
8432                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8433                 return 0;
8434         }
8435
8436         /*
8437          * Note:
8438          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8439          * delivery event since it indicates guest is accessing MMIO.
8440          * The vm-exit can be triggered again after return to guest that
8441          * will cause infinite loop.
8442          */
8443         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8444                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8445                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8446                         exit_reason != EXIT_REASON_PML_FULL &&
8447                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8448                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8449                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8450                 vcpu->run->internal.ndata = 2;
8451                 vcpu->run->internal.data[0] = vectoring_info;
8452                 vcpu->run->internal.data[1] = exit_reason;
8453                 return 0;
8454         }
8455
8456         if (exit_reason < kvm_vmx_max_exit_handlers
8457             && kvm_vmx_exit_handlers[exit_reason])
8458                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8459         else {
8460                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8461                                 exit_reason);
8462                 kvm_queue_exception(vcpu, UD_VECTOR);
8463                 return 1;
8464         }
8465 }
8466
8467 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8468 {
8469         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8470
8471         if (is_guest_mode(vcpu) &&
8472                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8473                 return;
8474
8475         if (irr == -1 || tpr < irr) {
8476                 vmcs_write32(TPR_THRESHOLD, 0);
8477                 return;
8478         }
8479
8480         vmcs_write32(TPR_THRESHOLD, irr);
8481 }
8482
8483 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8484 {
8485         u32 sec_exec_control;
8486
8487         /* Postpone execution until vmcs01 is the current VMCS. */
8488         if (is_guest_mode(vcpu)) {
8489                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8490                 return;
8491         }
8492
8493         if (!cpu_has_vmx_virtualize_x2apic_mode())
8494                 return;
8495
8496         if (!cpu_need_tpr_shadow(vcpu))
8497                 return;
8498
8499         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8500
8501         if (set) {
8502                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8503                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8504         } else {
8505                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8506                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8507                 vmx_flush_tlb_ept_only(vcpu);
8508         }
8509         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8510
8511         vmx_set_msr_bitmap(vcpu);
8512 }
8513
8514 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8515 {
8516         struct vcpu_vmx *vmx = to_vmx(vcpu);
8517
8518         /*
8519          * Currently we do not handle the nested case where L2 has an
8520          * APIC access page of its own; that page is still pinned.
8521          * Hence, we skip the case where the VCPU is in guest mode _and_
8522          * L1 prepared an APIC access page for L2.
8523          *
8524          * For the case where L1 and L2 share the same APIC access page
8525          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8526          * in the vmcs12), this function will only update either the vmcs01
8527          * or the vmcs02.  If the former, the vmcs02 will be updated by
8528          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8529          * the next L2->L1 exit.
8530          */
8531         if (!is_guest_mode(vcpu) ||
8532             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8533                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8534                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8535                 vmx_flush_tlb_ept_only(vcpu);
8536         }
8537 }
8538
8539 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8540 {
8541         u16 status;
8542         u8 old;
8543
8544         if (max_isr == -1)
8545                 max_isr = 0;
8546
8547         status = vmcs_read16(GUEST_INTR_STATUS);
8548         old = status >> 8;
8549         if (max_isr != old) {
8550                 status &= 0xff;
8551                 status |= max_isr << 8;
8552                 vmcs_write16(GUEST_INTR_STATUS, status);
8553         }
8554 }
8555
8556 static void vmx_set_rvi(int vector)
8557 {
8558         u16 status;
8559         u8 old;
8560
8561         if (vector == -1)
8562                 vector = 0;
8563
8564         status = vmcs_read16(GUEST_INTR_STATUS);
8565         old = (u8)status & 0xff;
8566         if ((u8)vector != old) {
8567                 status &= ~0xff;
8568                 status |= (u8)vector;
8569                 vmcs_write16(GUEST_INTR_STATUS, status);
8570         }
8571 }
8572
8573 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8574 {
8575         if (!is_guest_mode(vcpu)) {
8576                 vmx_set_rvi(max_irr);
8577                 return;
8578         }
8579
8580         if (max_irr == -1)
8581                 return;
8582
8583         /*
8584          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8585          * handles it.
8586          */
8587         if (nested_exit_on_intr(vcpu))
8588                 return;
8589
8590         /*
8591          * Else, fall back to pre-APICv interrupt injection since L2
8592          * is run without virtual interrupt delivery.
8593          */
8594         if (!kvm_event_needs_reinjection(vcpu) &&
8595             vmx_interrupt_allowed(vcpu)) {
8596                 kvm_queue_interrupt(vcpu, max_irr, false);
8597                 vmx_inject_irq(vcpu);
8598         }
8599 }
8600
8601 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8602 {
8603         struct vcpu_vmx *vmx = to_vmx(vcpu);
8604         int max_irr;
8605
8606         WARN_ON(!vcpu->arch.apicv_active);
8607         if (pi_test_on(&vmx->pi_desc)) {
8608                 pi_clear_on(&vmx->pi_desc);
8609                 /*
8610                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8611                  * But on x86 this is just a compiler barrier anyway.
8612                  */
8613                 smp_mb__after_atomic();
8614                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8615         } else {
8616                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8617         }
8618         vmx_hwapic_irr_update(vcpu, max_irr);
8619         return max_irr;
8620 }
8621
8622 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8623 {
8624         if (!kvm_vcpu_apicv_active(vcpu))
8625                 return;
8626
8627         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8628         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8629         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8630         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8631 }
8632
8633 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8634 {
8635         struct vcpu_vmx *vmx = to_vmx(vcpu);
8636
8637         pi_clear_on(&vmx->pi_desc);
8638         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8639 }
8640
8641 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8642 {
8643         u32 exit_intr_info;
8644
8645         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8646               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8647                 return;
8648
8649         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8650         exit_intr_info = vmx->exit_intr_info;
8651
8652         /* Handle machine checks before interrupts are enabled */
8653         if (is_machine_check(exit_intr_info))
8654                 kvm_machine_check();
8655
8656         /* We need to handle NMIs before interrupts are enabled */
8657         if (is_nmi(exit_intr_info)) {
8658                 kvm_before_handle_nmi(&vmx->vcpu);
8659                 asm("int $2");
8660                 kvm_after_handle_nmi(&vmx->vcpu);
8661         }
8662 }
8663
8664 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8665 {
8666         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8667         register void *__sp asm(_ASM_SP);
8668
8669         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8670                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8671                 unsigned int vector;
8672                 unsigned long entry;
8673                 gate_desc *desc;
8674                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8675 #ifdef CONFIG_X86_64
8676                 unsigned long tmp;
8677 #endif
8678
8679                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8680                 desc = (gate_desc *)vmx->host_idt_base + vector;
8681                 entry = gate_offset(*desc);
8682                 asm volatile(
8683 #ifdef CONFIG_X86_64
8684                         "mov %%" _ASM_SP ", %[sp]\n\t"
8685                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8686                         "push $%c[ss]\n\t"
8687                         "push %[sp]\n\t"
8688 #endif
8689                         "pushf\n\t"
8690                         __ASM_SIZE(push) " $%c[cs]\n\t"
8691                         "call *%[entry]\n\t"
8692                         :
8693 #ifdef CONFIG_X86_64
8694                         [sp]"=&r"(tmp),
8695 #endif
8696                         "+r"(__sp)
8697                         :
8698                         [entry]"r"(entry),
8699                         [ss]"i"(__KERNEL_DS),
8700                         [cs]"i"(__KERNEL_CS)
8701                         );
8702         }
8703 }
8704
8705 static bool vmx_has_high_real_mode_segbase(void)
8706 {
8707         return enable_unrestricted_guest || emulate_invalid_guest_state;
8708 }
8709
8710 static bool vmx_mpx_supported(void)
8711 {
8712         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8713                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8714 }
8715
8716 static bool vmx_xsaves_supported(void)
8717 {
8718         return vmcs_config.cpu_based_2nd_exec_ctrl &
8719                 SECONDARY_EXEC_XSAVES;
8720 }
8721
8722 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8723 {
8724         u32 exit_intr_info;
8725         bool unblock_nmi;
8726         u8 vector;
8727         bool idtv_info_valid;
8728
8729         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8730
8731         if (vmx->nmi_known_unmasked)
8732                 return;
8733         /*
8734          * Can't use vmx->exit_intr_info since we're not sure what
8735          * the exit reason is.
8736          */
8737         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8738         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8739         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8740         /*
8741          * SDM 3: 27.7.1.2 (September 2008)
8742          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8743          * a guest IRET fault.
8744          * SDM 3: 23.2.2 (September 2008)
8745          * Bit 12 is undefined in any of the following cases:
8746          *  If the VM exit sets the valid bit in the IDT-vectoring
8747          *   information field.
8748          *  If the VM exit is due to a double fault.
8749          */
8750         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8751             vector != DF_VECTOR && !idtv_info_valid)
8752                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8753                               GUEST_INTR_STATE_NMI);
8754         else
8755                 vmx->nmi_known_unmasked =
8756                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8757                           & GUEST_INTR_STATE_NMI);
8758 }
8759
8760 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8761                                       u32 idt_vectoring_info,
8762                                       int instr_len_field,
8763                                       int error_code_field)
8764 {
8765         u8 vector;
8766         int type;
8767         bool idtv_info_valid;
8768
8769         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8770
8771         vcpu->arch.nmi_injected = false;
8772         kvm_clear_exception_queue(vcpu);
8773         kvm_clear_interrupt_queue(vcpu);
8774
8775         if (!idtv_info_valid)
8776                 return;
8777
8778         kvm_make_request(KVM_REQ_EVENT, vcpu);
8779
8780         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8781         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8782
8783         switch (type) {
8784         case INTR_TYPE_NMI_INTR:
8785                 vcpu->arch.nmi_injected = true;
8786                 /*
8787                  * SDM 3: 27.7.1.2 (September 2008)
8788                  * Clear bit "block by NMI" before VM entry if a NMI
8789                  * delivery faulted.
8790                  */
8791                 vmx_set_nmi_mask(vcpu, false);
8792                 break;
8793         case INTR_TYPE_SOFT_EXCEPTION:
8794                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8795                 /* fall through */
8796         case INTR_TYPE_HARD_EXCEPTION:
8797                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8798                         u32 err = vmcs_read32(error_code_field);
8799                         kvm_requeue_exception_e(vcpu, vector, err);
8800                 } else
8801                         kvm_requeue_exception(vcpu, vector);
8802                 break;
8803         case INTR_TYPE_SOFT_INTR:
8804                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8805                 /* fall through */
8806         case INTR_TYPE_EXT_INTR:
8807                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8808                 break;
8809         default:
8810                 break;
8811         }
8812 }
8813
8814 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8815 {
8816         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8817                                   VM_EXIT_INSTRUCTION_LEN,
8818                                   IDT_VECTORING_ERROR_CODE);
8819 }
8820
8821 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8822 {
8823         __vmx_complete_interrupts(vcpu,
8824                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8825                                   VM_ENTRY_INSTRUCTION_LEN,
8826                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8827
8828         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8829 }
8830
8831 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8832 {
8833         int i, nr_msrs;
8834         struct perf_guest_switch_msr *msrs;
8835
8836         msrs = perf_guest_get_msrs(&nr_msrs);
8837
8838         if (!msrs)
8839                 return;
8840
8841         for (i = 0; i < nr_msrs; i++)
8842                 if (msrs[i].host == msrs[i].guest)
8843                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8844                 else
8845                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8846                                         msrs[i].host);
8847 }
8848
8849 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8850 {
8851         struct vcpu_vmx *vmx = to_vmx(vcpu);
8852         u64 tscl;
8853         u32 delta_tsc;
8854
8855         if (vmx->hv_deadline_tsc == -1)
8856                 return;
8857
8858         tscl = rdtsc();
8859         if (vmx->hv_deadline_tsc > tscl)
8860                 /* sure to be 32 bit only because checked on set_hv_timer */
8861                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8862                         cpu_preemption_timer_multi);
8863         else
8864                 delta_tsc = 0;
8865
8866         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8867 }
8868
8869 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8870 {
8871         struct vcpu_vmx *vmx = to_vmx(vcpu);
8872         unsigned long debugctlmsr, cr4;
8873
8874         /* Don't enter VMX if guest state is invalid, let the exit handler
8875            start emulation until we arrive back to a valid state */
8876         if (vmx->emulation_required)
8877                 return;
8878
8879         if (vmx->ple_window_dirty) {
8880                 vmx->ple_window_dirty = false;
8881                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8882         }
8883
8884         if (vmx->nested.sync_shadow_vmcs) {
8885                 copy_vmcs12_to_shadow(vmx);
8886                 vmx->nested.sync_shadow_vmcs = false;
8887         }
8888
8889         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8890                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8891         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8892                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8893
8894         cr4 = cr4_read_shadow();
8895         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8896                 vmcs_writel(HOST_CR4, cr4);
8897                 vmx->host_state.vmcs_host_cr4 = cr4;
8898         }
8899
8900         /* When single-stepping over STI and MOV SS, we must clear the
8901          * corresponding interruptibility bits in the guest state. Otherwise
8902          * vmentry fails as it then expects bit 14 (BS) in pending debug
8903          * exceptions being set, but that's not correct for the guest debugging
8904          * case. */
8905         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8906                 vmx_set_interrupt_shadow(vcpu, 0);
8907
8908         if (vmx->guest_pkru_valid)
8909                 __write_pkru(vmx->guest_pkru);
8910
8911         atomic_switch_perf_msrs(vmx);
8912         debugctlmsr = get_debugctlmsr();
8913
8914         vmx_arm_hv_timer(vcpu);
8915
8916         vmx->__launched = vmx->loaded_vmcs->launched;
8917         asm(
8918                 /* Store host registers */
8919                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8920                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8921                 "push %%" _ASM_CX " \n\t"
8922                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8923                 "je 1f \n\t"
8924                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8925                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8926                 "1: \n\t"
8927                 /* Reload cr2 if changed */
8928                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8929                 "mov %%cr2, %%" _ASM_DX " \n\t"
8930                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8931                 "je 2f \n\t"
8932                 "mov %%" _ASM_AX", %%cr2 \n\t"
8933                 "2: \n\t"
8934                 /* Check if vmlaunch of vmresume is needed */
8935                 "cmpl $0, %c[launched](%0) \n\t"
8936                 /* Load guest registers.  Don't clobber flags. */
8937                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8938                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8939                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8940                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8941                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8942                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8943 #ifdef CONFIG_X86_64
8944                 "mov %c[r8](%0),  %%r8  \n\t"
8945                 "mov %c[r9](%0),  %%r9  \n\t"
8946                 "mov %c[r10](%0), %%r10 \n\t"
8947                 "mov %c[r11](%0), %%r11 \n\t"
8948                 "mov %c[r12](%0), %%r12 \n\t"
8949                 "mov %c[r13](%0), %%r13 \n\t"
8950                 "mov %c[r14](%0), %%r14 \n\t"
8951                 "mov %c[r15](%0), %%r15 \n\t"
8952 #endif
8953                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8954
8955                 /* Enter guest mode */
8956                 "jne 1f \n\t"
8957                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8958                 "jmp 2f \n\t"
8959                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8960                 "2: "
8961                 /* Save guest registers, load host registers, keep flags */
8962                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8963                 "pop %0 \n\t"
8964                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8965                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8966                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8967                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8968                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8969                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8970                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8971 #ifdef CONFIG_X86_64
8972                 "mov %%r8,  %c[r8](%0) \n\t"
8973                 "mov %%r9,  %c[r9](%0) \n\t"
8974                 "mov %%r10, %c[r10](%0) \n\t"
8975                 "mov %%r11, %c[r11](%0) \n\t"
8976                 "mov %%r12, %c[r12](%0) \n\t"
8977                 "mov %%r13, %c[r13](%0) \n\t"
8978                 "mov %%r14, %c[r14](%0) \n\t"
8979                 "mov %%r15, %c[r15](%0) \n\t"
8980 #endif
8981                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8982                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8983
8984                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8985                 "setbe %c[fail](%0) \n\t"
8986                 ".pushsection .rodata \n\t"
8987                 ".global vmx_return \n\t"
8988                 "vmx_return: " _ASM_PTR " 2b \n\t"
8989                 ".popsection"
8990               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8991                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8992                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8993                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8994                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8995                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8996                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8997                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8998                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8999                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9000                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9001 #ifdef CONFIG_X86_64
9002                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9003                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9004                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9005                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9006                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9007                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9008                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9009                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9010 #endif
9011                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9012                 [wordsize]"i"(sizeof(ulong))
9013               : "cc", "memory"
9014 #ifdef CONFIG_X86_64
9015                 , "rax", "rbx", "rdi", "rsi"
9016                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9017 #else
9018                 , "eax", "ebx", "edi", "esi"
9019 #endif
9020               );
9021
9022         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9023         if (debugctlmsr)
9024                 update_debugctlmsr(debugctlmsr);
9025
9026 #ifndef CONFIG_X86_64
9027         /*
9028          * The sysexit path does not restore ds/es, so we must set them to
9029          * a reasonable value ourselves.
9030          *
9031          * We can't defer this to vmx_load_host_state() since that function
9032          * may be executed in interrupt context, which saves and restore segments
9033          * around it, nullifying its effect.
9034          */
9035         loadsegment(ds, __USER_DS);
9036         loadsegment(es, __USER_DS);
9037 #endif
9038
9039         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9040                                   | (1 << VCPU_EXREG_RFLAGS)
9041                                   | (1 << VCPU_EXREG_PDPTR)
9042                                   | (1 << VCPU_EXREG_SEGMENTS)
9043                                   | (1 << VCPU_EXREG_CR3));
9044         vcpu->arch.regs_dirty = 0;
9045
9046         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9047
9048         vmx->loaded_vmcs->launched = 1;
9049
9050         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9051
9052         /*
9053          * eager fpu is enabled if PKEY is supported and CR4 is switched
9054          * back on host, so it is safe to read guest PKRU from current
9055          * XSAVE.
9056          */
9057         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9058                 vmx->guest_pkru = __read_pkru();
9059                 if (vmx->guest_pkru != vmx->host_pkru) {
9060                         vmx->guest_pkru_valid = true;
9061                         __write_pkru(vmx->host_pkru);
9062                 } else
9063                         vmx->guest_pkru_valid = false;
9064         }
9065
9066         /*
9067          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9068          * we did not inject a still-pending event to L1 now because of
9069          * nested_run_pending, we need to re-enable this bit.
9070          */
9071         if (vmx->nested.nested_run_pending)
9072                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9073
9074         vmx->nested.nested_run_pending = 0;
9075
9076         vmx_complete_atomic_exit(vmx);
9077         vmx_recover_nmi_blocking(vmx);
9078         vmx_complete_interrupts(vmx);
9079 }
9080
9081 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9082 {
9083         struct vcpu_vmx *vmx = to_vmx(vcpu);
9084         int cpu;
9085
9086         if (vmx->loaded_vmcs == vmcs)
9087                 return;
9088
9089         cpu = get_cpu();
9090         vmx->loaded_vmcs = vmcs;
9091         vmx_vcpu_put(vcpu);
9092         vmx_vcpu_load(vcpu, cpu);
9093         vcpu->cpu = cpu;
9094         put_cpu();
9095 }
9096
9097 /*
9098  * Ensure that the current vmcs of the logical processor is the
9099  * vmcs01 of the vcpu before calling free_nested().
9100  */
9101 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9102 {
9103        struct vcpu_vmx *vmx = to_vmx(vcpu);
9104        int r;
9105
9106        r = vcpu_load(vcpu);
9107        BUG_ON(r);
9108        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9109        free_nested(vmx);
9110        vcpu_put(vcpu);
9111 }
9112
9113 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9114 {
9115         struct vcpu_vmx *vmx = to_vmx(vcpu);
9116
9117         if (enable_pml)
9118                 vmx_destroy_pml_buffer(vmx);
9119         free_vpid(vmx->vpid);
9120         leave_guest_mode(vcpu);
9121         vmx_free_vcpu_nested(vcpu);
9122         free_loaded_vmcs(vmx->loaded_vmcs);
9123         kfree(vmx->guest_msrs);
9124         kvm_vcpu_uninit(vcpu);
9125         kmem_cache_free(kvm_vcpu_cache, vmx);
9126 }
9127
9128 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9129 {
9130         int err;
9131         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9132         int cpu;
9133
9134         if (!vmx)
9135                 return ERR_PTR(-ENOMEM);
9136
9137         vmx->vpid = allocate_vpid();
9138
9139         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9140         if (err)
9141                 goto free_vcpu;
9142
9143         err = -ENOMEM;
9144
9145         /*
9146          * If PML is turned on, failure on enabling PML just results in failure
9147          * of creating the vcpu, therefore we can simplify PML logic (by
9148          * avoiding dealing with cases, such as enabling PML partially on vcpus
9149          * for the guest, etc.
9150          */
9151         if (enable_pml) {
9152                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9153                 if (!vmx->pml_pg)
9154                         goto uninit_vcpu;
9155         }
9156
9157         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9158         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9159                      > PAGE_SIZE);
9160
9161         if (!vmx->guest_msrs)
9162                 goto free_pml;
9163
9164         vmx->loaded_vmcs = &vmx->vmcs01;
9165         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9166         vmx->loaded_vmcs->shadow_vmcs = NULL;
9167         if (!vmx->loaded_vmcs->vmcs)
9168                 goto free_msrs;
9169         if (!vmm_exclusive)
9170                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9171         loaded_vmcs_init(vmx->loaded_vmcs);
9172         if (!vmm_exclusive)
9173                 kvm_cpu_vmxoff();
9174
9175         cpu = get_cpu();
9176         vmx_vcpu_load(&vmx->vcpu, cpu);
9177         vmx->vcpu.cpu = cpu;
9178         err = vmx_vcpu_setup(vmx);
9179         vmx_vcpu_put(&vmx->vcpu);
9180         put_cpu();
9181         if (err)
9182                 goto free_vmcs;
9183         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9184                 err = alloc_apic_access_page(kvm);
9185                 if (err)
9186                         goto free_vmcs;
9187         }
9188
9189         if (enable_ept) {
9190                 if (!kvm->arch.ept_identity_map_addr)
9191                         kvm->arch.ept_identity_map_addr =
9192                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9193                 err = init_rmode_identity_map(kvm);
9194                 if (err)
9195                         goto free_vmcs;
9196         }
9197
9198         if (nested) {
9199                 nested_vmx_setup_ctls_msrs(vmx);
9200                 vmx->nested.vpid02 = allocate_vpid();
9201         }
9202
9203         vmx->nested.posted_intr_nv = -1;
9204         vmx->nested.current_vmptr = -1ull;
9205         vmx->nested.current_vmcs12 = NULL;
9206
9207         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9208
9209         return &vmx->vcpu;
9210
9211 free_vmcs:
9212         free_vpid(vmx->nested.vpid02);
9213         free_loaded_vmcs(vmx->loaded_vmcs);
9214 free_msrs:
9215         kfree(vmx->guest_msrs);
9216 free_pml:
9217         vmx_destroy_pml_buffer(vmx);
9218 uninit_vcpu:
9219         kvm_vcpu_uninit(&vmx->vcpu);
9220 free_vcpu:
9221         free_vpid(vmx->vpid);
9222         kmem_cache_free(kvm_vcpu_cache, vmx);
9223         return ERR_PTR(err);
9224 }
9225
9226 static void __init vmx_check_processor_compat(void *rtn)
9227 {
9228         struct vmcs_config vmcs_conf;
9229
9230         *(int *)rtn = 0;
9231         if (setup_vmcs_config(&vmcs_conf) < 0)
9232                 *(int *)rtn = -EIO;
9233         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9234                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9235                                 smp_processor_id());
9236                 *(int *)rtn = -EIO;
9237         }
9238 }
9239
9240 static int get_ept_level(void)
9241 {
9242         return VMX_EPT_DEFAULT_GAW + 1;
9243 }
9244
9245 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9246 {
9247         u8 cache;
9248         u64 ipat = 0;
9249
9250         /* For VT-d and EPT combination
9251          * 1. MMIO: always map as UC
9252          * 2. EPT with VT-d:
9253          *   a. VT-d without snooping control feature: can't guarantee the
9254          *      result, try to trust guest.
9255          *   b. VT-d with snooping control feature: snooping control feature of
9256          *      VT-d engine can guarantee the cache correctness. Just set it
9257          *      to WB to keep consistent with host. So the same as item 3.
9258          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9259          *    consistent with host MTRR
9260          */
9261         if (is_mmio) {
9262                 cache = MTRR_TYPE_UNCACHABLE;
9263                 goto exit;
9264         }
9265
9266         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9267                 ipat = VMX_EPT_IPAT_BIT;
9268                 cache = MTRR_TYPE_WRBACK;
9269                 goto exit;
9270         }
9271
9272         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9273                 ipat = VMX_EPT_IPAT_BIT;
9274                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9275                         cache = MTRR_TYPE_WRBACK;
9276                 else
9277                         cache = MTRR_TYPE_UNCACHABLE;
9278                 goto exit;
9279         }
9280
9281         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9282
9283 exit:
9284         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9285 }
9286
9287 static int vmx_get_lpage_level(void)
9288 {
9289         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9290                 return PT_DIRECTORY_LEVEL;
9291         else
9292                 /* For shadow and EPT supported 1GB page */
9293                 return PT_PDPE_LEVEL;
9294 }
9295
9296 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9297 {
9298         /*
9299          * These bits in the secondary execution controls field
9300          * are dynamic, the others are mostly based on the hypervisor
9301          * architecture and the guest's CPUID.  Do not touch the
9302          * dynamic bits.
9303          */
9304         u32 mask =
9305                 SECONDARY_EXEC_SHADOW_VMCS |
9306                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9307                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9308
9309         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9310
9311         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9312                      (new_ctl & ~mask) | (cur_ctl & mask));
9313 }
9314
9315 /*
9316  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9317  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9318  */
9319 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9320 {
9321         struct vcpu_vmx *vmx = to_vmx(vcpu);
9322         struct kvm_cpuid_entry2 *entry;
9323
9324         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9325         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9326
9327 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9328         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9329                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9330 } while (0)
9331
9332         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9333         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9334         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9335         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9336         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9337         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9338         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9339         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9340         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9341         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9342         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9343         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9344         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9345         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9346         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9347
9348         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9349         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9350         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9351         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9352         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9353         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9354         cr4_fixed1_update(bit(11),            ecx, bit(2));
9355
9356 #undef cr4_fixed1_update
9357 }
9358
9359 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9360 {
9361         struct kvm_cpuid_entry2 *best;
9362         struct vcpu_vmx *vmx = to_vmx(vcpu);
9363         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9364
9365         if (vmx_rdtscp_supported()) {
9366                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9367                 if (!rdtscp_enabled)
9368                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9369
9370                 if (nested) {
9371                         if (rdtscp_enabled)
9372                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9373                                         SECONDARY_EXEC_RDTSCP;
9374                         else
9375                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9376                                         ~SECONDARY_EXEC_RDTSCP;
9377                 }
9378         }
9379
9380         /* Exposing INVPCID only when PCID is exposed */
9381         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9382         if (vmx_invpcid_supported() &&
9383             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9384             !guest_cpuid_has_pcid(vcpu))) {
9385                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9386
9387                 if (best)
9388                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9389         }
9390
9391         if (cpu_has_secondary_exec_ctrls())
9392                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9393
9394         if (nested_vmx_allowed(vcpu))
9395                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9396                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9397         else
9398                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9399                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9400
9401         if (nested_vmx_allowed(vcpu))
9402                 nested_vmx_cr_fixed1_bits_update(vcpu);
9403 }
9404
9405 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9406 {
9407         if (func == 1 && nested)
9408                 entry->ecx |= bit(X86_FEATURE_VMX);
9409 }
9410
9411 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9412                 struct x86_exception *fault)
9413 {
9414         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9415         u32 exit_reason;
9416
9417         if (fault->error_code & PFERR_RSVD_MASK)
9418                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9419         else
9420                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9421         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9422         vmcs12->guest_physical_address = fault->address;
9423 }
9424
9425 /* Callbacks for nested_ept_init_mmu_context: */
9426
9427 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9428 {
9429         /* return the page table to be shadowed - in our case, EPT12 */
9430         return get_vmcs12(vcpu)->ept_pointer;
9431 }
9432
9433 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9434 {
9435         WARN_ON(mmu_is_nested(vcpu));
9436         kvm_init_shadow_ept_mmu(vcpu,
9437                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9438                         VMX_EPT_EXECUTE_ONLY_BIT);
9439         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9440         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9441         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9442
9443         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9444 }
9445
9446 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9447 {
9448         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9449 }
9450
9451 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9452                                             u16 error_code)
9453 {
9454         bool inequality, bit;
9455
9456         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9457         inequality =
9458                 (error_code & vmcs12->page_fault_error_code_mask) !=
9459                  vmcs12->page_fault_error_code_match;
9460         return inequality ^ bit;
9461 }
9462
9463 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9464                 struct x86_exception *fault)
9465 {
9466         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9467
9468         WARN_ON(!is_guest_mode(vcpu));
9469
9470         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9471                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9472                                   vmcs_read32(VM_EXIT_INTR_INFO),
9473                                   vmcs_readl(EXIT_QUALIFICATION));
9474         else
9475                 kvm_inject_page_fault(vcpu, fault);
9476 }
9477
9478 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9479                                                struct vmcs12 *vmcs12);
9480
9481 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9482                                         struct vmcs12 *vmcs12)
9483 {
9484         struct vcpu_vmx *vmx = to_vmx(vcpu);
9485         u64 hpa;
9486
9487         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9488                 /*
9489                  * Translate L1 physical address to host physical
9490                  * address for vmcs02. Keep the page pinned, so this
9491                  * physical address remains valid. We keep a reference
9492                  * to it so we can release it later.
9493                  */
9494                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9495                         nested_release_page(vmx->nested.apic_access_page);
9496                 vmx->nested.apic_access_page =
9497                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9498                 /*
9499                  * If translation failed, no matter: This feature asks
9500                  * to exit when accessing the given address, and if it
9501                  * can never be accessed, this feature won't do
9502                  * anything anyway.
9503                  */
9504                 if (vmx->nested.apic_access_page) {
9505                         hpa = page_to_phys(vmx->nested.apic_access_page);
9506                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9507                 } else {
9508                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9509                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9510                 }
9511         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9512                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9513                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9514                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9515                 kvm_vcpu_reload_apic_access_page(vcpu);
9516         }
9517
9518         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9519                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9520                         nested_release_page(vmx->nested.virtual_apic_page);
9521                 vmx->nested.virtual_apic_page =
9522                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9523
9524                 /*
9525                  * If translation failed, VM entry will fail because
9526                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9527                  * Failing the vm entry is _not_ what the processor
9528                  * does but it's basically the only possibility we
9529                  * have.  We could still enter the guest if CR8 load
9530                  * exits are enabled, CR8 store exits are enabled, and
9531                  * virtualize APIC access is disabled; in this case
9532                  * the processor would never use the TPR shadow and we
9533                  * could simply clear the bit from the execution
9534                  * control.  But such a configuration is useless, so
9535                  * let's keep the code simple.
9536                  */
9537                 if (vmx->nested.virtual_apic_page) {
9538                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9539                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9540                 }
9541         }
9542
9543         if (nested_cpu_has_posted_intr(vmcs12)) {
9544                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9545                         kunmap(vmx->nested.pi_desc_page);
9546                         nested_release_page(vmx->nested.pi_desc_page);
9547                 }
9548                 vmx->nested.pi_desc_page =
9549                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9550                 vmx->nested.pi_desc =
9551                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9552                 if (!vmx->nested.pi_desc) {
9553                         nested_release_page_clean(vmx->nested.pi_desc_page);
9554                         return;
9555                 }
9556                 vmx->nested.pi_desc =
9557                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9558                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9559                         (PAGE_SIZE - 1)));
9560                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9561                         page_to_phys(vmx->nested.pi_desc_page) +
9562                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9563                         (PAGE_SIZE - 1)));
9564         }
9565         if (cpu_has_vmx_msr_bitmap() &&
9566             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9567             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9568                 ;
9569         else
9570                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9571                                 CPU_BASED_USE_MSR_BITMAPS);
9572 }
9573
9574 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9575 {
9576         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9577         struct vcpu_vmx *vmx = to_vmx(vcpu);
9578
9579         if (vcpu->arch.virtual_tsc_khz == 0)
9580                 return;
9581
9582         /* Make sure short timeouts reliably trigger an immediate vmexit.
9583          * hrtimer_start does not guarantee this. */
9584         if (preemption_timeout <= 1) {
9585                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9586                 return;
9587         }
9588
9589         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9590         preemption_timeout *= 1000000;
9591         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9592         hrtimer_start(&vmx->nested.preemption_timer,
9593                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9594 }
9595
9596 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9597                                                 struct vmcs12 *vmcs12)
9598 {
9599         int maxphyaddr;
9600         u64 addr;
9601
9602         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9603                 return 0;
9604
9605         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9606                 WARN_ON(1);
9607                 return -EINVAL;
9608         }
9609         maxphyaddr = cpuid_maxphyaddr(vcpu);
9610
9611         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9612            ((addr + PAGE_SIZE) >> maxphyaddr))
9613                 return -EINVAL;
9614
9615         return 0;
9616 }
9617
9618 /*
9619  * Merge L0's and L1's MSR bitmap, return false to indicate that
9620  * we do not use the hardware.
9621  */
9622 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9623                                                struct vmcs12 *vmcs12)
9624 {
9625         int msr;
9626         struct page *page;
9627         unsigned long *msr_bitmap_l1;
9628         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9629
9630         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9631         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9632                 return false;
9633
9634         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9635         if (!page)
9636                 return false;
9637         msr_bitmap_l1 = (unsigned long *)kmap(page);
9638
9639         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9640
9641         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9642                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9643                         for (msr = 0x800; msr <= 0x8ff; msr++)
9644                                 nested_vmx_disable_intercept_for_msr(
9645                                         msr_bitmap_l1, msr_bitmap_l0,
9646                                         msr, MSR_TYPE_R);
9647
9648                 nested_vmx_disable_intercept_for_msr(
9649                                 msr_bitmap_l1, msr_bitmap_l0,
9650                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9651                                 MSR_TYPE_R | MSR_TYPE_W);
9652
9653                 if (nested_cpu_has_vid(vmcs12)) {
9654                         nested_vmx_disable_intercept_for_msr(
9655                                 msr_bitmap_l1, msr_bitmap_l0,
9656                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9657                                 MSR_TYPE_W);
9658                         nested_vmx_disable_intercept_for_msr(
9659                                 msr_bitmap_l1, msr_bitmap_l0,
9660                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9661                                 MSR_TYPE_W);
9662                 }
9663         }
9664         kunmap(page);
9665         nested_release_page_clean(page);
9666
9667         return true;
9668 }
9669
9670 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9671                                            struct vmcs12 *vmcs12)
9672 {
9673         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9674             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9675             !nested_cpu_has_vid(vmcs12) &&
9676             !nested_cpu_has_posted_intr(vmcs12))
9677                 return 0;
9678
9679         /*
9680          * If virtualize x2apic mode is enabled,
9681          * virtualize apic access must be disabled.
9682          */
9683         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9684             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9685                 return -EINVAL;
9686
9687         /*
9688          * If virtual interrupt delivery is enabled,
9689          * we must exit on external interrupts.
9690          */
9691         if (nested_cpu_has_vid(vmcs12) &&
9692            !nested_exit_on_intr(vcpu))
9693                 return -EINVAL;
9694
9695         /*
9696          * bits 15:8 should be zero in posted_intr_nv,
9697          * the descriptor address has been already checked
9698          * in nested_get_vmcs12_pages.
9699          */
9700         if (nested_cpu_has_posted_intr(vmcs12) &&
9701            (!nested_cpu_has_vid(vmcs12) ||
9702             !nested_exit_intr_ack_set(vcpu) ||
9703             vmcs12->posted_intr_nv & 0xff00))
9704                 return -EINVAL;
9705
9706         /* tpr shadow is needed by all apicv features. */
9707         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9708                 return -EINVAL;
9709
9710         return 0;
9711 }
9712
9713 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9714                                        unsigned long count_field,
9715                                        unsigned long addr_field)
9716 {
9717         int maxphyaddr;
9718         u64 count, addr;
9719
9720         if (vmcs12_read_any(vcpu, count_field, &count) ||
9721             vmcs12_read_any(vcpu, addr_field, &addr)) {
9722                 WARN_ON(1);
9723                 return -EINVAL;
9724         }
9725         if (count == 0)
9726                 return 0;
9727         maxphyaddr = cpuid_maxphyaddr(vcpu);
9728         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9729             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9730                 pr_debug_ratelimited(
9731                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9732                         addr_field, maxphyaddr, count, addr);
9733                 return -EINVAL;
9734         }
9735         return 0;
9736 }
9737
9738 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9739                                                 struct vmcs12 *vmcs12)
9740 {
9741         if (vmcs12->vm_exit_msr_load_count == 0 &&
9742             vmcs12->vm_exit_msr_store_count == 0 &&
9743             vmcs12->vm_entry_msr_load_count == 0)
9744                 return 0; /* Fast path */
9745         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9746                                         VM_EXIT_MSR_LOAD_ADDR) ||
9747             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9748                                         VM_EXIT_MSR_STORE_ADDR) ||
9749             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9750                                         VM_ENTRY_MSR_LOAD_ADDR))
9751                 return -EINVAL;
9752         return 0;
9753 }
9754
9755 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9756                                        struct vmx_msr_entry *e)
9757 {
9758         /* x2APIC MSR accesses are not allowed */
9759         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9760                 return -EINVAL;
9761         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9762             e->index == MSR_IA32_UCODE_REV)
9763                 return -EINVAL;
9764         if (e->reserved != 0)
9765                 return -EINVAL;
9766         return 0;
9767 }
9768
9769 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9770                                      struct vmx_msr_entry *e)
9771 {
9772         if (e->index == MSR_FS_BASE ||
9773             e->index == MSR_GS_BASE ||
9774             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9775             nested_vmx_msr_check_common(vcpu, e))
9776                 return -EINVAL;
9777         return 0;
9778 }
9779
9780 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9781                                       struct vmx_msr_entry *e)
9782 {
9783         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9784             nested_vmx_msr_check_common(vcpu, e))
9785                 return -EINVAL;
9786         return 0;
9787 }
9788
9789 /*
9790  * Load guest's/host's msr at nested entry/exit.
9791  * return 0 for success, entry index for failure.
9792  */
9793 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9794 {
9795         u32 i;
9796         struct vmx_msr_entry e;
9797         struct msr_data msr;
9798
9799         msr.host_initiated = false;
9800         for (i = 0; i < count; i++) {
9801                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9802                                         &e, sizeof(e))) {
9803                         pr_debug_ratelimited(
9804                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9805                                 __func__, i, gpa + i * sizeof(e));
9806                         goto fail;
9807                 }
9808                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9809                         pr_debug_ratelimited(
9810                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9811                                 __func__, i, e.index, e.reserved);
9812                         goto fail;
9813                 }
9814                 msr.index = e.index;
9815                 msr.data = e.value;
9816                 if (kvm_set_msr(vcpu, &msr)) {
9817                         pr_debug_ratelimited(
9818                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9819                                 __func__, i, e.index, e.value);
9820                         goto fail;
9821                 }
9822         }
9823         return 0;
9824 fail:
9825         return i + 1;
9826 }
9827
9828 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9829 {
9830         u32 i;
9831         struct vmx_msr_entry e;
9832
9833         for (i = 0; i < count; i++) {
9834                 struct msr_data msr_info;
9835                 if (kvm_vcpu_read_guest(vcpu,
9836                                         gpa + i * sizeof(e),
9837                                         &e, 2 * sizeof(u32))) {
9838                         pr_debug_ratelimited(
9839                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9840                                 __func__, i, gpa + i * sizeof(e));
9841                         return -EINVAL;
9842                 }
9843                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9844                         pr_debug_ratelimited(
9845                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9846                                 __func__, i, e.index, e.reserved);
9847                         return -EINVAL;
9848                 }
9849                 msr_info.host_initiated = false;
9850                 msr_info.index = e.index;
9851                 if (kvm_get_msr(vcpu, &msr_info)) {
9852                         pr_debug_ratelimited(
9853                                 "%s cannot read MSR (%u, 0x%x)\n",
9854                                 __func__, i, e.index);
9855                         return -EINVAL;
9856                 }
9857                 if (kvm_vcpu_write_guest(vcpu,
9858                                          gpa + i * sizeof(e) +
9859                                              offsetof(struct vmx_msr_entry, value),
9860                                          &msr_info.data, sizeof(msr_info.data))) {
9861                         pr_debug_ratelimited(
9862                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9863                                 __func__, i, e.index, msr_info.data);
9864                         return -EINVAL;
9865                 }
9866         }
9867         return 0;
9868 }
9869
9870 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9871 {
9872         unsigned long invalid_mask;
9873
9874         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9875         return (val & invalid_mask) == 0;
9876 }
9877
9878 /*
9879  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9880  * emulating VM entry into a guest with EPT enabled.
9881  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9882  * is assigned to entry_failure_code on failure.
9883  */
9884 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9885                                u32 *entry_failure_code)
9886 {
9887         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9888                 if (!nested_cr3_valid(vcpu, cr3)) {
9889                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9890                         return 1;
9891                 }
9892
9893                 /*
9894                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9895                  * must not be dereferenced.
9896                  */
9897                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9898                     !nested_ept) {
9899                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9900                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9901                                 return 1;
9902                         }
9903                 }
9904
9905                 vcpu->arch.cr3 = cr3;
9906                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9907         }
9908
9909         kvm_mmu_reset_context(vcpu);
9910         return 0;
9911 }
9912
9913 /*
9914  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9915  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9916  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9917  * guest in a way that will both be appropriate to L1's requests, and our
9918  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9919  * function also has additional necessary side-effects, like setting various
9920  * vcpu->arch fields.
9921  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9922  * is assigned to entry_failure_code on failure.
9923  */
9924 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9925                           bool from_vmentry, u32 *entry_failure_code)
9926 {
9927         struct vcpu_vmx *vmx = to_vmx(vcpu);
9928         u32 exec_control;
9929
9930         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9931         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9932         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9933         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9934         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9935         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9936         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9937         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9938         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9939         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9940         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9941         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9942         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9943         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9944         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9945         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9946         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9947         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9948         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9949         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9950         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9951         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9952         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9953         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9954         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9955         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9956         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9957         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9958         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9959         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9960         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9961         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9962         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9963         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9964         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9965         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9966
9967         if (from_vmentry &&
9968             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
9969                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9970                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9971         } else {
9972                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9973                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9974         }
9975         if (from_vmentry) {
9976                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9977                              vmcs12->vm_entry_intr_info_field);
9978                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9979                              vmcs12->vm_entry_exception_error_code);
9980                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9981                              vmcs12->vm_entry_instruction_len);
9982                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9983                              vmcs12->guest_interruptibility_info);
9984         } else {
9985                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9986         }
9987         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9988         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9989         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9990                 vmcs12->guest_pending_dbg_exceptions);
9991         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9992         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9993
9994         if (nested_cpu_has_xsaves(vmcs12))
9995                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9996         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9997
9998         exec_control = vmcs12->pin_based_vm_exec_control;
9999
10000         /* Preemption timer setting is only taken from vmcs01.  */
10001         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10002         exec_control |= vmcs_config.pin_based_exec_ctrl;
10003         if (vmx->hv_deadline_tsc == -1)
10004                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10005
10006         /* Posted interrupts setting is only taken from vmcs12.  */
10007         if (nested_cpu_has_posted_intr(vmcs12)) {
10008                 /*
10009                  * Note that we use L0's vector here and in
10010                  * vmx_deliver_nested_posted_interrupt.
10011                  */
10012                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10013                 vmx->nested.pi_pending = false;
10014                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10015         } else {
10016                 exec_control &= ~PIN_BASED_POSTED_INTR;
10017         }
10018
10019         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10020
10021         vmx->nested.preemption_timer_expired = false;
10022         if (nested_cpu_has_preemption_timer(vmcs12))
10023                 vmx_start_preemption_timer(vcpu);
10024
10025         /*
10026          * Whether page-faults are trapped is determined by a combination of
10027          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10028          * If enable_ept, L0 doesn't care about page faults and we should
10029          * set all of these to L1's desires. However, if !enable_ept, L0 does
10030          * care about (at least some) page faults, and because it is not easy
10031          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10032          * to exit on each and every L2 page fault. This is done by setting
10033          * MASK=MATCH=0 and (see below) EB.PF=1.
10034          * Note that below we don't need special code to set EB.PF beyond the
10035          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10036          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10037          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10038          *
10039          * A problem with this approach (when !enable_ept) is that L1 may be
10040          * injected with more page faults than it asked for. This could have
10041          * caused problems, but in practice existing hypervisors don't care.
10042          * To fix this, we will need to emulate the PFEC checking (on the L1
10043          * page tables), using walk_addr(), when injecting PFs to L1.
10044          */
10045         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10046                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10047         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10048                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10049
10050         if (cpu_has_secondary_exec_ctrls()) {
10051                 exec_control = vmx_secondary_exec_control(vmx);
10052
10053                 /* Take the following fields only from vmcs12 */
10054                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10055                                   SECONDARY_EXEC_RDTSCP |
10056                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10057                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10058                 if (nested_cpu_has(vmcs12,
10059                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10060                         exec_control |= vmcs12->secondary_vm_exec_control;
10061
10062                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10063                         vmcs_write64(EOI_EXIT_BITMAP0,
10064                                 vmcs12->eoi_exit_bitmap0);
10065                         vmcs_write64(EOI_EXIT_BITMAP1,
10066                                 vmcs12->eoi_exit_bitmap1);
10067                         vmcs_write64(EOI_EXIT_BITMAP2,
10068                                 vmcs12->eoi_exit_bitmap2);
10069                         vmcs_write64(EOI_EXIT_BITMAP3,
10070                                 vmcs12->eoi_exit_bitmap3);
10071                         vmcs_write16(GUEST_INTR_STATUS,
10072                                 vmcs12->guest_intr_status);
10073                 }
10074
10075                 /*
10076                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10077                  * nested_get_vmcs12_pages will either fix it up or
10078                  * remove the VM execution control.
10079                  */
10080                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10081                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10082
10083                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10084         }
10085
10086
10087         /*
10088          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10089          * Some constant fields are set here by vmx_set_constant_host_state().
10090          * Other fields are different per CPU, and will be set later when
10091          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10092          */
10093         vmx_set_constant_host_state(vmx);
10094
10095         /*
10096          * Set the MSR load/store lists to match L0's settings.
10097          */
10098         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10099         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10100         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10101         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10102         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10103
10104         /*
10105          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10106          * entry, but only if the current (host) sp changed from the value
10107          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10108          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10109          * here we just force the write to happen on entry.
10110          */
10111         vmx->host_rsp = 0;
10112
10113         exec_control = vmx_exec_control(vmx); /* L0's desires */
10114         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10115         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10116         exec_control &= ~CPU_BASED_TPR_SHADOW;
10117         exec_control |= vmcs12->cpu_based_vm_exec_control;
10118
10119         /*
10120          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10121          * nested_get_vmcs12_pages can't fix it up, the illegal value
10122          * will result in a VM entry failure.
10123          */
10124         if (exec_control & CPU_BASED_TPR_SHADOW) {
10125                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10126                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10127         }
10128
10129         /*
10130          * Merging of IO bitmap not currently supported.
10131          * Rather, exit every time.
10132          */
10133         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10134         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10135
10136         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10137
10138         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10139          * bitwise-or of what L1 wants to trap for L2, and what we want to
10140          * trap. Note that CR0.TS also needs updating - we do this later.
10141          */
10142         update_exception_bitmap(vcpu);
10143         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10144         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10145
10146         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10147          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10148          * bits are further modified by vmx_set_efer() below.
10149          */
10150         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10151
10152         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10153          * emulated by vmx_set_efer(), below.
10154          */
10155         vm_entry_controls_init(vmx,
10156                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10157                         ~VM_ENTRY_IA32E_MODE) |
10158                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10159
10160         if (from_vmentry &&
10161             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10162                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10163                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10164         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10165                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10166         }
10167
10168         set_cr4_guest_host_mask(vmx);
10169
10170         if (from_vmentry &&
10171             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10172                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10173
10174         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10175                 vmcs_write64(TSC_OFFSET,
10176                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10177         else
10178                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10179         if (kvm_has_tsc_control)
10180                 decache_tsc_multiplier(vmx);
10181
10182         if (enable_vpid) {
10183                 /*
10184                  * There is no direct mapping between vpid02 and vpid12, the
10185                  * vpid02 is per-vCPU for L0 and reused while the value of
10186                  * vpid12 is changed w/ one invvpid during nested vmentry.
10187                  * The vpid12 is allocated by L1 for L2, so it will not
10188                  * influence global bitmap(for vpid01 and vpid02 allocation)
10189                  * even if spawn a lot of nested vCPUs.
10190                  */
10191                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10192                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10193                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10194                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10195                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10196                         }
10197                 } else {
10198                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10199                         vmx_flush_tlb(vcpu);
10200                 }
10201
10202         }
10203
10204         if (nested_cpu_has_ept(vmcs12)) {
10205                 kvm_mmu_unload(vcpu);
10206                 nested_ept_init_mmu_context(vcpu);
10207         } else if (nested_cpu_has2(vmcs12,
10208                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10209                 vmx_flush_tlb_ept_only(vcpu);
10210         }
10211
10212         /*
10213          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10214          * bits which we consider mandatory enabled.
10215          * The CR0_READ_SHADOW is what L2 should have expected to read given
10216          * the specifications by L1; It's not enough to take
10217          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10218          * have more bits than L1 expected.
10219          */
10220         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10221         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10222
10223         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10224         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10225
10226         if (from_vmentry &&
10227             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10228                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10229         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10230                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10231         else
10232                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10233         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10234         vmx_set_efer(vcpu, vcpu->arch.efer);
10235
10236         /* Shadow page tables on either EPT or shadow page tables. */
10237         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10238                                 entry_failure_code))
10239                 return 1;
10240
10241         if (!enable_ept)
10242                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10243
10244         /*
10245          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10246          */
10247         if (enable_ept) {
10248                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10249                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10250                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10251                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10252         }
10253
10254         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10255         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10256         return 0;
10257 }
10258
10259 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10260 {
10261         struct vcpu_vmx *vmx = to_vmx(vcpu);
10262
10263         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10264             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10265                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10266
10267         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10268                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10269
10270         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10271                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10272
10273         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10274                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10275
10276         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10277                                 vmx->nested.nested_vmx_procbased_ctls_low,
10278                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10279             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10280                                 vmx->nested.nested_vmx_secondary_ctls_low,
10281                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10282             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10283                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10284                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10285             !vmx_control_verify(vmcs12->vm_exit_controls,
10286                                 vmx->nested.nested_vmx_exit_ctls_low,
10287                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10288             !vmx_control_verify(vmcs12->vm_entry_controls,
10289                                 vmx->nested.nested_vmx_entry_ctls_low,
10290                                 vmx->nested.nested_vmx_entry_ctls_high))
10291                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10292
10293         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10294             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10295             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10296                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10297
10298         return 0;
10299 }
10300
10301 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10302                                   u32 *exit_qual)
10303 {
10304         bool ia32e;
10305
10306         *exit_qual = ENTRY_FAIL_DEFAULT;
10307
10308         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10309             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10310                 return 1;
10311
10312         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10313             vmcs12->vmcs_link_pointer != -1ull) {
10314                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10315                 return 1;
10316         }
10317
10318         /*
10319          * If the load IA32_EFER VM-entry control is 1, the following checks
10320          * are performed on the field for the IA32_EFER MSR:
10321          * - Bits reserved in the IA32_EFER MSR must be 0.
10322          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10323          *   the IA-32e mode guest VM-exit control. It must also be identical
10324          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10325          *   CR0.PG) is 1.
10326          */
10327         if (to_vmx(vcpu)->nested.nested_run_pending &&
10328             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10329                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10330                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10331                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10332                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10333                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10334                         return 1;
10335         }
10336
10337         /*
10338          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10339          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10340          * the values of the LMA and LME bits in the field must each be that of
10341          * the host address-space size VM-exit control.
10342          */
10343         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10344                 ia32e = (vmcs12->vm_exit_controls &
10345                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10346                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10347                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10348                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10349                         return 1;
10350         }
10351
10352         return 0;
10353 }
10354
10355 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10356 {
10357         struct vcpu_vmx *vmx = to_vmx(vcpu);
10358         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10359         struct loaded_vmcs *vmcs02;
10360         u32 msr_entry_idx;
10361         u32 exit_qual;
10362
10363         vmcs02 = nested_get_current_vmcs02(vmx);
10364         if (!vmcs02)
10365                 return -ENOMEM;
10366
10367         enter_guest_mode(vcpu);
10368
10369         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10370                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10371
10372         vmx_switch_vmcs(vcpu, vmcs02);
10373         vmx_segment_cache_clear(vmx);
10374
10375         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10376                 leave_guest_mode(vcpu);
10377                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10378                 nested_vmx_entry_failure(vcpu, vmcs12,
10379                                          EXIT_REASON_INVALID_STATE, exit_qual);
10380                 return 1;
10381         }
10382
10383         nested_get_vmcs12_pages(vcpu, vmcs12);
10384
10385         msr_entry_idx = nested_vmx_load_msr(vcpu,
10386                                             vmcs12->vm_entry_msr_load_addr,
10387                                             vmcs12->vm_entry_msr_load_count);
10388         if (msr_entry_idx) {
10389                 leave_guest_mode(vcpu);
10390                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10391                 nested_vmx_entry_failure(vcpu, vmcs12,
10392                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10393                 return 1;
10394         }
10395
10396         vmcs12->launch_state = 1;
10397
10398         /*
10399          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10400          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10401          * returned as far as L1 is concerned. It will only return (and set
10402          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10403          */
10404         return 0;
10405 }
10406
10407 /*
10408  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10409  * for running an L2 nested guest.
10410  */
10411 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10412 {
10413         struct vmcs12 *vmcs12;
10414         struct vcpu_vmx *vmx = to_vmx(vcpu);
10415         u32 exit_qual;
10416         int ret;
10417
10418         if (!nested_vmx_check_permission(vcpu))
10419                 return 1;
10420
10421         if (!nested_vmx_check_vmcs12(vcpu))
10422                 goto out;
10423
10424         vmcs12 = get_vmcs12(vcpu);
10425
10426         if (enable_shadow_vmcs)
10427                 copy_shadow_to_vmcs12(vmx);
10428
10429         /*
10430          * The nested entry process starts with enforcing various prerequisites
10431          * on vmcs12 as required by the Intel SDM, and act appropriately when
10432          * they fail: As the SDM explains, some conditions should cause the
10433          * instruction to fail, while others will cause the instruction to seem
10434          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10435          * To speed up the normal (success) code path, we should avoid checking
10436          * for misconfigurations which will anyway be caught by the processor
10437          * when using the merged vmcs02.
10438          */
10439         if (vmcs12->launch_state == launch) {
10440                 nested_vmx_failValid(vcpu,
10441                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10442                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10443                 goto out;
10444         }
10445
10446         ret = check_vmentry_prereqs(vcpu, vmcs12);
10447         if (ret) {
10448                 nested_vmx_failValid(vcpu, ret);
10449                 goto out;
10450         }
10451
10452         /*
10453          * After this point, the trap flag no longer triggers a singlestep trap
10454          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10455          * This is not 100% correct; for performance reasons, we delegate most
10456          * of the checks on host state to the processor.  If those fail,
10457          * the singlestep trap is missed.
10458          */
10459         skip_emulated_instruction(vcpu);
10460
10461         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10462         if (ret) {
10463                 nested_vmx_entry_failure(vcpu, vmcs12,
10464                                          EXIT_REASON_INVALID_STATE, exit_qual);
10465                 return 1;
10466         }
10467
10468         /*
10469          * We're finally done with prerequisite checking, and can start with
10470          * the nested entry.
10471          */
10472
10473         ret = enter_vmx_non_root_mode(vcpu, true);
10474         if (ret)
10475                 return ret;
10476
10477         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10478                 return kvm_vcpu_halt(vcpu);
10479
10480         vmx->nested.nested_run_pending = 1;
10481
10482         return 1;
10483
10484 out:
10485         return kvm_skip_emulated_instruction(vcpu);
10486 }
10487
10488 /*
10489  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10490  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10491  * This function returns the new value we should put in vmcs12.guest_cr0.
10492  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10493  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10494  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10495  *     didn't trap the bit, because if L1 did, so would L0).
10496  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10497  *     been modified by L2, and L1 knows it. So just leave the old value of
10498  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10499  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10500  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10501  *     changed these bits, and therefore they need to be updated, but L0
10502  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10503  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10504  */
10505 static inline unsigned long
10506 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10507 {
10508         return
10509         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10510         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10511         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10512                         vcpu->arch.cr0_guest_owned_bits));
10513 }
10514
10515 static inline unsigned long
10516 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10517 {
10518         return
10519         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10520         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10521         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10522                         vcpu->arch.cr4_guest_owned_bits));
10523 }
10524
10525 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10526                                        struct vmcs12 *vmcs12)
10527 {
10528         u32 idt_vectoring;
10529         unsigned int nr;
10530
10531         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10532                 nr = vcpu->arch.exception.nr;
10533                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10534
10535                 if (kvm_exception_is_soft(nr)) {
10536                         vmcs12->vm_exit_instruction_len =
10537                                 vcpu->arch.event_exit_inst_len;
10538                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10539                 } else
10540                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10541
10542                 if (vcpu->arch.exception.has_error_code) {
10543                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10544                         vmcs12->idt_vectoring_error_code =
10545                                 vcpu->arch.exception.error_code;
10546                 }
10547
10548                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10549         } else if (vcpu->arch.nmi_injected) {
10550                 vmcs12->idt_vectoring_info_field =
10551                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10552         } else if (vcpu->arch.interrupt.pending) {
10553                 nr = vcpu->arch.interrupt.nr;
10554                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10555
10556                 if (vcpu->arch.interrupt.soft) {
10557                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10558                         vmcs12->vm_entry_instruction_len =
10559                                 vcpu->arch.event_exit_inst_len;
10560                 } else
10561                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10562
10563                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10564         }
10565 }
10566
10567 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10568 {
10569         struct vcpu_vmx *vmx = to_vmx(vcpu);
10570
10571         if (vcpu->arch.exception.pending ||
10572                 vcpu->arch.nmi_injected ||
10573                 vcpu->arch.interrupt.pending)
10574                 return -EBUSY;
10575
10576         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10577             vmx->nested.preemption_timer_expired) {
10578                 if (vmx->nested.nested_run_pending)
10579                         return -EBUSY;
10580                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10581                 return 0;
10582         }
10583
10584         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10585                 if (vmx->nested.nested_run_pending)
10586                         return -EBUSY;
10587                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10588                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10589                                   INTR_INFO_VALID_MASK, 0);
10590                 /*
10591                  * The NMI-triggered VM exit counts as injection:
10592                  * clear this one and block further NMIs.
10593                  */
10594                 vcpu->arch.nmi_pending = 0;
10595                 vmx_set_nmi_mask(vcpu, true);
10596                 return 0;
10597         }
10598
10599         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10600             nested_exit_on_intr(vcpu)) {
10601                 if (vmx->nested.nested_run_pending)
10602                         return -EBUSY;
10603                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10604                 return 0;
10605         }
10606
10607         vmx_complete_nested_posted_interrupt(vcpu);
10608         return 0;
10609 }
10610
10611 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10612 {
10613         ktime_t remaining =
10614                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10615         u64 value;
10616
10617         if (ktime_to_ns(remaining) <= 0)
10618                 return 0;
10619
10620         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10621         do_div(value, 1000000);
10622         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10623 }
10624
10625 /*
10626  * Update the guest state fields of vmcs12 to reflect changes that
10627  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10628  * VM-entry controls is also updated, since this is really a guest
10629  * state bit.)
10630  */
10631 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10632 {
10633         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10634         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10635
10636         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10637         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10638         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10639
10640         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10641         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10642         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10643         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10644         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10645         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10646         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10647         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10648         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10649         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10650         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10651         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10652         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10653         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10654         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10655         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10656         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10657         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10658         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10659         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10660         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10661         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10662         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10663         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10664         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10665         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10666         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10667         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10668         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10669         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10670         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10671         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10672         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10673         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10674         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10675         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10676
10677         vmcs12->guest_interruptibility_info =
10678                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10679         vmcs12->guest_pending_dbg_exceptions =
10680                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10681         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10682                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10683         else
10684                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10685
10686         if (nested_cpu_has_preemption_timer(vmcs12)) {
10687                 if (vmcs12->vm_exit_controls &
10688                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10689                         vmcs12->vmx_preemption_timer_value =
10690                                 vmx_get_preemption_timer_value(vcpu);
10691                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10692         }
10693
10694         /*
10695          * In some cases (usually, nested EPT), L2 is allowed to change its
10696          * own CR3 without exiting. If it has changed it, we must keep it.
10697          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10698          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10699          *
10700          * Additionally, restore L2's PDPTR to vmcs12.
10701          */
10702         if (enable_ept) {
10703                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10704                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10705                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10706                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10707                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10708         }
10709
10710         if (nested_cpu_has_ept(vmcs12))
10711                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10712
10713         if (nested_cpu_has_vid(vmcs12))
10714                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10715
10716         vmcs12->vm_entry_controls =
10717                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10718                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10719
10720         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10721                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10722                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10723         }
10724
10725         /* TODO: These cannot have changed unless we have MSR bitmaps and
10726          * the relevant bit asks not to trap the change */
10727         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10728                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10729         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10730                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10731         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10732         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10733         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10734         if (kvm_mpx_supported())
10735                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10736         if (nested_cpu_has_xsaves(vmcs12))
10737                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10738 }
10739
10740 /*
10741  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10742  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10743  * and this function updates it to reflect the changes to the guest state while
10744  * L2 was running (and perhaps made some exits which were handled directly by L0
10745  * without going back to L1), and to reflect the exit reason.
10746  * Note that we do not have to copy here all VMCS fields, just those that
10747  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10748  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10749  * which already writes to vmcs12 directly.
10750  */
10751 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10752                            u32 exit_reason, u32 exit_intr_info,
10753                            unsigned long exit_qualification)
10754 {
10755         /* update guest state fields: */
10756         sync_vmcs12(vcpu, vmcs12);
10757
10758         /* update exit information fields: */
10759
10760         vmcs12->vm_exit_reason = exit_reason;
10761         vmcs12->exit_qualification = exit_qualification;
10762
10763         vmcs12->vm_exit_intr_info = exit_intr_info;
10764         if ((vmcs12->vm_exit_intr_info &
10765              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10766             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10767                 vmcs12->vm_exit_intr_error_code =
10768                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10769         vmcs12->idt_vectoring_info_field = 0;
10770         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10771         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10772
10773         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10774                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10775                  * instead of reading the real value. */
10776                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10777
10778                 /*
10779                  * Transfer the event that L0 or L1 may wanted to inject into
10780                  * L2 to IDT_VECTORING_INFO_FIELD.
10781                  */
10782                 vmcs12_save_pending_event(vcpu, vmcs12);
10783         }
10784
10785         /*
10786          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10787          * preserved above and would only end up incorrectly in L1.
10788          */
10789         vcpu->arch.nmi_injected = false;
10790         kvm_clear_exception_queue(vcpu);
10791         kvm_clear_interrupt_queue(vcpu);
10792 }
10793
10794 /*
10795  * A part of what we need to when the nested L2 guest exits and we want to
10796  * run its L1 parent, is to reset L1's guest state to the host state specified
10797  * in vmcs12.
10798  * This function is to be called not only on normal nested exit, but also on
10799  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10800  * Failures During or After Loading Guest State").
10801  * This function should be called when the active VMCS is L1's (vmcs01).
10802  */
10803 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10804                                    struct vmcs12 *vmcs12)
10805 {
10806         struct kvm_segment seg;
10807         u32 entry_failure_code;
10808
10809         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10810                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10811         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10812                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10813         else
10814                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10815         vmx_set_efer(vcpu, vcpu->arch.efer);
10816
10817         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10818         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10819         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10820         /*
10821          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10822          * actually changed, because vmx_set_cr0 refers to efer set above.
10823          *
10824          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10825          * (KVM doesn't change it);
10826          */
10827         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10828         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10829
10830         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10831         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10832         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10833
10834         nested_ept_uninit_mmu_context(vcpu);
10835
10836         /*
10837          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10838          * couldn't have changed.
10839          */
10840         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10841                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10842
10843         if (!enable_ept)
10844                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10845
10846         if (enable_vpid) {
10847                 /*
10848                  * Trivially support vpid by letting L2s share their parent
10849                  * L1's vpid. TODO: move to a more elaborate solution, giving
10850                  * each L2 its own vpid and exposing the vpid feature to L1.
10851                  */
10852                 vmx_flush_tlb(vcpu);
10853         }
10854
10855
10856         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10857         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10858         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10859         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10860         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10861
10862         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10863         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10864                 vmcs_write64(GUEST_BNDCFGS, 0);
10865
10866         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10867                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10868                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10869         }
10870         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10871                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10872                         vmcs12->host_ia32_perf_global_ctrl);
10873
10874         /* Set L1 segment info according to Intel SDM
10875             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10876         seg = (struct kvm_segment) {
10877                 .base = 0,
10878                 .limit = 0xFFFFFFFF,
10879                 .selector = vmcs12->host_cs_selector,
10880                 .type = 11,
10881                 .present = 1,
10882                 .s = 1,
10883                 .g = 1
10884         };
10885         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10886                 seg.l = 1;
10887         else
10888                 seg.db = 1;
10889         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10890         seg = (struct kvm_segment) {
10891                 .base = 0,
10892                 .limit = 0xFFFFFFFF,
10893                 .type = 3,
10894                 .present = 1,
10895                 .s = 1,
10896                 .db = 1,
10897                 .g = 1
10898         };
10899         seg.selector = vmcs12->host_ds_selector;
10900         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10901         seg.selector = vmcs12->host_es_selector;
10902         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10903         seg.selector = vmcs12->host_ss_selector;
10904         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10905         seg.selector = vmcs12->host_fs_selector;
10906         seg.base = vmcs12->host_fs_base;
10907         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10908         seg.selector = vmcs12->host_gs_selector;
10909         seg.base = vmcs12->host_gs_base;
10910         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10911         seg = (struct kvm_segment) {
10912                 .base = vmcs12->host_tr_base,
10913                 .limit = 0x67,
10914                 .selector = vmcs12->host_tr_selector,
10915                 .type = 11,
10916                 .present = 1
10917         };
10918         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10919
10920         kvm_set_dr(vcpu, 7, 0x400);
10921         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10922
10923         if (cpu_has_vmx_msr_bitmap())
10924                 vmx_set_msr_bitmap(vcpu);
10925
10926         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10927                                 vmcs12->vm_exit_msr_load_count))
10928                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10929 }
10930
10931 /*
10932  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10933  * and modify vmcs12 to make it see what it would expect to see there if
10934  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10935  */
10936 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10937                               u32 exit_intr_info,
10938                               unsigned long exit_qualification)
10939 {
10940         struct vcpu_vmx *vmx = to_vmx(vcpu);
10941         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10942         u32 vm_inst_error = 0;
10943
10944         /* trying to cancel vmlaunch/vmresume is a bug */
10945         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10946
10947         leave_guest_mode(vcpu);
10948         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10949                        exit_qualification);
10950
10951         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10952                                  vmcs12->vm_exit_msr_store_count))
10953                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10954
10955         if (unlikely(vmx->fail))
10956                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10957
10958         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10959
10960         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10961             && nested_exit_intr_ack_set(vcpu)) {
10962                 int irq = kvm_cpu_get_interrupt(vcpu);
10963                 WARN_ON(irq < 0);
10964                 vmcs12->vm_exit_intr_info = irq |
10965                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10966         }
10967
10968         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10969                                        vmcs12->exit_qualification,
10970                                        vmcs12->idt_vectoring_info_field,
10971                                        vmcs12->vm_exit_intr_info,
10972                                        vmcs12->vm_exit_intr_error_code,
10973                                        KVM_ISA_VMX);
10974
10975         vm_entry_controls_reset_shadow(vmx);
10976         vm_exit_controls_reset_shadow(vmx);
10977         vmx_segment_cache_clear(vmx);
10978
10979         /* if no vmcs02 cache requested, remove the one we used */
10980         if (VMCS02_POOL_SIZE == 0)
10981                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10982
10983         load_vmcs12_host_state(vcpu, vmcs12);
10984
10985         /* Update any VMCS fields that might have changed while L2 ran */
10986         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10987         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10988         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10989         if (vmx->hv_deadline_tsc == -1)
10990                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10991                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10992         else
10993                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10994                               PIN_BASED_VMX_PREEMPTION_TIMER);
10995         if (kvm_has_tsc_control)
10996                 decache_tsc_multiplier(vmx);
10997
10998         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10999                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11000                 vmx_set_virtual_x2apic_mode(vcpu,
11001                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11002         } else if (!nested_cpu_has_ept(vmcs12) &&
11003                    nested_cpu_has2(vmcs12,
11004                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11005                 vmx_flush_tlb_ept_only(vcpu);
11006         }
11007
11008         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11009         vmx->host_rsp = 0;
11010
11011         /* Unpin physical memory we referred to in vmcs02 */
11012         if (vmx->nested.apic_access_page) {
11013                 nested_release_page(vmx->nested.apic_access_page);
11014                 vmx->nested.apic_access_page = NULL;
11015         }
11016         if (vmx->nested.virtual_apic_page) {
11017                 nested_release_page(vmx->nested.virtual_apic_page);
11018                 vmx->nested.virtual_apic_page = NULL;
11019         }
11020         if (vmx->nested.pi_desc_page) {
11021                 kunmap(vmx->nested.pi_desc_page);
11022                 nested_release_page(vmx->nested.pi_desc_page);
11023                 vmx->nested.pi_desc_page = NULL;
11024                 vmx->nested.pi_desc = NULL;
11025         }
11026
11027         /*
11028          * We are now running in L2, mmu_notifier will force to reload the
11029          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11030          */
11031         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11032
11033         /*
11034          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11035          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11036          * success or failure flag accordingly.
11037          */
11038         if (unlikely(vmx->fail)) {
11039                 vmx->fail = 0;
11040                 nested_vmx_failValid(vcpu, vm_inst_error);
11041         } else
11042                 nested_vmx_succeed(vcpu);
11043         if (enable_shadow_vmcs)
11044                 vmx->nested.sync_shadow_vmcs = true;
11045
11046         /* in case we halted in L2 */
11047         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11048 }
11049
11050 /*
11051  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11052  */
11053 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11054 {
11055         if (is_guest_mode(vcpu)) {
11056                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11057                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11058         }
11059         free_nested(to_vmx(vcpu));
11060 }
11061
11062 /*
11063  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11064  * 23.7 "VM-entry failures during or after loading guest state" (this also
11065  * lists the acceptable exit-reason and exit-qualification parameters).
11066  * It should only be called before L2 actually succeeded to run, and when
11067  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11068  */
11069 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11070                         struct vmcs12 *vmcs12,
11071                         u32 reason, unsigned long qualification)
11072 {
11073         load_vmcs12_host_state(vcpu, vmcs12);
11074         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11075         vmcs12->exit_qualification = qualification;
11076         nested_vmx_succeed(vcpu);
11077         if (enable_shadow_vmcs)
11078                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11079 }
11080
11081 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11082                                struct x86_instruction_info *info,
11083                                enum x86_intercept_stage stage)
11084 {
11085         return X86EMUL_CONTINUE;
11086 }
11087
11088 #ifdef CONFIG_X86_64
11089 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11090 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11091                                   u64 divisor, u64 *result)
11092 {
11093         u64 low = a << shift, high = a >> (64 - shift);
11094
11095         /* To avoid the overflow on divq */
11096         if (high >= divisor)
11097                 return 1;
11098
11099         /* Low hold the result, high hold rem which is discarded */
11100         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11101             "rm" (divisor), "0" (low), "1" (high));
11102         *result = low;
11103
11104         return 0;
11105 }
11106
11107 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11108 {
11109         struct vcpu_vmx *vmx = to_vmx(vcpu);
11110         u64 tscl = rdtsc();
11111         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11112         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11113
11114         /* Convert to host delta tsc if tsc scaling is enabled */
11115         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11116                         u64_shl_div_u64(delta_tsc,
11117                                 kvm_tsc_scaling_ratio_frac_bits,
11118                                 vcpu->arch.tsc_scaling_ratio,
11119                                 &delta_tsc))
11120                 return -ERANGE;
11121
11122         /*
11123          * If the delta tsc can't fit in the 32 bit after the multi shift,
11124          * we can't use the preemption timer.
11125          * It's possible that it fits on later vmentries, but checking
11126          * on every vmentry is costly so we just use an hrtimer.
11127          */
11128         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11129                 return -ERANGE;
11130
11131         vmx->hv_deadline_tsc = tscl + delta_tsc;
11132         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11133                         PIN_BASED_VMX_PREEMPTION_TIMER);
11134         return 0;
11135 }
11136
11137 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11138 {
11139         struct vcpu_vmx *vmx = to_vmx(vcpu);
11140         vmx->hv_deadline_tsc = -1;
11141         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11142                         PIN_BASED_VMX_PREEMPTION_TIMER);
11143 }
11144 #endif
11145
11146 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11147 {
11148         if (ple_gap)
11149                 shrink_ple_window(vcpu);
11150 }
11151
11152 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11153                                      struct kvm_memory_slot *slot)
11154 {
11155         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11156         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11157 }
11158
11159 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11160                                        struct kvm_memory_slot *slot)
11161 {
11162         kvm_mmu_slot_set_dirty(kvm, slot);
11163 }
11164
11165 static void vmx_flush_log_dirty(struct kvm *kvm)
11166 {
11167         kvm_flush_pml_buffers(kvm);
11168 }
11169
11170 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11171                                            struct kvm_memory_slot *memslot,
11172                                            gfn_t offset, unsigned long mask)
11173 {
11174         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11175 }
11176
11177 /*
11178  * This routine does the following things for vCPU which is going
11179  * to be blocked if VT-d PI is enabled.
11180  * - Store the vCPU to the wakeup list, so when interrupts happen
11181  *   we can find the right vCPU to wake up.
11182  * - Change the Posted-interrupt descriptor as below:
11183  *      'NDST' <-- vcpu->pre_pcpu
11184  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11185  * - If 'ON' is set during this process, which means at least one
11186  *   interrupt is posted for this vCPU, we cannot block it, in
11187  *   this case, return 1, otherwise, return 0.
11188  *
11189  */
11190 static int pi_pre_block(struct kvm_vcpu *vcpu)
11191 {
11192         unsigned long flags;
11193         unsigned int dest;
11194         struct pi_desc old, new;
11195         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11196
11197         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11198                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11199                 !kvm_vcpu_apicv_active(vcpu))
11200                 return 0;
11201
11202         vcpu->pre_pcpu = vcpu->cpu;
11203         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11204                           vcpu->pre_pcpu), flags);
11205         list_add_tail(&vcpu->blocked_vcpu_list,
11206                       &per_cpu(blocked_vcpu_on_cpu,
11207                       vcpu->pre_pcpu));
11208         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11209                                vcpu->pre_pcpu), flags);
11210
11211         do {
11212                 old.control = new.control = pi_desc->control;
11213
11214                 /*
11215                  * We should not block the vCPU if
11216                  * an interrupt is posted for it.
11217                  */
11218                 if (pi_test_on(pi_desc) == 1) {
11219                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11220                                           vcpu->pre_pcpu), flags);
11221                         list_del(&vcpu->blocked_vcpu_list);
11222                         spin_unlock_irqrestore(
11223                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11224                                         vcpu->pre_pcpu), flags);
11225                         vcpu->pre_pcpu = -1;
11226
11227                         return 1;
11228                 }
11229
11230                 WARN((pi_desc->sn == 1),
11231                      "Warning: SN field of posted-interrupts "
11232                      "is set before blocking\n");
11233
11234                 /*
11235                  * Since vCPU can be preempted during this process,
11236                  * vcpu->cpu could be different with pre_pcpu, we
11237                  * need to set pre_pcpu as the destination of wakeup
11238                  * notification event, then we can find the right vCPU
11239                  * to wakeup in wakeup handler if interrupts happen
11240                  * when the vCPU is in blocked state.
11241                  */
11242                 dest = cpu_physical_id(vcpu->pre_pcpu);
11243
11244                 if (x2apic_enabled())
11245                         new.ndst = dest;
11246                 else
11247                         new.ndst = (dest << 8) & 0xFF00;
11248
11249                 /* set 'NV' to 'wakeup vector' */
11250                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11251         } while (cmpxchg(&pi_desc->control, old.control,
11252                         new.control) != old.control);
11253
11254         return 0;
11255 }
11256
11257 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11258 {
11259         if (pi_pre_block(vcpu))
11260                 return 1;
11261
11262         if (kvm_lapic_hv_timer_in_use(vcpu))
11263                 kvm_lapic_switch_to_sw_timer(vcpu);
11264
11265         return 0;
11266 }
11267
11268 static void pi_post_block(struct kvm_vcpu *vcpu)
11269 {
11270         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11271         struct pi_desc old, new;
11272         unsigned int dest;
11273         unsigned long flags;
11274
11275         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11276                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11277                 !kvm_vcpu_apicv_active(vcpu))
11278                 return;
11279
11280         do {
11281                 old.control = new.control = pi_desc->control;
11282
11283                 dest = cpu_physical_id(vcpu->cpu);
11284
11285                 if (x2apic_enabled())
11286                         new.ndst = dest;
11287                 else
11288                         new.ndst = (dest << 8) & 0xFF00;
11289
11290                 /* Allow posting non-urgent interrupts */
11291                 new.sn = 0;
11292
11293                 /* set 'NV' to 'notification vector' */
11294                 new.nv = POSTED_INTR_VECTOR;
11295         } while (cmpxchg(&pi_desc->control, old.control,
11296                         new.control) != old.control);
11297
11298         if(vcpu->pre_pcpu != -1) {
11299                 spin_lock_irqsave(
11300                         &per_cpu(blocked_vcpu_on_cpu_lock,
11301                         vcpu->pre_pcpu), flags);
11302                 list_del(&vcpu->blocked_vcpu_list);
11303                 spin_unlock_irqrestore(
11304                         &per_cpu(blocked_vcpu_on_cpu_lock,
11305                         vcpu->pre_pcpu), flags);
11306                 vcpu->pre_pcpu = -1;
11307         }
11308 }
11309
11310 static void vmx_post_block(struct kvm_vcpu *vcpu)
11311 {
11312         if (kvm_x86_ops->set_hv_timer)
11313                 kvm_lapic_switch_to_hv_timer(vcpu);
11314
11315         pi_post_block(vcpu);
11316 }
11317
11318 /*
11319  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11320  *
11321  * @kvm: kvm
11322  * @host_irq: host irq of the interrupt
11323  * @guest_irq: gsi of the interrupt
11324  * @set: set or unset PI
11325  * returns 0 on success, < 0 on failure
11326  */
11327 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11328                               uint32_t guest_irq, bool set)
11329 {
11330         struct kvm_kernel_irq_routing_entry *e;
11331         struct kvm_irq_routing_table *irq_rt;
11332         struct kvm_lapic_irq irq;
11333         struct kvm_vcpu *vcpu;
11334         struct vcpu_data vcpu_info;
11335         int idx, ret = -EINVAL;
11336
11337         if (!kvm_arch_has_assigned_device(kvm) ||
11338                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11339                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11340                 return 0;
11341
11342         idx = srcu_read_lock(&kvm->irq_srcu);
11343         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11344         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11345
11346         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11347                 if (e->type != KVM_IRQ_ROUTING_MSI)
11348                         continue;
11349                 /*
11350                  * VT-d PI cannot support posting multicast/broadcast
11351                  * interrupts to a vCPU, we still use interrupt remapping
11352                  * for these kind of interrupts.
11353                  *
11354                  * For lowest-priority interrupts, we only support
11355                  * those with single CPU as the destination, e.g. user
11356                  * configures the interrupts via /proc/irq or uses
11357                  * irqbalance to make the interrupts single-CPU.
11358                  *
11359                  * We will support full lowest-priority interrupt later.
11360                  */
11361
11362                 kvm_set_msi_irq(kvm, e, &irq);
11363                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11364                         /*
11365                          * Make sure the IRTE is in remapped mode if
11366                          * we don't handle it in posted mode.
11367                          */
11368                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11369                         if (ret < 0) {
11370                                 printk(KERN_INFO
11371                                    "failed to back to remapped mode, irq: %u\n",
11372                                    host_irq);
11373                                 goto out;
11374                         }
11375
11376                         continue;
11377                 }
11378
11379                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11380                 vcpu_info.vector = irq.vector;
11381
11382                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11383                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11384
11385                 if (set)
11386                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11387                 else {
11388                         /* suppress notification event before unposting */
11389                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11390                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11391                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11392                 }
11393
11394                 if (ret < 0) {
11395                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11396                                         __func__);
11397                         goto out;
11398                 }
11399         }
11400
11401         ret = 0;
11402 out:
11403         srcu_read_unlock(&kvm->irq_srcu, idx);
11404         return ret;
11405 }
11406
11407 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11408 {
11409         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11410                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11411                         FEATURE_CONTROL_LMCE;
11412         else
11413                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11414                         ~FEATURE_CONTROL_LMCE;
11415 }
11416
11417 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11418         .cpu_has_kvm_support = cpu_has_kvm_support,
11419         .disabled_by_bios = vmx_disabled_by_bios,
11420         .hardware_setup = hardware_setup,
11421         .hardware_unsetup = hardware_unsetup,
11422         .check_processor_compatibility = vmx_check_processor_compat,
11423         .hardware_enable = hardware_enable,
11424         .hardware_disable = hardware_disable,
11425         .cpu_has_accelerated_tpr = report_flexpriority,
11426         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11427
11428         .vcpu_create = vmx_create_vcpu,
11429         .vcpu_free = vmx_free_vcpu,
11430         .vcpu_reset = vmx_vcpu_reset,
11431
11432         .prepare_guest_switch = vmx_save_host_state,
11433         .vcpu_load = vmx_vcpu_load,
11434         .vcpu_put = vmx_vcpu_put,
11435
11436         .update_bp_intercept = update_exception_bitmap,
11437         .get_msr = vmx_get_msr,
11438         .set_msr = vmx_set_msr,
11439         .get_segment_base = vmx_get_segment_base,
11440         .get_segment = vmx_get_segment,
11441         .set_segment = vmx_set_segment,
11442         .get_cpl = vmx_get_cpl,
11443         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11444         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11445         .decache_cr3 = vmx_decache_cr3,
11446         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11447         .set_cr0 = vmx_set_cr0,
11448         .set_cr3 = vmx_set_cr3,
11449         .set_cr4 = vmx_set_cr4,
11450         .set_efer = vmx_set_efer,
11451         .get_idt = vmx_get_idt,
11452         .set_idt = vmx_set_idt,
11453         .get_gdt = vmx_get_gdt,
11454         .set_gdt = vmx_set_gdt,
11455         .get_dr6 = vmx_get_dr6,
11456         .set_dr6 = vmx_set_dr6,
11457         .set_dr7 = vmx_set_dr7,
11458         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11459         .cache_reg = vmx_cache_reg,
11460         .get_rflags = vmx_get_rflags,
11461         .set_rflags = vmx_set_rflags,
11462
11463         .get_pkru = vmx_get_pkru,
11464
11465         .tlb_flush = vmx_flush_tlb,
11466
11467         .run = vmx_vcpu_run,
11468         .handle_exit = vmx_handle_exit,
11469         .skip_emulated_instruction = skip_emulated_instruction,
11470         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11471         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11472         .patch_hypercall = vmx_patch_hypercall,
11473         .set_irq = vmx_inject_irq,
11474         .set_nmi = vmx_inject_nmi,
11475         .queue_exception = vmx_queue_exception,
11476         .cancel_injection = vmx_cancel_injection,
11477         .interrupt_allowed = vmx_interrupt_allowed,
11478         .nmi_allowed = vmx_nmi_allowed,
11479         .get_nmi_mask = vmx_get_nmi_mask,
11480         .set_nmi_mask = vmx_set_nmi_mask,
11481         .enable_nmi_window = enable_nmi_window,
11482         .enable_irq_window = enable_irq_window,
11483         .update_cr8_intercept = update_cr8_intercept,
11484         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11485         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11486         .get_enable_apicv = vmx_get_enable_apicv,
11487         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11488         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11489         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11490         .hwapic_irr_update = vmx_hwapic_irr_update,
11491         .hwapic_isr_update = vmx_hwapic_isr_update,
11492         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11493         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11494
11495         .set_tss_addr = vmx_set_tss_addr,
11496         .get_tdp_level = get_ept_level,
11497         .get_mt_mask = vmx_get_mt_mask,
11498
11499         .get_exit_info = vmx_get_exit_info,
11500
11501         .get_lpage_level = vmx_get_lpage_level,
11502
11503         .cpuid_update = vmx_cpuid_update,
11504
11505         .rdtscp_supported = vmx_rdtscp_supported,
11506         .invpcid_supported = vmx_invpcid_supported,
11507
11508         .set_supported_cpuid = vmx_set_supported_cpuid,
11509
11510         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11511
11512         .write_tsc_offset = vmx_write_tsc_offset,
11513
11514         .set_tdp_cr3 = vmx_set_cr3,
11515
11516         .check_intercept = vmx_check_intercept,
11517         .handle_external_intr = vmx_handle_external_intr,
11518         .mpx_supported = vmx_mpx_supported,
11519         .xsaves_supported = vmx_xsaves_supported,
11520
11521         .check_nested_events = vmx_check_nested_events,
11522
11523         .sched_in = vmx_sched_in,
11524
11525         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11526         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11527         .flush_log_dirty = vmx_flush_log_dirty,
11528         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11529
11530         .pre_block = vmx_pre_block,
11531         .post_block = vmx_post_block,
11532
11533         .pmu_ops = &intel_pmu_ops,
11534
11535         .update_pi_irte = vmx_update_pi_irte,
11536
11537 #ifdef CONFIG_X86_64
11538         .set_hv_timer = vmx_set_hv_timer,
11539         .cancel_hv_timer = vmx_cancel_hv_timer,
11540 #endif
11541
11542         .setup_mce = vmx_setup_mce,
11543 };
11544
11545 static int __init vmx_init(void)
11546 {
11547         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11548                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11549         if (r)
11550                 return r;
11551
11552 #ifdef CONFIG_KEXEC_CORE
11553         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11554                            crash_vmclear_local_loaded_vmcss);
11555 #endif
11556
11557         return 0;
11558 }
11559
11560 static void __exit vmx_exit(void)
11561 {
11562 #ifdef CONFIG_KEXEC_CORE
11563         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11564         synchronize_rcu();
11565 #endif
11566
11567         kvm_exit();
11568 }
11569
11570 module_init(vmx_init)
11571 module_exit(vmx_exit)