2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
68 static bool __read_mostly enable_vpid = 1;
69 module_param_named(vpid, enable_vpid, bool, 0444);
71 static bool __read_mostly flexpriority_enabled = 1;
72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
74 static bool __read_mostly enable_ept = 1;
75 module_param_named(ept, enable_ept, bool, S_IRUGO);
77 static bool __read_mostly enable_unrestricted_guest = 1;
78 module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
81 static bool __read_mostly enable_ept_ad_bits = 1;
82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
84 static bool __read_mostly emulate_invalid_guest_state = true;
85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
87 static bool __read_mostly vmm_exclusive = 1;
88 module_param(vmm_exclusive, bool, S_IRUGO);
90 static bool __read_mostly fasteoi = 1;
91 module_param(fasteoi, bool, S_IRUGO);
93 static bool __read_mostly enable_apicv = 1;
94 module_param(enable_apicv, bool, S_IRUGO);
96 static bool __read_mostly enable_shadow_vmcs = 1;
97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested = 0;
104 module_param(nested, bool, S_IRUGO);
106 static u64 __read_mostly host_xss;
108 static bool __read_mostly enable_pml = 1;
109 module_param_named(pml, enable_pml, bool, S_IRUGO);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi;
115 static bool __read_mostly enable_preemption_timer = 1;
117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
137 * ple_gap: upper bound on the amount of time between two successive
138 * executions of PAUSE in a loop. Also indicate if ple enabled.
139 * According to test, this time is usually smaller than 128 cycles.
140 * ple_window: upper bound on the amount of time a guest is allowed to execute
141 * in a PAUSE loop. Tests indicate that most spinlocks are held for
142 * less than 2^12 cycles
143 * Time is measured based on a counter that runs at the same rate as the TSC,
144 * refer SDM volume 3b section 21.6.13 & 22.1.3.
146 #define KVM_VMX_DEFAULT_PLE_GAP 128
147 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
151 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
154 module_param(ple_gap, int, S_IRUGO);
156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
157 module_param(ple_window, int, S_IRUGO);
159 /* Default doubles per-vcpu window every exit. */
160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
161 module_param(ple_window_grow, int, S_IRUGO);
163 /* Default resets per-vcpu window every exit to ple_window. */
164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
165 module_param(ple_window_shrink, int, S_IRUGO);
167 /* Default is to compute the maximum so we can never overflow. */
168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
169 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
170 module_param(ple_window_max, int, S_IRUGO);
172 extern const ulong vmx_return;
174 #define NR_AUTOLOAD_MSRS 8
175 #define VMCS02_POOL_SIZE 1
184 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
185 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
186 * loaded on this CPU (so we can clear them if the CPU goes down).
192 struct list_head loaded_vmcss_on_cpu_link;
195 struct shared_msr_entry {
202 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
203 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
204 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
205 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
206 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
207 * More than one of these structures may exist, if L1 runs multiple L2 guests.
208 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
209 * underlying hardware which will be used to run L2.
210 * This structure is packed to ensure that its layout is identical across
211 * machines (necessary for live migration).
212 * If there are changes in this struct, VMCS12_REVISION must be changed.
214 typedef u64 natural_width;
215 struct __packed vmcs12 {
216 /* According to the Intel spec, a VMCS region must start with the
217 * following two fields. Then follow implementation-specific data.
222 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
223 u32 padding[7]; /* room for future expansion */
228 u64 vm_exit_msr_store_addr;
229 u64 vm_exit_msr_load_addr;
230 u64 vm_entry_msr_load_addr;
232 u64 virtual_apic_page_addr;
233 u64 apic_access_addr;
234 u64 posted_intr_desc_addr;
236 u64 eoi_exit_bitmap0;
237 u64 eoi_exit_bitmap1;
238 u64 eoi_exit_bitmap2;
239 u64 eoi_exit_bitmap3;
241 u64 guest_physical_address;
242 u64 vmcs_link_pointer;
243 u64 guest_ia32_debugctl;
246 u64 guest_ia32_perf_global_ctrl;
254 u64 host_ia32_perf_global_ctrl;
255 u64 padding64[8]; /* room for future expansion */
257 * To allow migration of L1 (complete with its L2 guests) between
258 * machines of different natural widths (32 or 64 bit), we cannot have
259 * unsigned long fields with no explict size. We use u64 (aliased
260 * natural_width) instead. Luckily, x86 is little-endian.
262 natural_width cr0_guest_host_mask;
263 natural_width cr4_guest_host_mask;
264 natural_width cr0_read_shadow;
265 natural_width cr4_read_shadow;
266 natural_width cr3_target_value0;
267 natural_width cr3_target_value1;
268 natural_width cr3_target_value2;
269 natural_width cr3_target_value3;
270 natural_width exit_qualification;
271 natural_width guest_linear_address;
272 natural_width guest_cr0;
273 natural_width guest_cr3;
274 natural_width guest_cr4;
275 natural_width guest_es_base;
276 natural_width guest_cs_base;
277 natural_width guest_ss_base;
278 natural_width guest_ds_base;
279 natural_width guest_fs_base;
280 natural_width guest_gs_base;
281 natural_width guest_ldtr_base;
282 natural_width guest_tr_base;
283 natural_width guest_gdtr_base;
284 natural_width guest_idtr_base;
285 natural_width guest_dr7;
286 natural_width guest_rsp;
287 natural_width guest_rip;
288 natural_width guest_rflags;
289 natural_width guest_pending_dbg_exceptions;
290 natural_width guest_sysenter_esp;
291 natural_width guest_sysenter_eip;
292 natural_width host_cr0;
293 natural_width host_cr3;
294 natural_width host_cr4;
295 natural_width host_fs_base;
296 natural_width host_gs_base;
297 natural_width host_tr_base;
298 natural_width host_gdtr_base;
299 natural_width host_idtr_base;
300 natural_width host_ia32_sysenter_esp;
301 natural_width host_ia32_sysenter_eip;
302 natural_width host_rsp;
303 natural_width host_rip;
304 natural_width paddingl[8]; /* room for future expansion */
305 u32 pin_based_vm_exec_control;
306 u32 cpu_based_vm_exec_control;
307 u32 exception_bitmap;
308 u32 page_fault_error_code_mask;
309 u32 page_fault_error_code_match;
310 u32 cr3_target_count;
311 u32 vm_exit_controls;
312 u32 vm_exit_msr_store_count;
313 u32 vm_exit_msr_load_count;
314 u32 vm_entry_controls;
315 u32 vm_entry_msr_load_count;
316 u32 vm_entry_intr_info_field;
317 u32 vm_entry_exception_error_code;
318 u32 vm_entry_instruction_len;
320 u32 secondary_vm_exec_control;
321 u32 vm_instruction_error;
323 u32 vm_exit_intr_info;
324 u32 vm_exit_intr_error_code;
325 u32 idt_vectoring_info_field;
326 u32 idt_vectoring_error_code;
327 u32 vm_exit_instruction_len;
328 u32 vmx_instruction_info;
335 u32 guest_ldtr_limit;
337 u32 guest_gdtr_limit;
338 u32 guest_idtr_limit;
339 u32 guest_es_ar_bytes;
340 u32 guest_cs_ar_bytes;
341 u32 guest_ss_ar_bytes;
342 u32 guest_ds_ar_bytes;
343 u32 guest_fs_ar_bytes;
344 u32 guest_gs_ar_bytes;
345 u32 guest_ldtr_ar_bytes;
346 u32 guest_tr_ar_bytes;
347 u32 guest_interruptibility_info;
348 u32 guest_activity_state;
349 u32 guest_sysenter_cs;
350 u32 host_ia32_sysenter_cs;
351 u32 vmx_preemption_timer_value;
352 u32 padding32[7]; /* room for future expansion */
353 u16 virtual_processor_id;
355 u16 guest_es_selector;
356 u16 guest_cs_selector;
357 u16 guest_ss_selector;
358 u16 guest_ds_selector;
359 u16 guest_fs_selector;
360 u16 guest_gs_selector;
361 u16 guest_ldtr_selector;
362 u16 guest_tr_selector;
363 u16 guest_intr_status;
364 u16 host_es_selector;
365 u16 host_cs_selector;
366 u16 host_ss_selector;
367 u16 host_ds_selector;
368 u16 host_fs_selector;
369 u16 host_gs_selector;
370 u16 host_tr_selector;
374 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
375 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
376 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
378 #define VMCS12_REVISION 0x11e57ed0
381 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
382 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
383 * current implementation, 4K are reserved to avoid future complications.
385 #define VMCS12_SIZE 0x1000
387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
389 struct list_head list;
391 struct loaded_vmcs vmcs02;
395 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
396 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
399 /* Has the level1 guest done vmxon? */
403 /* The guest-physical address of the current VMCS L1 keeps for L2 */
405 /* The host-usable pointer to the above */
406 struct page *current_vmcs12_page;
407 struct vmcs12 *current_vmcs12;
409 * Cache of the guest's VMCS, existing outside of guest memory.
410 * Loaded from guest memory during VMPTRLD. Flushed to guest
411 * memory during VMXOFF, VMCLEAR, VMPTRLD.
413 struct vmcs12 *cached_vmcs12;
414 struct vmcs *current_shadow_vmcs;
416 * Indicates if the shadow vmcs must be updated with the
417 * data hold by vmcs12
419 bool sync_shadow_vmcs;
421 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
422 struct list_head vmcs02_pool;
424 u64 vmcs01_tsc_offset;
425 bool change_vmcs01_virtual_x2apic_mode;
426 /* L2 must run next, and mustn't decide to exit to L1. */
427 bool nested_run_pending;
429 * Guest pages referred to in vmcs02 with host-physical pointers, so
430 * we must keep them pinned while L2 runs.
432 struct page *apic_access_page;
433 struct page *virtual_apic_page;
434 struct page *pi_desc_page;
435 struct pi_desc *pi_desc;
439 unsigned long *msr_bitmap;
441 struct hrtimer preemption_timer;
442 bool preemption_timer_expired;
444 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
450 u32 nested_vmx_procbased_ctls_low;
451 u32 nested_vmx_procbased_ctls_high;
452 u32 nested_vmx_true_procbased_ctls_low;
453 u32 nested_vmx_secondary_ctls_low;
454 u32 nested_vmx_secondary_ctls_high;
455 u32 nested_vmx_pinbased_ctls_low;
456 u32 nested_vmx_pinbased_ctls_high;
457 u32 nested_vmx_exit_ctls_low;
458 u32 nested_vmx_exit_ctls_high;
459 u32 nested_vmx_true_exit_ctls_low;
460 u32 nested_vmx_entry_ctls_low;
461 u32 nested_vmx_entry_ctls_high;
462 u32 nested_vmx_true_entry_ctls_low;
463 u32 nested_vmx_misc_low;
464 u32 nested_vmx_misc_high;
465 u32 nested_vmx_ept_caps;
466 u32 nested_vmx_vpid_caps;
469 #define POSTED_INTR_ON 0
470 #define POSTED_INTR_SN 1
472 /* Posted-Interrupt Descriptor */
474 u32 pir[8]; /* Posted interrupt requested */
477 /* bit 256 - Outstanding Notification */
479 /* bit 257 - Suppress Notification */
481 /* bit 271:258 - Reserved */
483 /* bit 279:272 - Notification Vector */
485 /* bit 287:280 - Reserved */
487 /* bit 319:288 - Notification Destination */
495 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
497 return test_and_set_bit(POSTED_INTR_ON,
498 (unsigned long *)&pi_desc->control);
501 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
503 return test_and_clear_bit(POSTED_INTR_ON,
504 (unsigned long *)&pi_desc->control);
507 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
509 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
512 static inline void pi_clear_sn(struct pi_desc *pi_desc)
514 return clear_bit(POSTED_INTR_SN,
515 (unsigned long *)&pi_desc->control);
518 static inline void pi_set_sn(struct pi_desc *pi_desc)
520 return set_bit(POSTED_INTR_SN,
521 (unsigned long *)&pi_desc->control);
524 static inline int pi_test_on(struct pi_desc *pi_desc)
526 return test_bit(POSTED_INTR_ON,
527 (unsigned long *)&pi_desc->control);
530 static inline int pi_test_sn(struct pi_desc *pi_desc)
532 return test_bit(POSTED_INTR_SN,
533 (unsigned long *)&pi_desc->control);
537 struct kvm_vcpu vcpu;
538 unsigned long host_rsp;
540 bool nmi_known_unmasked;
542 u32 idt_vectoring_info;
544 struct shared_msr_entry *guest_msrs;
547 unsigned long host_idt_base;
549 u64 msr_host_kernel_gs_base;
550 u64 msr_guest_kernel_gs_base;
552 u32 vm_entry_controls_shadow;
553 u32 vm_exit_controls_shadow;
555 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
556 * non-nested (L1) guest, it always points to vmcs01. For a nested
557 * guest (L2), it points to a different VMCS.
559 struct loaded_vmcs vmcs01;
560 struct loaded_vmcs *loaded_vmcs;
561 bool __launched; /* temporary, used in vmx_vcpu_run */
562 struct msr_autoload {
564 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
565 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
569 u16 fs_sel, gs_sel, ldt_sel;
573 int gs_ldt_reload_needed;
574 int fs_reload_needed;
575 u64 msr_host_bndcfgs;
576 unsigned long vmcs_host_cr4; /* May not match real cr4 */
581 struct kvm_segment segs[8];
584 u32 bitmask; /* 4 bits per segment (1 bit per field) */
585 struct kvm_save_segment {
593 bool emulation_required;
595 /* Support for vnmi-less CPUs */
596 int soft_vnmi_blocked;
598 s64 vnmi_blocked_time;
601 /* Posted interrupt descriptor */
602 struct pi_desc pi_desc;
604 /* Support for a guest hypervisor (nested VMX) */
605 struct nested_vmx nested;
607 /* Dynamic PLE window. */
609 bool ple_window_dirty;
611 /* Support for PML */
612 #define PML_ENTITY_NUM 512
615 /* apic deadline value in host tsc */
618 u64 current_tsc_ratio;
620 bool guest_pkru_valid;
625 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
626 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
627 * in msr_ia32_feature_control_valid_bits.
629 u64 msr_ia32_feature_control;
630 u64 msr_ia32_feature_control_valid_bits;
633 enum segment_cache_field {
642 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
644 return container_of(vcpu, struct vcpu_vmx, vcpu);
647 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
649 return &(to_vmx(vcpu)->pi_desc);
652 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
653 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
654 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
655 [number##_HIGH] = VMCS12_OFFSET(name)+4
658 static unsigned long shadow_read_only_fields[] = {
660 * We do NOT shadow fields that are modified when L0
661 * traps and emulates any vmx instruction (e.g. VMPTRLD,
662 * VMXON...) executed by L1.
663 * For example, VM_INSTRUCTION_ERROR is read
664 * by L1 if a vmx instruction fails (part of the error path).
665 * Note the code assumes this logic. If for some reason
666 * we start shadowing these fields then we need to
667 * force a shadow sync when L0 emulates vmx instructions
668 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
669 * by nested_vmx_failValid)
673 VM_EXIT_INSTRUCTION_LEN,
674 IDT_VECTORING_INFO_FIELD,
675 IDT_VECTORING_ERROR_CODE,
676 VM_EXIT_INTR_ERROR_CODE,
678 GUEST_LINEAR_ADDRESS,
679 GUEST_PHYSICAL_ADDRESS
681 static int max_shadow_read_only_fields =
682 ARRAY_SIZE(shadow_read_only_fields);
684 static unsigned long shadow_read_write_fields[] = {
691 GUEST_INTERRUPTIBILITY_INFO,
704 CPU_BASED_VM_EXEC_CONTROL,
705 VM_ENTRY_EXCEPTION_ERROR_CODE,
706 VM_ENTRY_INTR_INFO_FIELD,
707 VM_ENTRY_INSTRUCTION_LEN,
708 VM_ENTRY_EXCEPTION_ERROR_CODE,
714 static int max_shadow_read_write_fields =
715 ARRAY_SIZE(shadow_read_write_fields);
717 static const unsigned short vmcs_field_to_offset_table[] = {
718 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
719 FIELD(POSTED_INTR_NV, posted_intr_nv),
720 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
721 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
722 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
723 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
724 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
725 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
726 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
727 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
728 FIELD(GUEST_INTR_STATUS, guest_intr_status),
729 FIELD(HOST_ES_SELECTOR, host_es_selector),
730 FIELD(HOST_CS_SELECTOR, host_cs_selector),
731 FIELD(HOST_SS_SELECTOR, host_ss_selector),
732 FIELD(HOST_DS_SELECTOR, host_ds_selector),
733 FIELD(HOST_FS_SELECTOR, host_fs_selector),
734 FIELD(HOST_GS_SELECTOR, host_gs_selector),
735 FIELD(HOST_TR_SELECTOR, host_tr_selector),
736 FIELD64(IO_BITMAP_A, io_bitmap_a),
737 FIELD64(IO_BITMAP_B, io_bitmap_b),
738 FIELD64(MSR_BITMAP, msr_bitmap),
739 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
740 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
741 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
742 FIELD64(TSC_OFFSET, tsc_offset),
743 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
744 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
745 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
746 FIELD64(EPT_POINTER, ept_pointer),
747 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
748 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
749 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
750 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
751 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
752 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
753 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
754 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
755 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
756 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
757 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
758 FIELD64(GUEST_PDPTR0, guest_pdptr0),
759 FIELD64(GUEST_PDPTR1, guest_pdptr1),
760 FIELD64(GUEST_PDPTR2, guest_pdptr2),
761 FIELD64(GUEST_PDPTR3, guest_pdptr3),
762 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
763 FIELD64(HOST_IA32_PAT, host_ia32_pat),
764 FIELD64(HOST_IA32_EFER, host_ia32_efer),
765 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
766 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
767 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
768 FIELD(EXCEPTION_BITMAP, exception_bitmap),
769 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
770 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
771 FIELD(CR3_TARGET_COUNT, cr3_target_count),
772 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
773 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
774 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
775 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
776 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
777 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
778 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
779 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
780 FIELD(TPR_THRESHOLD, tpr_threshold),
781 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
782 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
783 FIELD(VM_EXIT_REASON, vm_exit_reason),
784 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
785 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
786 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
787 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
788 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
789 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
790 FIELD(GUEST_ES_LIMIT, guest_es_limit),
791 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
792 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
793 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
794 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
795 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
796 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
797 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
798 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
799 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
800 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
801 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
802 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
803 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
804 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
805 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
806 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
807 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
808 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
809 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
810 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
811 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
812 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
813 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
814 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
815 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
816 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
817 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
818 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
819 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
820 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
821 FIELD(EXIT_QUALIFICATION, exit_qualification),
822 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
823 FIELD(GUEST_CR0, guest_cr0),
824 FIELD(GUEST_CR3, guest_cr3),
825 FIELD(GUEST_CR4, guest_cr4),
826 FIELD(GUEST_ES_BASE, guest_es_base),
827 FIELD(GUEST_CS_BASE, guest_cs_base),
828 FIELD(GUEST_SS_BASE, guest_ss_base),
829 FIELD(GUEST_DS_BASE, guest_ds_base),
830 FIELD(GUEST_FS_BASE, guest_fs_base),
831 FIELD(GUEST_GS_BASE, guest_gs_base),
832 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
833 FIELD(GUEST_TR_BASE, guest_tr_base),
834 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
835 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
836 FIELD(GUEST_DR7, guest_dr7),
837 FIELD(GUEST_RSP, guest_rsp),
838 FIELD(GUEST_RIP, guest_rip),
839 FIELD(GUEST_RFLAGS, guest_rflags),
840 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
841 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
842 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
843 FIELD(HOST_CR0, host_cr0),
844 FIELD(HOST_CR3, host_cr3),
845 FIELD(HOST_CR4, host_cr4),
846 FIELD(HOST_FS_BASE, host_fs_base),
847 FIELD(HOST_GS_BASE, host_gs_base),
848 FIELD(HOST_TR_BASE, host_tr_base),
849 FIELD(HOST_GDTR_BASE, host_gdtr_base),
850 FIELD(HOST_IDTR_BASE, host_idtr_base),
851 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
852 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
853 FIELD(HOST_RSP, host_rsp),
854 FIELD(HOST_RIP, host_rip),
857 static inline short vmcs_field_to_offset(unsigned long field)
859 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
861 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
862 vmcs_field_to_offset_table[field] == 0)
865 return vmcs_field_to_offset_table[field];
868 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
870 return to_vmx(vcpu)->nested.cached_vmcs12;
873 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
875 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
876 if (is_error_page(page))
882 static void nested_release_page(struct page *page)
884 kvm_release_page_dirty(page);
887 static void nested_release_page_clean(struct page *page)
889 kvm_release_page_clean(page);
892 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
893 static u64 construct_eptp(unsigned long root_hpa);
894 static void kvm_cpu_vmxon(u64 addr);
895 static void kvm_cpu_vmxoff(void);
896 static bool vmx_xsaves_supported(void);
897 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
898 static void vmx_set_segment(struct kvm_vcpu *vcpu,
899 struct kvm_segment *var, int seg);
900 static void vmx_get_segment(struct kvm_vcpu *vcpu,
901 struct kvm_segment *var, int seg);
902 static bool guest_state_valid(struct kvm_vcpu *vcpu);
903 static u32 vmx_segment_access_rights(struct kvm_segment *var);
904 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
905 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
906 static int alloc_identity_pagetable(struct kvm *kvm);
908 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
909 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
911 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
912 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
914 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
915 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
918 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
919 * can find which vCPU should be waken up.
921 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
922 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
924 static unsigned long *vmx_io_bitmap_a;
925 static unsigned long *vmx_io_bitmap_b;
926 static unsigned long *vmx_msr_bitmap_legacy;
927 static unsigned long *vmx_msr_bitmap_longmode;
928 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
929 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
930 static unsigned long *vmx_msr_bitmap_legacy_x2apic_apicv_inactive;
931 static unsigned long *vmx_msr_bitmap_longmode_x2apic_apicv_inactive;
932 static unsigned long *vmx_vmread_bitmap;
933 static unsigned long *vmx_vmwrite_bitmap;
935 static bool cpu_has_load_ia32_efer;
936 static bool cpu_has_load_perf_global_ctrl;
938 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
939 static DEFINE_SPINLOCK(vmx_vpid_lock);
941 static struct vmcs_config {
946 u32 pin_based_exec_ctrl;
947 u32 cpu_based_exec_ctrl;
948 u32 cpu_based_2nd_exec_ctrl;
953 static struct vmx_capability {
958 #define VMX_SEGMENT_FIELD(seg) \
959 [VCPU_SREG_##seg] = { \
960 .selector = GUEST_##seg##_SELECTOR, \
961 .base = GUEST_##seg##_BASE, \
962 .limit = GUEST_##seg##_LIMIT, \
963 .ar_bytes = GUEST_##seg##_AR_BYTES, \
966 static const struct kvm_vmx_segment_field {
971 } kvm_vmx_segment_fields[] = {
972 VMX_SEGMENT_FIELD(CS),
973 VMX_SEGMENT_FIELD(DS),
974 VMX_SEGMENT_FIELD(ES),
975 VMX_SEGMENT_FIELD(FS),
976 VMX_SEGMENT_FIELD(GS),
977 VMX_SEGMENT_FIELD(SS),
978 VMX_SEGMENT_FIELD(TR),
979 VMX_SEGMENT_FIELD(LDTR),
982 static u64 host_efer;
984 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
987 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
988 * away by decrementing the array size.
990 static const u32 vmx_msr_index[] = {
992 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
994 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
997 static inline bool is_exception_n(u32 intr_info, u8 vector)
999 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1000 INTR_INFO_VALID_MASK)) ==
1001 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1004 static inline bool is_debug(u32 intr_info)
1006 return is_exception_n(intr_info, DB_VECTOR);
1009 static inline bool is_breakpoint(u32 intr_info)
1011 return is_exception_n(intr_info, BP_VECTOR);
1014 static inline bool is_page_fault(u32 intr_info)
1016 return is_exception_n(intr_info, PF_VECTOR);
1019 static inline bool is_no_device(u32 intr_info)
1021 return is_exception_n(intr_info, NM_VECTOR);
1024 static inline bool is_invalid_opcode(u32 intr_info)
1026 return is_exception_n(intr_info, UD_VECTOR);
1029 static inline bool is_external_interrupt(u32 intr_info)
1031 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1032 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1035 static inline bool is_machine_check(u32 intr_info)
1037 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038 INTR_INFO_VALID_MASK)) ==
1039 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1042 static inline bool cpu_has_vmx_msr_bitmap(void)
1044 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1047 static inline bool cpu_has_vmx_tpr_shadow(void)
1049 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1052 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1054 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1057 static inline bool cpu_has_secondary_exec_ctrls(void)
1059 return vmcs_config.cpu_based_exec_ctrl &
1060 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1063 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1065 return vmcs_config.cpu_based_2nd_exec_ctrl &
1066 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1069 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1071 return vmcs_config.cpu_based_2nd_exec_ctrl &
1072 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1075 static inline bool cpu_has_vmx_apic_register_virt(void)
1077 return vmcs_config.cpu_based_2nd_exec_ctrl &
1078 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1081 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1083 return vmcs_config.cpu_based_2nd_exec_ctrl &
1084 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1088 * Comment's format: document - errata name - stepping - processor name.
1090 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1092 static u32 vmx_preemption_cpu_tfms[] = {
1093 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1095 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1096 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1097 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1099 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1101 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1102 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1104 * 320767.pdf - AAP86 - B1 -
1105 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1108 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1110 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1112 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1114 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1115 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1116 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1120 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1122 u32 eax = cpuid_eax(0x00000001), i;
1124 /* Clear the reserved bits */
1125 eax &= ~(0x3U << 14 | 0xfU << 28);
1126 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1127 if (eax == vmx_preemption_cpu_tfms[i])
1133 static inline bool cpu_has_vmx_preemption_timer(void)
1135 return vmcs_config.pin_based_exec_ctrl &
1136 PIN_BASED_VMX_PREEMPTION_TIMER;
1139 static inline bool cpu_has_vmx_posted_intr(void)
1141 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1142 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1145 static inline bool cpu_has_vmx_apicv(void)
1147 return cpu_has_vmx_apic_register_virt() &&
1148 cpu_has_vmx_virtual_intr_delivery() &&
1149 cpu_has_vmx_posted_intr();
1152 static inline bool cpu_has_vmx_flexpriority(void)
1154 return cpu_has_vmx_tpr_shadow() &&
1155 cpu_has_vmx_virtualize_apic_accesses();
1158 static inline bool cpu_has_vmx_ept_execute_only(void)
1160 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1163 static inline bool cpu_has_vmx_ept_2m_page(void)
1165 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1168 static inline bool cpu_has_vmx_ept_1g_page(void)
1170 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1173 static inline bool cpu_has_vmx_ept_4levels(void)
1175 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1178 static inline bool cpu_has_vmx_ept_ad_bits(void)
1180 return vmx_capability.ept & VMX_EPT_AD_BIT;
1183 static inline bool cpu_has_vmx_invept_context(void)
1185 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1188 static inline bool cpu_has_vmx_invept_global(void)
1190 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1193 static inline bool cpu_has_vmx_invvpid_single(void)
1195 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1198 static inline bool cpu_has_vmx_invvpid_global(void)
1200 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1203 static inline bool cpu_has_vmx_ept(void)
1205 return vmcs_config.cpu_based_2nd_exec_ctrl &
1206 SECONDARY_EXEC_ENABLE_EPT;
1209 static inline bool cpu_has_vmx_unrestricted_guest(void)
1211 return vmcs_config.cpu_based_2nd_exec_ctrl &
1212 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1215 static inline bool cpu_has_vmx_ple(void)
1217 return vmcs_config.cpu_based_2nd_exec_ctrl &
1218 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1221 static inline bool cpu_has_vmx_basic_inout(void)
1223 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1226 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1228 return flexpriority_enabled && lapic_in_kernel(vcpu);
1231 static inline bool cpu_has_vmx_vpid(void)
1233 return vmcs_config.cpu_based_2nd_exec_ctrl &
1234 SECONDARY_EXEC_ENABLE_VPID;
1237 static inline bool cpu_has_vmx_rdtscp(void)
1239 return vmcs_config.cpu_based_2nd_exec_ctrl &
1240 SECONDARY_EXEC_RDTSCP;
1243 static inline bool cpu_has_vmx_invpcid(void)
1245 return vmcs_config.cpu_based_2nd_exec_ctrl &
1246 SECONDARY_EXEC_ENABLE_INVPCID;
1249 static inline bool cpu_has_virtual_nmis(void)
1251 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1254 static inline bool cpu_has_vmx_wbinvd_exit(void)
1256 return vmcs_config.cpu_based_2nd_exec_ctrl &
1257 SECONDARY_EXEC_WBINVD_EXITING;
1260 static inline bool cpu_has_vmx_shadow_vmcs(void)
1263 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1264 /* check if the cpu supports writing r/o exit information fields */
1265 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1268 return vmcs_config.cpu_based_2nd_exec_ctrl &
1269 SECONDARY_EXEC_SHADOW_VMCS;
1272 static inline bool cpu_has_vmx_pml(void)
1274 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1277 static inline bool cpu_has_vmx_tsc_scaling(void)
1279 return vmcs_config.cpu_based_2nd_exec_ctrl &
1280 SECONDARY_EXEC_TSC_SCALING;
1283 static inline bool report_flexpriority(void)
1285 return flexpriority_enabled;
1288 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1290 return vmcs12->cpu_based_vm_exec_control & bit;
1293 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1295 return (vmcs12->cpu_based_vm_exec_control &
1296 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1297 (vmcs12->secondary_vm_exec_control & bit);
1300 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1302 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1305 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1307 return vmcs12->pin_based_vm_exec_control &
1308 PIN_BASED_VMX_PREEMPTION_TIMER;
1311 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1313 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1316 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1318 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1319 vmx_xsaves_supported();
1322 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1324 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1327 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1329 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1332 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1334 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1337 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1339 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1342 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1344 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1347 static inline bool is_exception(u32 intr_info)
1349 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1350 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1353 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1355 unsigned long exit_qualification);
1356 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1357 struct vmcs12 *vmcs12,
1358 u32 reason, unsigned long qualification);
1360 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1364 for (i = 0; i < vmx->nmsrs; ++i)
1365 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1370 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1376 } operand = { vpid, 0, gva };
1378 asm volatile (__ex(ASM_VMX_INVVPID)
1379 /* CF==1 or ZF==1 --> rc = -1 */
1380 "; ja 1f ; ud2 ; 1:"
1381 : : "a"(&operand), "c"(ext) : "cc", "memory");
1384 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1388 } operand = {eptp, gpa};
1390 asm volatile (__ex(ASM_VMX_INVEPT)
1391 /* CF==1 or ZF==1 --> rc = -1 */
1392 "; ja 1f ; ud2 ; 1:\n"
1393 : : "a" (&operand), "c" (ext) : "cc", "memory");
1396 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1400 i = __find_msr_index(vmx, msr);
1402 return &vmx->guest_msrs[i];
1406 static void vmcs_clear(struct vmcs *vmcs)
1408 u64 phys_addr = __pa(vmcs);
1411 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1412 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1415 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1419 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1421 vmcs_clear(loaded_vmcs->vmcs);
1422 loaded_vmcs->cpu = -1;
1423 loaded_vmcs->launched = 0;
1426 static void vmcs_load(struct vmcs *vmcs)
1428 u64 phys_addr = __pa(vmcs);
1431 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1432 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1435 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1439 #ifdef CONFIG_KEXEC_CORE
1441 * This bitmap is used to indicate whether the vmclear
1442 * operation is enabled on all cpus. All disabled by
1445 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1447 static inline void crash_enable_local_vmclear(int cpu)
1449 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1452 static inline void crash_disable_local_vmclear(int cpu)
1454 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1457 static inline int crash_local_vmclear_enabled(int cpu)
1459 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1462 static void crash_vmclear_local_loaded_vmcss(void)
1464 int cpu = raw_smp_processor_id();
1465 struct loaded_vmcs *v;
1467 if (!crash_local_vmclear_enabled(cpu))
1470 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1471 loaded_vmcss_on_cpu_link)
1472 vmcs_clear(v->vmcs);
1475 static inline void crash_enable_local_vmclear(int cpu) { }
1476 static inline void crash_disable_local_vmclear(int cpu) { }
1477 #endif /* CONFIG_KEXEC_CORE */
1479 static void __loaded_vmcs_clear(void *arg)
1481 struct loaded_vmcs *loaded_vmcs = arg;
1482 int cpu = raw_smp_processor_id();
1484 if (loaded_vmcs->cpu != cpu)
1485 return; /* vcpu migration can race with cpu offline */
1486 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1487 per_cpu(current_vmcs, cpu) = NULL;
1488 crash_disable_local_vmclear(cpu);
1489 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1492 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1493 * is before setting loaded_vmcs->vcpu to -1 which is done in
1494 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1495 * then adds the vmcs into percpu list before it is deleted.
1499 loaded_vmcs_init(loaded_vmcs);
1500 crash_enable_local_vmclear(cpu);
1503 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1505 int cpu = loaded_vmcs->cpu;
1508 smp_call_function_single(cpu,
1509 __loaded_vmcs_clear, loaded_vmcs, 1);
1512 static inline void vpid_sync_vcpu_single(int vpid)
1517 if (cpu_has_vmx_invvpid_single())
1518 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1521 static inline void vpid_sync_vcpu_global(void)
1523 if (cpu_has_vmx_invvpid_global())
1524 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1527 static inline void vpid_sync_context(int vpid)
1529 if (cpu_has_vmx_invvpid_single())
1530 vpid_sync_vcpu_single(vpid);
1532 vpid_sync_vcpu_global();
1535 static inline void ept_sync_global(void)
1537 if (cpu_has_vmx_invept_global())
1538 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1541 static inline void ept_sync_context(u64 eptp)
1544 if (cpu_has_vmx_invept_context())
1545 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1551 static __always_inline void vmcs_check16(unsigned long field)
1553 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1554 "16-bit accessor invalid for 64-bit field");
1555 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1556 "16-bit accessor invalid for 64-bit high field");
1557 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1558 "16-bit accessor invalid for 32-bit high field");
1559 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1560 "16-bit accessor invalid for natural width field");
1563 static __always_inline void vmcs_check32(unsigned long field)
1565 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1566 "32-bit accessor invalid for 16-bit field");
1567 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1568 "32-bit accessor invalid for natural width field");
1571 static __always_inline void vmcs_check64(unsigned long field)
1573 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1574 "64-bit accessor invalid for 16-bit field");
1575 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1576 "64-bit accessor invalid for 64-bit high field");
1577 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1578 "64-bit accessor invalid for 32-bit field");
1579 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1580 "64-bit accessor invalid for natural width field");
1583 static __always_inline void vmcs_checkl(unsigned long field)
1585 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1586 "Natural width accessor invalid for 16-bit field");
1587 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1588 "Natural width accessor invalid for 64-bit field");
1589 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1590 "Natural width accessor invalid for 64-bit high field");
1591 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1592 "Natural width accessor invalid for 32-bit field");
1595 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1597 unsigned long value;
1599 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1600 : "=a"(value) : "d"(field) : "cc");
1604 static __always_inline u16 vmcs_read16(unsigned long field)
1606 vmcs_check16(field);
1607 return __vmcs_readl(field);
1610 static __always_inline u32 vmcs_read32(unsigned long field)
1612 vmcs_check32(field);
1613 return __vmcs_readl(field);
1616 static __always_inline u64 vmcs_read64(unsigned long field)
1618 vmcs_check64(field);
1619 #ifdef CONFIG_X86_64
1620 return __vmcs_readl(field);
1622 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1626 static __always_inline unsigned long vmcs_readl(unsigned long field)
1629 return __vmcs_readl(field);
1632 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1634 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1635 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1639 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1643 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1644 : "=q"(error) : "a"(value), "d"(field) : "cc");
1645 if (unlikely(error))
1646 vmwrite_error(field, value);
1649 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1651 vmcs_check16(field);
1652 __vmcs_writel(field, value);
1655 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1657 vmcs_check32(field);
1658 __vmcs_writel(field, value);
1661 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1663 vmcs_check64(field);
1664 __vmcs_writel(field, value);
1665 #ifndef CONFIG_X86_64
1667 __vmcs_writel(field+1, value >> 32);
1671 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1674 __vmcs_writel(field, value);
1677 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1679 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1680 "vmcs_clear_bits does not support 64-bit fields");
1681 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1684 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1686 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1687 "vmcs_set_bits does not support 64-bit fields");
1688 __vmcs_writel(field, __vmcs_readl(field) | mask);
1691 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1693 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1696 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1698 vmcs_write32(VM_ENTRY_CONTROLS, val);
1699 vmx->vm_entry_controls_shadow = val;
1702 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1704 if (vmx->vm_entry_controls_shadow != val)
1705 vm_entry_controls_init(vmx, val);
1708 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1710 return vmx->vm_entry_controls_shadow;
1714 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1716 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1719 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1721 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1724 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1726 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1729 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1731 vmcs_write32(VM_EXIT_CONTROLS, val);
1732 vmx->vm_exit_controls_shadow = val;
1735 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1737 if (vmx->vm_exit_controls_shadow != val)
1738 vm_exit_controls_init(vmx, val);
1741 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1743 return vmx->vm_exit_controls_shadow;
1747 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1749 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1752 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1754 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1757 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1759 vmx->segment_cache.bitmask = 0;
1762 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1766 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1768 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1769 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1770 vmx->segment_cache.bitmask = 0;
1772 ret = vmx->segment_cache.bitmask & mask;
1773 vmx->segment_cache.bitmask |= mask;
1777 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1779 u16 *p = &vmx->segment_cache.seg[seg].selector;
1781 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1782 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1786 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1788 ulong *p = &vmx->segment_cache.seg[seg].base;
1790 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1791 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1795 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1797 u32 *p = &vmx->segment_cache.seg[seg].limit;
1799 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1800 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1804 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1806 u32 *p = &vmx->segment_cache.seg[seg].ar;
1808 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1809 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1813 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1817 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1818 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1819 if ((vcpu->guest_debug &
1820 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1821 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1822 eb |= 1u << BP_VECTOR;
1823 if (to_vmx(vcpu)->rmode.vm86_active)
1826 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1827 if (vcpu->fpu_active)
1828 eb &= ~(1u << NM_VECTOR);
1830 /* When we are running a nested L2 guest and L1 specified for it a
1831 * certain exception bitmap, we must trap the same exceptions and pass
1832 * them to L1. When running L2, we will only handle the exceptions
1833 * specified above if L1 did not want them.
1835 if (is_guest_mode(vcpu))
1836 eb |= get_vmcs12(vcpu)->exception_bitmap;
1838 vmcs_write32(EXCEPTION_BITMAP, eb);
1841 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1842 unsigned long entry, unsigned long exit)
1844 vm_entry_controls_clearbit(vmx, entry);
1845 vm_exit_controls_clearbit(vmx, exit);
1848 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1851 struct msr_autoload *m = &vmx->msr_autoload;
1855 if (cpu_has_load_ia32_efer) {
1856 clear_atomic_switch_msr_special(vmx,
1857 VM_ENTRY_LOAD_IA32_EFER,
1858 VM_EXIT_LOAD_IA32_EFER);
1862 case MSR_CORE_PERF_GLOBAL_CTRL:
1863 if (cpu_has_load_perf_global_ctrl) {
1864 clear_atomic_switch_msr_special(vmx,
1865 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1866 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1872 for (i = 0; i < m->nr; ++i)
1873 if (m->guest[i].index == msr)
1879 m->guest[i] = m->guest[m->nr];
1880 m->host[i] = m->host[m->nr];
1881 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1882 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1885 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1886 unsigned long entry, unsigned long exit,
1887 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1888 u64 guest_val, u64 host_val)
1890 vmcs_write64(guest_val_vmcs, guest_val);
1891 vmcs_write64(host_val_vmcs, host_val);
1892 vm_entry_controls_setbit(vmx, entry);
1893 vm_exit_controls_setbit(vmx, exit);
1896 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1897 u64 guest_val, u64 host_val)
1900 struct msr_autoload *m = &vmx->msr_autoload;
1904 if (cpu_has_load_ia32_efer) {
1905 add_atomic_switch_msr_special(vmx,
1906 VM_ENTRY_LOAD_IA32_EFER,
1907 VM_EXIT_LOAD_IA32_EFER,
1910 guest_val, host_val);
1914 case MSR_CORE_PERF_GLOBAL_CTRL:
1915 if (cpu_has_load_perf_global_ctrl) {
1916 add_atomic_switch_msr_special(vmx,
1917 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1918 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1919 GUEST_IA32_PERF_GLOBAL_CTRL,
1920 HOST_IA32_PERF_GLOBAL_CTRL,
1921 guest_val, host_val);
1925 case MSR_IA32_PEBS_ENABLE:
1926 /* PEBS needs a quiescent period after being disabled (to write
1927 * a record). Disabling PEBS through VMX MSR swapping doesn't
1928 * provide that period, so a CPU could write host's record into
1931 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1934 for (i = 0; i < m->nr; ++i)
1935 if (m->guest[i].index == msr)
1938 if (i == NR_AUTOLOAD_MSRS) {
1939 printk_once(KERN_WARNING "Not enough msr switch entries. "
1940 "Can't add msr %x\n", msr);
1942 } else if (i == m->nr) {
1944 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1945 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1948 m->guest[i].index = msr;
1949 m->guest[i].value = guest_val;
1950 m->host[i].index = msr;
1951 m->host[i].value = host_val;
1954 static void reload_tss(void)
1957 * VT restores TR but not its size. Useless.
1959 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1960 struct desc_struct *descs;
1962 descs = (void *)gdt->address;
1963 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1967 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1969 u64 guest_efer = vmx->vcpu.arch.efer;
1970 u64 ignore_bits = 0;
1974 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1975 * host CPUID is more efficient than testing guest CPUID
1976 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1978 if (boot_cpu_has(X86_FEATURE_SMEP))
1979 guest_efer |= EFER_NX;
1980 else if (!(guest_efer & EFER_NX))
1981 ignore_bits |= EFER_NX;
1985 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1987 ignore_bits |= EFER_SCE;
1988 #ifdef CONFIG_X86_64
1989 ignore_bits |= EFER_LMA | EFER_LME;
1990 /* SCE is meaningful only in long mode on Intel */
1991 if (guest_efer & EFER_LMA)
1992 ignore_bits &= ~(u64)EFER_SCE;
1995 clear_atomic_switch_msr(vmx, MSR_EFER);
1998 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1999 * On CPUs that support "load IA32_EFER", always switch EFER
2000 * atomically, since it's faster than switching it manually.
2002 if (cpu_has_load_ia32_efer ||
2003 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2004 if (!(guest_efer & EFER_LMA))
2005 guest_efer &= ~EFER_LME;
2006 if (guest_efer != host_efer)
2007 add_atomic_switch_msr(vmx, MSR_EFER,
2008 guest_efer, host_efer);
2011 guest_efer &= ~ignore_bits;
2012 guest_efer |= host_efer & ignore_bits;
2014 vmx->guest_msrs[efer_offset].data = guest_efer;
2015 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2021 static unsigned long segment_base(u16 selector)
2023 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2024 struct desc_struct *d;
2025 unsigned long table_base;
2028 if (!(selector & ~3))
2031 table_base = gdt->address;
2033 if (selector & 4) { /* from ldt */
2034 u16 ldt_selector = kvm_read_ldt();
2036 if (!(ldt_selector & ~3))
2039 table_base = segment_base(ldt_selector);
2041 d = (struct desc_struct *)(table_base + (selector & ~7));
2042 v = get_desc_base(d);
2043 #ifdef CONFIG_X86_64
2044 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2045 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2050 static inline unsigned long kvm_read_tr_base(void)
2053 asm("str %0" : "=g"(tr));
2054 return segment_base(tr);
2057 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2059 struct vcpu_vmx *vmx = to_vmx(vcpu);
2062 if (vmx->host_state.loaded)
2065 vmx->host_state.loaded = 1;
2067 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2068 * allow segment selectors with cpl > 0 or ti == 1.
2070 vmx->host_state.ldt_sel = kvm_read_ldt();
2071 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2072 savesegment(fs, vmx->host_state.fs_sel);
2073 if (!(vmx->host_state.fs_sel & 7)) {
2074 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2075 vmx->host_state.fs_reload_needed = 0;
2077 vmcs_write16(HOST_FS_SELECTOR, 0);
2078 vmx->host_state.fs_reload_needed = 1;
2080 savesegment(gs, vmx->host_state.gs_sel);
2081 if (!(vmx->host_state.gs_sel & 7))
2082 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2084 vmcs_write16(HOST_GS_SELECTOR, 0);
2085 vmx->host_state.gs_ldt_reload_needed = 1;
2088 #ifdef CONFIG_X86_64
2089 savesegment(ds, vmx->host_state.ds_sel);
2090 savesegment(es, vmx->host_state.es_sel);
2093 #ifdef CONFIG_X86_64
2094 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2095 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2097 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2098 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2101 #ifdef CONFIG_X86_64
2102 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2103 if (is_long_mode(&vmx->vcpu))
2104 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2106 if (boot_cpu_has(X86_FEATURE_MPX))
2107 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2108 for (i = 0; i < vmx->save_nmsrs; ++i)
2109 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2110 vmx->guest_msrs[i].data,
2111 vmx->guest_msrs[i].mask);
2114 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2116 if (!vmx->host_state.loaded)
2119 ++vmx->vcpu.stat.host_state_reload;
2120 vmx->host_state.loaded = 0;
2121 #ifdef CONFIG_X86_64
2122 if (is_long_mode(&vmx->vcpu))
2123 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2125 if (vmx->host_state.gs_ldt_reload_needed) {
2126 kvm_load_ldt(vmx->host_state.ldt_sel);
2127 #ifdef CONFIG_X86_64
2128 load_gs_index(vmx->host_state.gs_sel);
2130 loadsegment(gs, vmx->host_state.gs_sel);
2133 if (vmx->host_state.fs_reload_needed)
2134 loadsegment(fs, vmx->host_state.fs_sel);
2135 #ifdef CONFIG_X86_64
2136 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2137 loadsegment(ds, vmx->host_state.ds_sel);
2138 loadsegment(es, vmx->host_state.es_sel);
2142 #ifdef CONFIG_X86_64
2143 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2145 if (vmx->host_state.msr_host_bndcfgs)
2146 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2148 * If the FPU is not active (through the host task or
2149 * the guest vcpu), then restore the cr0.TS bit.
2151 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2153 load_gdt(this_cpu_ptr(&host_gdt));
2156 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2159 __vmx_load_host_state(vmx);
2163 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2165 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2166 struct pi_desc old, new;
2169 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2170 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2171 !kvm_vcpu_apicv_active(vcpu))
2175 old.control = new.control = pi_desc->control;
2178 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2179 * are two possible cases:
2180 * 1. After running 'pre_block', context switch
2181 * happened. For this case, 'sn' was set in
2182 * vmx_vcpu_put(), so we need to clear it here.
2183 * 2. After running 'pre_block', we were blocked,
2184 * and woken up by some other guy. For this case,
2185 * we don't need to do anything, 'pi_post_block'
2186 * will do everything for us. However, we cannot
2187 * check whether it is case #1 or case #2 here
2188 * (maybe, not needed), so we also clear sn here,
2189 * I think it is not a big deal.
2191 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2192 if (vcpu->cpu != cpu) {
2193 dest = cpu_physical_id(cpu);
2195 if (x2apic_enabled())
2198 new.ndst = (dest << 8) & 0xFF00;
2201 /* set 'NV' to 'notification vector' */
2202 new.nv = POSTED_INTR_VECTOR;
2205 /* Allow posting non-urgent interrupts */
2207 } while (cmpxchg(&pi_desc->control, old.control,
2208 new.control) != old.control);
2211 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2213 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2214 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2218 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2219 * vcpu mutex is already taken.
2221 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2223 struct vcpu_vmx *vmx = to_vmx(vcpu);
2224 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2225 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2228 kvm_cpu_vmxon(phys_addr);
2229 else if (!already_loaded)
2230 loaded_vmcs_clear(vmx->loaded_vmcs);
2232 if (!already_loaded) {
2233 local_irq_disable();
2234 crash_disable_local_vmclear(cpu);
2237 * Read loaded_vmcs->cpu should be before fetching
2238 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2239 * See the comments in __loaded_vmcs_clear().
2243 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2244 &per_cpu(loaded_vmcss_on_cpu, cpu));
2245 crash_enable_local_vmclear(cpu);
2249 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2250 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2251 vmcs_load(vmx->loaded_vmcs->vmcs);
2254 if (!already_loaded) {
2255 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2256 unsigned long sysenter_esp;
2258 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2261 * Linux uses per-cpu TSS and GDT, so set these when switching
2264 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2265 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2267 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2268 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2270 vmx->loaded_vmcs->cpu = cpu;
2273 /* Setup TSC multiplier */
2274 if (kvm_has_tsc_control &&
2275 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2276 decache_tsc_multiplier(vmx);
2278 vmx_vcpu_pi_load(vcpu, cpu);
2279 vmx->host_pkru = read_pkru();
2282 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2284 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2286 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2287 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2288 !kvm_vcpu_apicv_active(vcpu))
2291 /* Set SN when the vCPU is preempted */
2292 if (vcpu->preempted)
2296 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2298 vmx_vcpu_pi_put(vcpu);
2300 __vmx_load_host_state(to_vmx(vcpu));
2301 if (!vmm_exclusive) {
2302 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2308 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2312 if (vcpu->fpu_active)
2314 vcpu->fpu_active = 1;
2315 cr0 = vmcs_readl(GUEST_CR0);
2316 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2317 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2318 vmcs_writel(GUEST_CR0, cr0);
2319 update_exception_bitmap(vcpu);
2320 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2321 if (is_guest_mode(vcpu))
2322 vcpu->arch.cr0_guest_owned_bits &=
2323 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2324 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2327 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2330 * Return the cr0 value that a nested guest would read. This is a combination
2331 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2332 * its hypervisor (cr0_read_shadow).
2334 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2336 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2337 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2339 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2341 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2342 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2345 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2347 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2348 * set this *before* calling this function.
2350 vmx_decache_cr0_guest_bits(vcpu);
2351 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2352 update_exception_bitmap(vcpu);
2353 vcpu->arch.cr0_guest_owned_bits = 0;
2354 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2355 if (is_guest_mode(vcpu)) {
2357 * L1's specified read shadow might not contain the TS bit,
2358 * so now that we turned on shadowing of this bit, we need to
2359 * set this bit of the shadow. Like in nested_vmx_run we need
2360 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2361 * up-to-date here because we just decached cr0.TS (and we'll
2362 * only update vmcs12->guest_cr0 on nested exit).
2364 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2365 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2366 (vcpu->arch.cr0 & X86_CR0_TS);
2367 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2369 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2372 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2374 unsigned long rflags, save_rflags;
2376 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2377 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2378 rflags = vmcs_readl(GUEST_RFLAGS);
2379 if (to_vmx(vcpu)->rmode.vm86_active) {
2380 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2381 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2382 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2384 to_vmx(vcpu)->rflags = rflags;
2386 return to_vmx(vcpu)->rflags;
2389 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2391 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2392 to_vmx(vcpu)->rflags = rflags;
2393 if (to_vmx(vcpu)->rmode.vm86_active) {
2394 to_vmx(vcpu)->rmode.save_rflags = rflags;
2395 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2397 vmcs_writel(GUEST_RFLAGS, rflags);
2400 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2402 return to_vmx(vcpu)->guest_pkru;
2405 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2407 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2410 if (interruptibility & GUEST_INTR_STATE_STI)
2411 ret |= KVM_X86_SHADOW_INT_STI;
2412 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2413 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2418 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2420 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2421 u32 interruptibility = interruptibility_old;
2423 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2425 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2426 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2427 else if (mask & KVM_X86_SHADOW_INT_STI)
2428 interruptibility |= GUEST_INTR_STATE_STI;
2430 if ((interruptibility != interruptibility_old))
2431 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2434 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2438 rip = kvm_rip_read(vcpu);
2439 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2440 kvm_rip_write(vcpu, rip);
2442 /* skipping an emulated instruction also counts */
2443 vmx_set_interrupt_shadow(vcpu, 0);
2447 * KVM wants to inject page-faults which it got to the guest. This function
2448 * checks whether in a nested guest, we need to inject them to L1 or L2.
2450 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2452 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2454 if (!(vmcs12->exception_bitmap & (1u << nr)))
2457 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2458 vmcs_read32(VM_EXIT_INTR_INFO),
2459 vmcs_readl(EXIT_QUALIFICATION));
2463 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2464 bool has_error_code, u32 error_code,
2467 struct vcpu_vmx *vmx = to_vmx(vcpu);
2468 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2470 if (!reinject && is_guest_mode(vcpu) &&
2471 nested_vmx_check_exception(vcpu, nr))
2474 if (has_error_code) {
2475 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2476 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2479 if (vmx->rmode.vm86_active) {
2481 if (kvm_exception_is_soft(nr))
2482 inc_eip = vcpu->arch.event_exit_inst_len;
2483 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2484 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2488 if (kvm_exception_is_soft(nr)) {
2489 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2490 vmx->vcpu.arch.event_exit_inst_len);
2491 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2493 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2495 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2498 static bool vmx_rdtscp_supported(void)
2500 return cpu_has_vmx_rdtscp();
2503 static bool vmx_invpcid_supported(void)
2505 return cpu_has_vmx_invpcid() && enable_ept;
2509 * Swap MSR entry in host/guest MSR entry array.
2511 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2513 struct shared_msr_entry tmp;
2515 tmp = vmx->guest_msrs[to];
2516 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2517 vmx->guest_msrs[from] = tmp;
2520 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2522 unsigned long *msr_bitmap;
2524 if (is_guest_mode(vcpu))
2525 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2526 else if (cpu_has_secondary_exec_ctrls() &&
2527 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2528 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2529 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2530 if (is_long_mode(vcpu))
2531 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2533 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2535 if (is_long_mode(vcpu))
2536 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv_inactive;
2538 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv_inactive;
2541 if (is_long_mode(vcpu))
2542 msr_bitmap = vmx_msr_bitmap_longmode;
2544 msr_bitmap = vmx_msr_bitmap_legacy;
2547 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2551 * Set up the vmcs to automatically save and restore system
2552 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2553 * mode, as fiddling with msrs is very expensive.
2555 static void setup_msrs(struct vcpu_vmx *vmx)
2557 int save_nmsrs, index;
2560 #ifdef CONFIG_X86_64
2561 if (is_long_mode(&vmx->vcpu)) {
2562 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2564 move_msr_up(vmx, index, save_nmsrs++);
2565 index = __find_msr_index(vmx, MSR_LSTAR);
2567 move_msr_up(vmx, index, save_nmsrs++);
2568 index = __find_msr_index(vmx, MSR_CSTAR);
2570 move_msr_up(vmx, index, save_nmsrs++);
2571 index = __find_msr_index(vmx, MSR_TSC_AUX);
2572 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2573 move_msr_up(vmx, index, save_nmsrs++);
2575 * MSR_STAR is only needed on long mode guests, and only
2576 * if efer.sce is enabled.
2578 index = __find_msr_index(vmx, MSR_STAR);
2579 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2580 move_msr_up(vmx, index, save_nmsrs++);
2583 index = __find_msr_index(vmx, MSR_EFER);
2584 if (index >= 0 && update_transition_efer(vmx, index))
2585 move_msr_up(vmx, index, save_nmsrs++);
2587 vmx->save_nmsrs = save_nmsrs;
2589 if (cpu_has_vmx_msr_bitmap())
2590 vmx_set_msr_bitmap(&vmx->vcpu);
2594 * reads and returns guest's timestamp counter "register"
2595 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2596 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2598 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2600 u64 host_tsc, tsc_offset;
2603 tsc_offset = vmcs_read64(TSC_OFFSET);
2604 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2608 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2609 * counter, even if a nested guest (L2) is currently running.
2611 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2615 tsc_offset = is_guest_mode(vcpu) ?
2616 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2617 vmcs_read64(TSC_OFFSET);
2618 return host_tsc + tsc_offset;
2622 * writes 'offset' into guest's timestamp counter offset register
2624 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2626 if (is_guest_mode(vcpu)) {
2628 * We're here if L1 chose not to trap WRMSR to TSC. According
2629 * to the spec, this should set L1's TSC; The offset that L1
2630 * set for L2 remains unchanged, and still needs to be added
2631 * to the newly set TSC to get L2's TSC.
2633 struct vmcs12 *vmcs12;
2634 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2635 /* recalculate vmcs02.TSC_OFFSET: */
2636 vmcs12 = get_vmcs12(vcpu);
2637 vmcs_write64(TSC_OFFSET, offset +
2638 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2639 vmcs12->tsc_offset : 0));
2641 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2642 vmcs_read64(TSC_OFFSET), offset);
2643 vmcs_write64(TSC_OFFSET, offset);
2647 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2649 u64 offset = vmcs_read64(TSC_OFFSET);
2651 vmcs_write64(TSC_OFFSET, offset + adjustment);
2652 if (is_guest_mode(vcpu)) {
2653 /* Even when running L2, the adjustment needs to apply to L1 */
2654 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2656 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2657 offset + adjustment);
2660 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2662 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2663 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2667 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2668 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2669 * all guests if the "nested" module option is off, and can also be disabled
2670 * for a single guest by disabling its VMX cpuid bit.
2672 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2674 return nested && guest_cpuid_has_vmx(vcpu);
2678 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2679 * returned for the various VMX controls MSRs when nested VMX is enabled.
2680 * The same values should also be used to verify that vmcs12 control fields are
2681 * valid during nested entry from L1 to L2.
2682 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2683 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2684 * bit in the high half is on if the corresponding bit in the control field
2685 * may be on. See also vmx_control_verify().
2687 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2690 * Note that as a general rule, the high half of the MSRs (bits in
2691 * the control fields which may be 1) should be initialized by the
2692 * intersection of the underlying hardware's MSR (i.e., features which
2693 * can be supported) and the list of features we want to expose -
2694 * because they are known to be properly supported in our code.
2695 * Also, usually, the low half of the MSRs (bits which must be 1) can
2696 * be set to 0, meaning that L1 may turn off any of these bits. The
2697 * reason is that if one of these bits is necessary, it will appear
2698 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2699 * fields of vmcs01 and vmcs02, will turn these bits off - and
2700 * nested_vmx_exit_handled() will not pass related exits to L1.
2701 * These rules have exceptions below.
2704 /* pin-based controls */
2705 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2706 vmx->nested.nested_vmx_pinbased_ctls_low,
2707 vmx->nested.nested_vmx_pinbased_ctls_high);
2708 vmx->nested.nested_vmx_pinbased_ctls_low |=
2709 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2710 vmx->nested.nested_vmx_pinbased_ctls_high &=
2711 PIN_BASED_EXT_INTR_MASK |
2712 PIN_BASED_NMI_EXITING |
2713 PIN_BASED_VIRTUAL_NMIS;
2714 vmx->nested.nested_vmx_pinbased_ctls_high |=
2715 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2716 PIN_BASED_VMX_PREEMPTION_TIMER;
2717 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2718 vmx->nested.nested_vmx_pinbased_ctls_high |=
2719 PIN_BASED_POSTED_INTR;
2722 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2723 vmx->nested.nested_vmx_exit_ctls_low,
2724 vmx->nested.nested_vmx_exit_ctls_high);
2725 vmx->nested.nested_vmx_exit_ctls_low =
2726 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2728 vmx->nested.nested_vmx_exit_ctls_high &=
2729 #ifdef CONFIG_X86_64
2730 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2732 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2733 vmx->nested.nested_vmx_exit_ctls_high |=
2734 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2735 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2736 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2738 if (kvm_mpx_supported())
2739 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2741 /* We support free control of debug control saving. */
2742 vmx->nested.nested_vmx_true_exit_ctls_low =
2743 vmx->nested.nested_vmx_exit_ctls_low &
2744 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2746 /* entry controls */
2747 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2748 vmx->nested.nested_vmx_entry_ctls_low,
2749 vmx->nested.nested_vmx_entry_ctls_high);
2750 vmx->nested.nested_vmx_entry_ctls_low =
2751 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2752 vmx->nested.nested_vmx_entry_ctls_high &=
2753 #ifdef CONFIG_X86_64
2754 VM_ENTRY_IA32E_MODE |
2756 VM_ENTRY_LOAD_IA32_PAT;
2757 vmx->nested.nested_vmx_entry_ctls_high |=
2758 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2759 if (kvm_mpx_supported())
2760 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2762 /* We support free control of debug control loading. */
2763 vmx->nested.nested_vmx_true_entry_ctls_low =
2764 vmx->nested.nested_vmx_entry_ctls_low &
2765 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2767 /* cpu-based controls */
2768 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2769 vmx->nested.nested_vmx_procbased_ctls_low,
2770 vmx->nested.nested_vmx_procbased_ctls_high);
2771 vmx->nested.nested_vmx_procbased_ctls_low =
2772 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2773 vmx->nested.nested_vmx_procbased_ctls_high &=
2774 CPU_BASED_VIRTUAL_INTR_PENDING |
2775 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2776 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2777 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2778 CPU_BASED_CR3_STORE_EXITING |
2779 #ifdef CONFIG_X86_64
2780 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2782 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2783 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2784 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2785 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2786 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2788 * We can allow some features even when not supported by the
2789 * hardware. For example, L1 can specify an MSR bitmap - and we
2790 * can use it to avoid exits to L1 - even when L0 runs L2
2791 * without MSR bitmaps.
2793 vmx->nested.nested_vmx_procbased_ctls_high |=
2794 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2795 CPU_BASED_USE_MSR_BITMAPS;
2797 /* We support free control of CR3 access interception. */
2798 vmx->nested.nested_vmx_true_procbased_ctls_low =
2799 vmx->nested.nested_vmx_procbased_ctls_low &
2800 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2802 /* secondary cpu-based controls */
2803 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2804 vmx->nested.nested_vmx_secondary_ctls_low,
2805 vmx->nested.nested_vmx_secondary_ctls_high);
2806 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2807 vmx->nested.nested_vmx_secondary_ctls_high &=
2808 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2809 SECONDARY_EXEC_RDTSCP |
2810 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2811 SECONDARY_EXEC_ENABLE_VPID |
2812 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2813 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2814 SECONDARY_EXEC_WBINVD_EXITING |
2815 SECONDARY_EXEC_XSAVES;
2818 /* nested EPT: emulate EPT also to L1 */
2819 vmx->nested.nested_vmx_secondary_ctls_high |=
2820 SECONDARY_EXEC_ENABLE_EPT;
2821 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2822 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2824 if (cpu_has_vmx_ept_execute_only())
2825 vmx->nested.nested_vmx_ept_caps |=
2826 VMX_EPT_EXECUTE_ONLY_BIT;
2827 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2828 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2829 VMX_EPT_EXTENT_CONTEXT_BIT;
2831 vmx->nested.nested_vmx_ept_caps = 0;
2834 * Old versions of KVM use the single-context version without
2835 * checking for support, so declare that it is supported even
2836 * though it is treated as global context. The alternative is
2837 * not failing the single-context invvpid, and it is worse.
2840 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2841 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2842 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2844 vmx->nested.nested_vmx_vpid_caps = 0;
2846 if (enable_unrestricted_guest)
2847 vmx->nested.nested_vmx_secondary_ctls_high |=
2848 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2850 /* miscellaneous data */
2851 rdmsr(MSR_IA32_VMX_MISC,
2852 vmx->nested.nested_vmx_misc_low,
2853 vmx->nested.nested_vmx_misc_high);
2854 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2855 vmx->nested.nested_vmx_misc_low |=
2856 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2857 VMX_MISC_ACTIVITY_HLT;
2858 vmx->nested.nested_vmx_misc_high = 0;
2861 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2864 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2866 return ((control & high) | low) == control;
2869 static inline u64 vmx_control_msr(u32 low, u32 high)
2871 return low | ((u64)high << 32);
2874 /* Returns 0 on success, non-0 otherwise. */
2875 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2877 struct vcpu_vmx *vmx = to_vmx(vcpu);
2879 switch (msr_index) {
2880 case MSR_IA32_VMX_BASIC:
2882 * This MSR reports some information about VMX support. We
2883 * should return information about the VMX we emulate for the
2884 * guest, and the VMCS structure we give it - not about the
2885 * VMX support of the underlying hardware.
2887 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2888 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2889 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2890 if (cpu_has_vmx_basic_inout())
2891 *pdata |= VMX_BASIC_INOUT;
2893 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2894 case MSR_IA32_VMX_PINBASED_CTLS:
2895 *pdata = vmx_control_msr(
2896 vmx->nested.nested_vmx_pinbased_ctls_low,
2897 vmx->nested.nested_vmx_pinbased_ctls_high);
2899 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2900 *pdata = vmx_control_msr(
2901 vmx->nested.nested_vmx_true_procbased_ctls_low,
2902 vmx->nested.nested_vmx_procbased_ctls_high);
2904 case MSR_IA32_VMX_PROCBASED_CTLS:
2905 *pdata = vmx_control_msr(
2906 vmx->nested.nested_vmx_procbased_ctls_low,
2907 vmx->nested.nested_vmx_procbased_ctls_high);
2909 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2910 *pdata = vmx_control_msr(
2911 vmx->nested.nested_vmx_true_exit_ctls_low,
2912 vmx->nested.nested_vmx_exit_ctls_high);
2914 case MSR_IA32_VMX_EXIT_CTLS:
2915 *pdata = vmx_control_msr(
2916 vmx->nested.nested_vmx_exit_ctls_low,
2917 vmx->nested.nested_vmx_exit_ctls_high);
2919 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2920 *pdata = vmx_control_msr(
2921 vmx->nested.nested_vmx_true_entry_ctls_low,
2922 vmx->nested.nested_vmx_entry_ctls_high);
2924 case MSR_IA32_VMX_ENTRY_CTLS:
2925 *pdata = vmx_control_msr(
2926 vmx->nested.nested_vmx_entry_ctls_low,
2927 vmx->nested.nested_vmx_entry_ctls_high);
2929 case MSR_IA32_VMX_MISC:
2930 *pdata = vmx_control_msr(
2931 vmx->nested.nested_vmx_misc_low,
2932 vmx->nested.nested_vmx_misc_high);
2935 * These MSRs specify bits which the guest must keep fixed (on or off)
2936 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2937 * We picked the standard core2 setting.
2939 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2940 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2941 case MSR_IA32_VMX_CR0_FIXED0:
2942 *pdata = VMXON_CR0_ALWAYSON;
2944 case MSR_IA32_VMX_CR0_FIXED1:
2947 case MSR_IA32_VMX_CR4_FIXED0:
2948 *pdata = VMXON_CR4_ALWAYSON;
2950 case MSR_IA32_VMX_CR4_FIXED1:
2953 case MSR_IA32_VMX_VMCS_ENUM:
2954 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2956 case MSR_IA32_VMX_PROCBASED_CTLS2:
2957 *pdata = vmx_control_msr(
2958 vmx->nested.nested_vmx_secondary_ctls_low,
2959 vmx->nested.nested_vmx_secondary_ctls_high);
2961 case MSR_IA32_VMX_EPT_VPID_CAP:
2962 *pdata = vmx->nested.nested_vmx_ept_caps |
2963 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2972 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2975 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2977 return !(val & ~valid_bits);
2981 * Reads an msr value (of 'msr_index') into 'pdata'.
2982 * Returns 0 on success, non-0 otherwise.
2983 * Assumes vcpu_load() was already called.
2985 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2987 struct shared_msr_entry *msr;
2989 switch (msr_info->index) {
2990 #ifdef CONFIG_X86_64
2992 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2995 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2997 case MSR_KERNEL_GS_BASE:
2998 vmx_load_host_state(to_vmx(vcpu));
2999 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3003 return kvm_get_msr_common(vcpu, msr_info);
3005 msr_info->data = guest_read_tsc(vcpu);
3007 case MSR_IA32_SYSENTER_CS:
3008 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3010 case MSR_IA32_SYSENTER_EIP:
3011 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3013 case MSR_IA32_SYSENTER_ESP:
3014 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3016 case MSR_IA32_BNDCFGS:
3017 if (!kvm_mpx_supported())
3019 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3021 case MSR_IA32_MCG_EXT_CTL:
3022 if (!msr_info->host_initiated &&
3023 !(to_vmx(vcpu)->msr_ia32_feature_control &
3024 FEATURE_CONTROL_LMCE))
3026 msr_info->data = vcpu->arch.mcg_ext_ctl;
3028 case MSR_IA32_FEATURE_CONTROL:
3029 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3031 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3032 if (!nested_vmx_allowed(vcpu))
3034 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3036 if (!vmx_xsaves_supported())
3038 msr_info->data = vcpu->arch.ia32_xss;
3041 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3043 /* Otherwise falls through */
3045 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3047 msr_info->data = msr->data;
3050 return kvm_get_msr_common(vcpu, msr_info);
3056 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3059 * Writes msr value into into the appropriate "register".
3060 * Returns 0 on success, non-0 otherwise.
3061 * Assumes vcpu_load() was already called.
3063 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3065 struct vcpu_vmx *vmx = to_vmx(vcpu);
3066 struct shared_msr_entry *msr;
3068 u32 msr_index = msr_info->index;
3069 u64 data = msr_info->data;
3071 switch (msr_index) {
3073 ret = kvm_set_msr_common(vcpu, msr_info);
3075 #ifdef CONFIG_X86_64
3077 vmx_segment_cache_clear(vmx);
3078 vmcs_writel(GUEST_FS_BASE, data);
3081 vmx_segment_cache_clear(vmx);
3082 vmcs_writel(GUEST_GS_BASE, data);
3084 case MSR_KERNEL_GS_BASE:
3085 vmx_load_host_state(vmx);
3086 vmx->msr_guest_kernel_gs_base = data;
3089 case MSR_IA32_SYSENTER_CS:
3090 vmcs_write32(GUEST_SYSENTER_CS, data);
3092 case MSR_IA32_SYSENTER_EIP:
3093 vmcs_writel(GUEST_SYSENTER_EIP, data);
3095 case MSR_IA32_SYSENTER_ESP:
3096 vmcs_writel(GUEST_SYSENTER_ESP, data);
3098 case MSR_IA32_BNDCFGS:
3099 if (!kvm_mpx_supported())
3101 vmcs_write64(GUEST_BNDCFGS, data);
3104 kvm_write_tsc(vcpu, msr_info);
3106 case MSR_IA32_CR_PAT:
3107 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3108 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3110 vmcs_write64(GUEST_IA32_PAT, data);
3111 vcpu->arch.pat = data;
3114 ret = kvm_set_msr_common(vcpu, msr_info);
3116 case MSR_IA32_TSC_ADJUST:
3117 ret = kvm_set_msr_common(vcpu, msr_info);
3119 case MSR_IA32_MCG_EXT_CTL:
3120 if ((!msr_info->host_initiated &&
3121 !(to_vmx(vcpu)->msr_ia32_feature_control &
3122 FEATURE_CONTROL_LMCE)) ||
3123 (data & ~MCG_EXT_CTL_LMCE_EN))
3125 vcpu->arch.mcg_ext_ctl = data;
3127 case MSR_IA32_FEATURE_CONTROL:
3128 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3129 (to_vmx(vcpu)->msr_ia32_feature_control &
3130 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3132 vmx->msr_ia32_feature_control = data;
3133 if (msr_info->host_initiated && data == 0)
3134 vmx_leave_nested(vcpu);
3136 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3137 return 1; /* they are read-only */
3139 if (!vmx_xsaves_supported())
3142 * The only supported bit as of Skylake is bit 8, but
3143 * it is not supported on KVM.
3147 vcpu->arch.ia32_xss = data;
3148 if (vcpu->arch.ia32_xss != host_xss)
3149 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3150 vcpu->arch.ia32_xss, host_xss);
3152 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3155 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3157 /* Check reserved bit, higher 32 bits should be zero */
3158 if ((data >> 32) != 0)
3160 /* Otherwise falls through */
3162 msr = find_msr_entry(vmx, msr_index);
3164 u64 old_msr_data = msr->data;
3166 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3168 ret = kvm_set_shared_msr(msr->index, msr->data,
3172 msr->data = old_msr_data;
3176 ret = kvm_set_msr_common(vcpu, msr_info);
3182 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3184 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3187 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3190 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3192 case VCPU_EXREG_PDPTR:
3194 ept_save_pdptrs(vcpu);
3201 static __init int cpu_has_kvm_support(void)
3203 return cpu_has_vmx();
3206 static __init int vmx_disabled_by_bios(void)
3210 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3211 if (msr & FEATURE_CONTROL_LOCKED) {
3212 /* launched w/ TXT and VMX disabled */
3213 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3216 /* launched w/o TXT and VMX only enabled w/ TXT */
3217 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3218 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3219 && !tboot_enabled()) {
3220 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3221 "activate TXT before enabling KVM\n");
3224 /* launched w/o TXT and VMX disabled */
3225 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3226 && !tboot_enabled())
3233 static void kvm_cpu_vmxon(u64 addr)
3235 intel_pt_handle_vmx(1);
3237 asm volatile (ASM_VMX_VMXON_RAX
3238 : : "a"(&addr), "m"(addr)
3242 static int hardware_enable(void)
3244 int cpu = raw_smp_processor_id();
3245 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3248 if (cr4_read_shadow() & X86_CR4_VMXE)
3251 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3252 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3253 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3256 * Now we can enable the vmclear operation in kdump
3257 * since the loaded_vmcss_on_cpu list on this cpu
3258 * has been initialized.
3260 * Though the cpu is not in VMX operation now, there
3261 * is no problem to enable the vmclear operation
3262 * for the loaded_vmcss_on_cpu list is empty!
3264 crash_enable_local_vmclear(cpu);
3266 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3268 test_bits = FEATURE_CONTROL_LOCKED;
3269 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3270 if (tboot_enabled())
3271 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3273 if ((old & test_bits) != test_bits) {
3274 /* enable and lock */
3275 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3277 cr4_set_bits(X86_CR4_VMXE);
3279 if (vmm_exclusive) {
3280 kvm_cpu_vmxon(phys_addr);
3284 native_store_gdt(this_cpu_ptr(&host_gdt));
3289 static void vmclear_local_loaded_vmcss(void)
3291 int cpu = raw_smp_processor_id();
3292 struct loaded_vmcs *v, *n;
3294 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3295 loaded_vmcss_on_cpu_link)
3296 __loaded_vmcs_clear(v);
3300 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3303 static void kvm_cpu_vmxoff(void)
3305 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3307 intel_pt_handle_vmx(0);
3310 static void hardware_disable(void)
3312 if (vmm_exclusive) {
3313 vmclear_local_loaded_vmcss();
3316 cr4_clear_bits(X86_CR4_VMXE);
3319 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3320 u32 msr, u32 *result)
3322 u32 vmx_msr_low, vmx_msr_high;
3323 u32 ctl = ctl_min | ctl_opt;
3325 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3327 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3328 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3330 /* Ensure minimum (required) set of control bits are supported. */
3338 static __init bool allow_1_setting(u32 msr, u32 ctl)
3340 u32 vmx_msr_low, vmx_msr_high;
3342 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3343 return vmx_msr_high & ctl;
3346 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3348 u32 vmx_msr_low, vmx_msr_high;
3349 u32 min, opt, min2, opt2;
3350 u32 _pin_based_exec_control = 0;
3351 u32 _cpu_based_exec_control = 0;
3352 u32 _cpu_based_2nd_exec_control = 0;
3353 u32 _vmexit_control = 0;
3354 u32 _vmentry_control = 0;
3356 min = CPU_BASED_HLT_EXITING |
3357 #ifdef CONFIG_X86_64
3358 CPU_BASED_CR8_LOAD_EXITING |
3359 CPU_BASED_CR8_STORE_EXITING |
3361 CPU_BASED_CR3_LOAD_EXITING |
3362 CPU_BASED_CR3_STORE_EXITING |
3363 CPU_BASED_USE_IO_BITMAPS |
3364 CPU_BASED_MOV_DR_EXITING |
3365 CPU_BASED_USE_TSC_OFFSETING |
3366 CPU_BASED_MWAIT_EXITING |
3367 CPU_BASED_MONITOR_EXITING |
3368 CPU_BASED_INVLPG_EXITING |
3369 CPU_BASED_RDPMC_EXITING;
3371 opt = CPU_BASED_TPR_SHADOW |
3372 CPU_BASED_USE_MSR_BITMAPS |
3373 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3374 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3375 &_cpu_based_exec_control) < 0)
3377 #ifdef CONFIG_X86_64
3378 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3379 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3380 ~CPU_BASED_CR8_STORE_EXITING;
3382 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3384 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3385 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3386 SECONDARY_EXEC_WBINVD_EXITING |
3387 SECONDARY_EXEC_ENABLE_VPID |
3388 SECONDARY_EXEC_ENABLE_EPT |
3389 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3390 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3391 SECONDARY_EXEC_RDTSCP |
3392 SECONDARY_EXEC_ENABLE_INVPCID |
3393 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3394 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3395 SECONDARY_EXEC_SHADOW_VMCS |
3396 SECONDARY_EXEC_XSAVES |
3397 SECONDARY_EXEC_ENABLE_PML |
3398 SECONDARY_EXEC_TSC_SCALING;
3399 if (adjust_vmx_controls(min2, opt2,
3400 MSR_IA32_VMX_PROCBASED_CTLS2,
3401 &_cpu_based_2nd_exec_control) < 0)
3404 #ifndef CONFIG_X86_64
3405 if (!(_cpu_based_2nd_exec_control &
3406 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3407 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3410 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3411 _cpu_based_2nd_exec_control &= ~(
3412 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3413 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3414 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3416 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3417 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3419 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3420 CPU_BASED_CR3_STORE_EXITING |
3421 CPU_BASED_INVLPG_EXITING);
3422 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3423 vmx_capability.ept, vmx_capability.vpid);
3426 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3427 #ifdef CONFIG_X86_64
3428 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3430 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3431 VM_EXIT_CLEAR_BNDCFGS;
3432 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3433 &_vmexit_control) < 0)
3436 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3437 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3438 PIN_BASED_VMX_PREEMPTION_TIMER;
3439 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3440 &_pin_based_exec_control) < 0)
3443 if (cpu_has_broken_vmx_preemption_timer())
3444 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3445 if (!(_cpu_based_2nd_exec_control &
3446 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3447 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3449 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3450 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3451 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3452 &_vmentry_control) < 0)
3455 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3457 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3458 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3461 #ifdef CONFIG_X86_64
3462 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3463 if (vmx_msr_high & (1u<<16))
3467 /* Require Write-Back (WB) memory type for VMCS accesses. */
3468 if (((vmx_msr_high >> 18) & 15) != 6)
3471 vmcs_conf->size = vmx_msr_high & 0x1fff;
3472 vmcs_conf->order = get_order(vmcs_conf->size);
3473 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3474 vmcs_conf->revision_id = vmx_msr_low;
3476 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3477 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3478 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3479 vmcs_conf->vmexit_ctrl = _vmexit_control;
3480 vmcs_conf->vmentry_ctrl = _vmentry_control;
3482 cpu_has_load_ia32_efer =
3483 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3484 VM_ENTRY_LOAD_IA32_EFER)
3485 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3486 VM_EXIT_LOAD_IA32_EFER);
3488 cpu_has_load_perf_global_ctrl =
3489 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3490 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3491 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3492 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3495 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3496 * but due to errata below it can't be used. Workaround is to use
3497 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3499 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3504 * BC86,AAY89,BD102 (model 44)
3508 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3509 switch (boot_cpu_data.x86_model) {
3515 cpu_has_load_perf_global_ctrl = false;
3516 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3517 "does not work properly. Using workaround\n");
3524 if (boot_cpu_has(X86_FEATURE_XSAVES))
3525 rdmsrl(MSR_IA32_XSS, host_xss);
3530 static struct vmcs *alloc_vmcs_cpu(int cpu)
3532 int node = cpu_to_node(cpu);
3536 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3539 vmcs = page_address(pages);
3540 memset(vmcs, 0, vmcs_config.size);
3541 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3545 static struct vmcs *alloc_vmcs(void)
3547 return alloc_vmcs_cpu(raw_smp_processor_id());
3550 static void free_vmcs(struct vmcs *vmcs)
3552 free_pages((unsigned long)vmcs, vmcs_config.order);
3556 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3558 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3560 if (!loaded_vmcs->vmcs)
3562 loaded_vmcs_clear(loaded_vmcs);
3563 free_vmcs(loaded_vmcs->vmcs);
3564 loaded_vmcs->vmcs = NULL;
3567 static void free_kvm_area(void)
3571 for_each_possible_cpu(cpu) {
3572 free_vmcs(per_cpu(vmxarea, cpu));
3573 per_cpu(vmxarea, cpu) = NULL;
3577 static void init_vmcs_shadow_fields(void)
3581 /* No checks for read only fields yet */
3583 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3584 switch (shadow_read_write_fields[i]) {
3586 if (!kvm_mpx_supported())
3594 shadow_read_write_fields[j] =
3595 shadow_read_write_fields[i];
3598 max_shadow_read_write_fields = j;
3600 /* shadowed fields guest access without vmexit */
3601 for (i = 0; i < max_shadow_read_write_fields; i++) {
3602 clear_bit(shadow_read_write_fields[i],
3603 vmx_vmwrite_bitmap);
3604 clear_bit(shadow_read_write_fields[i],
3607 for (i = 0; i < max_shadow_read_only_fields; i++)
3608 clear_bit(shadow_read_only_fields[i],
3612 static __init int alloc_kvm_area(void)
3616 for_each_possible_cpu(cpu) {
3619 vmcs = alloc_vmcs_cpu(cpu);
3625 per_cpu(vmxarea, cpu) = vmcs;
3630 static bool emulation_required(struct kvm_vcpu *vcpu)
3632 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3635 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3636 struct kvm_segment *save)
3638 if (!emulate_invalid_guest_state) {
3640 * CS and SS RPL should be equal during guest entry according
3641 * to VMX spec, but in reality it is not always so. Since vcpu
3642 * is in the middle of the transition from real mode to
3643 * protected mode it is safe to assume that RPL 0 is a good
3646 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3647 save->selector &= ~SEGMENT_RPL_MASK;
3648 save->dpl = save->selector & SEGMENT_RPL_MASK;
3651 vmx_set_segment(vcpu, save, seg);
3654 static void enter_pmode(struct kvm_vcpu *vcpu)
3656 unsigned long flags;
3657 struct vcpu_vmx *vmx = to_vmx(vcpu);
3660 * Update real mode segment cache. It may be not up-to-date if sement
3661 * register was written while vcpu was in a guest mode.
3663 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3664 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3665 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3666 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3667 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3668 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3670 vmx->rmode.vm86_active = 0;
3672 vmx_segment_cache_clear(vmx);
3674 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3676 flags = vmcs_readl(GUEST_RFLAGS);
3677 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3678 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3679 vmcs_writel(GUEST_RFLAGS, flags);
3681 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3682 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3684 update_exception_bitmap(vcpu);
3686 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3687 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3688 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3689 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3690 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3691 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3694 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3696 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3697 struct kvm_segment var = *save;
3700 if (seg == VCPU_SREG_CS)
3703 if (!emulate_invalid_guest_state) {
3704 var.selector = var.base >> 4;
3705 var.base = var.base & 0xffff0;
3715 if (save->base & 0xf)
3716 printk_once(KERN_WARNING "kvm: segment base is not "
3717 "paragraph aligned when entering "
3718 "protected mode (seg=%d)", seg);
3721 vmcs_write16(sf->selector, var.selector);
3722 vmcs_write32(sf->base, var.base);
3723 vmcs_write32(sf->limit, var.limit);
3724 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3727 static void enter_rmode(struct kvm_vcpu *vcpu)
3729 unsigned long flags;
3730 struct vcpu_vmx *vmx = to_vmx(vcpu);
3732 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3733 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3734 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3735 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3736 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3737 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3738 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3740 vmx->rmode.vm86_active = 1;
3743 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3744 * vcpu. Warn the user that an update is overdue.
3746 if (!vcpu->kvm->arch.tss_addr)
3747 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3748 "called before entering vcpu\n");
3750 vmx_segment_cache_clear(vmx);
3752 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3753 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3754 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3756 flags = vmcs_readl(GUEST_RFLAGS);
3757 vmx->rmode.save_rflags = flags;
3759 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3761 vmcs_writel(GUEST_RFLAGS, flags);
3762 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3763 update_exception_bitmap(vcpu);
3765 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3766 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3767 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3768 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3769 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3770 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3772 kvm_mmu_reset_context(vcpu);
3775 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3777 struct vcpu_vmx *vmx = to_vmx(vcpu);
3778 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3784 * Force kernel_gs_base reloading before EFER changes, as control
3785 * of this msr depends on is_long_mode().
3787 vmx_load_host_state(to_vmx(vcpu));
3788 vcpu->arch.efer = efer;
3789 if (efer & EFER_LMA) {
3790 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3793 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3795 msr->data = efer & ~EFER_LME;
3800 #ifdef CONFIG_X86_64
3802 static void enter_lmode(struct kvm_vcpu *vcpu)
3806 vmx_segment_cache_clear(to_vmx(vcpu));
3808 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3809 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3810 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3812 vmcs_write32(GUEST_TR_AR_BYTES,
3813 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3814 | VMX_AR_TYPE_BUSY_64_TSS);
3816 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3819 static void exit_lmode(struct kvm_vcpu *vcpu)
3821 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3822 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3827 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3829 vpid_sync_context(vpid);
3831 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3833 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3837 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3839 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3842 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3844 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3846 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3847 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3850 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3852 if (enable_ept && is_paging(vcpu))
3853 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3854 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3857 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3859 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3861 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3862 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3865 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3867 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3869 if (!test_bit(VCPU_EXREG_PDPTR,
3870 (unsigned long *)&vcpu->arch.regs_dirty))
3873 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3874 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3875 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3876 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3877 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3881 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3883 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3885 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3886 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3887 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3888 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3889 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3892 __set_bit(VCPU_EXREG_PDPTR,
3893 (unsigned long *)&vcpu->arch.regs_avail);
3894 __set_bit(VCPU_EXREG_PDPTR,
3895 (unsigned long *)&vcpu->arch.regs_dirty);
3898 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3900 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3902 struct kvm_vcpu *vcpu)
3904 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3905 vmx_decache_cr3(vcpu);
3906 if (!(cr0 & X86_CR0_PG)) {
3907 /* From paging/starting to nonpaging */
3908 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3909 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3910 (CPU_BASED_CR3_LOAD_EXITING |
3911 CPU_BASED_CR3_STORE_EXITING));
3912 vcpu->arch.cr0 = cr0;
3913 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3914 } else if (!is_paging(vcpu)) {
3915 /* From nonpaging to paging */
3916 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3917 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3918 ~(CPU_BASED_CR3_LOAD_EXITING |
3919 CPU_BASED_CR3_STORE_EXITING));
3920 vcpu->arch.cr0 = cr0;
3921 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3924 if (!(cr0 & X86_CR0_WP))
3925 *hw_cr0 &= ~X86_CR0_WP;
3928 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3930 struct vcpu_vmx *vmx = to_vmx(vcpu);
3931 unsigned long hw_cr0;
3933 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3934 if (enable_unrestricted_guest)
3935 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3937 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3939 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3942 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3946 #ifdef CONFIG_X86_64
3947 if (vcpu->arch.efer & EFER_LME) {
3948 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3950 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3956 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3958 if (!vcpu->fpu_active)
3959 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3961 vmcs_writel(CR0_READ_SHADOW, cr0);
3962 vmcs_writel(GUEST_CR0, hw_cr0);
3963 vcpu->arch.cr0 = cr0;
3965 /* depends on vcpu->arch.cr0 to be set to a new value */
3966 vmx->emulation_required = emulation_required(vcpu);
3969 static u64 construct_eptp(unsigned long root_hpa)
3973 /* TODO write the value reading from MSR */
3974 eptp = VMX_EPT_DEFAULT_MT |
3975 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3976 if (enable_ept_ad_bits)
3977 eptp |= VMX_EPT_AD_ENABLE_BIT;
3978 eptp |= (root_hpa & PAGE_MASK);
3983 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3985 unsigned long guest_cr3;
3990 eptp = construct_eptp(cr3);
3991 vmcs_write64(EPT_POINTER, eptp);
3992 if (is_paging(vcpu) || is_guest_mode(vcpu))
3993 guest_cr3 = kvm_read_cr3(vcpu);
3995 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3996 ept_load_pdptrs(vcpu);
3999 vmx_flush_tlb(vcpu);
4000 vmcs_writel(GUEST_CR3, guest_cr3);
4003 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4006 * Pass through host's Machine Check Enable value to hw_cr4, which
4007 * is in force while we are in guest mode. Do not let guests control
4008 * this bit, even if host CR4.MCE == 0.
4010 unsigned long hw_cr4 =
4011 (cr4_read_shadow() & X86_CR4_MCE) |
4012 (cr4 & ~X86_CR4_MCE) |
4013 (to_vmx(vcpu)->rmode.vm86_active ?
4014 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4016 if (cr4 & X86_CR4_VMXE) {
4018 * To use VMXON (and later other VMX instructions), a guest
4019 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4020 * So basically the check on whether to allow nested VMX
4023 if (!nested_vmx_allowed(vcpu))
4026 if (to_vmx(vcpu)->nested.vmxon &&
4027 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
4030 vcpu->arch.cr4 = cr4;
4032 if (!is_paging(vcpu)) {
4033 hw_cr4 &= ~X86_CR4_PAE;
4034 hw_cr4 |= X86_CR4_PSE;
4035 } else if (!(cr4 & X86_CR4_PAE)) {
4036 hw_cr4 &= ~X86_CR4_PAE;
4040 if (!enable_unrestricted_guest && !is_paging(vcpu))
4042 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4043 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4044 * to be manually disabled when guest switches to non-paging
4047 * If !enable_unrestricted_guest, the CPU is always running
4048 * with CR0.PG=1 and CR4 needs to be modified.
4049 * If enable_unrestricted_guest, the CPU automatically
4050 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4052 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4054 vmcs_writel(CR4_READ_SHADOW, cr4);
4055 vmcs_writel(GUEST_CR4, hw_cr4);
4059 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4060 struct kvm_segment *var, int seg)
4062 struct vcpu_vmx *vmx = to_vmx(vcpu);
4065 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4066 *var = vmx->rmode.segs[seg];
4067 if (seg == VCPU_SREG_TR
4068 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4070 var->base = vmx_read_guest_seg_base(vmx, seg);
4071 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4074 var->base = vmx_read_guest_seg_base(vmx, seg);
4075 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4076 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4077 ar = vmx_read_guest_seg_ar(vmx, seg);
4078 var->unusable = (ar >> 16) & 1;
4079 var->type = ar & 15;
4080 var->s = (ar >> 4) & 1;
4081 var->dpl = (ar >> 5) & 3;
4083 * Some userspaces do not preserve unusable property. Since usable
4084 * segment has to be present according to VMX spec we can use present
4085 * property to amend userspace bug by making unusable segment always
4086 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4087 * segment as unusable.
4089 var->present = !var->unusable;
4090 var->avl = (ar >> 12) & 1;
4091 var->l = (ar >> 13) & 1;
4092 var->db = (ar >> 14) & 1;
4093 var->g = (ar >> 15) & 1;
4096 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4098 struct kvm_segment s;
4100 if (to_vmx(vcpu)->rmode.vm86_active) {
4101 vmx_get_segment(vcpu, &s, seg);
4104 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4107 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4109 struct vcpu_vmx *vmx = to_vmx(vcpu);
4111 if (unlikely(vmx->rmode.vm86_active))
4114 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4115 return VMX_AR_DPL(ar);
4119 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4123 if (var->unusable || !var->present)
4126 ar = var->type & 15;
4127 ar |= (var->s & 1) << 4;
4128 ar |= (var->dpl & 3) << 5;
4129 ar |= (var->present & 1) << 7;
4130 ar |= (var->avl & 1) << 12;
4131 ar |= (var->l & 1) << 13;
4132 ar |= (var->db & 1) << 14;
4133 ar |= (var->g & 1) << 15;
4139 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4140 struct kvm_segment *var, int seg)
4142 struct vcpu_vmx *vmx = to_vmx(vcpu);
4143 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4145 vmx_segment_cache_clear(vmx);
4147 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4148 vmx->rmode.segs[seg] = *var;
4149 if (seg == VCPU_SREG_TR)
4150 vmcs_write16(sf->selector, var->selector);
4152 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4156 vmcs_writel(sf->base, var->base);
4157 vmcs_write32(sf->limit, var->limit);
4158 vmcs_write16(sf->selector, var->selector);
4161 * Fix the "Accessed" bit in AR field of segment registers for older
4163 * IA32 arch specifies that at the time of processor reset the
4164 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4165 * is setting it to 0 in the userland code. This causes invalid guest
4166 * state vmexit when "unrestricted guest" mode is turned on.
4167 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4168 * tree. Newer qemu binaries with that qemu fix would not need this
4171 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4172 var->type |= 0x1; /* Accessed */
4174 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4177 vmx->emulation_required = emulation_required(vcpu);
4180 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4182 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4184 *db = (ar >> 14) & 1;
4185 *l = (ar >> 13) & 1;
4188 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4190 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4191 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4194 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4196 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4197 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4200 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4202 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4203 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4206 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4208 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4209 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4212 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4214 struct kvm_segment var;
4217 vmx_get_segment(vcpu, &var, seg);
4219 if (seg == VCPU_SREG_CS)
4221 ar = vmx_segment_access_rights(&var);
4223 if (var.base != (var.selector << 4))
4225 if (var.limit != 0xffff)
4233 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4235 struct kvm_segment cs;
4236 unsigned int cs_rpl;
4238 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4239 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4243 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4247 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4248 if (cs.dpl > cs_rpl)
4251 if (cs.dpl != cs_rpl)
4257 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4261 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4263 struct kvm_segment ss;
4264 unsigned int ss_rpl;
4266 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4267 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4271 if (ss.type != 3 && ss.type != 7)
4275 if (ss.dpl != ss_rpl) /* DPL != RPL */
4283 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4285 struct kvm_segment var;
4288 vmx_get_segment(vcpu, &var, seg);
4289 rpl = var.selector & SEGMENT_RPL_MASK;
4297 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4298 if (var.dpl < rpl) /* DPL < RPL */
4302 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4308 static bool tr_valid(struct kvm_vcpu *vcpu)
4310 struct kvm_segment tr;
4312 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4316 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4318 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4326 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4328 struct kvm_segment ldtr;
4330 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4334 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4344 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4346 struct kvm_segment cs, ss;
4348 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4349 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4351 return ((cs.selector & SEGMENT_RPL_MASK) ==
4352 (ss.selector & SEGMENT_RPL_MASK));
4356 * Check if guest state is valid. Returns true if valid, false if
4358 * We assume that registers are always usable
4360 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4362 if (enable_unrestricted_guest)
4365 /* real mode guest state checks */
4366 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4367 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4369 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4371 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4373 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4375 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4377 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4380 /* protected mode guest state checks */
4381 if (!cs_ss_rpl_check(vcpu))
4383 if (!code_segment_valid(vcpu))
4385 if (!stack_segment_valid(vcpu))
4387 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4389 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4391 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4393 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4395 if (!tr_valid(vcpu))
4397 if (!ldtr_valid(vcpu))
4401 * - Add checks on RIP
4402 * - Add checks on RFLAGS
4408 static int init_rmode_tss(struct kvm *kvm)
4414 idx = srcu_read_lock(&kvm->srcu);
4415 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4416 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4419 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4420 r = kvm_write_guest_page(kvm, fn++, &data,
4421 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4424 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4427 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4431 r = kvm_write_guest_page(kvm, fn, &data,
4432 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4435 srcu_read_unlock(&kvm->srcu, idx);
4439 static int init_rmode_identity_map(struct kvm *kvm)
4442 kvm_pfn_t identity_map_pfn;
4448 /* Protect kvm->arch.ept_identity_pagetable_done. */
4449 mutex_lock(&kvm->slots_lock);
4451 if (likely(kvm->arch.ept_identity_pagetable_done))
4454 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4456 r = alloc_identity_pagetable(kvm);
4460 idx = srcu_read_lock(&kvm->srcu);
4461 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4464 /* Set up identity-mapping pagetable for EPT in real mode */
4465 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4466 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4467 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4468 r = kvm_write_guest_page(kvm, identity_map_pfn,
4469 &tmp, i * sizeof(tmp), sizeof(tmp));
4473 kvm->arch.ept_identity_pagetable_done = true;
4476 srcu_read_unlock(&kvm->srcu, idx);
4479 mutex_unlock(&kvm->slots_lock);
4483 static void seg_setup(int seg)
4485 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4488 vmcs_write16(sf->selector, 0);
4489 vmcs_writel(sf->base, 0);
4490 vmcs_write32(sf->limit, 0xffff);
4492 if (seg == VCPU_SREG_CS)
4493 ar |= 0x08; /* code segment */
4495 vmcs_write32(sf->ar_bytes, ar);
4498 static int alloc_apic_access_page(struct kvm *kvm)
4503 mutex_lock(&kvm->slots_lock);
4504 if (kvm->arch.apic_access_page_done)
4506 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4507 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4511 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4512 if (is_error_page(page)) {
4518 * Do not pin the page in memory, so that memory hot-unplug
4519 * is able to migrate it.
4522 kvm->arch.apic_access_page_done = true;
4524 mutex_unlock(&kvm->slots_lock);
4528 static int alloc_identity_pagetable(struct kvm *kvm)
4530 /* Called with kvm->slots_lock held. */
4534 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4536 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4537 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4542 static int allocate_vpid(void)
4548 spin_lock(&vmx_vpid_lock);
4549 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4550 if (vpid < VMX_NR_VPIDS)
4551 __set_bit(vpid, vmx_vpid_bitmap);
4554 spin_unlock(&vmx_vpid_lock);
4558 static void free_vpid(int vpid)
4560 if (!enable_vpid || vpid == 0)
4562 spin_lock(&vmx_vpid_lock);
4563 __clear_bit(vpid, vmx_vpid_bitmap);
4564 spin_unlock(&vmx_vpid_lock);
4567 #define MSR_TYPE_R 1
4568 #define MSR_TYPE_W 2
4569 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4572 int f = sizeof(unsigned long);
4574 if (!cpu_has_vmx_msr_bitmap())
4578 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4579 * have the write-low and read-high bitmap offsets the wrong way round.
4580 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4582 if (msr <= 0x1fff) {
4583 if (type & MSR_TYPE_R)
4585 __clear_bit(msr, msr_bitmap + 0x000 / f);
4587 if (type & MSR_TYPE_W)
4589 __clear_bit(msr, msr_bitmap + 0x800 / f);
4591 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4593 if (type & MSR_TYPE_R)
4595 __clear_bit(msr, msr_bitmap + 0x400 / f);
4597 if (type & MSR_TYPE_W)
4599 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4604 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4607 int f = sizeof(unsigned long);
4609 if (!cpu_has_vmx_msr_bitmap())
4613 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4614 * have the write-low and read-high bitmap offsets the wrong way round.
4615 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4617 if (msr <= 0x1fff) {
4618 if (type & MSR_TYPE_R)
4620 __set_bit(msr, msr_bitmap + 0x000 / f);
4622 if (type & MSR_TYPE_W)
4624 __set_bit(msr, msr_bitmap + 0x800 / f);
4626 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4628 if (type & MSR_TYPE_R)
4630 __set_bit(msr, msr_bitmap + 0x400 / f);
4632 if (type & MSR_TYPE_W)
4634 __set_bit(msr, msr_bitmap + 0xc00 / f);
4640 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4641 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4643 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4644 unsigned long *msr_bitmap_nested,
4647 int f = sizeof(unsigned long);
4649 if (!cpu_has_vmx_msr_bitmap()) {
4655 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4656 * have the write-low and read-high bitmap offsets the wrong way round.
4657 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4659 if (msr <= 0x1fff) {
4660 if (type & MSR_TYPE_R &&
4661 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4663 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4665 if (type & MSR_TYPE_W &&
4666 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4668 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4670 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4672 if (type & MSR_TYPE_R &&
4673 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4675 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4677 if (type & MSR_TYPE_W &&
4678 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4680 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4685 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4688 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4689 msr, MSR_TYPE_R | MSR_TYPE_W);
4690 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4691 msr, MSR_TYPE_R | MSR_TYPE_W);
4694 static void vmx_enable_intercept_msr_read_x2apic(u32 msr, bool apicv_active)
4697 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4699 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4702 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv_inactive,
4704 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv_inactive,
4709 static void vmx_disable_intercept_msr_read_x2apic(u32 msr, bool apicv_active)
4712 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4714 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4717 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv_inactive,
4719 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv_inactive,
4724 static void vmx_disable_intercept_msr_write_x2apic(u32 msr, bool apicv_active)
4727 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4729 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4732 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv_inactive,
4734 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv_inactive,
4739 static bool vmx_get_enable_apicv(void)
4741 return enable_apicv;
4744 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4746 struct vcpu_vmx *vmx = to_vmx(vcpu);
4751 if (vmx->nested.pi_desc &&
4752 vmx->nested.pi_pending) {
4753 vmx->nested.pi_pending = false;
4754 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4757 max_irr = find_last_bit(
4758 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4763 vapic_page = kmap(vmx->nested.virtual_apic_page);
4768 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4769 kunmap(vmx->nested.virtual_apic_page);
4771 status = vmcs_read16(GUEST_INTR_STATUS);
4772 if ((u8)max_irr > ((u8)status & 0xff)) {
4774 status |= (u8)max_irr;
4775 vmcs_write16(GUEST_INTR_STATUS, status);
4781 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4784 if (vcpu->mode == IN_GUEST_MODE) {
4785 struct vcpu_vmx *vmx = to_vmx(vcpu);
4788 * Currently, we don't support urgent interrupt,
4789 * all interrupts are recognized as non-urgent
4790 * interrupt, so we cannot post interrupts when
4793 * If the vcpu is in guest mode, it means it is
4794 * running instead of being scheduled out and
4795 * waiting in the run queue, and that's the only
4796 * case when 'SN' is set currently, warning if
4799 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4801 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4802 POSTED_INTR_VECTOR);
4809 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4812 struct vcpu_vmx *vmx = to_vmx(vcpu);
4814 if (is_guest_mode(vcpu) &&
4815 vector == vmx->nested.posted_intr_nv) {
4816 /* the PIR and ON have been set by L1. */
4817 kvm_vcpu_trigger_posted_interrupt(vcpu);
4819 * If a posted intr is not recognized by hardware,
4820 * we will accomplish it in the next vmentry.
4822 vmx->nested.pi_pending = true;
4823 kvm_make_request(KVM_REQ_EVENT, vcpu);
4829 * Send interrupt to vcpu via posted interrupt way.
4830 * 1. If target vcpu is running(non-root mode), send posted interrupt
4831 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4832 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4833 * interrupt from PIR in next vmentry.
4835 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4837 struct vcpu_vmx *vmx = to_vmx(vcpu);
4840 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4844 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4847 r = pi_test_and_set_on(&vmx->pi_desc);
4848 kvm_make_request(KVM_REQ_EVENT, vcpu);
4849 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4850 kvm_vcpu_kick(vcpu);
4853 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4855 struct vcpu_vmx *vmx = to_vmx(vcpu);
4857 if (!pi_test_and_clear_on(&vmx->pi_desc))
4860 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4864 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4865 * will not change in the lifetime of the guest.
4866 * Note that host-state that does change is set elsewhere. E.g., host-state
4867 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4869 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4876 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4877 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4879 /* Save the most likely value for this task's CR4 in the VMCS. */
4880 cr4 = cr4_read_shadow();
4881 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4882 vmx->host_state.vmcs_host_cr4 = cr4;
4884 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4885 #ifdef CONFIG_X86_64
4887 * Load null selectors, so we can avoid reloading them in
4888 * __vmx_load_host_state(), in case userspace uses the null selectors
4889 * too (the expected case).
4891 vmcs_write16(HOST_DS_SELECTOR, 0);
4892 vmcs_write16(HOST_ES_SELECTOR, 0);
4894 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4895 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4897 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4898 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4900 native_store_idt(&dt);
4901 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4902 vmx->host_idt_base = dt.address;
4904 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4906 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4907 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4908 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4909 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4911 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4912 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4913 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4917 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4919 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4921 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4922 if (is_guest_mode(&vmx->vcpu))
4923 vmx->vcpu.arch.cr4_guest_owned_bits &=
4924 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4925 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4928 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4930 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4932 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4933 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4934 /* Enable the preemption timer dynamically */
4935 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4936 return pin_based_exec_ctrl;
4939 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4941 struct vcpu_vmx *vmx = to_vmx(vcpu);
4943 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4944 if (cpu_has_secondary_exec_ctrls()) {
4945 if (kvm_vcpu_apicv_active(vcpu))
4946 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4947 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4948 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4950 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4951 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4952 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4955 if (cpu_has_vmx_msr_bitmap())
4956 vmx_set_msr_bitmap(vcpu);
4959 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4961 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4963 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4964 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4966 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4967 exec_control &= ~CPU_BASED_TPR_SHADOW;
4968 #ifdef CONFIG_X86_64
4969 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4970 CPU_BASED_CR8_LOAD_EXITING;
4974 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4975 CPU_BASED_CR3_LOAD_EXITING |
4976 CPU_BASED_INVLPG_EXITING;
4977 return exec_control;
4980 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4982 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4983 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4984 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4986 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4988 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4989 enable_unrestricted_guest = 0;
4990 /* Enable INVPCID for non-ept guests may cause performance regression. */
4991 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4993 if (!enable_unrestricted_guest)
4994 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4996 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4997 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4998 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4999 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5000 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5001 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5003 We can NOT enable shadow_vmcs here because we don't have yet
5006 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5009 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5011 return exec_control;
5014 static void ept_set_mmio_spte_mask(void)
5017 * EPT Misconfigurations can be generated if the value of bits 2:0
5018 * of an EPT paging-structure entry is 110b (write/execute).
5019 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
5022 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
5025 #define VMX_XSS_EXIT_BITMAP 0
5027 * Sets up the vmcs for emulated real mode.
5029 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5031 #ifdef CONFIG_X86_64
5037 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5038 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5040 if (enable_shadow_vmcs) {
5041 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5042 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5044 if (cpu_has_vmx_msr_bitmap())
5045 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5047 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5050 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5051 vmx->hv_deadline_tsc = -1;
5053 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5055 if (cpu_has_secondary_exec_ctrls()) {
5056 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5057 vmx_secondary_exec_control(vmx));
5060 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5061 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5062 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5063 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5064 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5066 vmcs_write16(GUEST_INTR_STATUS, 0);
5068 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5069 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5073 vmcs_write32(PLE_GAP, ple_gap);
5074 vmx->ple_window = ple_window;
5075 vmx->ple_window_dirty = true;
5078 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5079 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5080 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5082 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5083 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5084 vmx_set_constant_host_state(vmx);
5085 #ifdef CONFIG_X86_64
5086 rdmsrl(MSR_FS_BASE, a);
5087 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5088 rdmsrl(MSR_GS_BASE, a);
5089 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5091 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5092 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5095 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5096 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5097 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5098 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5099 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5101 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5102 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5104 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5105 u32 index = vmx_msr_index[i];
5106 u32 data_low, data_high;
5109 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5111 if (wrmsr_safe(index, data_low, data_high) < 0)
5113 vmx->guest_msrs[j].index = i;
5114 vmx->guest_msrs[j].data = 0;
5115 vmx->guest_msrs[j].mask = -1ull;
5120 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5122 /* 22.2.1, 20.8.1 */
5123 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5125 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5126 set_cr4_guest_host_mask(vmx);
5128 if (vmx_xsaves_supported())
5129 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5132 ASSERT(vmx->pml_pg);
5133 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5134 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5140 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5142 struct vcpu_vmx *vmx = to_vmx(vcpu);
5143 struct msr_data apic_base_msr;
5146 vmx->rmode.vm86_active = 0;
5148 vmx->soft_vnmi_blocked = 0;
5150 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5151 kvm_set_cr8(vcpu, 0);
5154 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5155 MSR_IA32_APICBASE_ENABLE;
5156 if (kvm_vcpu_is_reset_bsp(vcpu))
5157 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5158 apic_base_msr.host_initiated = true;
5159 kvm_set_apic_base(vcpu, &apic_base_msr);
5162 vmx_segment_cache_clear(vmx);
5164 seg_setup(VCPU_SREG_CS);
5165 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5166 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5168 seg_setup(VCPU_SREG_DS);
5169 seg_setup(VCPU_SREG_ES);
5170 seg_setup(VCPU_SREG_FS);
5171 seg_setup(VCPU_SREG_GS);
5172 seg_setup(VCPU_SREG_SS);
5174 vmcs_write16(GUEST_TR_SELECTOR, 0);
5175 vmcs_writel(GUEST_TR_BASE, 0);
5176 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5177 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5179 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5180 vmcs_writel(GUEST_LDTR_BASE, 0);
5181 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5182 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5185 vmcs_write32(GUEST_SYSENTER_CS, 0);
5186 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5187 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5188 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5191 vmcs_writel(GUEST_RFLAGS, 0x02);
5192 kvm_rip_write(vcpu, 0xfff0);
5194 vmcs_writel(GUEST_GDTR_BASE, 0);
5195 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5197 vmcs_writel(GUEST_IDTR_BASE, 0);
5198 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5200 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5201 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5202 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5206 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5208 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5209 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5210 if (cpu_need_tpr_shadow(vcpu))
5211 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5212 __pa(vcpu->arch.apic->regs));
5213 vmcs_write32(TPR_THRESHOLD, 0);
5216 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5218 if (kvm_vcpu_apicv_active(vcpu))
5219 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5222 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5224 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5225 vmx->vcpu.arch.cr0 = cr0;
5226 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5227 vmx_set_cr4(vcpu, 0);
5228 vmx_set_efer(vcpu, 0);
5229 vmx_fpu_activate(vcpu);
5230 update_exception_bitmap(vcpu);
5232 vpid_sync_context(vmx->vpid);
5236 * In nested virtualization, check if L1 asked to exit on external interrupts.
5237 * For most existing hypervisors, this will always return true.
5239 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5241 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5242 PIN_BASED_EXT_INTR_MASK;
5246 * In nested virtualization, check if L1 has set
5247 * VM_EXIT_ACK_INTR_ON_EXIT
5249 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5251 return get_vmcs12(vcpu)->vm_exit_controls &
5252 VM_EXIT_ACK_INTR_ON_EXIT;
5255 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5257 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5258 PIN_BASED_NMI_EXITING;
5261 static void enable_irq_window(struct kvm_vcpu *vcpu)
5263 u32 cpu_based_vm_exec_control;
5265 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5266 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5267 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5270 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5272 u32 cpu_based_vm_exec_control;
5274 if (!cpu_has_virtual_nmis() ||
5275 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5276 enable_irq_window(vcpu);
5280 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5281 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5282 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5285 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5287 struct vcpu_vmx *vmx = to_vmx(vcpu);
5289 int irq = vcpu->arch.interrupt.nr;
5291 trace_kvm_inj_virq(irq);
5293 ++vcpu->stat.irq_injections;
5294 if (vmx->rmode.vm86_active) {
5296 if (vcpu->arch.interrupt.soft)
5297 inc_eip = vcpu->arch.event_exit_inst_len;
5298 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5299 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5302 intr = irq | INTR_INFO_VALID_MASK;
5303 if (vcpu->arch.interrupt.soft) {
5304 intr |= INTR_TYPE_SOFT_INTR;
5305 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5306 vmx->vcpu.arch.event_exit_inst_len);
5308 intr |= INTR_TYPE_EXT_INTR;
5309 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5312 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5314 struct vcpu_vmx *vmx = to_vmx(vcpu);
5316 if (!is_guest_mode(vcpu)) {
5317 if (!cpu_has_virtual_nmis()) {
5319 * Tracking the NMI-blocked state in software is built upon
5320 * finding the next open IRQ window. This, in turn, depends on
5321 * well-behaving guests: They have to keep IRQs disabled at
5322 * least as long as the NMI handler runs. Otherwise we may
5323 * cause NMI nesting, maybe breaking the guest. But as this is
5324 * highly unlikely, we can live with the residual risk.
5326 vmx->soft_vnmi_blocked = 1;
5327 vmx->vnmi_blocked_time = 0;
5330 ++vcpu->stat.nmi_injections;
5331 vmx->nmi_known_unmasked = false;
5334 if (vmx->rmode.vm86_active) {
5335 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5340 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5341 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5344 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5346 if (!cpu_has_virtual_nmis())
5347 return to_vmx(vcpu)->soft_vnmi_blocked;
5348 if (to_vmx(vcpu)->nmi_known_unmasked)
5350 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5353 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5355 struct vcpu_vmx *vmx = to_vmx(vcpu);
5357 if (!cpu_has_virtual_nmis()) {
5358 if (vmx->soft_vnmi_blocked != masked) {
5359 vmx->soft_vnmi_blocked = masked;
5360 vmx->vnmi_blocked_time = 0;
5363 vmx->nmi_known_unmasked = !masked;
5365 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5366 GUEST_INTR_STATE_NMI);
5368 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5369 GUEST_INTR_STATE_NMI);
5373 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5375 if (to_vmx(vcpu)->nested.nested_run_pending)
5378 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5381 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5382 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5383 | GUEST_INTR_STATE_NMI));
5386 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5388 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5389 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5390 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5391 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5394 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5398 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5402 kvm->arch.tss_addr = addr;
5403 return init_rmode_tss(kvm);
5406 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5411 * Update instruction length as we may reinject the exception
5412 * from user space while in guest debugging mode.
5414 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5415 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5416 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5420 if (vcpu->guest_debug &
5421 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5438 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5439 int vec, u32 err_code)
5442 * Instruction with address size override prefix opcode 0x67
5443 * Cause the #SS fault with 0 error code in VM86 mode.
5445 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5446 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5447 if (vcpu->arch.halt_request) {
5448 vcpu->arch.halt_request = 0;
5449 return kvm_vcpu_halt(vcpu);
5457 * Forward all other exceptions that are valid in real mode.
5458 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5459 * the required debugging infrastructure rework.
5461 kvm_queue_exception(vcpu, vec);
5466 * Trigger machine check on the host. We assume all the MSRs are already set up
5467 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5468 * We pass a fake environment to the machine check handler because we want
5469 * the guest to be always treated like user space, no matter what context
5470 * it used internally.
5472 static void kvm_machine_check(void)
5474 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5475 struct pt_regs regs = {
5476 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5477 .flags = X86_EFLAGS_IF,
5480 do_machine_check(®s, 0);
5484 static int handle_machine_check(struct kvm_vcpu *vcpu)
5486 /* already handled by vcpu_run */
5490 static int handle_exception(struct kvm_vcpu *vcpu)
5492 struct vcpu_vmx *vmx = to_vmx(vcpu);
5493 struct kvm_run *kvm_run = vcpu->run;
5494 u32 intr_info, ex_no, error_code;
5495 unsigned long cr2, rip, dr6;
5497 enum emulation_result er;
5499 vect_info = vmx->idt_vectoring_info;
5500 intr_info = vmx->exit_intr_info;
5502 if (is_machine_check(intr_info))
5503 return handle_machine_check(vcpu);
5505 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5506 return 1; /* already handled by vmx_vcpu_run() */
5508 if (is_no_device(intr_info)) {
5509 vmx_fpu_activate(vcpu);
5513 if (is_invalid_opcode(intr_info)) {
5514 if (is_guest_mode(vcpu)) {
5515 kvm_queue_exception(vcpu, UD_VECTOR);
5518 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5519 if (er != EMULATE_DONE)
5520 kvm_queue_exception(vcpu, UD_VECTOR);
5525 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5526 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5529 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5530 * MMIO, it is better to report an internal error.
5531 * See the comments in vmx_handle_exit.
5533 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5534 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5535 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5536 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5537 vcpu->run->internal.ndata = 3;
5538 vcpu->run->internal.data[0] = vect_info;
5539 vcpu->run->internal.data[1] = intr_info;
5540 vcpu->run->internal.data[2] = error_code;
5544 if (is_page_fault(intr_info)) {
5545 /* EPT won't cause page fault directly */
5547 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5548 trace_kvm_page_fault(cr2, error_code);
5550 if (kvm_event_needs_reinjection(vcpu))
5551 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5552 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5555 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5557 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5558 return handle_rmode_exception(vcpu, ex_no, error_code);
5562 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5565 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5566 if (!(vcpu->guest_debug &
5567 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5568 vcpu->arch.dr6 &= ~15;
5569 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5570 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5571 skip_emulated_instruction(vcpu);
5573 kvm_queue_exception(vcpu, DB_VECTOR);
5576 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5577 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5581 * Update instruction length as we may reinject #BP from
5582 * user space while in guest debugging mode. Reading it for
5583 * #DB as well causes no harm, it is not used in that case.
5585 vmx->vcpu.arch.event_exit_inst_len =
5586 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5587 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5588 rip = kvm_rip_read(vcpu);
5589 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5590 kvm_run->debug.arch.exception = ex_no;
5593 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5594 kvm_run->ex.exception = ex_no;
5595 kvm_run->ex.error_code = error_code;
5601 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5603 ++vcpu->stat.irq_exits;
5607 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5609 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5613 static int handle_io(struct kvm_vcpu *vcpu)
5615 unsigned long exit_qualification;
5616 int size, in, string;
5619 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5620 string = (exit_qualification & 16) != 0;
5621 in = (exit_qualification & 8) != 0;
5623 ++vcpu->stat.io_exits;
5626 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5628 port = exit_qualification >> 16;
5629 size = (exit_qualification & 7) + 1;
5630 skip_emulated_instruction(vcpu);
5632 return kvm_fast_pio_out(vcpu, size, port);
5636 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5639 * Patch in the VMCALL instruction:
5641 hypercall[0] = 0x0f;
5642 hypercall[1] = 0x01;
5643 hypercall[2] = 0xc1;
5646 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5648 unsigned long always_on = VMXON_CR0_ALWAYSON;
5649 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5651 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5652 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5653 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5654 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5655 return (val & always_on) == always_on;
5658 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5659 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5661 if (is_guest_mode(vcpu)) {
5662 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5663 unsigned long orig_val = val;
5666 * We get here when L2 changed cr0 in a way that did not change
5667 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5668 * but did change L0 shadowed bits. So we first calculate the
5669 * effective cr0 value that L1 would like to write into the
5670 * hardware. It consists of the L2-owned bits from the new
5671 * value combined with the L1-owned bits from L1's guest_cr0.
5673 val = (val & ~vmcs12->cr0_guest_host_mask) |
5674 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5676 if (!nested_cr0_valid(vcpu, val))
5679 if (kvm_set_cr0(vcpu, val))
5681 vmcs_writel(CR0_READ_SHADOW, orig_val);
5684 if (to_vmx(vcpu)->nested.vmxon &&
5685 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5687 return kvm_set_cr0(vcpu, val);
5691 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5693 if (is_guest_mode(vcpu)) {
5694 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5695 unsigned long orig_val = val;
5697 /* analogously to handle_set_cr0 */
5698 val = (val & ~vmcs12->cr4_guest_host_mask) |
5699 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5700 if (kvm_set_cr4(vcpu, val))
5702 vmcs_writel(CR4_READ_SHADOW, orig_val);
5705 return kvm_set_cr4(vcpu, val);
5708 /* called to set cr0 as appropriate for clts instruction exit. */
5709 static void handle_clts(struct kvm_vcpu *vcpu)
5711 if (is_guest_mode(vcpu)) {
5713 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5714 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5715 * just pretend it's off (also in arch.cr0 for fpu_activate).
5717 vmcs_writel(CR0_READ_SHADOW,
5718 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5719 vcpu->arch.cr0 &= ~X86_CR0_TS;
5721 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5724 static int handle_cr(struct kvm_vcpu *vcpu)
5726 unsigned long exit_qualification, val;
5731 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5732 cr = exit_qualification & 15;
5733 reg = (exit_qualification >> 8) & 15;
5734 switch ((exit_qualification >> 4) & 3) {
5735 case 0: /* mov to cr */
5736 val = kvm_register_readl(vcpu, reg);
5737 trace_kvm_cr_write(cr, val);
5740 err = handle_set_cr0(vcpu, val);
5741 kvm_complete_insn_gp(vcpu, err);
5744 err = kvm_set_cr3(vcpu, val);
5745 kvm_complete_insn_gp(vcpu, err);
5748 err = handle_set_cr4(vcpu, val);
5749 kvm_complete_insn_gp(vcpu, err);
5752 u8 cr8_prev = kvm_get_cr8(vcpu);
5754 err = kvm_set_cr8(vcpu, cr8);
5755 kvm_complete_insn_gp(vcpu, err);
5756 if (lapic_in_kernel(vcpu))
5758 if (cr8_prev <= cr8)
5760 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5767 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5768 skip_emulated_instruction(vcpu);
5769 vmx_fpu_activate(vcpu);
5771 case 1: /*mov from cr*/
5774 val = kvm_read_cr3(vcpu);
5775 kvm_register_write(vcpu, reg, val);
5776 trace_kvm_cr_read(cr, val);
5777 skip_emulated_instruction(vcpu);
5780 val = kvm_get_cr8(vcpu);
5781 kvm_register_write(vcpu, reg, val);
5782 trace_kvm_cr_read(cr, val);
5783 skip_emulated_instruction(vcpu);
5788 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5789 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5790 kvm_lmsw(vcpu, val);
5792 skip_emulated_instruction(vcpu);
5797 vcpu->run->exit_reason = 0;
5798 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5799 (int)(exit_qualification >> 4) & 3, cr);
5803 static int handle_dr(struct kvm_vcpu *vcpu)
5805 unsigned long exit_qualification;
5808 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5809 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5811 /* First, if DR does not exist, trigger UD */
5812 if (!kvm_require_dr(vcpu, dr))
5815 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5816 if (!kvm_require_cpl(vcpu, 0))
5818 dr7 = vmcs_readl(GUEST_DR7);
5821 * As the vm-exit takes precedence over the debug trap, we
5822 * need to emulate the latter, either for the host or the
5823 * guest debugging itself.
5825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5826 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5827 vcpu->run->debug.arch.dr7 = dr7;
5828 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5829 vcpu->run->debug.arch.exception = DB_VECTOR;
5830 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5833 vcpu->arch.dr6 &= ~15;
5834 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5835 kvm_queue_exception(vcpu, DB_VECTOR);
5840 if (vcpu->guest_debug == 0) {
5841 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5842 CPU_BASED_MOV_DR_EXITING);
5845 * No more DR vmexits; force a reload of the debug registers
5846 * and reenter on this instruction. The next vmexit will
5847 * retrieve the full state of the debug registers.
5849 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5853 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5854 if (exit_qualification & TYPE_MOV_FROM_DR) {
5857 if (kvm_get_dr(vcpu, dr, &val))
5859 kvm_register_write(vcpu, reg, val);
5861 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5864 skip_emulated_instruction(vcpu);
5868 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5870 return vcpu->arch.dr6;
5873 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5877 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5879 get_debugreg(vcpu->arch.db[0], 0);
5880 get_debugreg(vcpu->arch.db[1], 1);
5881 get_debugreg(vcpu->arch.db[2], 2);
5882 get_debugreg(vcpu->arch.db[3], 3);
5883 get_debugreg(vcpu->arch.dr6, 6);
5884 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5886 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5887 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5890 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5892 vmcs_writel(GUEST_DR7, val);
5895 static int handle_cpuid(struct kvm_vcpu *vcpu)
5897 kvm_emulate_cpuid(vcpu);
5901 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5903 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5904 struct msr_data msr_info;
5906 msr_info.index = ecx;
5907 msr_info.host_initiated = false;
5908 if (vmx_get_msr(vcpu, &msr_info)) {
5909 trace_kvm_msr_read_ex(ecx);
5910 kvm_inject_gp(vcpu, 0);
5914 trace_kvm_msr_read(ecx, msr_info.data);
5916 /* FIXME: handling of bits 32:63 of rax, rdx */
5917 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5918 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5919 skip_emulated_instruction(vcpu);
5923 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5925 struct msr_data msr;
5926 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5927 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5928 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5932 msr.host_initiated = false;
5933 if (kvm_set_msr(vcpu, &msr) != 0) {
5934 trace_kvm_msr_write_ex(ecx, data);
5935 kvm_inject_gp(vcpu, 0);
5939 trace_kvm_msr_write(ecx, data);
5940 skip_emulated_instruction(vcpu);
5944 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5946 kvm_make_request(KVM_REQ_EVENT, vcpu);
5950 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5952 u32 cpu_based_vm_exec_control;
5954 /* clear pending irq */
5955 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5956 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5957 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5959 kvm_make_request(KVM_REQ_EVENT, vcpu);
5961 ++vcpu->stat.irq_window_exits;
5965 static int handle_halt(struct kvm_vcpu *vcpu)
5967 return kvm_emulate_halt(vcpu);
5970 static int handle_vmcall(struct kvm_vcpu *vcpu)
5972 return kvm_emulate_hypercall(vcpu);
5975 static int handle_invd(struct kvm_vcpu *vcpu)
5977 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5980 static int handle_invlpg(struct kvm_vcpu *vcpu)
5982 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5984 kvm_mmu_invlpg(vcpu, exit_qualification);
5985 skip_emulated_instruction(vcpu);
5989 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5993 err = kvm_rdpmc(vcpu);
5994 kvm_complete_insn_gp(vcpu, err);
5999 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6001 kvm_emulate_wbinvd(vcpu);
6005 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6007 u64 new_bv = kvm_read_edx_eax(vcpu);
6008 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6010 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6011 skip_emulated_instruction(vcpu);
6015 static int handle_xsaves(struct kvm_vcpu *vcpu)
6017 skip_emulated_instruction(vcpu);
6018 WARN(1, "this should never happen\n");
6022 static int handle_xrstors(struct kvm_vcpu *vcpu)
6024 skip_emulated_instruction(vcpu);
6025 WARN(1, "this should never happen\n");
6029 static int handle_apic_access(struct kvm_vcpu *vcpu)
6031 if (likely(fasteoi)) {
6032 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6033 int access_type, offset;
6035 access_type = exit_qualification & APIC_ACCESS_TYPE;
6036 offset = exit_qualification & APIC_ACCESS_OFFSET;
6038 * Sane guest uses MOV to write EOI, with written value
6039 * not cared. So make a short-circuit here by avoiding
6040 * heavy instruction emulation.
6042 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6043 (offset == APIC_EOI)) {
6044 kvm_lapic_set_eoi(vcpu);
6045 skip_emulated_instruction(vcpu);
6049 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6052 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6054 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6055 int vector = exit_qualification & 0xff;
6057 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6058 kvm_apic_set_eoi_accelerated(vcpu, vector);
6062 static int handle_apic_write(struct kvm_vcpu *vcpu)
6064 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6065 u32 offset = exit_qualification & 0xfff;
6067 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6068 kvm_apic_write_nodecode(vcpu, offset);
6072 static int handle_task_switch(struct kvm_vcpu *vcpu)
6074 struct vcpu_vmx *vmx = to_vmx(vcpu);
6075 unsigned long exit_qualification;
6076 bool has_error_code = false;
6079 int reason, type, idt_v, idt_index;
6081 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6082 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6083 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6085 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6087 reason = (u32)exit_qualification >> 30;
6088 if (reason == TASK_SWITCH_GATE && idt_v) {
6090 case INTR_TYPE_NMI_INTR:
6091 vcpu->arch.nmi_injected = false;
6092 vmx_set_nmi_mask(vcpu, true);
6094 case INTR_TYPE_EXT_INTR:
6095 case INTR_TYPE_SOFT_INTR:
6096 kvm_clear_interrupt_queue(vcpu);
6098 case INTR_TYPE_HARD_EXCEPTION:
6099 if (vmx->idt_vectoring_info &
6100 VECTORING_INFO_DELIVER_CODE_MASK) {
6101 has_error_code = true;
6103 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6106 case INTR_TYPE_SOFT_EXCEPTION:
6107 kvm_clear_exception_queue(vcpu);
6113 tss_selector = exit_qualification;
6115 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6116 type != INTR_TYPE_EXT_INTR &&
6117 type != INTR_TYPE_NMI_INTR))
6118 skip_emulated_instruction(vcpu);
6120 if (kvm_task_switch(vcpu, tss_selector,
6121 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6122 has_error_code, error_code) == EMULATE_FAIL) {
6123 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6124 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6125 vcpu->run->internal.ndata = 0;
6130 * TODO: What about debug traps on tss switch?
6131 * Are we supposed to inject them and update dr6?
6137 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6139 unsigned long exit_qualification;
6144 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6146 gla_validity = (exit_qualification >> 7) & 0x3;
6147 if (gla_validity == 0x2) {
6148 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6149 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6150 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6151 vmcs_readl(GUEST_LINEAR_ADDRESS));
6152 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6153 (long unsigned int)exit_qualification);
6154 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6155 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6160 * EPT violation happened while executing iret from NMI,
6161 * "blocked by NMI" bit has to be set before next VM entry.
6162 * There are errata that may cause this bit to not be set:
6165 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6166 cpu_has_virtual_nmis() &&
6167 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6168 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6170 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6171 trace_kvm_page_fault(gpa, exit_qualification);
6173 /* it is a read fault? */
6174 error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6175 /* it is a write fault? */
6176 error_code |= exit_qualification & PFERR_WRITE_MASK;
6177 /* It is a fetch fault? */
6178 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6179 /* ept page table is present? */
6180 error_code |= (exit_qualification & 0x38) != 0;
6182 vcpu->arch.exit_qualification = exit_qualification;
6184 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6187 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6192 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6193 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6194 skip_emulated_instruction(vcpu);
6195 trace_kvm_fast_mmio(gpa);
6199 ret = handle_mmio_page_fault(vcpu, gpa, true);
6200 if (likely(ret == RET_MMIO_PF_EMULATE))
6201 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6204 if (unlikely(ret == RET_MMIO_PF_INVALID))
6205 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6207 if (unlikely(ret == RET_MMIO_PF_RETRY))
6210 /* It is the real ept misconfig */
6213 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6214 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6219 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6221 u32 cpu_based_vm_exec_control;
6223 /* clear pending NMI */
6224 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6225 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6226 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6227 ++vcpu->stat.nmi_window_exits;
6228 kvm_make_request(KVM_REQ_EVENT, vcpu);
6233 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6235 struct vcpu_vmx *vmx = to_vmx(vcpu);
6236 enum emulation_result err = EMULATE_DONE;
6239 bool intr_window_requested;
6240 unsigned count = 130;
6242 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6243 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6245 while (vmx->emulation_required && count-- != 0) {
6246 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6247 return handle_interrupt_window(&vmx->vcpu);
6249 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6252 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6254 if (err == EMULATE_USER_EXIT) {
6255 ++vcpu->stat.mmio_exits;
6260 if (err != EMULATE_DONE) {
6261 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6262 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6263 vcpu->run->internal.ndata = 0;
6267 if (vcpu->arch.halt_request) {
6268 vcpu->arch.halt_request = 0;
6269 ret = kvm_vcpu_halt(vcpu);
6273 if (signal_pending(current))
6283 static int __grow_ple_window(int val)
6285 if (ple_window_grow < 1)
6288 val = min(val, ple_window_actual_max);
6290 if (ple_window_grow < ple_window)
6291 val *= ple_window_grow;
6293 val += ple_window_grow;
6298 static int __shrink_ple_window(int val, int modifier, int minimum)
6303 if (modifier < ple_window)
6308 return max(val, minimum);
6311 static void grow_ple_window(struct kvm_vcpu *vcpu)
6313 struct vcpu_vmx *vmx = to_vmx(vcpu);
6314 int old = vmx->ple_window;
6316 vmx->ple_window = __grow_ple_window(old);
6318 if (vmx->ple_window != old)
6319 vmx->ple_window_dirty = true;
6321 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6324 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6326 struct vcpu_vmx *vmx = to_vmx(vcpu);
6327 int old = vmx->ple_window;
6329 vmx->ple_window = __shrink_ple_window(old,
6330 ple_window_shrink, ple_window);
6332 if (vmx->ple_window != old)
6333 vmx->ple_window_dirty = true;
6335 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6339 * ple_window_actual_max is computed to be one grow_ple_window() below
6340 * ple_window_max. (See __grow_ple_window for the reason.)
6341 * This prevents overflows, because ple_window_max is int.
6342 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6344 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6346 static void update_ple_window_actual_max(void)
6348 ple_window_actual_max =
6349 __shrink_ple_window(max(ple_window_max, ple_window),
6350 ple_window_grow, INT_MIN);
6354 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6356 static void wakeup_handler(void)
6358 struct kvm_vcpu *vcpu;
6359 int cpu = smp_processor_id();
6361 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6362 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6363 blocked_vcpu_list) {
6364 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6366 if (pi_test_on(pi_desc) == 1)
6367 kvm_vcpu_kick(vcpu);
6369 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6372 static __init int hardware_setup(void)
6374 int r = -ENOMEM, i, msr;
6376 rdmsrl_safe(MSR_EFER, &host_efer);
6378 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6379 kvm_define_shared_msr(i, vmx_msr_index[i]);
6381 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6382 if (!vmx_io_bitmap_a)
6385 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6386 if (!vmx_io_bitmap_b)
6389 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6390 if (!vmx_msr_bitmap_legacy)
6393 vmx_msr_bitmap_legacy_x2apic =
6394 (unsigned long *)__get_free_page(GFP_KERNEL);
6395 if (!vmx_msr_bitmap_legacy_x2apic)
6398 vmx_msr_bitmap_legacy_x2apic_apicv_inactive =
6399 (unsigned long *)__get_free_page(GFP_KERNEL);
6400 if (!vmx_msr_bitmap_legacy_x2apic_apicv_inactive)
6403 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6404 if (!vmx_msr_bitmap_longmode)
6407 vmx_msr_bitmap_longmode_x2apic =
6408 (unsigned long *)__get_free_page(GFP_KERNEL);
6409 if (!vmx_msr_bitmap_longmode_x2apic)
6412 vmx_msr_bitmap_longmode_x2apic_apicv_inactive =
6413 (unsigned long *)__get_free_page(GFP_KERNEL);
6414 if (!vmx_msr_bitmap_longmode_x2apic_apicv_inactive)
6417 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6418 if (!vmx_vmread_bitmap)
6421 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6422 if (!vmx_vmwrite_bitmap)
6425 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6426 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6429 * Allow direct access to the PC debug port (it is often used for I/O
6430 * delays, but the vmexits simply slow things down).
6432 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6433 clear_bit(0x80, vmx_io_bitmap_a);
6435 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6437 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6438 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6440 if (setup_vmcs_config(&vmcs_config) < 0) {
6445 if (boot_cpu_has(X86_FEATURE_NX))
6446 kvm_enable_efer_bits(EFER_NX);
6448 if (!cpu_has_vmx_vpid())
6450 if (!cpu_has_vmx_shadow_vmcs())
6451 enable_shadow_vmcs = 0;
6452 if (enable_shadow_vmcs)
6453 init_vmcs_shadow_fields();
6455 if (!cpu_has_vmx_ept() ||
6456 !cpu_has_vmx_ept_4levels()) {
6458 enable_unrestricted_guest = 0;
6459 enable_ept_ad_bits = 0;
6462 if (!cpu_has_vmx_ept_ad_bits())
6463 enable_ept_ad_bits = 0;
6465 if (!cpu_has_vmx_unrestricted_guest())
6466 enable_unrestricted_guest = 0;
6468 if (!cpu_has_vmx_flexpriority())
6469 flexpriority_enabled = 0;
6472 * set_apic_access_page_addr() is used to reload apic access
6473 * page upon invalidation. No need to do anything if not
6474 * using the APIC_ACCESS_ADDR VMCS field.
6476 if (!flexpriority_enabled)
6477 kvm_x86_ops->set_apic_access_page_addr = NULL;
6479 if (!cpu_has_vmx_tpr_shadow())
6480 kvm_x86_ops->update_cr8_intercept = NULL;
6482 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6483 kvm_disable_largepages();
6485 if (!cpu_has_vmx_ple())
6488 if (!cpu_has_vmx_apicv())
6491 if (cpu_has_vmx_tsc_scaling()) {
6492 kvm_has_tsc_control = true;
6493 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6494 kvm_tsc_scaling_ratio_frac_bits = 48;
6497 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6498 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6499 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6500 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6501 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6502 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6503 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6505 memcpy(vmx_msr_bitmap_legacy_x2apic,
6506 vmx_msr_bitmap_legacy, PAGE_SIZE);
6507 memcpy(vmx_msr_bitmap_longmode_x2apic,
6508 vmx_msr_bitmap_longmode, PAGE_SIZE);
6509 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv_inactive,
6510 vmx_msr_bitmap_legacy, PAGE_SIZE);
6511 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv_inactive,
6512 vmx_msr_bitmap_longmode, PAGE_SIZE);
6514 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6517 * enable_apicv && kvm_vcpu_apicv_active()
6519 for (msr = 0x800; msr <= 0x8ff; msr++)
6520 vmx_disable_intercept_msr_read_x2apic(msr, true);
6523 vmx_enable_intercept_msr_read_x2apic(0x839, true);
6525 vmx_disable_intercept_msr_write_x2apic(0x808, true);
6527 vmx_disable_intercept_msr_write_x2apic(0x80b, true);
6529 vmx_disable_intercept_msr_write_x2apic(0x83f, true);
6532 * (enable_apicv && !kvm_vcpu_apicv_active()) ||
6536 vmx_disable_intercept_msr_read_x2apic(0x808, false);
6537 vmx_disable_intercept_msr_write_x2apic(0x808, false);
6540 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6541 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6542 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6543 0ull, VMX_EPT_EXECUTABLE_MASK,
6544 cpu_has_vmx_ept_execute_only() ?
6545 0ull : VMX_EPT_READABLE_MASK);
6546 ept_set_mmio_spte_mask();
6551 update_ple_window_actual_max();
6554 * Only enable PML when hardware supports PML feature, and both EPT
6555 * and EPT A/D bit features are enabled -- PML depends on them to work.
6557 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6561 kvm_x86_ops->slot_enable_log_dirty = NULL;
6562 kvm_x86_ops->slot_disable_log_dirty = NULL;
6563 kvm_x86_ops->flush_log_dirty = NULL;
6564 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6567 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6570 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6571 cpu_preemption_timer_multi =
6572 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6574 kvm_x86_ops->set_hv_timer = NULL;
6575 kvm_x86_ops->cancel_hv_timer = NULL;
6578 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6580 kvm_mce_cap_supported |= MCG_LMCE_P;
6582 return alloc_kvm_area();
6585 free_page((unsigned long)vmx_vmwrite_bitmap);
6587 free_page((unsigned long)vmx_vmread_bitmap);
6589 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic_apicv_inactive);
6591 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6593 free_page((unsigned long)vmx_msr_bitmap_longmode);
6595 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic_apicv_inactive);
6597 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6599 free_page((unsigned long)vmx_msr_bitmap_legacy);
6601 free_page((unsigned long)vmx_io_bitmap_b);
6603 free_page((unsigned long)vmx_io_bitmap_a);
6608 static __exit void hardware_unsetup(void)
6610 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6611 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic_apicv_inactive);
6612 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6613 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic_apicv_inactive);
6614 free_page((unsigned long)vmx_msr_bitmap_legacy);
6615 free_page((unsigned long)vmx_msr_bitmap_longmode);
6616 free_page((unsigned long)vmx_io_bitmap_b);
6617 free_page((unsigned long)vmx_io_bitmap_a);
6618 free_page((unsigned long)vmx_vmwrite_bitmap);
6619 free_page((unsigned long)vmx_vmread_bitmap);
6625 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6626 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6628 static int handle_pause(struct kvm_vcpu *vcpu)
6631 grow_ple_window(vcpu);
6633 skip_emulated_instruction(vcpu);
6634 kvm_vcpu_on_spin(vcpu);
6639 static int handle_nop(struct kvm_vcpu *vcpu)
6641 skip_emulated_instruction(vcpu);
6645 static int handle_mwait(struct kvm_vcpu *vcpu)
6647 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6648 return handle_nop(vcpu);
6651 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6656 static int handle_monitor(struct kvm_vcpu *vcpu)
6658 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6659 return handle_nop(vcpu);
6663 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6664 * We could reuse a single VMCS for all the L2 guests, but we also want the
6665 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6666 * allows keeping them loaded on the processor, and in the future will allow
6667 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6668 * every entry if they never change.
6669 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6670 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6672 * The following functions allocate and free a vmcs02 in this pool.
6675 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6676 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6678 struct vmcs02_list *item;
6679 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6680 if (item->vmptr == vmx->nested.current_vmptr) {
6681 list_move(&item->list, &vmx->nested.vmcs02_pool);
6682 return &item->vmcs02;
6685 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6686 /* Recycle the least recently used VMCS. */
6687 item = list_last_entry(&vmx->nested.vmcs02_pool,
6688 struct vmcs02_list, list);
6689 item->vmptr = vmx->nested.current_vmptr;
6690 list_move(&item->list, &vmx->nested.vmcs02_pool);
6691 return &item->vmcs02;
6694 /* Create a new VMCS */
6695 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6698 item->vmcs02.vmcs = alloc_vmcs();
6699 if (!item->vmcs02.vmcs) {
6703 loaded_vmcs_init(&item->vmcs02);
6704 item->vmptr = vmx->nested.current_vmptr;
6705 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6706 vmx->nested.vmcs02_num++;
6707 return &item->vmcs02;
6710 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6711 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6713 struct vmcs02_list *item;
6714 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6715 if (item->vmptr == vmptr) {
6716 free_loaded_vmcs(&item->vmcs02);
6717 list_del(&item->list);
6719 vmx->nested.vmcs02_num--;
6725 * Free all VMCSs saved for this vcpu, except the one pointed by
6726 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6727 * must be &vmx->vmcs01.
6729 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6731 struct vmcs02_list *item, *n;
6733 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6734 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6736 * Something will leak if the above WARN triggers. Better than
6739 if (vmx->loaded_vmcs == &item->vmcs02)
6742 free_loaded_vmcs(&item->vmcs02);
6743 list_del(&item->list);
6745 vmx->nested.vmcs02_num--;
6750 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6751 * set the success or error code of an emulated VMX instruction, as specified
6752 * by Vol 2B, VMX Instruction Reference, "Conventions".
6754 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6756 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6757 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6758 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6761 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6763 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6764 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6765 X86_EFLAGS_SF | X86_EFLAGS_OF))
6769 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6770 u32 vm_instruction_error)
6772 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6774 * failValid writes the error number to the current VMCS, which
6775 * can't be done there isn't a current VMCS.
6777 nested_vmx_failInvalid(vcpu);
6780 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6781 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6782 X86_EFLAGS_SF | X86_EFLAGS_OF))
6784 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6786 * We don't need to force a shadow sync because
6787 * VM_INSTRUCTION_ERROR is not shadowed
6791 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6793 /* TODO: not to reset guest simply here. */
6794 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6795 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6798 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6800 struct vcpu_vmx *vmx =
6801 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6803 vmx->nested.preemption_timer_expired = true;
6804 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6805 kvm_vcpu_kick(&vmx->vcpu);
6807 return HRTIMER_NORESTART;
6811 * Decode the memory-address operand of a vmx instruction, as recorded on an
6812 * exit caused by such an instruction (run by a guest hypervisor).
6813 * On success, returns 0. When the operand is invalid, returns 1 and throws
6816 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6817 unsigned long exit_qualification,
6818 u32 vmx_instruction_info, bool wr, gva_t *ret)
6822 struct kvm_segment s;
6825 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6826 * Execution", on an exit, vmx_instruction_info holds most of the
6827 * addressing components of the operand. Only the displacement part
6828 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6829 * For how an actual address is calculated from all these components,
6830 * refer to Vol. 1, "Operand Addressing".
6832 int scaling = vmx_instruction_info & 3;
6833 int addr_size = (vmx_instruction_info >> 7) & 7;
6834 bool is_reg = vmx_instruction_info & (1u << 10);
6835 int seg_reg = (vmx_instruction_info >> 15) & 7;
6836 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6837 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6838 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6839 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6842 kvm_queue_exception(vcpu, UD_VECTOR);
6846 /* Addr = segment_base + offset */
6847 /* offset = base + [index * scale] + displacement */
6848 off = exit_qualification; /* holds the displacement */
6850 off += kvm_register_read(vcpu, base_reg);
6852 off += kvm_register_read(vcpu, index_reg)<<scaling;
6853 vmx_get_segment(vcpu, &s, seg_reg);
6854 *ret = s.base + off;
6856 if (addr_size == 1) /* 32 bit */
6859 /* Checks for #GP/#SS exceptions. */
6861 if (is_long_mode(vcpu)) {
6862 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6863 * non-canonical form. This is the only check on the memory
6864 * destination for long mode!
6866 exn = is_noncanonical_address(*ret);
6867 } else if (is_protmode(vcpu)) {
6868 /* Protected mode: apply checks for segment validity in the
6870 * - segment type check (#GP(0) may be thrown)
6871 * - usability check (#GP(0)/#SS(0))
6872 * - limit check (#GP(0)/#SS(0))
6875 /* #GP(0) if the destination operand is located in a
6876 * read-only data segment or any code segment.
6878 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6880 /* #GP(0) if the source operand is located in an
6881 * execute-only code segment
6883 exn = ((s.type & 0xa) == 8);
6885 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6888 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6890 exn = (s.unusable != 0);
6891 /* Protected mode: #GP(0)/#SS(0) if the memory
6892 * operand is outside the segment limit.
6894 exn = exn || (off + sizeof(u64) > s.limit);
6897 kvm_queue_exception_e(vcpu,
6898 seg_reg == VCPU_SREG_SS ?
6899 SS_VECTOR : GP_VECTOR,
6908 * This function performs the various checks including
6909 * - if it's 4KB aligned
6910 * - No bits beyond the physical address width are set
6911 * - Returns 0 on success or else 1
6912 * (Intel SDM Section 30.3)
6914 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6919 struct x86_exception e;
6921 struct vcpu_vmx *vmx = to_vmx(vcpu);
6922 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6924 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6925 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6928 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6929 sizeof(vmptr), &e)) {
6930 kvm_inject_page_fault(vcpu, &e);
6934 switch (exit_reason) {
6935 case EXIT_REASON_VMON:
6938 * The first 4 bytes of VMXON region contain the supported
6939 * VMCS revision identifier
6941 * Note - IA32_VMX_BASIC[48] will never be 1
6942 * for the nested case;
6943 * which replaces physical address width with 32
6946 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6947 nested_vmx_failInvalid(vcpu);
6948 skip_emulated_instruction(vcpu);
6952 page = nested_get_page(vcpu, vmptr);
6954 *(u32 *)kmap(page) != VMCS12_REVISION) {
6955 nested_vmx_failInvalid(vcpu);
6957 skip_emulated_instruction(vcpu);
6961 vmx->nested.vmxon_ptr = vmptr;
6963 case EXIT_REASON_VMCLEAR:
6964 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6965 nested_vmx_failValid(vcpu,
6966 VMXERR_VMCLEAR_INVALID_ADDRESS);
6967 skip_emulated_instruction(vcpu);
6971 if (vmptr == vmx->nested.vmxon_ptr) {
6972 nested_vmx_failValid(vcpu,
6973 VMXERR_VMCLEAR_VMXON_POINTER);
6974 skip_emulated_instruction(vcpu);
6978 case EXIT_REASON_VMPTRLD:
6979 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6980 nested_vmx_failValid(vcpu,
6981 VMXERR_VMPTRLD_INVALID_ADDRESS);
6982 skip_emulated_instruction(vcpu);
6986 if (vmptr == vmx->nested.vmxon_ptr) {
6987 nested_vmx_failValid(vcpu,
6988 VMXERR_VMCLEAR_VMXON_POINTER);
6989 skip_emulated_instruction(vcpu);
6994 return 1; /* shouldn't happen */
7003 * Emulate the VMXON instruction.
7004 * Currently, we just remember that VMX is active, and do not save or even
7005 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7006 * do not currently need to store anything in that guest-allocated memory
7007 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7008 * argument is different from the VMXON pointer (which the spec says they do).
7010 static int handle_vmon(struct kvm_vcpu *vcpu)
7012 struct kvm_segment cs;
7013 struct vcpu_vmx *vmx = to_vmx(vcpu);
7014 struct vmcs *shadow_vmcs;
7015 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7016 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7018 /* The Intel VMX Instruction Reference lists a bunch of bits that
7019 * are prerequisite to running VMXON, most notably cr4.VMXE must be
7020 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7021 * Otherwise, we should fail with #UD. We test these now:
7023 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7024 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7025 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7026 kvm_queue_exception(vcpu, UD_VECTOR);
7030 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7031 if (is_long_mode(vcpu) && !cs.l) {
7032 kvm_queue_exception(vcpu, UD_VECTOR);
7036 if (vmx_get_cpl(vcpu)) {
7037 kvm_inject_gp(vcpu, 0);
7041 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7044 if (vmx->nested.vmxon) {
7045 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7046 skip_emulated_instruction(vcpu);
7050 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7051 != VMXON_NEEDED_FEATURES) {
7052 kvm_inject_gp(vcpu, 0);
7056 if (cpu_has_vmx_msr_bitmap()) {
7057 vmx->nested.msr_bitmap =
7058 (unsigned long *)__get_free_page(GFP_KERNEL);
7059 if (!vmx->nested.msr_bitmap)
7060 goto out_msr_bitmap;
7063 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7064 if (!vmx->nested.cached_vmcs12)
7065 goto out_cached_vmcs12;
7067 if (enable_shadow_vmcs) {
7068 shadow_vmcs = alloc_vmcs();
7070 goto out_shadow_vmcs;
7071 /* mark vmcs as shadow */
7072 shadow_vmcs->revision_id |= (1u << 31);
7073 /* init shadow vmcs */
7074 vmcs_clear(shadow_vmcs);
7075 vmx->nested.current_shadow_vmcs = shadow_vmcs;
7078 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7079 vmx->nested.vmcs02_num = 0;
7081 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7082 HRTIMER_MODE_REL_PINNED);
7083 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7085 vmx->nested.vmxon = true;
7087 skip_emulated_instruction(vcpu);
7088 nested_vmx_succeed(vcpu);
7092 kfree(vmx->nested.cached_vmcs12);
7095 free_page((unsigned long)vmx->nested.msr_bitmap);
7102 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7103 * for running VMX instructions (except VMXON, whose prerequisites are
7104 * slightly different). It also specifies what exception to inject otherwise.
7106 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7108 struct kvm_segment cs;
7109 struct vcpu_vmx *vmx = to_vmx(vcpu);
7111 if (!vmx->nested.vmxon) {
7112 kvm_queue_exception(vcpu, UD_VECTOR);
7116 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7117 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7118 (is_long_mode(vcpu) && !cs.l)) {
7119 kvm_queue_exception(vcpu, UD_VECTOR);
7123 if (vmx_get_cpl(vcpu)) {
7124 kvm_inject_gp(vcpu, 0);
7131 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7133 if (vmx->nested.current_vmptr == -1ull)
7136 /* current_vmptr and current_vmcs12 are always set/reset together */
7137 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7140 if (enable_shadow_vmcs) {
7141 /* copy to memory all shadowed fields in case
7142 they were modified */
7143 copy_shadow_to_vmcs12(vmx);
7144 vmx->nested.sync_shadow_vmcs = false;
7145 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7146 SECONDARY_EXEC_SHADOW_VMCS);
7147 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7149 vmx->nested.posted_intr_nv = -1;
7151 /* Flush VMCS12 to guest memory */
7152 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7155 kunmap(vmx->nested.current_vmcs12_page);
7156 nested_release_page(vmx->nested.current_vmcs12_page);
7157 vmx->nested.current_vmptr = -1ull;
7158 vmx->nested.current_vmcs12 = NULL;
7162 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7163 * just stops using VMX.
7165 static void free_nested(struct vcpu_vmx *vmx)
7167 if (!vmx->nested.vmxon)
7170 vmx->nested.vmxon = false;
7171 free_vpid(vmx->nested.vpid02);
7172 nested_release_vmcs12(vmx);
7173 if (vmx->nested.msr_bitmap) {
7174 free_page((unsigned long)vmx->nested.msr_bitmap);
7175 vmx->nested.msr_bitmap = NULL;
7177 if (enable_shadow_vmcs)
7178 free_vmcs(vmx->nested.current_shadow_vmcs);
7179 kfree(vmx->nested.cached_vmcs12);
7180 /* Unpin physical memory we referred to in current vmcs02 */
7181 if (vmx->nested.apic_access_page) {
7182 nested_release_page(vmx->nested.apic_access_page);
7183 vmx->nested.apic_access_page = NULL;
7185 if (vmx->nested.virtual_apic_page) {
7186 nested_release_page(vmx->nested.virtual_apic_page);
7187 vmx->nested.virtual_apic_page = NULL;
7189 if (vmx->nested.pi_desc_page) {
7190 kunmap(vmx->nested.pi_desc_page);
7191 nested_release_page(vmx->nested.pi_desc_page);
7192 vmx->nested.pi_desc_page = NULL;
7193 vmx->nested.pi_desc = NULL;
7196 nested_free_all_saved_vmcss(vmx);
7199 /* Emulate the VMXOFF instruction */
7200 static int handle_vmoff(struct kvm_vcpu *vcpu)
7202 if (!nested_vmx_check_permission(vcpu))
7204 free_nested(to_vmx(vcpu));
7205 skip_emulated_instruction(vcpu);
7206 nested_vmx_succeed(vcpu);
7210 /* Emulate the VMCLEAR instruction */
7211 static int handle_vmclear(struct kvm_vcpu *vcpu)
7213 struct vcpu_vmx *vmx = to_vmx(vcpu);
7215 struct vmcs12 *vmcs12;
7218 if (!nested_vmx_check_permission(vcpu))
7221 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7224 if (vmptr == vmx->nested.current_vmptr)
7225 nested_release_vmcs12(vmx);
7227 page = nested_get_page(vcpu, vmptr);
7230 * For accurate processor emulation, VMCLEAR beyond available
7231 * physical memory should do nothing at all. However, it is
7232 * possible that a nested vmx bug, not a guest hypervisor bug,
7233 * resulted in this case, so let's shut down before doing any
7236 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7239 vmcs12 = kmap(page);
7240 vmcs12->launch_state = 0;
7242 nested_release_page(page);
7244 nested_free_vmcs02(vmx, vmptr);
7246 skip_emulated_instruction(vcpu);
7247 nested_vmx_succeed(vcpu);
7251 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7253 /* Emulate the VMLAUNCH instruction */
7254 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7256 return nested_vmx_run(vcpu, true);
7259 /* Emulate the VMRESUME instruction */
7260 static int handle_vmresume(struct kvm_vcpu *vcpu)
7263 return nested_vmx_run(vcpu, false);
7266 enum vmcs_field_type {
7267 VMCS_FIELD_TYPE_U16 = 0,
7268 VMCS_FIELD_TYPE_U64 = 1,
7269 VMCS_FIELD_TYPE_U32 = 2,
7270 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7273 static inline int vmcs_field_type(unsigned long field)
7275 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7276 return VMCS_FIELD_TYPE_U32;
7277 return (field >> 13) & 0x3 ;
7280 static inline int vmcs_field_readonly(unsigned long field)
7282 return (((field >> 10) & 0x3) == 1);
7286 * Read a vmcs12 field. Since these can have varying lengths and we return
7287 * one type, we chose the biggest type (u64) and zero-extend the return value
7288 * to that size. Note that the caller, handle_vmread, might need to use only
7289 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7290 * 64-bit fields are to be returned).
7292 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7293 unsigned long field, u64 *ret)
7295 short offset = vmcs_field_to_offset(field);
7301 p = ((char *)(get_vmcs12(vcpu))) + offset;
7303 switch (vmcs_field_type(field)) {
7304 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7305 *ret = *((natural_width *)p);
7307 case VMCS_FIELD_TYPE_U16:
7310 case VMCS_FIELD_TYPE_U32:
7313 case VMCS_FIELD_TYPE_U64:
7323 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7324 unsigned long field, u64 field_value){
7325 short offset = vmcs_field_to_offset(field);
7326 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7330 switch (vmcs_field_type(field)) {
7331 case VMCS_FIELD_TYPE_U16:
7332 *(u16 *)p = field_value;
7334 case VMCS_FIELD_TYPE_U32:
7335 *(u32 *)p = field_value;
7337 case VMCS_FIELD_TYPE_U64:
7338 *(u64 *)p = field_value;
7340 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7341 *(natural_width *)p = field_value;
7350 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7353 unsigned long field;
7355 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7356 const unsigned long *fields = shadow_read_write_fields;
7357 const int num_fields = max_shadow_read_write_fields;
7361 vmcs_load(shadow_vmcs);
7363 for (i = 0; i < num_fields; i++) {
7365 switch (vmcs_field_type(field)) {
7366 case VMCS_FIELD_TYPE_U16:
7367 field_value = vmcs_read16(field);
7369 case VMCS_FIELD_TYPE_U32:
7370 field_value = vmcs_read32(field);
7372 case VMCS_FIELD_TYPE_U64:
7373 field_value = vmcs_read64(field);
7375 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7376 field_value = vmcs_readl(field);
7382 vmcs12_write_any(&vmx->vcpu, field, field_value);
7385 vmcs_clear(shadow_vmcs);
7386 vmcs_load(vmx->loaded_vmcs->vmcs);
7391 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7393 const unsigned long *fields[] = {
7394 shadow_read_write_fields,
7395 shadow_read_only_fields
7397 const int max_fields[] = {
7398 max_shadow_read_write_fields,
7399 max_shadow_read_only_fields
7402 unsigned long field;
7403 u64 field_value = 0;
7404 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7406 vmcs_load(shadow_vmcs);
7408 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7409 for (i = 0; i < max_fields[q]; i++) {
7410 field = fields[q][i];
7411 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7413 switch (vmcs_field_type(field)) {
7414 case VMCS_FIELD_TYPE_U16:
7415 vmcs_write16(field, (u16)field_value);
7417 case VMCS_FIELD_TYPE_U32:
7418 vmcs_write32(field, (u32)field_value);
7420 case VMCS_FIELD_TYPE_U64:
7421 vmcs_write64(field, (u64)field_value);
7423 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7424 vmcs_writel(field, (long)field_value);
7433 vmcs_clear(shadow_vmcs);
7434 vmcs_load(vmx->loaded_vmcs->vmcs);
7438 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7439 * used before) all generate the same failure when it is missing.
7441 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7443 struct vcpu_vmx *vmx = to_vmx(vcpu);
7444 if (vmx->nested.current_vmptr == -1ull) {
7445 nested_vmx_failInvalid(vcpu);
7446 skip_emulated_instruction(vcpu);
7452 static int handle_vmread(struct kvm_vcpu *vcpu)
7454 unsigned long field;
7456 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7457 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7460 if (!nested_vmx_check_permission(vcpu) ||
7461 !nested_vmx_check_vmcs12(vcpu))
7464 /* Decode instruction info and find the field to read */
7465 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7466 /* Read the field, zero-extended to a u64 field_value */
7467 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7468 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7469 skip_emulated_instruction(vcpu);
7473 * Now copy part of this value to register or memory, as requested.
7474 * Note that the number of bits actually copied is 32 or 64 depending
7475 * on the guest's mode (32 or 64 bit), not on the given field's length.
7477 if (vmx_instruction_info & (1u << 10)) {
7478 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7481 if (get_vmx_mem_address(vcpu, exit_qualification,
7482 vmx_instruction_info, true, &gva))
7484 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7485 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7486 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7489 nested_vmx_succeed(vcpu);
7490 skip_emulated_instruction(vcpu);
7495 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7497 unsigned long field;
7499 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7500 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7501 /* The value to write might be 32 or 64 bits, depending on L1's long
7502 * mode, and eventually we need to write that into a field of several
7503 * possible lengths. The code below first zero-extends the value to 64
7504 * bit (field_value), and then copies only the appropriate number of
7505 * bits into the vmcs12 field.
7507 u64 field_value = 0;
7508 struct x86_exception e;
7510 if (!nested_vmx_check_permission(vcpu) ||
7511 !nested_vmx_check_vmcs12(vcpu))
7514 if (vmx_instruction_info & (1u << 10))
7515 field_value = kvm_register_readl(vcpu,
7516 (((vmx_instruction_info) >> 3) & 0xf));
7518 if (get_vmx_mem_address(vcpu, exit_qualification,
7519 vmx_instruction_info, false, &gva))
7521 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7522 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7523 kvm_inject_page_fault(vcpu, &e);
7529 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7530 if (vmcs_field_readonly(field)) {
7531 nested_vmx_failValid(vcpu,
7532 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7533 skip_emulated_instruction(vcpu);
7537 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7538 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7539 skip_emulated_instruction(vcpu);
7543 nested_vmx_succeed(vcpu);
7544 skip_emulated_instruction(vcpu);
7548 /* Emulate the VMPTRLD instruction */
7549 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7551 struct vcpu_vmx *vmx = to_vmx(vcpu);
7554 if (!nested_vmx_check_permission(vcpu))
7557 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7560 if (vmx->nested.current_vmptr != vmptr) {
7561 struct vmcs12 *new_vmcs12;
7563 page = nested_get_page(vcpu, vmptr);
7565 nested_vmx_failInvalid(vcpu);
7566 skip_emulated_instruction(vcpu);
7569 new_vmcs12 = kmap(page);
7570 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7572 nested_release_page_clean(page);
7573 nested_vmx_failValid(vcpu,
7574 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7575 skip_emulated_instruction(vcpu);
7579 nested_release_vmcs12(vmx);
7580 vmx->nested.current_vmptr = vmptr;
7581 vmx->nested.current_vmcs12 = new_vmcs12;
7582 vmx->nested.current_vmcs12_page = page;
7584 * Load VMCS12 from guest memory since it is not already
7587 memcpy(vmx->nested.cached_vmcs12,
7588 vmx->nested.current_vmcs12, VMCS12_SIZE);
7590 if (enable_shadow_vmcs) {
7591 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7592 SECONDARY_EXEC_SHADOW_VMCS);
7593 vmcs_write64(VMCS_LINK_POINTER,
7594 __pa(vmx->nested.current_shadow_vmcs));
7595 vmx->nested.sync_shadow_vmcs = true;
7599 nested_vmx_succeed(vcpu);
7600 skip_emulated_instruction(vcpu);
7604 /* Emulate the VMPTRST instruction */
7605 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7607 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7608 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7610 struct x86_exception e;
7612 if (!nested_vmx_check_permission(vcpu))
7615 if (get_vmx_mem_address(vcpu, exit_qualification,
7616 vmx_instruction_info, true, &vmcs_gva))
7618 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7619 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7620 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7622 kvm_inject_page_fault(vcpu, &e);
7625 nested_vmx_succeed(vcpu);
7626 skip_emulated_instruction(vcpu);
7630 /* Emulate the INVEPT instruction */
7631 static int handle_invept(struct kvm_vcpu *vcpu)
7633 struct vcpu_vmx *vmx = to_vmx(vcpu);
7634 u32 vmx_instruction_info, types;
7637 struct x86_exception e;
7642 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7643 SECONDARY_EXEC_ENABLE_EPT) ||
7644 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7645 kvm_queue_exception(vcpu, UD_VECTOR);
7649 if (!nested_vmx_check_permission(vcpu))
7652 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7653 kvm_queue_exception(vcpu, UD_VECTOR);
7657 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7658 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7660 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7662 if (!(types & (1UL << type))) {
7663 nested_vmx_failValid(vcpu,
7664 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7665 skip_emulated_instruction(vcpu);
7669 /* According to the Intel VMX instruction reference, the memory
7670 * operand is read even if it isn't needed (e.g., for type==global)
7672 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7673 vmx_instruction_info, false, &gva))
7675 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7676 sizeof(operand), &e)) {
7677 kvm_inject_page_fault(vcpu, &e);
7682 case VMX_EPT_EXTENT_GLOBAL:
7684 * TODO: track mappings and invalidate
7685 * single context requests appropriately
7687 case VMX_EPT_EXTENT_CONTEXT:
7688 kvm_mmu_sync_roots(vcpu);
7689 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7690 nested_vmx_succeed(vcpu);
7697 skip_emulated_instruction(vcpu);
7701 static int handle_invvpid(struct kvm_vcpu *vcpu)
7703 struct vcpu_vmx *vmx = to_vmx(vcpu);
7704 u32 vmx_instruction_info;
7705 unsigned long type, types;
7707 struct x86_exception e;
7710 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7711 SECONDARY_EXEC_ENABLE_VPID) ||
7712 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7713 kvm_queue_exception(vcpu, UD_VECTOR);
7717 if (!nested_vmx_check_permission(vcpu))
7720 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7721 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7723 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7725 if (!(types & (1UL << type))) {
7726 nested_vmx_failValid(vcpu,
7727 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7728 skip_emulated_instruction(vcpu);
7732 /* according to the intel vmx instruction reference, the memory
7733 * operand is read even if it isn't needed (e.g., for type==global)
7735 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7736 vmx_instruction_info, false, &gva))
7738 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7740 kvm_inject_page_fault(vcpu, &e);
7745 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7747 * Old versions of KVM use the single-context version so we
7748 * have to support it; just treat it the same as all-context.
7750 case VMX_VPID_EXTENT_ALL_CONTEXT:
7751 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7752 nested_vmx_succeed(vcpu);
7755 /* Trap individual address invalidation invvpid calls */
7760 skip_emulated_instruction(vcpu);
7764 static int handle_pml_full(struct kvm_vcpu *vcpu)
7766 unsigned long exit_qualification;
7768 trace_kvm_pml_full(vcpu->vcpu_id);
7770 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7773 * PML buffer FULL happened while executing iret from NMI,
7774 * "blocked by NMI" bit has to be set before next VM entry.
7776 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7777 cpu_has_virtual_nmis() &&
7778 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7779 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7780 GUEST_INTR_STATE_NMI);
7783 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7784 * here.., and there's no userspace involvement needed for PML.
7789 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7791 kvm_lapic_expired_hv_timer(vcpu);
7796 * The exit handlers return 1 if the exit was handled fully and guest execution
7797 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7798 * to be done to userspace and return 0.
7800 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7801 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7802 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7803 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7804 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7805 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7806 [EXIT_REASON_CR_ACCESS] = handle_cr,
7807 [EXIT_REASON_DR_ACCESS] = handle_dr,
7808 [EXIT_REASON_CPUID] = handle_cpuid,
7809 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7810 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7811 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7812 [EXIT_REASON_HLT] = handle_halt,
7813 [EXIT_REASON_INVD] = handle_invd,
7814 [EXIT_REASON_INVLPG] = handle_invlpg,
7815 [EXIT_REASON_RDPMC] = handle_rdpmc,
7816 [EXIT_REASON_VMCALL] = handle_vmcall,
7817 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7818 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7819 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7820 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7821 [EXIT_REASON_VMREAD] = handle_vmread,
7822 [EXIT_REASON_VMRESUME] = handle_vmresume,
7823 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7824 [EXIT_REASON_VMOFF] = handle_vmoff,
7825 [EXIT_REASON_VMON] = handle_vmon,
7826 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7827 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7828 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7829 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7830 [EXIT_REASON_WBINVD] = handle_wbinvd,
7831 [EXIT_REASON_XSETBV] = handle_xsetbv,
7832 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7833 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7834 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7835 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7836 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7837 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7838 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7839 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7840 [EXIT_REASON_INVEPT] = handle_invept,
7841 [EXIT_REASON_INVVPID] = handle_invvpid,
7842 [EXIT_REASON_XSAVES] = handle_xsaves,
7843 [EXIT_REASON_XRSTORS] = handle_xrstors,
7844 [EXIT_REASON_PML_FULL] = handle_pml_full,
7845 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7848 static const int kvm_vmx_max_exit_handlers =
7849 ARRAY_SIZE(kvm_vmx_exit_handlers);
7851 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7852 struct vmcs12 *vmcs12)
7854 unsigned long exit_qualification;
7855 gpa_t bitmap, last_bitmap;
7860 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7861 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7863 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7865 port = exit_qualification >> 16;
7866 size = (exit_qualification & 7) + 1;
7868 last_bitmap = (gpa_t)-1;
7873 bitmap = vmcs12->io_bitmap_a;
7874 else if (port < 0x10000)
7875 bitmap = vmcs12->io_bitmap_b;
7878 bitmap += (port & 0x7fff) / 8;
7880 if (last_bitmap != bitmap)
7881 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7883 if (b & (1 << (port & 7)))
7888 last_bitmap = bitmap;
7895 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7896 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7897 * disinterest in the current event (read or write a specific MSR) by using an
7898 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7900 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7901 struct vmcs12 *vmcs12, u32 exit_reason)
7903 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7906 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7910 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7911 * for the four combinations of read/write and low/high MSR numbers.
7912 * First we need to figure out which of the four to use:
7914 bitmap = vmcs12->msr_bitmap;
7915 if (exit_reason == EXIT_REASON_MSR_WRITE)
7917 if (msr_index >= 0xc0000000) {
7918 msr_index -= 0xc0000000;
7922 /* Then read the msr_index'th bit from this bitmap: */
7923 if (msr_index < 1024*8) {
7925 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7927 return 1 & (b >> (msr_index & 7));
7929 return true; /* let L1 handle the wrong parameter */
7933 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7934 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7935 * intercept (via guest_host_mask etc.) the current event.
7937 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7938 struct vmcs12 *vmcs12)
7940 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7941 int cr = exit_qualification & 15;
7942 int reg = (exit_qualification >> 8) & 15;
7943 unsigned long val = kvm_register_readl(vcpu, reg);
7945 switch ((exit_qualification >> 4) & 3) {
7946 case 0: /* mov to cr */
7949 if (vmcs12->cr0_guest_host_mask &
7950 (val ^ vmcs12->cr0_read_shadow))
7954 if ((vmcs12->cr3_target_count >= 1 &&
7955 vmcs12->cr3_target_value0 == val) ||
7956 (vmcs12->cr3_target_count >= 2 &&
7957 vmcs12->cr3_target_value1 == val) ||
7958 (vmcs12->cr3_target_count >= 3 &&
7959 vmcs12->cr3_target_value2 == val) ||
7960 (vmcs12->cr3_target_count >= 4 &&
7961 vmcs12->cr3_target_value3 == val))
7963 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7967 if (vmcs12->cr4_guest_host_mask &
7968 (vmcs12->cr4_read_shadow ^ val))
7972 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7978 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7979 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7982 case 1: /* mov from cr */
7985 if (vmcs12->cpu_based_vm_exec_control &
7986 CPU_BASED_CR3_STORE_EXITING)
7990 if (vmcs12->cpu_based_vm_exec_control &
7991 CPU_BASED_CR8_STORE_EXITING)
7998 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7999 * cr0. Other attempted changes are ignored, with no exit.
8001 if (vmcs12->cr0_guest_host_mask & 0xe &
8002 (val ^ vmcs12->cr0_read_shadow))
8004 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8005 !(vmcs12->cr0_read_shadow & 0x1) &&
8014 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8015 * should handle it ourselves in L0 (and then continue L2). Only call this
8016 * when in is_guest_mode (L2).
8018 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8020 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8021 struct vcpu_vmx *vmx = to_vmx(vcpu);
8022 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8023 u32 exit_reason = vmx->exit_reason;
8025 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8026 vmcs_readl(EXIT_QUALIFICATION),
8027 vmx->idt_vectoring_info,
8029 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8032 if (vmx->nested.nested_run_pending)
8035 if (unlikely(vmx->fail)) {
8036 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8037 vmcs_read32(VM_INSTRUCTION_ERROR));
8041 switch (exit_reason) {
8042 case EXIT_REASON_EXCEPTION_NMI:
8043 if (!is_exception(intr_info))
8045 else if (is_page_fault(intr_info))
8047 else if (is_no_device(intr_info) &&
8048 !(vmcs12->guest_cr0 & X86_CR0_TS))
8050 else if (is_debug(intr_info) &&
8052 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8054 else if (is_breakpoint(intr_info) &&
8055 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8057 return vmcs12->exception_bitmap &
8058 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8059 case EXIT_REASON_EXTERNAL_INTERRUPT:
8061 case EXIT_REASON_TRIPLE_FAULT:
8063 case EXIT_REASON_PENDING_INTERRUPT:
8064 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8065 case EXIT_REASON_NMI_WINDOW:
8066 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8067 case EXIT_REASON_TASK_SWITCH:
8069 case EXIT_REASON_CPUID:
8070 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
8073 case EXIT_REASON_HLT:
8074 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8075 case EXIT_REASON_INVD:
8077 case EXIT_REASON_INVLPG:
8078 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8079 case EXIT_REASON_RDPMC:
8080 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8081 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8082 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8083 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8084 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8085 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8086 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8087 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8088 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8090 * VMX instructions trap unconditionally. This allows L1 to
8091 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8094 case EXIT_REASON_CR_ACCESS:
8095 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8096 case EXIT_REASON_DR_ACCESS:
8097 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8098 case EXIT_REASON_IO_INSTRUCTION:
8099 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8100 case EXIT_REASON_MSR_READ:
8101 case EXIT_REASON_MSR_WRITE:
8102 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8103 case EXIT_REASON_INVALID_STATE:
8105 case EXIT_REASON_MWAIT_INSTRUCTION:
8106 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8107 case EXIT_REASON_MONITOR_TRAP_FLAG:
8108 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8109 case EXIT_REASON_MONITOR_INSTRUCTION:
8110 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8111 case EXIT_REASON_PAUSE_INSTRUCTION:
8112 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8113 nested_cpu_has2(vmcs12,
8114 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8115 case EXIT_REASON_MCE_DURING_VMENTRY:
8117 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8118 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8119 case EXIT_REASON_APIC_ACCESS:
8120 return nested_cpu_has2(vmcs12,
8121 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8122 case EXIT_REASON_APIC_WRITE:
8123 case EXIT_REASON_EOI_INDUCED:
8124 /* apic_write and eoi_induced should exit unconditionally. */
8126 case EXIT_REASON_EPT_VIOLATION:
8128 * L0 always deals with the EPT violation. If nested EPT is
8129 * used, and the nested mmu code discovers that the address is
8130 * missing in the guest EPT table (EPT12), the EPT violation
8131 * will be injected with nested_ept_inject_page_fault()
8134 case EXIT_REASON_EPT_MISCONFIG:
8136 * L2 never uses directly L1's EPT, but rather L0's own EPT
8137 * table (shadow on EPT) or a merged EPT table that L0 built
8138 * (EPT on EPT). So any problems with the structure of the
8139 * table is L0's fault.
8142 case EXIT_REASON_WBINVD:
8143 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8144 case EXIT_REASON_XSETBV:
8146 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8148 * This should never happen, since it is not possible to
8149 * set XSS to a non-zero value---neither in L1 nor in L2.
8150 * If if it were, XSS would have to be checked against
8151 * the XSS exit bitmap in vmcs12.
8153 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8154 case EXIT_REASON_PREEMPTION_TIMER:
8161 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8163 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8164 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8167 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8170 __free_page(vmx->pml_pg);
8175 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8177 struct vcpu_vmx *vmx = to_vmx(vcpu);
8181 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8183 /* Do nothing if PML buffer is empty */
8184 if (pml_idx == (PML_ENTITY_NUM - 1))
8187 /* PML index always points to next available PML buffer entity */
8188 if (pml_idx >= PML_ENTITY_NUM)
8193 pml_buf = page_address(vmx->pml_pg);
8194 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8197 gpa = pml_buf[pml_idx];
8198 WARN_ON(gpa & (PAGE_SIZE - 1));
8199 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8202 /* reset PML index */
8203 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8207 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8208 * Called before reporting dirty_bitmap to userspace.
8210 static void kvm_flush_pml_buffers(struct kvm *kvm)
8213 struct kvm_vcpu *vcpu;
8215 * We only need to kick vcpu out of guest mode here, as PML buffer
8216 * is flushed at beginning of all VMEXITs, and it's obvious that only
8217 * vcpus running in guest are possible to have unflushed GPAs in PML
8220 kvm_for_each_vcpu(i, vcpu, kvm)
8221 kvm_vcpu_kick(vcpu);
8224 static void vmx_dump_sel(char *name, uint32_t sel)
8226 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8227 name, vmcs_read32(sel),
8228 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8229 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8230 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8233 static void vmx_dump_dtsel(char *name, uint32_t limit)
8235 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8236 name, vmcs_read32(limit),
8237 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8240 static void dump_vmcs(void)
8242 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8243 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8244 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8245 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8246 u32 secondary_exec_control = 0;
8247 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8248 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8251 if (cpu_has_secondary_exec_ctrls())
8252 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8254 pr_err("*** Guest State ***\n");
8255 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8256 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8257 vmcs_readl(CR0_GUEST_HOST_MASK));
8258 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8259 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8260 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8261 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8262 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8264 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8265 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8266 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8267 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8269 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8270 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8271 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8272 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8273 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8274 vmcs_readl(GUEST_SYSENTER_ESP),
8275 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8276 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8277 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8278 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8279 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8280 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8281 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8282 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8283 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8284 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8285 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8286 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8287 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8288 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8289 efer, vmcs_read64(GUEST_IA32_PAT));
8290 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8291 vmcs_read64(GUEST_IA32_DEBUGCTL),
8292 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8293 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8294 pr_err("PerfGlobCtl = 0x%016llx\n",
8295 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8296 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8297 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8298 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8299 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8300 vmcs_read32(GUEST_ACTIVITY_STATE));
8301 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8302 pr_err("InterruptStatus = %04x\n",
8303 vmcs_read16(GUEST_INTR_STATUS));
8305 pr_err("*** Host State ***\n");
8306 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8307 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8308 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8309 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8310 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8311 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8312 vmcs_read16(HOST_TR_SELECTOR));
8313 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8314 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8315 vmcs_readl(HOST_TR_BASE));
8316 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8317 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8318 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8319 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8320 vmcs_readl(HOST_CR4));
8321 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8322 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8323 vmcs_read32(HOST_IA32_SYSENTER_CS),
8324 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8325 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8326 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8327 vmcs_read64(HOST_IA32_EFER),
8328 vmcs_read64(HOST_IA32_PAT));
8329 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8330 pr_err("PerfGlobCtl = 0x%016llx\n",
8331 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8333 pr_err("*** Control State ***\n");
8334 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8335 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8336 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8337 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8338 vmcs_read32(EXCEPTION_BITMAP),
8339 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8340 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8341 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8342 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8343 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8344 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8345 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8346 vmcs_read32(VM_EXIT_INTR_INFO),
8347 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8348 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8349 pr_err(" reason=%08x qualification=%016lx\n",
8350 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8351 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8352 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8353 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8354 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8355 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8356 pr_err("TSC Multiplier = 0x%016llx\n",
8357 vmcs_read64(TSC_MULTIPLIER));
8358 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8359 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8360 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8361 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8362 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8363 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8364 n = vmcs_read32(CR3_TARGET_COUNT);
8365 for (i = 0; i + 1 < n; i += 4)
8366 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8367 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8368 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8370 pr_err("CR3 target%u=%016lx\n",
8371 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8372 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8373 pr_err("PLE Gap=%08x Window=%08x\n",
8374 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8375 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8376 pr_err("Virtual processor ID = 0x%04x\n",
8377 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8381 * The guest has exited. See if we can fix it or if we need userspace
8384 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8386 struct vcpu_vmx *vmx = to_vmx(vcpu);
8387 u32 exit_reason = vmx->exit_reason;
8388 u32 vectoring_info = vmx->idt_vectoring_info;
8390 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8393 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8394 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8395 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8396 * mode as if vcpus is in root mode, the PML buffer must has been
8400 vmx_flush_pml_buffer(vcpu);
8402 /* If guest state is invalid, start emulating */
8403 if (vmx->emulation_required)
8404 return handle_invalid_guest_state(vcpu);
8406 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8407 nested_vmx_vmexit(vcpu, exit_reason,
8408 vmcs_read32(VM_EXIT_INTR_INFO),
8409 vmcs_readl(EXIT_QUALIFICATION));
8413 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8415 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8416 vcpu->run->fail_entry.hardware_entry_failure_reason
8421 if (unlikely(vmx->fail)) {
8422 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8423 vcpu->run->fail_entry.hardware_entry_failure_reason
8424 = vmcs_read32(VM_INSTRUCTION_ERROR);
8430 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8431 * delivery event since it indicates guest is accessing MMIO.
8432 * The vm-exit can be triggered again after return to guest that
8433 * will cause infinite loop.
8435 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8436 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8437 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8438 exit_reason != EXIT_REASON_PML_FULL &&
8439 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8440 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8441 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8442 vcpu->run->internal.ndata = 2;
8443 vcpu->run->internal.data[0] = vectoring_info;
8444 vcpu->run->internal.data[1] = exit_reason;
8448 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8449 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8450 get_vmcs12(vcpu))))) {
8451 if (vmx_interrupt_allowed(vcpu)) {
8452 vmx->soft_vnmi_blocked = 0;
8453 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8454 vcpu->arch.nmi_pending) {
8456 * This CPU don't support us in finding the end of an
8457 * NMI-blocked window if the guest runs with IRQs
8458 * disabled. So we pull the trigger after 1 s of
8459 * futile waiting, but inform the user about this.
8461 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8462 "state on VCPU %d after 1 s timeout\n",
8463 __func__, vcpu->vcpu_id);
8464 vmx->soft_vnmi_blocked = 0;
8468 if (exit_reason < kvm_vmx_max_exit_handlers
8469 && kvm_vmx_exit_handlers[exit_reason])
8470 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8472 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8473 kvm_queue_exception(vcpu, UD_VECTOR);
8478 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8480 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8482 if (is_guest_mode(vcpu) &&
8483 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8486 if (irr == -1 || tpr < irr) {
8487 vmcs_write32(TPR_THRESHOLD, 0);
8491 vmcs_write32(TPR_THRESHOLD, irr);
8494 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8496 u32 sec_exec_control;
8498 /* Postpone execution until vmcs01 is the current VMCS. */
8499 if (is_guest_mode(vcpu)) {
8500 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8504 if (!cpu_has_vmx_virtualize_x2apic_mode())
8507 if (!cpu_need_tpr_shadow(vcpu))
8510 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8513 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8514 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8516 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8517 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8519 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8521 vmx_set_msr_bitmap(vcpu);
8524 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8526 struct vcpu_vmx *vmx = to_vmx(vcpu);
8529 * Currently we do not handle the nested case where L2 has an
8530 * APIC access page of its own; that page is still pinned.
8531 * Hence, we skip the case where the VCPU is in guest mode _and_
8532 * L1 prepared an APIC access page for L2.
8534 * For the case where L1 and L2 share the same APIC access page
8535 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8536 * in the vmcs12), this function will only update either the vmcs01
8537 * or the vmcs02. If the former, the vmcs02 will be updated by
8538 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8539 * the next L2->L1 exit.
8541 if (!is_guest_mode(vcpu) ||
8542 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8543 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8544 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8547 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8555 status = vmcs_read16(GUEST_INTR_STATUS);
8557 if (max_isr != old) {
8559 status |= max_isr << 8;
8560 vmcs_write16(GUEST_INTR_STATUS, status);
8564 static void vmx_set_rvi(int vector)
8572 status = vmcs_read16(GUEST_INTR_STATUS);
8573 old = (u8)status & 0xff;
8574 if ((u8)vector != old) {
8576 status |= (u8)vector;
8577 vmcs_write16(GUEST_INTR_STATUS, status);
8581 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8583 if (!is_guest_mode(vcpu)) {
8584 vmx_set_rvi(max_irr);
8592 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8595 if (nested_exit_on_intr(vcpu))
8599 * Else, fall back to pre-APICv interrupt injection since L2
8600 * is run without virtual interrupt delivery.
8602 if (!kvm_event_needs_reinjection(vcpu) &&
8603 vmx_interrupt_allowed(vcpu)) {
8604 kvm_queue_interrupt(vcpu, max_irr, false);
8605 vmx_inject_irq(vcpu);
8609 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8611 if (!kvm_vcpu_apicv_active(vcpu))
8614 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8615 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8616 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8617 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8620 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8624 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8625 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8628 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8629 exit_intr_info = vmx->exit_intr_info;
8631 /* Handle machine checks before interrupts are enabled */
8632 if (is_machine_check(exit_intr_info))
8633 kvm_machine_check();
8635 /* We need to handle NMIs before interrupts are enabled */
8636 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8637 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8638 kvm_before_handle_nmi(&vmx->vcpu);
8640 kvm_after_handle_nmi(&vmx->vcpu);
8644 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8646 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8647 register void *__sp asm(_ASM_SP);
8650 * If external interrupt exists, IF bit is set in rflags/eflags on the
8651 * interrupt stack frame, and interrupt will be enabled on a return
8652 * from interrupt handler.
8654 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8655 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8656 unsigned int vector;
8657 unsigned long entry;
8659 struct vcpu_vmx *vmx = to_vmx(vcpu);
8660 #ifdef CONFIG_X86_64
8664 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8665 desc = (gate_desc *)vmx->host_idt_base + vector;
8666 entry = gate_offset(*desc);
8668 #ifdef CONFIG_X86_64
8669 "mov %%" _ASM_SP ", %[sp]\n\t"
8670 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8675 __ASM_SIZE(push) " $%c[cs]\n\t"
8676 "call *%[entry]\n\t"
8678 #ifdef CONFIG_X86_64
8684 [ss]"i"(__KERNEL_DS),
8685 [cs]"i"(__KERNEL_CS)
8690 static bool vmx_has_high_real_mode_segbase(void)
8692 return enable_unrestricted_guest || emulate_invalid_guest_state;
8695 static bool vmx_mpx_supported(void)
8697 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8698 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8701 static bool vmx_xsaves_supported(void)
8703 return vmcs_config.cpu_based_2nd_exec_ctrl &
8704 SECONDARY_EXEC_XSAVES;
8707 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8712 bool idtv_info_valid;
8714 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8716 if (cpu_has_virtual_nmis()) {
8717 if (vmx->nmi_known_unmasked)
8720 * Can't use vmx->exit_intr_info since we're not sure what
8721 * the exit reason is.
8723 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8724 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8725 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8727 * SDM 3: 27.7.1.2 (September 2008)
8728 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8729 * a guest IRET fault.
8730 * SDM 3: 23.2.2 (September 2008)
8731 * Bit 12 is undefined in any of the following cases:
8732 * If the VM exit sets the valid bit in the IDT-vectoring
8733 * information field.
8734 * If the VM exit is due to a double fault.
8736 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8737 vector != DF_VECTOR && !idtv_info_valid)
8738 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8739 GUEST_INTR_STATE_NMI);
8741 vmx->nmi_known_unmasked =
8742 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8743 & GUEST_INTR_STATE_NMI);
8744 } else if (unlikely(vmx->soft_vnmi_blocked))
8745 vmx->vnmi_blocked_time +=
8746 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8749 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8750 u32 idt_vectoring_info,
8751 int instr_len_field,
8752 int error_code_field)
8756 bool idtv_info_valid;
8758 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8760 vcpu->arch.nmi_injected = false;
8761 kvm_clear_exception_queue(vcpu);
8762 kvm_clear_interrupt_queue(vcpu);
8764 if (!idtv_info_valid)
8767 kvm_make_request(KVM_REQ_EVENT, vcpu);
8769 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8770 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8773 case INTR_TYPE_NMI_INTR:
8774 vcpu->arch.nmi_injected = true;
8776 * SDM 3: 27.7.1.2 (September 2008)
8777 * Clear bit "block by NMI" before VM entry if a NMI
8780 vmx_set_nmi_mask(vcpu, false);
8782 case INTR_TYPE_SOFT_EXCEPTION:
8783 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8785 case INTR_TYPE_HARD_EXCEPTION:
8786 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8787 u32 err = vmcs_read32(error_code_field);
8788 kvm_requeue_exception_e(vcpu, vector, err);
8790 kvm_requeue_exception(vcpu, vector);
8792 case INTR_TYPE_SOFT_INTR:
8793 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8795 case INTR_TYPE_EXT_INTR:
8796 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8803 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8805 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8806 VM_EXIT_INSTRUCTION_LEN,
8807 IDT_VECTORING_ERROR_CODE);
8810 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8812 __vmx_complete_interrupts(vcpu,
8813 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8814 VM_ENTRY_INSTRUCTION_LEN,
8815 VM_ENTRY_EXCEPTION_ERROR_CODE);
8817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8820 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8823 struct perf_guest_switch_msr *msrs;
8825 msrs = perf_guest_get_msrs(&nr_msrs);
8830 for (i = 0; i < nr_msrs; i++)
8831 if (msrs[i].host == msrs[i].guest)
8832 clear_atomic_switch_msr(vmx, msrs[i].msr);
8834 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8838 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8840 struct vcpu_vmx *vmx = to_vmx(vcpu);
8844 if (vmx->hv_deadline_tsc == -1)
8848 if (vmx->hv_deadline_tsc > tscl)
8849 /* sure to be 32 bit only because checked on set_hv_timer */
8850 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8851 cpu_preemption_timer_multi);
8855 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8858 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8860 struct vcpu_vmx *vmx = to_vmx(vcpu);
8861 unsigned long debugctlmsr, cr4;
8863 /* Record the guest's net vcpu time for enforced NMI injections. */
8864 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8865 vmx->entry_time = ktime_get();
8867 /* Don't enter VMX if guest state is invalid, let the exit handler
8868 start emulation until we arrive back to a valid state */
8869 if (vmx->emulation_required)
8872 if (vmx->ple_window_dirty) {
8873 vmx->ple_window_dirty = false;
8874 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8877 if (vmx->nested.sync_shadow_vmcs) {
8878 copy_vmcs12_to_shadow(vmx);
8879 vmx->nested.sync_shadow_vmcs = false;
8882 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8883 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8884 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8885 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8887 cr4 = cr4_read_shadow();
8888 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8889 vmcs_writel(HOST_CR4, cr4);
8890 vmx->host_state.vmcs_host_cr4 = cr4;
8893 /* When single-stepping over STI and MOV SS, we must clear the
8894 * corresponding interruptibility bits in the guest state. Otherwise
8895 * vmentry fails as it then expects bit 14 (BS) in pending debug
8896 * exceptions being set, but that's not correct for the guest debugging
8898 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8899 vmx_set_interrupt_shadow(vcpu, 0);
8901 if (vmx->guest_pkru_valid)
8902 __write_pkru(vmx->guest_pkru);
8904 atomic_switch_perf_msrs(vmx);
8905 debugctlmsr = get_debugctlmsr();
8907 vmx_arm_hv_timer(vcpu);
8909 vmx->__launched = vmx->loaded_vmcs->launched;
8911 /* Store host registers */
8912 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8913 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8914 "push %%" _ASM_CX " \n\t"
8915 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8917 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8918 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8920 /* Reload cr2 if changed */
8921 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8922 "mov %%cr2, %%" _ASM_DX " \n\t"
8923 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8925 "mov %%" _ASM_AX", %%cr2 \n\t"
8927 /* Check if vmlaunch of vmresume is needed */
8928 "cmpl $0, %c[launched](%0) \n\t"
8929 /* Load guest registers. Don't clobber flags. */
8930 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8931 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8932 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8933 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8934 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8935 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8936 #ifdef CONFIG_X86_64
8937 "mov %c[r8](%0), %%r8 \n\t"
8938 "mov %c[r9](%0), %%r9 \n\t"
8939 "mov %c[r10](%0), %%r10 \n\t"
8940 "mov %c[r11](%0), %%r11 \n\t"
8941 "mov %c[r12](%0), %%r12 \n\t"
8942 "mov %c[r13](%0), %%r13 \n\t"
8943 "mov %c[r14](%0), %%r14 \n\t"
8944 "mov %c[r15](%0), %%r15 \n\t"
8946 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8948 /* Enter guest mode */
8950 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8952 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8954 /* Save guest registers, load host registers, keep flags */
8955 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8957 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8958 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8959 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8960 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8961 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8962 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8963 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8964 #ifdef CONFIG_X86_64
8965 "mov %%r8, %c[r8](%0) \n\t"
8966 "mov %%r9, %c[r9](%0) \n\t"
8967 "mov %%r10, %c[r10](%0) \n\t"
8968 "mov %%r11, %c[r11](%0) \n\t"
8969 "mov %%r12, %c[r12](%0) \n\t"
8970 "mov %%r13, %c[r13](%0) \n\t"
8971 "mov %%r14, %c[r14](%0) \n\t"
8972 "mov %%r15, %c[r15](%0) \n\t"
8974 "mov %%cr2, %%" _ASM_AX " \n\t"
8975 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8977 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8978 "setbe %c[fail](%0) \n\t"
8979 ".pushsection .rodata \n\t"
8980 ".global vmx_return \n\t"
8981 "vmx_return: " _ASM_PTR " 2b \n\t"
8983 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8984 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8985 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8986 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8987 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8988 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8989 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8990 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8991 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8992 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8993 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8994 #ifdef CONFIG_X86_64
8995 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8996 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8997 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8998 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8999 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9000 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9001 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9002 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9004 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9005 [wordsize]"i"(sizeof(ulong))
9007 #ifdef CONFIG_X86_64
9008 , "rax", "rbx", "rdi", "rsi"
9009 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9011 , "eax", "ebx", "edi", "esi"
9015 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9017 update_debugctlmsr(debugctlmsr);
9019 #ifndef CONFIG_X86_64
9021 * The sysexit path does not restore ds/es, so we must set them to
9022 * a reasonable value ourselves.
9024 * We can't defer this to vmx_load_host_state() since that function
9025 * may be executed in interrupt context, which saves and restore segments
9026 * around it, nullifying its effect.
9028 loadsegment(ds, __USER_DS);
9029 loadsegment(es, __USER_DS);
9032 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9033 | (1 << VCPU_EXREG_RFLAGS)
9034 | (1 << VCPU_EXREG_PDPTR)
9035 | (1 << VCPU_EXREG_SEGMENTS)
9036 | (1 << VCPU_EXREG_CR3));
9037 vcpu->arch.regs_dirty = 0;
9039 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9041 vmx->loaded_vmcs->launched = 1;
9043 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9046 * eager fpu is enabled if PKEY is supported and CR4 is switched
9047 * back on host, so it is safe to read guest PKRU from current
9050 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9051 vmx->guest_pkru = __read_pkru();
9052 if (vmx->guest_pkru != vmx->host_pkru) {
9053 vmx->guest_pkru_valid = true;
9054 __write_pkru(vmx->host_pkru);
9056 vmx->guest_pkru_valid = false;
9060 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9061 * we did not inject a still-pending event to L1 now because of
9062 * nested_run_pending, we need to re-enable this bit.
9064 if (vmx->nested.nested_run_pending)
9065 kvm_make_request(KVM_REQ_EVENT, vcpu);
9067 vmx->nested.nested_run_pending = 0;
9069 vmx_complete_atomic_exit(vmx);
9070 vmx_recover_nmi_blocking(vmx);
9071 vmx_complete_interrupts(vmx);
9074 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9076 struct vcpu_vmx *vmx = to_vmx(vcpu);
9079 if (vmx->loaded_vmcs == &vmx->vmcs01)
9083 vmx->loaded_vmcs = &vmx->vmcs01;
9085 vmx_vcpu_load(vcpu, cpu);
9091 * Ensure that the current vmcs of the logical processor is the
9092 * vmcs01 of the vcpu before calling free_nested().
9094 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9096 struct vcpu_vmx *vmx = to_vmx(vcpu);
9099 r = vcpu_load(vcpu);
9101 vmx_load_vmcs01(vcpu);
9106 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9108 struct vcpu_vmx *vmx = to_vmx(vcpu);
9111 vmx_destroy_pml_buffer(vmx);
9112 free_vpid(vmx->vpid);
9113 leave_guest_mode(vcpu);
9114 vmx_free_vcpu_nested(vcpu);
9115 free_loaded_vmcs(vmx->loaded_vmcs);
9116 kfree(vmx->guest_msrs);
9117 kvm_vcpu_uninit(vcpu);
9118 kmem_cache_free(kvm_vcpu_cache, vmx);
9121 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9124 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9128 return ERR_PTR(-ENOMEM);
9130 vmx->vpid = allocate_vpid();
9132 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9139 * If PML is turned on, failure on enabling PML just results in failure
9140 * of creating the vcpu, therefore we can simplify PML logic (by
9141 * avoiding dealing with cases, such as enabling PML partially on vcpus
9142 * for the guest, etc.
9145 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9150 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9151 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9154 if (!vmx->guest_msrs)
9157 vmx->loaded_vmcs = &vmx->vmcs01;
9158 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9159 if (!vmx->loaded_vmcs->vmcs)
9162 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9163 loaded_vmcs_init(vmx->loaded_vmcs);
9168 vmx_vcpu_load(&vmx->vcpu, cpu);
9169 vmx->vcpu.cpu = cpu;
9170 err = vmx_vcpu_setup(vmx);
9171 vmx_vcpu_put(&vmx->vcpu);
9175 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9176 err = alloc_apic_access_page(kvm);
9182 if (!kvm->arch.ept_identity_map_addr)
9183 kvm->arch.ept_identity_map_addr =
9184 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9185 err = init_rmode_identity_map(kvm);
9191 nested_vmx_setup_ctls_msrs(vmx);
9192 vmx->nested.vpid02 = allocate_vpid();
9195 vmx->nested.posted_intr_nv = -1;
9196 vmx->nested.current_vmptr = -1ull;
9197 vmx->nested.current_vmcs12 = NULL;
9199 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9204 free_vpid(vmx->nested.vpid02);
9205 free_loaded_vmcs(vmx->loaded_vmcs);
9207 kfree(vmx->guest_msrs);
9209 vmx_destroy_pml_buffer(vmx);
9211 kvm_vcpu_uninit(&vmx->vcpu);
9213 free_vpid(vmx->vpid);
9214 kmem_cache_free(kvm_vcpu_cache, vmx);
9215 return ERR_PTR(err);
9218 static void __init vmx_check_processor_compat(void *rtn)
9220 struct vmcs_config vmcs_conf;
9223 if (setup_vmcs_config(&vmcs_conf) < 0)
9225 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9226 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9227 smp_processor_id());
9232 static int get_ept_level(void)
9234 return VMX_EPT_DEFAULT_GAW + 1;
9237 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9242 /* For VT-d and EPT combination
9243 * 1. MMIO: always map as UC
9245 * a. VT-d without snooping control feature: can't guarantee the
9246 * result, try to trust guest.
9247 * b. VT-d with snooping control feature: snooping control feature of
9248 * VT-d engine can guarantee the cache correctness. Just set it
9249 * to WB to keep consistent with host. So the same as item 3.
9250 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9251 * consistent with host MTRR
9254 cache = MTRR_TYPE_UNCACHABLE;
9258 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9259 ipat = VMX_EPT_IPAT_BIT;
9260 cache = MTRR_TYPE_WRBACK;
9264 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9265 ipat = VMX_EPT_IPAT_BIT;
9266 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9267 cache = MTRR_TYPE_WRBACK;
9269 cache = MTRR_TYPE_UNCACHABLE;
9273 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9276 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9279 static int vmx_get_lpage_level(void)
9281 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9282 return PT_DIRECTORY_LEVEL;
9284 /* For shadow and EPT supported 1GB page */
9285 return PT_PDPE_LEVEL;
9288 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9291 * These bits in the secondary execution controls field
9292 * are dynamic, the others are mostly based on the hypervisor
9293 * architecture and the guest's CPUID. Do not touch the
9297 SECONDARY_EXEC_SHADOW_VMCS |
9298 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9299 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9301 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9303 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9304 (new_ctl & ~mask) | (cur_ctl & mask));
9307 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9309 struct kvm_cpuid_entry2 *best;
9310 struct vcpu_vmx *vmx = to_vmx(vcpu);
9311 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9313 if (vmx_rdtscp_supported()) {
9314 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9315 if (!rdtscp_enabled)
9316 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9320 vmx->nested.nested_vmx_secondary_ctls_high |=
9321 SECONDARY_EXEC_RDTSCP;
9323 vmx->nested.nested_vmx_secondary_ctls_high &=
9324 ~SECONDARY_EXEC_RDTSCP;
9328 /* Exposing INVPCID only when PCID is exposed */
9329 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9330 if (vmx_invpcid_supported() &&
9331 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9332 !guest_cpuid_has_pcid(vcpu))) {
9333 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9336 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9339 if (cpu_has_secondary_exec_ctrls())
9340 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9342 if (nested_vmx_allowed(vcpu))
9343 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9344 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9346 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9347 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9350 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9352 if (func == 1 && nested)
9353 entry->ecx |= bit(X86_FEATURE_VMX);
9356 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9357 struct x86_exception *fault)
9359 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9362 if (fault->error_code & PFERR_RSVD_MASK)
9363 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9365 exit_reason = EXIT_REASON_EPT_VIOLATION;
9366 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9367 vmcs12->guest_physical_address = fault->address;
9370 /* Callbacks for nested_ept_init_mmu_context: */
9372 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9374 /* return the page table to be shadowed - in our case, EPT12 */
9375 return get_vmcs12(vcpu)->ept_pointer;
9378 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9380 WARN_ON(mmu_is_nested(vcpu));
9381 kvm_init_shadow_ept_mmu(vcpu,
9382 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9383 VMX_EPT_EXECUTE_ONLY_BIT);
9384 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9385 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9386 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9388 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9391 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9393 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9396 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9399 bool inequality, bit;
9401 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9403 (error_code & vmcs12->page_fault_error_code_mask) !=
9404 vmcs12->page_fault_error_code_match;
9405 return inequality ^ bit;
9408 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9409 struct x86_exception *fault)
9411 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9413 WARN_ON(!is_guest_mode(vcpu));
9415 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9416 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9417 vmcs_read32(VM_EXIT_INTR_INFO),
9418 vmcs_readl(EXIT_QUALIFICATION));
9420 kvm_inject_page_fault(vcpu, fault);
9423 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9424 struct vmcs12 *vmcs12)
9426 struct vcpu_vmx *vmx = to_vmx(vcpu);
9427 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9429 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9430 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9431 vmcs12->apic_access_addr >> maxphyaddr)
9435 * Translate L1 physical address to host physical
9436 * address for vmcs02. Keep the page pinned, so this
9437 * physical address remains valid. We keep a reference
9438 * to it so we can release it later.
9440 if (vmx->nested.apic_access_page) /* shouldn't happen */
9441 nested_release_page(vmx->nested.apic_access_page);
9442 vmx->nested.apic_access_page =
9443 nested_get_page(vcpu, vmcs12->apic_access_addr);
9446 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9447 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9448 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9451 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9452 nested_release_page(vmx->nested.virtual_apic_page);
9453 vmx->nested.virtual_apic_page =
9454 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9457 * Failing the vm entry is _not_ what the processor does
9458 * but it's basically the only possibility we have.
9459 * We could still enter the guest if CR8 load exits are
9460 * enabled, CR8 store exits are enabled, and virtualize APIC
9461 * access is disabled; in this case the processor would never
9462 * use the TPR shadow and we could simply clear the bit from
9463 * the execution control. But such a configuration is useless,
9464 * so let's keep the code simple.
9466 if (!vmx->nested.virtual_apic_page)
9470 if (nested_cpu_has_posted_intr(vmcs12)) {
9471 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9472 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9475 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9476 kunmap(vmx->nested.pi_desc_page);
9477 nested_release_page(vmx->nested.pi_desc_page);
9479 vmx->nested.pi_desc_page =
9480 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9481 if (!vmx->nested.pi_desc_page)
9484 vmx->nested.pi_desc =
9485 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9486 if (!vmx->nested.pi_desc) {
9487 nested_release_page_clean(vmx->nested.pi_desc_page);
9490 vmx->nested.pi_desc =
9491 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9492 (unsigned long)(vmcs12->posted_intr_desc_addr &
9499 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9501 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9502 struct vcpu_vmx *vmx = to_vmx(vcpu);
9504 if (vcpu->arch.virtual_tsc_khz == 0)
9507 /* Make sure short timeouts reliably trigger an immediate vmexit.
9508 * hrtimer_start does not guarantee this. */
9509 if (preemption_timeout <= 1) {
9510 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9514 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9515 preemption_timeout *= 1000000;
9516 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9517 hrtimer_start(&vmx->nested.preemption_timer,
9518 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9521 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9522 struct vmcs12 *vmcs12)
9527 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9530 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9534 maxphyaddr = cpuid_maxphyaddr(vcpu);
9536 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9537 ((addr + PAGE_SIZE) >> maxphyaddr))
9544 * Merge L0's and L1's MSR bitmap, return false to indicate that
9545 * we do not use the hardware.
9547 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9548 struct vmcs12 *vmcs12)
9552 unsigned long *msr_bitmap_l1;
9553 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9555 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9556 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9559 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9564 msr_bitmap_l1 = (unsigned long *)kmap(page);
9565 if (!msr_bitmap_l1) {
9566 nested_release_page_clean(page);
9571 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9573 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9574 if (nested_cpu_has_apic_reg_virt(vmcs12))
9575 for (msr = 0x800; msr <= 0x8ff; msr++)
9576 nested_vmx_disable_intercept_for_msr(
9577 msr_bitmap_l1, msr_bitmap_l0,
9580 nested_vmx_disable_intercept_for_msr(
9581 msr_bitmap_l1, msr_bitmap_l0,
9582 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9583 MSR_TYPE_R | MSR_TYPE_W);
9585 if (nested_cpu_has_vid(vmcs12)) {
9586 nested_vmx_disable_intercept_for_msr(
9587 msr_bitmap_l1, msr_bitmap_l0,
9588 APIC_BASE_MSR + (APIC_EOI >> 4),
9590 nested_vmx_disable_intercept_for_msr(
9591 msr_bitmap_l1, msr_bitmap_l0,
9592 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9597 nested_release_page_clean(page);
9602 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9603 struct vmcs12 *vmcs12)
9605 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9606 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9607 !nested_cpu_has_vid(vmcs12) &&
9608 !nested_cpu_has_posted_intr(vmcs12))
9612 * If virtualize x2apic mode is enabled,
9613 * virtualize apic access must be disabled.
9615 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9616 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9620 * If virtual interrupt delivery is enabled,
9621 * we must exit on external interrupts.
9623 if (nested_cpu_has_vid(vmcs12) &&
9624 !nested_exit_on_intr(vcpu))
9628 * bits 15:8 should be zero in posted_intr_nv,
9629 * the descriptor address has been already checked
9630 * in nested_get_vmcs12_pages.
9632 if (nested_cpu_has_posted_intr(vmcs12) &&
9633 (!nested_cpu_has_vid(vmcs12) ||
9634 !nested_exit_intr_ack_set(vcpu) ||
9635 vmcs12->posted_intr_nv & 0xff00))
9638 /* tpr shadow is needed by all apicv features. */
9639 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9645 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9646 unsigned long count_field,
9647 unsigned long addr_field)
9652 if (vmcs12_read_any(vcpu, count_field, &count) ||
9653 vmcs12_read_any(vcpu, addr_field, &addr)) {
9659 maxphyaddr = cpuid_maxphyaddr(vcpu);
9660 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9661 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9662 pr_debug_ratelimited(
9663 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9664 addr_field, maxphyaddr, count, addr);
9670 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9671 struct vmcs12 *vmcs12)
9673 if (vmcs12->vm_exit_msr_load_count == 0 &&
9674 vmcs12->vm_exit_msr_store_count == 0 &&
9675 vmcs12->vm_entry_msr_load_count == 0)
9676 return 0; /* Fast path */
9677 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9678 VM_EXIT_MSR_LOAD_ADDR) ||
9679 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9680 VM_EXIT_MSR_STORE_ADDR) ||
9681 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9682 VM_ENTRY_MSR_LOAD_ADDR))
9687 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9688 struct vmx_msr_entry *e)
9690 /* x2APIC MSR accesses are not allowed */
9691 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9693 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9694 e->index == MSR_IA32_UCODE_REV)
9696 if (e->reserved != 0)
9701 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9702 struct vmx_msr_entry *e)
9704 if (e->index == MSR_FS_BASE ||
9705 e->index == MSR_GS_BASE ||
9706 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9707 nested_vmx_msr_check_common(vcpu, e))
9712 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9713 struct vmx_msr_entry *e)
9715 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9716 nested_vmx_msr_check_common(vcpu, e))
9722 * Load guest's/host's msr at nested entry/exit.
9723 * return 0 for success, entry index for failure.
9725 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9728 struct vmx_msr_entry e;
9729 struct msr_data msr;
9731 msr.host_initiated = false;
9732 for (i = 0; i < count; i++) {
9733 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9735 pr_debug_ratelimited(
9736 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9737 __func__, i, gpa + i * sizeof(e));
9740 if (nested_vmx_load_msr_check(vcpu, &e)) {
9741 pr_debug_ratelimited(
9742 "%s check failed (%u, 0x%x, 0x%x)\n",
9743 __func__, i, e.index, e.reserved);
9746 msr.index = e.index;
9748 if (kvm_set_msr(vcpu, &msr)) {
9749 pr_debug_ratelimited(
9750 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9751 __func__, i, e.index, e.value);
9760 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9763 struct vmx_msr_entry e;
9765 for (i = 0; i < count; i++) {
9766 struct msr_data msr_info;
9767 if (kvm_vcpu_read_guest(vcpu,
9768 gpa + i * sizeof(e),
9769 &e, 2 * sizeof(u32))) {
9770 pr_debug_ratelimited(
9771 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9772 __func__, i, gpa + i * sizeof(e));
9775 if (nested_vmx_store_msr_check(vcpu, &e)) {
9776 pr_debug_ratelimited(
9777 "%s check failed (%u, 0x%x, 0x%x)\n",
9778 __func__, i, e.index, e.reserved);
9781 msr_info.host_initiated = false;
9782 msr_info.index = e.index;
9783 if (kvm_get_msr(vcpu, &msr_info)) {
9784 pr_debug_ratelimited(
9785 "%s cannot read MSR (%u, 0x%x)\n",
9786 __func__, i, e.index);
9789 if (kvm_vcpu_write_guest(vcpu,
9790 gpa + i * sizeof(e) +
9791 offsetof(struct vmx_msr_entry, value),
9792 &msr_info.data, sizeof(msr_info.data))) {
9793 pr_debug_ratelimited(
9794 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9795 __func__, i, e.index, msr_info.data);
9803 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9804 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9805 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9806 * guest in a way that will both be appropriate to L1's requests, and our
9807 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9808 * function also has additional necessary side-effects, like setting various
9809 * vcpu->arch fields.
9811 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9813 struct vcpu_vmx *vmx = to_vmx(vcpu);
9816 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9817 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9818 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9819 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9820 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9821 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9822 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9823 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9824 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9825 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9826 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9827 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9828 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9829 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9830 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9831 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9832 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9833 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9834 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9835 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9836 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9837 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9838 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9839 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9840 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9841 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9842 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9843 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9844 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9845 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9846 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9847 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9848 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9849 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9850 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9851 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9853 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9854 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9855 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9857 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9858 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9860 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9861 vmcs12->vm_entry_intr_info_field);
9862 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9863 vmcs12->vm_entry_exception_error_code);
9864 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9865 vmcs12->vm_entry_instruction_len);
9866 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9867 vmcs12->guest_interruptibility_info);
9868 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9869 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9870 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9871 vmcs12->guest_pending_dbg_exceptions);
9872 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9873 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9875 if (nested_cpu_has_xsaves(vmcs12))
9876 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9877 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9879 exec_control = vmcs12->pin_based_vm_exec_control;
9881 /* Preemption timer setting is only taken from vmcs01. */
9882 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9883 exec_control |= vmcs_config.pin_based_exec_ctrl;
9884 if (vmx->hv_deadline_tsc == -1)
9885 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9887 /* Posted interrupts setting is only taken from vmcs12. */
9888 if (nested_cpu_has_posted_intr(vmcs12)) {
9890 * Note that we use L0's vector here and in
9891 * vmx_deliver_nested_posted_interrupt.
9893 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9894 vmx->nested.pi_pending = false;
9895 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9896 vmcs_write64(POSTED_INTR_DESC_ADDR,
9897 page_to_phys(vmx->nested.pi_desc_page) +
9898 (unsigned long)(vmcs12->posted_intr_desc_addr &
9901 exec_control &= ~PIN_BASED_POSTED_INTR;
9903 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9905 vmx->nested.preemption_timer_expired = false;
9906 if (nested_cpu_has_preemption_timer(vmcs12))
9907 vmx_start_preemption_timer(vcpu);
9910 * Whether page-faults are trapped is determined by a combination of
9911 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9912 * If enable_ept, L0 doesn't care about page faults and we should
9913 * set all of these to L1's desires. However, if !enable_ept, L0 does
9914 * care about (at least some) page faults, and because it is not easy
9915 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9916 * to exit on each and every L2 page fault. This is done by setting
9917 * MASK=MATCH=0 and (see below) EB.PF=1.
9918 * Note that below we don't need special code to set EB.PF beyond the
9919 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9920 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9921 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9923 * A problem with this approach (when !enable_ept) is that L1 may be
9924 * injected with more page faults than it asked for. This could have
9925 * caused problems, but in practice existing hypervisors don't care.
9926 * To fix this, we will need to emulate the PFEC checking (on the L1
9927 * page tables), using walk_addr(), when injecting PFs to L1.
9929 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9930 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9931 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9932 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9934 if (cpu_has_secondary_exec_ctrls()) {
9935 exec_control = vmx_secondary_exec_control(vmx);
9937 /* Take the following fields only from vmcs12 */
9938 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9939 SECONDARY_EXEC_RDTSCP |
9940 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9941 SECONDARY_EXEC_APIC_REGISTER_VIRT);
9942 if (nested_cpu_has(vmcs12,
9943 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9944 exec_control |= vmcs12->secondary_vm_exec_control;
9946 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9948 * If translation failed, no matter: This feature asks
9949 * to exit when accessing the given address, and if it
9950 * can never be accessed, this feature won't do
9953 if (!vmx->nested.apic_access_page)
9955 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9957 vmcs_write64(APIC_ACCESS_ADDR,
9958 page_to_phys(vmx->nested.apic_access_page));
9959 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9960 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9962 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9963 kvm_vcpu_reload_apic_access_page(vcpu);
9966 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9967 vmcs_write64(EOI_EXIT_BITMAP0,
9968 vmcs12->eoi_exit_bitmap0);
9969 vmcs_write64(EOI_EXIT_BITMAP1,
9970 vmcs12->eoi_exit_bitmap1);
9971 vmcs_write64(EOI_EXIT_BITMAP2,
9972 vmcs12->eoi_exit_bitmap2);
9973 vmcs_write64(EOI_EXIT_BITMAP3,
9974 vmcs12->eoi_exit_bitmap3);
9975 vmcs_write16(GUEST_INTR_STATUS,
9976 vmcs12->guest_intr_status);
9979 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9984 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9985 * Some constant fields are set here by vmx_set_constant_host_state().
9986 * Other fields are different per CPU, and will be set later when
9987 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9989 vmx_set_constant_host_state(vmx);
9992 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9993 * entry, but only if the current (host) sp changed from the value
9994 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9995 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9996 * here we just force the write to happen on entry.
10000 exec_control = vmx_exec_control(vmx); /* L0's desires */
10001 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10002 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10003 exec_control &= ~CPU_BASED_TPR_SHADOW;
10004 exec_control |= vmcs12->cpu_based_vm_exec_control;
10006 if (exec_control & CPU_BASED_TPR_SHADOW) {
10007 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
10008 page_to_phys(vmx->nested.virtual_apic_page));
10009 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10012 if (cpu_has_vmx_msr_bitmap() &&
10013 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
10014 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
10015 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
10017 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
10020 * Merging of IO bitmap not currently supported.
10021 * Rather, exit every time.
10023 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10024 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10026 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10028 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10029 * bitwise-or of what L1 wants to trap for L2, and what we want to
10030 * trap. Note that CR0.TS also needs updating - we do this later.
10032 update_exception_bitmap(vcpu);
10033 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10034 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10036 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10037 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10038 * bits are further modified by vmx_set_efer() below.
10040 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10042 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10043 * emulated by vmx_set_efer(), below.
10045 vm_entry_controls_init(vmx,
10046 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10047 ~VM_ENTRY_IA32E_MODE) |
10048 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10050 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
10051 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10052 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10053 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
10054 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10057 set_cr4_guest_host_mask(vmx);
10059 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10060 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10062 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10063 vmcs_write64(TSC_OFFSET,
10064 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
10066 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10067 if (kvm_has_tsc_control)
10068 decache_tsc_multiplier(vmx);
10072 * There is no direct mapping between vpid02 and vpid12, the
10073 * vpid02 is per-vCPU for L0 and reused while the value of
10074 * vpid12 is changed w/ one invvpid during nested vmentry.
10075 * The vpid12 is allocated by L1 for L2, so it will not
10076 * influence global bitmap(for vpid01 and vpid02 allocation)
10077 * even if spawn a lot of nested vCPUs.
10079 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10080 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10081 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10082 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10083 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10086 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10087 vmx_flush_tlb(vcpu);
10092 if (nested_cpu_has_ept(vmcs12)) {
10093 kvm_mmu_unload(vcpu);
10094 nested_ept_init_mmu_context(vcpu);
10097 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10098 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10099 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10100 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10102 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10103 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10104 vmx_set_efer(vcpu, vcpu->arch.efer);
10107 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10108 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10109 * The CR0_READ_SHADOW is what L2 should have expected to read given
10110 * the specifications by L1; It's not enough to take
10111 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10112 * have more bits than L1 expected.
10114 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10115 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10117 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10118 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10120 /* shadow page tables on either EPT or shadow page tables */
10121 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10122 kvm_mmu_reset_context(vcpu);
10125 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10128 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10131 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10132 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10133 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10134 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10137 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10138 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10142 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10143 * for running an L2 nested guest.
10145 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10147 struct vmcs12 *vmcs12;
10148 struct vcpu_vmx *vmx = to_vmx(vcpu);
10150 struct loaded_vmcs *vmcs02;
10154 if (!nested_vmx_check_permission(vcpu) ||
10155 !nested_vmx_check_vmcs12(vcpu))
10158 skip_emulated_instruction(vcpu);
10159 vmcs12 = get_vmcs12(vcpu);
10161 if (enable_shadow_vmcs)
10162 copy_shadow_to_vmcs12(vmx);
10165 * The nested entry process starts with enforcing various prerequisites
10166 * on vmcs12 as required by the Intel SDM, and act appropriately when
10167 * they fail: As the SDM explains, some conditions should cause the
10168 * instruction to fail, while others will cause the instruction to seem
10169 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10170 * To speed up the normal (success) code path, we should avoid checking
10171 * for misconfigurations which will anyway be caught by the processor
10172 * when using the merged vmcs02.
10174 if (vmcs12->launch_state == launch) {
10175 nested_vmx_failValid(vcpu,
10176 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10177 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10181 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10182 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10183 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10187 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10188 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10192 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10193 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10197 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10198 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10202 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10203 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10207 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10208 vmx->nested.nested_vmx_true_procbased_ctls_low,
10209 vmx->nested.nested_vmx_procbased_ctls_high) ||
10210 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10211 vmx->nested.nested_vmx_secondary_ctls_low,
10212 vmx->nested.nested_vmx_secondary_ctls_high) ||
10213 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10214 vmx->nested.nested_vmx_pinbased_ctls_low,
10215 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10216 !vmx_control_verify(vmcs12->vm_exit_controls,
10217 vmx->nested.nested_vmx_true_exit_ctls_low,
10218 vmx->nested.nested_vmx_exit_ctls_high) ||
10219 !vmx_control_verify(vmcs12->vm_entry_controls,
10220 vmx->nested.nested_vmx_true_entry_ctls_low,
10221 vmx->nested.nested_vmx_entry_ctls_high))
10223 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10227 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10228 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10229 nested_vmx_failValid(vcpu,
10230 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10234 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10235 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10236 nested_vmx_entry_failure(vcpu, vmcs12,
10237 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10240 if (vmcs12->vmcs_link_pointer != -1ull) {
10241 nested_vmx_entry_failure(vcpu, vmcs12,
10242 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10247 * If the load IA32_EFER VM-entry control is 1, the following checks
10248 * are performed on the field for the IA32_EFER MSR:
10249 * - Bits reserved in the IA32_EFER MSR must be 0.
10250 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10251 * the IA-32e mode guest VM-exit control. It must also be identical
10252 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10255 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10256 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10257 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10258 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10259 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10260 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10261 nested_vmx_entry_failure(vcpu, vmcs12,
10262 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10268 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10269 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10270 * the values of the LMA and LME bits in the field must each be that of
10271 * the host address-space size VM-exit control.
10273 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10274 ia32e = (vmcs12->vm_exit_controls &
10275 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10276 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10277 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10278 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10279 nested_vmx_entry_failure(vcpu, vmcs12,
10280 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10286 * We're finally done with prerequisite checking, and can start with
10287 * the nested entry.
10290 vmcs02 = nested_get_current_vmcs02(vmx);
10294 enter_guest_mode(vcpu);
10296 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10298 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10299 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10302 vmx->loaded_vmcs = vmcs02;
10303 vmx_vcpu_put(vcpu);
10304 vmx_vcpu_load(vcpu, cpu);
10308 vmx_segment_cache_clear(vmx);
10310 prepare_vmcs02(vcpu, vmcs12);
10312 msr_entry_idx = nested_vmx_load_msr(vcpu,
10313 vmcs12->vm_entry_msr_load_addr,
10314 vmcs12->vm_entry_msr_load_count);
10315 if (msr_entry_idx) {
10316 leave_guest_mode(vcpu);
10317 vmx_load_vmcs01(vcpu);
10318 nested_vmx_entry_failure(vcpu, vmcs12,
10319 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10323 vmcs12->launch_state = 1;
10325 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10326 return kvm_vcpu_halt(vcpu);
10328 vmx->nested.nested_run_pending = 1;
10331 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10332 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10333 * returned as far as L1 is concerned. It will only return (and set
10334 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10340 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10341 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10342 * This function returns the new value we should put in vmcs12.guest_cr0.
10343 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10344 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10345 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10346 * didn't trap the bit, because if L1 did, so would L0).
10347 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10348 * been modified by L2, and L1 knows it. So just leave the old value of
10349 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10350 * isn't relevant, because if L0 traps this bit it can set it to anything.
10351 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10352 * changed these bits, and therefore they need to be updated, but L0
10353 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10354 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10356 static inline unsigned long
10357 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10360 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10361 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10362 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10363 vcpu->arch.cr0_guest_owned_bits));
10366 static inline unsigned long
10367 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10370 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10371 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10372 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10373 vcpu->arch.cr4_guest_owned_bits));
10376 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10377 struct vmcs12 *vmcs12)
10382 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10383 nr = vcpu->arch.exception.nr;
10384 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10386 if (kvm_exception_is_soft(nr)) {
10387 vmcs12->vm_exit_instruction_len =
10388 vcpu->arch.event_exit_inst_len;
10389 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10391 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10393 if (vcpu->arch.exception.has_error_code) {
10394 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10395 vmcs12->idt_vectoring_error_code =
10396 vcpu->arch.exception.error_code;
10399 vmcs12->idt_vectoring_info_field = idt_vectoring;
10400 } else if (vcpu->arch.nmi_injected) {
10401 vmcs12->idt_vectoring_info_field =
10402 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10403 } else if (vcpu->arch.interrupt.pending) {
10404 nr = vcpu->arch.interrupt.nr;
10405 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10407 if (vcpu->arch.interrupt.soft) {
10408 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10409 vmcs12->vm_entry_instruction_len =
10410 vcpu->arch.event_exit_inst_len;
10412 idt_vectoring |= INTR_TYPE_EXT_INTR;
10414 vmcs12->idt_vectoring_info_field = idt_vectoring;
10418 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10420 struct vcpu_vmx *vmx = to_vmx(vcpu);
10422 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10423 vmx->nested.preemption_timer_expired) {
10424 if (vmx->nested.nested_run_pending)
10426 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10430 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10431 if (vmx->nested.nested_run_pending ||
10432 vcpu->arch.interrupt.pending)
10434 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10435 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10436 INTR_INFO_VALID_MASK, 0);
10438 * The NMI-triggered VM exit counts as injection:
10439 * clear this one and block further NMIs.
10441 vcpu->arch.nmi_pending = 0;
10442 vmx_set_nmi_mask(vcpu, true);
10446 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10447 nested_exit_on_intr(vcpu)) {
10448 if (vmx->nested.nested_run_pending)
10450 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10454 return vmx_complete_nested_posted_interrupt(vcpu);
10457 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10459 ktime_t remaining =
10460 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10463 if (ktime_to_ns(remaining) <= 0)
10466 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10467 do_div(value, 1000000);
10468 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10472 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10473 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10474 * and this function updates it to reflect the changes to the guest state while
10475 * L2 was running (and perhaps made some exits which were handled directly by L0
10476 * without going back to L1), and to reflect the exit reason.
10477 * Note that we do not have to copy here all VMCS fields, just those that
10478 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10479 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10480 * which already writes to vmcs12 directly.
10482 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10483 u32 exit_reason, u32 exit_intr_info,
10484 unsigned long exit_qualification)
10486 /* update guest state fields: */
10487 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10488 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10490 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10491 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10492 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10494 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10495 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10496 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10497 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10498 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10499 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10500 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10501 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10502 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10503 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10504 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10505 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10506 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10507 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10508 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10509 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10510 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10511 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10512 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10513 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10514 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10515 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10516 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10517 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10518 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10519 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10520 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10521 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10522 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10523 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10524 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10525 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10526 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10527 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10528 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10529 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10531 vmcs12->guest_interruptibility_info =
10532 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10533 vmcs12->guest_pending_dbg_exceptions =
10534 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10535 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10536 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10538 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10540 if (nested_cpu_has_preemption_timer(vmcs12)) {
10541 if (vmcs12->vm_exit_controls &
10542 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10543 vmcs12->vmx_preemption_timer_value =
10544 vmx_get_preemption_timer_value(vcpu);
10545 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10549 * In some cases (usually, nested EPT), L2 is allowed to change its
10550 * own CR3 without exiting. If it has changed it, we must keep it.
10551 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10552 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10554 * Additionally, restore L2's PDPTR to vmcs12.
10557 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10558 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10559 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10560 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10561 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10564 if (nested_cpu_has_ept(vmcs12))
10565 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10567 if (nested_cpu_has_vid(vmcs12))
10568 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10570 vmcs12->vm_entry_controls =
10571 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10572 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10574 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10575 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10576 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10579 /* TODO: These cannot have changed unless we have MSR bitmaps and
10580 * the relevant bit asks not to trap the change */
10581 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10582 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10583 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10584 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10585 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10586 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10587 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10588 if (kvm_mpx_supported())
10589 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10590 if (nested_cpu_has_xsaves(vmcs12))
10591 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10593 /* update exit information fields: */
10595 vmcs12->vm_exit_reason = exit_reason;
10596 vmcs12->exit_qualification = exit_qualification;
10598 vmcs12->vm_exit_intr_info = exit_intr_info;
10599 if ((vmcs12->vm_exit_intr_info &
10600 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10601 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10602 vmcs12->vm_exit_intr_error_code =
10603 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10604 vmcs12->idt_vectoring_info_field = 0;
10605 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10606 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10608 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10609 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10610 * instead of reading the real value. */
10611 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10614 * Transfer the event that L0 or L1 may wanted to inject into
10615 * L2 to IDT_VECTORING_INFO_FIELD.
10617 vmcs12_save_pending_event(vcpu, vmcs12);
10621 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10622 * preserved above and would only end up incorrectly in L1.
10624 vcpu->arch.nmi_injected = false;
10625 kvm_clear_exception_queue(vcpu);
10626 kvm_clear_interrupt_queue(vcpu);
10630 * A part of what we need to when the nested L2 guest exits and we want to
10631 * run its L1 parent, is to reset L1's guest state to the host state specified
10633 * This function is to be called not only on normal nested exit, but also on
10634 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10635 * Failures During or After Loading Guest State").
10636 * This function should be called when the active VMCS is L1's (vmcs01).
10638 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10639 struct vmcs12 *vmcs12)
10641 struct kvm_segment seg;
10643 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10644 vcpu->arch.efer = vmcs12->host_ia32_efer;
10645 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10646 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10648 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10649 vmx_set_efer(vcpu, vcpu->arch.efer);
10651 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10652 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10653 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10655 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10656 * actually changed, because it depends on the current state of
10657 * fpu_active (which may have changed).
10658 * Note that vmx_set_cr0 refers to efer set above.
10660 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10662 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10663 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10664 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10666 update_exception_bitmap(vcpu);
10667 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10668 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10671 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10672 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10674 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10675 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10677 nested_ept_uninit_mmu_context(vcpu);
10679 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10680 kvm_mmu_reset_context(vcpu);
10683 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10687 * Trivially support vpid by letting L2s share their parent
10688 * L1's vpid. TODO: move to a more elaborate solution, giving
10689 * each L2 its own vpid and exposing the vpid feature to L1.
10691 vmx_flush_tlb(vcpu);
10695 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10696 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10697 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10698 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10699 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10701 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10702 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10703 vmcs_write64(GUEST_BNDCFGS, 0);
10705 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10706 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10707 vcpu->arch.pat = vmcs12->host_ia32_pat;
10709 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10710 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10711 vmcs12->host_ia32_perf_global_ctrl);
10713 /* Set L1 segment info according to Intel SDM
10714 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10715 seg = (struct kvm_segment) {
10717 .limit = 0xFFFFFFFF,
10718 .selector = vmcs12->host_cs_selector,
10724 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10728 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10729 seg = (struct kvm_segment) {
10731 .limit = 0xFFFFFFFF,
10738 seg.selector = vmcs12->host_ds_selector;
10739 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10740 seg.selector = vmcs12->host_es_selector;
10741 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10742 seg.selector = vmcs12->host_ss_selector;
10743 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10744 seg.selector = vmcs12->host_fs_selector;
10745 seg.base = vmcs12->host_fs_base;
10746 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10747 seg.selector = vmcs12->host_gs_selector;
10748 seg.base = vmcs12->host_gs_base;
10749 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10750 seg = (struct kvm_segment) {
10751 .base = vmcs12->host_tr_base,
10753 .selector = vmcs12->host_tr_selector,
10757 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10759 kvm_set_dr(vcpu, 7, 0x400);
10760 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10762 if (cpu_has_vmx_msr_bitmap())
10763 vmx_set_msr_bitmap(vcpu);
10765 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10766 vmcs12->vm_exit_msr_load_count))
10767 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10771 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10772 * and modify vmcs12 to make it see what it would expect to see there if
10773 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10775 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10776 u32 exit_intr_info,
10777 unsigned long exit_qualification)
10779 struct vcpu_vmx *vmx = to_vmx(vcpu);
10780 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10782 /* trying to cancel vmlaunch/vmresume is a bug */
10783 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10785 leave_guest_mode(vcpu);
10786 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10787 exit_qualification);
10789 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10790 vmcs12->vm_exit_msr_store_count))
10791 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10793 vmx_load_vmcs01(vcpu);
10795 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10796 && nested_exit_intr_ack_set(vcpu)) {
10797 int irq = kvm_cpu_get_interrupt(vcpu);
10799 vmcs12->vm_exit_intr_info = irq |
10800 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10803 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10804 vmcs12->exit_qualification,
10805 vmcs12->idt_vectoring_info_field,
10806 vmcs12->vm_exit_intr_info,
10807 vmcs12->vm_exit_intr_error_code,
10810 vm_entry_controls_reset_shadow(vmx);
10811 vm_exit_controls_reset_shadow(vmx);
10812 vmx_segment_cache_clear(vmx);
10814 /* if no vmcs02 cache requested, remove the one we used */
10815 if (VMCS02_POOL_SIZE == 0)
10816 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10818 load_vmcs12_host_state(vcpu, vmcs12);
10820 /* Update any VMCS fields that might have changed while L2 ran */
10821 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10822 if (vmx->hv_deadline_tsc == -1)
10823 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10824 PIN_BASED_VMX_PREEMPTION_TIMER);
10826 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10827 PIN_BASED_VMX_PREEMPTION_TIMER);
10828 if (kvm_has_tsc_control)
10829 decache_tsc_multiplier(vmx);
10831 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10832 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10833 vmx_set_virtual_x2apic_mode(vcpu,
10834 vcpu->arch.apic_base & X2APIC_ENABLE);
10837 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10840 /* Unpin physical memory we referred to in vmcs02 */
10841 if (vmx->nested.apic_access_page) {
10842 nested_release_page(vmx->nested.apic_access_page);
10843 vmx->nested.apic_access_page = NULL;
10845 if (vmx->nested.virtual_apic_page) {
10846 nested_release_page(vmx->nested.virtual_apic_page);
10847 vmx->nested.virtual_apic_page = NULL;
10849 if (vmx->nested.pi_desc_page) {
10850 kunmap(vmx->nested.pi_desc_page);
10851 nested_release_page(vmx->nested.pi_desc_page);
10852 vmx->nested.pi_desc_page = NULL;
10853 vmx->nested.pi_desc = NULL;
10857 * We are now running in L2, mmu_notifier will force to reload the
10858 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10860 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
10863 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10864 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10865 * success or failure flag accordingly.
10867 if (unlikely(vmx->fail)) {
10869 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10871 nested_vmx_succeed(vcpu);
10872 if (enable_shadow_vmcs)
10873 vmx->nested.sync_shadow_vmcs = true;
10875 /* in case we halted in L2 */
10876 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10880 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10882 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10884 if (is_guest_mode(vcpu))
10885 nested_vmx_vmexit(vcpu, -1, 0, 0);
10886 free_nested(to_vmx(vcpu));
10890 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10891 * 23.7 "VM-entry failures during or after loading guest state" (this also
10892 * lists the acceptable exit-reason and exit-qualification parameters).
10893 * It should only be called before L2 actually succeeded to run, and when
10894 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10896 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10897 struct vmcs12 *vmcs12,
10898 u32 reason, unsigned long qualification)
10900 load_vmcs12_host_state(vcpu, vmcs12);
10901 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10902 vmcs12->exit_qualification = qualification;
10903 nested_vmx_succeed(vcpu);
10904 if (enable_shadow_vmcs)
10905 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10908 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10909 struct x86_instruction_info *info,
10910 enum x86_intercept_stage stage)
10912 return X86EMUL_CONTINUE;
10915 #ifdef CONFIG_X86_64
10916 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10917 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10918 u64 divisor, u64 *result)
10920 u64 low = a << shift, high = a >> (64 - shift);
10922 /* To avoid the overflow on divq */
10923 if (high >= divisor)
10926 /* Low hold the result, high hold rem which is discarded */
10927 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10928 "rm" (divisor), "0" (low), "1" (high));
10934 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10936 struct vcpu_vmx *vmx = to_vmx(vcpu);
10937 u64 tscl = rdtsc();
10938 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10939 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10941 /* Convert to host delta tsc if tsc scaling is enabled */
10942 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10943 u64_shl_div_u64(delta_tsc,
10944 kvm_tsc_scaling_ratio_frac_bits,
10945 vcpu->arch.tsc_scaling_ratio,
10950 * If the delta tsc can't fit in the 32 bit after the multi shift,
10951 * we can't use the preemption timer.
10952 * It's possible that it fits on later vmentries, but checking
10953 * on every vmentry is costly so we just use an hrtimer.
10955 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10958 vmx->hv_deadline_tsc = tscl + delta_tsc;
10959 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10960 PIN_BASED_VMX_PREEMPTION_TIMER);
10964 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10966 struct vcpu_vmx *vmx = to_vmx(vcpu);
10967 vmx->hv_deadline_tsc = -1;
10968 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10969 PIN_BASED_VMX_PREEMPTION_TIMER);
10973 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10976 shrink_ple_window(vcpu);
10979 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10980 struct kvm_memory_slot *slot)
10982 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10983 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10986 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10987 struct kvm_memory_slot *slot)
10989 kvm_mmu_slot_set_dirty(kvm, slot);
10992 static void vmx_flush_log_dirty(struct kvm *kvm)
10994 kvm_flush_pml_buffers(kvm);
10997 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10998 struct kvm_memory_slot *memslot,
10999 gfn_t offset, unsigned long mask)
11001 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11005 * This routine does the following things for vCPU which is going
11006 * to be blocked if VT-d PI is enabled.
11007 * - Store the vCPU to the wakeup list, so when interrupts happen
11008 * we can find the right vCPU to wake up.
11009 * - Change the Posted-interrupt descriptor as below:
11010 * 'NDST' <-- vcpu->pre_pcpu
11011 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11012 * - If 'ON' is set during this process, which means at least one
11013 * interrupt is posted for this vCPU, we cannot block it, in
11014 * this case, return 1, otherwise, return 0.
11017 static int pi_pre_block(struct kvm_vcpu *vcpu)
11019 unsigned long flags;
11021 struct pi_desc old, new;
11022 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11024 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11025 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11026 !kvm_vcpu_apicv_active(vcpu))
11029 vcpu->pre_pcpu = vcpu->cpu;
11030 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11031 vcpu->pre_pcpu), flags);
11032 list_add_tail(&vcpu->blocked_vcpu_list,
11033 &per_cpu(blocked_vcpu_on_cpu,
11035 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11036 vcpu->pre_pcpu), flags);
11039 old.control = new.control = pi_desc->control;
11042 * We should not block the vCPU if
11043 * an interrupt is posted for it.
11045 if (pi_test_on(pi_desc) == 1) {
11046 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11047 vcpu->pre_pcpu), flags);
11048 list_del(&vcpu->blocked_vcpu_list);
11049 spin_unlock_irqrestore(
11050 &per_cpu(blocked_vcpu_on_cpu_lock,
11051 vcpu->pre_pcpu), flags);
11052 vcpu->pre_pcpu = -1;
11057 WARN((pi_desc->sn == 1),
11058 "Warning: SN field of posted-interrupts "
11059 "is set before blocking\n");
11062 * Since vCPU can be preempted during this process,
11063 * vcpu->cpu could be different with pre_pcpu, we
11064 * need to set pre_pcpu as the destination of wakeup
11065 * notification event, then we can find the right vCPU
11066 * to wakeup in wakeup handler if interrupts happen
11067 * when the vCPU is in blocked state.
11069 dest = cpu_physical_id(vcpu->pre_pcpu);
11071 if (x2apic_enabled())
11074 new.ndst = (dest << 8) & 0xFF00;
11076 /* set 'NV' to 'wakeup vector' */
11077 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11078 } while (cmpxchg(&pi_desc->control, old.control,
11079 new.control) != old.control);
11084 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11086 if (pi_pre_block(vcpu))
11089 if (kvm_lapic_hv_timer_in_use(vcpu))
11090 kvm_lapic_switch_to_sw_timer(vcpu);
11095 static void pi_post_block(struct kvm_vcpu *vcpu)
11097 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11098 struct pi_desc old, new;
11100 unsigned long flags;
11102 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11103 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11104 !kvm_vcpu_apicv_active(vcpu))
11108 old.control = new.control = pi_desc->control;
11110 dest = cpu_physical_id(vcpu->cpu);
11112 if (x2apic_enabled())
11115 new.ndst = (dest << 8) & 0xFF00;
11117 /* Allow posting non-urgent interrupts */
11120 /* set 'NV' to 'notification vector' */
11121 new.nv = POSTED_INTR_VECTOR;
11122 } while (cmpxchg(&pi_desc->control, old.control,
11123 new.control) != old.control);
11125 if(vcpu->pre_pcpu != -1) {
11127 &per_cpu(blocked_vcpu_on_cpu_lock,
11128 vcpu->pre_pcpu), flags);
11129 list_del(&vcpu->blocked_vcpu_list);
11130 spin_unlock_irqrestore(
11131 &per_cpu(blocked_vcpu_on_cpu_lock,
11132 vcpu->pre_pcpu), flags);
11133 vcpu->pre_pcpu = -1;
11137 static void vmx_post_block(struct kvm_vcpu *vcpu)
11139 if (kvm_x86_ops->set_hv_timer)
11140 kvm_lapic_switch_to_hv_timer(vcpu);
11142 pi_post_block(vcpu);
11146 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11149 * @host_irq: host irq of the interrupt
11150 * @guest_irq: gsi of the interrupt
11151 * @set: set or unset PI
11152 * returns 0 on success, < 0 on failure
11154 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11155 uint32_t guest_irq, bool set)
11157 struct kvm_kernel_irq_routing_entry *e;
11158 struct kvm_irq_routing_table *irq_rt;
11159 struct kvm_lapic_irq irq;
11160 struct kvm_vcpu *vcpu;
11161 struct vcpu_data vcpu_info;
11162 int idx, ret = -EINVAL;
11164 if (!kvm_arch_has_assigned_device(kvm) ||
11165 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11166 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11169 idx = srcu_read_lock(&kvm->irq_srcu);
11170 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11171 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11173 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11174 if (e->type != KVM_IRQ_ROUTING_MSI)
11177 * VT-d PI cannot support posting multicast/broadcast
11178 * interrupts to a vCPU, we still use interrupt remapping
11179 * for these kind of interrupts.
11181 * For lowest-priority interrupts, we only support
11182 * those with single CPU as the destination, e.g. user
11183 * configures the interrupts via /proc/irq or uses
11184 * irqbalance to make the interrupts single-CPU.
11186 * We will support full lowest-priority interrupt later.
11189 kvm_set_msi_irq(kvm, e, &irq);
11190 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11192 * Make sure the IRTE is in remapped mode if
11193 * we don't handle it in posted mode.
11195 ret = irq_set_vcpu_affinity(host_irq, NULL);
11198 "failed to back to remapped mode, irq: %u\n",
11206 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11207 vcpu_info.vector = irq.vector;
11209 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11210 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11213 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11215 /* suppress notification event before unposting */
11216 pi_set_sn(vcpu_to_pi_desc(vcpu));
11217 ret = irq_set_vcpu_affinity(host_irq, NULL);
11218 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11222 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11230 srcu_read_unlock(&kvm->irq_srcu, idx);
11234 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11236 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11237 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11238 FEATURE_CONTROL_LMCE;
11240 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11241 ~FEATURE_CONTROL_LMCE;
11244 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11245 .cpu_has_kvm_support = cpu_has_kvm_support,
11246 .disabled_by_bios = vmx_disabled_by_bios,
11247 .hardware_setup = hardware_setup,
11248 .hardware_unsetup = hardware_unsetup,
11249 .check_processor_compatibility = vmx_check_processor_compat,
11250 .hardware_enable = hardware_enable,
11251 .hardware_disable = hardware_disable,
11252 .cpu_has_accelerated_tpr = report_flexpriority,
11253 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11255 .vcpu_create = vmx_create_vcpu,
11256 .vcpu_free = vmx_free_vcpu,
11257 .vcpu_reset = vmx_vcpu_reset,
11259 .prepare_guest_switch = vmx_save_host_state,
11260 .vcpu_load = vmx_vcpu_load,
11261 .vcpu_put = vmx_vcpu_put,
11263 .update_bp_intercept = update_exception_bitmap,
11264 .get_msr = vmx_get_msr,
11265 .set_msr = vmx_set_msr,
11266 .get_segment_base = vmx_get_segment_base,
11267 .get_segment = vmx_get_segment,
11268 .set_segment = vmx_set_segment,
11269 .get_cpl = vmx_get_cpl,
11270 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11271 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11272 .decache_cr3 = vmx_decache_cr3,
11273 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11274 .set_cr0 = vmx_set_cr0,
11275 .set_cr3 = vmx_set_cr3,
11276 .set_cr4 = vmx_set_cr4,
11277 .set_efer = vmx_set_efer,
11278 .get_idt = vmx_get_idt,
11279 .set_idt = vmx_set_idt,
11280 .get_gdt = vmx_get_gdt,
11281 .set_gdt = vmx_set_gdt,
11282 .get_dr6 = vmx_get_dr6,
11283 .set_dr6 = vmx_set_dr6,
11284 .set_dr7 = vmx_set_dr7,
11285 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11286 .cache_reg = vmx_cache_reg,
11287 .get_rflags = vmx_get_rflags,
11288 .set_rflags = vmx_set_rflags,
11290 .get_pkru = vmx_get_pkru,
11292 .fpu_activate = vmx_fpu_activate,
11293 .fpu_deactivate = vmx_fpu_deactivate,
11295 .tlb_flush = vmx_flush_tlb,
11297 .run = vmx_vcpu_run,
11298 .handle_exit = vmx_handle_exit,
11299 .skip_emulated_instruction = skip_emulated_instruction,
11300 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11301 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11302 .patch_hypercall = vmx_patch_hypercall,
11303 .set_irq = vmx_inject_irq,
11304 .set_nmi = vmx_inject_nmi,
11305 .queue_exception = vmx_queue_exception,
11306 .cancel_injection = vmx_cancel_injection,
11307 .interrupt_allowed = vmx_interrupt_allowed,
11308 .nmi_allowed = vmx_nmi_allowed,
11309 .get_nmi_mask = vmx_get_nmi_mask,
11310 .set_nmi_mask = vmx_set_nmi_mask,
11311 .enable_nmi_window = enable_nmi_window,
11312 .enable_irq_window = enable_irq_window,
11313 .update_cr8_intercept = update_cr8_intercept,
11314 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11315 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11316 .get_enable_apicv = vmx_get_enable_apicv,
11317 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11318 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11319 .hwapic_irr_update = vmx_hwapic_irr_update,
11320 .hwapic_isr_update = vmx_hwapic_isr_update,
11321 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11322 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11324 .set_tss_addr = vmx_set_tss_addr,
11325 .get_tdp_level = get_ept_level,
11326 .get_mt_mask = vmx_get_mt_mask,
11328 .get_exit_info = vmx_get_exit_info,
11330 .get_lpage_level = vmx_get_lpage_level,
11332 .cpuid_update = vmx_cpuid_update,
11334 .rdtscp_supported = vmx_rdtscp_supported,
11335 .invpcid_supported = vmx_invpcid_supported,
11337 .set_supported_cpuid = vmx_set_supported_cpuid,
11339 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11341 .write_tsc_offset = vmx_write_tsc_offset,
11342 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11343 .read_l1_tsc = vmx_read_l1_tsc,
11345 .set_tdp_cr3 = vmx_set_cr3,
11347 .check_intercept = vmx_check_intercept,
11348 .handle_external_intr = vmx_handle_external_intr,
11349 .mpx_supported = vmx_mpx_supported,
11350 .xsaves_supported = vmx_xsaves_supported,
11352 .check_nested_events = vmx_check_nested_events,
11354 .sched_in = vmx_sched_in,
11356 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11357 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11358 .flush_log_dirty = vmx_flush_log_dirty,
11359 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11361 .pre_block = vmx_pre_block,
11362 .post_block = vmx_post_block,
11364 .pmu_ops = &intel_pmu_ops,
11366 .update_pi_irte = vmx_update_pi_irte,
11368 #ifdef CONFIG_X86_64
11369 .set_hv_timer = vmx_set_hv_timer,
11370 .cancel_hv_timer = vmx_cancel_hv_timer,
11373 .setup_mce = vmx_setup_mce,
11376 static int __init vmx_init(void)
11378 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11379 __alignof__(struct vcpu_vmx), THIS_MODULE);
11383 #ifdef CONFIG_KEXEC_CORE
11384 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11385 crash_vmclear_local_loaded_vmcss);
11391 static void __exit vmx_exit(void)
11393 #ifdef CONFIG_KEXEC_CORE
11394 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11401 module_init(vmx_init)
11402 module_exit(vmx_exit)