arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  65         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  66 #define KVM_GUEST_CR0_MASK                                              \
  67         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  69         (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
  70 #define KVM_VM_CR0_ALWAYS_ON                                            \
  71         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  72 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  73         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  74          | X86_CR4_OSXMMEXCPT)
  75
  76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  78
  79 /*
  80  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  81  * ple_gap:    upper bound on the amount of time between two successive
  82  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  83  *             According to test, this time is usually small than 41 cycles.
  84  * ple_window: upper bound on the amount of time a guest is allowed to execute
  85  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  86  *             less than 2^12 cycles
  87  * Time is measured based on a counter that runs at the same rate as the TSC,
  88  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  89  */
  90 #define KVM_VMX_DEFAULT_PLE_GAP    41
  91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  92 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  93 module_param(ple_gap, int, S_IRUGO);
  94
  95 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  96 module_param(ple_window, int, S_IRUGO);
  97
  98 struct vmcs {
  99         u32 revision_id;
 100         u32 abort;
 101         char data[0];
 102 };
 103
 104 struct shared_msr_entry {
 105         unsigned index;
 106         u64 data;
 107         u64 mask;
 108 };
 109
 110 struct vcpu_vmx {
 111         struct kvm_vcpu       vcpu;
 112         struct list_head      local_vcpus_link;
 113         unsigned long         host_rsp;
 114         int                   launched;
 115         u8                    fail;
 116         u32                   idt_vectoring_info;
 117         struct shared_msr_entry *guest_msrs;
 118         int                   nmsrs;
 119         int                   save_nmsrs;
 120 #ifdef CONFIG_X86_64
 121         u64                   msr_host_kernel_gs_base;
 122         u64                   msr_guest_kernel_gs_base;
 123 #endif
 124         struct vmcs          *vmcs;
 125         struct {
 126                 int           loaded;
 127                 u16           fs_sel, gs_sel, ldt_sel;
 128                 int           gs_ldt_reload_needed;
 129                 int           fs_reload_needed;
 130         } host_state;
 131         struct {
 132                 int vm86_active;
 133                 u8 save_iopl;
 134                 struct kvm_save_segment {
 135                         u16 selector;
 136                         unsigned long base;
 137                         u32 limit;
 138                         u32 ar;
 139                 } tr, es, ds, fs, gs;
 140                 struct {
 141                         bool pending;
 142                         u8 vector;
 143                         unsigned rip;
 144                 } irq;
 145         } rmode;
 146         int vpid;
 147         bool emulation_required;
 148
 149         /* Support for vnmi-less CPUs */
 150         int soft_vnmi_blocked;
 151         ktime_t entry_time;
 152         s64 vnmi_blocked_time;
 153         u32 exit_reason;
 154 };
 155
 156 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 157 {
 158         return container_of(vcpu, struct vcpu_vmx, vcpu);
 159 }
 160
 161 static int init_rmode(struct kvm *kvm);
 162 static u64 construct_eptp(unsigned long root_hpa);
 163
 164 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 165 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 166 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 167
 168 static unsigned long *vmx_io_bitmap_a;
 169 static unsigned long *vmx_io_bitmap_b;
 170 static unsigned long *vmx_msr_bitmap_legacy;
 171 static unsigned long *vmx_msr_bitmap_longmode;
 172
 173 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 174 static DEFINE_SPINLOCK(vmx_vpid_lock);
 175
 176 static struct vmcs_config {
 177         int size;
 178         int order;
 179         u32 revision_id;
 180         u32 pin_based_exec_ctrl;
 181         u32 cpu_based_exec_ctrl;
 182         u32 cpu_based_2nd_exec_ctrl;
 183         u32 vmexit_ctrl;
 184         u32 vmentry_ctrl;
 185 } vmcs_config;
 186
 187 static struct vmx_capability {
 188         u32 ept;
 189         u32 vpid;
 190 } vmx_capability;
 191
 192 #define VMX_SEGMENT_FIELD(seg)                                  \
 193         [VCPU_SREG_##seg] = {                                   \
 194                 .selector = GUEST_##seg##_SELECTOR,             \
 195                 .base = GUEST_##seg##_BASE,                     \
 196                 .limit = GUEST_##seg##_LIMIT,                   \
 197                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 198         }
 199
 200 static struct kvm_vmx_segment_field {
 201         unsigned selector;
 202         unsigned base;
 203         unsigned limit;
 204         unsigned ar_bytes;
 205 } kvm_vmx_segment_fields[] = {
 206         VMX_SEGMENT_FIELD(CS),
 207         VMX_SEGMENT_FIELD(DS),
 208         VMX_SEGMENT_FIELD(ES),
 209         VMX_SEGMENT_FIELD(FS),
 210         VMX_SEGMENT_FIELD(GS),
 211         VMX_SEGMENT_FIELD(SS),
 212         VMX_SEGMENT_FIELD(TR),
 213         VMX_SEGMENT_FIELD(LDTR),
 214 };
 215
 216 static u64 host_efer;
 217
 218 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 219
 220 /*
 221  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 222  * away by decrementing the array size.
 223  */
 224 static const u32 vmx_msr_index[] = {
 225 #ifdef CONFIG_X86_64
 226         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 227 #endif
 228         MSR_EFER, MSR_K6_STAR,
 229 };
 230 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 231
 232 static inline int is_page_fault(u32 intr_info)
 233 {
 234         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 235                              INTR_INFO_VALID_MASK)) ==
 236                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 237 }
 238
 239 static inline int is_no_device(u32 intr_info)
 240 {
 241         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 242                              INTR_INFO_VALID_MASK)) ==
 243                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 244 }
 245
 246 static inline int is_invalid_opcode(u32 intr_info)
 247 {
 248         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 249                              INTR_INFO_VALID_MASK)) ==
 250                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 251 }
 252
 253 static inline int is_external_interrupt(u32 intr_info)
 254 {
 255         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 256                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 257 }
 258
 259 static inline int is_machine_check(u32 intr_info)
 260 {
 261         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 262                              INTR_INFO_VALID_MASK)) ==
 263                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 264 }
 265
 266 static inline int cpu_has_vmx_msr_bitmap(void)
 267 {
 268         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 269 }
 270
 271 static inline int cpu_has_vmx_tpr_shadow(void)
 272 {
 273         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 274 }
 275
 276 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 277 {
 278         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 279 }
 280
 281 static inline int cpu_has_secondary_exec_ctrls(void)
 282 {
 283         return vmcs_config.cpu_based_exec_ctrl &
 284                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 285 }
 286
 287 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 288 {
 289         return vmcs_config.cpu_based_2nd_exec_ctrl &
 290                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 291 }
 292
 293 static inline bool cpu_has_vmx_flexpriority(void)
 294 {
 295         return cpu_has_vmx_tpr_shadow() &&
 296                 cpu_has_vmx_virtualize_apic_accesses();
 297 }
 298
 299 static inline bool cpu_has_vmx_ept_execute_only(void)
 300 {
 301         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 302 }
 303
 304 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 305 {
 306         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 307 }
 308
 309 static inline bool cpu_has_vmx_eptp_writeback(void)
 310 {
 311         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 312 }
 313
 314 static inline bool cpu_has_vmx_ept_2m_page(void)
 315 {
 316         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 317 }
 318
 319 static inline int cpu_has_vmx_invept_individual_addr(void)
 320 {
 321         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 322 }
 323
 324 static inline int cpu_has_vmx_invept_context(void)
 325 {
 326         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 327 }
 328
 329 static inline int cpu_has_vmx_invept_global(void)
 330 {
 331         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 332 }
 333
 334 static inline int cpu_has_vmx_ept(void)
 335 {
 336         return vmcs_config.cpu_based_2nd_exec_ctrl &
 337                 SECONDARY_EXEC_ENABLE_EPT;
 338 }
 339
 340 static inline int cpu_has_vmx_unrestricted_guest(void)
 341 {
 342         return vmcs_config.cpu_based_2nd_exec_ctrl &
 343                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 344 }
 345
 346 static inline int cpu_has_vmx_ple(void)
 347 {
 348         return vmcs_config.cpu_based_2nd_exec_ctrl &
 349                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 350 }
 351
 352 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 353 {
 354         return flexpriority_enabled &&
 355                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 356                 (irqchip_in_kernel(kvm));
 357 }
 358
 359 static inline int cpu_has_vmx_vpid(void)
 360 {
 361         return vmcs_config.cpu_based_2nd_exec_ctrl &
 362                 SECONDARY_EXEC_ENABLE_VPID;
 363 }
 364
 365 static inline int cpu_has_virtual_nmis(void)
 366 {
 367         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 368 }
 369
 370 static inline bool report_flexpriority(void)
 371 {
 372         return flexpriority_enabled;
 373 }
 374
 375 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 376 {
 377         int i;
 378
 379         for (i = 0; i < vmx->nmsrs; ++i)
 380                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 381                         return i;
 382         return -1;
 383 }
 384
 385 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 386 {
 387     struct {
 388         u64 vpid : 16;
 389         u64 rsvd : 48;
 390         u64 gva;
 391     } operand = { vpid, 0, gva };
 392
 393     asm volatile (__ex(ASM_VMX_INVVPID)
 394                   /* CF==1 or ZF==1 --> rc = -1 */
 395                   "; ja 1f ; ud2 ; 1:"
 396                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 397 }
 398
 399 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 400 {
 401         struct {
 402                 u64 eptp, gpa;
 403         } operand = {eptp, gpa};
 404
 405         asm volatile (__ex(ASM_VMX_INVEPT)
 406                         /* CF==1 or ZF==1 --> rc = -1 */
 407                         "; ja 1f ; ud2 ; 1:\n"
 408                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 409 }
 410
 411 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 412 {
 413         int i;
 414
 415         i = __find_msr_index(vmx, msr);
 416         if (i >= 0)
 417                 return &vmx->guest_msrs[i];
 418         return NULL;
 419 }
 420
 421 static void vmcs_clear(struct vmcs *vmcs)
 422 {
 423         u64 phys_addr = __pa(vmcs);
 424         u8 error;
 425
 426         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 427                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 428                       : "cc", "memory");
 429         if (error)
 430                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 431                        vmcs, phys_addr);
 432 }
 433
 434 static void __vcpu_clear(void *arg)
 435 {
 436         struct vcpu_vmx *vmx = arg;
 437         int cpu = raw_smp_processor_id();
 438
 439         if (vmx->vcpu.cpu == cpu)
 440                 vmcs_clear(vmx->vmcs);
 441         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 442                 per_cpu(current_vmcs, cpu) = NULL;
 443         rdtscll(vmx->vcpu.arch.host_tsc);
 444         list_del(&vmx->local_vcpus_link);
 445         vmx->vcpu.cpu = -1;
 446         vmx->launched = 0;
 447 }
 448
 449 static void vcpu_clear(struct vcpu_vmx *vmx)
 450 {
 451         if (vmx->vcpu.cpu == -1)
 452                 return;
 453         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 454 }
 455
 456 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 457 {
 458         if (vmx->vpid == 0)
 459                 return;
 460
 461         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 462 }
 463
 464 static inline void ept_sync_global(void)
 465 {
 466         if (cpu_has_vmx_invept_global())
 467                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 468 }
 469
 470 static inline void ept_sync_context(u64 eptp)
 471 {
 472         if (enable_ept) {
 473                 if (cpu_has_vmx_invept_context())
 474                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 475                 else
 476                         ept_sync_global();
 477         }
 478 }
 479
 480 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 481 {
 482         if (enable_ept) {
 483                 if (cpu_has_vmx_invept_individual_addr())
 484                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 485                                         eptp, gpa);
 486                 else
 487                         ept_sync_context(eptp);
 488         }
 489 }
 490
 491 static unsigned long vmcs_readl(unsigned long field)
 492 {
 493         unsigned long value;
 494
 495         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 496                       : "=a"(value) : "d"(field) : "cc");
 497         return value;
 498 }
 499
 500 static u16 vmcs_read16(unsigned long field)
 501 {
 502         return vmcs_readl(field);
 503 }
 504
 505 static u32 vmcs_read32(unsigned long field)
 506 {
 507         return vmcs_readl(field);
 508 }
 509
 510 static u64 vmcs_read64(unsigned long field)
 511 {
 512 #ifdef CONFIG_X86_64
 513         return vmcs_readl(field);
 514 #else
 515         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 516 #endif
 517 }
 518
 519 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 520 {
 521         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 522                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 523         dump_stack();
 524 }
 525
 526 static void vmcs_writel(unsigned long field, unsigned long value)
 527 {
 528         u8 error;
 529
 530         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 531                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 532         if (unlikely(error))
 533                 vmwrite_error(field, value);
 534 }
 535
 536 static void vmcs_write16(unsigned long field, u16 value)
 537 {
 538         vmcs_writel(field, value);
 539 }
 540
 541 static void vmcs_write32(unsigned long field, u32 value)
 542 {
 543         vmcs_writel(field, value);
 544 }
 545
 546 static void vmcs_write64(unsigned long field, u64 value)
 547 {
 548         vmcs_writel(field, value);
 549 #ifndef CONFIG_X86_64
 550         asm volatile ("");
 551         vmcs_writel(field+1, value >> 32);
 552 #endif
 553 }
 554
 555 static void vmcs_clear_bits(unsigned long field, u32 mask)
 556 {
 557         vmcs_writel(field, vmcs_readl(field) & ~mask);
 558 }
 559
 560 static void vmcs_set_bits(unsigned long field, u32 mask)
 561 {
 562         vmcs_writel(field, vmcs_readl(field) | mask);
 563 }
 564
 565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 566 {
 567         u32 eb;
 568
 569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 570         if (!vcpu->fpu_active)
 571                 eb |= 1u << NM_VECTOR;
 572         /*
 573          * Unconditionally intercept #DB so we can maintain dr6 without
 574          * reading it every exit.
 575          */
 576         eb |= 1u << DB_VECTOR;
 577         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 578                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 579                         eb |= 1u << BP_VECTOR;
 580         }
 581         if (to_vmx(vcpu)->rmode.vm86_active)
 582                 eb = ~0;
 583         if (enable_ept)
 584                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 585         vmcs_write32(EXCEPTION_BITMAP, eb);
 586 }
 587
 588 static void reload_tss(void)
 589 {
 590         /*
 591          * VT restores TR but not its size.  Useless.
 592          */
 593         struct descriptor_table gdt;
 594         struct desc_struct *descs;
 595
 596         kvm_get_gdt(&gdt);
 597         descs = (void *)gdt.base;
 598         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 599         load_TR_desc();
 600 }
 601
 602 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 603 {
 604         u64 guest_efer;
 605         u64 ignore_bits;
 606
 607         guest_efer = vmx->vcpu.arch.shadow_efer;
 608
 609         /*
 610          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 611          * outside long mode
 612          */
 613         ignore_bits = EFER_NX | EFER_SCE;
 614 #ifdef CONFIG_X86_64
 615         ignore_bits |= EFER_LMA | EFER_LME;
 616         /* SCE is meaningful only in long mode on Intel */
 617         if (guest_efer & EFER_LMA)
 618                 ignore_bits &= ~(u64)EFER_SCE;
 619 #endif
 620         guest_efer &= ~ignore_bits;
 621         guest_efer |= host_efer & ignore_bits;
 622         vmx->guest_msrs[efer_offset].data = guest_efer;
 623         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 624         return true;
 625 }
 626
 627 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 628 {
 629         struct vcpu_vmx *vmx = to_vmx(vcpu);
 630         int i;
 631
 632         if (vmx->host_state.loaded)
 633                 return;
 634
 635         vmx->host_state.loaded = 1;
 636         /*
 637          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 638          * allow segment selectors with cpl > 0 or ti == 1.
 639          */
 640         vmx->host_state.ldt_sel = kvm_read_ldt();
 641         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 642         vmx->host_state.fs_sel = kvm_read_fs();
 643         if (!(vmx->host_state.fs_sel & 7)) {
 644                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 645                 vmx->host_state.fs_reload_needed = 0;
 646         } else {
 647                 vmcs_write16(HOST_FS_SELECTOR, 0);
 648                 vmx->host_state.fs_reload_needed = 1;
 649         }
 650         vmx->host_state.gs_sel = kvm_read_gs();
 651         if (!(vmx->host_state.gs_sel & 7))
 652                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 653         else {
 654                 vmcs_write16(HOST_GS_SELECTOR, 0);
 655                 vmx->host_state.gs_ldt_reload_needed = 1;
 656         }
 657
 658 #ifdef CONFIG_X86_64
 659         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 660         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 661 #else
 662         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 663         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 664 #endif
 665
 666 #ifdef CONFIG_X86_64
 667         if (is_long_mode(&vmx->vcpu)) {
 668                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 669                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 670         }
 671 #endif
 672         for (i = 0; i < vmx->save_nmsrs; ++i)
 673                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 674                                    vmx->guest_msrs[i].data,
 675                                    vmx->guest_msrs[i].mask);
 676 }
 677
 678 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 679 {
 680         unsigned long flags;
 681
 682         if (!vmx->host_state.loaded)
 683                 return;
 684
 685         ++vmx->vcpu.stat.host_state_reload;
 686         vmx->host_state.loaded = 0;
 687         if (vmx->host_state.fs_reload_needed)
 688                 kvm_load_fs(vmx->host_state.fs_sel);
 689         if (vmx->host_state.gs_ldt_reload_needed) {
 690                 kvm_load_ldt(vmx->host_state.ldt_sel);
 691                 /*
 692                  * If we have to reload gs, we must take care to
 693                  * preserve our gs base.
 694                  */
 695                 local_irq_save(flags);
 696                 kvm_load_gs(vmx->host_state.gs_sel);
 697 #ifdef CONFIG_X86_64
 698                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 699 #endif
 700                 local_irq_restore(flags);
 701         }
 702         reload_tss();
 703 #ifdef CONFIG_X86_64
 704         if (is_long_mode(&vmx->vcpu)) {
 705                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 706                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 707         }
 708 #endif
 709 }
 710
 711 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 712 {
 713         preempt_disable();
 714         __vmx_load_host_state(vmx);
 715         preempt_enable();
 716 }
 717
 718 /*
 719  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 720  * vcpu mutex is already taken.
 721  */
 722 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 723 {
 724         struct vcpu_vmx *vmx = to_vmx(vcpu);
 725         u64 phys_addr = __pa(vmx->vmcs);
 726         u64 tsc_this, delta, new_offset;
 727
 728         if (vcpu->cpu != cpu) {
 729                 vcpu_clear(vmx);
 730                 kvm_migrate_timers(vcpu);
 731                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 732                 local_irq_disable();
 733                 list_add(&vmx->local_vcpus_link,
 734                          &per_cpu(vcpus_on_cpu, cpu));
 735                 local_irq_enable();
 736         }
 737
 738         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 739                 u8 error;
 740
 741                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 742                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 743                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 744                               : "cc");
 745                 if (error)
 746                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 747                                vmx->vmcs, phys_addr);
 748         }
 749
 750         if (vcpu->cpu != cpu) {
 751                 struct descriptor_table dt;
 752                 unsigned long sysenter_esp;
 753
 754                 vcpu->cpu = cpu;
 755                 /*
 756                  * Linux uses per-cpu TSS and GDT, so set these when switching
 757                  * processors.
 758                  */
 759                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 760                 kvm_get_gdt(&dt);
 761                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 762
 763                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 764                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 765
 766                 /*
 767                  * Make sure the time stamp counter is monotonous.
 768                  */
 769                 rdtscll(tsc_this);
 770                 if (tsc_this < vcpu->arch.host_tsc) {
 771                         delta = vcpu->arch.host_tsc - tsc_this;
 772                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 773                         vmcs_write64(TSC_OFFSET, new_offset);
 774                 }
 775         }
 776 }
 777
 778 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 779 {
 780         __vmx_load_host_state(to_vmx(vcpu));
 781 }
 782
 783 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 784 {
 785         if (vcpu->fpu_active)
 786                 return;
 787         vcpu->fpu_active = 1;
 788         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 789         if (vcpu->arch.cr0 & X86_CR0_TS)
 790                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 791         update_exception_bitmap(vcpu);
 792 }
 793
 794 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 795 {
 796         if (!vcpu->fpu_active)
 797                 return;
 798         vcpu->fpu_active = 0;
 799         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 800         update_exception_bitmap(vcpu);
 801 }
 802
 803 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 804 {
 805         unsigned long rflags;
 806
 807         rflags = vmcs_readl(GUEST_RFLAGS);
 808         if (to_vmx(vcpu)->rmode.vm86_active)
 809                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 810         return rflags;
 811 }
 812
 813 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 814 {
 815         if (to_vmx(vcpu)->rmode.vm86_active)
 816                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 817         vmcs_writel(GUEST_RFLAGS, rflags);
 818 }
 819
 820 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 821 {
 822         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 823         int ret = 0;
 824
 825         if (interruptibility & GUEST_INTR_STATE_STI)
 826                 ret |= X86_SHADOW_INT_STI;
 827         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 828                 ret |= X86_SHADOW_INT_MOV_SS;
 829
 830         return ret & mask;
 831 }
 832
 833 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 834 {
 835         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 836         u32 interruptibility = interruptibility_old;
 837
 838         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 839
 840         if (mask & X86_SHADOW_INT_MOV_SS)
 841                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 842         if (mask & X86_SHADOW_INT_STI)
 843                 interruptibility |= GUEST_INTR_STATE_STI;
 844
 845         if ((interruptibility != interruptibility_old))
 846                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 847 }
 848
 849 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 850 {
 851         unsigned long rip;
 852
 853         rip = kvm_rip_read(vcpu);
 854         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 855         kvm_rip_write(vcpu, rip);
 856
 857         /* skipping an emulated instruction also counts */
 858         vmx_set_interrupt_shadow(vcpu, 0);
 859 }
 860
 861 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 862                                 bool has_error_code, u32 error_code)
 863 {
 864         struct vcpu_vmx *vmx = to_vmx(vcpu);
 865         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 866
 867         if (has_error_code) {
 868                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 869                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 870         }
 871
 872         if (vmx->rmode.vm86_active) {
 873                 vmx->rmode.irq.pending = true;
 874                 vmx->rmode.irq.vector = nr;
 875                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 876                 if (kvm_exception_is_soft(nr))
 877                         vmx->rmode.irq.rip +=
 878                                 vmx->vcpu.arch.event_exit_inst_len;
 879                 intr_info |= INTR_TYPE_SOFT_INTR;
 880                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 881                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 882                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 883                 return;
 884         }
 885
 886         if (kvm_exception_is_soft(nr)) {
 887                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 888                              vmx->vcpu.arch.event_exit_inst_len);
 889                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 890         } else
 891                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 892
 893         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 894 }
 895
 896 /*
 897  * Swap MSR entry in host/guest MSR entry array.
 898  */
 899 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 900 {
 901         struct shared_msr_entry tmp;
 902
 903         tmp = vmx->guest_msrs[to];
 904         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 905         vmx->guest_msrs[from] = tmp;
 906 }
 907
 908 /*
 909  * Set up the vmcs to automatically save and restore system
 910  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 911  * mode, as fiddling with msrs is very expensive.
 912  */
 913 static void setup_msrs(struct vcpu_vmx *vmx)
 914 {
 915         int save_nmsrs, index;
 916         unsigned long *msr_bitmap;
 917
 918         vmx_load_host_state(vmx);
 919         save_nmsrs = 0;
 920 #ifdef CONFIG_X86_64
 921         if (is_long_mode(&vmx->vcpu)) {
 922                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 923                 if (index >= 0)
 924                         move_msr_up(vmx, index, save_nmsrs++);
 925                 index = __find_msr_index(vmx, MSR_LSTAR);
 926                 if (index >= 0)
 927                         move_msr_up(vmx, index, save_nmsrs++);
 928                 index = __find_msr_index(vmx, MSR_CSTAR);
 929                 if (index >= 0)
 930                         move_msr_up(vmx, index, save_nmsrs++);
 931                 /*
 932                  * MSR_K6_STAR is only needed on long mode guests, and only
 933                  * if efer.sce is enabled.
 934                  */
 935                 index = __find_msr_index(vmx, MSR_K6_STAR);
 936                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 937                         move_msr_up(vmx, index, save_nmsrs++);
 938         }
 939 #endif
 940         index = __find_msr_index(vmx, MSR_EFER);
 941         if (index >= 0 && update_transition_efer(vmx, index))
 942                 move_msr_up(vmx, index, save_nmsrs++);
 943
 944         vmx->save_nmsrs = save_nmsrs;
 945
 946         if (cpu_has_vmx_msr_bitmap()) {
 947                 if (is_long_mode(&vmx->vcpu))
 948                         msr_bitmap = vmx_msr_bitmap_longmode;
 949                 else
 950                         msr_bitmap = vmx_msr_bitmap_legacy;
 951
 952                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 953         }
 954 }
 955
 956 /*
 957  * reads and returns guest's timestamp counter "register"
 958  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 959  */
 960 static u64 guest_read_tsc(void)
 961 {
 962         u64 host_tsc, tsc_offset;
 963
 964         rdtscll(host_tsc);
 965         tsc_offset = vmcs_read64(TSC_OFFSET);
 966         return host_tsc + tsc_offset;
 967 }
 968
 969 /*
 970  * writes 'guest_tsc' into guest's timestamp counter "register"
 971  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 972  */
 973 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 974 {
 975         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 976 }
 977
 978 /*
 979  * Reads an msr value (of 'msr_index') into 'pdata'.
 980  * Returns 0 on success, non-0 otherwise.
 981  * Assumes vcpu_load() was already called.
 982  */
 983 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 984 {
 985         u64 data;
 986         struct shared_msr_entry *msr;
 987
 988         if (!pdata) {
 989                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 990                 return -EINVAL;
 991         }
 992
 993         switch (msr_index) {
 994 #ifdef CONFIG_X86_64
 995         case MSR_FS_BASE:
 996                 data = vmcs_readl(GUEST_FS_BASE);
 997                 break;
 998         case MSR_GS_BASE:
 999                 data = vmcs_readl(GUEST_GS_BASE);
1000                 break;
1001         case MSR_KERNEL_GS_BASE:
1002                 vmx_load_host_state(to_vmx(vcpu));
1003                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1004                 break;
1005 #endif
1006         case MSR_EFER:
1007                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1008         case MSR_IA32_TSC:
1009                 data = guest_read_tsc();
1010                 break;
1011         case MSR_IA32_SYSENTER_CS:
1012                 data = vmcs_read32(GUEST_SYSENTER_CS);
1013                 break;
1014         case MSR_IA32_SYSENTER_EIP:
1015                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1016                 break;
1017         case MSR_IA32_SYSENTER_ESP:
1018                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1019                 break;
1020         default:
1021                 vmx_load_host_state(to_vmx(vcpu));
1022                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1023                 if (msr) {
1024                         vmx_load_host_state(to_vmx(vcpu));
1025                         data = msr->data;
1026                         break;
1027                 }
1028                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1029         }
1030
1031         *pdata = data;
1032         return 0;
1033 }
1034
1035 /*
1036  * Writes msr value into into the appropriate "register".
1037  * Returns 0 on success, non-0 otherwise.
1038  * Assumes vcpu_load() was already called.
1039  */
1040 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1041 {
1042         struct vcpu_vmx *vmx = to_vmx(vcpu);
1043         struct shared_msr_entry *msr;
1044         u64 host_tsc;
1045         int ret = 0;
1046
1047         switch (msr_index) {
1048         case MSR_EFER:
1049                 vmx_load_host_state(vmx);
1050                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1051                 break;
1052 #ifdef CONFIG_X86_64
1053         case MSR_FS_BASE:
1054                 vmcs_writel(GUEST_FS_BASE, data);
1055                 break;
1056         case MSR_GS_BASE:
1057                 vmcs_writel(GUEST_GS_BASE, data);
1058                 break;
1059         case MSR_KERNEL_GS_BASE:
1060                 vmx_load_host_state(vmx);
1061                 vmx->msr_guest_kernel_gs_base = data;
1062                 break;
1063 #endif
1064         case MSR_IA32_SYSENTER_CS:
1065                 vmcs_write32(GUEST_SYSENTER_CS, data);
1066                 break;
1067         case MSR_IA32_SYSENTER_EIP:
1068                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1069                 break;
1070         case MSR_IA32_SYSENTER_ESP:
1071                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1072                 break;
1073         case MSR_IA32_TSC:
1074                 rdtscll(host_tsc);
1075                 guest_write_tsc(data, host_tsc);
1076                 break;
1077         case MSR_IA32_CR_PAT:
1078                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1079                         vmcs_write64(GUEST_IA32_PAT, data);
1080                         vcpu->arch.pat = data;
1081                         break;
1082                 }
1083                 /* Otherwise falls through to kvm_set_msr_common */
1084         default:
1085                 msr = find_msr_entry(vmx, msr_index);
1086                 if (msr) {
1087                         vmx_load_host_state(vmx);
1088                         msr->data = data;
1089                         break;
1090                 }
1091                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1092         }
1093
1094         return ret;
1095 }
1096
1097 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1098 {
1099         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1100         switch (reg) {
1101         case VCPU_REGS_RSP:
1102                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1103                 break;
1104         case VCPU_REGS_RIP:
1105                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1106                 break;
1107         case VCPU_EXREG_PDPTR:
1108                 if (enable_ept)
1109                         ept_save_pdptrs(vcpu);
1110                 break;
1111         default:
1112                 break;
1113         }
1114 }
1115
1116 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1117 {
1118         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1119                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1120         else
1121                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1122
1123         update_exception_bitmap(vcpu);
1124 }
1125
1126 static __init int cpu_has_kvm_support(void)
1127 {
1128         return cpu_has_vmx();
1129 }
1130
1131 static __init int vmx_disabled_by_bios(void)
1132 {
1133         u64 msr;
1134
1135         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1136         return (msr & (FEATURE_CONTROL_LOCKED |
1137                        FEATURE_CONTROL_VMXON_ENABLED))
1138             == FEATURE_CONTROL_LOCKED;
1139         /* locked but not enabled */
1140 }
1141
1142 static int hardware_enable(void *garbage)
1143 {
1144         int cpu = raw_smp_processor_id();
1145         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1146         u64 old;
1147
1148         if (read_cr4() & X86_CR4_VMXE)
1149                 return -EBUSY;
1150
1151         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1152         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1153         if ((old & (FEATURE_CONTROL_LOCKED |
1154                     FEATURE_CONTROL_VMXON_ENABLED))
1155             != (FEATURE_CONTROL_LOCKED |
1156                 FEATURE_CONTROL_VMXON_ENABLED))
1157                 /* enable and lock */
1158                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1159                        FEATURE_CONTROL_LOCKED |
1160                        FEATURE_CONTROL_VMXON_ENABLED);
1161         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1162         asm volatile (ASM_VMX_VMXON_RAX
1163                       : : "a"(&phys_addr), "m"(phys_addr)
1164                       : "memory", "cc");
1165
1166         ept_sync_global();
1167
1168         return 0;
1169 }
1170
1171 static void vmclear_local_vcpus(void)
1172 {
1173         int cpu = raw_smp_processor_id();
1174         struct vcpu_vmx *vmx, *n;
1175
1176         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1177                                  local_vcpus_link)
1178                 __vcpu_clear(vmx);
1179 }
1180
1181
1182 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1183  * tricks.
1184  */
1185 static void kvm_cpu_vmxoff(void)
1186 {
1187         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1188         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1189 }
1190
1191 static void hardware_disable(void *garbage)
1192 {
1193         vmclear_local_vcpus();
1194         kvm_cpu_vmxoff();
1195 }
1196
1197 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1198                                       u32 msr, u32 *result)
1199 {
1200         u32 vmx_msr_low, vmx_msr_high;
1201         u32 ctl = ctl_min | ctl_opt;
1202
1203         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1204
1205         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1206         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1207
1208         /* Ensure minimum (required) set of control bits are supported. */
1209         if (ctl_min & ~ctl)
1210                 return -EIO;
1211
1212         *result = ctl;
1213         return 0;
1214 }
1215
1216 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1217 {
1218         u32 vmx_msr_low, vmx_msr_high;
1219         u32 min, opt, min2, opt2;
1220         u32 _pin_based_exec_control = 0;
1221         u32 _cpu_based_exec_control = 0;
1222         u32 _cpu_based_2nd_exec_control = 0;
1223         u32 _vmexit_control = 0;
1224         u32 _vmentry_control = 0;
1225
1226         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1227         opt = PIN_BASED_VIRTUAL_NMIS;
1228         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1229                                 &_pin_based_exec_control) < 0)
1230                 return -EIO;
1231
1232         min = CPU_BASED_HLT_EXITING |
1233 #ifdef CONFIG_X86_64
1234               CPU_BASED_CR8_LOAD_EXITING |
1235               CPU_BASED_CR8_STORE_EXITING |
1236 #endif
1237               CPU_BASED_CR3_LOAD_EXITING |
1238               CPU_BASED_CR3_STORE_EXITING |
1239               CPU_BASED_USE_IO_BITMAPS |
1240               CPU_BASED_MOV_DR_EXITING |
1241               CPU_BASED_USE_TSC_OFFSETING |
1242               CPU_BASED_MWAIT_EXITING |
1243               CPU_BASED_MONITOR_EXITING |
1244               CPU_BASED_INVLPG_EXITING;
1245         opt = CPU_BASED_TPR_SHADOW |
1246               CPU_BASED_USE_MSR_BITMAPS |
1247               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1248         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1249                                 &_cpu_based_exec_control) < 0)
1250                 return -EIO;
1251 #ifdef CONFIG_X86_64
1252         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1253                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1254                                            ~CPU_BASED_CR8_STORE_EXITING;
1255 #endif
1256         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1257                 min2 = 0;
1258                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1259                         SECONDARY_EXEC_WBINVD_EXITING |
1260                         SECONDARY_EXEC_ENABLE_VPID |
1261                         SECONDARY_EXEC_ENABLE_EPT |
1262                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1263                         SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1264                 if (adjust_vmx_controls(min2, opt2,
1265                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1266                                         &_cpu_based_2nd_exec_control) < 0)
1267                         return -EIO;
1268         }
1269 #ifndef CONFIG_X86_64
1270         if (!(_cpu_based_2nd_exec_control &
1271                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1272                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1273 #endif
1274         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1275                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1276                    enabled */
1277                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1278                                              CPU_BASED_CR3_STORE_EXITING |
1279                                              CPU_BASED_INVLPG_EXITING);
1280                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1281                       vmx_capability.ept, vmx_capability.vpid);
1282         }
1283
1284         min = 0;
1285 #ifdef CONFIG_X86_64
1286         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1287 #endif
1288         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1289         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1290                                 &_vmexit_control) < 0)
1291                 return -EIO;
1292
1293         min = 0;
1294         opt = VM_ENTRY_LOAD_IA32_PAT;
1295         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1296                                 &_vmentry_control) < 0)
1297                 return -EIO;
1298
1299         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1300
1301         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1302         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1303                 return -EIO;
1304
1305 #ifdef CONFIG_X86_64
1306         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1307         if (vmx_msr_high & (1u<<16))
1308                 return -EIO;
1309 #endif
1310
1311         /* Require Write-Back (WB) memory type for VMCS accesses. */
1312         if (((vmx_msr_high >> 18) & 15) != 6)
1313                 return -EIO;
1314
1315         vmcs_conf->size = vmx_msr_high & 0x1fff;
1316         vmcs_conf->order = get_order(vmcs_config.size);
1317         vmcs_conf->revision_id = vmx_msr_low;
1318
1319         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1320         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1321         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1322         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1323         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1324
1325         return 0;
1326 }
1327
1328 static struct vmcs *alloc_vmcs_cpu(int cpu)
1329 {
1330         int node = cpu_to_node(cpu);
1331         struct page *pages;
1332         struct vmcs *vmcs;
1333
1334         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1335         if (!pages)
1336                 return NULL;
1337         vmcs = page_address(pages);
1338         memset(vmcs, 0, vmcs_config.size);
1339         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1340         return vmcs;
1341 }
1342
1343 static struct vmcs *alloc_vmcs(void)
1344 {
1345         return alloc_vmcs_cpu(raw_smp_processor_id());
1346 }
1347
1348 static void free_vmcs(struct vmcs *vmcs)
1349 {
1350         free_pages((unsigned long)vmcs, vmcs_config.order);
1351 }
1352
1353 static void free_kvm_area(void)
1354 {
1355         int cpu;
1356
1357         for_each_possible_cpu(cpu) {
1358                 free_vmcs(per_cpu(vmxarea, cpu));
1359                 per_cpu(vmxarea, cpu) = NULL;
1360         }
1361 }
1362
1363 static __init int alloc_kvm_area(void)
1364 {
1365         int cpu;
1366
1367         for_each_possible_cpu(cpu) {
1368                 struct vmcs *vmcs;
1369
1370                 vmcs = alloc_vmcs_cpu(cpu);
1371                 if (!vmcs) {
1372                         free_kvm_area();
1373                         return -ENOMEM;
1374                 }
1375
1376                 per_cpu(vmxarea, cpu) = vmcs;
1377         }
1378         return 0;
1379 }
1380
1381 static __init int hardware_setup(void)
1382 {
1383         if (setup_vmcs_config(&vmcs_config) < 0)
1384                 return -EIO;
1385
1386         if (boot_cpu_has(X86_FEATURE_NX))
1387                 kvm_enable_efer_bits(EFER_NX);
1388
1389         if (!cpu_has_vmx_vpid())
1390                 enable_vpid = 0;
1391
1392         if (!cpu_has_vmx_ept()) {
1393                 enable_ept = 0;
1394                 enable_unrestricted_guest = 0;
1395         }
1396
1397         if (!cpu_has_vmx_unrestricted_guest())
1398                 enable_unrestricted_guest = 0;
1399
1400         if (!cpu_has_vmx_flexpriority())
1401                 flexpriority_enabled = 0;
1402
1403         if (!cpu_has_vmx_tpr_shadow())
1404                 kvm_x86_ops->update_cr8_intercept = NULL;
1405
1406         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1407                 kvm_disable_largepages();
1408
1409         if (!cpu_has_vmx_ple())
1410                 ple_gap = 0;
1411
1412         return alloc_kvm_area();
1413 }
1414
1415 static __exit void hardware_unsetup(void)
1416 {
1417         free_kvm_area();
1418 }
1419
1420 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1421 {
1422         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1423
1424         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1425                 vmcs_write16(sf->selector, save->selector);
1426                 vmcs_writel(sf->base, save->base);
1427                 vmcs_write32(sf->limit, save->limit);
1428                 vmcs_write32(sf->ar_bytes, save->ar);
1429         } else {
1430                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1431                         << AR_DPL_SHIFT;
1432                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1433         }
1434 }
1435
1436 static void enter_pmode(struct kvm_vcpu *vcpu)
1437 {
1438         unsigned long flags;
1439         struct vcpu_vmx *vmx = to_vmx(vcpu);
1440
1441         vmx->emulation_required = 1;
1442         vmx->rmode.vm86_active = 0;
1443
1444         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1445         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1446         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1447
1448         flags = vmcs_readl(GUEST_RFLAGS);
1449         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1450         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1451         vmcs_writel(GUEST_RFLAGS, flags);
1452
1453         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1454                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1455
1456         update_exception_bitmap(vcpu);
1457
1458         if (emulate_invalid_guest_state)
1459                 return;
1460
1461         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1462         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1463         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1464         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1465
1466         vmcs_write16(GUEST_SS_SELECTOR, 0);
1467         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1468
1469         vmcs_write16(GUEST_CS_SELECTOR,
1470                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1471         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1472 }
1473
1474 static gva_t rmode_tss_base(struct kvm *kvm)
1475 {
1476         if (!kvm->arch.tss_addr) {
1477                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1478                                  kvm->memslots[0].npages - 3;
1479                 return base_gfn << PAGE_SHIFT;
1480         }
1481         return kvm->arch.tss_addr;
1482 }
1483
1484 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1485 {
1486         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1487
1488         save->selector = vmcs_read16(sf->selector);
1489         save->base = vmcs_readl(sf->base);
1490         save->limit = vmcs_read32(sf->limit);
1491         save->ar = vmcs_read32(sf->ar_bytes);
1492         vmcs_write16(sf->selector, save->base >> 4);
1493         vmcs_write32(sf->base, save->base & 0xfffff);
1494         vmcs_write32(sf->limit, 0xffff);
1495         vmcs_write32(sf->ar_bytes, 0xf3);
1496 }
1497
1498 static void enter_rmode(struct kvm_vcpu *vcpu)
1499 {
1500         unsigned long flags;
1501         struct vcpu_vmx *vmx = to_vmx(vcpu);
1502
1503         if (enable_unrestricted_guest)
1504                 return;
1505
1506         vmx->emulation_required = 1;
1507         vmx->rmode.vm86_active = 1;
1508
1509         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1510         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1511
1512         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1513         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1514
1515         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1516         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1517
1518         flags = vmcs_readl(GUEST_RFLAGS);
1519         vmx->rmode.save_iopl
1520                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1521
1522         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1523
1524         vmcs_writel(GUEST_RFLAGS, flags);
1525         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1526         update_exception_bitmap(vcpu);
1527
1528         if (emulate_invalid_guest_state)
1529                 goto continue_rmode;
1530
1531         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1532         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1533         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1534
1535         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1536         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1537         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1538                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1539         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1540
1541         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1542         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1543         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1544         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1545
1546 continue_rmode:
1547         kvm_mmu_reset_context(vcpu);
1548         init_rmode(vcpu->kvm);
1549 }
1550
1551 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1552 {
1553         struct vcpu_vmx *vmx = to_vmx(vcpu);
1554         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1555
1556         if (!msr)
1557                 return;
1558
1559         /*
1560          * Force kernel_gs_base reloading before EFER changes, as control
1561          * of this msr depends on is_long_mode().
1562          */
1563         vmx_load_host_state(to_vmx(vcpu));
1564         vcpu->arch.shadow_efer = efer;
1565         if (!msr)
1566                 return;
1567         if (efer & EFER_LMA) {
1568                 vmcs_write32(VM_ENTRY_CONTROLS,
1569                              vmcs_read32(VM_ENTRY_CONTROLS) |
1570                              VM_ENTRY_IA32E_MODE);
1571                 msr->data = efer;
1572         } else {
1573                 vmcs_write32(VM_ENTRY_CONTROLS,
1574                              vmcs_read32(VM_ENTRY_CONTROLS) &
1575                              ~VM_ENTRY_IA32E_MODE);
1576
1577                 msr->data = efer & ~EFER_LME;
1578         }
1579         setup_msrs(vmx);
1580 }
1581
1582 #ifdef CONFIG_X86_64
1583
1584 static void enter_lmode(struct kvm_vcpu *vcpu)
1585 {
1586         u32 guest_tr_ar;
1587
1588         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1589         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1590                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1591                        __func__);
1592                 vmcs_write32(GUEST_TR_AR_BYTES,
1593                              (guest_tr_ar & ~AR_TYPE_MASK)
1594                              | AR_TYPE_BUSY_64_TSS);
1595         }
1596         vcpu->arch.shadow_efer |= EFER_LMA;
1597         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1598 }
1599
1600 static void exit_lmode(struct kvm_vcpu *vcpu)
1601 {
1602         vcpu->arch.shadow_efer &= ~EFER_LMA;
1603
1604         vmcs_write32(VM_ENTRY_CONTROLS,
1605                      vmcs_read32(VM_ENTRY_CONTROLS)
1606                      & ~VM_ENTRY_IA32E_MODE);
1607 }
1608
1609 #endif
1610
1611 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1612 {
1613         vpid_sync_vcpu_all(to_vmx(vcpu));
1614         if (enable_ept)
1615                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1616 }
1617
1618 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1619 {
1620         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1621
1622         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1623         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1624 }
1625
1626 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1627 {
1628         if (!test_bit(VCPU_EXREG_PDPTR,
1629                       (unsigned long *)&vcpu->arch.regs_dirty))
1630                 return;
1631
1632         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1633                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1634                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1635                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1636                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1637         }
1638 }
1639
1640 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1641 {
1642         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1643                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1644                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1645                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1646                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1647         }
1648
1649         __set_bit(VCPU_EXREG_PDPTR,
1650                   (unsigned long *)&vcpu->arch.regs_avail);
1651         __set_bit(VCPU_EXREG_PDPTR,
1652                   (unsigned long *)&vcpu->arch.regs_dirty);
1653 }
1654
1655 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1656
1657 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1658                                         unsigned long cr0,
1659                                         struct kvm_vcpu *vcpu)
1660 {
1661         if (!(cr0 & X86_CR0_PG)) {
1662                 /* From paging/starting to nonpaging */
1663                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1664                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1665                              (CPU_BASED_CR3_LOAD_EXITING |
1666                               CPU_BASED_CR3_STORE_EXITING));
1667                 vcpu->arch.cr0 = cr0;
1668                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1669         } else if (!is_paging(vcpu)) {
1670                 /* From nonpaging to paging */
1671                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1672                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1673                              ~(CPU_BASED_CR3_LOAD_EXITING |
1674                                CPU_BASED_CR3_STORE_EXITING));
1675                 vcpu->arch.cr0 = cr0;
1676                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1677         }
1678
1679         if (!(cr0 & X86_CR0_WP))
1680                 *hw_cr0 &= ~X86_CR0_WP;
1681 }
1682
1683 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1684                                         struct kvm_vcpu *vcpu)
1685 {
1686         if (!is_paging(vcpu)) {
1687                 *hw_cr4 &= ~X86_CR4_PAE;
1688                 *hw_cr4 |= X86_CR4_PSE;
1689         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1690                 *hw_cr4 &= ~X86_CR4_PAE;
1691 }
1692
1693 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1694 {
1695         struct vcpu_vmx *vmx = to_vmx(vcpu);
1696         unsigned long hw_cr0;
1697
1698         if (enable_unrestricted_guest)
1699                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1700                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1701         else
1702                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1703
1704         vmx_fpu_deactivate(vcpu);
1705
1706         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1707                 enter_pmode(vcpu);
1708
1709         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1710                 enter_rmode(vcpu);
1711
1712 #ifdef CONFIG_X86_64
1713         if (vcpu->arch.shadow_efer & EFER_LME) {
1714                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1715                         enter_lmode(vcpu);
1716                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1717                         exit_lmode(vcpu);
1718         }
1719 #endif
1720
1721         if (enable_ept)
1722                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1723
1724         vmcs_writel(CR0_READ_SHADOW, cr0);
1725         vmcs_writel(GUEST_CR0, hw_cr0);
1726         vcpu->arch.cr0 = cr0;
1727
1728         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1729                 vmx_fpu_activate(vcpu);
1730 }
1731
1732 static u64 construct_eptp(unsigned long root_hpa)
1733 {
1734         u64 eptp;
1735
1736         /* TODO write the value reading from MSR */
1737         eptp = VMX_EPT_DEFAULT_MT |
1738                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1739         eptp |= (root_hpa & PAGE_MASK);
1740
1741         return eptp;
1742 }
1743
1744 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1745 {
1746         unsigned long guest_cr3;
1747         u64 eptp;
1748
1749         guest_cr3 = cr3;
1750         if (enable_ept) {
1751                 eptp = construct_eptp(cr3);
1752                 vmcs_write64(EPT_POINTER, eptp);
1753                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1754                         vcpu->kvm->arch.ept_identity_map_addr;
1755                 ept_load_pdptrs(vcpu);
1756         }
1757
1758         vmx_flush_tlb(vcpu);
1759         vmcs_writel(GUEST_CR3, guest_cr3);
1760         if (vcpu->arch.cr0 & X86_CR0_PE)
1761                 vmx_fpu_deactivate(vcpu);
1762 }
1763
1764 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1765 {
1766         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1767                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1768
1769         vcpu->arch.cr4 = cr4;
1770         if (enable_ept)
1771                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1772
1773         vmcs_writel(CR4_READ_SHADOW, cr4);
1774         vmcs_writel(GUEST_CR4, hw_cr4);
1775 }
1776
1777 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1778 {
1779         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1780
1781         return vmcs_readl(sf->base);
1782 }
1783
1784 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1785                             struct kvm_segment *var, int seg)
1786 {
1787         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1788         u32 ar;
1789
1790         var->base = vmcs_readl(sf->base);
1791         var->limit = vmcs_read32(sf->limit);
1792         var->selector = vmcs_read16(sf->selector);
1793         ar = vmcs_read32(sf->ar_bytes);
1794         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1795                 ar = 0;
1796         var->type = ar & 15;
1797         var->s = (ar >> 4) & 1;
1798         var->dpl = (ar >> 5) & 3;
1799         var->present = (ar >> 7) & 1;
1800         var->avl = (ar >> 12) & 1;
1801         var->l = (ar >> 13) & 1;
1802         var->db = (ar >> 14) & 1;
1803         var->g = (ar >> 15) & 1;
1804         var->unusable = (ar >> 16) & 1;
1805 }
1806
1807 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1808 {
1809         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1810                 return 0;
1811
1812         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1813                 return 3;
1814
1815         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1816 }
1817
1818 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1819 {
1820         u32 ar;
1821
1822         if (var->unusable)
1823                 ar = 1 << 16;
1824         else {
1825                 ar = var->type & 15;
1826                 ar |= (var->s & 1) << 4;
1827                 ar |= (var->dpl & 3) << 5;
1828                 ar |= (var->present & 1) << 7;
1829                 ar |= (var->avl & 1) << 12;
1830                 ar |= (var->l & 1) << 13;
1831                 ar |= (var->db & 1) << 14;
1832                 ar |= (var->g & 1) << 15;
1833         }
1834         if (ar == 0) /* a 0 value means unusable */
1835                 ar = AR_UNUSABLE_MASK;
1836
1837         return ar;
1838 }
1839
1840 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1841                             struct kvm_segment *var, int seg)
1842 {
1843         struct vcpu_vmx *vmx = to_vmx(vcpu);
1844         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1845         u32 ar;
1846
1847         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1848                 vmx->rmode.tr.selector = var->selector;
1849                 vmx->rmode.tr.base = var->base;
1850                 vmx->rmode.tr.limit = var->limit;
1851                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1852                 return;
1853         }
1854         vmcs_writel(sf->base, var->base);
1855         vmcs_write32(sf->limit, var->limit);
1856         vmcs_write16(sf->selector, var->selector);
1857         if (vmx->rmode.vm86_active && var->s) {
1858                 /*
1859                  * Hack real-mode segments into vm86 compatibility.
1860                  */
1861                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1862                         vmcs_writel(sf->base, 0xf0000);
1863                 ar = 0xf3;
1864         } else
1865                 ar = vmx_segment_access_rights(var);
1866
1867         /*
1868          *   Fix the "Accessed" bit in AR field of segment registers for older
1869          * qemu binaries.
1870          *   IA32 arch specifies that at the time of processor reset the
1871          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1872          * is setting it to 0 in the usedland code. This causes invalid guest
1873          * state vmexit when "unrestricted guest" mode is turned on.
1874          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1875          * tree. Newer qemu binaries with that qemu fix would not need this
1876          * kvm hack.
1877          */
1878         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1879                 ar |= 0x1; /* Accessed */
1880
1881         vmcs_write32(sf->ar_bytes, ar);
1882 }
1883
1884 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1885 {
1886         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1887
1888         *db = (ar >> 14) & 1;
1889         *l = (ar >> 13) & 1;
1890 }
1891
1892 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1893 {
1894         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1895         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1896 }
1897
1898 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1899 {
1900         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1901         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1902 }
1903
1904 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1905 {
1906         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1907         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1908 }
1909
1910 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1911 {
1912         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1913         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1914 }
1915
1916 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1917 {
1918         struct kvm_segment var;
1919         u32 ar;
1920
1921         vmx_get_segment(vcpu, &var, seg);
1922         ar = vmx_segment_access_rights(&var);
1923
1924         if (var.base != (var.selector << 4))
1925                 return false;
1926         if (var.limit != 0xffff)
1927                 return false;
1928         if (ar != 0xf3)
1929                 return false;
1930
1931         return true;
1932 }
1933
1934 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1935 {
1936         struct kvm_segment cs;
1937         unsigned int cs_rpl;
1938
1939         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1940         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1941
1942         if (cs.unusable)
1943                 return false;
1944         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1945                 return false;
1946         if (!cs.s)
1947                 return false;
1948         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1949                 if (cs.dpl > cs_rpl)
1950                         return false;
1951         } else {
1952                 if (cs.dpl != cs_rpl)
1953                         return false;
1954         }
1955         if (!cs.present)
1956                 return false;
1957
1958         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1959         return true;
1960 }
1961
1962 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1963 {
1964         struct kvm_segment ss;
1965         unsigned int ss_rpl;
1966
1967         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1968         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1969
1970         if (ss.unusable)
1971                 return true;
1972         if (ss.type != 3 && ss.type != 7)
1973                 return false;
1974         if (!ss.s)
1975                 return false;
1976         if (ss.dpl != ss_rpl) /* DPL != RPL */
1977                 return false;
1978         if (!ss.present)
1979                 return false;
1980
1981         return true;
1982 }
1983
1984 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1985 {
1986         struct kvm_segment var;
1987         unsigned int rpl;
1988
1989         vmx_get_segment(vcpu, &var, seg);
1990         rpl = var.selector & SELECTOR_RPL_MASK;
1991
1992         if (var.unusable)
1993                 return true;
1994         if (!var.s)
1995                 return false;
1996         if (!var.present)
1997                 return false;
1998         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1999                 if (var.dpl < rpl) /* DPL < RPL */
2000                         return false;
2001         }
2002
2003         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2004          * rights flags
2005          */
2006         return true;
2007 }
2008
2009 static bool tr_valid(struct kvm_vcpu *vcpu)
2010 {
2011         struct kvm_segment tr;
2012
2013         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2014
2015         if (tr.unusable)
2016                 return false;
2017         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2018                 return false;
2019         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2020                 return false;
2021         if (!tr.present)
2022                 return false;
2023
2024         return true;
2025 }
2026
2027 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2028 {
2029         struct kvm_segment ldtr;
2030
2031         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2032
2033         if (ldtr.unusable)
2034                 return true;
2035         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2036                 return false;
2037         if (ldtr.type != 2)
2038                 return false;
2039         if (!ldtr.present)
2040                 return false;
2041
2042         return true;
2043 }
2044
2045 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2046 {
2047         struct kvm_segment cs, ss;
2048
2049         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2050         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2051
2052         return ((cs.selector & SELECTOR_RPL_MASK) ==
2053                  (ss.selector & SELECTOR_RPL_MASK));
2054 }
2055
2056 /*
2057  * Check if guest state is valid. Returns true if valid, false if
2058  * not.
2059  * We assume that registers are always usable
2060  */
2061 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2062 {
2063         /* real mode guest state checks */
2064         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2065                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2066                         return false;
2067                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2068                         return false;
2069                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2070                         return false;
2071                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2072                         return false;
2073                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2074                         return false;
2075                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2076                         return false;
2077         } else {
2078         /* protected mode guest state checks */
2079                 if (!cs_ss_rpl_check(vcpu))
2080                         return false;
2081                 if (!code_segment_valid(vcpu))
2082                         return false;
2083                 if (!stack_segment_valid(vcpu))
2084                         return false;
2085                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2086                         return false;
2087                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2088                         return false;
2089                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2090                         return false;
2091                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2092                         return false;
2093                 if (!tr_valid(vcpu))
2094                         return false;
2095                 if (!ldtr_valid(vcpu))
2096                         return false;
2097         }
2098         /* TODO:
2099          * - Add checks on RIP
2100          * - Add checks on RFLAGS
2101          */
2102
2103         return true;
2104 }
2105
2106 static int init_rmode_tss(struct kvm *kvm)
2107 {
2108         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2109         u16 data = 0;
2110         int ret = 0;
2111         int r;
2112
2113         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2114         if (r < 0)
2115                 goto out;
2116         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2117         r = kvm_write_guest_page(kvm, fn++, &data,
2118                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2119         if (r < 0)
2120                 goto out;
2121         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2122         if (r < 0)
2123                 goto out;
2124         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2125         if (r < 0)
2126                 goto out;
2127         data = ~0;
2128         r = kvm_write_guest_page(kvm, fn, &data,
2129                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2130                                  sizeof(u8));
2131         if (r < 0)
2132                 goto out;
2133
2134         ret = 1;
2135 out:
2136         return ret;
2137 }
2138
2139 static int init_rmode_identity_map(struct kvm *kvm)
2140 {
2141         int i, r, ret;
2142         pfn_t identity_map_pfn;
2143         u32 tmp;
2144
2145         if (!enable_ept)
2146                 return 1;
2147         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2148                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2149                         "haven't been allocated!\n");
2150                 return 0;
2151         }
2152         if (likely(kvm->arch.ept_identity_pagetable_done))
2153                 return 1;
2154         ret = 0;
2155         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2156         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2157         if (r < 0)
2158                 goto out;
2159         /* Set up identity-mapping pagetable for EPT in real mode */
2160         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2161                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2162                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2163                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2164                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2165                 if (r < 0)
2166                         goto out;
2167         }
2168         kvm->arch.ept_identity_pagetable_done = true;
2169         ret = 1;
2170 out:
2171         return ret;
2172 }
2173
2174 static void seg_setup(int seg)
2175 {
2176         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2177         unsigned int ar;
2178
2179         vmcs_write16(sf->selector, 0);
2180         vmcs_writel(sf->base, 0);
2181         vmcs_write32(sf->limit, 0xffff);
2182         if (enable_unrestricted_guest) {
2183                 ar = 0x93;
2184                 if (seg == VCPU_SREG_CS)
2185                         ar |= 0x08; /* code segment */
2186         } else
2187                 ar = 0xf3;
2188
2189         vmcs_write32(sf->ar_bytes, ar);
2190 }
2191
2192 static int alloc_apic_access_page(struct kvm *kvm)
2193 {
2194         struct kvm_userspace_memory_region kvm_userspace_mem;
2195         int r = 0;
2196
2197         down_write(&kvm->slots_lock);
2198         if (kvm->arch.apic_access_page)
2199                 goto out;
2200         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2201         kvm_userspace_mem.flags = 0;
2202         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2203         kvm_userspace_mem.memory_size = PAGE_SIZE;
2204         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2205         if (r)
2206                 goto out;
2207
2208         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2209 out:
2210         up_write(&kvm->slots_lock);
2211         return r;
2212 }
2213
2214 static int alloc_identity_pagetable(struct kvm *kvm)
2215 {
2216         struct kvm_userspace_memory_region kvm_userspace_mem;
2217         int r = 0;
2218
2219         down_write(&kvm->slots_lock);
2220         if (kvm->arch.ept_identity_pagetable)
2221                 goto out;
2222         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2223         kvm_userspace_mem.flags = 0;
2224         kvm_userspace_mem.guest_phys_addr =
2225                 kvm->arch.ept_identity_map_addr;
2226         kvm_userspace_mem.memory_size = PAGE_SIZE;
2227         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2228         if (r)
2229                 goto out;
2230
2231         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2232                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2233 out:
2234         up_write(&kvm->slots_lock);
2235         return r;
2236 }
2237
2238 static void allocate_vpid(struct vcpu_vmx *vmx)
2239 {
2240         int vpid;
2241
2242         vmx->vpid = 0;
2243         if (!enable_vpid)
2244                 return;
2245         spin_lock(&vmx_vpid_lock);
2246         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2247         if (vpid < VMX_NR_VPIDS) {
2248                 vmx->vpid = vpid;
2249                 __set_bit(vpid, vmx_vpid_bitmap);
2250         }
2251         spin_unlock(&vmx_vpid_lock);
2252 }
2253
2254 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2255 {
2256         int f = sizeof(unsigned long);
2257
2258         if (!cpu_has_vmx_msr_bitmap())
2259                 return;
2260
2261         /*
2262          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2263          * have the write-low and read-high bitmap offsets the wrong way round.
2264          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2265          */
2266         if (msr <= 0x1fff) {
2267                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2268                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2269         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2270                 msr &= 0x1fff;
2271                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2272                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2273         }
2274 }
2275
2276 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2277 {
2278         if (!longmode_only)
2279                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2280         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2281 }
2282
2283 /*
2284  * Sets up the vmcs for emulated real mode.
2285  */
2286 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2287 {
2288         u32 host_sysenter_cs, msr_low, msr_high;
2289         u32 junk;
2290         u64 host_pat, tsc_this, tsc_base;
2291         unsigned long a;
2292         struct descriptor_table dt;
2293         int i;
2294         unsigned long kvm_vmx_return;
2295         u32 exec_control;
2296
2297         /* I/O */
2298         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2299         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2300
2301         if (cpu_has_vmx_msr_bitmap())
2302                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2303
2304         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2305
2306         /* Control */
2307         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2308                 vmcs_config.pin_based_exec_ctrl);
2309
2310         exec_control = vmcs_config.cpu_based_exec_ctrl;
2311         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2312                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2313 #ifdef CONFIG_X86_64
2314                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2315                                 CPU_BASED_CR8_LOAD_EXITING;
2316 #endif
2317         }
2318         if (!enable_ept)
2319                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2320                                 CPU_BASED_CR3_LOAD_EXITING  |
2321                                 CPU_BASED_INVLPG_EXITING;
2322         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2323
2324         if (cpu_has_secondary_exec_ctrls()) {
2325                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2326                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2327                         exec_control &=
2328                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2329                 if (vmx->vpid == 0)
2330                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2331                 if (!enable_ept) {
2332                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2333                         enable_unrestricted_guest = 0;
2334                 }
2335                 if (!enable_unrestricted_guest)
2336                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2337                 if (!ple_gap)
2338                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2339                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2340         }
2341
2342         if (ple_gap) {
2343                 vmcs_write32(PLE_GAP, ple_gap);
2344                 vmcs_write32(PLE_WINDOW, ple_window);
2345         }
2346
2347         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2348         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2349         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2350
2351         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2352         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2353         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2354
2355         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2356         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2357         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2358         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2359         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2360         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2361 #ifdef CONFIG_X86_64
2362         rdmsrl(MSR_FS_BASE, a);
2363         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2364         rdmsrl(MSR_GS_BASE, a);
2365         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2366 #else
2367         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2368         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2369 #endif
2370
2371         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2372
2373         kvm_get_idt(&dt);
2374         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2375
2376         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2377         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2378         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2379         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2380         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2381
2382         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2383         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2384         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2385         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2386         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2387         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2388
2389         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2390                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2391                 host_pat = msr_low | ((u64) msr_high << 32);
2392                 vmcs_write64(HOST_IA32_PAT, host_pat);
2393         }
2394         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2395                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2396                 host_pat = msr_low | ((u64) msr_high << 32);
2397                 /* Write the default value follow host pat */
2398                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2399                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2400                 vmx->vcpu.arch.pat = host_pat;
2401         }
2402
2403         for (i = 0; i < NR_VMX_MSR; ++i) {
2404                 u32 index = vmx_msr_index[i];
2405                 u32 data_low, data_high;
2406                 u64 data;
2407                 int j = vmx->nmsrs;
2408
2409                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2410                         continue;
2411                 if (wrmsr_safe(index, data_low, data_high) < 0)
2412                         continue;
2413                 data = data_low | ((u64)data_high << 32);
2414                 vmx->guest_msrs[j].index = i;
2415                 vmx->guest_msrs[j].data = 0;
2416                 vmx->guest_msrs[j].mask = -1ull;
2417                 ++vmx->nmsrs;
2418         }
2419
2420         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2421
2422         /* 22.2.1, 20.8.1 */
2423         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2424
2425         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2426         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2427         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2428
2429         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2430         rdtscll(tsc_this);
2431         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2432                 tsc_base = tsc_this;
2433
2434         guest_write_tsc(0, tsc_base);
2435
2436         return 0;
2437 }
2438
2439 static int init_rmode(struct kvm *kvm)
2440 {
2441         if (!init_rmode_tss(kvm))
2442                 return 0;
2443         if (!init_rmode_identity_map(kvm))
2444                 return 0;
2445         return 1;
2446 }
2447
2448 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2449 {
2450         struct vcpu_vmx *vmx = to_vmx(vcpu);
2451         u64 msr;
2452         int ret;
2453
2454         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2455         down_read(&vcpu->kvm->slots_lock);
2456         if (!init_rmode(vmx->vcpu.kvm)) {
2457                 ret = -ENOMEM;
2458                 goto out;
2459         }
2460
2461         vmx->rmode.vm86_active = 0;
2462
2463         vmx->soft_vnmi_blocked = 0;
2464
2465         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2466         kvm_set_cr8(&vmx->vcpu, 0);
2467         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2468         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2469                 msr |= MSR_IA32_APICBASE_BSP;
2470         kvm_set_apic_base(&vmx->vcpu, msr);
2471
2472         fx_init(&vmx->vcpu);
2473
2474         seg_setup(VCPU_SREG_CS);
2475         /*
2476          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2477          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2478          */
2479         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2480                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2481                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2482         } else {
2483                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2484                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2485         }
2486
2487         seg_setup(VCPU_SREG_DS);
2488         seg_setup(VCPU_SREG_ES);
2489         seg_setup(VCPU_SREG_FS);
2490         seg_setup(VCPU_SREG_GS);
2491         seg_setup(VCPU_SREG_SS);
2492
2493         vmcs_write16(GUEST_TR_SELECTOR, 0);
2494         vmcs_writel(GUEST_TR_BASE, 0);
2495         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2496         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2497
2498         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2499         vmcs_writel(GUEST_LDTR_BASE, 0);
2500         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2501         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2502
2503         vmcs_write32(GUEST_SYSENTER_CS, 0);
2504         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2505         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2506
2507         vmcs_writel(GUEST_RFLAGS, 0x02);
2508         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2509                 kvm_rip_write(vcpu, 0xfff0);
2510         else
2511                 kvm_rip_write(vcpu, 0);
2512         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2513
2514         vmcs_writel(GUEST_DR7, 0x400);
2515
2516         vmcs_writel(GUEST_GDTR_BASE, 0);
2517         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2518
2519         vmcs_writel(GUEST_IDTR_BASE, 0);
2520         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2521
2522         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2523         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2524         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2525
2526         /* Special registers */
2527         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2528
2529         setup_msrs(vmx);
2530
2531         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2532
2533         if (cpu_has_vmx_tpr_shadow()) {
2534                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2535                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2536                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2537                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2538                 vmcs_write32(TPR_THRESHOLD, 0);
2539         }
2540
2541         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2542                 vmcs_write64(APIC_ACCESS_ADDR,
2543                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2544
2545         if (vmx->vpid != 0)
2546                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2547
2548         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2549         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2550         vmx_set_cr4(&vmx->vcpu, 0);
2551         vmx_set_efer(&vmx->vcpu, 0);
2552         vmx_fpu_activate(&vmx->vcpu);
2553         update_exception_bitmap(&vmx->vcpu);
2554
2555         vpid_sync_vcpu_all(vmx);
2556
2557         ret = 0;
2558
2559         /* HACK: Don't enable emulation on guest boot/reset */
2560         vmx->emulation_required = 0;
2561
2562 out:
2563         up_read(&vcpu->kvm->slots_lock);
2564         return ret;
2565 }
2566
2567 static void enable_irq_window(struct kvm_vcpu *vcpu)
2568 {
2569         u32 cpu_based_vm_exec_control;
2570
2571         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2572         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2573         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2574 }
2575
2576 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2577 {
2578         u32 cpu_based_vm_exec_control;
2579
2580         if (!cpu_has_virtual_nmis()) {
2581                 enable_irq_window(vcpu);
2582                 return;
2583         }
2584
2585         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2586         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2587         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2588 }
2589
2590 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2591 {
2592         struct vcpu_vmx *vmx = to_vmx(vcpu);
2593         uint32_t intr;
2594         int irq = vcpu->arch.interrupt.nr;
2595
2596         trace_kvm_inj_virq(irq);
2597
2598         ++vcpu->stat.irq_injections;
2599         if (vmx->rmode.vm86_active) {
2600                 vmx->rmode.irq.pending = true;
2601                 vmx->rmode.irq.vector = irq;
2602                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2603                 if (vcpu->arch.interrupt.soft)
2604                         vmx->rmode.irq.rip +=
2605                                 vmx->vcpu.arch.event_exit_inst_len;
2606                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2607                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2608                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2609                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2610                 return;
2611         }
2612         intr = irq | INTR_INFO_VALID_MASK;
2613         if (vcpu->arch.interrupt.soft) {
2614                 intr |= INTR_TYPE_SOFT_INTR;
2615                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2616                              vmx->vcpu.arch.event_exit_inst_len);
2617         } else
2618                 intr |= INTR_TYPE_EXT_INTR;
2619         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2620 }
2621
2622 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2623 {
2624         struct vcpu_vmx *vmx = to_vmx(vcpu);
2625
2626         if (!cpu_has_virtual_nmis()) {
2627                 /*
2628                  * Tracking the NMI-blocked state in software is built upon
2629                  * finding the next open IRQ window. This, in turn, depends on
2630                  * well-behaving guests: They have to keep IRQs disabled at
2631                  * least as long as the NMI handler runs. Otherwise we may
2632                  * cause NMI nesting, maybe breaking the guest. But as this is
2633                  * highly unlikely, we can live with the residual risk.
2634                  */
2635                 vmx->soft_vnmi_blocked = 1;
2636                 vmx->vnmi_blocked_time = 0;
2637         }
2638
2639         ++vcpu->stat.nmi_injections;
2640         if (vmx->rmode.vm86_active) {
2641                 vmx->rmode.irq.pending = true;
2642                 vmx->rmode.irq.vector = NMI_VECTOR;
2643                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2644                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2645                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2646                              INTR_INFO_VALID_MASK);
2647                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2648                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2649                 return;
2650         }
2651         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2652                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2653 }
2654
2655 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2656 {
2657         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2658                 return 0;
2659
2660         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2661                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2662                                 GUEST_INTR_STATE_NMI));
2663 }
2664
2665 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2666 {
2667         if (!cpu_has_virtual_nmis())
2668                 return to_vmx(vcpu)->soft_vnmi_blocked;
2669         else
2670                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2671                           GUEST_INTR_STATE_NMI);
2672 }
2673
2674 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2675 {
2676         struct vcpu_vmx *vmx = to_vmx(vcpu);
2677
2678         if (!cpu_has_virtual_nmis()) {
2679                 if (vmx->soft_vnmi_blocked != masked) {
2680                         vmx->soft_vnmi_blocked = masked;
2681                         vmx->vnmi_blocked_time = 0;
2682                 }
2683         } else {
2684                 if (masked)
2685                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2686                                       GUEST_INTR_STATE_NMI);
2687                 else
2688                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2689                                         GUEST_INTR_STATE_NMI);
2690         }
2691 }
2692
2693 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2694 {
2695         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2696                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2697                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2698 }
2699
2700 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2701 {
2702         int ret;
2703         struct kvm_userspace_memory_region tss_mem = {
2704                 .slot = TSS_PRIVATE_MEMSLOT,
2705                 .guest_phys_addr = addr,
2706                 .memory_size = PAGE_SIZE * 3,
2707                 .flags = 0,
2708         };
2709
2710         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2711         if (ret)
2712                 return ret;
2713         kvm->arch.tss_addr = addr;
2714         return 0;
2715 }
2716
2717 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2718                                   int vec, u32 err_code)
2719 {
2720         /*
2721          * Instruction with address size override prefix opcode 0x67
2722          * Cause the #SS fault with 0 error code in VM86 mode.
2723          */
2724         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2725                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2726                         return 1;
2727         /*
2728          * Forward all other exceptions that are valid in real mode.
2729          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2730          *        the required debugging infrastructure rework.
2731          */
2732         switch (vec) {
2733         case DB_VECTOR:
2734                 if (vcpu->guest_debug &
2735                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2736                         return 0;
2737                 kvm_queue_exception(vcpu, vec);
2738                 return 1;
2739         case BP_VECTOR:
2740                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2741                         return 0;
2742                 /* fall through */
2743         case DE_VECTOR:
2744         case OF_VECTOR:
2745         case BR_VECTOR:
2746         case UD_VECTOR:
2747         case DF_VECTOR:
2748         case SS_VECTOR:
2749         case GP_VECTOR:
2750         case MF_VECTOR:
2751                 kvm_queue_exception(vcpu, vec);
2752                 return 1;
2753         }
2754         return 0;
2755 }
2756
2757 /*
2758  * Trigger machine check on the host. We assume all the MSRs are already set up
2759  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2760  * We pass a fake environment to the machine check handler because we want
2761  * the guest to be always treated like user space, no matter what context
2762  * it used internally.
2763  */
2764 static void kvm_machine_check(void)
2765 {
2766 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2767         struct pt_regs regs = {
2768                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2769                 .flags = X86_EFLAGS_IF,
2770         };
2771
2772         do_machine_check(&regs, 0);
2773 #endif
2774 }
2775
2776 static int handle_machine_check(struct kvm_vcpu *vcpu)
2777 {
2778         /* already handled by vcpu_run */
2779         return 1;
2780 }
2781
2782 static int handle_exception(struct kvm_vcpu *vcpu)
2783 {
2784         struct vcpu_vmx *vmx = to_vmx(vcpu);
2785         struct kvm_run *kvm_run = vcpu->run;
2786         u32 intr_info, ex_no, error_code;
2787         unsigned long cr2, rip, dr6;
2788         u32 vect_info;
2789         enum emulation_result er;
2790
2791         vect_info = vmx->idt_vectoring_info;
2792         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2793
2794         if (is_machine_check(intr_info))
2795                 return handle_machine_check(vcpu);
2796
2797         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2798             !is_page_fault(intr_info)) {
2799                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2800                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2801                 vcpu->run->internal.ndata = 2;
2802                 vcpu->run->internal.data[0] = vect_info;
2803                 vcpu->run->internal.data[1] = intr_info;
2804                 return 0;
2805         }
2806
2807         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2808                 return 1;  /* already handled by vmx_vcpu_run() */
2809
2810         if (is_no_device(intr_info)) {
2811                 vmx_fpu_activate(vcpu);
2812                 return 1;
2813         }
2814
2815         if (is_invalid_opcode(intr_info)) {
2816                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2817                 if (er != EMULATE_DONE)
2818                         kvm_queue_exception(vcpu, UD_VECTOR);
2819                 return 1;
2820         }
2821
2822         error_code = 0;
2823         rip = kvm_rip_read(vcpu);
2824         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2825                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2826         if (is_page_fault(intr_info)) {
2827                 /* EPT won't cause page fault directly */
2828                 if (enable_ept)
2829                         BUG();
2830                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2831                 trace_kvm_page_fault(cr2, error_code);
2832
2833                 if (kvm_event_needs_reinjection(vcpu))
2834                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2835                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2836         }
2837
2838         if (vmx->rmode.vm86_active &&
2839             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2840                                                                 error_code)) {
2841                 if (vcpu->arch.halt_request) {
2842                         vcpu->arch.halt_request = 0;
2843                         return kvm_emulate_halt(vcpu);
2844                 }
2845                 return 1;
2846         }
2847
2848         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2849         switch (ex_no) {
2850         case DB_VECTOR:
2851                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2852                 if (!(vcpu->guest_debug &
2853                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2854                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2855                         kvm_queue_exception(vcpu, DB_VECTOR);
2856                         return 1;
2857                 }
2858                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2859                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2860                 /* fall through */
2861         case BP_VECTOR:
2862                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2863                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2864                 kvm_run->debug.arch.exception = ex_no;
2865                 break;
2866         default:
2867                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2868                 kvm_run->ex.exception = ex_no;
2869                 kvm_run->ex.error_code = error_code;
2870                 break;
2871         }
2872         return 0;
2873 }
2874
2875 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2876 {
2877         ++vcpu->stat.irq_exits;
2878         return 1;
2879 }
2880
2881 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2882 {
2883         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2884         return 0;
2885 }
2886
2887 static int handle_io(struct kvm_vcpu *vcpu)
2888 {
2889         unsigned long exit_qualification;
2890         int size, in, string;
2891         unsigned port;
2892
2893         ++vcpu->stat.io_exits;
2894         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2895         string = (exit_qualification & 16) != 0;
2896
2897         if (string) {
2898                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2899                         return 0;
2900                 return 1;
2901         }
2902
2903         size = (exit_qualification & 7) + 1;
2904         in = (exit_qualification & 8) != 0;
2905         port = exit_qualification >> 16;
2906
2907         skip_emulated_instruction(vcpu);
2908         return kvm_emulate_pio(vcpu, in, size, port);
2909 }
2910
2911 static void
2912 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2913 {
2914         /*
2915          * Patch in the VMCALL instruction:
2916          */
2917         hypercall[0] = 0x0f;
2918         hypercall[1] = 0x01;
2919         hypercall[2] = 0xc1;
2920 }
2921
2922 static int handle_cr(struct kvm_vcpu *vcpu)
2923 {
2924         unsigned long exit_qualification, val;
2925         int cr;
2926         int reg;
2927
2928         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2929         cr = exit_qualification & 15;
2930         reg = (exit_qualification >> 8) & 15;
2931         switch ((exit_qualification >> 4) & 3) {
2932         case 0: /* mov to cr */
2933                 val = kvm_register_read(vcpu, reg);
2934                 trace_kvm_cr_write(cr, val);
2935                 switch (cr) {
2936                 case 0:
2937                         kvm_set_cr0(vcpu, val);
2938                         skip_emulated_instruction(vcpu);
2939                         return 1;
2940                 case 3:
2941                         kvm_set_cr3(vcpu, val);
2942                         skip_emulated_instruction(vcpu);
2943                         return 1;
2944                 case 4:
2945                         kvm_set_cr4(vcpu, val);
2946                         skip_emulated_instruction(vcpu);
2947                         return 1;
2948                 case 8: {
2949                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2950                                 u8 cr8 = kvm_register_read(vcpu, reg);
2951                                 kvm_set_cr8(vcpu, cr8);
2952                                 skip_emulated_instruction(vcpu);
2953                                 if (irqchip_in_kernel(vcpu->kvm))
2954                                         return 1;
2955                                 if (cr8_prev <= cr8)
2956                                         return 1;
2957                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2958                                 return 0;
2959                         }
2960                 };
2961                 break;
2962         case 2: /* clts */
2963                 vmx_fpu_deactivate(vcpu);
2964                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2965                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2966                 vmx_fpu_activate(vcpu);
2967                 skip_emulated_instruction(vcpu);
2968                 return 1;
2969         case 1: /*mov from cr*/
2970                 switch (cr) {
2971                 case 3:
2972                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2973                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2974                         skip_emulated_instruction(vcpu);
2975                         return 1;
2976                 case 8:
2977                         val = kvm_get_cr8(vcpu);
2978                         kvm_register_write(vcpu, reg, val);
2979                         trace_kvm_cr_read(cr, val);
2980                         skip_emulated_instruction(vcpu);
2981                         return 1;
2982                 }
2983                 break;
2984         case 3: /* lmsw */
2985                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2986
2987                 skip_emulated_instruction(vcpu);
2988                 return 1;
2989         default:
2990                 break;
2991         }
2992         vcpu->run->exit_reason = 0;
2993         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2994                (int)(exit_qualification >> 4) & 3, cr);
2995         return 0;
2996 }
2997
2998 static int handle_dr(struct kvm_vcpu *vcpu)
2999 {
3000         unsigned long exit_qualification;
3001         unsigned long val;
3002         int dr, reg;
3003
3004         if (!kvm_require_cpl(vcpu, 0))
3005                 return 1;
3006         dr = vmcs_readl(GUEST_DR7);
3007         if (dr & DR7_GD) {
3008                 /*
3009                  * As the vm-exit takes precedence over the debug trap, we
3010                  * need to emulate the latter, either for the host or the
3011                  * guest debugging itself.
3012                  */
3013                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3014                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3015                         vcpu->run->debug.arch.dr7 = dr;
3016                         vcpu->run->debug.arch.pc =
3017                                 vmcs_readl(GUEST_CS_BASE) +
3018                                 vmcs_readl(GUEST_RIP);
3019                         vcpu->run->debug.arch.exception = DB_VECTOR;
3020                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3021                         return 0;
3022                 } else {
3023                         vcpu->arch.dr7 &= ~DR7_GD;
3024                         vcpu->arch.dr6 |= DR6_BD;
3025                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3026                         kvm_queue_exception(vcpu, DB_VECTOR);
3027                         return 1;
3028                 }
3029         }
3030
3031         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3032         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3033         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3034         if (exit_qualification & TYPE_MOV_FROM_DR) {
3035                 switch (dr) {
3036                 case 0 ... 3:
3037                         val = vcpu->arch.db[dr];
3038                         break;
3039                 case 6:
3040                         val = vcpu->arch.dr6;
3041                         break;
3042                 case 7:
3043                         val = vcpu->arch.dr7;
3044                         break;
3045                 default:
3046                         val = 0;
3047                 }
3048                 kvm_register_write(vcpu, reg, val);
3049         } else {
3050                 val = vcpu->arch.regs[reg];
3051                 switch (dr) {
3052                 case 0 ... 3:
3053                         vcpu->arch.db[dr] = val;
3054                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3055                                 vcpu->arch.eff_db[dr] = val;
3056                         break;
3057                 case 4 ... 5:
3058                         if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
3059                                 kvm_queue_exception(vcpu, UD_VECTOR);
3060                         break;
3061                 case 6:
3062                         if (val & 0xffffffff00000000ULL) {
3063                                 kvm_queue_exception(vcpu, GP_VECTOR);
3064                                 break;
3065                         }
3066                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3067                         break;
3068                 case 7:
3069                         if (val & 0xffffffff00000000ULL) {
3070                                 kvm_queue_exception(vcpu, GP_VECTOR);
3071                                 break;
3072                         }
3073                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3074                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3075                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3076                                 vcpu->arch.switch_db_regs =
3077                                         (val & DR7_BP_EN_MASK);
3078                         }
3079                         break;
3080                 }
3081         }
3082         skip_emulated_instruction(vcpu);
3083         return 1;
3084 }
3085
3086 static int handle_cpuid(struct kvm_vcpu *vcpu)
3087 {
3088         kvm_emulate_cpuid(vcpu);
3089         return 1;
3090 }
3091
3092 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3093 {
3094         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3095         u64 data;
3096
3097         if (vmx_get_msr(vcpu, ecx, &data)) {
3098                 kvm_inject_gp(vcpu, 0);
3099                 return 1;
3100         }
3101
3102         trace_kvm_msr_read(ecx, data);
3103
3104         /* FIXME: handling of bits 32:63 of rax, rdx */
3105         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3106         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3107         skip_emulated_instruction(vcpu);
3108         return 1;
3109 }
3110
3111 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3112 {
3113         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3114         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3115                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3116
3117         trace_kvm_msr_write(ecx, data);
3118
3119         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3120                 kvm_inject_gp(vcpu, 0);
3121                 return 1;
3122         }
3123
3124         skip_emulated_instruction(vcpu);
3125         return 1;
3126 }
3127
3128 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3129 {
3130         return 1;
3131 }
3132
3133 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3134 {
3135         u32 cpu_based_vm_exec_control;
3136
3137         /* clear pending irq */
3138         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3139         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3140         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3141
3142         ++vcpu->stat.irq_window_exits;
3143
3144         /*
3145          * If the user space waits to inject interrupts, exit as soon as
3146          * possible
3147          */
3148         if (!irqchip_in_kernel(vcpu->kvm) &&
3149             vcpu->run->request_interrupt_window &&
3150             !kvm_cpu_has_interrupt(vcpu)) {
3151                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3152                 return 0;
3153         }
3154         return 1;
3155 }
3156
3157 static int handle_halt(struct kvm_vcpu *vcpu)
3158 {
3159         skip_emulated_instruction(vcpu);
3160         return kvm_emulate_halt(vcpu);
3161 }
3162
3163 static int handle_vmcall(struct kvm_vcpu *vcpu)
3164 {
3165         skip_emulated_instruction(vcpu);
3166         kvm_emulate_hypercall(vcpu);
3167         return 1;
3168 }
3169
3170 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3171 {
3172         kvm_queue_exception(vcpu, UD_VECTOR);
3173         return 1;
3174 }
3175
3176 static int handle_invlpg(struct kvm_vcpu *vcpu)
3177 {
3178         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3179
3180         kvm_mmu_invlpg(vcpu, exit_qualification);
3181         skip_emulated_instruction(vcpu);
3182         return 1;
3183 }
3184
3185 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3186 {
3187         skip_emulated_instruction(vcpu);
3188         /* TODO: Add support for VT-d/pass-through device */
3189         return 1;
3190 }
3191
3192 static int handle_apic_access(struct kvm_vcpu *vcpu)
3193 {
3194         unsigned long exit_qualification;
3195         enum emulation_result er;
3196         unsigned long offset;
3197
3198         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3199         offset = exit_qualification & 0xffful;
3200
3201         er = emulate_instruction(vcpu, 0, 0, 0);
3202
3203         if (er !=  EMULATE_DONE) {
3204                 printk(KERN_ERR
3205                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3206                        offset);
3207                 return -ENOEXEC;
3208         }
3209         return 1;
3210 }
3211
3212 static int handle_task_switch(struct kvm_vcpu *vcpu)
3213 {
3214         struct vcpu_vmx *vmx = to_vmx(vcpu);
3215         unsigned long exit_qualification;
3216         u16 tss_selector;
3217         int reason, type, idt_v;
3218
3219         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3220         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3221
3222         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3223
3224         reason = (u32)exit_qualification >> 30;
3225         if (reason == TASK_SWITCH_GATE && idt_v) {
3226                 switch (type) {
3227                 case INTR_TYPE_NMI_INTR:
3228                         vcpu->arch.nmi_injected = false;
3229                         if (cpu_has_virtual_nmis())
3230                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3231                                               GUEST_INTR_STATE_NMI);
3232                         break;
3233                 case INTR_TYPE_EXT_INTR:
3234                 case INTR_TYPE_SOFT_INTR:
3235                         kvm_clear_interrupt_queue(vcpu);
3236                         break;
3237                 case INTR_TYPE_HARD_EXCEPTION:
3238                 case INTR_TYPE_SOFT_EXCEPTION:
3239                         kvm_clear_exception_queue(vcpu);
3240                         break;
3241                 default:
3242                         break;
3243                 }
3244         }
3245         tss_selector = exit_qualification;
3246
3247         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3248                        type != INTR_TYPE_EXT_INTR &&
3249                        type != INTR_TYPE_NMI_INTR))
3250                 skip_emulated_instruction(vcpu);
3251
3252         if (!kvm_task_switch(vcpu, tss_selector, reason))
3253                 return 0;
3254
3255         /* clear all local breakpoint enable flags */
3256         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3257
3258         /*
3259          * TODO: What about debug traps on tss switch?
3260          *       Are we supposed to inject them and update dr6?
3261          */
3262
3263         return 1;
3264 }
3265
3266 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3267 {
3268         unsigned long exit_qualification;
3269         gpa_t gpa;
3270         int gla_validity;
3271
3272         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3273
3274         if (exit_qualification & (1 << 6)) {
3275                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3276                 return -EINVAL;
3277         }
3278
3279         gla_validity = (exit_qualification >> 7) & 0x3;
3280         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3281                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3282                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3283                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3284                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3285                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3286                         (long unsigned int)exit_qualification);
3287                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3288                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3289                 return 0;
3290         }
3291
3292         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3293         trace_kvm_page_fault(gpa, exit_qualification);
3294         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3295 }
3296
3297 static u64 ept_rsvd_mask(u64 spte, int level)
3298 {
3299         int i;
3300         u64 mask = 0;
3301
3302         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3303                 mask |= (1ULL << i);
3304
3305         if (level > 2)
3306                 /* bits 7:3 reserved */
3307                 mask |= 0xf8;
3308         else if (level == 2) {
3309                 if (spte & (1ULL << 7))
3310                         /* 2MB ref, bits 20:12 reserved */
3311                         mask |= 0x1ff000;
3312                 else
3313                         /* bits 6:3 reserved */
3314                         mask |= 0x78;
3315         }
3316
3317         return mask;
3318 }
3319
3320 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3321                                        int level)
3322 {
3323         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3324
3325         /* 010b (write-only) */
3326         WARN_ON((spte & 0x7) == 0x2);
3327
3328         /* 110b (write/execute) */
3329         WARN_ON((spte & 0x7) == 0x6);
3330
3331         /* 100b (execute-only) and value not supported by logical processor */
3332         if (!cpu_has_vmx_ept_execute_only())
3333                 WARN_ON((spte & 0x7) == 0x4);
3334
3335         /* not 000b */
3336         if ((spte & 0x7)) {
3337                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3338
3339                 if (rsvd_bits != 0) {
3340                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3341                                          __func__, rsvd_bits);
3342                         WARN_ON(1);
3343                 }
3344
3345                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3346                         u64 ept_mem_type = (spte & 0x38) >> 3;
3347
3348                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3349                             ept_mem_type == 7) {
3350                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3351                                                 __func__, ept_mem_type);
3352                                 WARN_ON(1);
3353                         }
3354                 }
3355         }
3356 }
3357
3358 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3359 {
3360         u64 sptes[4];
3361         int nr_sptes, i;
3362         gpa_t gpa;
3363
3364         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3365
3366         printk(KERN_ERR "EPT: Misconfiguration.\n");
3367         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3368
3369         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3370
3371         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3372                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3373
3374         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3375         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3376
3377         return 0;
3378 }
3379
3380 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3381 {
3382         u32 cpu_based_vm_exec_control;
3383
3384         /* clear pending NMI */
3385         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3386         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3387         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3388         ++vcpu->stat.nmi_window_exits;
3389
3390         return 1;
3391 }
3392
3393 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3394 {
3395         struct vcpu_vmx *vmx = to_vmx(vcpu);
3396         enum emulation_result err = EMULATE_DONE;
3397         int ret = 1;
3398
3399         while (!guest_state_valid(vcpu)) {
3400                 err = emulate_instruction(vcpu, 0, 0, 0);
3401
3402                 if (err == EMULATE_DO_MMIO) {
3403                         ret = 0;
3404                         goto out;
3405                 }
3406
3407                 if (err != EMULATE_DONE) {
3408                         kvm_report_emulation_failure(vcpu, "emulation failure");
3409                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3410                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3411                         vcpu->run->internal.ndata = 0;
3412                         ret = 0;
3413                         goto out;
3414                 }
3415
3416                 if (signal_pending(current))
3417                         goto out;
3418                 if (need_resched())
3419                         schedule();
3420         }
3421
3422         vmx->emulation_required = 0;
3423 out:
3424         return ret;
3425 }
3426
3427 /*
3428  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3429  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3430  */
3431 static int handle_pause(struct kvm_vcpu *vcpu)
3432 {
3433         skip_emulated_instruction(vcpu);
3434         kvm_vcpu_on_spin(vcpu);
3435
3436         return 1;
3437 }
3438
3439 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3440 {
3441         kvm_queue_exception(vcpu, UD_VECTOR);
3442         return 1;
3443 }
3444
3445 /*
3446  * The exit handlers return 1 if the exit was handled fully and guest execution
3447  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3448  * to be done to userspace and return 0.
3449  */
3450 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3451         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3452         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3453         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3454         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3455         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3456         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3457         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3458         [EXIT_REASON_CPUID]                   = handle_cpuid,
3459         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3460         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3461         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3462         [EXIT_REASON_HLT]                     = handle_halt,
3463         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3464         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3465         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3466         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3467         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3468         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3469         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3470         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3471         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3472         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3473         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3474         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3475         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3476         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3477         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3478         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3479         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3480         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3481         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3482         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3483         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3484 };
3485
3486 static const int kvm_vmx_max_exit_handlers =
3487         ARRAY_SIZE(kvm_vmx_exit_handlers);
3488
3489 /*
3490  * The guest has exited.  See if we can fix it or if we need userspace
3491  * assistance.
3492  */
3493 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3494 {
3495         struct vcpu_vmx *vmx = to_vmx(vcpu);
3496         u32 exit_reason = vmx->exit_reason;
3497         u32 vectoring_info = vmx->idt_vectoring_info;
3498
3499         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3500
3501         /* If guest state is invalid, start emulating */
3502         if (vmx->emulation_required && emulate_invalid_guest_state)
3503                 return handle_invalid_guest_state(vcpu);
3504
3505         /* Access CR3 don't cause VMExit in paging mode, so we need
3506          * to sync with guest real CR3. */
3507         if (enable_ept && is_paging(vcpu))
3508                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3509
3510         if (unlikely(vmx->fail)) {
3511                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3512                 vcpu->run->fail_entry.hardware_entry_failure_reason
3513                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3514                 return 0;
3515         }
3516
3517         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3518                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3519                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3520                         exit_reason != EXIT_REASON_TASK_SWITCH))
3521                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3522                        "(0x%x) and exit reason is 0x%x\n",
3523                        __func__, vectoring_info, exit_reason);
3524
3525         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3526                 if (vmx_interrupt_allowed(vcpu)) {
3527                         vmx->soft_vnmi_blocked = 0;
3528                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3529                            vcpu->arch.nmi_pending) {
3530                         /*
3531                          * This CPU don't support us in finding the end of an
3532                          * NMI-blocked window if the guest runs with IRQs
3533                          * disabled. So we pull the trigger after 1 s of
3534                          * futile waiting, but inform the user about this.
3535                          */
3536                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3537                                "state on VCPU %d after 1 s timeout\n",
3538                                __func__, vcpu->vcpu_id);
3539                         vmx->soft_vnmi_blocked = 0;
3540                 }
3541         }
3542
3543         if (exit_reason < kvm_vmx_max_exit_handlers
3544             && kvm_vmx_exit_handlers[exit_reason])
3545                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3546         else {
3547                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3548                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3549         }
3550         return 0;
3551 }
3552
3553 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3554 {
3555         if (irr == -1 || tpr < irr) {
3556                 vmcs_write32(TPR_THRESHOLD, 0);
3557                 return;
3558         }
3559
3560         vmcs_write32(TPR_THRESHOLD, irr);
3561 }
3562
3563 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3564 {
3565         u32 exit_intr_info;
3566         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3567         bool unblock_nmi;
3568         u8 vector;
3569         int type;
3570         bool idtv_info_valid;
3571
3572         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3573
3574         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3575
3576         /* Handle machine checks before interrupts are enabled */
3577         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3578             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3579                 && is_machine_check(exit_intr_info)))
3580                 kvm_machine_check();
3581
3582         /* We need to handle NMIs before interrupts are enabled */
3583         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3584             (exit_intr_info & INTR_INFO_VALID_MASK))
3585                 asm("int $2");
3586
3587         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3588
3589         if (cpu_has_virtual_nmis()) {
3590                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3591                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3592                 /*
3593                  * SDM 3: 27.7.1.2 (September 2008)
3594                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3595                  * a guest IRET fault.
3596                  * SDM 3: 23.2.2 (September 2008)
3597                  * Bit 12 is undefined in any of the following cases:
3598                  *  If the VM exit sets the valid bit in the IDT-vectoring
3599                  *   information field.
3600                  *  If the VM exit is due to a double fault.
3601                  */
3602                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3603                     vector != DF_VECTOR && !idtv_info_valid)
3604                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3605                                       GUEST_INTR_STATE_NMI);
3606         } else if (unlikely(vmx->soft_vnmi_blocked))
3607                 vmx->vnmi_blocked_time +=
3608                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3609
3610         vmx->vcpu.arch.nmi_injected = false;
3611         kvm_clear_exception_queue(&vmx->vcpu);
3612         kvm_clear_interrupt_queue(&vmx->vcpu);
3613
3614         if (!idtv_info_valid)
3615                 return;
3616
3617         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3618         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3619
3620         switch (type) {
3621         case INTR_TYPE_NMI_INTR:
3622                 vmx->vcpu.arch.nmi_injected = true;
3623                 /*
3624                  * SDM 3: 27.7.1.2 (September 2008)
3625                  * Clear bit "block by NMI" before VM entry if a NMI
3626                  * delivery faulted.
3627                  */
3628                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3629                                 GUEST_INTR_STATE_NMI);
3630                 break;
3631         case INTR_TYPE_SOFT_EXCEPTION:
3632                 vmx->vcpu.arch.event_exit_inst_len =
3633                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3634                 /* fall through */
3635         case INTR_TYPE_HARD_EXCEPTION:
3636                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3637                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3638                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3639                 } else
3640                         kvm_queue_exception(&vmx->vcpu, vector);
3641                 break;
3642         case INTR_TYPE_SOFT_INTR:
3643                 vmx->vcpu.arch.event_exit_inst_len =
3644                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3645                 /* fall through */
3646         case INTR_TYPE_EXT_INTR:
3647                 kvm_queue_interrupt(&vmx->vcpu, vector,
3648                         type == INTR_TYPE_SOFT_INTR);
3649                 break;
3650         default:
3651                 break;
3652         }
3653 }
3654
3655 /*
3656  * Failure to inject an interrupt should give us the information
3657  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3658  * when fetching the interrupt redirection bitmap in the real-mode
3659  * tss, this doesn't happen.  So we do it ourselves.
3660  */
3661 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3662 {
3663         vmx->rmode.irq.pending = 0;
3664         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3665                 return;
3666         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3667         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3668                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3669                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3670                 return;
3671         }
3672         vmx->idt_vectoring_info =
3673                 VECTORING_INFO_VALID_MASK
3674                 | INTR_TYPE_EXT_INTR
3675                 | vmx->rmode.irq.vector;
3676 }
3677
3678 #ifdef CONFIG_X86_64
3679 #define R "r"
3680 #define Q "q"
3681 #else
3682 #define R "e"
3683 #define Q "l"
3684 #endif
3685
3686 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3687 {
3688         struct vcpu_vmx *vmx = to_vmx(vcpu);
3689
3690         /* Record the guest's net vcpu time for enforced NMI injections. */
3691         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3692                 vmx->entry_time = ktime_get();
3693
3694         /* Don't enter VMX if guest state is invalid, let the exit handler
3695            start emulation until we arrive back to a valid state */
3696         if (vmx->emulation_required && emulate_invalid_guest_state)
3697                 return;
3698
3699         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3700                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3701         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3702                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3703
3704         /* When single-stepping over STI and MOV SS, we must clear the
3705          * corresponding interruptibility bits in the guest state. Otherwise
3706          * vmentry fails as it then expects bit 14 (BS) in pending debug
3707          * exceptions being set, but that's not correct for the guest debugging
3708          * case. */
3709         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3710                 vmx_set_interrupt_shadow(vcpu, 0);
3711
3712         /*
3713          * Loading guest fpu may have cleared host cr0.ts
3714          */
3715         vmcs_writel(HOST_CR0, read_cr0());
3716
3717         if (vcpu->arch.switch_db_regs)
3718                 set_debugreg(vcpu->arch.dr6, 6);
3719
3720         asm(
3721                 /* Store host registers */
3722                 "push %%"R"dx; push %%"R"bp;"
3723                 "push %%"R"cx \n\t"
3724                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3725                 "je 1f \n\t"
3726                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3727                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3728                 "1: \n\t"
3729                 /* Reload cr2 if changed */
3730                 "mov %c[cr2](%0), %%"R"ax \n\t"
3731                 "mov %%cr2, %%"R"dx \n\t"
3732                 "cmp %%"R"ax, %%"R"dx \n\t"
3733                 "je 2f \n\t"
3734                 "mov %%"R"ax, %%cr2 \n\t"
3735                 "2: \n\t"
3736                 /* Check if vmlaunch of vmresume is needed */
3737                 "cmpl $0, %c[launched](%0) \n\t"
3738                 /* Load guest registers.  Don't clobber flags. */
3739                 "mov %c[rax](%0), %%"R"ax \n\t"
3740                 "mov %c[rbx](%0), %%"R"bx \n\t"
3741                 "mov %c[rdx](%0), %%"R"dx \n\t"
3742                 "mov %c[rsi](%0), %%"R"si \n\t"
3743                 "mov %c[rdi](%0), %%"R"di \n\t"
3744                 "mov %c[rbp](%0), %%"R"bp \n\t"
3745 #ifdef CONFIG_X86_64
3746                 "mov %c[r8](%0),  %%r8  \n\t"
3747                 "mov %c[r9](%0),  %%r9  \n\t"
3748                 "mov %c[r10](%0), %%r10 \n\t"
3749                 "mov %c[r11](%0), %%r11 \n\t"
3750                 "mov %c[r12](%0), %%r12 \n\t"
3751                 "mov %c[r13](%0), %%r13 \n\t"
3752                 "mov %c[r14](%0), %%r14 \n\t"
3753                 "mov %c[r15](%0), %%r15 \n\t"
3754 #endif
3755                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3756
3757                 /* Enter guest mode */
3758                 "jne .Llaunched \n\t"
3759                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3760                 "jmp .Lkvm_vmx_return \n\t"
3761                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3762                 ".Lkvm_vmx_return: "
3763                 /* Save guest registers, load host registers, keep flags */
3764                 "xchg %0,     (%%"R"sp) \n\t"
3765                 "mov %%"R"ax, %c[rax](%0) \n\t"
3766                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3767                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3768                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3769                 "mov %%"R"si, %c[rsi](%0) \n\t"
3770                 "mov %%"R"di, %c[rdi](%0) \n\t"
3771                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3772 #ifdef CONFIG_X86_64
3773                 "mov %%r8,  %c[r8](%0) \n\t"
3774                 "mov %%r9,  %c[r9](%0) \n\t"
3775                 "mov %%r10, %c[r10](%0) \n\t"
3776                 "mov %%r11, %c[r11](%0) \n\t"
3777                 "mov %%r12, %c[r12](%0) \n\t"
3778                 "mov %%r13, %c[r13](%0) \n\t"
3779                 "mov %%r14, %c[r14](%0) \n\t"
3780                 "mov %%r15, %c[r15](%0) \n\t"
3781 #endif
3782                 "mov %%cr2, %%"R"ax   \n\t"
3783                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3784
3785                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3786                 "setbe %c[fail](%0) \n\t"
3787               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3788                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3789                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3790                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3791                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3792                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3793                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3794                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3795                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3796                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3797                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3798 #ifdef CONFIG_X86_64
3799                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3800                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3801                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3802                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3803                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3804                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3805                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3806                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3807 #endif
3808                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3809               : "cc", "memory"
3810                 , R"bx", R"di", R"si"
3811 #ifdef CONFIG_X86_64
3812                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3813 #endif
3814               );
3815
3816         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3817                                   | (1 << VCPU_EXREG_PDPTR));
3818         vcpu->arch.regs_dirty = 0;
3819
3820         if (vcpu->arch.switch_db_regs)
3821                 get_debugreg(vcpu->arch.dr6, 6);
3822
3823         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3824         if (vmx->rmode.irq.pending)
3825                 fixup_rmode_irq(vmx);
3826
3827         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3828         vmx->launched = 1;
3829
3830         vmx_complete_interrupts(vmx);
3831 }
3832
3833 #undef R
3834 #undef Q
3835
3836 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3837 {
3838         struct vcpu_vmx *vmx = to_vmx(vcpu);
3839
3840         if (vmx->vmcs) {
3841                 vcpu_clear(vmx);
3842                 free_vmcs(vmx->vmcs);
3843                 vmx->vmcs = NULL;
3844         }
3845 }
3846
3847 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3848 {
3849         struct vcpu_vmx *vmx = to_vmx(vcpu);
3850
3851         spin_lock(&vmx_vpid_lock);
3852         if (vmx->vpid != 0)
3853                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3854         spin_unlock(&vmx_vpid_lock);
3855         vmx_free_vmcs(vcpu);
3856         kfree(vmx->guest_msrs);
3857         kvm_vcpu_uninit(vcpu);
3858         kmem_cache_free(kvm_vcpu_cache, vmx);
3859 }
3860
3861 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3862 {
3863         int err;
3864         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3865         int cpu;
3866
3867         if (!vmx)
3868                 return ERR_PTR(-ENOMEM);
3869
3870         allocate_vpid(vmx);
3871
3872         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3873         if (err)
3874                 goto free_vcpu;
3875
3876         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3877         if (!vmx->guest_msrs) {
3878                 err = -ENOMEM;
3879                 goto uninit_vcpu;
3880         }
3881
3882         vmx->vmcs = alloc_vmcs();
3883         if (!vmx->vmcs)
3884                 goto free_msrs;
3885
3886         vmcs_clear(vmx->vmcs);
3887
3888         cpu = get_cpu();
3889         vmx_vcpu_load(&vmx->vcpu, cpu);
3890         err = vmx_vcpu_setup(vmx);
3891         vmx_vcpu_put(&vmx->vcpu);
3892         put_cpu();
3893         if (err)
3894                 goto free_vmcs;
3895         if (vm_need_virtualize_apic_accesses(kvm))
3896                 if (alloc_apic_access_page(kvm) != 0)
3897                         goto free_vmcs;
3898
3899         if (enable_ept) {
3900                 if (!kvm->arch.ept_identity_map_addr)
3901                         kvm->arch.ept_identity_map_addr =
3902                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3903                 if (alloc_identity_pagetable(kvm) != 0)
3904                         goto free_vmcs;
3905         }
3906
3907         return &vmx->vcpu;
3908
3909 free_vmcs:
3910         free_vmcs(vmx->vmcs);
3911 free_msrs:
3912         kfree(vmx->guest_msrs);
3913 uninit_vcpu:
3914         kvm_vcpu_uninit(&vmx->vcpu);
3915 free_vcpu:
3916         kmem_cache_free(kvm_vcpu_cache, vmx);
3917         return ERR_PTR(err);
3918 }
3919
3920 static void __init vmx_check_processor_compat(void *rtn)
3921 {
3922         struct vmcs_config vmcs_conf;
3923
3924         *(int *)rtn = 0;
3925         if (setup_vmcs_config(&vmcs_conf) < 0)
3926                 *(int *)rtn = -EIO;
3927         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3928                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3929                                 smp_processor_id());
3930                 *(int *)rtn = -EIO;
3931         }
3932 }
3933
3934 static int get_ept_level(void)
3935 {
3936         return VMX_EPT_DEFAULT_GAW + 1;
3937 }
3938
3939 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3940 {
3941         u64 ret;
3942
3943         /* For VT-d and EPT combination
3944          * 1. MMIO: always map as UC
3945          * 2. EPT with VT-d:
3946          *   a. VT-d without snooping control feature: can't guarantee the
3947          *      result, try to trust guest.
3948          *   b. VT-d with snooping control feature: snooping control feature of
3949          *      VT-d engine can guarantee the cache correctness. Just set it
3950          *      to WB to keep consistent with host. So the same as item 3.
3951          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3952          *    consistent with host MTRR
3953          */
3954         if (is_mmio)
3955                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3956         else if (vcpu->kvm->arch.iommu_domain &&
3957                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3958                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3959                       VMX_EPT_MT_EPTE_SHIFT;
3960         else
3961                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3962                         | VMX_EPT_IGMT_BIT;
3963
3964         return ret;
3965 }
3966
3967 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3968         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3969         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3970         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3971         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3972         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3973         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3974         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3975         { EXIT_REASON_CPUID,                   "cpuid" },
3976         { EXIT_REASON_MSR_READ,                "rdmsr" },
3977         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3978         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3979         { EXIT_REASON_HLT,                     "halt" },
3980         { EXIT_REASON_INVLPG,                  "invlpg" },
3981         { EXIT_REASON_VMCALL,                  "hypercall" },
3982         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3983         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3984         { EXIT_REASON_WBINVD,                  "wbinvd" },
3985         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3986         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3987         { -1, NULL }
3988 };
3989
3990 static bool vmx_gb_page_enable(void)
3991 {
3992         return false;
3993 }
3994
3995 static struct kvm_x86_ops vmx_x86_ops = {
3996         .cpu_has_kvm_support = cpu_has_kvm_support,
3997         .disabled_by_bios = vmx_disabled_by_bios,
3998         .hardware_setup = hardware_setup,
3999         .hardware_unsetup = hardware_unsetup,
4000         .check_processor_compatibility = vmx_check_processor_compat,
4001         .hardware_enable = hardware_enable,
4002         .hardware_disable = hardware_disable,
4003         .cpu_has_accelerated_tpr = report_flexpriority,
4004
4005         .vcpu_create = vmx_create_vcpu,
4006         .vcpu_free = vmx_free_vcpu,
4007         .vcpu_reset = vmx_vcpu_reset,
4008
4009         .prepare_guest_switch = vmx_save_host_state,
4010         .vcpu_load = vmx_vcpu_load,
4011         .vcpu_put = vmx_vcpu_put,
4012
4013         .set_guest_debug = set_guest_debug,
4014         .get_msr = vmx_get_msr,
4015         .set_msr = vmx_set_msr,
4016         .get_segment_base = vmx_get_segment_base,
4017         .get_segment = vmx_get_segment,
4018         .set_segment = vmx_set_segment,
4019         .get_cpl = vmx_get_cpl,
4020         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4021         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4022         .set_cr0 = vmx_set_cr0,
4023         .set_cr3 = vmx_set_cr3,
4024         .set_cr4 = vmx_set_cr4,
4025         .set_efer = vmx_set_efer,
4026         .get_idt = vmx_get_idt,
4027         .set_idt = vmx_set_idt,
4028         .get_gdt = vmx_get_gdt,
4029         .set_gdt = vmx_set_gdt,
4030         .cache_reg = vmx_cache_reg,
4031         .get_rflags = vmx_get_rflags,
4032         .set_rflags = vmx_set_rflags,
4033
4034         .tlb_flush = vmx_flush_tlb,
4035
4036         .run = vmx_vcpu_run,
4037         .handle_exit = vmx_handle_exit,
4038         .skip_emulated_instruction = skip_emulated_instruction,
4039         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4040         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4041         .patch_hypercall = vmx_patch_hypercall,
4042         .set_irq = vmx_inject_irq,
4043         .set_nmi = vmx_inject_nmi,
4044         .queue_exception = vmx_queue_exception,
4045         .interrupt_allowed = vmx_interrupt_allowed,
4046         .nmi_allowed = vmx_nmi_allowed,
4047         .get_nmi_mask = vmx_get_nmi_mask,
4048         .set_nmi_mask = vmx_set_nmi_mask,
4049         .enable_nmi_window = enable_nmi_window,
4050         .enable_irq_window = enable_irq_window,
4051         .update_cr8_intercept = update_cr8_intercept,
4052
4053         .set_tss_addr = vmx_set_tss_addr,
4054         .get_tdp_level = get_ept_level,
4055         .get_mt_mask = vmx_get_mt_mask,
4056
4057         .exit_reasons_str = vmx_exit_reasons_str,
4058         .gb_page_enable = vmx_gb_page_enable,
4059 };
4060
4061 static int __init vmx_init(void)
4062 {
4063         int r, i;
4064
4065         rdmsrl_safe(MSR_EFER, &host_efer);
4066
4067         for (i = 0; i < NR_VMX_MSR; ++i)
4068                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4069
4070         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4071         if (!vmx_io_bitmap_a)
4072                 return -ENOMEM;
4073
4074         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4075         if (!vmx_io_bitmap_b) {
4076                 r = -ENOMEM;
4077                 goto out;
4078         }
4079
4080         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4081         if (!vmx_msr_bitmap_legacy) {
4082                 r = -ENOMEM;
4083                 goto out1;
4084         }
4085
4086         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4087         if (!vmx_msr_bitmap_longmode) {
4088                 r = -ENOMEM;
4089                 goto out2;
4090         }
4091
4092         /*
4093          * Allow direct access to the PC debug port (it is often used for I/O
4094          * delays, but the vmexits simply slow things down).
4095          */
4096         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4097         clear_bit(0x80, vmx_io_bitmap_a);
4098
4099         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4100
4101         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4102         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4103
4104         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4105
4106         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4107         if (r)
4108                 goto out3;
4109
4110         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4111         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4112         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4113         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4114         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4115         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4116
4117         if (enable_ept) {
4118                 bypass_guest_pf = 0;
4119                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4120                         VMX_EPT_WRITABLE_MASK);
4121                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4122                                 VMX_EPT_EXECUTABLE_MASK);
4123                 kvm_enable_tdp();
4124         } else
4125                 kvm_disable_tdp();
4126
4127         if (bypass_guest_pf)
4128                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4129
4130         return 0;
4131
4132 out3:
4133         free_page((unsigned long)vmx_msr_bitmap_longmode);
4134 out2:
4135         free_page((unsigned long)vmx_msr_bitmap_legacy);
4136 out1:
4137         free_page((unsigned long)vmx_io_bitmap_b);
4138 out:
4139         free_page((unsigned long)vmx_io_bitmap_a);
4140         return r;
4141 }
4142
4143 static void __exit vmx_exit(void)
4144 {
4145         free_page((unsigned long)vmx_msr_bitmap_legacy);
4146         free_page((unsigned long)vmx_msr_bitmap_longmode);
4147         free_page((unsigned long)vmx_io_bitmap_b);
4148         free_page((unsigned long)vmx_io_bitmap_a);
4149
4150         kvm_exit();
4151 }
4152
4153 module_init(vmx_init)
4154 module_exit(vmx_exit)