arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "vmx.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/desc.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 static int enable_vpid = 1;
  42 module_param(enable_vpid, bool, 0);
  43
  44 static int flexpriority_enabled = 1;
  45 module_param(flexpriority_enabled, bool, 0);
  46
  47 static int enable_ept = 1;
  48 module_param(enable_ept, bool, 0);
  49
  50 struct vmcs {
  51         u32 revision_id;
  52         u32 abort;
  53         char data[0];
  54 };
  55
  56 struct vcpu_vmx {
  57         struct kvm_vcpu       vcpu;
  58         int                   launched;
  59         u8                    fail;
  60         u32                   idt_vectoring_info;
  61         struct kvm_msr_entry *guest_msrs;
  62         struct kvm_msr_entry *host_msrs;
  63         int                   nmsrs;
  64         int                   save_nmsrs;
  65         int                   msr_offset_efer;
  66 #ifdef CONFIG_X86_64
  67         int                   msr_offset_kernel_gs_base;
  68 #endif
  69         struct vmcs          *vmcs;
  70         struct {
  71                 int           loaded;
  72                 u16           fs_sel, gs_sel, ldt_sel;
  73                 int           gs_ldt_reload_needed;
  74                 int           fs_reload_needed;
  75                 int           guest_efer_loaded;
  76         } host_state;
  77         struct {
  78                 struct {
  79                         bool pending;
  80                         u8 vector;
  81                         unsigned rip;
  82                 } irq;
  83         } rmode;
  84         int vpid;
  85 };
  86
  87 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  88 {
  89         return container_of(vcpu, struct vcpu_vmx, vcpu);
  90 }
  91
  92 static int init_rmode(struct kvm *kvm);
  93
  94 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  95 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  96
  97 static struct page *vmx_io_bitmap_a;
  98 static struct page *vmx_io_bitmap_b;
  99 static struct page *vmx_msr_bitmap;
 100
 101 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 102 static DEFINE_SPINLOCK(vmx_vpid_lock);
 103
 104 static struct vmcs_config {
 105         int size;
 106         int order;
 107         u32 revision_id;
 108         u32 pin_based_exec_ctrl;
 109         u32 cpu_based_exec_ctrl;
 110         u32 cpu_based_2nd_exec_ctrl;
 111         u32 vmexit_ctrl;
 112         u32 vmentry_ctrl;
 113 } vmcs_config;
 114
 115 struct vmx_capability {
 116         u32 ept;
 117         u32 vpid;
 118 } vmx_capability;
 119
 120 #define VMX_SEGMENT_FIELD(seg)                                  \
 121         [VCPU_SREG_##seg] = {                                   \
 122                 .selector = GUEST_##seg##_SELECTOR,             \
 123                 .base = GUEST_##seg##_BASE,                     \
 124                 .limit = GUEST_##seg##_LIMIT,                   \
 125                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 126         }
 127
 128 static struct kvm_vmx_segment_field {
 129         unsigned selector;
 130         unsigned base;
 131         unsigned limit;
 132         unsigned ar_bytes;
 133 } kvm_vmx_segment_fields[] = {
 134         VMX_SEGMENT_FIELD(CS),
 135         VMX_SEGMENT_FIELD(DS),
 136         VMX_SEGMENT_FIELD(ES),
 137         VMX_SEGMENT_FIELD(FS),
 138         VMX_SEGMENT_FIELD(GS),
 139         VMX_SEGMENT_FIELD(SS),
 140         VMX_SEGMENT_FIELD(TR),
 141         VMX_SEGMENT_FIELD(LDTR),
 142 };
 143
 144 /*
 145  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 146  * away by decrementing the array size.
 147  */
 148 static const u32 vmx_msr_index[] = {
 149 #ifdef CONFIG_X86_64
 150         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 151 #endif
 152         MSR_EFER, MSR_K6_STAR,
 153 };
 154 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 155
 156 static void load_msrs(struct kvm_msr_entry *e, int n)
 157 {
 158         int i;
 159
 160         for (i = 0; i < n; ++i)
 161                 wrmsrl(e[i].index, e[i].data);
 162 }
 163
 164 static void save_msrs(struct kvm_msr_entry *e, int n)
 165 {
 166         int i;
 167
 168         for (i = 0; i < n; ++i)
 169                 rdmsrl(e[i].index, e[i].data);
 170 }
 171
 172 static inline int is_page_fault(u32 intr_info)
 173 {
 174         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 175                              INTR_INFO_VALID_MASK)) ==
 176                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 177 }
 178
 179 static inline int is_no_device(u32 intr_info)
 180 {
 181         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 182                              INTR_INFO_VALID_MASK)) ==
 183                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 184 }
 185
 186 static inline int is_invalid_opcode(u32 intr_info)
 187 {
 188         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 189                              INTR_INFO_VALID_MASK)) ==
 190                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 191 }
 192
 193 static inline int is_external_interrupt(u32 intr_info)
 194 {
 195         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 196                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 197 }
 198
 199 static inline int cpu_has_vmx_msr_bitmap(void)
 200 {
 201         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 202 }
 203
 204 static inline int cpu_has_vmx_tpr_shadow(void)
 205 {
 206         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 207 }
 208
 209 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 210 {
 211         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 212 }
 213
 214 static inline int cpu_has_secondary_exec_ctrls(void)
 215 {
 216         return (vmcs_config.cpu_based_exec_ctrl &
 217                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 218 }
 219
 220 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 221 {
 222         return flexpriority_enabled
 223                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 224                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 225 }
 226
 227 static inline int cpu_has_vmx_invept_individual_addr(void)
 228 {
 229         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 230 }
 231
 232 static inline int cpu_has_vmx_invept_context(void)
 233 {
 234         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 235 }
 236
 237 static inline int cpu_has_vmx_invept_global(void)
 238 {
 239         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 240 }
 241
 242 static inline int cpu_has_vmx_ept(void)
 243 {
 244         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 245                 SECONDARY_EXEC_ENABLE_EPT);
 246 }
 247
 248 static inline int vm_need_ept(void)
 249 {
 250         return (cpu_has_vmx_ept() && enable_ept);
 251 }
 252
 253 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 254 {
 255         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 256                 (irqchip_in_kernel(kvm)));
 257 }
 258
 259 static inline int cpu_has_vmx_vpid(void)
 260 {
 261         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 262                 SECONDARY_EXEC_ENABLE_VPID);
 263 }
 264
 265 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 266 {
 267         int i;
 268
 269         for (i = 0; i < vmx->nmsrs; ++i)
 270                 if (vmx->guest_msrs[i].index == msr)
 271                         return i;
 272         return -1;
 273 }
 274
 275 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 276 {
 277     struct {
 278         u64 vpid : 16;
 279         u64 rsvd : 48;
 280         u64 gva;
 281     } operand = { vpid, 0, gva };
 282
 283     asm volatile (__ex(ASM_VMX_INVVPID)
 284                   /* CF==1 or ZF==1 --> rc = -1 */
 285                   "; ja 1f ; ud2 ; 1:"
 286                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 287 }
 288
 289 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 290 {
 291         struct {
 292                 u64 eptp, gpa;
 293         } operand = {eptp, gpa};
 294
 295         asm volatile (__ex(ASM_VMX_INVEPT)
 296                         /* CF==1 or ZF==1 --> rc = -1 */
 297                         "; ja 1f ; ud2 ; 1:\n"
 298                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 299 }
 300
 301 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 302 {
 303         int i;
 304
 305         i = __find_msr_index(vmx, msr);
 306         if (i >= 0)
 307                 return &vmx->guest_msrs[i];
 308         return NULL;
 309 }
 310
 311 static void vmcs_clear(struct vmcs *vmcs)
 312 {
 313         u64 phys_addr = __pa(vmcs);
 314         u8 error;
 315
 316         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 317                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 318                       : "cc", "memory");
 319         if (error)
 320                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 321                        vmcs, phys_addr);
 322 }
 323
 324 static void __vcpu_clear(void *arg)
 325 {
 326         struct vcpu_vmx *vmx = arg;
 327         int cpu = raw_smp_processor_id();
 328
 329         if (vmx->vcpu.cpu == cpu)
 330                 vmcs_clear(vmx->vmcs);
 331         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 332                 per_cpu(current_vmcs, cpu) = NULL;
 333         rdtscll(vmx->vcpu.arch.host_tsc);
 334 }
 335
 336 static void vcpu_clear(struct vcpu_vmx *vmx)
 337 {
 338         if (vmx->vcpu.cpu == -1)
 339                 return;
 340         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 341         vmx->launched = 0;
 342 }
 343
 344 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 345 {
 346         if (vmx->vpid == 0)
 347                 return;
 348
 349         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 350 }
 351
 352 static inline void ept_sync_global(void)
 353 {
 354         if (cpu_has_vmx_invept_global())
 355                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 356 }
 357
 358 static inline void ept_sync_context(u64 eptp)
 359 {
 360         if (vm_need_ept()) {
 361                 if (cpu_has_vmx_invept_context())
 362                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 363                 else
 364                         ept_sync_global();
 365         }
 366 }
 367
 368 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 369 {
 370         if (vm_need_ept()) {
 371                 if (cpu_has_vmx_invept_individual_addr())
 372                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 373                                         eptp, gpa);
 374                 else
 375                         ept_sync_context(eptp);
 376         }
 377 }
 378
 379 static unsigned long vmcs_readl(unsigned long field)
 380 {
 381         unsigned long value;
 382
 383         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 384                       : "=a"(value) : "d"(field) : "cc");
 385         return value;
 386 }
 387
 388 static u16 vmcs_read16(unsigned long field)
 389 {
 390         return vmcs_readl(field);
 391 }
 392
 393 static u32 vmcs_read32(unsigned long field)
 394 {
 395         return vmcs_readl(field);
 396 }
 397
 398 static u64 vmcs_read64(unsigned long field)
 399 {
 400 #ifdef CONFIG_X86_64
 401         return vmcs_readl(field);
 402 #else
 403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 404 #endif
 405 }
 406
 407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 408 {
 409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 411         dump_stack();
 412 }
 413
 414 static void vmcs_writel(unsigned long field, unsigned long value)
 415 {
 416         u8 error;
 417
 418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 420         if (unlikely(error))
 421                 vmwrite_error(field, value);
 422 }
 423
 424 static void vmcs_write16(unsigned long field, u16 value)
 425 {
 426         vmcs_writel(field, value);
 427 }
 428
 429 static void vmcs_write32(unsigned long field, u32 value)
 430 {
 431         vmcs_writel(field, value);
 432 }
 433
 434 static void vmcs_write64(unsigned long field, u64 value)
 435 {
 436         vmcs_writel(field, value);
 437 #ifndef CONFIG_X86_64
 438         asm volatile ("");
 439         vmcs_writel(field+1, value >> 32);
 440 #endif
 441 }
 442
 443 static void vmcs_clear_bits(unsigned long field, u32 mask)
 444 {
 445         vmcs_writel(field, vmcs_readl(field) & ~mask);
 446 }
 447
 448 static void vmcs_set_bits(unsigned long field, u32 mask)
 449 {
 450         vmcs_writel(field, vmcs_readl(field) | mask);
 451 }
 452
 453 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 454 {
 455         u32 eb;
 456
 457         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 458         if (!vcpu->fpu_active)
 459                 eb |= 1u << NM_VECTOR;
 460         if (vcpu->guest_debug.enabled)
 461                 eb |= 1u << 1;
 462         if (vcpu->arch.rmode.active)
 463                 eb = ~0;
 464         if (vm_need_ept())
 465                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 466         vmcs_write32(EXCEPTION_BITMAP, eb);
 467 }
 468
 469 static void reload_tss(void)
 470 {
 471         /*
 472          * VT restores TR but not its size.  Useless.
 473          */
 474         struct descriptor_table gdt;
 475         struct desc_struct *descs;
 476
 477         get_gdt(&gdt);
 478         descs = (void *)gdt.base;
 479         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 480         load_TR_desc();
 481 }
 482
 483 static void load_transition_efer(struct vcpu_vmx *vmx)
 484 {
 485         int efer_offset = vmx->msr_offset_efer;
 486         u64 host_efer = vmx->host_msrs[efer_offset].data;
 487         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 488         u64 ignore_bits;
 489
 490         if (efer_offset < 0)
 491                 return;
 492         /*
 493          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 494          * outside long mode
 495          */
 496         ignore_bits = EFER_NX | EFER_SCE;
 497 #ifdef CONFIG_X86_64
 498         ignore_bits |= EFER_LMA | EFER_LME;
 499         /* SCE is meaningful only in long mode on Intel */
 500         if (guest_efer & EFER_LMA)
 501                 ignore_bits &= ~(u64)EFER_SCE;
 502 #endif
 503         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 504                 return;
 505
 506         vmx->host_state.guest_efer_loaded = 1;
 507         guest_efer &= ~ignore_bits;
 508         guest_efer |= host_efer & ignore_bits;
 509         wrmsrl(MSR_EFER, guest_efer);
 510         vmx->vcpu.stat.efer_reload++;
 511 }
 512
 513 static void reload_host_efer(struct vcpu_vmx *vmx)
 514 {
 515         if (vmx->host_state.guest_efer_loaded) {
 516                 vmx->host_state.guest_efer_loaded = 0;
 517                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 518         }
 519 }
 520
 521 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 522 {
 523         struct vcpu_vmx *vmx = to_vmx(vcpu);
 524
 525         if (vmx->host_state.loaded)
 526                 return;
 527
 528         vmx->host_state.loaded = 1;
 529         /*
 530          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 531          * allow segment selectors with cpl > 0 or ti == 1.
 532          */
 533         vmx->host_state.ldt_sel = read_ldt();
 534         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 535         vmx->host_state.fs_sel = read_fs();
 536         if (!(vmx->host_state.fs_sel & 7)) {
 537                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 538                 vmx->host_state.fs_reload_needed = 0;
 539         } else {
 540                 vmcs_write16(HOST_FS_SELECTOR, 0);
 541                 vmx->host_state.fs_reload_needed = 1;
 542         }
 543         vmx->host_state.gs_sel = read_gs();
 544         if (!(vmx->host_state.gs_sel & 7))
 545                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 546         else {
 547                 vmcs_write16(HOST_GS_SELECTOR, 0);
 548                 vmx->host_state.gs_ldt_reload_needed = 1;
 549         }
 550
 551 #ifdef CONFIG_X86_64
 552         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 553         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 554 #else
 555         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 556         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 557 #endif
 558
 559 #ifdef CONFIG_X86_64
 560         if (is_long_mode(&vmx->vcpu))
 561                 save_msrs(vmx->host_msrs +
 562                           vmx->msr_offset_kernel_gs_base, 1);
 563
 564 #endif
 565         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 566         load_transition_efer(vmx);
 567 }
 568
 569 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 570 {
 571         unsigned long flags;
 572
 573         if (!vmx->host_state.loaded)
 574                 return;
 575
 576         ++vmx->vcpu.stat.host_state_reload;
 577         vmx->host_state.loaded = 0;
 578         if (vmx->host_state.fs_reload_needed)
 579                 load_fs(vmx->host_state.fs_sel);
 580         if (vmx->host_state.gs_ldt_reload_needed) {
 581                 load_ldt(vmx->host_state.ldt_sel);
 582                 /*
 583                  * If we have to reload gs, we must take care to
 584                  * preserve our gs base.
 585                  */
 586                 local_irq_save(flags);
 587                 load_gs(vmx->host_state.gs_sel);
 588 #ifdef CONFIG_X86_64
 589                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 590 #endif
 591                 local_irq_restore(flags);
 592         }
 593         reload_tss();
 594         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 595         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 596         reload_host_efer(vmx);
 597 }
 598
 599 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 600 {
 601         preempt_disable();
 602         __vmx_load_host_state(vmx);
 603         preempt_enable();
 604 }
 605
 606 /*
 607  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 608  * vcpu mutex is already taken.
 609  */
 610 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 611 {
 612         struct vcpu_vmx *vmx = to_vmx(vcpu);
 613         u64 phys_addr = __pa(vmx->vmcs);
 614         u64 tsc_this, delta, new_offset;
 615
 616         if (vcpu->cpu != cpu) {
 617                 vcpu_clear(vmx);
 618                 kvm_migrate_timers(vcpu);
 619                 vpid_sync_vcpu_all(vmx);
 620         }
 621
 622         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 623                 u8 error;
 624
 625                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 626                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 627                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 628                               : "cc");
 629                 if (error)
 630                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 631                                vmx->vmcs, phys_addr);
 632         }
 633
 634         if (vcpu->cpu != cpu) {
 635                 struct descriptor_table dt;
 636                 unsigned long sysenter_esp;
 637
 638                 vcpu->cpu = cpu;
 639                 /*
 640                  * Linux uses per-cpu TSS and GDT, so set these when switching
 641                  * processors.
 642                  */
 643                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 644                 get_gdt(&dt);
 645                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 646
 647                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 648                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 649
 650                 /*
 651                  * Make sure the time stamp counter is monotonous.
 652                  */
 653                 rdtscll(tsc_this);
 654                 if (tsc_this < vcpu->arch.host_tsc) {
 655                         delta = vcpu->arch.host_tsc - tsc_this;
 656                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 657                         vmcs_write64(TSC_OFFSET, new_offset);
 658                 }
 659         }
 660 }
 661
 662 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 663 {
 664         __vmx_load_host_state(to_vmx(vcpu));
 665 }
 666
 667 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 668 {
 669         if (vcpu->fpu_active)
 670                 return;
 671         vcpu->fpu_active = 1;
 672         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 673         if (vcpu->arch.cr0 & X86_CR0_TS)
 674                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 675         update_exception_bitmap(vcpu);
 676 }
 677
 678 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 679 {
 680         if (!vcpu->fpu_active)
 681                 return;
 682         vcpu->fpu_active = 0;
 683         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 684         update_exception_bitmap(vcpu);
 685 }
 686
 687 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 688 {
 689         vcpu_clear(to_vmx(vcpu));
 690 }
 691
 692 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 693 {
 694         return vmcs_readl(GUEST_RFLAGS);
 695 }
 696
 697 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 698 {
 699         if (vcpu->arch.rmode.active)
 700                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 701         vmcs_writel(GUEST_RFLAGS, rflags);
 702 }
 703
 704 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 705 {
 706         unsigned long rip;
 707         u32 interruptibility;
 708
 709         rip = vmcs_readl(GUEST_RIP);
 710         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 711         vmcs_writel(GUEST_RIP, rip);
 712
 713         /*
 714          * We emulated an instruction, so temporary interrupt blocking
 715          * should be removed, if set.
 716          */
 717         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 718         if (interruptibility & 3)
 719                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 720                              interruptibility & ~3);
 721         vcpu->arch.interrupt_window_open = 1;
 722 }
 723
 724 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 725                                 bool has_error_code, u32 error_code)
 726 {
 727         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 728                      nr | INTR_TYPE_EXCEPTION
 729                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 730                      | INTR_INFO_VALID_MASK);
 731         if (has_error_code)
 732                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 733 }
 734
 735 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 736 {
 737         struct vcpu_vmx *vmx = to_vmx(vcpu);
 738
 739         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
 740 }
 741
 742 /*
 743  * Swap MSR entry in host/guest MSR entry array.
 744  */
 745 #ifdef CONFIG_X86_64
 746 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 747 {
 748         struct kvm_msr_entry tmp;
 749
 750         tmp = vmx->guest_msrs[to];
 751         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 752         vmx->guest_msrs[from] = tmp;
 753         tmp = vmx->host_msrs[to];
 754         vmx->host_msrs[to] = vmx->host_msrs[from];
 755         vmx->host_msrs[from] = tmp;
 756 }
 757 #endif
 758
 759 /*
 760  * Set up the vmcs to automatically save and restore system
 761  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 762  * mode, as fiddling with msrs is very expensive.
 763  */
 764 static void setup_msrs(struct vcpu_vmx *vmx)
 765 {
 766         int save_nmsrs;
 767
 768         vmx_load_host_state(vmx);
 769         save_nmsrs = 0;
 770 #ifdef CONFIG_X86_64
 771         if (is_long_mode(&vmx->vcpu)) {
 772                 int index;
 773
 774                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 775                 if (index >= 0)
 776                         move_msr_up(vmx, index, save_nmsrs++);
 777                 index = __find_msr_index(vmx, MSR_LSTAR);
 778                 if (index >= 0)
 779                         move_msr_up(vmx, index, save_nmsrs++);
 780                 index = __find_msr_index(vmx, MSR_CSTAR);
 781                 if (index >= 0)
 782                         move_msr_up(vmx, index, save_nmsrs++);
 783                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 784                 if (index >= 0)
 785                         move_msr_up(vmx, index, save_nmsrs++);
 786                 /*
 787                  * MSR_K6_STAR is only needed on long mode guests, and only
 788                  * if efer.sce is enabled.
 789                  */
 790                 index = __find_msr_index(vmx, MSR_K6_STAR);
 791                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 792                         move_msr_up(vmx, index, save_nmsrs++);
 793         }
 794 #endif
 795         vmx->save_nmsrs = save_nmsrs;
 796
 797 #ifdef CONFIG_X86_64
 798         vmx->msr_offset_kernel_gs_base =
 799                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 800 #endif
 801         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 802 }
 803
 804 /*
 805  * reads and returns guest's timestamp counter "register"
 806  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 807  */
 808 static u64 guest_read_tsc(void)
 809 {
 810         u64 host_tsc, tsc_offset;
 811
 812         rdtscll(host_tsc);
 813         tsc_offset = vmcs_read64(TSC_OFFSET);
 814         return host_tsc + tsc_offset;
 815 }
 816
 817 /*
 818  * writes 'guest_tsc' into guest's timestamp counter "register"
 819  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 820  */
 821 static void guest_write_tsc(u64 guest_tsc)
 822 {
 823         u64 host_tsc;
 824
 825         rdtscll(host_tsc);
 826         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 827 }
 828
 829 /*
 830  * Reads an msr value (of 'msr_index') into 'pdata'.
 831  * Returns 0 on success, non-0 otherwise.
 832  * Assumes vcpu_load() was already called.
 833  */
 834 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 835 {
 836         u64 data;
 837         struct kvm_msr_entry *msr;
 838
 839         if (!pdata) {
 840                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 841                 return -EINVAL;
 842         }
 843
 844         switch (msr_index) {
 845 #ifdef CONFIG_X86_64
 846         case MSR_FS_BASE:
 847                 data = vmcs_readl(GUEST_FS_BASE);
 848                 break;
 849         case MSR_GS_BASE:
 850                 data = vmcs_readl(GUEST_GS_BASE);
 851                 break;
 852         case MSR_EFER:
 853                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 854 #endif
 855         case MSR_IA32_TIME_STAMP_COUNTER:
 856                 data = guest_read_tsc();
 857                 break;
 858         case MSR_IA32_SYSENTER_CS:
 859                 data = vmcs_read32(GUEST_SYSENTER_CS);
 860                 break;
 861         case MSR_IA32_SYSENTER_EIP:
 862                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 863                 break;
 864         case MSR_IA32_SYSENTER_ESP:
 865                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 866                 break;
 867         default:
 868                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 869                 if (msr) {
 870                         data = msr->data;
 871                         break;
 872                 }
 873                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 874         }
 875
 876         *pdata = data;
 877         return 0;
 878 }
 879
 880 /*
 881  * Writes msr value into into the appropriate "register".
 882  * Returns 0 on success, non-0 otherwise.
 883  * Assumes vcpu_load() was already called.
 884  */
 885 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 886 {
 887         struct vcpu_vmx *vmx = to_vmx(vcpu);
 888         struct kvm_msr_entry *msr;
 889         int ret = 0;
 890
 891         switch (msr_index) {
 892 #ifdef CONFIG_X86_64
 893         case MSR_EFER:
 894                 vmx_load_host_state(vmx);
 895                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 896                 break;
 897         case MSR_FS_BASE:
 898                 vmcs_writel(GUEST_FS_BASE, data);
 899                 break;
 900         case MSR_GS_BASE:
 901                 vmcs_writel(GUEST_GS_BASE, data);
 902                 break;
 903 #endif
 904         case MSR_IA32_SYSENTER_CS:
 905                 vmcs_write32(GUEST_SYSENTER_CS, data);
 906                 break;
 907         case MSR_IA32_SYSENTER_EIP:
 908                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 909                 break;
 910         case MSR_IA32_SYSENTER_ESP:
 911                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 912                 break;
 913         case MSR_IA32_TIME_STAMP_COUNTER:
 914                 guest_write_tsc(data);
 915                 break;
 916         default:
 917                 vmx_load_host_state(vmx);
 918                 msr = find_msr_entry(vmx, msr_index);
 919                 if (msr) {
 920                         msr->data = data;
 921                         break;
 922                 }
 923                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 924         }
 925
 926         return ret;
 927 }
 928
 929 /*
 930  * Sync the rsp and rip registers into the vcpu structure.  This allows
 931  * registers to be accessed by indexing vcpu->arch.regs.
 932  */
 933 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 934 {
 935         vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 936         vcpu->arch.rip = vmcs_readl(GUEST_RIP);
 937 }
 938
 939 /*
 940  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 941  * modification.
 942  */
 943 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 944 {
 945         vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
 946         vmcs_writel(GUEST_RIP, vcpu->arch.rip);
 947 }
 948
 949 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 950 {
 951         unsigned long dr7 = 0x400;
 952         int old_singlestep;
 953
 954         old_singlestep = vcpu->guest_debug.singlestep;
 955
 956         vcpu->guest_debug.enabled = dbg->enabled;
 957         if (vcpu->guest_debug.enabled) {
 958                 int i;
 959
 960                 dr7 |= 0x200;  /* exact */
 961                 for (i = 0; i < 4; ++i) {
 962                         if (!dbg->breakpoints[i].enabled)
 963                                 continue;
 964                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 965                         dr7 |= 2 << (i*2);    /* global enable */
 966                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 967                 }
 968
 969                 vcpu->guest_debug.singlestep = dbg->singlestep;
 970         } else
 971                 vcpu->guest_debug.singlestep = 0;
 972
 973         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 974                 unsigned long flags;
 975
 976                 flags = vmcs_readl(GUEST_RFLAGS);
 977                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 978                 vmcs_writel(GUEST_RFLAGS, flags);
 979         }
 980
 981         update_exception_bitmap(vcpu);
 982         vmcs_writel(GUEST_DR7, dr7);
 983
 984         return 0;
 985 }
 986
 987 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 988 {
 989         struct vcpu_vmx *vmx = to_vmx(vcpu);
 990         u32 idtv_info_field;
 991
 992         idtv_info_field = vmx->idt_vectoring_info;
 993         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 994                 if (is_external_interrupt(idtv_info_field))
 995                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 996                 else
 997                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 998         }
 999         return -1;
1000 }
1001
1002 static __init int cpu_has_kvm_support(void)
1003 {
1004         unsigned long ecx = cpuid_ecx(1);
1005         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1006 }
1007
1008 static __init int vmx_disabled_by_bios(void)
1009 {
1010         u64 msr;
1011
1012         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1013         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1014                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1015             == MSR_IA32_FEATURE_CONTROL_LOCKED;
1016         /* locked but not enabled */
1017 }
1018
1019 static void hardware_enable(void *garbage)
1020 {
1021         int cpu = raw_smp_processor_id();
1022         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1023         u64 old;
1024
1025         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1026         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1027                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1028             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
1029                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1030                 /* enable and lock */
1031                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1032                        MSR_IA32_FEATURE_CONTROL_LOCKED |
1033                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
1034         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1035         asm volatile (ASM_VMX_VMXON_RAX
1036                       : : "a"(&phys_addr), "m"(phys_addr)
1037                       : "memory", "cc");
1038 }
1039
1040 static void hardware_disable(void *garbage)
1041 {
1042         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1043         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1044 }
1045
1046 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1047                                       u32 msr, u32 *result)
1048 {
1049         u32 vmx_msr_low, vmx_msr_high;
1050         u32 ctl = ctl_min | ctl_opt;
1051
1052         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1053
1054         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1055         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1056
1057         /* Ensure minimum (required) set of control bits are supported. */
1058         if (ctl_min & ~ctl)
1059                 return -EIO;
1060
1061         *result = ctl;
1062         return 0;
1063 }
1064
1065 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1066 {
1067         u32 vmx_msr_low, vmx_msr_high;
1068         u32 min, opt, min2, opt2;
1069         u32 _pin_based_exec_control = 0;
1070         u32 _cpu_based_exec_control = 0;
1071         u32 _cpu_based_2nd_exec_control = 0;
1072         u32 _vmexit_control = 0;
1073         u32 _vmentry_control = 0;
1074
1075         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1076         opt = 0;
1077         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1078                                 &_pin_based_exec_control) < 0)
1079                 return -EIO;
1080
1081         min = CPU_BASED_HLT_EXITING |
1082 #ifdef CONFIG_X86_64
1083               CPU_BASED_CR8_LOAD_EXITING |
1084               CPU_BASED_CR8_STORE_EXITING |
1085 #endif
1086               CPU_BASED_CR3_LOAD_EXITING |
1087               CPU_BASED_CR3_STORE_EXITING |
1088               CPU_BASED_USE_IO_BITMAPS |
1089               CPU_BASED_MOV_DR_EXITING |
1090               CPU_BASED_USE_TSC_OFFSETING;
1091         opt = CPU_BASED_TPR_SHADOW |
1092               CPU_BASED_USE_MSR_BITMAPS |
1093               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1094         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1095                                 &_cpu_based_exec_control) < 0)
1096                 return -EIO;
1097 #ifdef CONFIG_X86_64
1098         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1099                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1100                                            ~CPU_BASED_CR8_STORE_EXITING;
1101 #endif
1102         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1103                 min2 = 0;
1104                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1105                         SECONDARY_EXEC_WBINVD_EXITING |
1106                         SECONDARY_EXEC_ENABLE_VPID |
1107                         SECONDARY_EXEC_ENABLE_EPT;
1108                 if (adjust_vmx_controls(min2, opt2,
1109                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1110                                         &_cpu_based_2nd_exec_control) < 0)
1111                         return -EIO;
1112         }
1113 #ifndef CONFIG_X86_64
1114         if (!(_cpu_based_2nd_exec_control &
1115                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1116                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1117 #endif
1118         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1119                 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1120                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1121                          CPU_BASED_CR3_STORE_EXITING);
1122                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1123                                         &_cpu_based_exec_control) < 0)
1124                         return -EIO;
1125                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1126                       vmx_capability.ept, vmx_capability.vpid);
1127         }
1128
1129         min = 0;
1130 #ifdef CONFIG_X86_64
1131         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1132 #endif
1133         opt = 0;
1134         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1135                                 &_vmexit_control) < 0)
1136                 return -EIO;
1137
1138         min = opt = 0;
1139         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1140                                 &_vmentry_control) < 0)
1141                 return -EIO;
1142
1143         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1144
1145         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1146         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1147                 return -EIO;
1148
1149 #ifdef CONFIG_X86_64
1150         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1151         if (vmx_msr_high & (1u<<16))
1152                 return -EIO;
1153 #endif
1154
1155         /* Require Write-Back (WB) memory type for VMCS accesses. */
1156         if (((vmx_msr_high >> 18) & 15) != 6)
1157                 return -EIO;
1158
1159         vmcs_conf->size = vmx_msr_high & 0x1fff;
1160         vmcs_conf->order = get_order(vmcs_config.size);
1161         vmcs_conf->revision_id = vmx_msr_low;
1162
1163         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1164         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1165         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1166         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1167         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1168
1169         return 0;
1170 }
1171
1172 static struct vmcs *alloc_vmcs_cpu(int cpu)
1173 {
1174         int node = cpu_to_node(cpu);
1175         struct page *pages;
1176         struct vmcs *vmcs;
1177
1178         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1179         if (!pages)
1180                 return NULL;
1181         vmcs = page_address(pages);
1182         memset(vmcs, 0, vmcs_config.size);
1183         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1184         return vmcs;
1185 }
1186
1187 static struct vmcs *alloc_vmcs(void)
1188 {
1189         return alloc_vmcs_cpu(raw_smp_processor_id());
1190 }
1191
1192 static void free_vmcs(struct vmcs *vmcs)
1193 {
1194         free_pages((unsigned long)vmcs, vmcs_config.order);
1195 }
1196
1197 static void free_kvm_area(void)
1198 {
1199         int cpu;
1200
1201         for_each_online_cpu(cpu)
1202                 free_vmcs(per_cpu(vmxarea, cpu));
1203 }
1204
1205 static __init int alloc_kvm_area(void)
1206 {
1207         int cpu;
1208
1209         for_each_online_cpu(cpu) {
1210                 struct vmcs *vmcs;
1211
1212                 vmcs = alloc_vmcs_cpu(cpu);
1213                 if (!vmcs) {
1214                         free_kvm_area();
1215                         return -ENOMEM;
1216                 }
1217
1218                 per_cpu(vmxarea, cpu) = vmcs;
1219         }
1220         return 0;
1221 }
1222
1223 static __init int hardware_setup(void)
1224 {
1225         if (setup_vmcs_config(&vmcs_config) < 0)
1226                 return -EIO;
1227
1228         if (boot_cpu_has(X86_FEATURE_NX))
1229                 kvm_enable_efer_bits(EFER_NX);
1230
1231         return alloc_kvm_area();
1232 }
1233
1234 static __exit void hardware_unsetup(void)
1235 {
1236         free_kvm_area();
1237 }
1238
1239 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1240 {
1241         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1242
1243         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1244                 vmcs_write16(sf->selector, save->selector);
1245                 vmcs_writel(sf->base, save->base);
1246                 vmcs_write32(sf->limit, save->limit);
1247                 vmcs_write32(sf->ar_bytes, save->ar);
1248         } else {
1249                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1250                         << AR_DPL_SHIFT;
1251                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1252         }
1253 }
1254
1255 static void enter_pmode(struct kvm_vcpu *vcpu)
1256 {
1257         unsigned long flags;
1258
1259         vcpu->arch.rmode.active = 0;
1260
1261         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1262         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1263         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1264
1265         flags = vmcs_readl(GUEST_RFLAGS);
1266         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1267         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1268         vmcs_writel(GUEST_RFLAGS, flags);
1269
1270         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1271                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1272
1273         update_exception_bitmap(vcpu);
1274
1275         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1276         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1277         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1278         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1279
1280         vmcs_write16(GUEST_SS_SELECTOR, 0);
1281         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1282
1283         vmcs_write16(GUEST_CS_SELECTOR,
1284                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1285         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1286 }
1287
1288 static gva_t rmode_tss_base(struct kvm *kvm)
1289 {
1290         if (!kvm->arch.tss_addr) {
1291                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1292                                  kvm->memslots[0].npages - 3;
1293                 return base_gfn << PAGE_SHIFT;
1294         }
1295         return kvm->arch.tss_addr;
1296 }
1297
1298 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1299 {
1300         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1301
1302         save->selector = vmcs_read16(sf->selector);
1303         save->base = vmcs_readl(sf->base);
1304         save->limit = vmcs_read32(sf->limit);
1305         save->ar = vmcs_read32(sf->ar_bytes);
1306         vmcs_write16(sf->selector, save->base >> 4);
1307         vmcs_write32(sf->base, save->base & 0xfffff);
1308         vmcs_write32(sf->limit, 0xffff);
1309         vmcs_write32(sf->ar_bytes, 0xf3);
1310 }
1311
1312 static void enter_rmode(struct kvm_vcpu *vcpu)
1313 {
1314         unsigned long flags;
1315
1316         vcpu->arch.rmode.active = 1;
1317
1318         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1319         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1320
1321         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1322         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1323
1324         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1325         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1326
1327         flags = vmcs_readl(GUEST_RFLAGS);
1328         vcpu->arch.rmode.save_iopl
1329                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1330
1331         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1332
1333         vmcs_writel(GUEST_RFLAGS, flags);
1334         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1335         update_exception_bitmap(vcpu);
1336
1337         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1338         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1339         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1340
1341         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1342         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1343         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1344                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1345         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1346
1347         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1348         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1349         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1350         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1351
1352         kvm_mmu_reset_context(vcpu);
1353         init_rmode(vcpu->kvm);
1354 }
1355
1356 #ifdef CONFIG_X86_64
1357
1358 static void enter_lmode(struct kvm_vcpu *vcpu)
1359 {
1360         u32 guest_tr_ar;
1361
1362         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1363         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1364                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1365                        __func__);
1366                 vmcs_write32(GUEST_TR_AR_BYTES,
1367                              (guest_tr_ar & ~AR_TYPE_MASK)
1368                              | AR_TYPE_BUSY_64_TSS);
1369         }
1370
1371         vcpu->arch.shadow_efer |= EFER_LMA;
1372
1373         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1374         vmcs_write32(VM_ENTRY_CONTROLS,
1375                      vmcs_read32(VM_ENTRY_CONTROLS)
1376                      | VM_ENTRY_IA32E_MODE);
1377 }
1378
1379 static void exit_lmode(struct kvm_vcpu *vcpu)
1380 {
1381         vcpu->arch.shadow_efer &= ~EFER_LMA;
1382
1383         vmcs_write32(VM_ENTRY_CONTROLS,
1384                      vmcs_read32(VM_ENTRY_CONTROLS)
1385                      & ~VM_ENTRY_IA32E_MODE);
1386 }
1387
1388 #endif
1389
1390 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1391 {
1392         vpid_sync_vcpu_all(to_vmx(vcpu));
1393 }
1394
1395 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1396 {
1397         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1398         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1399 }
1400
1401 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1402 {
1403         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1404                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1405                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1406                         return;
1407                 }
1408                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1409                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1410                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1411                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1412         }
1413 }
1414
1415 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1416
1417 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1418                                         unsigned long cr0,
1419                                         struct kvm_vcpu *vcpu)
1420 {
1421         if (!(cr0 & X86_CR0_PG)) {
1422                 /* From paging/starting to nonpaging */
1423                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1424                              vmcs_config.cpu_based_exec_ctrl |
1425                              (CPU_BASED_CR3_LOAD_EXITING |
1426                               CPU_BASED_CR3_STORE_EXITING));
1427                 vcpu->arch.cr0 = cr0;
1428                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1429                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1430                 *hw_cr0 &= ~X86_CR0_WP;
1431         } else if (!is_paging(vcpu)) {
1432                 /* From nonpaging to paging */
1433                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1434                              vmcs_config.cpu_based_exec_ctrl &
1435                              ~(CPU_BASED_CR3_LOAD_EXITING |
1436                                CPU_BASED_CR3_STORE_EXITING));
1437                 vcpu->arch.cr0 = cr0;
1438                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1440                         *hw_cr0 &= ~X86_CR0_WP;
1441         }
1442 }
1443
1444 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1445                                         struct kvm_vcpu *vcpu)
1446 {
1447         if (!is_paging(vcpu)) {
1448                 *hw_cr4 &= ~X86_CR4_PAE;
1449                 *hw_cr4 |= X86_CR4_PSE;
1450         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1451                 *hw_cr4 &= ~X86_CR4_PAE;
1452 }
1453
1454 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1455 {
1456         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1457                                 KVM_VM_CR0_ALWAYS_ON;
1458
1459         vmx_fpu_deactivate(vcpu);
1460
1461         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1462                 enter_pmode(vcpu);
1463
1464         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1465                 enter_rmode(vcpu);
1466
1467 #ifdef CONFIG_X86_64
1468         if (vcpu->arch.shadow_efer & EFER_LME) {
1469                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1470                         enter_lmode(vcpu);
1471                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1472                         exit_lmode(vcpu);
1473         }
1474 #endif
1475
1476         if (vm_need_ept())
1477                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1478
1479         vmcs_writel(CR0_READ_SHADOW, cr0);
1480         vmcs_writel(GUEST_CR0, hw_cr0);
1481         vcpu->arch.cr0 = cr0;
1482
1483         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1484                 vmx_fpu_activate(vcpu);
1485 }
1486
1487 static u64 construct_eptp(unsigned long root_hpa)
1488 {
1489         u64 eptp;
1490
1491         /* TODO write the value reading from MSR */
1492         eptp = VMX_EPT_DEFAULT_MT |
1493                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1494         eptp |= (root_hpa & PAGE_MASK);
1495
1496         return eptp;
1497 }
1498
1499 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1500 {
1501         unsigned long guest_cr3;
1502         u64 eptp;
1503
1504         guest_cr3 = cr3;
1505         if (vm_need_ept()) {
1506                 eptp = construct_eptp(cr3);
1507                 vmcs_write64(EPT_POINTER, eptp);
1508                 ept_sync_context(eptp);
1509                 ept_load_pdptrs(vcpu);
1510                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1511                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1512         }
1513
1514         vmx_flush_tlb(vcpu);
1515         vmcs_writel(GUEST_CR3, guest_cr3);
1516         if (vcpu->arch.cr0 & X86_CR0_PE)
1517                 vmx_fpu_deactivate(vcpu);
1518 }
1519
1520 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1521 {
1522         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1523                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1524
1525         vcpu->arch.cr4 = cr4;
1526         if (vm_need_ept())
1527                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1528
1529         vmcs_writel(CR4_READ_SHADOW, cr4);
1530         vmcs_writel(GUEST_CR4, hw_cr4);
1531 }
1532
1533 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1534 {
1535         struct vcpu_vmx *vmx = to_vmx(vcpu);
1536         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1537
1538         vcpu->arch.shadow_efer = efer;
1539         if (!msr)
1540                 return;
1541         if (efer & EFER_LMA) {
1542                 vmcs_write32(VM_ENTRY_CONTROLS,
1543                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1544                                      VM_ENTRY_IA32E_MODE);
1545                 msr->data = efer;
1546
1547         } else {
1548                 vmcs_write32(VM_ENTRY_CONTROLS,
1549                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1550                                      ~VM_ENTRY_IA32E_MODE);
1551
1552                 msr->data = efer & ~EFER_LME;
1553         }
1554         setup_msrs(vmx);
1555 }
1556
1557 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1558 {
1559         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1560
1561         return vmcs_readl(sf->base);
1562 }
1563
1564 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1565                             struct kvm_segment *var, int seg)
1566 {
1567         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1568         u32 ar;
1569
1570         var->base = vmcs_readl(sf->base);
1571         var->limit = vmcs_read32(sf->limit);
1572         var->selector = vmcs_read16(sf->selector);
1573         ar = vmcs_read32(sf->ar_bytes);
1574         if (ar & AR_UNUSABLE_MASK)
1575                 ar = 0;
1576         var->type = ar & 15;
1577         var->s = (ar >> 4) & 1;
1578         var->dpl = (ar >> 5) & 3;
1579         var->present = (ar >> 7) & 1;
1580         var->avl = (ar >> 12) & 1;
1581         var->l = (ar >> 13) & 1;
1582         var->db = (ar >> 14) & 1;
1583         var->g = (ar >> 15) & 1;
1584         var->unusable = (ar >> 16) & 1;
1585 }
1586
1587 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1588 {
1589         struct kvm_segment kvm_seg;
1590
1591         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1592                 return 0;
1593
1594         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1595                 return 3;
1596
1597         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1598         return kvm_seg.selector & 3;
1599 }
1600
1601 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1602 {
1603         u32 ar;
1604
1605         if (var->unusable)
1606                 ar = 1 << 16;
1607         else {
1608                 ar = var->type & 15;
1609                 ar |= (var->s & 1) << 4;
1610                 ar |= (var->dpl & 3) << 5;
1611                 ar |= (var->present & 1) << 7;
1612                 ar |= (var->avl & 1) << 12;
1613                 ar |= (var->l & 1) << 13;
1614                 ar |= (var->db & 1) << 14;
1615                 ar |= (var->g & 1) << 15;
1616         }
1617         if (ar == 0) /* a 0 value means unusable */
1618                 ar = AR_UNUSABLE_MASK;
1619
1620         return ar;
1621 }
1622
1623 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1624                             struct kvm_segment *var, int seg)
1625 {
1626         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1627         u32 ar;
1628
1629         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1630                 vcpu->arch.rmode.tr.selector = var->selector;
1631                 vcpu->arch.rmode.tr.base = var->base;
1632                 vcpu->arch.rmode.tr.limit = var->limit;
1633                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1634                 return;
1635         }
1636         vmcs_writel(sf->base, var->base);
1637         vmcs_write32(sf->limit, var->limit);
1638         vmcs_write16(sf->selector, var->selector);
1639         if (vcpu->arch.rmode.active && var->s) {
1640                 /*
1641                  * Hack real-mode segments into vm86 compatibility.
1642                  */
1643                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1644                         vmcs_writel(sf->base, 0xf0000);
1645                 ar = 0xf3;
1646         } else
1647                 ar = vmx_segment_access_rights(var);
1648         vmcs_write32(sf->ar_bytes, ar);
1649 }
1650
1651 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1652 {
1653         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1654
1655         *db = (ar >> 14) & 1;
1656         *l = (ar >> 13) & 1;
1657 }
1658
1659 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1660 {
1661         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1662         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1663 }
1664
1665 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1666 {
1667         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1668         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1669 }
1670
1671 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1672 {
1673         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1674         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1675 }
1676
1677 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1678 {
1679         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1680         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1681 }
1682
1683 static int init_rmode_tss(struct kvm *kvm)
1684 {
1685         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1686         u16 data = 0;
1687         int ret = 0;
1688         int r;
1689
1690         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1691         if (r < 0)
1692                 goto out;
1693         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1694         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1695         if (r < 0)
1696                 goto out;
1697         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1698         if (r < 0)
1699                 goto out;
1700         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1701         if (r < 0)
1702                 goto out;
1703         data = ~0;
1704         r = kvm_write_guest_page(kvm, fn, &data,
1705                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1706                                  sizeof(u8));
1707         if (r < 0)
1708                 goto out;
1709
1710         ret = 1;
1711 out:
1712         return ret;
1713 }
1714
1715 static int init_rmode_identity_map(struct kvm *kvm)
1716 {
1717         int i, r, ret;
1718         pfn_t identity_map_pfn;
1719         u32 tmp;
1720
1721         if (!vm_need_ept())
1722                 return 1;
1723         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1724                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1725                         "haven't been allocated!\n");
1726                 return 0;
1727         }
1728         if (likely(kvm->arch.ept_identity_pagetable_done))
1729                 return 1;
1730         ret = 0;
1731         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1732         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1733         if (r < 0)
1734                 goto out;
1735         /* Set up identity-mapping pagetable for EPT in real mode */
1736         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1737                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1738                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1739                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1740                                 &tmp, i * sizeof(tmp), sizeof(tmp));
1741                 if (r < 0)
1742                         goto out;
1743         }
1744         kvm->arch.ept_identity_pagetable_done = true;
1745         ret = 1;
1746 out:
1747         return ret;
1748 }
1749
1750 static void seg_setup(int seg)
1751 {
1752         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1753
1754         vmcs_write16(sf->selector, 0);
1755         vmcs_writel(sf->base, 0);
1756         vmcs_write32(sf->limit, 0xffff);
1757         vmcs_write32(sf->ar_bytes, 0x93);
1758 }
1759
1760 static int alloc_apic_access_page(struct kvm *kvm)
1761 {
1762         struct kvm_userspace_memory_region kvm_userspace_mem;
1763         int r = 0;
1764
1765         down_write(&kvm->slots_lock);
1766         if (kvm->arch.apic_access_page)
1767                 goto out;
1768         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1769         kvm_userspace_mem.flags = 0;
1770         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1771         kvm_userspace_mem.memory_size = PAGE_SIZE;
1772         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1773         if (r)
1774                 goto out;
1775
1776         down_read(&current->mm->mmap_sem);
1777         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1778         up_read(&current->mm->mmap_sem);
1779 out:
1780         up_write(&kvm->slots_lock);
1781         return r;
1782 }
1783
1784 static int alloc_identity_pagetable(struct kvm *kvm)
1785 {
1786         struct kvm_userspace_memory_region kvm_userspace_mem;
1787         int r = 0;
1788
1789         down_write(&kvm->slots_lock);
1790         if (kvm->arch.ept_identity_pagetable)
1791                 goto out;
1792         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1793         kvm_userspace_mem.flags = 0;
1794         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1795         kvm_userspace_mem.memory_size = PAGE_SIZE;
1796         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1797         if (r)
1798                 goto out;
1799
1800         down_read(&current->mm->mmap_sem);
1801         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1802                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1803         up_read(&current->mm->mmap_sem);
1804 out:
1805         up_write(&kvm->slots_lock);
1806         return r;
1807 }
1808
1809 static void allocate_vpid(struct vcpu_vmx *vmx)
1810 {
1811         int vpid;
1812
1813         vmx->vpid = 0;
1814         if (!enable_vpid || !cpu_has_vmx_vpid())
1815                 return;
1816         spin_lock(&vmx_vpid_lock);
1817         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1818         if (vpid < VMX_NR_VPIDS) {
1819                 vmx->vpid = vpid;
1820                 __set_bit(vpid, vmx_vpid_bitmap);
1821         }
1822         spin_unlock(&vmx_vpid_lock);
1823 }
1824
1825 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1826 {
1827         void *va;
1828
1829         if (!cpu_has_vmx_msr_bitmap())
1830                 return;
1831
1832         /*
1833          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1834          * have the write-low and read-high bitmap offsets the wrong way round.
1835          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1836          */
1837         va = kmap(msr_bitmap);
1838         if (msr <= 0x1fff) {
1839                 __clear_bit(msr, va + 0x000); /* read-low */
1840                 __clear_bit(msr, va + 0x800); /* write-low */
1841         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1842                 msr &= 0x1fff;
1843                 __clear_bit(msr, va + 0x400); /* read-high */
1844                 __clear_bit(msr, va + 0xc00); /* write-high */
1845         }
1846         kunmap(msr_bitmap);
1847 }
1848
1849 /*
1850  * Sets up the vmcs for emulated real mode.
1851  */
1852 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1853 {
1854         u32 host_sysenter_cs;
1855         u32 junk;
1856         unsigned long a;
1857         struct descriptor_table dt;
1858         int i;
1859         unsigned long kvm_vmx_return;
1860         u32 exec_control;
1861
1862         /* I/O */
1863         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1864         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1865
1866         if (cpu_has_vmx_msr_bitmap())
1867                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1868
1869         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1870
1871         /* Control */
1872         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1873                 vmcs_config.pin_based_exec_ctrl);
1874
1875         exec_control = vmcs_config.cpu_based_exec_ctrl;
1876         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1877                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1878 #ifdef CONFIG_X86_64
1879                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1880                                 CPU_BASED_CR8_LOAD_EXITING;
1881 #endif
1882         }
1883         if (!vm_need_ept())
1884                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1885                                 CPU_BASED_CR3_LOAD_EXITING;
1886         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1887
1888         if (cpu_has_secondary_exec_ctrls()) {
1889                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1890                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1891                         exec_control &=
1892                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1893                 if (vmx->vpid == 0)
1894                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1895                 if (!vm_need_ept())
1896                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
1897                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1898         }
1899
1900         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1901         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1902         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1903
1904         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1905         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1906         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1907
1908         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1909         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1910         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1911         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1912         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1913         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1914 #ifdef CONFIG_X86_64
1915         rdmsrl(MSR_FS_BASE, a);
1916         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1917         rdmsrl(MSR_GS_BASE, a);
1918         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1919 #else
1920         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1921         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1922 #endif
1923
1924         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1925
1926         get_idt(&dt);
1927         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1928
1929         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1930         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1931         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1932         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1933         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1934
1935         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1936         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1937         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1938         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1939         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1940         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1941
1942         for (i = 0; i < NR_VMX_MSR; ++i) {
1943                 u32 index = vmx_msr_index[i];
1944                 u32 data_low, data_high;
1945                 u64 data;
1946                 int j = vmx->nmsrs;
1947
1948                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1949                         continue;
1950                 if (wrmsr_safe(index, data_low, data_high) < 0)
1951                         continue;
1952                 data = data_low | ((u64)data_high << 32);
1953                 vmx->host_msrs[j].index = index;
1954                 vmx->host_msrs[j].reserved = 0;
1955                 vmx->host_msrs[j].data = data;
1956                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1957                 ++vmx->nmsrs;
1958         }
1959
1960         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1961
1962         /* 22.2.1, 20.8.1 */
1963         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1964
1965         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1966         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1967
1968
1969         return 0;
1970 }
1971
1972 static int init_rmode(struct kvm *kvm)
1973 {
1974         if (!init_rmode_tss(kvm))
1975                 return 0;
1976         if (!init_rmode_identity_map(kvm))
1977                 return 0;
1978         return 1;
1979 }
1980
1981 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1982 {
1983         struct vcpu_vmx *vmx = to_vmx(vcpu);
1984         u64 msr;
1985         int ret;
1986
1987         down_read(&vcpu->kvm->slots_lock);
1988         if (!init_rmode(vmx->vcpu.kvm)) {
1989                 ret = -ENOMEM;
1990                 goto out;
1991         }
1992
1993         vmx->vcpu.arch.rmode.active = 0;
1994
1995         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1996         kvm_set_cr8(&vmx->vcpu, 0);
1997         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1998         if (vmx->vcpu.vcpu_id == 0)
1999                 msr |= MSR_IA32_APICBASE_BSP;
2000         kvm_set_apic_base(&vmx->vcpu, msr);
2001
2002         fx_init(&vmx->vcpu);
2003
2004         /*
2005          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2006          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2007          */
2008         if (vmx->vcpu.vcpu_id == 0) {
2009                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2010                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2011         } else {
2012                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2013                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2014         }
2015         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2016         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2017
2018         seg_setup(VCPU_SREG_DS);
2019         seg_setup(VCPU_SREG_ES);
2020         seg_setup(VCPU_SREG_FS);
2021         seg_setup(VCPU_SREG_GS);
2022         seg_setup(VCPU_SREG_SS);
2023
2024         vmcs_write16(GUEST_TR_SELECTOR, 0);
2025         vmcs_writel(GUEST_TR_BASE, 0);
2026         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2027         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2028
2029         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2030         vmcs_writel(GUEST_LDTR_BASE, 0);
2031         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2032         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2033
2034         vmcs_write32(GUEST_SYSENTER_CS, 0);
2035         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2036         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2037
2038         vmcs_writel(GUEST_RFLAGS, 0x02);
2039         if (vmx->vcpu.vcpu_id == 0)
2040                 vmcs_writel(GUEST_RIP, 0xfff0);
2041         else
2042                 vmcs_writel(GUEST_RIP, 0);
2043         vmcs_writel(GUEST_RSP, 0);
2044
2045         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2046         vmcs_writel(GUEST_DR7, 0x400);
2047
2048         vmcs_writel(GUEST_GDTR_BASE, 0);
2049         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2050
2051         vmcs_writel(GUEST_IDTR_BASE, 0);
2052         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2053
2054         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2055         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2056         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2057
2058         guest_write_tsc(0);
2059
2060         /* Special registers */
2061         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2062
2063         setup_msrs(vmx);
2064
2065         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2066
2067         if (cpu_has_vmx_tpr_shadow()) {
2068                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2069                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2070                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2071                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2072                 vmcs_write32(TPR_THRESHOLD, 0);
2073         }
2074
2075         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2076                 vmcs_write64(APIC_ACCESS_ADDR,
2077                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2078
2079         if (vmx->vpid != 0)
2080                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2081
2082         vmx->vcpu.arch.cr0 = 0x60000010;
2083         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2084         vmx_set_cr4(&vmx->vcpu, 0);
2085         vmx_set_efer(&vmx->vcpu, 0);
2086         vmx_fpu_activate(&vmx->vcpu);
2087         update_exception_bitmap(&vmx->vcpu);
2088
2089         vpid_sync_vcpu_all(vmx);
2090
2091         ret = 0;
2092
2093 out:
2094         up_read(&vcpu->kvm->slots_lock);
2095         return ret;
2096 }
2097
2098 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2099 {
2100         struct vcpu_vmx *vmx = to_vmx(vcpu);
2101
2102         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2103
2104         if (vcpu->arch.rmode.active) {
2105                 vmx->rmode.irq.pending = true;
2106                 vmx->rmode.irq.vector = irq;
2107                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
2108                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2109                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2110                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2111                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
2112                 return;
2113         }
2114         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2115                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2116 }
2117
2118 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2119 {
2120         int word_index = __ffs(vcpu->arch.irq_summary);
2121         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2122         int irq = word_index * BITS_PER_LONG + bit_index;
2123
2124         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2125         if (!vcpu->arch.irq_pending[word_index])
2126                 clear_bit(word_index, &vcpu->arch.irq_summary);
2127         vmx_inject_irq(vcpu, irq);
2128 }
2129
2130
2131 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2132                                        struct kvm_run *kvm_run)
2133 {
2134         u32 cpu_based_vm_exec_control;
2135
2136         vcpu->arch.interrupt_window_open =
2137                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2138                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2139
2140         if (vcpu->arch.interrupt_window_open &&
2141             vcpu->arch.irq_summary &&
2142             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
2143                 /*
2144                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2145                  */
2146                 kvm_do_inject_irq(vcpu);
2147
2148         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2149         if (!vcpu->arch.interrupt_window_open &&
2150             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2151                 /*
2152                  * Interrupts blocked.  Wait for unblock.
2153                  */
2154                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2155         else
2156                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2157         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2158 }
2159
2160 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2161 {
2162         int ret;
2163         struct kvm_userspace_memory_region tss_mem = {
2164                 .slot = 8,
2165                 .guest_phys_addr = addr,
2166                 .memory_size = PAGE_SIZE * 3,
2167                 .flags = 0,
2168         };
2169
2170         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2171         if (ret)
2172                 return ret;
2173         kvm->arch.tss_addr = addr;
2174         return 0;
2175 }
2176
2177 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2178 {
2179         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2180
2181         set_debugreg(dbg->bp[0], 0);
2182         set_debugreg(dbg->bp[1], 1);
2183         set_debugreg(dbg->bp[2], 2);
2184         set_debugreg(dbg->bp[3], 3);
2185
2186         if (dbg->singlestep) {
2187                 unsigned long flags;
2188
2189                 flags = vmcs_readl(GUEST_RFLAGS);
2190                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2191                 vmcs_writel(GUEST_RFLAGS, flags);
2192         }
2193 }
2194
2195 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2196                                   int vec, u32 err_code)
2197 {
2198         if (!vcpu->arch.rmode.active)
2199                 return 0;
2200
2201         /*
2202          * Instruction with address size override prefix opcode 0x67
2203          * Cause the #SS fault with 0 error code in VM86 mode.
2204          */
2205         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2206                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2207                         return 1;
2208         return 0;
2209 }
2210
2211 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2212 {
2213         struct vcpu_vmx *vmx = to_vmx(vcpu);
2214         u32 intr_info, error_code;
2215         unsigned long cr2, rip;
2216         u32 vect_info;
2217         enum emulation_result er;
2218
2219         vect_info = vmx->idt_vectoring_info;
2220         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2221
2222         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2223                                                 !is_page_fault(intr_info))
2224                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2225                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2226
2227         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2228                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2229                 set_bit(irq, vcpu->arch.irq_pending);
2230                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2231         }
2232
2233         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2234                 return 1;  /* already handled by vmx_vcpu_run() */
2235
2236         if (is_no_device(intr_info)) {
2237                 vmx_fpu_activate(vcpu);
2238                 return 1;
2239         }
2240
2241         if (is_invalid_opcode(intr_info)) {
2242                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2243                 if (er != EMULATE_DONE)
2244                         kvm_queue_exception(vcpu, UD_VECTOR);
2245                 return 1;
2246         }
2247
2248         error_code = 0;
2249         rip = vmcs_readl(GUEST_RIP);
2250         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2251                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2252         if (is_page_fault(intr_info)) {
2253                 /* EPT won't cause page fault directly */
2254                 if (vm_need_ept())
2255                         BUG();
2256                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2257                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2258                             (u32)((u64)cr2 >> 32), handler);
2259                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2260         }
2261
2262         if (vcpu->arch.rmode.active &&
2263             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2264                                                                 error_code)) {
2265                 if (vcpu->arch.halt_request) {
2266                         vcpu->arch.halt_request = 0;
2267                         return kvm_emulate_halt(vcpu);
2268                 }
2269                 return 1;
2270         }
2271
2272         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2273             (INTR_TYPE_EXCEPTION | 1)) {
2274                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2275                 return 0;
2276         }
2277         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2278         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2279         kvm_run->ex.error_code = error_code;
2280         return 0;
2281 }
2282
2283 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2284                                      struct kvm_run *kvm_run)
2285 {
2286         ++vcpu->stat.irq_exits;
2287         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2288         return 1;
2289 }
2290
2291 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2292 {
2293         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2294         return 0;
2295 }
2296
2297 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2298 {
2299         unsigned long exit_qualification;
2300         int size, down, in, string, rep;
2301         unsigned port;
2302
2303         ++vcpu->stat.io_exits;
2304         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2305         string = (exit_qualification & 16) != 0;
2306
2307         if (string) {
2308                 if (emulate_instruction(vcpu,
2309                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2310                         return 0;
2311                 return 1;
2312         }
2313
2314         size = (exit_qualification & 7) + 1;
2315         in = (exit_qualification & 8) != 0;
2316         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2317         rep = (exit_qualification & 32) != 0;
2318         port = exit_qualification >> 16;
2319
2320         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2321 }
2322
2323 static void
2324 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2325 {
2326         /*
2327          * Patch in the VMCALL instruction:
2328          */
2329         hypercall[0] = 0x0f;
2330         hypercall[1] = 0x01;
2331         hypercall[2] = 0xc1;
2332 }
2333
2334 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2335 {
2336         unsigned long exit_qualification;
2337         int cr;
2338         int reg;
2339
2340         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2341         cr = exit_qualification & 15;
2342         reg = (exit_qualification >> 8) & 15;
2343         switch ((exit_qualification >> 4) & 3) {
2344         case 0: /* mov to cr */
2345                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2346                             (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
2347                 switch (cr) {
2348                 case 0:
2349                         vcpu_load_rsp_rip(vcpu);
2350                         kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2351                         skip_emulated_instruction(vcpu);
2352                         return 1;
2353                 case 3:
2354                         vcpu_load_rsp_rip(vcpu);
2355                         kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2356                         skip_emulated_instruction(vcpu);
2357                         return 1;
2358                 case 4:
2359                         vcpu_load_rsp_rip(vcpu);
2360                         kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2361                         skip_emulated_instruction(vcpu);
2362                         return 1;
2363                 case 8:
2364                         vcpu_load_rsp_rip(vcpu);
2365                         kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2366                         skip_emulated_instruction(vcpu);
2367                         if (irqchip_in_kernel(vcpu->kvm))
2368                                 return 1;
2369                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2370                         return 0;
2371                 };
2372                 break;
2373         case 2: /* clts */
2374                 vcpu_load_rsp_rip(vcpu);
2375                 vmx_fpu_deactivate(vcpu);
2376                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2377                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2378                 vmx_fpu_activate(vcpu);
2379                 KVMTRACE_0D(CLTS, vcpu, handler);
2380                 skip_emulated_instruction(vcpu);
2381                 return 1;
2382         case 1: /*mov from cr*/
2383                 switch (cr) {
2384                 case 3:
2385                         vcpu_load_rsp_rip(vcpu);
2386                         vcpu->arch.regs[reg] = vcpu->arch.cr3;
2387                         vcpu_put_rsp_rip(vcpu);
2388                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2389                                     (u32)vcpu->arch.regs[reg],
2390                                     (u32)((u64)vcpu->arch.regs[reg] >> 32),
2391                                     handler);
2392                         skip_emulated_instruction(vcpu);
2393                         return 1;
2394                 case 8:
2395                         vcpu_load_rsp_rip(vcpu);
2396                         vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2397                         vcpu_put_rsp_rip(vcpu);
2398                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2399                                     (u32)vcpu->arch.regs[reg], handler);
2400                         skip_emulated_instruction(vcpu);
2401                         return 1;
2402                 }
2403                 break;
2404         case 3: /* lmsw */
2405                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2406
2407                 skip_emulated_instruction(vcpu);
2408                 return 1;
2409         default:
2410                 break;
2411         }
2412         kvm_run->exit_reason = 0;
2413         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2414                (int)(exit_qualification >> 4) & 3, cr);
2415         return 0;
2416 }
2417
2418 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2419 {
2420         unsigned long exit_qualification;
2421         unsigned long val;
2422         int dr, reg;
2423
2424         /*
2425          * FIXME: this code assumes the host is debugging the guest.
2426          *        need to deal with guest debugging itself too.
2427          */
2428         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2429         dr = exit_qualification & 7;
2430         reg = (exit_qualification >> 8) & 15;
2431         vcpu_load_rsp_rip(vcpu);
2432         if (exit_qualification & 16) {
2433                 /* mov from dr */
2434                 switch (dr) {
2435                 case 6:
2436                         val = 0xffff0ff0;
2437                         break;
2438                 case 7:
2439                         val = 0x400;
2440                         break;
2441                 default:
2442                         val = 0;
2443                 }
2444                 vcpu->arch.regs[reg] = val;
2445                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2446         } else {
2447                 /* mov to dr */
2448         }
2449         vcpu_put_rsp_rip(vcpu);
2450         skip_emulated_instruction(vcpu);
2451         return 1;
2452 }
2453
2454 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2455 {
2456         kvm_emulate_cpuid(vcpu);
2457         return 1;
2458 }
2459
2460 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2461 {
2462         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2463         u64 data;
2464
2465         if (vmx_get_msr(vcpu, ecx, &data)) {
2466                 kvm_inject_gp(vcpu, 0);
2467                 return 1;
2468         }
2469
2470         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2471                     handler);
2472
2473         /* FIXME: handling of bits 32:63 of rax, rdx */
2474         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2475         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2476         skip_emulated_instruction(vcpu);
2477         return 1;
2478 }
2479
2480 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2481 {
2482         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2483         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2484                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2485
2486         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2487                     handler);
2488
2489         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2490                 kvm_inject_gp(vcpu, 0);
2491                 return 1;
2492         }
2493
2494         skip_emulated_instruction(vcpu);
2495         return 1;
2496 }
2497
2498 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2499                                       struct kvm_run *kvm_run)
2500 {
2501         return 1;
2502 }
2503
2504 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2505                                    struct kvm_run *kvm_run)
2506 {
2507         u32 cpu_based_vm_exec_control;
2508
2509         /* clear pending irq */
2510         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2511         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2512         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2513
2514         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2515
2516         /*
2517          * If the user space waits to inject interrupts, exit as soon as
2518          * possible
2519          */
2520         if (kvm_run->request_interrupt_window &&
2521             !vcpu->arch.irq_summary) {
2522                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2523                 ++vcpu->stat.irq_window_exits;
2524                 return 0;
2525         }
2526         return 1;
2527 }
2528
2529 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2530 {
2531         skip_emulated_instruction(vcpu);
2532         return kvm_emulate_halt(vcpu);
2533 }
2534
2535 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2536 {
2537         skip_emulated_instruction(vcpu);
2538         kvm_emulate_hypercall(vcpu);
2539         return 1;
2540 }
2541
2542 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2543 {
2544         skip_emulated_instruction(vcpu);
2545         /* TODO: Add support for VT-d/pass-through device */
2546         return 1;
2547 }
2548
2549 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2550 {
2551         u64 exit_qualification;
2552         enum emulation_result er;
2553         unsigned long offset;
2554
2555         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2556         offset = exit_qualification & 0xffful;
2557
2558         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2559
2560         if (er !=  EMULATE_DONE) {
2561                 printk(KERN_ERR
2562                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2563                        offset);
2564                 return -ENOTSUPP;
2565         }
2566         return 1;
2567 }
2568
2569 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2570 {
2571         unsigned long exit_qualification;
2572         u16 tss_selector;
2573         int reason;
2574
2575         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2576
2577         reason = (u32)exit_qualification >> 30;
2578         tss_selector = exit_qualification;
2579
2580         return kvm_task_switch(vcpu, tss_selector, reason);
2581 }
2582
2583 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2584 {
2585         u64 exit_qualification;
2586         enum emulation_result er;
2587         gpa_t gpa;
2588         unsigned long hva;
2589         int gla_validity;
2590         int r;
2591
2592         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2593
2594         if (exit_qualification & (1 << 6)) {
2595                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2596                 return -ENOTSUPP;
2597         }
2598
2599         gla_validity = (exit_qualification >> 7) & 0x3;
2600         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2601                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2602                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2603                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2604                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2605                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2606                         (long unsigned int)exit_qualification);
2607                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2608                 kvm_run->hw.hardware_exit_reason = 0;
2609                 return -ENOTSUPP;
2610         }
2611
2612         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2613         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2614         if (!kvm_is_error_hva(hva)) {
2615                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2616                 if (r < 0) {
2617                         printk(KERN_ERR "EPT: Not enough memory!\n");
2618                         return -ENOMEM;
2619                 }
2620                 return 1;
2621         } else {
2622                 /* must be MMIO */
2623                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2624
2625                 if (er == EMULATE_FAIL) {
2626                         printk(KERN_ERR
2627                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2628                          er);
2629                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2630                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2631                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2632                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2633                                 (long unsigned int)exit_qualification);
2634                         return -ENOTSUPP;
2635                 } else if (er == EMULATE_DO_MMIO)
2636                         return 0;
2637         }
2638         return 1;
2639 }
2640
2641 /*
2642  * The exit handlers return 1 if the exit was handled fully and guest execution
2643  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2644  * to be done to userspace and return 0.
2645  */
2646 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2647                                       struct kvm_run *kvm_run) = {
2648         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2649         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2650         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2651         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2652         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2653         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2654         [EXIT_REASON_CPUID]                   = handle_cpuid,
2655         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2656         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2657         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2658         [EXIT_REASON_HLT]                     = handle_halt,
2659         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2660         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2661         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2662         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2663         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
2664         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
2665 };
2666
2667 static const int kvm_vmx_max_exit_handlers =
2668         ARRAY_SIZE(kvm_vmx_exit_handlers);
2669
2670 /*
2671  * The guest has exited.  See if we can fix it or if we need userspace
2672  * assistance.
2673  */
2674 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2675 {
2676         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2677         struct vcpu_vmx *vmx = to_vmx(vcpu);
2678         u32 vectoring_info = vmx->idt_vectoring_info;
2679
2680         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2681                     (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2682
2683         /* Access CR3 don't cause VMExit in paging mode, so we need
2684          * to sync with guest real CR3. */
2685         if (vm_need_ept() && is_paging(vcpu)) {
2686                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2687                 ept_load_pdptrs(vcpu);
2688         }
2689
2690         if (unlikely(vmx->fail)) {
2691                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2692                 kvm_run->fail_entry.hardware_entry_failure_reason
2693                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2694                 return 0;
2695         }
2696
2697         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2698                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2699                         exit_reason != EXIT_REASON_EPT_VIOLATION))
2700                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2701                        "exit reason is 0x%x\n", __func__, exit_reason);
2702         if (exit_reason < kvm_vmx_max_exit_handlers
2703             && kvm_vmx_exit_handlers[exit_reason])
2704                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2705         else {
2706                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2707                 kvm_run->hw.hardware_exit_reason = exit_reason;
2708         }
2709         return 0;
2710 }
2711
2712 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2713 {
2714         int max_irr, tpr;
2715
2716         if (!vm_need_tpr_shadow(vcpu->kvm))
2717                 return;
2718
2719         if (!kvm_lapic_enabled(vcpu) ||
2720             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2721                 vmcs_write32(TPR_THRESHOLD, 0);
2722                 return;
2723         }
2724
2725         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2726         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2727 }
2728
2729 static void enable_irq_window(struct kvm_vcpu *vcpu)
2730 {
2731         u32 cpu_based_vm_exec_control;
2732
2733         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2734         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2735         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2736 }
2737
2738 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2739 {
2740         struct vcpu_vmx *vmx = to_vmx(vcpu);
2741         u32 idtv_info_field, intr_info_field;
2742         int has_ext_irq, interrupt_window_open;
2743         int vector;
2744
2745         update_tpr_threshold(vcpu);
2746
2747         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2748         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2749         idtv_info_field = vmx->idt_vectoring_info;
2750         if (intr_info_field & INTR_INFO_VALID_MASK) {
2751                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2752                         /* TODO: fault when IDT_Vectoring */
2753                         if (printk_ratelimit())
2754                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2755                 }
2756                 if (has_ext_irq)
2757                         enable_irq_window(vcpu);
2758                 return;
2759         }
2760         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2761                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2762                     == INTR_TYPE_EXT_INTR
2763                     && vcpu->arch.rmode.active) {
2764                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2765
2766                         vmx_inject_irq(vcpu, vect);
2767                         if (unlikely(has_ext_irq))
2768                                 enable_irq_window(vcpu);
2769                         return;
2770                 }
2771
2772                 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2773
2774                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2775                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2776                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2777
2778                 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2779                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2780                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2781                 if (unlikely(has_ext_irq))
2782                         enable_irq_window(vcpu);
2783                 return;
2784         }
2785         if (!has_ext_irq)
2786                 return;
2787         interrupt_window_open =
2788                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2789                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2790         if (interrupt_window_open) {
2791                 vector = kvm_cpu_get_interrupt(vcpu);
2792                 vmx_inject_irq(vcpu, vector);
2793                 kvm_timer_intr_post(vcpu, vector);
2794         } else
2795                 enable_irq_window(vcpu);
2796 }
2797
2798 /*
2799  * Failure to inject an interrupt should give us the information
2800  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2801  * when fetching the interrupt redirection bitmap in the real-mode
2802  * tss, this doesn't happen.  So we do it ourselves.
2803  */
2804 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2805 {
2806         vmx->rmode.irq.pending = 0;
2807         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2808                 return;
2809         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2810         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2811                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2812                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2813                 return;
2814         }
2815         vmx->idt_vectoring_info =
2816                 VECTORING_INFO_VALID_MASK
2817                 | INTR_TYPE_EXT_INTR
2818                 | vmx->rmode.irq.vector;
2819 }
2820
2821 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2822 {
2823         struct vcpu_vmx *vmx = to_vmx(vcpu);
2824         u32 intr_info;
2825
2826         /*
2827          * Loading guest fpu may have cleared host cr0.ts
2828          */
2829         vmcs_writel(HOST_CR0, read_cr0());
2830
2831         asm(
2832                 /* Store host registers */
2833 #ifdef CONFIG_X86_64
2834                 "push %%rdx; push %%rbp;"
2835                 "push %%rcx \n\t"
2836 #else
2837                 "push %%edx; push %%ebp;"
2838                 "push %%ecx \n\t"
2839 #endif
2840                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
2841                 /* Check if vmlaunch of vmresume is needed */
2842                 "cmpl $0, %c[launched](%0) \n\t"
2843                 /* Load guest registers.  Don't clobber flags. */
2844 #ifdef CONFIG_X86_64
2845                 "mov %c[cr2](%0), %%rax \n\t"
2846                 "mov %%rax, %%cr2 \n\t"
2847                 "mov %c[rax](%0), %%rax \n\t"
2848                 "mov %c[rbx](%0), %%rbx \n\t"
2849                 "mov %c[rdx](%0), %%rdx \n\t"
2850                 "mov %c[rsi](%0), %%rsi \n\t"
2851                 "mov %c[rdi](%0), %%rdi \n\t"
2852                 "mov %c[rbp](%0), %%rbp \n\t"
2853                 "mov %c[r8](%0),  %%r8  \n\t"
2854                 "mov %c[r9](%0),  %%r9  \n\t"
2855                 "mov %c[r10](%0), %%r10 \n\t"
2856                 "mov %c[r11](%0), %%r11 \n\t"
2857                 "mov %c[r12](%0), %%r12 \n\t"
2858                 "mov %c[r13](%0), %%r13 \n\t"
2859                 "mov %c[r14](%0), %%r14 \n\t"
2860                 "mov %c[r15](%0), %%r15 \n\t"
2861                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2862 #else
2863                 "mov %c[cr2](%0), %%eax \n\t"
2864                 "mov %%eax,   %%cr2 \n\t"
2865                 "mov %c[rax](%0), %%eax \n\t"
2866                 "mov %c[rbx](%0), %%ebx \n\t"
2867                 "mov %c[rdx](%0), %%edx \n\t"
2868                 "mov %c[rsi](%0), %%esi \n\t"
2869                 "mov %c[rdi](%0), %%edi \n\t"
2870                 "mov %c[rbp](%0), %%ebp \n\t"
2871                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2872 #endif
2873                 /* Enter guest mode */
2874                 "jne .Llaunched \n\t"
2875                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
2876                 "jmp .Lkvm_vmx_return \n\t"
2877                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
2878                 ".Lkvm_vmx_return: "
2879                 /* Save guest registers, load host registers, keep flags */
2880 #ifdef CONFIG_X86_64
2881                 "xchg %0,     (%%rsp) \n\t"
2882                 "mov %%rax, %c[rax](%0) \n\t"
2883                 "mov %%rbx, %c[rbx](%0) \n\t"
2884                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2885                 "mov %%rdx, %c[rdx](%0) \n\t"
2886                 "mov %%rsi, %c[rsi](%0) \n\t"
2887                 "mov %%rdi, %c[rdi](%0) \n\t"
2888                 "mov %%rbp, %c[rbp](%0) \n\t"
2889                 "mov %%r8,  %c[r8](%0) \n\t"
2890                 "mov %%r9,  %c[r9](%0) \n\t"
2891                 "mov %%r10, %c[r10](%0) \n\t"
2892                 "mov %%r11, %c[r11](%0) \n\t"
2893                 "mov %%r12, %c[r12](%0) \n\t"
2894                 "mov %%r13, %c[r13](%0) \n\t"
2895                 "mov %%r14, %c[r14](%0) \n\t"
2896                 "mov %%r15, %c[r15](%0) \n\t"
2897                 "mov %%cr2, %%rax   \n\t"
2898                 "mov %%rax, %c[cr2](%0) \n\t"
2899
2900                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2901 #else
2902                 "xchg %0, (%%esp) \n\t"
2903                 "mov %%eax, %c[rax](%0) \n\t"
2904                 "mov %%ebx, %c[rbx](%0) \n\t"
2905                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2906                 "mov %%edx, %c[rdx](%0) \n\t"
2907                 "mov %%esi, %c[rsi](%0) \n\t"
2908                 "mov %%edi, %c[rdi](%0) \n\t"
2909                 "mov %%ebp, %c[rbp](%0) \n\t"
2910                 "mov %%cr2, %%eax  \n\t"
2911                 "mov %%eax, %c[cr2](%0) \n\t"
2912
2913                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2914 #endif
2915                 "setbe %c[fail](%0) \n\t"
2916               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2917                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2918                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2919                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2920                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2921                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2922                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2923                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2924                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2925                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2926 #ifdef CONFIG_X86_64
2927                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2928                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2929                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2930                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2931                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2932                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2933                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2934                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2935 #endif
2936                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2937               : "cc", "memory"
2938 #ifdef CONFIG_X86_64
2939                 , "rbx", "rdi", "rsi"
2940                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2941 #else
2942                 , "ebx", "edi", "rsi"
2943 #endif
2944               );
2945
2946         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2947         if (vmx->rmode.irq.pending)
2948                 fixup_rmode_irq(vmx);
2949
2950         vcpu->arch.interrupt_window_open =
2951                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2952
2953         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2954         vmx->launched = 1;
2955
2956         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2957
2958         /* We need to handle NMIs before interrupts are enabled */
2959         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
2960                 KVMTRACE_0D(NMI, vcpu, handler);
2961                 asm("int $2");
2962         }
2963 }
2964
2965 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2966 {
2967         struct vcpu_vmx *vmx = to_vmx(vcpu);
2968
2969         if (vmx->vmcs) {
2970                 on_each_cpu(__vcpu_clear, vmx, 1);
2971                 free_vmcs(vmx->vmcs);
2972                 vmx->vmcs = NULL;
2973         }
2974 }
2975
2976 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2977 {
2978         struct vcpu_vmx *vmx = to_vmx(vcpu);
2979
2980         spin_lock(&vmx_vpid_lock);
2981         if (vmx->vpid != 0)
2982                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2983         spin_unlock(&vmx_vpid_lock);
2984         vmx_free_vmcs(vcpu);
2985         kfree(vmx->host_msrs);
2986         kfree(vmx->guest_msrs);
2987         kvm_vcpu_uninit(vcpu);
2988         kmem_cache_free(kvm_vcpu_cache, vmx);
2989 }
2990
2991 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2992 {
2993         int err;
2994         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2995         int cpu;
2996
2997         if (!vmx)
2998                 return ERR_PTR(-ENOMEM);
2999
3000         allocate_vpid(vmx);
3001         if (id == 0 && vm_need_ept()) {
3002                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3003                         VMX_EPT_WRITABLE_MASK |
3004                         VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3005                 kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
3006                                 VMX_EPT_FAKE_DIRTY_MASK, 0ull,
3007                                 VMX_EPT_EXECUTABLE_MASK);
3008                 kvm_enable_tdp();
3009         }
3010
3011         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3012         if (err)
3013                 goto free_vcpu;
3014
3015         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3016         if (!vmx->guest_msrs) {
3017                 err = -ENOMEM;
3018                 goto uninit_vcpu;
3019         }
3020
3021         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3022         if (!vmx->host_msrs)
3023                 goto free_guest_msrs;
3024
3025         vmx->vmcs = alloc_vmcs();
3026         if (!vmx->vmcs)
3027                 goto free_msrs;
3028
3029         vmcs_clear(vmx->vmcs);
3030
3031         cpu = get_cpu();
3032         vmx_vcpu_load(&vmx->vcpu, cpu);
3033         err = vmx_vcpu_setup(vmx);
3034         vmx_vcpu_put(&vmx->vcpu);
3035         put_cpu();
3036         if (err)
3037                 goto free_vmcs;
3038         if (vm_need_virtualize_apic_accesses(kvm))
3039                 if (alloc_apic_access_page(kvm) != 0)
3040                         goto free_vmcs;
3041
3042         if (vm_need_ept())
3043                 if (alloc_identity_pagetable(kvm) != 0)
3044                         goto free_vmcs;
3045
3046         return &vmx->vcpu;
3047
3048 free_vmcs:
3049         free_vmcs(vmx->vmcs);
3050 free_msrs:
3051         kfree(vmx->host_msrs);
3052 free_guest_msrs:
3053         kfree(vmx->guest_msrs);
3054 uninit_vcpu:
3055         kvm_vcpu_uninit(&vmx->vcpu);
3056 free_vcpu:
3057         kmem_cache_free(kvm_vcpu_cache, vmx);
3058         return ERR_PTR(err);
3059 }
3060
3061 static void __init vmx_check_processor_compat(void *rtn)
3062 {
3063         struct vmcs_config vmcs_conf;
3064
3065         *(int *)rtn = 0;
3066         if (setup_vmcs_config(&vmcs_conf) < 0)
3067                 *(int *)rtn = -EIO;
3068         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3069                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3070                                 smp_processor_id());
3071                 *(int *)rtn = -EIO;
3072         }
3073 }
3074
3075 static int get_ept_level(void)
3076 {
3077         return VMX_EPT_DEFAULT_GAW + 1;
3078 }
3079
3080 static struct kvm_x86_ops vmx_x86_ops = {
3081         .cpu_has_kvm_support = cpu_has_kvm_support,
3082         .disabled_by_bios = vmx_disabled_by_bios,
3083         .hardware_setup = hardware_setup,
3084         .hardware_unsetup = hardware_unsetup,
3085         .check_processor_compatibility = vmx_check_processor_compat,
3086         .hardware_enable = hardware_enable,
3087         .hardware_disable = hardware_disable,
3088         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3089
3090         .vcpu_create = vmx_create_vcpu,
3091         .vcpu_free = vmx_free_vcpu,
3092         .vcpu_reset = vmx_vcpu_reset,
3093
3094         .prepare_guest_switch = vmx_save_host_state,
3095         .vcpu_load = vmx_vcpu_load,
3096         .vcpu_put = vmx_vcpu_put,
3097         .vcpu_decache = vmx_vcpu_decache,
3098
3099         .set_guest_debug = set_guest_debug,
3100         .guest_debug_pre = kvm_guest_debug_pre,
3101         .get_msr = vmx_get_msr,
3102         .set_msr = vmx_set_msr,
3103         .get_segment_base = vmx_get_segment_base,
3104         .get_segment = vmx_get_segment,
3105         .set_segment = vmx_set_segment,
3106         .get_cpl = vmx_get_cpl,
3107         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3108         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3109         .set_cr0 = vmx_set_cr0,
3110         .set_cr3 = vmx_set_cr3,
3111         .set_cr4 = vmx_set_cr4,
3112         .set_efer = vmx_set_efer,
3113         .get_idt = vmx_get_idt,
3114         .set_idt = vmx_set_idt,
3115         .get_gdt = vmx_get_gdt,
3116         .set_gdt = vmx_set_gdt,
3117         .cache_regs = vcpu_load_rsp_rip,
3118         .decache_regs = vcpu_put_rsp_rip,
3119         .get_rflags = vmx_get_rflags,
3120         .set_rflags = vmx_set_rflags,
3121
3122         .tlb_flush = vmx_flush_tlb,
3123
3124         .run = vmx_vcpu_run,
3125         .handle_exit = kvm_handle_exit,
3126         .skip_emulated_instruction = skip_emulated_instruction,
3127         .patch_hypercall = vmx_patch_hypercall,
3128         .get_irq = vmx_get_irq,
3129         .set_irq = vmx_inject_irq,
3130         .queue_exception = vmx_queue_exception,
3131         .exception_injected = vmx_exception_injected,
3132         .inject_pending_irq = vmx_intr_assist,
3133         .inject_pending_vectors = do_interrupt_requests,
3134
3135         .set_tss_addr = vmx_set_tss_addr,
3136         .get_tdp_level = get_ept_level,
3137 };
3138
3139 static int __init vmx_init(void)
3140 {
3141         void *va;
3142         int r;
3143
3144         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3145         if (!vmx_io_bitmap_a)
3146                 return -ENOMEM;
3147
3148         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3149         if (!vmx_io_bitmap_b) {
3150                 r = -ENOMEM;
3151                 goto out;
3152         }
3153
3154         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3155         if (!vmx_msr_bitmap) {
3156                 r = -ENOMEM;
3157                 goto out1;
3158         }
3159
3160         /*
3161          * Allow direct access to the PC debug port (it is often used for I/O
3162          * delays, but the vmexits simply slow things down).
3163          */
3164         va = kmap(vmx_io_bitmap_a);
3165         memset(va, 0xff, PAGE_SIZE);
3166         clear_bit(0x80, va);
3167         kunmap(vmx_io_bitmap_a);
3168
3169         va = kmap(vmx_io_bitmap_b);
3170         memset(va, 0xff, PAGE_SIZE);
3171         kunmap(vmx_io_bitmap_b);
3172
3173         va = kmap(vmx_msr_bitmap);
3174         memset(va, 0xff, PAGE_SIZE);
3175         kunmap(vmx_msr_bitmap);
3176
3177         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3178
3179         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3180         if (r)
3181                 goto out2;
3182
3183         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3184         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3185         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3186         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3187         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3188
3189         if (cpu_has_vmx_ept())
3190                 bypass_guest_pf = 0;
3191
3192         if (bypass_guest_pf)
3193                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3194
3195         ept_sync_global();
3196
3197         return 0;
3198
3199 out2:
3200         __free_page(vmx_msr_bitmap);
3201 out1:
3202         __free_page(vmx_io_bitmap_b);
3203 out:
3204         __free_page(vmx_io_bitmap_a);
3205         return r;
3206 }
3207
3208 static void __exit vmx_exit(void)
3209 {
3210         __free_page(vmx_msr_bitmap);
3211         __free_page(vmx_io_bitmap_b);
3212         __free_page(vmx_io_bitmap_a);
3213
3214         kvm_exit();
3215 }
3216
3217 module_init(vmx_init)
3218 module_exit(vmx_exit)