arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         u32 exit_reason;
 619
 620         /* Posted interrupt descriptor */
 621         struct pi_desc pi_desc;
 622
 623         /* Support for a guest hypervisor (nested VMX) */
 624         struct nested_vmx nested;
 625
 626         /* Dynamic PLE window. */
 627         int ple_window;
 628         bool ple_window_dirty;
 629
 630         /* Support for PML */
 631 #define PML_ENTITY_NUM          512
 632         struct page *pml_pg;
 633
 634         /* apic deadline value in host tsc */
 635         u64 hv_deadline_tsc;
 636
 637         u64 current_tsc_ratio;
 638
 639         bool guest_pkru_valid;
 640         u32 guest_pkru;
 641         u32 host_pkru;
 642
 643         /*
 644          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 645          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 646          * in msr_ia32_feature_control_valid_bits.
 647          */
 648         u64 msr_ia32_feature_control;
 649         u64 msr_ia32_feature_control_valid_bits;
 650 };
 651
 652 enum segment_cache_field {
 653         SEG_FIELD_SEL = 0,
 654         SEG_FIELD_BASE = 1,
 655         SEG_FIELD_LIMIT = 2,
 656         SEG_FIELD_AR = 3,
 657
 658         SEG_FIELD_NR = 4
 659 };
 660
 661 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 662 {
 663         return container_of(vcpu, struct vcpu_vmx, vcpu);
 664 }
 665
 666 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 667 {
 668         return &(to_vmx(vcpu)->pi_desc);
 669 }
 670
 671 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 672 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 673 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 674                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 675
 676
 677 static unsigned long shadow_read_only_fields[] = {
 678         /*
 679          * We do NOT shadow fields that are modified when L0
 680          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 681          * VMXON...) executed by L1.
 682          * For example, VM_INSTRUCTION_ERROR is read
 683          * by L1 if a vmx instruction fails (part of the error path).
 684          * Note the code assumes this logic. If for some reason
 685          * we start shadowing these fields then we need to
 686          * force a shadow sync when L0 emulates vmx instructions
 687          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 688          * by nested_vmx_failValid)
 689          */
 690         VM_EXIT_REASON,
 691         VM_EXIT_INTR_INFO,
 692         VM_EXIT_INSTRUCTION_LEN,
 693         IDT_VECTORING_INFO_FIELD,
 694         IDT_VECTORING_ERROR_CODE,
 695         VM_EXIT_INTR_ERROR_CODE,
 696         EXIT_QUALIFICATION,
 697         GUEST_LINEAR_ADDRESS,
 698         GUEST_PHYSICAL_ADDRESS
 699 };
 700 static int max_shadow_read_only_fields =
 701         ARRAY_SIZE(shadow_read_only_fields);
 702
 703 static unsigned long shadow_read_write_fields[] = {
 704         TPR_THRESHOLD,
 705         GUEST_RIP,
 706         GUEST_RSP,
 707         GUEST_CR0,
 708         GUEST_CR3,
 709         GUEST_CR4,
 710         GUEST_INTERRUPTIBILITY_INFO,
 711         GUEST_RFLAGS,
 712         GUEST_CS_SELECTOR,
 713         GUEST_CS_AR_BYTES,
 714         GUEST_CS_LIMIT,
 715         GUEST_CS_BASE,
 716         GUEST_ES_BASE,
 717         GUEST_BNDCFGS,
 718         CR0_GUEST_HOST_MASK,
 719         CR0_READ_SHADOW,
 720         CR4_READ_SHADOW,
 721         TSC_OFFSET,
 722         EXCEPTION_BITMAP,
 723         CPU_BASED_VM_EXEC_CONTROL,
 724         VM_ENTRY_EXCEPTION_ERROR_CODE,
 725         VM_ENTRY_INTR_INFO_FIELD,
 726         VM_ENTRY_INSTRUCTION_LEN,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         HOST_FS_BASE,
 729         HOST_GS_BASE,
 730         HOST_FS_SELECTOR,
 731         HOST_GS_SELECTOR
 732 };
 733 static int max_shadow_read_write_fields =
 734         ARRAY_SIZE(shadow_read_write_fields);
 735
 736 static const unsigned short vmcs_field_to_offset_table[] = {
 737         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 738         FIELD(POSTED_INTR_NV, posted_intr_nv),
 739         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 740         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 741         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 742         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 743         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 744         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 745         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 746         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 747         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 748         FIELD(HOST_ES_SELECTOR, host_es_selector),
 749         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 750         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 751         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 752         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 753         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 754         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 755         FIELD64(IO_BITMAP_A, io_bitmap_a),
 756         FIELD64(IO_BITMAP_B, io_bitmap_b),
 757         FIELD64(MSR_BITMAP, msr_bitmap),
 758         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 759         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 760         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 761         FIELD64(TSC_OFFSET, tsc_offset),
 762         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 763         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 764         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 765         FIELD64(EPT_POINTER, ept_pointer),
 766         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 767         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 768         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 769         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 770         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 771         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 772         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 773         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 774         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 775         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 776         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 777         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 778         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 779         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 780         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 781         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 782         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 783         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 784         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 785         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 786         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 787         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 788         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 789         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 790         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 791         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 792         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 793         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 794         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 795         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 796         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 797         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 798         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 799         FIELD(TPR_THRESHOLD, tpr_threshold),
 800         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 801         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 802         FIELD(VM_EXIT_REASON, vm_exit_reason),
 803         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 804         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 805         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 806         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 807         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 808         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 809         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 810         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 811         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 812         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 813         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 814         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 815         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 816         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 817         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 818         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 819         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 820         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 821         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 822         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 823         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 824         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 825         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 826         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 827         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 828         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 829         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 830         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 831         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 832         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 833         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 834         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 835         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 836         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 837         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 838         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 839         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 840         FIELD(EXIT_QUALIFICATION, exit_qualification),
 841         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 842         FIELD(GUEST_CR0, guest_cr0),
 843         FIELD(GUEST_CR3, guest_cr3),
 844         FIELD(GUEST_CR4, guest_cr4),
 845         FIELD(GUEST_ES_BASE, guest_es_base),
 846         FIELD(GUEST_CS_BASE, guest_cs_base),
 847         FIELD(GUEST_SS_BASE, guest_ss_base),
 848         FIELD(GUEST_DS_BASE, guest_ds_base),
 849         FIELD(GUEST_FS_BASE, guest_fs_base),
 850         FIELD(GUEST_GS_BASE, guest_gs_base),
 851         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 852         FIELD(GUEST_TR_BASE, guest_tr_base),
 853         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 854         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 855         FIELD(GUEST_DR7, guest_dr7),
 856         FIELD(GUEST_RSP, guest_rsp),
 857         FIELD(GUEST_RIP, guest_rip),
 858         FIELD(GUEST_RFLAGS, guest_rflags),
 859         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 860         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 861         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 862         FIELD(HOST_CR0, host_cr0),
 863         FIELD(HOST_CR3, host_cr3),
 864         FIELD(HOST_CR4, host_cr4),
 865         FIELD(HOST_FS_BASE, host_fs_base),
 866         FIELD(HOST_GS_BASE, host_gs_base),
 867         FIELD(HOST_TR_BASE, host_tr_base),
 868         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 869         FIELD(HOST_IDTR_BASE, host_idtr_base),
 870         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 871         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 872         FIELD(HOST_RSP, host_rsp),
 873         FIELD(HOST_RIP, host_rip),
 874 };
 875
 876 static inline short vmcs_field_to_offset(unsigned long field)
 877 {
 878         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 879
 880         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 881             vmcs_field_to_offset_table[field] == 0)
 882                 return -ENOENT;
 883
 884         return vmcs_field_to_offset_table[field];
 885 }
 886
 887 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 888 {
 889         return to_vmx(vcpu)->nested.cached_vmcs12;
 890 }
 891
 892 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 893 {
 894         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 895         if (is_error_page(page))
 896                 return NULL;
 897
 898         return page;
 899 }
 900
 901 static void nested_release_page(struct page *page)
 902 {
 903         kvm_release_page_dirty(page);
 904 }
 905
 906 static void nested_release_page_clean(struct page *page)
 907 {
 908         kvm_release_page_clean(page);
 909 }
 910
 911 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 912 static u64 construct_eptp(unsigned long root_hpa);
 913 static void kvm_cpu_vmxon(u64 addr);
 914 static void kvm_cpu_vmxoff(void);
 915 static bool vmx_xsaves_supported(void);
 916 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 917 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 918                             struct kvm_segment *var, int seg);
 919 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 920                             struct kvm_segment *var, int seg);
 921 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 922 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 923 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 924 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 925 static int alloc_identity_pagetable(struct kvm *kvm);
 926
 927 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 928 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 929 /*
 930  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 931  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 932  */
 933 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 934 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 935
 936 /*
 937  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 938  * can find which vCPU should be waken up.
 939  */
 940 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 941 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 942
 943 enum {
 944         VMX_IO_BITMAP_A,
 945         VMX_IO_BITMAP_B,
 946         VMX_MSR_BITMAP_LEGACY,
 947         VMX_MSR_BITMAP_LONGMODE,
 948         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 949         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 950         VMX_MSR_BITMAP_LEGACY_X2APIC,
 951         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 952         VMX_VMREAD_BITMAP,
 953         VMX_VMWRITE_BITMAP,
 954         VMX_BITMAP_NR
 955 };
 956
 957 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 958
 959 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 960 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 961 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 962 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 963 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 964 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 965 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 966 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 967 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 968 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 969
 970 static bool cpu_has_load_ia32_efer;
 971 static bool cpu_has_load_perf_global_ctrl;
 972
 973 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 974 static DEFINE_SPINLOCK(vmx_vpid_lock);
 975
 976 static struct vmcs_config {
 977         int size;
 978         int order;
 979         u32 basic_cap;
 980         u32 revision_id;
 981         u32 pin_based_exec_ctrl;
 982         u32 cpu_based_exec_ctrl;
 983         u32 cpu_based_2nd_exec_ctrl;
 984         u32 vmexit_ctrl;
 985         u32 vmentry_ctrl;
 986 } vmcs_config;
 987
 988 static struct vmx_capability {
 989         u32 ept;
 990         u32 vpid;
 991 } vmx_capability;
 992
 993 #define VMX_SEGMENT_FIELD(seg)                                  \
 994         [VCPU_SREG_##seg] = {                                   \
 995                 .selector = GUEST_##seg##_SELECTOR,             \
 996                 .base = GUEST_##seg##_BASE,                     \
 997                 .limit = GUEST_##seg##_LIMIT,                   \
 998                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 999         }
1000
1001 static const struct kvm_vmx_segment_field {
1002         unsigned selector;
1003         unsigned base;
1004         unsigned limit;
1005         unsigned ar_bytes;
1006 } kvm_vmx_segment_fields[] = {
1007         VMX_SEGMENT_FIELD(CS),
1008         VMX_SEGMENT_FIELD(DS),
1009         VMX_SEGMENT_FIELD(ES),
1010         VMX_SEGMENT_FIELD(FS),
1011         VMX_SEGMENT_FIELD(GS),
1012         VMX_SEGMENT_FIELD(SS),
1013         VMX_SEGMENT_FIELD(TR),
1014         VMX_SEGMENT_FIELD(LDTR),
1015 };
1016
1017 static u64 host_efer;
1018
1019 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1020
1021 /*
1022  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1023  * away by decrementing the array size.
1024  */
1025 static const u32 vmx_msr_index[] = {
1026 #ifdef CONFIG_X86_64
1027         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1028 #endif
1029         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1030 };
1031
1032 static inline bool is_exception_n(u32 intr_info, u8 vector)
1033 {
1034         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1035                              INTR_INFO_VALID_MASK)) ==
1036                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1037 }
1038
1039 static inline bool is_debug(u32 intr_info)
1040 {
1041         return is_exception_n(intr_info, DB_VECTOR);
1042 }
1043
1044 static inline bool is_breakpoint(u32 intr_info)
1045 {
1046         return is_exception_n(intr_info, BP_VECTOR);
1047 }
1048
1049 static inline bool is_page_fault(u32 intr_info)
1050 {
1051         return is_exception_n(intr_info, PF_VECTOR);
1052 }
1053
1054 static inline bool is_no_device(u32 intr_info)
1055 {
1056         return is_exception_n(intr_info, NM_VECTOR);
1057 }
1058
1059 static inline bool is_invalid_opcode(u32 intr_info)
1060 {
1061         return is_exception_n(intr_info, UD_VECTOR);
1062 }
1063
1064 static inline bool is_external_interrupt(u32 intr_info)
1065 {
1066         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1067                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1068 }
1069
1070 static inline bool is_machine_check(u32 intr_info)
1071 {
1072         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1073                              INTR_INFO_VALID_MASK)) ==
1074                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1075 }
1076
1077 static inline bool cpu_has_vmx_msr_bitmap(void)
1078 {
1079         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1080 }
1081
1082 static inline bool cpu_has_vmx_tpr_shadow(void)
1083 {
1084         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1085 }
1086
1087 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1088 {
1089         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1090 }
1091
1092 static inline bool cpu_has_secondary_exec_ctrls(void)
1093 {
1094         return vmcs_config.cpu_based_exec_ctrl &
1095                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1096 }
1097
1098 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1099 {
1100         return vmcs_config.cpu_based_2nd_exec_ctrl &
1101                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1102 }
1103
1104 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1105 {
1106         return vmcs_config.cpu_based_2nd_exec_ctrl &
1107                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1108 }
1109
1110 static inline bool cpu_has_vmx_apic_register_virt(void)
1111 {
1112         return vmcs_config.cpu_based_2nd_exec_ctrl &
1113                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1114 }
1115
1116 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1117 {
1118         return vmcs_config.cpu_based_2nd_exec_ctrl &
1119                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1120 }
1121
1122 /*
1123  * Comment's format: document - errata name - stepping - processor name.
1124  * Refer from
1125  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1126  */
1127 static u32 vmx_preemption_cpu_tfms[] = {
1128 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1129 0x000206E6,
1130 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1131 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1132 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1133 0x00020652,
1134 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1135 0x00020655,
1136 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1137 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1138 /*
1139  * 320767.pdf - AAP86  - B1 -
1140  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1141  */
1142 0x000106E5,
1143 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1144 0x000106A0,
1145 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1146 0x000106A1,
1147 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1148 0x000106A4,
1149  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1150  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1151  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1152 0x000106A5,
1153 };
1154
1155 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1156 {
1157         u32 eax = cpuid_eax(0x00000001), i;
1158
1159         /* Clear the reserved bits */
1160         eax &= ~(0x3U << 14 | 0xfU << 28);
1161         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1162                 if (eax == vmx_preemption_cpu_tfms[i])
1163                         return true;
1164
1165         return false;
1166 }
1167
1168 static inline bool cpu_has_vmx_preemption_timer(void)
1169 {
1170         return vmcs_config.pin_based_exec_ctrl &
1171                 PIN_BASED_VMX_PREEMPTION_TIMER;
1172 }
1173
1174 static inline bool cpu_has_vmx_posted_intr(void)
1175 {
1176         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1177                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1178 }
1179
1180 static inline bool cpu_has_vmx_apicv(void)
1181 {
1182         return cpu_has_vmx_apic_register_virt() &&
1183                 cpu_has_vmx_virtual_intr_delivery() &&
1184                 cpu_has_vmx_posted_intr();
1185 }
1186
1187 static inline bool cpu_has_vmx_flexpriority(void)
1188 {
1189         return cpu_has_vmx_tpr_shadow() &&
1190                 cpu_has_vmx_virtualize_apic_accesses();
1191 }
1192
1193 static inline bool cpu_has_vmx_ept_execute_only(void)
1194 {
1195         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept_2m_page(void)
1199 {
1200         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1201 }
1202
1203 static inline bool cpu_has_vmx_ept_1g_page(void)
1204 {
1205         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_ept_4levels(void)
1209 {
1210         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_ept_ad_bits(void)
1214 {
1215         return vmx_capability.ept & VMX_EPT_AD_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_invept_context(void)
1219 {
1220         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_invept_global(void)
1224 {
1225         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1226 }
1227
1228 static inline bool cpu_has_vmx_invvpid_single(void)
1229 {
1230         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1231 }
1232
1233 static inline bool cpu_has_vmx_invvpid_global(void)
1234 {
1235         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1236 }
1237
1238 static inline bool cpu_has_vmx_invvpid(void)
1239 {
1240         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1241 }
1242
1243 static inline bool cpu_has_vmx_ept(void)
1244 {
1245         return vmcs_config.cpu_based_2nd_exec_ctrl &
1246                 SECONDARY_EXEC_ENABLE_EPT;
1247 }
1248
1249 static inline bool cpu_has_vmx_unrestricted_guest(void)
1250 {
1251         return vmcs_config.cpu_based_2nd_exec_ctrl &
1252                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1253 }
1254
1255 static inline bool cpu_has_vmx_ple(void)
1256 {
1257         return vmcs_config.cpu_based_2nd_exec_ctrl &
1258                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1259 }
1260
1261 static inline bool cpu_has_vmx_basic_inout(void)
1262 {
1263         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1264 }
1265
1266 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1267 {
1268         return flexpriority_enabled && lapic_in_kernel(vcpu);
1269 }
1270
1271 static inline bool cpu_has_vmx_vpid(void)
1272 {
1273         return vmcs_config.cpu_based_2nd_exec_ctrl &
1274                 SECONDARY_EXEC_ENABLE_VPID;
1275 }
1276
1277 static inline bool cpu_has_vmx_rdtscp(void)
1278 {
1279         return vmcs_config.cpu_based_2nd_exec_ctrl &
1280                 SECONDARY_EXEC_RDTSCP;
1281 }
1282
1283 static inline bool cpu_has_vmx_invpcid(void)
1284 {
1285         return vmcs_config.cpu_based_2nd_exec_ctrl &
1286                 SECONDARY_EXEC_ENABLE_INVPCID;
1287 }
1288
1289 static inline bool cpu_has_vmx_wbinvd_exit(void)
1290 {
1291         return vmcs_config.cpu_based_2nd_exec_ctrl &
1292                 SECONDARY_EXEC_WBINVD_EXITING;
1293 }
1294
1295 static inline bool cpu_has_vmx_shadow_vmcs(void)
1296 {
1297         u64 vmx_msr;
1298         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1299         /* check if the cpu supports writing r/o exit information fields */
1300         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1301                 return false;
1302
1303         return vmcs_config.cpu_based_2nd_exec_ctrl &
1304                 SECONDARY_EXEC_SHADOW_VMCS;
1305 }
1306
1307 static inline bool cpu_has_vmx_pml(void)
1308 {
1309         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1310 }
1311
1312 static inline bool cpu_has_vmx_tsc_scaling(void)
1313 {
1314         return vmcs_config.cpu_based_2nd_exec_ctrl &
1315                 SECONDARY_EXEC_TSC_SCALING;
1316 }
1317
1318 static inline bool report_flexpriority(void)
1319 {
1320         return flexpriority_enabled;
1321 }
1322
1323 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1324 {
1325         return vmcs12->cpu_based_vm_exec_control & bit;
1326 }
1327
1328 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1329 {
1330         return (vmcs12->cpu_based_vm_exec_control &
1331                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1332                 (vmcs12->secondary_vm_exec_control & bit);
1333 }
1334
1335 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1336 {
1337         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1338 }
1339
1340 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1341 {
1342         return vmcs12->pin_based_vm_exec_control &
1343                 PIN_BASED_VMX_PREEMPTION_TIMER;
1344 }
1345
1346 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1347 {
1348         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1349 }
1350
1351 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1352 {
1353         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1354                 vmx_xsaves_supported();
1355 }
1356
1357 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1358 {
1359         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1360 }
1361
1362 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1363 {
1364         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1365 }
1366
1367 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1368 {
1369         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1370 }
1371
1372 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1373 {
1374         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1375 }
1376
1377 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1378 {
1379         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1380 }
1381
1382 static inline bool is_nmi(u32 intr_info)
1383 {
1384         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1385                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1386 }
1387
1388 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1389                               u32 exit_intr_info,
1390                               unsigned long exit_qualification);
1391 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1392                         struct vmcs12 *vmcs12,
1393                         u32 reason, unsigned long qualification);
1394
1395 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1396 {
1397         int i;
1398
1399         for (i = 0; i < vmx->nmsrs; ++i)
1400                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1401                         return i;
1402         return -1;
1403 }
1404
1405 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1406 {
1407     struct {
1408         u64 vpid : 16;
1409         u64 rsvd : 48;
1410         u64 gva;
1411     } operand = { vpid, 0, gva };
1412
1413     asm volatile (__ex(ASM_VMX_INVVPID)
1414                   /* CF==1 or ZF==1 --> rc = -1 */
1415                   "; ja 1f ; ud2 ; 1:"
1416                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1417 }
1418
1419 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1420 {
1421         struct {
1422                 u64 eptp, gpa;
1423         } operand = {eptp, gpa};
1424
1425         asm volatile (__ex(ASM_VMX_INVEPT)
1426                         /* CF==1 or ZF==1 --> rc = -1 */
1427                         "; ja 1f ; ud2 ; 1:\n"
1428                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1429 }
1430
1431 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1432 {
1433         int i;
1434
1435         i = __find_msr_index(vmx, msr);
1436         if (i >= 0)
1437                 return &vmx->guest_msrs[i];
1438         return NULL;
1439 }
1440
1441 static void vmcs_clear(struct vmcs *vmcs)
1442 {
1443         u64 phys_addr = __pa(vmcs);
1444         u8 error;
1445
1446         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1447                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1448                       : "cc", "memory");
1449         if (error)
1450                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1451                        vmcs, phys_addr);
1452 }
1453
1454 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1455 {
1456         vmcs_clear(loaded_vmcs->vmcs);
1457         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1458                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1459         loaded_vmcs->cpu = -1;
1460         loaded_vmcs->launched = 0;
1461 }
1462
1463 static void vmcs_load(struct vmcs *vmcs)
1464 {
1465         u64 phys_addr = __pa(vmcs);
1466         u8 error;
1467
1468         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1469                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1470                         : "cc", "memory");
1471         if (error)
1472                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1473                        vmcs, phys_addr);
1474 }
1475
1476 #ifdef CONFIG_KEXEC_CORE
1477 /*
1478  * This bitmap is used to indicate whether the vmclear
1479  * operation is enabled on all cpus. All disabled by
1480  * default.
1481  */
1482 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1483
1484 static inline void crash_enable_local_vmclear(int cpu)
1485 {
1486         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1487 }
1488
1489 static inline void crash_disable_local_vmclear(int cpu)
1490 {
1491         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1492 }
1493
1494 static inline int crash_local_vmclear_enabled(int cpu)
1495 {
1496         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1497 }
1498
1499 static void crash_vmclear_local_loaded_vmcss(void)
1500 {
1501         int cpu = raw_smp_processor_id();
1502         struct loaded_vmcs *v;
1503
1504         if (!crash_local_vmclear_enabled(cpu))
1505                 return;
1506
1507         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1508                             loaded_vmcss_on_cpu_link)
1509                 vmcs_clear(v->vmcs);
1510 }
1511 #else
1512 static inline void crash_enable_local_vmclear(int cpu) { }
1513 static inline void crash_disable_local_vmclear(int cpu) { }
1514 #endif /* CONFIG_KEXEC_CORE */
1515
1516 static void __loaded_vmcs_clear(void *arg)
1517 {
1518         struct loaded_vmcs *loaded_vmcs = arg;
1519         int cpu = raw_smp_processor_id();
1520
1521         if (loaded_vmcs->cpu != cpu)
1522                 return; /* vcpu migration can race with cpu offline */
1523         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1524                 per_cpu(current_vmcs, cpu) = NULL;
1525         crash_disable_local_vmclear(cpu);
1526         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1527
1528         /*
1529          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1530          * is before setting loaded_vmcs->vcpu to -1 which is done in
1531          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1532          * then adds the vmcs into percpu list before it is deleted.
1533          */
1534         smp_wmb();
1535
1536         loaded_vmcs_init(loaded_vmcs);
1537         crash_enable_local_vmclear(cpu);
1538 }
1539
1540 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1541 {
1542         int cpu = loaded_vmcs->cpu;
1543
1544         if (cpu != -1)
1545                 smp_call_function_single(cpu,
1546                          __loaded_vmcs_clear, loaded_vmcs, 1);
1547 }
1548
1549 static inline void vpid_sync_vcpu_single(int vpid)
1550 {
1551         if (vpid == 0)
1552                 return;
1553
1554         if (cpu_has_vmx_invvpid_single())
1555                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1556 }
1557
1558 static inline void vpid_sync_vcpu_global(void)
1559 {
1560         if (cpu_has_vmx_invvpid_global())
1561                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1562 }
1563
1564 static inline void vpid_sync_context(int vpid)
1565 {
1566         if (cpu_has_vmx_invvpid_single())
1567                 vpid_sync_vcpu_single(vpid);
1568         else
1569                 vpid_sync_vcpu_global();
1570 }
1571
1572 static inline void ept_sync_global(void)
1573 {
1574         if (cpu_has_vmx_invept_global())
1575                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1576 }
1577
1578 static inline void ept_sync_context(u64 eptp)
1579 {
1580         if (enable_ept) {
1581                 if (cpu_has_vmx_invept_context())
1582                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1583                 else
1584                         ept_sync_global();
1585         }
1586 }
1587
1588 static __always_inline void vmcs_check16(unsigned long field)
1589 {
1590         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1591                          "16-bit accessor invalid for 64-bit field");
1592         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1593                          "16-bit accessor invalid for 64-bit high field");
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1595                          "16-bit accessor invalid for 32-bit high field");
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1597                          "16-bit accessor invalid for natural width field");
1598 }
1599
1600 static __always_inline void vmcs_check32(unsigned long field)
1601 {
1602         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1603                          "32-bit accessor invalid for 16-bit field");
1604         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1605                          "32-bit accessor invalid for natural width field");
1606 }
1607
1608 static __always_inline void vmcs_check64(unsigned long field)
1609 {
1610         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1611                          "64-bit accessor invalid for 16-bit field");
1612         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1613                          "64-bit accessor invalid for 64-bit high field");
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1615                          "64-bit accessor invalid for 32-bit field");
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1617                          "64-bit accessor invalid for natural width field");
1618 }
1619
1620 static __always_inline void vmcs_checkl(unsigned long field)
1621 {
1622         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1623                          "Natural width accessor invalid for 16-bit field");
1624         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1625                          "Natural width accessor invalid for 64-bit field");
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1627                          "Natural width accessor invalid for 64-bit high field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1629                          "Natural width accessor invalid for 32-bit field");
1630 }
1631
1632 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1633 {
1634         unsigned long value;
1635
1636         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1637                       : "=a"(value) : "d"(field) : "cc");
1638         return value;
1639 }
1640
1641 static __always_inline u16 vmcs_read16(unsigned long field)
1642 {
1643         vmcs_check16(field);
1644         return __vmcs_readl(field);
1645 }
1646
1647 static __always_inline u32 vmcs_read32(unsigned long field)
1648 {
1649         vmcs_check32(field);
1650         return __vmcs_readl(field);
1651 }
1652
1653 static __always_inline u64 vmcs_read64(unsigned long field)
1654 {
1655         vmcs_check64(field);
1656 #ifdef CONFIG_X86_64
1657         return __vmcs_readl(field);
1658 #else
1659         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1660 #endif
1661 }
1662
1663 static __always_inline unsigned long vmcs_readl(unsigned long field)
1664 {
1665         vmcs_checkl(field);
1666         return __vmcs_readl(field);
1667 }
1668
1669 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1670 {
1671         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1672                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1673         dump_stack();
1674 }
1675
1676 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1677 {
1678         u8 error;
1679
1680         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1681                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1682         if (unlikely(error))
1683                 vmwrite_error(field, value);
1684 }
1685
1686 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1687 {
1688         vmcs_check16(field);
1689         __vmcs_writel(field, value);
1690 }
1691
1692 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1693 {
1694         vmcs_check32(field);
1695         __vmcs_writel(field, value);
1696 }
1697
1698 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1699 {
1700         vmcs_check64(field);
1701         __vmcs_writel(field, value);
1702 #ifndef CONFIG_X86_64
1703         asm volatile ("");
1704         __vmcs_writel(field+1, value >> 32);
1705 #endif
1706 }
1707
1708 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1709 {
1710         vmcs_checkl(field);
1711         __vmcs_writel(field, value);
1712 }
1713
1714 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1715 {
1716         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1717                          "vmcs_clear_bits does not support 64-bit fields");
1718         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1719 }
1720
1721 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1722 {
1723         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1724                          "vmcs_set_bits does not support 64-bit fields");
1725         __vmcs_writel(field, __vmcs_readl(field) | mask);
1726 }
1727
1728 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1729 {
1730         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1731 }
1732
1733 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1734 {
1735         vmcs_write32(VM_ENTRY_CONTROLS, val);
1736         vmx->vm_entry_controls_shadow = val;
1737 }
1738
1739 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1740 {
1741         if (vmx->vm_entry_controls_shadow != val)
1742                 vm_entry_controls_init(vmx, val);
1743 }
1744
1745 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1746 {
1747         return vmx->vm_entry_controls_shadow;
1748 }
1749
1750
1751 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1752 {
1753         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1754 }
1755
1756 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1757 {
1758         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1759 }
1760
1761 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1762 {
1763         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1764 }
1765
1766 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1767 {
1768         vmcs_write32(VM_EXIT_CONTROLS, val);
1769         vmx->vm_exit_controls_shadow = val;
1770 }
1771
1772 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1773 {
1774         if (vmx->vm_exit_controls_shadow != val)
1775                 vm_exit_controls_init(vmx, val);
1776 }
1777
1778 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1779 {
1780         return vmx->vm_exit_controls_shadow;
1781 }
1782
1783
1784 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1785 {
1786         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1787 }
1788
1789 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1790 {
1791         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1792 }
1793
1794 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1795 {
1796         vmx->segment_cache.bitmask = 0;
1797 }
1798
1799 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1800                                        unsigned field)
1801 {
1802         bool ret;
1803         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1804
1805         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1806                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1807                 vmx->segment_cache.bitmask = 0;
1808         }
1809         ret = vmx->segment_cache.bitmask & mask;
1810         vmx->segment_cache.bitmask |= mask;
1811         return ret;
1812 }
1813
1814 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1815 {
1816         u16 *p = &vmx->segment_cache.seg[seg].selector;
1817
1818         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1819                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1820         return *p;
1821 }
1822
1823 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1824 {
1825         ulong *p = &vmx->segment_cache.seg[seg].base;
1826
1827         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1828                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1829         return *p;
1830 }
1831
1832 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1833 {
1834         u32 *p = &vmx->segment_cache.seg[seg].limit;
1835
1836         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1837                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1838         return *p;
1839 }
1840
1841 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1842 {
1843         u32 *p = &vmx->segment_cache.seg[seg].ar;
1844
1845         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1846                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1847         return *p;
1848 }
1849
1850 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1851 {
1852         u32 eb;
1853
1854         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1855              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1856         if ((vcpu->guest_debug &
1857              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1858             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1859                 eb |= 1u << BP_VECTOR;
1860         if (to_vmx(vcpu)->rmode.vm86_active)
1861                 eb = ~0;
1862         if (enable_ept)
1863                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1864
1865         /* When we are running a nested L2 guest and L1 specified for it a
1866          * certain exception bitmap, we must trap the same exceptions and pass
1867          * them to L1. When running L2, we will only handle the exceptions
1868          * specified above if L1 did not want them.
1869          */
1870         if (is_guest_mode(vcpu))
1871                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1872
1873         vmcs_write32(EXCEPTION_BITMAP, eb);
1874 }
1875
1876 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1877                 unsigned long entry, unsigned long exit)
1878 {
1879         vm_entry_controls_clearbit(vmx, entry);
1880         vm_exit_controls_clearbit(vmx, exit);
1881 }
1882
1883 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1884 {
1885         unsigned i;
1886         struct msr_autoload *m = &vmx->msr_autoload;
1887
1888         switch (msr) {
1889         case MSR_EFER:
1890                 if (cpu_has_load_ia32_efer) {
1891                         clear_atomic_switch_msr_special(vmx,
1892                                         VM_ENTRY_LOAD_IA32_EFER,
1893                                         VM_EXIT_LOAD_IA32_EFER);
1894                         return;
1895                 }
1896                 break;
1897         case MSR_CORE_PERF_GLOBAL_CTRL:
1898                 if (cpu_has_load_perf_global_ctrl) {
1899                         clear_atomic_switch_msr_special(vmx,
1900                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1901                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1902                         return;
1903                 }
1904                 break;
1905         }
1906
1907         for (i = 0; i < m->nr; ++i)
1908                 if (m->guest[i].index == msr)
1909                         break;
1910
1911         if (i == m->nr)
1912                 return;
1913         --m->nr;
1914         m->guest[i] = m->guest[m->nr];
1915         m->host[i] = m->host[m->nr];
1916         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1917         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1918 }
1919
1920 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1921                 unsigned long entry, unsigned long exit,
1922                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1923                 u64 guest_val, u64 host_val)
1924 {
1925         vmcs_write64(guest_val_vmcs, guest_val);
1926         vmcs_write64(host_val_vmcs, host_val);
1927         vm_entry_controls_setbit(vmx, entry);
1928         vm_exit_controls_setbit(vmx, exit);
1929 }
1930
1931 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1932                                   u64 guest_val, u64 host_val)
1933 {
1934         unsigned i;
1935         struct msr_autoload *m = &vmx->msr_autoload;
1936
1937         switch (msr) {
1938         case MSR_EFER:
1939                 if (cpu_has_load_ia32_efer) {
1940                         add_atomic_switch_msr_special(vmx,
1941                                         VM_ENTRY_LOAD_IA32_EFER,
1942                                         VM_EXIT_LOAD_IA32_EFER,
1943                                         GUEST_IA32_EFER,
1944                                         HOST_IA32_EFER,
1945                                         guest_val, host_val);
1946                         return;
1947                 }
1948                 break;
1949         case MSR_CORE_PERF_GLOBAL_CTRL:
1950                 if (cpu_has_load_perf_global_ctrl) {
1951                         add_atomic_switch_msr_special(vmx,
1952                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1953                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1954                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1955                                         HOST_IA32_PERF_GLOBAL_CTRL,
1956                                         guest_val, host_val);
1957                         return;
1958                 }
1959                 break;
1960         case MSR_IA32_PEBS_ENABLE:
1961                 /* PEBS needs a quiescent period after being disabled (to write
1962                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1963                  * provide that period, so a CPU could write host's record into
1964                  * guest's memory.
1965                  */
1966                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1967         }
1968
1969         for (i = 0; i < m->nr; ++i)
1970                 if (m->guest[i].index == msr)
1971                         break;
1972
1973         if (i == NR_AUTOLOAD_MSRS) {
1974                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1975                                 "Can't add msr %x\n", msr);
1976                 return;
1977         } else if (i == m->nr) {
1978                 ++m->nr;
1979                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1980                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1981         }
1982
1983         m->guest[i].index = msr;
1984         m->guest[i].value = guest_val;
1985         m->host[i].index = msr;
1986         m->host[i].value = host_val;
1987 }
1988
1989 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1990 {
1991         u64 guest_efer = vmx->vcpu.arch.efer;
1992         u64 ignore_bits = 0;
1993
1994         if (!enable_ept) {
1995                 /*
1996                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1997                  * host CPUID is more efficient than testing guest CPUID
1998                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1999                  */
2000                 if (boot_cpu_has(X86_FEATURE_SMEP))
2001                         guest_efer |= EFER_NX;
2002                 else if (!(guest_efer & EFER_NX))
2003                         ignore_bits |= EFER_NX;
2004         }
2005
2006         /*
2007          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2008          */
2009         ignore_bits |= EFER_SCE;
2010 #ifdef CONFIG_X86_64
2011         ignore_bits |= EFER_LMA | EFER_LME;
2012         /* SCE is meaningful only in long mode on Intel */
2013         if (guest_efer & EFER_LMA)
2014                 ignore_bits &= ~(u64)EFER_SCE;
2015 #endif
2016
2017         clear_atomic_switch_msr(vmx, MSR_EFER);
2018
2019         /*
2020          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2021          * On CPUs that support "load IA32_EFER", always switch EFER
2022          * atomically, since it's faster than switching it manually.
2023          */
2024         if (cpu_has_load_ia32_efer ||
2025             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2026                 if (!(guest_efer & EFER_LMA))
2027                         guest_efer &= ~EFER_LME;
2028                 if (guest_efer != host_efer)
2029                         add_atomic_switch_msr(vmx, MSR_EFER,
2030                                               guest_efer, host_efer);
2031                 return false;
2032         } else {
2033                 guest_efer &= ~ignore_bits;
2034                 guest_efer |= host_efer & ignore_bits;
2035
2036                 vmx->guest_msrs[efer_offset].data = guest_efer;
2037                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2038
2039                 return true;
2040         }
2041 }
2042
2043 #ifdef CONFIG_X86_32
2044 /*
2045  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2046  * VMCS rather than the segment table.  KVM uses this helper to figure
2047  * out the current bases to poke them into the VMCS before entry.
2048  */
2049 static unsigned long segment_base(u16 selector)
2050 {
2051         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2052         struct desc_struct *table;
2053         unsigned long v;
2054
2055         if (!(selector & ~SEGMENT_RPL_MASK))
2056                 return 0;
2057
2058         table = (struct desc_struct *)gdt->address;
2059
2060         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2061                 u16 ldt_selector = kvm_read_ldt();
2062
2063                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2064                         return 0;
2065
2066                 table = (struct desc_struct *)segment_base(ldt_selector);
2067         }
2068         v = get_desc_base(&table[selector >> 3]);
2069         return v;
2070 }
2071 #endif
2072
2073 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2074 {
2075         struct vcpu_vmx *vmx = to_vmx(vcpu);
2076         int i;
2077
2078         if (vmx->host_state.loaded)
2079                 return;
2080
2081         vmx->host_state.loaded = 1;
2082         /*
2083          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2084          * allow segment selectors with cpl > 0 or ti == 1.
2085          */
2086         vmx->host_state.ldt_sel = kvm_read_ldt();
2087         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2088         savesegment(fs, vmx->host_state.fs_sel);
2089         if (!(vmx->host_state.fs_sel & 7)) {
2090                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2091                 vmx->host_state.fs_reload_needed = 0;
2092         } else {
2093                 vmcs_write16(HOST_FS_SELECTOR, 0);
2094                 vmx->host_state.fs_reload_needed = 1;
2095         }
2096         savesegment(gs, vmx->host_state.gs_sel);
2097         if (!(vmx->host_state.gs_sel & 7))
2098                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2099         else {
2100                 vmcs_write16(HOST_GS_SELECTOR, 0);
2101                 vmx->host_state.gs_ldt_reload_needed = 1;
2102         }
2103
2104 #ifdef CONFIG_X86_64
2105         savesegment(ds, vmx->host_state.ds_sel);
2106         savesegment(es, vmx->host_state.es_sel);
2107 #endif
2108
2109 #ifdef CONFIG_X86_64
2110         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2111         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2112 #else
2113         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2114         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2115 #endif
2116
2117 #ifdef CONFIG_X86_64
2118         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2119         if (is_long_mode(&vmx->vcpu))
2120                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2121 #endif
2122         if (boot_cpu_has(X86_FEATURE_MPX))
2123                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2124         for (i = 0; i < vmx->save_nmsrs; ++i)
2125                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2126                                    vmx->guest_msrs[i].data,
2127                                    vmx->guest_msrs[i].mask);
2128 }
2129
2130 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2131 {
2132         if (!vmx->host_state.loaded)
2133                 return;
2134
2135         ++vmx->vcpu.stat.host_state_reload;
2136         vmx->host_state.loaded = 0;
2137 #ifdef CONFIG_X86_64
2138         if (is_long_mode(&vmx->vcpu))
2139                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2140 #endif
2141         if (vmx->host_state.gs_ldt_reload_needed) {
2142                 kvm_load_ldt(vmx->host_state.ldt_sel);
2143 #ifdef CONFIG_X86_64
2144                 load_gs_index(vmx->host_state.gs_sel);
2145 #else
2146                 loadsegment(gs, vmx->host_state.gs_sel);
2147 #endif
2148         }
2149         if (vmx->host_state.fs_reload_needed)
2150                 loadsegment(fs, vmx->host_state.fs_sel);
2151 #ifdef CONFIG_X86_64
2152         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2153                 loadsegment(ds, vmx->host_state.ds_sel);
2154                 loadsegment(es, vmx->host_state.es_sel);
2155         }
2156 #endif
2157         invalidate_tss_limit();
2158 #ifdef CONFIG_X86_64
2159         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2160 #endif
2161         if (vmx->host_state.msr_host_bndcfgs)
2162                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2163         load_gdt(this_cpu_ptr(&host_gdt));
2164 }
2165
2166 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2167 {
2168         preempt_disable();
2169         __vmx_load_host_state(vmx);
2170         preempt_enable();
2171 }
2172
2173 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2174 {
2175         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2176         struct pi_desc old, new;
2177         unsigned int dest;
2178
2179         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2180                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2181                 !kvm_vcpu_apicv_active(vcpu))
2182                 return;
2183
2184         do {
2185                 old.control = new.control = pi_desc->control;
2186
2187                 /*
2188                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2189                  * are two possible cases:
2190                  * 1. After running 'pre_block', context switch
2191                  *    happened. For this case, 'sn' was set in
2192                  *    vmx_vcpu_put(), so we need to clear it here.
2193                  * 2. After running 'pre_block', we were blocked,
2194                  *    and woken up by some other guy. For this case,
2195                  *    we don't need to do anything, 'pi_post_block'
2196                  *    will do everything for us. However, we cannot
2197                  *    check whether it is case #1 or case #2 here
2198                  *    (maybe, not needed), so we also clear sn here,
2199                  *    I think it is not a big deal.
2200                  */
2201                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2202                         if (vcpu->cpu != cpu) {
2203                                 dest = cpu_physical_id(cpu);
2204
2205                                 if (x2apic_enabled())
2206                                         new.ndst = dest;
2207                                 else
2208                                         new.ndst = (dest << 8) & 0xFF00;
2209                         }
2210
2211                         /* set 'NV' to 'notification vector' */
2212                         new.nv = POSTED_INTR_VECTOR;
2213                 }
2214
2215                 /* Allow posting non-urgent interrupts */
2216                 new.sn = 0;
2217         } while (cmpxchg(&pi_desc->control, old.control,
2218                         new.control) != old.control);
2219 }
2220
2221 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2222 {
2223         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2224         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2225 }
2226
2227 /*
2228  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2229  * vcpu mutex is already taken.
2230  */
2231 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2232 {
2233         struct vcpu_vmx *vmx = to_vmx(vcpu);
2234         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2235         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2236
2237         if (!vmm_exclusive)
2238                 kvm_cpu_vmxon(phys_addr);
2239         else if (!already_loaded)
2240                 loaded_vmcs_clear(vmx->loaded_vmcs);
2241
2242         if (!already_loaded) {
2243                 local_irq_disable();
2244                 crash_disable_local_vmclear(cpu);
2245
2246                 /*
2247                  * Read loaded_vmcs->cpu should be before fetching
2248                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2249                  * See the comments in __loaded_vmcs_clear().
2250                  */
2251                 smp_rmb();
2252
2253                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2254                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2255                 crash_enable_local_vmclear(cpu);
2256                 local_irq_enable();
2257         }
2258
2259         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2260                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2261                 vmcs_load(vmx->loaded_vmcs->vmcs);
2262         }
2263
2264         if (!already_loaded) {
2265                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2266                 unsigned long sysenter_esp;
2267
2268                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2269
2270                 /*
2271                  * Linux uses per-cpu TSS and GDT, so set these when switching
2272                  * processors.  See 22.2.4.
2273                  */
2274                 vmcs_writel(HOST_TR_BASE,
2275                             (unsigned long)this_cpu_ptr(&cpu_tss));
2276                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2277
2278                 /*
2279                  * VM exits change the host TR limit to 0x67 after a VM
2280                  * exit.  This is okay, since 0x67 covers everything except
2281                  * the IO bitmap and have have code to handle the IO bitmap
2282                  * being lost after a VM exit.
2283                  */
2284                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2285
2286                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2287                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2288
2289                 vmx->loaded_vmcs->cpu = cpu;
2290         }
2291
2292         /* Setup TSC multiplier */
2293         if (kvm_has_tsc_control &&
2294             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2295                 decache_tsc_multiplier(vmx);
2296
2297         vmx_vcpu_pi_load(vcpu, cpu);
2298         vmx->host_pkru = read_pkru();
2299 }
2300
2301 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2302 {
2303         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2304
2305         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2306                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2307                 !kvm_vcpu_apicv_active(vcpu))
2308                 return;
2309
2310         /* Set SN when the vCPU is preempted */
2311         if (vcpu->preempted)
2312                 pi_set_sn(pi_desc);
2313 }
2314
2315 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2316 {
2317         vmx_vcpu_pi_put(vcpu);
2318
2319         __vmx_load_host_state(to_vmx(vcpu));
2320         if (!vmm_exclusive) {
2321                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2322                 vcpu->cpu = -1;
2323                 kvm_cpu_vmxoff();
2324         }
2325 }
2326
2327 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2328
2329 /*
2330  * Return the cr0 value that a nested guest would read. This is a combination
2331  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2332  * its hypervisor (cr0_read_shadow).
2333  */
2334 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2335 {
2336         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2337                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2338 }
2339 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2340 {
2341         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2342                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2343 }
2344
2345 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2346 {
2347         unsigned long rflags, save_rflags;
2348
2349         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2350                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2351                 rflags = vmcs_readl(GUEST_RFLAGS);
2352                 if (to_vmx(vcpu)->rmode.vm86_active) {
2353                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2354                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2355                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2356                 }
2357                 to_vmx(vcpu)->rflags = rflags;
2358         }
2359         return to_vmx(vcpu)->rflags;
2360 }
2361
2362 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2363 {
2364         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2365         to_vmx(vcpu)->rflags = rflags;
2366         if (to_vmx(vcpu)->rmode.vm86_active) {
2367                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2368                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2369         }
2370         vmcs_writel(GUEST_RFLAGS, rflags);
2371 }
2372
2373 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2374 {
2375         return to_vmx(vcpu)->guest_pkru;
2376 }
2377
2378 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2379 {
2380         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2381         int ret = 0;
2382
2383         if (interruptibility & GUEST_INTR_STATE_STI)
2384                 ret |= KVM_X86_SHADOW_INT_STI;
2385         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2386                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2387
2388         return ret;
2389 }
2390
2391 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2392 {
2393         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2394         u32 interruptibility = interruptibility_old;
2395
2396         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2397
2398         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2399                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2400         else if (mask & KVM_X86_SHADOW_INT_STI)
2401                 interruptibility |= GUEST_INTR_STATE_STI;
2402
2403         if ((interruptibility != interruptibility_old))
2404                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2405 }
2406
2407 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2408 {
2409         unsigned long rip;
2410
2411         rip = kvm_rip_read(vcpu);
2412         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2413         kvm_rip_write(vcpu, rip);
2414
2415         /* skipping an emulated instruction also counts */
2416         vmx_set_interrupt_shadow(vcpu, 0);
2417 }
2418
2419 /*
2420  * KVM wants to inject page-faults which it got to the guest. This function
2421  * checks whether in a nested guest, we need to inject them to L1 or L2.
2422  */
2423 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2424 {
2425         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2426
2427         if (!(vmcs12->exception_bitmap & (1u << nr)))
2428                 return 0;
2429
2430         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2431                           vmcs_read32(VM_EXIT_INTR_INFO),
2432                           vmcs_readl(EXIT_QUALIFICATION));
2433         return 1;
2434 }
2435
2436 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2437                                 bool has_error_code, u32 error_code,
2438                                 bool reinject)
2439 {
2440         struct vcpu_vmx *vmx = to_vmx(vcpu);
2441         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2442
2443         if (!reinject && is_guest_mode(vcpu) &&
2444             nested_vmx_check_exception(vcpu, nr))
2445                 return;
2446
2447         if (has_error_code) {
2448                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2449                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2450         }
2451
2452         if (vmx->rmode.vm86_active) {
2453                 int inc_eip = 0;
2454                 if (kvm_exception_is_soft(nr))
2455                         inc_eip = vcpu->arch.event_exit_inst_len;
2456                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2457                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2458                 return;
2459         }
2460
2461         if (kvm_exception_is_soft(nr)) {
2462                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2463                              vmx->vcpu.arch.event_exit_inst_len);
2464                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2465         } else
2466                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2467
2468         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2469 }
2470
2471 static bool vmx_rdtscp_supported(void)
2472 {
2473         return cpu_has_vmx_rdtscp();
2474 }
2475
2476 static bool vmx_invpcid_supported(void)
2477 {
2478         return cpu_has_vmx_invpcid() && enable_ept;
2479 }
2480
2481 /*
2482  * Swap MSR entry in host/guest MSR entry array.
2483  */
2484 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2485 {
2486         struct shared_msr_entry tmp;
2487
2488         tmp = vmx->guest_msrs[to];
2489         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2490         vmx->guest_msrs[from] = tmp;
2491 }
2492
2493 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2494 {
2495         unsigned long *msr_bitmap;
2496
2497         if (is_guest_mode(vcpu))
2498                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2499         else if (cpu_has_secondary_exec_ctrls() &&
2500                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2501                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2502                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2503                         if (is_long_mode(vcpu))
2504                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2505                         else
2506                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2507                 } else {
2508                         if (is_long_mode(vcpu))
2509                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2510                         else
2511                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2512                 }
2513         } else {
2514                 if (is_long_mode(vcpu))
2515                         msr_bitmap = vmx_msr_bitmap_longmode;
2516                 else
2517                         msr_bitmap = vmx_msr_bitmap_legacy;
2518         }
2519
2520         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2521 }
2522
2523 /*
2524  * Set up the vmcs to automatically save and restore system
2525  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2526  * mode, as fiddling with msrs is very expensive.
2527  */
2528 static void setup_msrs(struct vcpu_vmx *vmx)
2529 {
2530         int save_nmsrs, index;
2531
2532         save_nmsrs = 0;
2533 #ifdef CONFIG_X86_64
2534         if (is_long_mode(&vmx->vcpu)) {
2535                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2536                 if (index >= 0)
2537                         move_msr_up(vmx, index, save_nmsrs++);
2538                 index = __find_msr_index(vmx, MSR_LSTAR);
2539                 if (index >= 0)
2540                         move_msr_up(vmx, index, save_nmsrs++);
2541                 index = __find_msr_index(vmx, MSR_CSTAR);
2542                 if (index >= 0)
2543                         move_msr_up(vmx, index, save_nmsrs++);
2544                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2545                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2546                         move_msr_up(vmx, index, save_nmsrs++);
2547                 /*
2548                  * MSR_STAR is only needed on long mode guests, and only
2549                  * if efer.sce is enabled.
2550                  */
2551                 index = __find_msr_index(vmx, MSR_STAR);
2552                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2553                         move_msr_up(vmx, index, save_nmsrs++);
2554         }
2555 #endif
2556         index = __find_msr_index(vmx, MSR_EFER);
2557         if (index >= 0 && update_transition_efer(vmx, index))
2558                 move_msr_up(vmx, index, save_nmsrs++);
2559
2560         vmx->save_nmsrs = save_nmsrs;
2561
2562         if (cpu_has_vmx_msr_bitmap())
2563                 vmx_set_msr_bitmap(&vmx->vcpu);
2564 }
2565
2566 /*
2567  * reads and returns guest's timestamp counter "register"
2568  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2569  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2570  */
2571 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2572 {
2573         u64 host_tsc, tsc_offset;
2574
2575         host_tsc = rdtsc();
2576         tsc_offset = vmcs_read64(TSC_OFFSET);
2577         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2578 }
2579
2580 /*
2581  * writes 'offset' into guest's timestamp counter offset register
2582  */
2583 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2584 {
2585         if (is_guest_mode(vcpu)) {
2586                 /*
2587                  * We're here if L1 chose not to trap WRMSR to TSC. According
2588                  * to the spec, this should set L1's TSC; The offset that L1
2589                  * set for L2 remains unchanged, and still needs to be added
2590                  * to the newly set TSC to get L2's TSC.
2591                  */
2592                 struct vmcs12 *vmcs12;
2593                 /* recalculate vmcs02.TSC_OFFSET: */
2594                 vmcs12 = get_vmcs12(vcpu);
2595                 vmcs_write64(TSC_OFFSET, offset +
2596                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2597                          vmcs12->tsc_offset : 0));
2598         } else {
2599                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2600                                            vmcs_read64(TSC_OFFSET), offset);
2601                 vmcs_write64(TSC_OFFSET, offset);
2602         }
2603 }
2604
2605 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2606 {
2607         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2608         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2609 }
2610
2611 /*
2612  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2613  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2614  * all guests if the "nested" module option is off, and can also be disabled
2615  * for a single guest by disabling its VMX cpuid bit.
2616  */
2617 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2618 {
2619         return nested && guest_cpuid_has_vmx(vcpu);
2620 }
2621
2622 /*
2623  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2624  * returned for the various VMX controls MSRs when nested VMX is enabled.
2625  * The same values should also be used to verify that vmcs12 control fields are
2626  * valid during nested entry from L1 to L2.
2627  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2628  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2629  * bit in the high half is on if the corresponding bit in the control field
2630  * may be on. See also vmx_control_verify().
2631  */
2632 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2633 {
2634         /*
2635          * Note that as a general rule, the high half of the MSRs (bits in
2636          * the control fields which may be 1) should be initialized by the
2637          * intersection of the underlying hardware's MSR (i.e., features which
2638          * can be supported) and the list of features we want to expose -
2639          * because they are known to be properly supported in our code.
2640          * Also, usually, the low half of the MSRs (bits which must be 1) can
2641          * be set to 0, meaning that L1 may turn off any of these bits. The
2642          * reason is that if one of these bits is necessary, it will appear
2643          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2644          * fields of vmcs01 and vmcs02, will turn these bits off - and
2645          * nested_vmx_exit_handled() will not pass related exits to L1.
2646          * These rules have exceptions below.
2647          */
2648
2649         /* pin-based controls */
2650         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2651                 vmx->nested.nested_vmx_pinbased_ctls_low,
2652                 vmx->nested.nested_vmx_pinbased_ctls_high);
2653         vmx->nested.nested_vmx_pinbased_ctls_low |=
2654                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2655         vmx->nested.nested_vmx_pinbased_ctls_high &=
2656                 PIN_BASED_EXT_INTR_MASK |
2657                 PIN_BASED_NMI_EXITING |
2658                 PIN_BASED_VIRTUAL_NMIS;
2659         vmx->nested.nested_vmx_pinbased_ctls_high |=
2660                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2661                 PIN_BASED_VMX_PREEMPTION_TIMER;
2662         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2663                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2664                         PIN_BASED_POSTED_INTR;
2665
2666         /* exit controls */
2667         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2668                 vmx->nested.nested_vmx_exit_ctls_low,
2669                 vmx->nested.nested_vmx_exit_ctls_high);
2670         vmx->nested.nested_vmx_exit_ctls_low =
2671                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2672
2673         vmx->nested.nested_vmx_exit_ctls_high &=
2674 #ifdef CONFIG_X86_64
2675                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2676 #endif
2677                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2678         vmx->nested.nested_vmx_exit_ctls_high |=
2679                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2680                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2681                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2682
2683         if (kvm_mpx_supported())
2684                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2685
2686         /* We support free control of debug control saving. */
2687         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2688
2689         /* entry controls */
2690         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2691                 vmx->nested.nested_vmx_entry_ctls_low,
2692                 vmx->nested.nested_vmx_entry_ctls_high);
2693         vmx->nested.nested_vmx_entry_ctls_low =
2694                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2695         vmx->nested.nested_vmx_entry_ctls_high &=
2696 #ifdef CONFIG_X86_64
2697                 VM_ENTRY_IA32E_MODE |
2698 #endif
2699                 VM_ENTRY_LOAD_IA32_PAT;
2700         vmx->nested.nested_vmx_entry_ctls_high |=
2701                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2702         if (kvm_mpx_supported())
2703                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2704
2705         /* We support free control of debug control loading. */
2706         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2707
2708         /* cpu-based controls */
2709         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2710                 vmx->nested.nested_vmx_procbased_ctls_low,
2711                 vmx->nested.nested_vmx_procbased_ctls_high);
2712         vmx->nested.nested_vmx_procbased_ctls_low =
2713                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2714         vmx->nested.nested_vmx_procbased_ctls_high &=
2715                 CPU_BASED_VIRTUAL_INTR_PENDING |
2716                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2717                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2718                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2719                 CPU_BASED_CR3_STORE_EXITING |
2720 #ifdef CONFIG_X86_64
2721                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2722 #endif
2723                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2724                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2725                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2726                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2727                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2728         /*
2729          * We can allow some features even when not supported by the
2730          * hardware. For example, L1 can specify an MSR bitmap - and we
2731          * can use it to avoid exits to L1 - even when L0 runs L2
2732          * without MSR bitmaps.
2733          */
2734         vmx->nested.nested_vmx_procbased_ctls_high |=
2735                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2736                 CPU_BASED_USE_MSR_BITMAPS;
2737
2738         /* We support free control of CR3 access interception. */
2739         vmx->nested.nested_vmx_procbased_ctls_low &=
2740                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2741
2742         /* secondary cpu-based controls */
2743         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2744                 vmx->nested.nested_vmx_secondary_ctls_low,
2745                 vmx->nested.nested_vmx_secondary_ctls_high);
2746         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2747         vmx->nested.nested_vmx_secondary_ctls_high &=
2748                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2749                 SECONDARY_EXEC_RDTSCP |
2750                 SECONDARY_EXEC_DESC |
2751                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2752                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2753                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2754                 SECONDARY_EXEC_WBINVD_EXITING |
2755                 SECONDARY_EXEC_XSAVES;
2756
2757         if (enable_ept) {
2758                 /* nested EPT: emulate EPT also to L1 */
2759                 vmx->nested.nested_vmx_secondary_ctls_high |=
2760                         SECONDARY_EXEC_ENABLE_EPT;
2761                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2762                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2763                 if (cpu_has_vmx_ept_execute_only())
2764                         vmx->nested.nested_vmx_ept_caps |=
2765                                 VMX_EPT_EXECUTE_ONLY_BIT;
2766                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2767                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2768                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2769                         VMX_EPT_1GB_PAGE_BIT;
2770                if (enable_ept_ad_bits)
2771                        vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2772         } else
2773                 vmx->nested.nested_vmx_ept_caps = 0;
2774
2775         /*
2776          * Old versions of KVM use the single-context version without
2777          * checking for support, so declare that it is supported even
2778          * though it is treated as global context.  The alternative is
2779          * not failing the single-context invvpid, and it is worse.
2780          */
2781         if (enable_vpid) {
2782                 vmx->nested.nested_vmx_secondary_ctls_high |=
2783                         SECONDARY_EXEC_ENABLE_VPID;
2784                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2785                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2786         } else
2787                 vmx->nested.nested_vmx_vpid_caps = 0;
2788
2789         if (enable_unrestricted_guest)
2790                 vmx->nested.nested_vmx_secondary_ctls_high |=
2791                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2792
2793         /* miscellaneous data */
2794         rdmsr(MSR_IA32_VMX_MISC,
2795                 vmx->nested.nested_vmx_misc_low,
2796                 vmx->nested.nested_vmx_misc_high);
2797         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2798         vmx->nested.nested_vmx_misc_low |=
2799                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2800                 VMX_MISC_ACTIVITY_HLT;
2801         vmx->nested.nested_vmx_misc_high = 0;
2802
2803         /*
2804          * This MSR reports some information about VMX support. We
2805          * should return information about the VMX we emulate for the
2806          * guest, and the VMCS structure we give it - not about the
2807          * VMX support of the underlying hardware.
2808          */
2809         vmx->nested.nested_vmx_basic =
2810                 VMCS12_REVISION |
2811                 VMX_BASIC_TRUE_CTLS |
2812                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2813                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2814
2815         if (cpu_has_vmx_basic_inout())
2816                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2817
2818         /*
2819          * These MSRs specify bits which the guest must keep fixed on
2820          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2821          * We picked the standard core2 setting.
2822          */
2823 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2824 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2825         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2826         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2827
2828         /* These MSRs specify bits which the guest must keep fixed off. */
2829         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2830         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2831
2832         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2833         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2834 }
2835
2836 /*
2837  * if fixed0[i] == 1: val[i] must be 1
2838  * if fixed1[i] == 0: val[i] must be 0
2839  */
2840 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2841 {
2842         return ((val & fixed1) | fixed0) == val;
2843 }
2844
2845 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2846 {
2847         return fixed_bits_valid(control, low, high);
2848 }
2849
2850 static inline u64 vmx_control_msr(u32 low, u32 high)
2851 {
2852         return low | ((u64)high << 32);
2853 }
2854
2855 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2856 {
2857         superset &= mask;
2858         subset &= mask;
2859
2860         return (superset | subset) == superset;
2861 }
2862
2863 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2864 {
2865         const u64 feature_and_reserved =
2866                 /* feature (except bit 48; see below) */
2867                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2868                 /* reserved */
2869                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2870         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2871
2872         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2873                 return -EINVAL;
2874
2875         /*
2876          * KVM does not emulate a version of VMX that constrains physical
2877          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2878          */
2879         if (data & BIT_ULL(48))
2880                 return -EINVAL;
2881
2882         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2883             vmx_basic_vmcs_revision_id(data))
2884                 return -EINVAL;
2885
2886         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2887                 return -EINVAL;
2888
2889         vmx->nested.nested_vmx_basic = data;
2890         return 0;
2891 }
2892
2893 static int
2894 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2895 {
2896         u64 supported;
2897         u32 *lowp, *highp;
2898
2899         switch (msr_index) {
2900         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2901                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2902                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2903                 break;
2904         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2905                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2906                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2907                 break;
2908         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2909                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2910                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2911                 break;
2912         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2913                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2914                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2915                 break;
2916         case MSR_IA32_VMX_PROCBASED_CTLS2:
2917                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2918                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2919                 break;
2920         default:
2921                 BUG();
2922         }
2923
2924         supported = vmx_control_msr(*lowp, *highp);
2925
2926         /* Check must-be-1 bits are still 1. */
2927         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2928                 return -EINVAL;
2929
2930         /* Check must-be-0 bits are still 0. */
2931         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2932                 return -EINVAL;
2933
2934         *lowp = data;
2935         *highp = data >> 32;
2936         return 0;
2937 }
2938
2939 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2940 {
2941         const u64 feature_and_reserved_bits =
2942                 /* feature */
2943                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2944                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2945                 /* reserved */
2946                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2947         u64 vmx_misc;
2948
2949         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2950                                    vmx->nested.nested_vmx_misc_high);
2951
2952         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2953                 return -EINVAL;
2954
2955         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2956              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2957             vmx_misc_preemption_timer_rate(data) !=
2958             vmx_misc_preemption_timer_rate(vmx_misc))
2959                 return -EINVAL;
2960
2961         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2962                 return -EINVAL;
2963
2964         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2965                 return -EINVAL;
2966
2967         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2968                 return -EINVAL;
2969
2970         vmx->nested.nested_vmx_misc_low = data;
2971         vmx->nested.nested_vmx_misc_high = data >> 32;
2972         return 0;
2973 }
2974
2975 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2976 {
2977         u64 vmx_ept_vpid_cap;
2978
2979         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2980                                            vmx->nested.nested_vmx_vpid_caps);
2981
2982         /* Every bit is either reserved or a feature bit. */
2983         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2984                 return -EINVAL;
2985
2986         vmx->nested.nested_vmx_ept_caps = data;
2987         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2988         return 0;
2989 }
2990
2991 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2992 {
2993         u64 *msr;
2994
2995         switch (msr_index) {
2996         case MSR_IA32_VMX_CR0_FIXED0:
2997                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
2998                 break;
2999         case MSR_IA32_VMX_CR4_FIXED0:
3000                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3001                 break;
3002         default:
3003                 BUG();
3004         }
3005
3006         /*
3007          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3008          * must be 1 in the restored value.
3009          */
3010         if (!is_bitwise_subset(data, *msr, -1ULL))
3011                 return -EINVAL;
3012
3013         *msr = data;
3014         return 0;
3015 }
3016
3017 /*
3018  * Called when userspace is restoring VMX MSRs.
3019  *
3020  * Returns 0 on success, non-0 otherwise.
3021  */
3022 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3023 {
3024         struct vcpu_vmx *vmx = to_vmx(vcpu);
3025
3026         switch (msr_index) {
3027         case MSR_IA32_VMX_BASIC:
3028                 return vmx_restore_vmx_basic(vmx, data);
3029         case MSR_IA32_VMX_PINBASED_CTLS:
3030         case MSR_IA32_VMX_PROCBASED_CTLS:
3031         case MSR_IA32_VMX_EXIT_CTLS:
3032         case MSR_IA32_VMX_ENTRY_CTLS:
3033                 /*
3034                  * The "non-true" VMX capability MSRs are generated from the
3035                  * "true" MSRs, so we do not support restoring them directly.
3036                  *
3037                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3038                  * should restore the "true" MSRs with the must-be-1 bits
3039                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3040                  * DEFAULT SETTINGS".
3041                  */
3042                 return -EINVAL;
3043         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3044         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3045         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3046         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3047         case MSR_IA32_VMX_PROCBASED_CTLS2:
3048                 return vmx_restore_control_msr(vmx, msr_index, data);
3049         case MSR_IA32_VMX_MISC:
3050                 return vmx_restore_vmx_misc(vmx, data);
3051         case MSR_IA32_VMX_CR0_FIXED0:
3052         case MSR_IA32_VMX_CR4_FIXED0:
3053                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3054         case MSR_IA32_VMX_CR0_FIXED1:
3055         case MSR_IA32_VMX_CR4_FIXED1:
3056                 /*
3057                  * These MSRs are generated based on the vCPU's CPUID, so we
3058                  * do not support restoring them directly.
3059                  */
3060                 return -EINVAL;
3061         case MSR_IA32_VMX_EPT_VPID_CAP:
3062                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3063         case MSR_IA32_VMX_VMCS_ENUM:
3064                 vmx->nested.nested_vmx_vmcs_enum = data;
3065                 return 0;
3066         default:
3067                 /*
3068                  * The rest of the VMX capability MSRs do not support restore.
3069                  */
3070                 return -EINVAL;
3071         }
3072 }
3073
3074 /* Returns 0 on success, non-0 otherwise. */
3075 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3076 {
3077         struct vcpu_vmx *vmx = to_vmx(vcpu);
3078
3079         switch (msr_index) {
3080         case MSR_IA32_VMX_BASIC:
3081                 *pdata = vmx->nested.nested_vmx_basic;
3082                 break;
3083         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3084         case MSR_IA32_VMX_PINBASED_CTLS:
3085                 *pdata = vmx_control_msr(
3086                         vmx->nested.nested_vmx_pinbased_ctls_low,
3087                         vmx->nested.nested_vmx_pinbased_ctls_high);
3088                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3089                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3090                 break;
3091         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3092         case MSR_IA32_VMX_PROCBASED_CTLS:
3093                 *pdata = vmx_control_msr(
3094                         vmx->nested.nested_vmx_procbased_ctls_low,
3095                         vmx->nested.nested_vmx_procbased_ctls_high);
3096                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3097                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3098                 break;
3099         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3100         case MSR_IA32_VMX_EXIT_CTLS:
3101                 *pdata = vmx_control_msr(
3102                         vmx->nested.nested_vmx_exit_ctls_low,
3103                         vmx->nested.nested_vmx_exit_ctls_high);
3104                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3105                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3106                 break;
3107         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3108         case MSR_IA32_VMX_ENTRY_CTLS:
3109                 *pdata = vmx_control_msr(
3110                         vmx->nested.nested_vmx_entry_ctls_low,
3111                         vmx->nested.nested_vmx_entry_ctls_high);
3112                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3113                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3114                 break;
3115         case MSR_IA32_VMX_MISC:
3116                 *pdata = vmx_control_msr(
3117                         vmx->nested.nested_vmx_misc_low,
3118                         vmx->nested.nested_vmx_misc_high);
3119                 break;
3120         case MSR_IA32_VMX_CR0_FIXED0:
3121                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3122                 break;
3123         case MSR_IA32_VMX_CR0_FIXED1:
3124                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3125                 break;
3126         case MSR_IA32_VMX_CR4_FIXED0:
3127                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3128                 break;
3129         case MSR_IA32_VMX_CR4_FIXED1:
3130                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3131                 break;
3132         case MSR_IA32_VMX_VMCS_ENUM:
3133                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3134                 break;
3135         case MSR_IA32_VMX_PROCBASED_CTLS2:
3136                 *pdata = vmx_control_msr(
3137                         vmx->nested.nested_vmx_secondary_ctls_low,
3138                         vmx->nested.nested_vmx_secondary_ctls_high);
3139                 break;
3140         case MSR_IA32_VMX_EPT_VPID_CAP:
3141                 *pdata = vmx->nested.nested_vmx_ept_caps |
3142                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3143                 break;
3144         default:
3145                 return 1;
3146         }
3147
3148         return 0;
3149 }
3150
3151 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3152                                                  uint64_t val)
3153 {
3154         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3155
3156         return !(val & ~valid_bits);
3157 }
3158
3159 /*
3160  * Reads an msr value (of 'msr_index') into 'pdata'.
3161  * Returns 0 on success, non-0 otherwise.
3162  * Assumes vcpu_load() was already called.
3163  */
3164 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3165 {
3166         struct shared_msr_entry *msr;
3167
3168         switch (msr_info->index) {
3169 #ifdef CONFIG_X86_64
3170         case MSR_FS_BASE:
3171                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3172                 break;
3173         case MSR_GS_BASE:
3174                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3175                 break;
3176         case MSR_KERNEL_GS_BASE:
3177                 vmx_load_host_state(to_vmx(vcpu));
3178                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3179                 break;
3180 #endif
3181         case MSR_EFER:
3182                 return kvm_get_msr_common(vcpu, msr_info);
3183         case MSR_IA32_TSC:
3184                 msr_info->data = guest_read_tsc(vcpu);
3185                 break;
3186         case MSR_IA32_SYSENTER_CS:
3187                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3188                 break;
3189         case MSR_IA32_SYSENTER_EIP:
3190                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3191                 break;
3192         case MSR_IA32_SYSENTER_ESP:
3193                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3194                 break;
3195         case MSR_IA32_BNDCFGS:
3196                 if (!kvm_mpx_supported())
3197                         return 1;
3198                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3199                 break;
3200         case MSR_IA32_MCG_EXT_CTL:
3201                 if (!msr_info->host_initiated &&
3202                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3203                       FEATURE_CONTROL_LMCE))
3204                         return 1;
3205                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3206                 break;
3207         case MSR_IA32_FEATURE_CONTROL:
3208                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3209                 break;
3210         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3211                 if (!nested_vmx_allowed(vcpu))
3212                         return 1;
3213                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3214         case MSR_IA32_XSS:
3215                 if (!vmx_xsaves_supported())
3216                         return 1;
3217                 msr_info->data = vcpu->arch.ia32_xss;
3218                 break;
3219         case MSR_TSC_AUX:
3220                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3221                         return 1;
3222                 /* Otherwise falls through */
3223         default:
3224                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3225                 if (msr) {
3226                         msr_info->data = msr->data;
3227                         break;
3228                 }
3229                 return kvm_get_msr_common(vcpu, msr_info);
3230         }
3231
3232         return 0;
3233 }
3234
3235 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3236
3237 /*
3238  * Writes msr value into into the appropriate "register".
3239  * Returns 0 on success, non-0 otherwise.
3240  * Assumes vcpu_load() was already called.
3241  */
3242 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3243 {
3244         struct vcpu_vmx *vmx = to_vmx(vcpu);
3245         struct shared_msr_entry *msr;
3246         int ret = 0;
3247         u32 msr_index = msr_info->index;
3248         u64 data = msr_info->data;
3249
3250         switch (msr_index) {
3251         case MSR_EFER:
3252                 ret = kvm_set_msr_common(vcpu, msr_info);
3253                 break;
3254 #ifdef CONFIG_X86_64
3255         case MSR_FS_BASE:
3256                 vmx_segment_cache_clear(vmx);
3257                 vmcs_writel(GUEST_FS_BASE, data);
3258                 break;
3259         case MSR_GS_BASE:
3260                 vmx_segment_cache_clear(vmx);
3261                 vmcs_writel(GUEST_GS_BASE, data);
3262                 break;
3263         case MSR_KERNEL_GS_BASE:
3264                 vmx_load_host_state(vmx);
3265                 vmx->msr_guest_kernel_gs_base = data;
3266                 break;
3267 #endif
3268         case MSR_IA32_SYSENTER_CS:
3269                 vmcs_write32(GUEST_SYSENTER_CS, data);
3270                 break;
3271         case MSR_IA32_SYSENTER_EIP:
3272                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3273                 break;
3274         case MSR_IA32_SYSENTER_ESP:
3275                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3276                 break;
3277         case MSR_IA32_BNDCFGS:
3278                 if (!kvm_mpx_supported())
3279                         return 1;
3280                 vmcs_write64(GUEST_BNDCFGS, data);
3281                 break;
3282         case MSR_IA32_TSC:
3283                 kvm_write_tsc(vcpu, msr_info);
3284                 break;
3285         case MSR_IA32_CR_PAT:
3286                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3287                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3288                                 return 1;
3289                         vmcs_write64(GUEST_IA32_PAT, data);
3290                         vcpu->arch.pat = data;
3291                         break;
3292                 }
3293                 ret = kvm_set_msr_common(vcpu, msr_info);
3294                 break;
3295         case MSR_IA32_TSC_ADJUST:
3296                 ret = kvm_set_msr_common(vcpu, msr_info);
3297                 break;
3298         case MSR_IA32_MCG_EXT_CTL:
3299                 if ((!msr_info->host_initiated &&
3300                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3301                        FEATURE_CONTROL_LMCE)) ||
3302                     (data & ~MCG_EXT_CTL_LMCE_EN))
3303                         return 1;
3304                 vcpu->arch.mcg_ext_ctl = data;
3305                 break;
3306         case MSR_IA32_FEATURE_CONTROL:
3307                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3308                     (to_vmx(vcpu)->msr_ia32_feature_control &
3309                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3310                         return 1;
3311                 vmx->msr_ia32_feature_control = data;
3312                 if (msr_info->host_initiated && data == 0)
3313                         vmx_leave_nested(vcpu);
3314                 break;
3315         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3316                 if (!msr_info->host_initiated)
3317                         return 1; /* they are read-only */
3318                 if (!nested_vmx_allowed(vcpu))
3319                         return 1;
3320                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3321         case MSR_IA32_XSS:
3322                 if (!vmx_xsaves_supported())
3323                         return 1;
3324                 /*
3325                  * The only supported bit as of Skylake is bit 8, but
3326                  * it is not supported on KVM.
3327                  */
3328                 if (data != 0)
3329                         return 1;
3330                 vcpu->arch.ia32_xss = data;
3331                 if (vcpu->arch.ia32_xss != host_xss)
3332                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3333                                 vcpu->arch.ia32_xss, host_xss);
3334                 else
3335                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3336                 break;
3337         case MSR_TSC_AUX:
3338                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3339                         return 1;
3340                 /* Check reserved bit, higher 32 bits should be zero */
3341                 if ((data >> 32) != 0)
3342                         return 1;
3343                 /* Otherwise falls through */
3344         default:
3345                 msr = find_msr_entry(vmx, msr_index);
3346                 if (msr) {
3347                         u64 old_msr_data = msr->data;
3348                         msr->data = data;
3349                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3350                                 preempt_disable();
3351                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3352                                                          msr->mask);
3353                                 preempt_enable();
3354                                 if (ret)
3355                                         msr->data = old_msr_data;
3356                         }
3357                         break;
3358                 }
3359                 ret = kvm_set_msr_common(vcpu, msr_info);
3360         }
3361
3362         return ret;
3363 }
3364
3365 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3366 {
3367         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3368         switch (reg) {
3369         case VCPU_REGS_RSP:
3370                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3371                 break;
3372         case VCPU_REGS_RIP:
3373                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3374                 break;
3375         case VCPU_EXREG_PDPTR:
3376                 if (enable_ept)
3377                         ept_save_pdptrs(vcpu);
3378                 break;
3379         default:
3380                 break;
3381         }
3382 }
3383
3384 static __init int cpu_has_kvm_support(void)
3385 {
3386         return cpu_has_vmx();
3387 }
3388
3389 static __init int vmx_disabled_by_bios(void)
3390 {
3391         u64 msr;
3392
3393         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3394         if (msr & FEATURE_CONTROL_LOCKED) {
3395                 /* launched w/ TXT and VMX disabled */
3396                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3397                         && tboot_enabled())
3398                         return 1;
3399                 /* launched w/o TXT and VMX only enabled w/ TXT */
3400                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3401                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3402                         && !tboot_enabled()) {
3403                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3404                                 "activate TXT before enabling KVM\n");
3405                         return 1;
3406                 }
3407                 /* launched w/o TXT and VMX disabled */
3408                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3409                         && !tboot_enabled())
3410                         return 1;
3411         }
3412
3413         return 0;
3414 }
3415
3416 static void kvm_cpu_vmxon(u64 addr)
3417 {
3418         intel_pt_handle_vmx(1);
3419
3420         asm volatile (ASM_VMX_VMXON_RAX
3421                         : : "a"(&addr), "m"(addr)
3422                         : "memory", "cc");
3423 }
3424
3425 static int hardware_enable(void)
3426 {
3427         int cpu = raw_smp_processor_id();
3428         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3429         u64 old, test_bits;
3430
3431         if (cr4_read_shadow() & X86_CR4_VMXE)
3432                 return -EBUSY;
3433
3434         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3435         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3436         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3437
3438         /*
3439          * Now we can enable the vmclear operation in kdump
3440          * since the loaded_vmcss_on_cpu list on this cpu
3441          * has been initialized.
3442          *
3443          * Though the cpu is not in VMX operation now, there
3444          * is no problem to enable the vmclear operation
3445          * for the loaded_vmcss_on_cpu list is empty!
3446          */
3447         crash_enable_local_vmclear(cpu);
3448
3449         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3450
3451         test_bits = FEATURE_CONTROL_LOCKED;
3452         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3453         if (tboot_enabled())
3454                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3455
3456         if ((old & test_bits) != test_bits) {
3457                 /* enable and lock */
3458                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3459         }
3460         cr4_set_bits(X86_CR4_VMXE);
3461
3462         if (vmm_exclusive) {
3463                 kvm_cpu_vmxon(phys_addr);
3464                 ept_sync_global();
3465         }
3466
3467         native_store_gdt(this_cpu_ptr(&host_gdt));
3468
3469         return 0;
3470 }
3471
3472 static void vmclear_local_loaded_vmcss(void)
3473 {
3474         int cpu = raw_smp_processor_id();
3475         struct loaded_vmcs *v, *n;
3476
3477         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3478                                  loaded_vmcss_on_cpu_link)
3479                 __loaded_vmcs_clear(v);
3480 }
3481
3482
3483 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3484  * tricks.
3485  */
3486 static void kvm_cpu_vmxoff(void)
3487 {
3488         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3489
3490         intel_pt_handle_vmx(0);
3491 }
3492
3493 static void hardware_disable(void)
3494 {
3495         if (vmm_exclusive) {
3496                 vmclear_local_loaded_vmcss();
3497                 kvm_cpu_vmxoff();
3498         }
3499         cr4_clear_bits(X86_CR4_VMXE);
3500 }
3501
3502 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3503                                       u32 msr, u32 *result)
3504 {
3505         u32 vmx_msr_low, vmx_msr_high;
3506         u32 ctl = ctl_min | ctl_opt;
3507
3508         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3509
3510         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3511         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3512
3513         /* Ensure minimum (required) set of control bits are supported. */
3514         if (ctl_min & ~ctl)
3515                 return -EIO;
3516
3517         *result = ctl;
3518         return 0;
3519 }
3520
3521 static __init bool allow_1_setting(u32 msr, u32 ctl)
3522 {
3523         u32 vmx_msr_low, vmx_msr_high;
3524
3525         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3526         return vmx_msr_high & ctl;
3527 }
3528
3529 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3530 {
3531         u32 vmx_msr_low, vmx_msr_high;
3532         u32 min, opt, min2, opt2;
3533         u32 _pin_based_exec_control = 0;
3534         u32 _cpu_based_exec_control = 0;
3535         u32 _cpu_based_2nd_exec_control = 0;
3536         u32 _vmexit_control = 0;
3537         u32 _vmentry_control = 0;
3538
3539         min = CPU_BASED_HLT_EXITING |
3540 #ifdef CONFIG_X86_64
3541               CPU_BASED_CR8_LOAD_EXITING |
3542               CPU_BASED_CR8_STORE_EXITING |
3543 #endif
3544               CPU_BASED_CR3_LOAD_EXITING |
3545               CPU_BASED_CR3_STORE_EXITING |
3546               CPU_BASED_USE_IO_BITMAPS |
3547               CPU_BASED_MOV_DR_EXITING |
3548               CPU_BASED_USE_TSC_OFFSETING |
3549               CPU_BASED_MWAIT_EXITING |
3550               CPU_BASED_MONITOR_EXITING |
3551               CPU_BASED_INVLPG_EXITING |
3552               CPU_BASED_RDPMC_EXITING;
3553
3554         opt = CPU_BASED_TPR_SHADOW |
3555               CPU_BASED_USE_MSR_BITMAPS |
3556               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3557         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3558                                 &_cpu_based_exec_control) < 0)
3559                 return -EIO;
3560 #ifdef CONFIG_X86_64
3561         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3562                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3563                                            ~CPU_BASED_CR8_STORE_EXITING;
3564 #endif
3565         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3566                 min2 = 0;
3567                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3568                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3569                         SECONDARY_EXEC_WBINVD_EXITING |
3570                         SECONDARY_EXEC_ENABLE_VPID |
3571                         SECONDARY_EXEC_ENABLE_EPT |
3572                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3573                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3574                         SECONDARY_EXEC_RDTSCP |
3575                         SECONDARY_EXEC_ENABLE_INVPCID |
3576                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3577                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3578                         SECONDARY_EXEC_SHADOW_VMCS |
3579                         SECONDARY_EXEC_XSAVES |
3580                         SECONDARY_EXEC_ENABLE_PML |
3581                         SECONDARY_EXEC_TSC_SCALING;
3582                 if (adjust_vmx_controls(min2, opt2,
3583                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3584                                         &_cpu_based_2nd_exec_control) < 0)
3585                         return -EIO;
3586         }
3587 #ifndef CONFIG_X86_64
3588         if (!(_cpu_based_2nd_exec_control &
3589                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3590                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3591 #endif
3592
3593         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3594                 _cpu_based_2nd_exec_control &= ~(
3595                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3596                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3597                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3598
3599         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3600                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3601                    enabled */
3602                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3603                                              CPU_BASED_CR3_STORE_EXITING |
3604                                              CPU_BASED_INVLPG_EXITING);
3605                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3606                       vmx_capability.ept, vmx_capability.vpid);
3607         }
3608
3609         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3610 #ifdef CONFIG_X86_64
3611         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3612 #endif
3613         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3614                 VM_EXIT_CLEAR_BNDCFGS;
3615         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3616                                 &_vmexit_control) < 0)
3617                 return -EIO;
3618
3619         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3620                 PIN_BASED_VIRTUAL_NMIS;
3621         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3622         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3623                                 &_pin_based_exec_control) < 0)
3624                 return -EIO;
3625
3626         if (cpu_has_broken_vmx_preemption_timer())
3627                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3628         if (!(_cpu_based_2nd_exec_control &
3629                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3630                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3631
3632         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3633         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3634         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3635                                 &_vmentry_control) < 0)
3636                 return -EIO;
3637
3638         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3639
3640         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3641         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3642                 return -EIO;
3643
3644 #ifdef CONFIG_X86_64
3645         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3646         if (vmx_msr_high & (1u<<16))
3647                 return -EIO;
3648 #endif
3649
3650         /* Require Write-Back (WB) memory type for VMCS accesses. */
3651         if (((vmx_msr_high >> 18) & 15) != 6)
3652                 return -EIO;
3653
3654         vmcs_conf->size = vmx_msr_high & 0x1fff;
3655         vmcs_conf->order = get_order(vmcs_conf->size);
3656         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3657         vmcs_conf->revision_id = vmx_msr_low;
3658
3659         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3660         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3661         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3662         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3663         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3664
3665         cpu_has_load_ia32_efer =
3666                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3667                                 VM_ENTRY_LOAD_IA32_EFER)
3668                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3669                                    VM_EXIT_LOAD_IA32_EFER);
3670
3671         cpu_has_load_perf_global_ctrl =
3672                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3673                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3674                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3675                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3676
3677         /*
3678          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3679          * but due to errata below it can't be used. Workaround is to use
3680          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3681          *
3682          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3683          *
3684          * AAK155             (model 26)
3685          * AAP115             (model 30)
3686          * AAT100             (model 37)
3687          * BC86,AAY89,BD102   (model 44)
3688          * BA97               (model 46)
3689          *
3690          */
3691         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3692                 switch (boot_cpu_data.x86_model) {
3693                 case 26:
3694                 case 30:
3695                 case 37:
3696                 case 44:
3697                 case 46:
3698                         cpu_has_load_perf_global_ctrl = false;
3699                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3700                                         "does not work properly. Using workaround\n");
3701                         break;
3702                 default:
3703                         break;
3704                 }
3705         }
3706
3707         if (boot_cpu_has(X86_FEATURE_XSAVES))
3708                 rdmsrl(MSR_IA32_XSS, host_xss);
3709
3710         return 0;
3711 }
3712
3713 static struct vmcs *alloc_vmcs_cpu(int cpu)
3714 {
3715         int node = cpu_to_node(cpu);
3716         struct page *pages;
3717         struct vmcs *vmcs;
3718
3719         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3720         if (!pages)
3721                 return NULL;
3722         vmcs = page_address(pages);
3723         memset(vmcs, 0, vmcs_config.size);
3724         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3725         return vmcs;
3726 }
3727
3728 static struct vmcs *alloc_vmcs(void)
3729 {
3730         return alloc_vmcs_cpu(raw_smp_processor_id());
3731 }
3732
3733 static void free_vmcs(struct vmcs *vmcs)
3734 {
3735         free_pages((unsigned long)vmcs, vmcs_config.order);
3736 }
3737
3738 /*
3739  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3740  */
3741 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3742 {
3743         if (!loaded_vmcs->vmcs)
3744                 return;
3745         loaded_vmcs_clear(loaded_vmcs);
3746         free_vmcs(loaded_vmcs->vmcs);
3747         loaded_vmcs->vmcs = NULL;
3748         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3749 }
3750
3751 static void free_kvm_area(void)
3752 {
3753         int cpu;
3754
3755         for_each_possible_cpu(cpu) {
3756                 free_vmcs(per_cpu(vmxarea, cpu));
3757                 per_cpu(vmxarea, cpu) = NULL;
3758         }
3759 }
3760
3761 static void init_vmcs_shadow_fields(void)
3762 {
3763         int i, j;
3764
3765         /* No checks for read only fields yet */
3766
3767         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3768                 switch (shadow_read_write_fields[i]) {
3769                 case GUEST_BNDCFGS:
3770                         if (!kvm_mpx_supported())
3771                                 continue;
3772                         break;
3773                 default:
3774                         break;
3775                 }
3776
3777                 if (j < i)
3778                         shadow_read_write_fields[j] =
3779                                 shadow_read_write_fields[i];
3780                 j++;
3781         }
3782         max_shadow_read_write_fields = j;
3783
3784         /* shadowed fields guest access without vmexit */
3785         for (i = 0; i < max_shadow_read_write_fields; i++) {
3786                 clear_bit(shadow_read_write_fields[i],
3787                           vmx_vmwrite_bitmap);
3788                 clear_bit(shadow_read_write_fields[i],
3789                           vmx_vmread_bitmap);
3790         }
3791         for (i = 0; i < max_shadow_read_only_fields; i++)
3792                 clear_bit(shadow_read_only_fields[i],
3793                           vmx_vmread_bitmap);
3794 }
3795
3796 static __init int alloc_kvm_area(void)
3797 {
3798         int cpu;
3799
3800         for_each_possible_cpu(cpu) {
3801                 struct vmcs *vmcs;
3802
3803                 vmcs = alloc_vmcs_cpu(cpu);
3804                 if (!vmcs) {
3805                         free_kvm_area();
3806                         return -ENOMEM;
3807                 }
3808
3809                 per_cpu(vmxarea, cpu) = vmcs;
3810         }
3811         return 0;
3812 }
3813
3814 static bool emulation_required(struct kvm_vcpu *vcpu)
3815 {
3816         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3817 }
3818
3819 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3820                 struct kvm_segment *save)
3821 {
3822         if (!emulate_invalid_guest_state) {
3823                 /*
3824                  * CS and SS RPL should be equal during guest entry according
3825                  * to VMX spec, but in reality it is not always so. Since vcpu
3826                  * is in the middle of the transition from real mode to
3827                  * protected mode it is safe to assume that RPL 0 is a good
3828                  * default value.
3829                  */
3830                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3831                         save->selector &= ~SEGMENT_RPL_MASK;
3832                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3833                 save->s = 1;
3834         }
3835         vmx_set_segment(vcpu, save, seg);
3836 }
3837
3838 static void enter_pmode(struct kvm_vcpu *vcpu)
3839 {
3840         unsigned long flags;
3841         struct vcpu_vmx *vmx = to_vmx(vcpu);
3842
3843         /*
3844          * Update real mode segment cache. It may be not up-to-date if sement
3845          * register was written while vcpu was in a guest mode.
3846          */
3847         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3848         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3849         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3850         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3851         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3852         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3853
3854         vmx->rmode.vm86_active = 0;
3855
3856         vmx_segment_cache_clear(vmx);
3857
3858         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3859
3860         flags = vmcs_readl(GUEST_RFLAGS);
3861         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3862         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3863         vmcs_writel(GUEST_RFLAGS, flags);
3864
3865         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3866                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3867
3868         update_exception_bitmap(vcpu);
3869
3870         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3871         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3872         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3873         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3874         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3875         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3876 }
3877
3878 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3879 {
3880         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3881         struct kvm_segment var = *save;
3882
3883         var.dpl = 0x3;
3884         if (seg == VCPU_SREG_CS)
3885                 var.type = 0x3;
3886
3887         if (!emulate_invalid_guest_state) {
3888                 var.selector = var.base >> 4;
3889                 var.base = var.base & 0xffff0;
3890                 var.limit = 0xffff;
3891                 var.g = 0;
3892                 var.db = 0;
3893                 var.present = 1;
3894                 var.s = 1;
3895                 var.l = 0;
3896                 var.unusable = 0;
3897                 var.type = 0x3;
3898                 var.avl = 0;
3899                 if (save->base & 0xf)
3900                         printk_once(KERN_WARNING "kvm: segment base is not "
3901                                         "paragraph aligned when entering "
3902                                         "protected mode (seg=%d)", seg);
3903         }
3904
3905         vmcs_write16(sf->selector, var.selector);
3906         vmcs_writel(sf->base, var.base);
3907         vmcs_write32(sf->limit, var.limit);
3908         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3909 }
3910
3911 static void enter_rmode(struct kvm_vcpu *vcpu)
3912 {
3913         unsigned long flags;
3914         struct vcpu_vmx *vmx = to_vmx(vcpu);
3915
3916         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3917         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3918         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3919         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3920         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3921         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3922         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3923
3924         vmx->rmode.vm86_active = 1;
3925
3926         /*
3927          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3928          * vcpu. Warn the user that an update is overdue.
3929          */
3930         if (!vcpu->kvm->arch.tss_addr)
3931                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3932                              "called before entering vcpu\n");
3933
3934         vmx_segment_cache_clear(vmx);
3935
3936         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3937         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3938         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3939
3940         flags = vmcs_readl(GUEST_RFLAGS);
3941         vmx->rmode.save_rflags = flags;
3942
3943         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3944
3945         vmcs_writel(GUEST_RFLAGS, flags);
3946         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3947         update_exception_bitmap(vcpu);
3948
3949         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3950         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3951         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3952         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3953         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3954         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3955
3956         kvm_mmu_reset_context(vcpu);
3957 }
3958
3959 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3960 {
3961         struct vcpu_vmx *vmx = to_vmx(vcpu);
3962         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3963
3964         if (!msr)
3965                 return;
3966
3967         /*
3968          * Force kernel_gs_base reloading before EFER changes, as control
3969          * of this msr depends on is_long_mode().
3970          */
3971         vmx_load_host_state(to_vmx(vcpu));
3972         vcpu->arch.efer = efer;
3973         if (efer & EFER_LMA) {
3974                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3975                 msr->data = efer;
3976         } else {
3977                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3978
3979                 msr->data = efer & ~EFER_LME;
3980         }
3981         setup_msrs(vmx);
3982 }
3983
3984 #ifdef CONFIG_X86_64
3985
3986 static void enter_lmode(struct kvm_vcpu *vcpu)
3987 {
3988         u32 guest_tr_ar;
3989
3990         vmx_segment_cache_clear(to_vmx(vcpu));
3991
3992         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3993         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3994                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3995                                      __func__);
3996                 vmcs_write32(GUEST_TR_AR_BYTES,
3997                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3998                              | VMX_AR_TYPE_BUSY_64_TSS);
3999         }
4000         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4001 }
4002
4003 static void exit_lmode(struct kvm_vcpu *vcpu)
4004 {
4005         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4006         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4007 }
4008
4009 #endif
4010
4011 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4012 {
4013         if (enable_ept) {
4014                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4015                         return;
4016                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4017         } else {
4018                 vpid_sync_context(vpid);
4019         }
4020 }
4021
4022 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4023 {
4024         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4025 }
4026
4027 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4028 {
4029         if (enable_ept)
4030                 vmx_flush_tlb(vcpu);
4031 }
4032
4033 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4034 {
4035         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4036
4037         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4038         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4039 }
4040
4041 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4042 {
4043         if (enable_ept && is_paging(vcpu))
4044                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4045         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4046 }
4047
4048 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4049 {
4050         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4051
4052         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4053         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4054 }
4055
4056 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4057 {
4058         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4059
4060         if (!test_bit(VCPU_EXREG_PDPTR,
4061                       (unsigned long *)&vcpu->arch.regs_dirty))
4062                 return;
4063
4064         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4065                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4066                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4067                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4068                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4069         }
4070 }
4071
4072 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4073 {
4074         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4075
4076         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4077                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4078                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4079                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4080                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4081         }
4082
4083         __set_bit(VCPU_EXREG_PDPTR,
4084                   (unsigned long *)&vcpu->arch.regs_avail);
4085         __set_bit(VCPU_EXREG_PDPTR,
4086                   (unsigned long *)&vcpu->arch.regs_dirty);
4087 }
4088
4089 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4090 {
4091         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4092         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4093         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4094
4095         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4096                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4097             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4098                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4099
4100         return fixed_bits_valid(val, fixed0, fixed1);
4101 }
4102
4103 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4104 {
4105         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4106         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4107
4108         return fixed_bits_valid(val, fixed0, fixed1);
4109 }
4110
4111 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4112 {
4113         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4114         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4115
4116         return fixed_bits_valid(val, fixed0, fixed1);
4117 }
4118
4119 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4120 #define nested_guest_cr4_valid  nested_cr4_valid
4121 #define nested_host_cr4_valid   nested_cr4_valid
4122
4123 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4124
4125 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4126                                         unsigned long cr0,
4127                                         struct kvm_vcpu *vcpu)
4128 {
4129         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4130                 vmx_decache_cr3(vcpu);
4131         if (!(cr0 & X86_CR0_PG)) {
4132                 /* From paging/starting to nonpaging */
4133                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4134                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4135                              (CPU_BASED_CR3_LOAD_EXITING |
4136                               CPU_BASED_CR3_STORE_EXITING));
4137                 vcpu->arch.cr0 = cr0;
4138                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4139         } else if (!is_paging(vcpu)) {
4140                 /* From nonpaging to paging */
4141                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4142                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4143                              ~(CPU_BASED_CR3_LOAD_EXITING |
4144                                CPU_BASED_CR3_STORE_EXITING));
4145                 vcpu->arch.cr0 = cr0;
4146                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4147         }
4148
4149         if (!(cr0 & X86_CR0_WP))
4150                 *hw_cr0 &= ~X86_CR0_WP;
4151 }
4152
4153 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4154 {
4155         struct vcpu_vmx *vmx = to_vmx(vcpu);
4156         unsigned long hw_cr0;
4157
4158         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4159         if (enable_unrestricted_guest)
4160                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4161         else {
4162                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4163
4164                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4165                         enter_pmode(vcpu);
4166
4167                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4168                         enter_rmode(vcpu);
4169         }
4170
4171 #ifdef CONFIG_X86_64
4172         if (vcpu->arch.efer & EFER_LME) {
4173                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4174                         enter_lmode(vcpu);
4175                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4176                         exit_lmode(vcpu);
4177         }
4178 #endif
4179
4180         if (enable_ept)
4181                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4182
4183         vmcs_writel(CR0_READ_SHADOW, cr0);
4184         vmcs_writel(GUEST_CR0, hw_cr0);
4185         vcpu->arch.cr0 = cr0;
4186
4187         /* depends on vcpu->arch.cr0 to be set to a new value */
4188         vmx->emulation_required = emulation_required(vcpu);
4189 }
4190
4191 static u64 construct_eptp(unsigned long root_hpa)
4192 {
4193         u64 eptp;
4194
4195         /* TODO write the value reading from MSR */
4196         eptp = VMX_EPT_DEFAULT_MT |
4197                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4198         if (enable_ept_ad_bits)
4199                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4200         eptp |= (root_hpa & PAGE_MASK);
4201
4202         return eptp;
4203 }
4204
4205 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4206 {
4207         unsigned long guest_cr3;
4208         u64 eptp;
4209
4210         guest_cr3 = cr3;
4211         if (enable_ept) {
4212                 eptp = construct_eptp(cr3);
4213                 vmcs_write64(EPT_POINTER, eptp);
4214                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4215                         guest_cr3 = kvm_read_cr3(vcpu);
4216                 else
4217                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4218                 ept_load_pdptrs(vcpu);
4219         }
4220
4221         vmx_flush_tlb(vcpu);
4222         vmcs_writel(GUEST_CR3, guest_cr3);
4223 }
4224
4225 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4226 {
4227         /*
4228          * Pass through host's Machine Check Enable value to hw_cr4, which
4229          * is in force while we are in guest mode.  Do not let guests control
4230          * this bit, even if host CR4.MCE == 0.
4231          */
4232         unsigned long hw_cr4 =
4233                 (cr4_read_shadow() & X86_CR4_MCE) |
4234                 (cr4 & ~X86_CR4_MCE) |
4235                 (to_vmx(vcpu)->rmode.vm86_active ?
4236                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4237
4238         if (cr4 & X86_CR4_VMXE) {
4239                 /*
4240                  * To use VMXON (and later other VMX instructions), a guest
4241                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4242                  * So basically the check on whether to allow nested VMX
4243                  * is here.
4244                  */
4245                 if (!nested_vmx_allowed(vcpu))
4246                         return 1;
4247         }
4248
4249         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4250                 return 1;
4251
4252         vcpu->arch.cr4 = cr4;
4253         if (enable_ept) {
4254                 if (!is_paging(vcpu)) {
4255                         hw_cr4 &= ~X86_CR4_PAE;
4256                         hw_cr4 |= X86_CR4_PSE;
4257                 } else if (!(cr4 & X86_CR4_PAE)) {
4258                         hw_cr4 &= ~X86_CR4_PAE;
4259                 }
4260         }
4261
4262         if (!enable_unrestricted_guest && !is_paging(vcpu))
4263                 /*
4264                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4265                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4266                  * to be manually disabled when guest switches to non-paging
4267                  * mode.
4268                  *
4269                  * If !enable_unrestricted_guest, the CPU is always running
4270                  * with CR0.PG=1 and CR4 needs to be modified.
4271                  * If enable_unrestricted_guest, the CPU automatically
4272                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4273                  */
4274                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4275
4276         vmcs_writel(CR4_READ_SHADOW, cr4);
4277         vmcs_writel(GUEST_CR4, hw_cr4);
4278         return 0;
4279 }
4280
4281 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4282                             struct kvm_segment *var, int seg)
4283 {
4284         struct vcpu_vmx *vmx = to_vmx(vcpu);
4285         u32 ar;
4286
4287         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4288                 *var = vmx->rmode.segs[seg];
4289                 if (seg == VCPU_SREG_TR
4290                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4291                         return;
4292                 var->base = vmx_read_guest_seg_base(vmx, seg);
4293                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4294                 return;
4295         }
4296         var->base = vmx_read_guest_seg_base(vmx, seg);
4297         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4298         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4299         ar = vmx_read_guest_seg_ar(vmx, seg);
4300         var->unusable = (ar >> 16) & 1;
4301         var->type = ar & 15;
4302         var->s = (ar >> 4) & 1;
4303         var->dpl = (ar >> 5) & 3;
4304         /*
4305          * Some userspaces do not preserve unusable property. Since usable
4306          * segment has to be present according to VMX spec we can use present
4307          * property to amend userspace bug by making unusable segment always
4308          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4309          * segment as unusable.
4310          */
4311         var->present = !var->unusable;
4312         var->avl = (ar >> 12) & 1;
4313         var->l = (ar >> 13) & 1;
4314         var->db = (ar >> 14) & 1;
4315         var->g = (ar >> 15) & 1;
4316 }
4317
4318 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4319 {
4320         struct kvm_segment s;
4321
4322         if (to_vmx(vcpu)->rmode.vm86_active) {
4323                 vmx_get_segment(vcpu, &s, seg);
4324                 return s.base;
4325         }
4326         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4327 }
4328
4329 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4330 {
4331         struct vcpu_vmx *vmx = to_vmx(vcpu);
4332
4333         if (unlikely(vmx->rmode.vm86_active))
4334                 return 0;
4335         else {
4336                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4337                 return VMX_AR_DPL(ar);
4338         }
4339 }
4340
4341 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4342 {
4343         u32 ar;
4344
4345         if (var->unusable || !var->present)
4346                 ar = 1 << 16;
4347         else {
4348                 ar = var->type & 15;
4349                 ar |= (var->s & 1) << 4;
4350                 ar |= (var->dpl & 3) << 5;
4351                 ar |= (var->present & 1) << 7;
4352                 ar |= (var->avl & 1) << 12;
4353                 ar |= (var->l & 1) << 13;
4354                 ar |= (var->db & 1) << 14;
4355                 ar |= (var->g & 1) << 15;
4356         }
4357
4358         return ar;
4359 }
4360
4361 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4362                             struct kvm_segment *var, int seg)
4363 {
4364         struct vcpu_vmx *vmx = to_vmx(vcpu);
4365         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4366
4367         vmx_segment_cache_clear(vmx);
4368
4369         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4370                 vmx->rmode.segs[seg] = *var;
4371                 if (seg == VCPU_SREG_TR)
4372                         vmcs_write16(sf->selector, var->selector);
4373                 else if (var->s)
4374                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4375                 goto out;
4376         }
4377
4378         vmcs_writel(sf->base, var->base);
4379         vmcs_write32(sf->limit, var->limit);
4380         vmcs_write16(sf->selector, var->selector);
4381
4382         /*
4383          *   Fix the "Accessed" bit in AR field of segment registers for older
4384          * qemu binaries.
4385          *   IA32 arch specifies that at the time of processor reset the
4386          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4387          * is setting it to 0 in the userland code. This causes invalid guest
4388          * state vmexit when "unrestricted guest" mode is turned on.
4389          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4390          * tree. Newer qemu binaries with that qemu fix would not need this
4391          * kvm hack.
4392          */
4393         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4394                 var->type |= 0x1; /* Accessed */
4395
4396         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4397
4398 out:
4399         vmx->emulation_required = emulation_required(vcpu);
4400 }
4401
4402 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4403 {
4404         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4405
4406         *db = (ar >> 14) & 1;
4407         *l = (ar >> 13) & 1;
4408 }
4409
4410 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4411 {
4412         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4413         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4414 }
4415
4416 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4417 {
4418         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4419         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4420 }
4421
4422 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4423 {
4424         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4425         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4426 }
4427
4428 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4429 {
4430         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4431         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4432 }
4433
4434 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4435 {
4436         struct kvm_segment var;
4437         u32 ar;
4438
4439         vmx_get_segment(vcpu, &var, seg);
4440         var.dpl = 0x3;
4441         if (seg == VCPU_SREG_CS)
4442                 var.type = 0x3;
4443         ar = vmx_segment_access_rights(&var);
4444
4445         if (var.base != (var.selector << 4))
4446                 return false;
4447         if (var.limit != 0xffff)
4448                 return false;
4449         if (ar != 0xf3)
4450                 return false;
4451
4452         return true;
4453 }
4454
4455 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4456 {
4457         struct kvm_segment cs;
4458         unsigned int cs_rpl;
4459
4460         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4461         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4462
4463         if (cs.unusable)
4464                 return false;
4465         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4466                 return false;
4467         if (!cs.s)
4468                 return false;
4469         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4470                 if (cs.dpl > cs_rpl)
4471                         return false;
4472         } else {
4473                 if (cs.dpl != cs_rpl)
4474                         return false;
4475         }
4476         if (!cs.present)
4477                 return false;
4478
4479         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4480         return true;
4481 }
4482
4483 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4484 {
4485         struct kvm_segment ss;
4486         unsigned int ss_rpl;
4487
4488         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4489         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4490
4491         if (ss.unusable)
4492                 return true;
4493         if (ss.type != 3 && ss.type != 7)
4494                 return false;
4495         if (!ss.s)
4496                 return false;
4497         if (ss.dpl != ss_rpl) /* DPL != RPL */
4498                 return false;
4499         if (!ss.present)
4500                 return false;
4501
4502         return true;
4503 }
4504
4505 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4506 {
4507         struct kvm_segment var;
4508         unsigned int rpl;
4509
4510         vmx_get_segment(vcpu, &var, seg);
4511         rpl = var.selector & SEGMENT_RPL_MASK;
4512
4513         if (var.unusable)
4514                 return true;
4515         if (!var.s)
4516                 return false;
4517         if (!var.present)
4518                 return false;
4519         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4520                 if (var.dpl < rpl) /* DPL < RPL */
4521                         return false;
4522         }
4523
4524         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4525          * rights flags
4526          */
4527         return true;
4528 }
4529
4530 static bool tr_valid(struct kvm_vcpu *vcpu)
4531 {
4532         struct kvm_segment tr;
4533
4534         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4535
4536         if (tr.unusable)
4537                 return false;
4538         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4539                 return false;
4540         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4541                 return false;
4542         if (!tr.present)
4543                 return false;
4544
4545         return true;
4546 }
4547
4548 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4549 {
4550         struct kvm_segment ldtr;
4551
4552         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4553
4554         if (ldtr.unusable)
4555                 return true;
4556         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4557                 return false;
4558         if (ldtr.type != 2)
4559                 return false;
4560         if (!ldtr.present)
4561                 return false;
4562
4563         return true;
4564 }
4565
4566 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4567 {
4568         struct kvm_segment cs, ss;
4569
4570         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4571         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4572
4573         return ((cs.selector & SEGMENT_RPL_MASK) ==
4574                  (ss.selector & SEGMENT_RPL_MASK));
4575 }
4576
4577 /*
4578  * Check if guest state is valid. Returns true if valid, false if
4579  * not.
4580  * We assume that registers are always usable
4581  */
4582 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4583 {
4584         if (enable_unrestricted_guest)
4585                 return true;
4586
4587         /* real mode guest state checks */
4588         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4589                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4590                         return false;
4591                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4592                         return false;
4593                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4594                         return false;
4595                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4596                         return false;
4597                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4598                         return false;
4599                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4600                         return false;
4601         } else {
4602         /* protected mode guest state checks */
4603                 if (!cs_ss_rpl_check(vcpu))
4604                         return false;
4605                 if (!code_segment_valid(vcpu))
4606                         return false;
4607                 if (!stack_segment_valid(vcpu))
4608                         return false;
4609                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4610                         return false;
4611                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4612                         return false;
4613                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4614                         return false;
4615                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4616                         return false;
4617                 if (!tr_valid(vcpu))
4618                         return false;
4619                 if (!ldtr_valid(vcpu))
4620                         return false;
4621         }
4622         /* TODO:
4623          * - Add checks on RIP
4624          * - Add checks on RFLAGS
4625          */
4626
4627         return true;
4628 }
4629
4630 static int init_rmode_tss(struct kvm *kvm)
4631 {
4632         gfn_t fn;
4633         u16 data = 0;
4634         int idx, r;
4635
4636         idx = srcu_read_lock(&kvm->srcu);
4637         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4638         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4639         if (r < 0)
4640                 goto out;
4641         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4642         r = kvm_write_guest_page(kvm, fn++, &data,
4643                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4644         if (r < 0)
4645                 goto out;
4646         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4647         if (r < 0)
4648                 goto out;
4649         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4650         if (r < 0)
4651                 goto out;
4652         data = ~0;
4653         r = kvm_write_guest_page(kvm, fn, &data,
4654                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4655                                  sizeof(u8));
4656 out:
4657         srcu_read_unlock(&kvm->srcu, idx);
4658         return r;
4659 }
4660
4661 static int init_rmode_identity_map(struct kvm *kvm)
4662 {
4663         int i, idx, r = 0;
4664         kvm_pfn_t identity_map_pfn;
4665         u32 tmp;
4666
4667         if (!enable_ept)
4668                 return 0;
4669
4670         /* Protect kvm->arch.ept_identity_pagetable_done. */
4671         mutex_lock(&kvm->slots_lock);
4672
4673         if (likely(kvm->arch.ept_identity_pagetable_done))
4674                 goto out2;
4675
4676         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4677
4678         r = alloc_identity_pagetable(kvm);
4679         if (r < 0)
4680                 goto out2;
4681
4682         idx = srcu_read_lock(&kvm->srcu);
4683         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4684         if (r < 0)
4685                 goto out;
4686         /* Set up identity-mapping pagetable for EPT in real mode */
4687         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4688                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4689                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4690                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4691                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4692                 if (r < 0)
4693                         goto out;
4694         }
4695         kvm->arch.ept_identity_pagetable_done = true;
4696
4697 out:
4698         srcu_read_unlock(&kvm->srcu, idx);
4699
4700 out2:
4701         mutex_unlock(&kvm->slots_lock);
4702         return r;
4703 }
4704
4705 static void seg_setup(int seg)
4706 {
4707         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4708         unsigned int ar;
4709
4710         vmcs_write16(sf->selector, 0);
4711         vmcs_writel(sf->base, 0);
4712         vmcs_write32(sf->limit, 0xffff);
4713         ar = 0x93;
4714         if (seg == VCPU_SREG_CS)
4715                 ar |= 0x08; /* code segment */
4716
4717         vmcs_write32(sf->ar_bytes, ar);
4718 }
4719
4720 static int alloc_apic_access_page(struct kvm *kvm)
4721 {
4722         struct page *page;
4723         int r = 0;
4724
4725         mutex_lock(&kvm->slots_lock);
4726         if (kvm->arch.apic_access_page_done)
4727                 goto out;
4728         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4729                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4730         if (r)
4731                 goto out;
4732
4733         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4734         if (is_error_page(page)) {
4735                 r = -EFAULT;
4736                 goto out;
4737         }
4738
4739         /*
4740          * Do not pin the page in memory, so that memory hot-unplug
4741          * is able to migrate it.
4742          */
4743         put_page(page);
4744         kvm->arch.apic_access_page_done = true;
4745 out:
4746         mutex_unlock(&kvm->slots_lock);
4747         return r;
4748 }
4749
4750 static int alloc_identity_pagetable(struct kvm *kvm)
4751 {
4752         /* Called with kvm->slots_lock held. */
4753
4754         int r = 0;
4755
4756         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4757
4758         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4759                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4760
4761         return r;
4762 }
4763
4764 static int allocate_vpid(void)
4765 {
4766         int vpid;
4767
4768         if (!enable_vpid)
4769                 return 0;
4770         spin_lock(&vmx_vpid_lock);
4771         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4772         if (vpid < VMX_NR_VPIDS)
4773                 __set_bit(vpid, vmx_vpid_bitmap);
4774         else
4775                 vpid = 0;
4776         spin_unlock(&vmx_vpid_lock);
4777         return vpid;
4778 }
4779
4780 static void free_vpid(int vpid)
4781 {
4782         if (!enable_vpid || vpid == 0)
4783                 return;
4784         spin_lock(&vmx_vpid_lock);
4785         __clear_bit(vpid, vmx_vpid_bitmap);
4786         spin_unlock(&vmx_vpid_lock);
4787 }
4788
4789 #define MSR_TYPE_R      1
4790 #define MSR_TYPE_W      2
4791 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4792                                                 u32 msr, int type)
4793 {
4794         int f = sizeof(unsigned long);
4795
4796         if (!cpu_has_vmx_msr_bitmap())
4797                 return;
4798
4799         /*
4800          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4801          * have the write-low and read-high bitmap offsets the wrong way round.
4802          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4803          */
4804         if (msr <= 0x1fff) {
4805                 if (type & MSR_TYPE_R)
4806                         /* read-low */
4807                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4808
4809                 if (type & MSR_TYPE_W)
4810                         /* write-low */
4811                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4812
4813         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4814                 msr &= 0x1fff;
4815                 if (type & MSR_TYPE_R)
4816                         /* read-high */
4817                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4818
4819                 if (type & MSR_TYPE_W)
4820                         /* write-high */
4821                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4822
4823         }
4824 }
4825
4826 /*
4827  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4828  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4829  */
4830 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4831                                                unsigned long *msr_bitmap_nested,
4832                                                u32 msr, int type)
4833 {
4834         int f = sizeof(unsigned long);
4835
4836         if (!cpu_has_vmx_msr_bitmap()) {
4837                 WARN_ON(1);
4838                 return;
4839         }
4840
4841         /*
4842          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4843          * have the write-low and read-high bitmap offsets the wrong way round.
4844          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4845          */
4846         if (msr <= 0x1fff) {
4847                 if (type & MSR_TYPE_R &&
4848                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4849                         /* read-low */
4850                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4851
4852                 if (type & MSR_TYPE_W &&
4853                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4854                         /* write-low */
4855                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4856
4857         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4858                 msr &= 0x1fff;
4859                 if (type & MSR_TYPE_R &&
4860                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4861                         /* read-high */
4862                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4863
4864                 if (type & MSR_TYPE_W &&
4865                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4866                         /* write-high */
4867                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4868
4869         }
4870 }
4871
4872 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4873 {
4874         if (!longmode_only)
4875                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4876                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4877         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4878                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4879 }
4880
4881 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4882 {
4883         if (apicv_active) {
4884                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4885                                 msr, type);
4886                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4887                                 msr, type);
4888         } else {
4889                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4890                                 msr, type);
4891                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4892                                 msr, type);
4893         }
4894 }
4895
4896 static bool vmx_get_enable_apicv(void)
4897 {
4898         return enable_apicv;
4899 }
4900
4901 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4902 {
4903         struct vcpu_vmx *vmx = to_vmx(vcpu);
4904         int max_irr;
4905         void *vapic_page;
4906         u16 status;
4907
4908         if (vmx->nested.pi_desc &&
4909             vmx->nested.pi_pending) {
4910                 vmx->nested.pi_pending = false;
4911                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4912                         return;
4913
4914                 max_irr = find_last_bit(
4915                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4916
4917                 if (max_irr == 256)
4918                         return;
4919
4920                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4921                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4922                 kunmap(vmx->nested.virtual_apic_page);
4923
4924                 status = vmcs_read16(GUEST_INTR_STATUS);
4925                 if ((u8)max_irr > ((u8)status & 0xff)) {
4926                         status &= ~0xff;
4927                         status |= (u8)max_irr;
4928                         vmcs_write16(GUEST_INTR_STATUS, status);
4929                 }
4930         }
4931 }
4932
4933 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4934 {
4935 #ifdef CONFIG_SMP
4936         if (vcpu->mode == IN_GUEST_MODE) {
4937                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4938
4939                 /*
4940                  * Currently, we don't support urgent interrupt,
4941                  * all interrupts are recognized as non-urgent
4942                  * interrupt, so we cannot post interrupts when
4943                  * 'SN' is set.
4944                  *
4945                  * If the vcpu is in guest mode, it means it is
4946                  * running instead of being scheduled out and
4947                  * waiting in the run queue, and that's the only
4948                  * case when 'SN' is set currently, warning if
4949                  * 'SN' is set.
4950                  */
4951                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4952
4953                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4954                                 POSTED_INTR_VECTOR);
4955                 return true;
4956         }
4957 #endif
4958         return false;
4959 }
4960
4961 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4962                                                 int vector)
4963 {
4964         struct vcpu_vmx *vmx = to_vmx(vcpu);
4965
4966         if (is_guest_mode(vcpu) &&
4967             vector == vmx->nested.posted_intr_nv) {
4968                 /* the PIR and ON have been set by L1. */
4969                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4970                 /*
4971                  * If a posted intr is not recognized by hardware,
4972                  * we will accomplish it in the next vmentry.
4973                  */
4974                 vmx->nested.pi_pending = true;
4975                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4976                 return 0;
4977         }
4978         return -1;
4979 }
4980 /*
4981  * Send interrupt to vcpu via posted interrupt way.
4982  * 1. If target vcpu is running(non-root mode), send posted interrupt
4983  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4984  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4985  * interrupt from PIR in next vmentry.
4986  */
4987 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4988 {
4989         struct vcpu_vmx *vmx = to_vmx(vcpu);
4990         int r;
4991
4992         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4993         if (!r)
4994                 return;
4995
4996         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4997                 return;
4998
4999         /* If a previous notification has sent the IPI, nothing to do.  */
5000         if (pi_test_and_set_on(&vmx->pi_desc))
5001                 return;
5002
5003         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5004                 kvm_vcpu_kick(vcpu);
5005 }
5006
5007 /*
5008  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5009  * will not change in the lifetime of the guest.
5010  * Note that host-state that does change is set elsewhere. E.g., host-state
5011  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5012  */
5013 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5014 {
5015         u32 low32, high32;
5016         unsigned long tmpl;
5017         struct desc_ptr dt;
5018         unsigned long cr0, cr4;
5019
5020         cr0 = read_cr0();
5021         WARN_ON(cr0 & X86_CR0_TS);
5022         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5023         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5024
5025         /* Save the most likely value for this task's CR4 in the VMCS. */
5026         cr4 = cr4_read_shadow();
5027         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5028         vmx->host_state.vmcs_host_cr4 = cr4;
5029
5030         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5031 #ifdef CONFIG_X86_64
5032         /*
5033          * Load null selectors, so we can avoid reloading them in
5034          * __vmx_load_host_state(), in case userspace uses the null selectors
5035          * too (the expected case).
5036          */
5037         vmcs_write16(HOST_DS_SELECTOR, 0);
5038         vmcs_write16(HOST_ES_SELECTOR, 0);
5039 #else
5040         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5041         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5042 #endif
5043         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5044         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5045
5046         native_store_idt(&dt);
5047         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5048         vmx->host_idt_base = dt.address;
5049
5050         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5051
5052         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5053         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5054         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5055         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5056
5057         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5058                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5059                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5060         }
5061 }
5062
5063 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5064 {
5065         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5066         if (enable_ept)
5067                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5068         if (is_guest_mode(&vmx->vcpu))
5069                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5070                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5071         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5072 }
5073
5074 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5075 {
5076         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5077
5078         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5079                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5080         /* Enable the preemption timer dynamically */
5081         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5082         return pin_based_exec_ctrl;
5083 }
5084
5085 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5086 {
5087         struct vcpu_vmx *vmx = to_vmx(vcpu);
5088
5089         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5090         if (cpu_has_secondary_exec_ctrls()) {
5091                 if (kvm_vcpu_apicv_active(vcpu))
5092                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5093                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5094                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5095                 else
5096                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5097                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5098                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5099         }
5100
5101         if (cpu_has_vmx_msr_bitmap())
5102                 vmx_set_msr_bitmap(vcpu);
5103 }
5104
5105 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5106 {
5107         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5108
5109         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5110                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5111
5112         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5113                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5114 #ifdef CONFIG_X86_64
5115                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5116                                 CPU_BASED_CR8_LOAD_EXITING;
5117 #endif
5118         }
5119         if (!enable_ept)
5120                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5121                                 CPU_BASED_CR3_LOAD_EXITING  |
5122                                 CPU_BASED_INVLPG_EXITING;
5123         return exec_control;
5124 }
5125
5126 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5127 {
5128         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5129         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5130                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5131         if (vmx->vpid == 0)
5132                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5133         if (!enable_ept) {
5134                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5135                 enable_unrestricted_guest = 0;
5136                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5137                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5138         }
5139         if (!enable_unrestricted_guest)
5140                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5141         if (!ple_gap)
5142                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5143         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5144                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5145                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5146         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5147         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5148            (handle_vmptrld).
5149            We can NOT enable shadow_vmcs here because we don't have yet
5150            a current VMCS12
5151         */
5152         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5153
5154         if (!enable_pml)
5155                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5156
5157         return exec_control;
5158 }
5159
5160 static void ept_set_mmio_spte_mask(void)
5161 {
5162         /*
5163          * EPT Misconfigurations can be generated if the value of bits 2:0
5164          * of an EPT paging-structure entry is 110b (write/execute).
5165          */
5166         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5167 }
5168
5169 #define VMX_XSS_EXIT_BITMAP 0
5170 /*
5171  * Sets up the vmcs for emulated real mode.
5172  */
5173 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5174 {
5175 #ifdef CONFIG_X86_64
5176         unsigned long a;
5177 #endif
5178         int i;
5179
5180         /* I/O */
5181         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5182         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5183
5184         if (enable_shadow_vmcs) {
5185                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5186                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5187         }
5188         if (cpu_has_vmx_msr_bitmap())
5189                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5190
5191         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5192
5193         /* Control */
5194         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5195         vmx->hv_deadline_tsc = -1;
5196
5197         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5198
5199         if (cpu_has_secondary_exec_ctrls()) {
5200                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5201                                 vmx_secondary_exec_control(vmx));
5202         }
5203
5204         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5205                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5206                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5207                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5208                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5209
5210                 vmcs_write16(GUEST_INTR_STATUS, 0);
5211
5212                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5213                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5214         }
5215
5216         if (ple_gap) {
5217                 vmcs_write32(PLE_GAP, ple_gap);
5218                 vmx->ple_window = ple_window;
5219                 vmx->ple_window_dirty = true;
5220         }
5221
5222         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5223         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5224         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5225
5226         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5227         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5228         vmx_set_constant_host_state(vmx);
5229 #ifdef CONFIG_X86_64
5230         rdmsrl(MSR_FS_BASE, a);
5231         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5232         rdmsrl(MSR_GS_BASE, a);
5233         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5234 #else
5235         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5236         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5237 #endif
5238
5239         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5240         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5241         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5242         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5243         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5244
5245         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5246                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5247
5248         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5249                 u32 index = vmx_msr_index[i];
5250                 u32 data_low, data_high;
5251                 int j = vmx->nmsrs;
5252
5253                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5254                         continue;
5255                 if (wrmsr_safe(index, data_low, data_high) < 0)
5256                         continue;
5257                 vmx->guest_msrs[j].index = i;
5258                 vmx->guest_msrs[j].data = 0;
5259                 vmx->guest_msrs[j].mask = -1ull;
5260                 ++vmx->nmsrs;
5261         }
5262
5263
5264         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5265
5266         /* 22.2.1, 20.8.1 */
5267         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5268
5269         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5270         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5271
5272         set_cr4_guest_host_mask(vmx);
5273
5274         if (vmx_xsaves_supported())
5275                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5276
5277         if (enable_pml) {
5278                 ASSERT(vmx->pml_pg);
5279                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5280                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5281         }
5282
5283         return 0;
5284 }
5285
5286 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5287 {
5288         struct vcpu_vmx *vmx = to_vmx(vcpu);
5289         struct msr_data apic_base_msr;
5290         u64 cr0;
5291
5292         vmx->rmode.vm86_active = 0;
5293
5294         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5295         kvm_set_cr8(vcpu, 0);
5296
5297         if (!init_event) {
5298                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5299                                      MSR_IA32_APICBASE_ENABLE;
5300                 if (kvm_vcpu_is_reset_bsp(vcpu))
5301                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5302                 apic_base_msr.host_initiated = true;
5303                 kvm_set_apic_base(vcpu, &apic_base_msr);
5304         }
5305
5306         vmx_segment_cache_clear(vmx);
5307
5308         seg_setup(VCPU_SREG_CS);
5309         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5310         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5311
5312         seg_setup(VCPU_SREG_DS);
5313         seg_setup(VCPU_SREG_ES);
5314         seg_setup(VCPU_SREG_FS);
5315         seg_setup(VCPU_SREG_GS);
5316         seg_setup(VCPU_SREG_SS);
5317
5318         vmcs_write16(GUEST_TR_SELECTOR, 0);
5319         vmcs_writel(GUEST_TR_BASE, 0);
5320         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5321         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5322
5323         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5324         vmcs_writel(GUEST_LDTR_BASE, 0);
5325         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5326         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5327
5328         if (!init_event) {
5329                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5330                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5331                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5332                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5333         }
5334
5335         vmcs_writel(GUEST_RFLAGS, 0x02);
5336         kvm_rip_write(vcpu, 0xfff0);
5337
5338         vmcs_writel(GUEST_GDTR_BASE, 0);
5339         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5340
5341         vmcs_writel(GUEST_IDTR_BASE, 0);
5342         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5343
5344         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5345         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5346         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5347
5348         setup_msrs(vmx);
5349
5350         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5351
5352         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5353                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5354                 if (cpu_need_tpr_shadow(vcpu))
5355                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5356                                      __pa(vcpu->arch.apic->regs));
5357                 vmcs_write32(TPR_THRESHOLD, 0);
5358         }
5359
5360         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5361
5362         if (kvm_vcpu_apicv_active(vcpu))
5363                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5364
5365         if (vmx->vpid != 0)
5366                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5367
5368         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5369         vmx->vcpu.arch.cr0 = cr0;
5370         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5371         vmx_set_cr4(vcpu, 0);
5372         vmx_set_efer(vcpu, 0);
5373
5374         update_exception_bitmap(vcpu);
5375
5376         vpid_sync_context(vmx->vpid);
5377 }
5378
5379 /*
5380  * In nested virtualization, check if L1 asked to exit on external interrupts.
5381  * For most existing hypervisors, this will always return true.
5382  */
5383 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5384 {
5385         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5386                 PIN_BASED_EXT_INTR_MASK;
5387 }
5388
5389 /*
5390  * In nested virtualization, check if L1 has set
5391  * VM_EXIT_ACK_INTR_ON_EXIT
5392  */
5393 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5394 {
5395         return get_vmcs12(vcpu)->vm_exit_controls &
5396                 VM_EXIT_ACK_INTR_ON_EXIT;
5397 }
5398
5399 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5400 {
5401         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5402                 PIN_BASED_NMI_EXITING;
5403 }
5404
5405 static void enable_irq_window(struct kvm_vcpu *vcpu)
5406 {
5407         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5408                       CPU_BASED_VIRTUAL_INTR_PENDING);
5409 }
5410
5411 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5412 {
5413         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5414                 enable_irq_window(vcpu);
5415                 return;
5416         }
5417
5418         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5419                       CPU_BASED_VIRTUAL_NMI_PENDING);
5420 }
5421
5422 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5423 {
5424         struct vcpu_vmx *vmx = to_vmx(vcpu);
5425         uint32_t intr;
5426         int irq = vcpu->arch.interrupt.nr;
5427
5428         trace_kvm_inj_virq(irq);
5429
5430         ++vcpu->stat.irq_injections;
5431         if (vmx->rmode.vm86_active) {
5432                 int inc_eip = 0;
5433                 if (vcpu->arch.interrupt.soft)
5434                         inc_eip = vcpu->arch.event_exit_inst_len;
5435                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5436                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5437                 return;
5438         }
5439         intr = irq | INTR_INFO_VALID_MASK;
5440         if (vcpu->arch.interrupt.soft) {
5441                 intr |= INTR_TYPE_SOFT_INTR;
5442                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5443                              vmx->vcpu.arch.event_exit_inst_len);
5444         } else
5445                 intr |= INTR_TYPE_EXT_INTR;
5446         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5447 }
5448
5449 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5450 {
5451         struct vcpu_vmx *vmx = to_vmx(vcpu);
5452
5453         if (!is_guest_mode(vcpu)) {
5454                 ++vcpu->stat.nmi_injections;
5455                 vmx->nmi_known_unmasked = false;
5456         }
5457
5458         if (vmx->rmode.vm86_active) {
5459                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5460                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5461                 return;
5462         }
5463
5464         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5465                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5466 }
5467
5468 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5469 {
5470         if (to_vmx(vcpu)->nmi_known_unmasked)
5471                 return false;
5472         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5473 }
5474
5475 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5476 {
5477         struct vcpu_vmx *vmx = to_vmx(vcpu);
5478
5479         vmx->nmi_known_unmasked = !masked;
5480         if (masked)
5481                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5482                               GUEST_INTR_STATE_NMI);
5483         else
5484                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5485                                 GUEST_INTR_STATE_NMI);
5486 }
5487
5488 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5489 {
5490         if (to_vmx(vcpu)->nested.nested_run_pending)
5491                 return 0;
5492
5493         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5494                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5495                    | GUEST_INTR_STATE_NMI));
5496 }
5497
5498 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5499 {
5500         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5501                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5502                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5503                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5504 }
5505
5506 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5507 {
5508         int ret;
5509
5510         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5511                                     PAGE_SIZE * 3);
5512         if (ret)
5513                 return ret;
5514         kvm->arch.tss_addr = addr;
5515         return init_rmode_tss(kvm);
5516 }
5517
5518 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5519 {
5520         switch (vec) {
5521         case BP_VECTOR:
5522                 /*
5523                  * Update instruction length as we may reinject the exception
5524                  * from user space while in guest debugging mode.
5525                  */
5526                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5527                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5528                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5529                         return false;
5530                 /* fall through */
5531         case DB_VECTOR:
5532                 if (vcpu->guest_debug &
5533                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5534                         return false;
5535                 /* fall through */
5536         case DE_VECTOR:
5537         case OF_VECTOR:
5538         case BR_VECTOR:
5539         case UD_VECTOR:
5540         case DF_VECTOR:
5541         case SS_VECTOR:
5542         case GP_VECTOR:
5543         case MF_VECTOR:
5544                 return true;
5545         break;
5546         }
5547         return false;
5548 }
5549
5550 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5551                                   int vec, u32 err_code)
5552 {
5553         /*
5554          * Instruction with address size override prefix opcode 0x67
5555          * Cause the #SS fault with 0 error code in VM86 mode.
5556          */
5557         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5558                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5559                         if (vcpu->arch.halt_request) {
5560                                 vcpu->arch.halt_request = 0;
5561                                 return kvm_vcpu_halt(vcpu);
5562                         }
5563                         return 1;
5564                 }
5565                 return 0;
5566         }
5567
5568         /*
5569          * Forward all other exceptions that are valid in real mode.
5570          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5571          *        the required debugging infrastructure rework.
5572          */
5573         kvm_queue_exception(vcpu, vec);
5574         return 1;
5575 }
5576
5577 /*
5578  * Trigger machine check on the host. We assume all the MSRs are already set up
5579  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5580  * We pass a fake environment to the machine check handler because we want
5581  * the guest to be always treated like user space, no matter what context
5582  * it used internally.
5583  */
5584 static void kvm_machine_check(void)
5585 {
5586 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5587         struct pt_regs regs = {
5588                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5589                 .flags = X86_EFLAGS_IF,
5590         };
5591
5592         do_machine_check(&regs, 0);
5593 #endif
5594 }
5595
5596 static int handle_machine_check(struct kvm_vcpu *vcpu)
5597 {
5598         /* already handled by vcpu_run */
5599         return 1;
5600 }
5601
5602 static int handle_exception(struct kvm_vcpu *vcpu)
5603 {
5604         struct vcpu_vmx *vmx = to_vmx(vcpu);
5605         struct kvm_run *kvm_run = vcpu->run;
5606         u32 intr_info, ex_no, error_code;
5607         unsigned long cr2, rip, dr6;
5608         u32 vect_info;
5609         enum emulation_result er;
5610
5611         vect_info = vmx->idt_vectoring_info;
5612         intr_info = vmx->exit_intr_info;
5613
5614         if (is_machine_check(intr_info))
5615                 return handle_machine_check(vcpu);
5616
5617         if (is_nmi(intr_info))
5618                 return 1;  /* already handled by vmx_vcpu_run() */
5619
5620         if (is_invalid_opcode(intr_info)) {
5621                 if (is_guest_mode(vcpu)) {
5622                         kvm_queue_exception(vcpu, UD_VECTOR);
5623                         return 1;
5624                 }
5625                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5626                 if (er != EMULATE_DONE)
5627                         kvm_queue_exception(vcpu, UD_VECTOR);
5628                 return 1;
5629         }
5630
5631         error_code = 0;
5632         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5633                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5634
5635         /*
5636          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5637          * MMIO, it is better to report an internal error.
5638          * See the comments in vmx_handle_exit.
5639          */
5640         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5641             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5642                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5643                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5644                 vcpu->run->internal.ndata = 3;
5645                 vcpu->run->internal.data[0] = vect_info;
5646                 vcpu->run->internal.data[1] = intr_info;
5647                 vcpu->run->internal.data[2] = error_code;
5648                 return 0;
5649         }
5650
5651         if (is_page_fault(intr_info)) {
5652                 /* EPT won't cause page fault directly */
5653                 BUG_ON(enable_ept);
5654                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5655                 trace_kvm_page_fault(cr2, error_code);
5656
5657                 if (kvm_event_needs_reinjection(vcpu))
5658                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5659                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5660         }
5661
5662         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5663
5664         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5665                 return handle_rmode_exception(vcpu, ex_no, error_code);
5666
5667         switch (ex_no) {
5668         case AC_VECTOR:
5669                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5670                 return 1;
5671         case DB_VECTOR:
5672                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5673                 if (!(vcpu->guest_debug &
5674                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5675                         vcpu->arch.dr6 &= ~15;
5676                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5677                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5678                                 skip_emulated_instruction(vcpu);
5679
5680                         kvm_queue_exception(vcpu, DB_VECTOR);
5681                         return 1;
5682                 }
5683                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5684                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5685                 /* fall through */
5686         case BP_VECTOR:
5687                 /*
5688                  * Update instruction length as we may reinject #BP from
5689                  * user space while in guest debugging mode. Reading it for
5690                  * #DB as well causes no harm, it is not used in that case.
5691                  */
5692                 vmx->vcpu.arch.event_exit_inst_len =
5693                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5694                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5695                 rip = kvm_rip_read(vcpu);
5696                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5697                 kvm_run->debug.arch.exception = ex_no;
5698                 break;
5699         default:
5700                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5701                 kvm_run->ex.exception = ex_no;
5702                 kvm_run->ex.error_code = error_code;
5703                 break;
5704         }
5705         return 0;
5706 }
5707
5708 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5709 {
5710         ++vcpu->stat.irq_exits;
5711         return 1;
5712 }
5713
5714 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5715 {
5716         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5717         return 0;
5718 }
5719
5720 static int handle_io(struct kvm_vcpu *vcpu)
5721 {
5722         unsigned long exit_qualification;
5723         int size, in, string, ret;
5724         unsigned port;
5725
5726         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5727         string = (exit_qualification & 16) != 0;
5728         in = (exit_qualification & 8) != 0;
5729
5730         ++vcpu->stat.io_exits;
5731
5732         if (string || in)
5733                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5734
5735         port = exit_qualification >> 16;
5736         size = (exit_qualification & 7) + 1;
5737
5738         ret = kvm_skip_emulated_instruction(vcpu);
5739
5740         /*
5741          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5742          * KVM_EXIT_DEBUG here.
5743          */
5744         return kvm_fast_pio_out(vcpu, size, port) && ret;
5745 }
5746
5747 static void
5748 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5749 {
5750         /*
5751          * Patch in the VMCALL instruction:
5752          */
5753         hypercall[0] = 0x0f;
5754         hypercall[1] = 0x01;
5755         hypercall[2] = 0xc1;
5756 }
5757
5758 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5759 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5760 {
5761         if (is_guest_mode(vcpu)) {
5762                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5763                 unsigned long orig_val = val;
5764
5765                 /*
5766                  * We get here when L2 changed cr0 in a way that did not change
5767                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5768                  * but did change L0 shadowed bits. So we first calculate the
5769                  * effective cr0 value that L1 would like to write into the
5770                  * hardware. It consists of the L2-owned bits from the new
5771                  * value combined with the L1-owned bits from L1's guest_cr0.
5772                  */
5773                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5774                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5775
5776                 if (!nested_guest_cr0_valid(vcpu, val))
5777                         return 1;
5778
5779                 if (kvm_set_cr0(vcpu, val))
5780                         return 1;
5781                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5782                 return 0;
5783         } else {
5784                 if (to_vmx(vcpu)->nested.vmxon &&
5785                     !nested_host_cr0_valid(vcpu, val))
5786                         return 1;
5787
5788                 return kvm_set_cr0(vcpu, val);
5789         }
5790 }
5791
5792 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5793 {
5794         if (is_guest_mode(vcpu)) {
5795                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5796                 unsigned long orig_val = val;
5797
5798                 /* analogously to handle_set_cr0 */
5799                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5800                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5801                 if (kvm_set_cr4(vcpu, val))
5802                         return 1;
5803                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5804                 return 0;
5805         } else
5806                 return kvm_set_cr4(vcpu, val);
5807 }
5808
5809 static int handle_cr(struct kvm_vcpu *vcpu)
5810 {
5811         unsigned long exit_qualification, val;
5812         int cr;
5813         int reg;
5814         int err;
5815         int ret;
5816
5817         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5818         cr = exit_qualification & 15;
5819         reg = (exit_qualification >> 8) & 15;
5820         switch ((exit_qualification >> 4) & 3) {
5821         case 0: /* mov to cr */
5822                 val = kvm_register_readl(vcpu, reg);
5823                 trace_kvm_cr_write(cr, val);
5824                 switch (cr) {
5825                 case 0:
5826                         err = handle_set_cr0(vcpu, val);
5827                         return kvm_complete_insn_gp(vcpu, err);
5828                 case 3:
5829                         err = kvm_set_cr3(vcpu, val);
5830                         return kvm_complete_insn_gp(vcpu, err);
5831                 case 4:
5832                         err = handle_set_cr4(vcpu, val);
5833                         return kvm_complete_insn_gp(vcpu, err);
5834                 case 8: {
5835                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5836                                 u8 cr8 = (u8)val;
5837                                 err = kvm_set_cr8(vcpu, cr8);
5838                                 ret = kvm_complete_insn_gp(vcpu, err);
5839                                 if (lapic_in_kernel(vcpu))
5840                                         return ret;
5841                                 if (cr8_prev <= cr8)
5842                                         return ret;
5843                                 /*
5844                                  * TODO: we might be squashing a
5845                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5846                                  * KVM_EXIT_DEBUG here.
5847                                  */
5848                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5849                                 return 0;
5850                         }
5851                 }
5852                 break;
5853         case 2: /* clts */
5854                 WARN_ONCE(1, "Guest should always own CR0.TS");
5855                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5856                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5857                 return kvm_skip_emulated_instruction(vcpu);
5858         case 1: /*mov from cr*/
5859                 switch (cr) {
5860                 case 3:
5861                         val = kvm_read_cr3(vcpu);
5862                         kvm_register_write(vcpu, reg, val);
5863                         trace_kvm_cr_read(cr, val);
5864                         return kvm_skip_emulated_instruction(vcpu);
5865                 case 8:
5866                         val = kvm_get_cr8(vcpu);
5867                         kvm_register_write(vcpu, reg, val);
5868                         trace_kvm_cr_read(cr, val);
5869                         return kvm_skip_emulated_instruction(vcpu);
5870                 }
5871                 break;
5872         case 3: /* lmsw */
5873                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5874                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5875                 kvm_lmsw(vcpu, val);
5876
5877                 return kvm_skip_emulated_instruction(vcpu);
5878         default:
5879                 break;
5880         }
5881         vcpu->run->exit_reason = 0;
5882         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5883                (int)(exit_qualification >> 4) & 3, cr);
5884         return 0;
5885 }
5886
5887 static int handle_dr(struct kvm_vcpu *vcpu)
5888 {
5889         unsigned long exit_qualification;
5890         int dr, dr7, reg;
5891
5892         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5893         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5894
5895         /* First, if DR does not exist, trigger UD */
5896         if (!kvm_require_dr(vcpu, dr))
5897                 return 1;
5898
5899         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5900         if (!kvm_require_cpl(vcpu, 0))
5901                 return 1;
5902         dr7 = vmcs_readl(GUEST_DR7);
5903         if (dr7 & DR7_GD) {
5904                 /*
5905                  * As the vm-exit takes precedence over the debug trap, we
5906                  * need to emulate the latter, either for the host or the
5907                  * guest debugging itself.
5908                  */
5909                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5910                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5911                         vcpu->run->debug.arch.dr7 = dr7;
5912                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5913                         vcpu->run->debug.arch.exception = DB_VECTOR;
5914                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5915                         return 0;
5916                 } else {
5917                         vcpu->arch.dr6 &= ~15;
5918                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5919                         kvm_queue_exception(vcpu, DB_VECTOR);
5920                         return 1;
5921                 }
5922         }
5923
5924         if (vcpu->guest_debug == 0) {
5925                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5926                                 CPU_BASED_MOV_DR_EXITING);
5927
5928                 /*
5929                  * No more DR vmexits; force a reload of the debug registers
5930                  * and reenter on this instruction.  The next vmexit will
5931                  * retrieve the full state of the debug registers.
5932                  */
5933                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5934                 return 1;
5935         }
5936
5937         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5938         if (exit_qualification & TYPE_MOV_FROM_DR) {
5939                 unsigned long val;
5940
5941                 if (kvm_get_dr(vcpu, dr, &val))
5942                         return 1;
5943                 kvm_register_write(vcpu, reg, val);
5944         } else
5945                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5946                         return 1;
5947
5948         return kvm_skip_emulated_instruction(vcpu);
5949 }
5950
5951 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5952 {
5953         return vcpu->arch.dr6;
5954 }
5955
5956 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5957 {
5958 }
5959
5960 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5961 {
5962         get_debugreg(vcpu->arch.db[0], 0);
5963         get_debugreg(vcpu->arch.db[1], 1);
5964         get_debugreg(vcpu->arch.db[2], 2);
5965         get_debugreg(vcpu->arch.db[3], 3);
5966         get_debugreg(vcpu->arch.dr6, 6);
5967         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5968
5969         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5970         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5971 }
5972
5973 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5974 {
5975         vmcs_writel(GUEST_DR7, val);
5976 }
5977
5978 static int handle_cpuid(struct kvm_vcpu *vcpu)
5979 {
5980         return kvm_emulate_cpuid(vcpu);
5981 }
5982
5983 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5984 {
5985         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5986         struct msr_data msr_info;
5987
5988         msr_info.index = ecx;
5989         msr_info.host_initiated = false;
5990         if (vmx_get_msr(vcpu, &msr_info)) {
5991                 trace_kvm_msr_read_ex(ecx);
5992                 kvm_inject_gp(vcpu, 0);
5993                 return 1;
5994         }
5995
5996         trace_kvm_msr_read(ecx, msr_info.data);
5997
5998         /* FIXME: handling of bits 32:63 of rax, rdx */
5999         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6000         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6001         return kvm_skip_emulated_instruction(vcpu);
6002 }
6003
6004 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6005 {
6006         struct msr_data msr;
6007         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6008         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6009                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6010
6011         msr.data = data;
6012         msr.index = ecx;
6013         msr.host_initiated = false;
6014         if (kvm_set_msr(vcpu, &msr) != 0) {
6015                 trace_kvm_msr_write_ex(ecx, data);
6016                 kvm_inject_gp(vcpu, 0);
6017                 return 1;
6018         }
6019
6020         trace_kvm_msr_write(ecx, data);
6021         return kvm_skip_emulated_instruction(vcpu);
6022 }
6023
6024 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6025 {
6026         kvm_apic_update_ppr(vcpu);
6027         return 1;
6028 }
6029
6030 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6031 {
6032         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6033                         CPU_BASED_VIRTUAL_INTR_PENDING);
6034
6035         kvm_make_request(KVM_REQ_EVENT, vcpu);
6036
6037         ++vcpu->stat.irq_window_exits;
6038         return 1;
6039 }
6040
6041 static int handle_halt(struct kvm_vcpu *vcpu)
6042 {
6043         return kvm_emulate_halt(vcpu);
6044 }
6045
6046 static int handle_vmcall(struct kvm_vcpu *vcpu)
6047 {
6048         return kvm_emulate_hypercall(vcpu);
6049 }
6050
6051 static int handle_invd(struct kvm_vcpu *vcpu)
6052 {
6053         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6054 }
6055
6056 static int handle_invlpg(struct kvm_vcpu *vcpu)
6057 {
6058         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6059
6060         kvm_mmu_invlpg(vcpu, exit_qualification);
6061         return kvm_skip_emulated_instruction(vcpu);
6062 }
6063
6064 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6065 {
6066         int err;
6067
6068         err = kvm_rdpmc(vcpu);
6069         return kvm_complete_insn_gp(vcpu, err);
6070 }
6071
6072 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6073 {
6074         return kvm_emulate_wbinvd(vcpu);
6075 }
6076
6077 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6078 {
6079         u64 new_bv = kvm_read_edx_eax(vcpu);
6080         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6081
6082         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6083                 return kvm_skip_emulated_instruction(vcpu);
6084         return 1;
6085 }
6086
6087 static int handle_xsaves(struct kvm_vcpu *vcpu)
6088 {
6089         kvm_skip_emulated_instruction(vcpu);
6090         WARN(1, "this should never happen\n");
6091         return 1;
6092 }
6093
6094 static int handle_xrstors(struct kvm_vcpu *vcpu)
6095 {
6096         kvm_skip_emulated_instruction(vcpu);
6097         WARN(1, "this should never happen\n");
6098         return 1;
6099 }
6100
6101 static int handle_apic_access(struct kvm_vcpu *vcpu)
6102 {
6103         if (likely(fasteoi)) {
6104                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6105                 int access_type, offset;
6106
6107                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6108                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6109                 /*
6110                  * Sane guest uses MOV to write EOI, with written value
6111                  * not cared. So make a short-circuit here by avoiding
6112                  * heavy instruction emulation.
6113                  */
6114                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6115                     (offset == APIC_EOI)) {
6116                         kvm_lapic_set_eoi(vcpu);
6117                         return kvm_skip_emulated_instruction(vcpu);
6118                 }
6119         }
6120         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6121 }
6122
6123 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6124 {
6125         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6126         int vector = exit_qualification & 0xff;
6127
6128         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6129         kvm_apic_set_eoi_accelerated(vcpu, vector);
6130         return 1;
6131 }
6132
6133 static int handle_apic_write(struct kvm_vcpu *vcpu)
6134 {
6135         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6136         u32 offset = exit_qualification & 0xfff;
6137
6138         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6139         kvm_apic_write_nodecode(vcpu, offset);
6140         return 1;
6141 }
6142
6143 static int handle_task_switch(struct kvm_vcpu *vcpu)
6144 {
6145         struct vcpu_vmx *vmx = to_vmx(vcpu);
6146         unsigned long exit_qualification;
6147         bool has_error_code = false;
6148         u32 error_code = 0;
6149         u16 tss_selector;
6150         int reason, type, idt_v, idt_index;
6151
6152         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6153         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6154         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6155
6156         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6157
6158         reason = (u32)exit_qualification >> 30;
6159         if (reason == TASK_SWITCH_GATE && idt_v) {
6160                 switch (type) {
6161                 case INTR_TYPE_NMI_INTR:
6162                         vcpu->arch.nmi_injected = false;
6163                         vmx_set_nmi_mask(vcpu, true);
6164                         break;
6165                 case INTR_TYPE_EXT_INTR:
6166                 case INTR_TYPE_SOFT_INTR:
6167                         kvm_clear_interrupt_queue(vcpu);
6168                         break;
6169                 case INTR_TYPE_HARD_EXCEPTION:
6170                         if (vmx->idt_vectoring_info &
6171                             VECTORING_INFO_DELIVER_CODE_MASK) {
6172                                 has_error_code = true;
6173                                 error_code =
6174                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6175                         }
6176                         /* fall through */
6177                 case INTR_TYPE_SOFT_EXCEPTION:
6178                         kvm_clear_exception_queue(vcpu);
6179                         break;
6180                 default:
6181                         break;
6182                 }
6183         }
6184         tss_selector = exit_qualification;
6185
6186         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6187                        type != INTR_TYPE_EXT_INTR &&
6188                        type != INTR_TYPE_NMI_INTR))
6189                 skip_emulated_instruction(vcpu);
6190
6191         if (kvm_task_switch(vcpu, tss_selector,
6192                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6193                             has_error_code, error_code) == EMULATE_FAIL) {
6194                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6195                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6196                 vcpu->run->internal.ndata = 0;
6197                 return 0;
6198         }
6199
6200         /*
6201          * TODO: What about debug traps on tss switch?
6202          *       Are we supposed to inject them and update dr6?
6203          */
6204
6205         return 1;
6206 }
6207
6208 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6209 {
6210         unsigned long exit_qualification;
6211         gpa_t gpa;
6212         u32 error_code;
6213
6214         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6215
6216         if (is_guest_mode(vcpu)
6217             && !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
6218                 /*
6219                  * Fix up exit_qualification according to whether guest
6220                  * page table accesses are reads or writes.
6221                  */
6222                 u64 eptp = nested_ept_get_cr3(vcpu);
6223                 if (eptp & VMX_EPT_AD_ENABLE_BIT)
6224                         exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
6225         }
6226
6227         /*
6228          * EPT violation happened while executing iret from NMI,
6229          * "blocked by NMI" bit has to be set before next VM entry.
6230          * There are errata that may cause this bit to not be set:
6231          * AAK134, BY25.
6232          */
6233         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6234                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6235                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6236
6237         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6238         trace_kvm_page_fault(gpa, exit_qualification);
6239
6240         /* Is it a read fault? */
6241         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6242                      ? PFERR_USER_MASK : 0;
6243         /* Is it a write fault? */
6244         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6245                       ? PFERR_WRITE_MASK : 0;
6246         /* Is it a fetch fault? */
6247         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6248                       ? PFERR_FETCH_MASK : 0;
6249         /* ept page table entry is present? */
6250         error_code |= (exit_qualification &
6251                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6252                         EPT_VIOLATION_EXECUTABLE))
6253                       ? PFERR_PRESENT_MASK : 0;
6254
6255         vcpu->arch.gpa_available = true;
6256         vcpu->arch.exit_qualification = exit_qualification;
6257
6258         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6259 }
6260
6261 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6262 {
6263         int ret;
6264         gpa_t gpa;
6265
6266         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6267         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6268                 trace_kvm_fast_mmio(gpa);
6269                 return kvm_skip_emulated_instruction(vcpu);
6270         }
6271
6272         ret = handle_mmio_page_fault(vcpu, gpa, true);
6273         vcpu->arch.gpa_available = true;
6274         if (likely(ret == RET_MMIO_PF_EMULATE))
6275                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6276                                               EMULATE_DONE;
6277
6278         if (unlikely(ret == RET_MMIO_PF_INVALID))
6279                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6280
6281         if (unlikely(ret == RET_MMIO_PF_RETRY))
6282                 return 1;
6283
6284         /* It is the real ept misconfig */
6285         WARN_ON(1);
6286
6287         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6288         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6289
6290         return 0;
6291 }
6292
6293 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6294 {
6295         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6296                         CPU_BASED_VIRTUAL_NMI_PENDING);
6297         ++vcpu->stat.nmi_window_exits;
6298         kvm_make_request(KVM_REQ_EVENT, vcpu);
6299
6300         return 1;
6301 }
6302
6303 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6304 {
6305         struct vcpu_vmx *vmx = to_vmx(vcpu);
6306         enum emulation_result err = EMULATE_DONE;
6307         int ret = 1;
6308         u32 cpu_exec_ctrl;
6309         bool intr_window_requested;
6310         unsigned count = 130;
6311
6312         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6313         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6314
6315         while (vmx->emulation_required && count-- != 0) {
6316                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6317                         return handle_interrupt_window(&vmx->vcpu);
6318
6319                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6320                         return 1;
6321
6322                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6323
6324                 if (err == EMULATE_USER_EXIT) {
6325                         ++vcpu->stat.mmio_exits;
6326                         ret = 0;
6327                         goto out;
6328                 }
6329
6330                 if (err != EMULATE_DONE) {
6331                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6332                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6333                         vcpu->run->internal.ndata = 0;
6334                         return 0;
6335                 }
6336
6337                 if (vcpu->arch.halt_request) {
6338                         vcpu->arch.halt_request = 0;
6339                         ret = kvm_vcpu_halt(vcpu);
6340                         goto out;
6341                 }
6342
6343                 if (signal_pending(current))
6344                         goto out;
6345                 if (need_resched())
6346                         schedule();
6347         }
6348
6349 out:
6350         return ret;
6351 }
6352
6353 static int __grow_ple_window(int val)
6354 {
6355         if (ple_window_grow < 1)
6356                 return ple_window;
6357
6358         val = min(val, ple_window_actual_max);
6359
6360         if (ple_window_grow < ple_window)
6361                 val *= ple_window_grow;
6362         else
6363                 val += ple_window_grow;
6364
6365         return val;
6366 }
6367
6368 static int __shrink_ple_window(int val, int modifier, int minimum)
6369 {
6370         if (modifier < 1)
6371                 return ple_window;
6372
6373         if (modifier < ple_window)
6374                 val /= modifier;
6375         else
6376                 val -= modifier;
6377
6378         return max(val, minimum);
6379 }
6380
6381 static void grow_ple_window(struct kvm_vcpu *vcpu)
6382 {
6383         struct vcpu_vmx *vmx = to_vmx(vcpu);
6384         int old = vmx->ple_window;
6385
6386         vmx->ple_window = __grow_ple_window(old);
6387
6388         if (vmx->ple_window != old)
6389                 vmx->ple_window_dirty = true;
6390
6391         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6392 }
6393
6394 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6395 {
6396         struct vcpu_vmx *vmx = to_vmx(vcpu);
6397         int old = vmx->ple_window;
6398
6399         vmx->ple_window = __shrink_ple_window(old,
6400                                               ple_window_shrink, ple_window);
6401
6402         if (vmx->ple_window != old)
6403                 vmx->ple_window_dirty = true;
6404
6405         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6406 }
6407
6408 /*
6409  * ple_window_actual_max is computed to be one grow_ple_window() below
6410  * ple_window_max. (See __grow_ple_window for the reason.)
6411  * This prevents overflows, because ple_window_max is int.
6412  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6413  * this process.
6414  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6415  */
6416 static void update_ple_window_actual_max(void)
6417 {
6418         ple_window_actual_max =
6419                         __shrink_ple_window(max(ple_window_max, ple_window),
6420                                             ple_window_grow, INT_MIN);
6421 }
6422
6423 /*
6424  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6425  */
6426 static void wakeup_handler(void)
6427 {
6428         struct kvm_vcpu *vcpu;
6429         int cpu = smp_processor_id();
6430
6431         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6432         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6433                         blocked_vcpu_list) {
6434                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6435
6436                 if (pi_test_on(pi_desc) == 1)
6437                         kvm_vcpu_kick(vcpu);
6438         }
6439         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6440 }
6441
6442 void vmx_enable_tdp(void)
6443 {
6444         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6445                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6446                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6447                 0ull, VMX_EPT_EXECUTABLE_MASK,
6448                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6449                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6450
6451         ept_set_mmio_spte_mask();
6452         kvm_enable_tdp();
6453 }
6454
6455 static __init int hardware_setup(void)
6456 {
6457         int r = -ENOMEM, i, msr;
6458
6459         rdmsrl_safe(MSR_EFER, &host_efer);
6460
6461         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6462                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6463
6464         for (i = 0; i < VMX_BITMAP_NR; i++) {
6465                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6466                 if (!vmx_bitmap[i])
6467                         goto out;
6468         }
6469
6470         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6471         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6472         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6473
6474         /*
6475          * Allow direct access to the PC debug port (it is often used for I/O
6476          * delays, but the vmexits simply slow things down).
6477          */
6478         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6479         clear_bit(0x80, vmx_io_bitmap_a);
6480
6481         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6482
6483         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6484         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6485
6486         if (setup_vmcs_config(&vmcs_config) < 0) {
6487                 r = -EIO;
6488                 goto out;
6489         }
6490
6491         if (boot_cpu_has(X86_FEATURE_NX))
6492                 kvm_enable_efer_bits(EFER_NX);
6493
6494         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6495                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6496                 enable_vpid = 0;
6497
6498         if (!cpu_has_vmx_shadow_vmcs())
6499                 enable_shadow_vmcs = 0;
6500         if (enable_shadow_vmcs)
6501                 init_vmcs_shadow_fields();
6502
6503         if (!cpu_has_vmx_ept() ||
6504             !cpu_has_vmx_ept_4levels()) {
6505                 enable_ept = 0;
6506                 enable_unrestricted_guest = 0;
6507                 enable_ept_ad_bits = 0;
6508         }
6509
6510         if (!cpu_has_vmx_ept_ad_bits())
6511                 enable_ept_ad_bits = 0;
6512
6513         if (!cpu_has_vmx_unrestricted_guest())
6514                 enable_unrestricted_guest = 0;
6515
6516         if (!cpu_has_vmx_flexpriority())
6517                 flexpriority_enabled = 0;
6518
6519         /*
6520          * set_apic_access_page_addr() is used to reload apic access
6521          * page upon invalidation.  No need to do anything if not
6522          * using the APIC_ACCESS_ADDR VMCS field.
6523          */
6524         if (!flexpriority_enabled)
6525                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6526
6527         if (!cpu_has_vmx_tpr_shadow())
6528                 kvm_x86_ops->update_cr8_intercept = NULL;
6529
6530         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6531                 kvm_disable_largepages();
6532
6533         if (!cpu_has_vmx_ple())
6534                 ple_gap = 0;
6535
6536         if (!cpu_has_vmx_apicv()) {
6537                 enable_apicv = 0;
6538                 kvm_x86_ops->sync_pir_to_irr = NULL;
6539         }
6540
6541         if (cpu_has_vmx_tsc_scaling()) {
6542                 kvm_has_tsc_control = true;
6543                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6544                 kvm_tsc_scaling_ratio_frac_bits = 48;
6545         }
6546
6547         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6548         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6549         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6550         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6551         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6552         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6553         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6554
6555         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6556                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6557         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6558                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6559         memcpy(vmx_msr_bitmap_legacy_x2apic,
6560                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6561         memcpy(vmx_msr_bitmap_longmode_x2apic,
6562                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6563
6564         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6565
6566         for (msr = 0x800; msr <= 0x8ff; msr++) {
6567                 if (msr == 0x839 /* TMCCT */)
6568                         continue;
6569                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6570         }
6571
6572         /*
6573          * TPR reads and writes can be virtualized even if virtual interrupt
6574          * delivery is not in use.
6575          */
6576         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6577         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6578
6579         /* EOI */
6580         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6581         /* SELF-IPI */
6582         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6583
6584         if (enable_ept)
6585                 vmx_enable_tdp();
6586         else
6587                 kvm_disable_tdp();
6588
6589         update_ple_window_actual_max();
6590
6591         /*
6592          * Only enable PML when hardware supports PML feature, and both EPT
6593          * and EPT A/D bit features are enabled -- PML depends on them to work.
6594          */
6595         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6596                 enable_pml = 0;
6597
6598         if (!enable_pml) {
6599                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6600                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6601                 kvm_x86_ops->flush_log_dirty = NULL;
6602                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6603         }
6604
6605         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6606                 u64 vmx_msr;
6607
6608                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6609                 cpu_preemption_timer_multi =
6610                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6611         } else {
6612                 kvm_x86_ops->set_hv_timer = NULL;
6613                 kvm_x86_ops->cancel_hv_timer = NULL;
6614         }
6615
6616         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6617
6618         kvm_mce_cap_supported |= MCG_LMCE_P;
6619
6620         return alloc_kvm_area();
6621
6622 out:
6623         for (i = 0; i < VMX_BITMAP_NR; i++)
6624                 free_page((unsigned long)vmx_bitmap[i]);
6625
6626     return r;
6627 }
6628
6629 static __exit void hardware_unsetup(void)
6630 {
6631         int i;
6632
6633         for (i = 0; i < VMX_BITMAP_NR; i++)
6634                 free_page((unsigned long)vmx_bitmap[i]);
6635
6636         free_kvm_area();
6637 }
6638
6639 /*
6640  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6641  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6642  */
6643 static int handle_pause(struct kvm_vcpu *vcpu)
6644 {
6645         if (ple_gap)
6646                 grow_ple_window(vcpu);
6647
6648         kvm_vcpu_on_spin(vcpu);
6649         return kvm_skip_emulated_instruction(vcpu);
6650 }
6651
6652 static int handle_nop(struct kvm_vcpu *vcpu)
6653 {
6654         return kvm_skip_emulated_instruction(vcpu);
6655 }
6656
6657 static int handle_mwait(struct kvm_vcpu *vcpu)
6658 {
6659         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6660         return handle_nop(vcpu);
6661 }
6662
6663 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6664 {
6665         return 1;
6666 }
6667
6668 static int handle_monitor(struct kvm_vcpu *vcpu)
6669 {
6670         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6671         return handle_nop(vcpu);
6672 }
6673
6674 /*
6675  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6676  * We could reuse a single VMCS for all the L2 guests, but we also want the
6677  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6678  * allows keeping them loaded on the processor, and in the future will allow
6679  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6680  * every entry if they never change.
6681  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6682  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6683  *
6684  * The following functions allocate and free a vmcs02 in this pool.
6685  */
6686
6687 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6688 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6689 {
6690         struct vmcs02_list *item;
6691         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6692                 if (item->vmptr == vmx->nested.current_vmptr) {
6693                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6694                         return &item->vmcs02;
6695                 }
6696
6697         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6698                 /* Recycle the least recently used VMCS. */
6699                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6700                                        struct vmcs02_list, list);
6701                 item->vmptr = vmx->nested.current_vmptr;
6702                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6703                 return &item->vmcs02;
6704         }
6705
6706         /* Create a new VMCS */
6707         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6708         if (!item)
6709                 return NULL;
6710         item->vmcs02.vmcs = alloc_vmcs();
6711         item->vmcs02.shadow_vmcs = NULL;
6712         if (!item->vmcs02.vmcs) {
6713                 kfree(item);
6714                 return NULL;
6715         }
6716         loaded_vmcs_init(&item->vmcs02);
6717         item->vmptr = vmx->nested.current_vmptr;
6718         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6719         vmx->nested.vmcs02_num++;
6720         return &item->vmcs02;
6721 }
6722
6723 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6724 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6725 {
6726         struct vmcs02_list *item;
6727         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6728                 if (item->vmptr == vmptr) {
6729                         free_loaded_vmcs(&item->vmcs02);
6730                         list_del(&item->list);
6731                         kfree(item);
6732                         vmx->nested.vmcs02_num--;
6733                         return;
6734                 }
6735 }
6736
6737 /*
6738  * Free all VMCSs saved for this vcpu, except the one pointed by
6739  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6740  * must be &vmx->vmcs01.
6741  */
6742 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6743 {
6744         struct vmcs02_list *item, *n;
6745
6746         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6747         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6748                 /*
6749                  * Something will leak if the above WARN triggers.  Better than
6750                  * a use-after-free.
6751                  */
6752                 if (vmx->loaded_vmcs == &item->vmcs02)
6753                         continue;
6754
6755                 free_loaded_vmcs(&item->vmcs02);
6756                 list_del(&item->list);
6757                 kfree(item);
6758                 vmx->nested.vmcs02_num--;
6759         }
6760 }
6761
6762 /*
6763  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6764  * set the success or error code of an emulated VMX instruction, as specified
6765  * by Vol 2B, VMX Instruction Reference, "Conventions".
6766  */
6767 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6768 {
6769         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6770                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6771                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6772 }
6773
6774 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6775 {
6776         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6777                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6778                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6779                         | X86_EFLAGS_CF);
6780 }
6781
6782 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6783                                         u32 vm_instruction_error)
6784 {
6785         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6786                 /*
6787                  * failValid writes the error number to the current VMCS, which
6788                  * can't be done there isn't a current VMCS.
6789                  */
6790                 nested_vmx_failInvalid(vcpu);
6791                 return;
6792         }
6793         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6794                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6795                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6796                         | X86_EFLAGS_ZF);
6797         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6798         /*
6799          * We don't need to force a shadow sync because
6800          * VM_INSTRUCTION_ERROR is not shadowed
6801          */
6802 }
6803
6804 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6805 {
6806         /* TODO: not to reset guest simply here. */
6807         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6808         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6809 }
6810
6811 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6812 {
6813         struct vcpu_vmx *vmx =
6814                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6815
6816         vmx->nested.preemption_timer_expired = true;
6817         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6818         kvm_vcpu_kick(&vmx->vcpu);
6819
6820         return HRTIMER_NORESTART;
6821 }
6822
6823 /*
6824  * Decode the memory-address operand of a vmx instruction, as recorded on an
6825  * exit caused by such an instruction (run by a guest hypervisor).
6826  * On success, returns 0. When the operand is invalid, returns 1 and throws
6827  * #UD or #GP.
6828  */
6829 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6830                                  unsigned long exit_qualification,
6831                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6832 {
6833         gva_t off;
6834         bool exn;
6835         struct kvm_segment s;
6836
6837         /*
6838          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6839          * Execution", on an exit, vmx_instruction_info holds most of the
6840          * addressing components of the operand. Only the displacement part
6841          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6842          * For how an actual address is calculated from all these components,
6843          * refer to Vol. 1, "Operand Addressing".
6844          */
6845         int  scaling = vmx_instruction_info & 3;
6846         int  addr_size = (vmx_instruction_info >> 7) & 7;
6847         bool is_reg = vmx_instruction_info & (1u << 10);
6848         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6849         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6850         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6851         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6852         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6853
6854         if (is_reg) {
6855                 kvm_queue_exception(vcpu, UD_VECTOR);
6856                 return 1;
6857         }
6858
6859         /* Addr = segment_base + offset */
6860         /* offset = base + [index * scale] + displacement */
6861         off = exit_qualification; /* holds the displacement */
6862         if (base_is_valid)
6863                 off += kvm_register_read(vcpu, base_reg);
6864         if (index_is_valid)
6865                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6866         vmx_get_segment(vcpu, &s, seg_reg);
6867         *ret = s.base + off;
6868
6869         if (addr_size == 1) /* 32 bit */
6870                 *ret &= 0xffffffff;
6871
6872         /* Checks for #GP/#SS exceptions. */
6873         exn = false;
6874         if (is_long_mode(vcpu)) {
6875                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6876                  * non-canonical form. This is the only check on the memory
6877                  * destination for long mode!
6878                  */
6879                 exn = is_noncanonical_address(*ret);
6880         } else if (is_protmode(vcpu)) {
6881                 /* Protected mode: apply checks for segment validity in the
6882                  * following order:
6883                  * - segment type check (#GP(0) may be thrown)
6884                  * - usability check (#GP(0)/#SS(0))
6885                  * - limit check (#GP(0)/#SS(0))
6886                  */
6887                 if (wr)
6888                         /* #GP(0) if the destination operand is located in a
6889                          * read-only data segment or any code segment.
6890                          */
6891                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6892                 else
6893                         /* #GP(0) if the source operand is located in an
6894                          * execute-only code segment
6895                          */
6896                         exn = ((s.type & 0xa) == 8);
6897                 if (exn) {
6898                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6899                         return 1;
6900                 }
6901                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6902                  */
6903                 exn = (s.unusable != 0);
6904                 /* Protected mode: #GP(0)/#SS(0) if the memory
6905                  * operand is outside the segment limit.
6906                  */
6907                 exn = exn || (off + sizeof(u64) > s.limit);
6908         }
6909         if (exn) {
6910                 kvm_queue_exception_e(vcpu,
6911                                       seg_reg == VCPU_SREG_SS ?
6912                                                 SS_VECTOR : GP_VECTOR,
6913                                       0);
6914                 return 1;
6915         }
6916
6917         return 0;
6918 }
6919
6920 /*
6921  * This function performs the various checks including
6922  * - if it's 4KB aligned
6923  * - No bits beyond the physical address width are set
6924  * - Returns 0 on success or else 1
6925  * (Intel SDM Section 30.3)
6926  */
6927 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6928                                   gpa_t *vmpointer)
6929 {
6930         gva_t gva;
6931         gpa_t vmptr;
6932         struct x86_exception e;
6933         struct page *page;
6934         struct vcpu_vmx *vmx = to_vmx(vcpu);
6935         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6936
6937         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6938                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6939                 return 1;
6940
6941         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6942                                 sizeof(vmptr), &e)) {
6943                 kvm_inject_page_fault(vcpu, &e);
6944                 return 1;
6945         }
6946
6947         switch (exit_reason) {
6948         case EXIT_REASON_VMON:
6949                 /*
6950                  * SDM 3: 24.11.5
6951                  * The first 4 bytes of VMXON region contain the supported
6952                  * VMCS revision identifier
6953                  *
6954                  * Note - IA32_VMX_BASIC[48] will never be 1
6955                  * for the nested case;
6956                  * which replaces physical address width with 32
6957                  *
6958                  */
6959                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6960                         nested_vmx_failInvalid(vcpu);
6961                         return kvm_skip_emulated_instruction(vcpu);
6962                 }
6963
6964                 page = nested_get_page(vcpu, vmptr);
6965                 if (page == NULL) {
6966                         nested_vmx_failInvalid(vcpu);
6967                         return kvm_skip_emulated_instruction(vcpu);
6968                 }
6969                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6970                         kunmap(page);
6971                         nested_release_page_clean(page);
6972                         nested_vmx_failInvalid(vcpu);
6973                         return kvm_skip_emulated_instruction(vcpu);
6974                 }
6975                 kunmap(page);
6976                 nested_release_page_clean(page);
6977                 vmx->nested.vmxon_ptr = vmptr;
6978                 break;
6979         case EXIT_REASON_VMCLEAR:
6980                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6981                         nested_vmx_failValid(vcpu,
6982                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6983                         return kvm_skip_emulated_instruction(vcpu);
6984                 }
6985
6986                 if (vmptr == vmx->nested.vmxon_ptr) {
6987                         nested_vmx_failValid(vcpu,
6988                                              VMXERR_VMCLEAR_VMXON_POINTER);
6989                         return kvm_skip_emulated_instruction(vcpu);
6990                 }
6991                 break;
6992         case EXIT_REASON_VMPTRLD:
6993                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6994                         nested_vmx_failValid(vcpu,
6995                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6996                         return kvm_skip_emulated_instruction(vcpu);
6997                 }
6998
6999                 if (vmptr == vmx->nested.vmxon_ptr) {
7000                         nested_vmx_failValid(vcpu,
7001                                              VMXERR_VMPTRLD_VMXON_POINTER);
7002                         return kvm_skip_emulated_instruction(vcpu);
7003                 }
7004                 break;
7005         default:
7006                 return 1; /* shouldn't happen */
7007         }
7008
7009         if (vmpointer)
7010                 *vmpointer = vmptr;
7011         return 0;
7012 }
7013
7014 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7015 {
7016         struct vcpu_vmx *vmx = to_vmx(vcpu);
7017         struct vmcs *shadow_vmcs;
7018
7019         if (cpu_has_vmx_msr_bitmap()) {
7020                 vmx->nested.msr_bitmap =
7021                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7022                 if (!vmx->nested.msr_bitmap)
7023                         goto out_msr_bitmap;
7024         }
7025
7026         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7027         if (!vmx->nested.cached_vmcs12)
7028                 goto out_cached_vmcs12;
7029
7030         if (enable_shadow_vmcs) {
7031                 shadow_vmcs = alloc_vmcs();
7032                 if (!shadow_vmcs)
7033                         goto out_shadow_vmcs;
7034                 /* mark vmcs as shadow */
7035                 shadow_vmcs->revision_id |= (1u << 31);
7036                 /* init shadow vmcs */
7037                 vmcs_clear(shadow_vmcs);
7038                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7039         }
7040
7041         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7042         vmx->nested.vmcs02_num = 0;
7043
7044         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7045                      HRTIMER_MODE_REL_PINNED);
7046         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7047
7048         vmx->nested.vmxon = true;
7049         return 0;
7050
7051 out_shadow_vmcs:
7052         kfree(vmx->nested.cached_vmcs12);
7053
7054 out_cached_vmcs12:
7055         free_page((unsigned long)vmx->nested.msr_bitmap);
7056
7057 out_msr_bitmap:
7058         return -ENOMEM;
7059 }
7060
7061 /*
7062  * Emulate the VMXON instruction.
7063  * Currently, we just remember that VMX is active, and do not save or even
7064  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7065  * do not currently need to store anything in that guest-allocated memory
7066  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7067  * argument is different from the VMXON pointer (which the spec says they do).
7068  */
7069 static int handle_vmon(struct kvm_vcpu *vcpu)
7070 {
7071         int ret;
7072         struct kvm_segment cs;
7073         struct vcpu_vmx *vmx = to_vmx(vcpu);
7074         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7075                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7076
7077         /* The Intel VMX Instruction Reference lists a bunch of bits that
7078          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7079          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7080          * Otherwise, we should fail with #UD. We test these now:
7081          */
7082         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7083             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7084             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7085                 kvm_queue_exception(vcpu, UD_VECTOR);
7086                 return 1;
7087         }
7088
7089         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7090         if (is_long_mode(vcpu) && !cs.l) {
7091                 kvm_queue_exception(vcpu, UD_VECTOR);
7092                 return 1;
7093         }
7094
7095         if (vmx_get_cpl(vcpu)) {
7096                 kvm_inject_gp(vcpu, 0);
7097                 return 1;
7098         }
7099
7100         if (vmx->nested.vmxon) {
7101                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7102                 return kvm_skip_emulated_instruction(vcpu);
7103         }
7104
7105         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7106                         != VMXON_NEEDED_FEATURES) {
7107                 kvm_inject_gp(vcpu, 0);
7108                 return 1;
7109         }
7110
7111         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7112                 return 1;
7113
7114         ret = enter_vmx_operation(vcpu);
7115         if (ret)
7116                 return ret;
7117
7118         nested_vmx_succeed(vcpu);
7119         return kvm_skip_emulated_instruction(vcpu);
7120 }
7121
7122 /*
7123  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7124  * for running VMX instructions (except VMXON, whose prerequisites are
7125  * slightly different). It also specifies what exception to inject otherwise.
7126  */
7127 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7128 {
7129         struct kvm_segment cs;
7130         struct vcpu_vmx *vmx = to_vmx(vcpu);
7131
7132         if (!vmx->nested.vmxon) {
7133                 kvm_queue_exception(vcpu, UD_VECTOR);
7134                 return 0;
7135         }
7136
7137         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7138         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7139             (is_long_mode(vcpu) && !cs.l)) {
7140                 kvm_queue_exception(vcpu, UD_VECTOR);
7141                 return 0;
7142         }
7143
7144         if (vmx_get_cpl(vcpu)) {
7145                 kvm_inject_gp(vcpu, 0);
7146                 return 0;
7147         }
7148
7149         return 1;
7150 }
7151
7152 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7153 {
7154         if (vmx->nested.current_vmptr == -1ull)
7155                 return;
7156
7157         /* current_vmptr and current_vmcs12 are always set/reset together */
7158         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7159                 return;
7160
7161         if (enable_shadow_vmcs) {
7162                 /* copy to memory all shadowed fields in case
7163                    they were modified */
7164                 copy_shadow_to_vmcs12(vmx);
7165                 vmx->nested.sync_shadow_vmcs = false;
7166                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7167                                 SECONDARY_EXEC_SHADOW_VMCS);
7168                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7169         }
7170         vmx->nested.posted_intr_nv = -1;
7171
7172         /* Flush VMCS12 to guest memory */
7173         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7174                VMCS12_SIZE);
7175
7176         kunmap(vmx->nested.current_vmcs12_page);
7177         nested_release_page(vmx->nested.current_vmcs12_page);
7178         vmx->nested.current_vmptr = -1ull;
7179         vmx->nested.current_vmcs12 = NULL;
7180 }
7181
7182 /*
7183  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7184  * just stops using VMX.
7185  */
7186 static void free_nested(struct vcpu_vmx *vmx)
7187 {
7188         if (!vmx->nested.vmxon)
7189                 return;
7190
7191         vmx->nested.vmxon = false;
7192         free_vpid(vmx->nested.vpid02);
7193         nested_release_vmcs12(vmx);
7194         if (vmx->nested.msr_bitmap) {
7195                 free_page((unsigned long)vmx->nested.msr_bitmap);
7196                 vmx->nested.msr_bitmap = NULL;
7197         }
7198         if (enable_shadow_vmcs) {
7199                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7200                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7201                 vmx->vmcs01.shadow_vmcs = NULL;
7202         }
7203         kfree(vmx->nested.cached_vmcs12);
7204         /* Unpin physical memory we referred to in current vmcs02 */
7205         if (vmx->nested.apic_access_page) {
7206                 nested_release_page(vmx->nested.apic_access_page);
7207                 vmx->nested.apic_access_page = NULL;
7208         }
7209         if (vmx->nested.virtual_apic_page) {
7210                 nested_release_page(vmx->nested.virtual_apic_page);
7211                 vmx->nested.virtual_apic_page = NULL;
7212         }
7213         if (vmx->nested.pi_desc_page) {
7214                 kunmap(vmx->nested.pi_desc_page);
7215                 nested_release_page(vmx->nested.pi_desc_page);
7216                 vmx->nested.pi_desc_page = NULL;
7217                 vmx->nested.pi_desc = NULL;
7218         }
7219
7220         nested_free_all_saved_vmcss(vmx);
7221 }
7222
7223 /* Emulate the VMXOFF instruction */
7224 static int handle_vmoff(struct kvm_vcpu *vcpu)
7225 {
7226         if (!nested_vmx_check_permission(vcpu))
7227                 return 1;
7228         free_nested(to_vmx(vcpu));
7229         nested_vmx_succeed(vcpu);
7230         return kvm_skip_emulated_instruction(vcpu);
7231 }
7232
7233 /* Emulate the VMCLEAR instruction */
7234 static int handle_vmclear(struct kvm_vcpu *vcpu)
7235 {
7236         struct vcpu_vmx *vmx = to_vmx(vcpu);
7237         u32 zero = 0;
7238         gpa_t vmptr;
7239
7240         if (!nested_vmx_check_permission(vcpu))
7241                 return 1;
7242
7243         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7244                 return 1;
7245
7246         if (vmptr == vmx->nested.current_vmptr)
7247                 nested_release_vmcs12(vmx);
7248
7249         kvm_vcpu_write_guest(vcpu,
7250                         vmptr + offsetof(struct vmcs12, launch_state),
7251                         &zero, sizeof(zero));
7252
7253         nested_free_vmcs02(vmx, vmptr);
7254
7255         nested_vmx_succeed(vcpu);
7256         return kvm_skip_emulated_instruction(vcpu);
7257 }
7258
7259 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7260
7261 /* Emulate the VMLAUNCH instruction */
7262 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7263 {
7264         return nested_vmx_run(vcpu, true);
7265 }
7266
7267 /* Emulate the VMRESUME instruction */
7268 static int handle_vmresume(struct kvm_vcpu *vcpu)
7269 {
7270
7271         return nested_vmx_run(vcpu, false);
7272 }
7273
7274 enum vmcs_field_type {
7275         VMCS_FIELD_TYPE_U16 = 0,
7276         VMCS_FIELD_TYPE_U64 = 1,
7277         VMCS_FIELD_TYPE_U32 = 2,
7278         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7279 };
7280
7281 static inline int vmcs_field_type(unsigned long field)
7282 {
7283         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7284                 return VMCS_FIELD_TYPE_U32;
7285         return (field >> 13) & 0x3 ;
7286 }
7287
7288 static inline int vmcs_field_readonly(unsigned long field)
7289 {
7290         return (((field >> 10) & 0x3) == 1);
7291 }
7292
7293 /*
7294  * Read a vmcs12 field. Since these can have varying lengths and we return
7295  * one type, we chose the biggest type (u64) and zero-extend the return value
7296  * to that size. Note that the caller, handle_vmread, might need to use only
7297  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7298  * 64-bit fields are to be returned).
7299  */
7300 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7301                                   unsigned long field, u64 *ret)
7302 {
7303         short offset = vmcs_field_to_offset(field);
7304         char *p;
7305
7306         if (offset < 0)
7307                 return offset;
7308
7309         p = ((char *)(get_vmcs12(vcpu))) + offset;
7310
7311         switch (vmcs_field_type(field)) {
7312         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7313                 *ret = *((natural_width *)p);
7314                 return 0;
7315         case VMCS_FIELD_TYPE_U16:
7316                 *ret = *((u16 *)p);
7317                 return 0;
7318         case VMCS_FIELD_TYPE_U32:
7319                 *ret = *((u32 *)p);
7320                 return 0;
7321         case VMCS_FIELD_TYPE_U64:
7322                 *ret = *((u64 *)p);
7323                 return 0;
7324         default:
7325                 WARN_ON(1);
7326                 return -ENOENT;
7327         }
7328 }
7329
7330
7331 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7332                                    unsigned long field, u64 field_value){
7333         short offset = vmcs_field_to_offset(field);
7334         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7335         if (offset < 0)
7336                 return offset;
7337
7338         switch (vmcs_field_type(field)) {
7339         case VMCS_FIELD_TYPE_U16:
7340                 *(u16 *)p = field_value;
7341                 return 0;
7342         case VMCS_FIELD_TYPE_U32:
7343                 *(u32 *)p = field_value;
7344                 return 0;
7345         case VMCS_FIELD_TYPE_U64:
7346                 *(u64 *)p = field_value;
7347                 return 0;
7348         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7349                 *(natural_width *)p = field_value;
7350                 return 0;
7351         default:
7352                 WARN_ON(1);
7353                 return -ENOENT;
7354         }
7355
7356 }
7357
7358 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7359 {
7360         int i;
7361         unsigned long field;
7362         u64 field_value;
7363         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7364         const unsigned long *fields = shadow_read_write_fields;
7365         const int num_fields = max_shadow_read_write_fields;
7366
7367         preempt_disable();
7368
7369         vmcs_load(shadow_vmcs);
7370
7371         for (i = 0; i < num_fields; i++) {
7372                 field = fields[i];
7373                 switch (vmcs_field_type(field)) {
7374                 case VMCS_FIELD_TYPE_U16:
7375                         field_value = vmcs_read16(field);
7376                         break;
7377                 case VMCS_FIELD_TYPE_U32:
7378                         field_value = vmcs_read32(field);
7379                         break;
7380                 case VMCS_FIELD_TYPE_U64:
7381                         field_value = vmcs_read64(field);
7382                         break;
7383                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7384                         field_value = vmcs_readl(field);
7385                         break;
7386                 default:
7387                         WARN_ON(1);
7388                         continue;
7389                 }
7390                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7391         }
7392
7393         vmcs_clear(shadow_vmcs);
7394         vmcs_load(vmx->loaded_vmcs->vmcs);
7395
7396         preempt_enable();
7397 }
7398
7399 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7400 {
7401         const unsigned long *fields[] = {
7402                 shadow_read_write_fields,
7403                 shadow_read_only_fields
7404         };
7405         const int max_fields[] = {
7406                 max_shadow_read_write_fields,
7407                 max_shadow_read_only_fields
7408         };
7409         int i, q;
7410         unsigned long field;
7411         u64 field_value = 0;
7412         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7413
7414         vmcs_load(shadow_vmcs);
7415
7416         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7417                 for (i = 0; i < max_fields[q]; i++) {
7418                         field = fields[q][i];
7419                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7420
7421                         switch (vmcs_field_type(field)) {
7422                         case VMCS_FIELD_TYPE_U16:
7423                                 vmcs_write16(field, (u16)field_value);
7424                                 break;
7425                         case VMCS_FIELD_TYPE_U32:
7426                                 vmcs_write32(field, (u32)field_value);
7427                                 break;
7428                         case VMCS_FIELD_TYPE_U64:
7429                                 vmcs_write64(field, (u64)field_value);
7430                                 break;
7431                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7432                                 vmcs_writel(field, (long)field_value);
7433                                 break;
7434                         default:
7435                                 WARN_ON(1);
7436                                 break;
7437                         }
7438                 }
7439         }
7440
7441         vmcs_clear(shadow_vmcs);
7442         vmcs_load(vmx->loaded_vmcs->vmcs);
7443 }
7444
7445 /*
7446  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7447  * used before) all generate the same failure when it is missing.
7448  */
7449 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7450 {
7451         struct vcpu_vmx *vmx = to_vmx(vcpu);
7452         if (vmx->nested.current_vmptr == -1ull) {
7453                 nested_vmx_failInvalid(vcpu);
7454                 return 0;
7455         }
7456         return 1;
7457 }
7458
7459 static int handle_vmread(struct kvm_vcpu *vcpu)
7460 {
7461         unsigned long field;
7462         u64 field_value;
7463         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7464         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7465         gva_t gva = 0;
7466
7467         if (!nested_vmx_check_permission(vcpu))
7468                 return 1;
7469
7470         if (!nested_vmx_check_vmcs12(vcpu))
7471                 return kvm_skip_emulated_instruction(vcpu);
7472
7473         /* Decode instruction info and find the field to read */
7474         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7475         /* Read the field, zero-extended to a u64 field_value */
7476         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7477                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7478                 return kvm_skip_emulated_instruction(vcpu);
7479         }
7480         /*
7481          * Now copy part of this value to register or memory, as requested.
7482          * Note that the number of bits actually copied is 32 or 64 depending
7483          * on the guest's mode (32 or 64 bit), not on the given field's length.
7484          */
7485         if (vmx_instruction_info & (1u << 10)) {
7486                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7487                         field_value);
7488         } else {
7489                 if (get_vmx_mem_address(vcpu, exit_qualification,
7490                                 vmx_instruction_info, true, &gva))
7491                         return 1;
7492                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7493                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7494                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7495         }
7496
7497         nested_vmx_succeed(vcpu);
7498         return kvm_skip_emulated_instruction(vcpu);
7499 }
7500
7501
7502 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7503 {
7504         unsigned long field;
7505         gva_t gva;
7506         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7507         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7508         /* The value to write might be 32 or 64 bits, depending on L1's long
7509          * mode, and eventually we need to write that into a field of several
7510          * possible lengths. The code below first zero-extends the value to 64
7511          * bit (field_value), and then copies only the appropriate number of
7512          * bits into the vmcs12 field.
7513          */
7514         u64 field_value = 0;
7515         struct x86_exception e;
7516
7517         if (!nested_vmx_check_permission(vcpu))
7518                 return 1;
7519
7520         if (!nested_vmx_check_vmcs12(vcpu))
7521                 return kvm_skip_emulated_instruction(vcpu);
7522
7523         if (vmx_instruction_info & (1u << 10))
7524                 field_value = kvm_register_readl(vcpu,
7525                         (((vmx_instruction_info) >> 3) & 0xf));
7526         else {
7527                 if (get_vmx_mem_address(vcpu, exit_qualification,
7528                                 vmx_instruction_info, false, &gva))
7529                         return 1;
7530                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7531                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7532                         kvm_inject_page_fault(vcpu, &e);
7533                         return 1;
7534                 }
7535         }
7536
7537
7538         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7539         if (vmcs_field_readonly(field)) {
7540                 nested_vmx_failValid(vcpu,
7541                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7542                 return kvm_skip_emulated_instruction(vcpu);
7543         }
7544
7545         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7546                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7547                 return kvm_skip_emulated_instruction(vcpu);
7548         }
7549
7550         nested_vmx_succeed(vcpu);
7551         return kvm_skip_emulated_instruction(vcpu);
7552 }
7553
7554 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7555 {
7556         vmx->nested.current_vmptr = vmptr;
7557         if (enable_shadow_vmcs) {
7558                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7559                               SECONDARY_EXEC_SHADOW_VMCS);
7560                 vmcs_write64(VMCS_LINK_POINTER,
7561                              __pa(vmx->vmcs01.shadow_vmcs));
7562                 vmx->nested.sync_shadow_vmcs = true;
7563         }
7564 }
7565
7566 /* Emulate the VMPTRLD instruction */
7567 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7568 {
7569         struct vcpu_vmx *vmx = to_vmx(vcpu);
7570         gpa_t vmptr;
7571
7572         if (!nested_vmx_check_permission(vcpu))
7573                 return 1;
7574
7575         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7576                 return 1;
7577
7578         if (vmx->nested.current_vmptr != vmptr) {
7579                 struct vmcs12 *new_vmcs12;
7580                 struct page *page;
7581                 page = nested_get_page(vcpu, vmptr);
7582                 if (page == NULL) {
7583                         nested_vmx_failInvalid(vcpu);
7584                         return kvm_skip_emulated_instruction(vcpu);
7585                 }
7586                 new_vmcs12 = kmap(page);
7587                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7588                         kunmap(page);
7589                         nested_release_page_clean(page);
7590                         nested_vmx_failValid(vcpu,
7591                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7592                         return kvm_skip_emulated_instruction(vcpu);
7593                 }
7594
7595                 nested_release_vmcs12(vmx);
7596                 vmx->nested.current_vmcs12 = new_vmcs12;
7597                 vmx->nested.current_vmcs12_page = page;
7598                 /*
7599                  * Load VMCS12 from guest memory since it is not already
7600                  * cached.
7601                  */
7602                 memcpy(vmx->nested.cached_vmcs12,
7603                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7604                 set_current_vmptr(vmx, vmptr);
7605         }
7606
7607         nested_vmx_succeed(vcpu);
7608         return kvm_skip_emulated_instruction(vcpu);
7609 }
7610
7611 /* Emulate the VMPTRST instruction */
7612 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7613 {
7614         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7615         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7616         gva_t vmcs_gva;
7617         struct x86_exception e;
7618
7619         if (!nested_vmx_check_permission(vcpu))
7620                 return 1;
7621
7622         if (get_vmx_mem_address(vcpu, exit_qualification,
7623                         vmx_instruction_info, true, &vmcs_gva))
7624                 return 1;
7625         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7626         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7627                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7628                                  sizeof(u64), &e)) {
7629                 kvm_inject_page_fault(vcpu, &e);
7630                 return 1;
7631         }
7632         nested_vmx_succeed(vcpu);
7633         return kvm_skip_emulated_instruction(vcpu);
7634 }
7635
7636 /* Emulate the INVEPT instruction */
7637 static int handle_invept(struct kvm_vcpu *vcpu)
7638 {
7639         struct vcpu_vmx *vmx = to_vmx(vcpu);
7640         u32 vmx_instruction_info, types;
7641         unsigned long type;
7642         gva_t gva;
7643         struct x86_exception e;
7644         struct {
7645                 u64 eptp, gpa;
7646         } operand;
7647
7648         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7649               SECONDARY_EXEC_ENABLE_EPT) ||
7650             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7651                 kvm_queue_exception(vcpu, UD_VECTOR);
7652                 return 1;
7653         }
7654
7655         if (!nested_vmx_check_permission(vcpu))
7656                 return 1;
7657
7658         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7659                 kvm_queue_exception(vcpu, UD_VECTOR);
7660                 return 1;
7661         }
7662
7663         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7664         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7665
7666         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7667
7668         if (type >= 32 || !(types & (1 << type))) {
7669                 nested_vmx_failValid(vcpu,
7670                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7671                 return kvm_skip_emulated_instruction(vcpu);
7672         }
7673
7674         /* According to the Intel VMX instruction reference, the memory
7675          * operand is read even if it isn't needed (e.g., for type==global)
7676          */
7677         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7678                         vmx_instruction_info, false, &gva))
7679                 return 1;
7680         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7681                                 sizeof(operand), &e)) {
7682                 kvm_inject_page_fault(vcpu, &e);
7683                 return 1;
7684         }
7685
7686         switch (type) {
7687         case VMX_EPT_EXTENT_GLOBAL:
7688         /*
7689          * TODO: track mappings and invalidate
7690          * single context requests appropriately
7691          */
7692         case VMX_EPT_EXTENT_CONTEXT:
7693                 kvm_mmu_sync_roots(vcpu);
7694                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7695                 nested_vmx_succeed(vcpu);
7696                 break;
7697         default:
7698                 BUG_ON(1);
7699                 break;
7700         }
7701
7702         return kvm_skip_emulated_instruction(vcpu);
7703 }
7704
7705 static int handle_invvpid(struct kvm_vcpu *vcpu)
7706 {
7707         struct vcpu_vmx *vmx = to_vmx(vcpu);
7708         u32 vmx_instruction_info;
7709         unsigned long type, types;
7710         gva_t gva;
7711         struct x86_exception e;
7712         int vpid;
7713
7714         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7715               SECONDARY_EXEC_ENABLE_VPID) ||
7716                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7717                 kvm_queue_exception(vcpu, UD_VECTOR);
7718                 return 1;
7719         }
7720
7721         if (!nested_vmx_check_permission(vcpu))
7722                 return 1;
7723
7724         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7725         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7726
7727         types = (vmx->nested.nested_vmx_vpid_caps &
7728                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7729
7730         if (type >= 32 || !(types & (1 << type))) {
7731                 nested_vmx_failValid(vcpu,
7732                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7733                 return kvm_skip_emulated_instruction(vcpu);
7734         }
7735
7736         /* according to the intel vmx instruction reference, the memory
7737          * operand is read even if it isn't needed (e.g., for type==global)
7738          */
7739         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7740                         vmx_instruction_info, false, &gva))
7741                 return 1;
7742         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7743                                 sizeof(u32), &e)) {
7744                 kvm_inject_page_fault(vcpu, &e);
7745                 return 1;
7746         }
7747
7748         switch (type) {
7749         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7750         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7751         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7752                 if (!vpid) {
7753                         nested_vmx_failValid(vcpu,
7754                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7755                         return kvm_skip_emulated_instruction(vcpu);
7756                 }
7757                 break;
7758         case VMX_VPID_EXTENT_ALL_CONTEXT:
7759                 break;
7760         default:
7761                 WARN_ON_ONCE(1);
7762                 return kvm_skip_emulated_instruction(vcpu);
7763         }
7764
7765         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7766         nested_vmx_succeed(vcpu);
7767
7768         return kvm_skip_emulated_instruction(vcpu);
7769 }
7770
7771 static int handle_pml_full(struct kvm_vcpu *vcpu)
7772 {
7773         unsigned long exit_qualification;
7774
7775         trace_kvm_pml_full(vcpu->vcpu_id);
7776
7777         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7778
7779         /*
7780          * PML buffer FULL happened while executing iret from NMI,
7781          * "blocked by NMI" bit has to be set before next VM entry.
7782          */
7783         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7784                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7785                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7786                                 GUEST_INTR_STATE_NMI);
7787
7788         /*
7789          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7790          * here.., and there's no userspace involvement needed for PML.
7791          */
7792         return 1;
7793 }
7794
7795 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7796 {
7797         kvm_lapic_expired_hv_timer(vcpu);
7798         return 1;
7799 }
7800
7801 /*
7802  * The exit handlers return 1 if the exit was handled fully and guest execution
7803  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7804  * to be done to userspace and return 0.
7805  */
7806 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7807         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7808         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7809         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7810         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7811         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7812         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7813         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7814         [EXIT_REASON_CPUID]                   = handle_cpuid,
7815         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7816         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7817         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7818         [EXIT_REASON_HLT]                     = handle_halt,
7819         [EXIT_REASON_INVD]                    = handle_invd,
7820         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7821         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7822         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7823         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7824         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7825         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7826         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7827         [EXIT_REASON_VMREAD]                  = handle_vmread,
7828         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7829         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7830         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7831         [EXIT_REASON_VMON]                    = handle_vmon,
7832         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7833         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7834         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7835         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7836         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7837         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7838         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7839         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7840         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7841         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7842         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7843         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7844         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7845         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7846         [EXIT_REASON_INVEPT]                  = handle_invept,
7847         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7848         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7849         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7850         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7851         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7852 };
7853
7854 static const int kvm_vmx_max_exit_handlers =
7855         ARRAY_SIZE(kvm_vmx_exit_handlers);
7856
7857 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7858                                        struct vmcs12 *vmcs12)
7859 {
7860         unsigned long exit_qualification;
7861         gpa_t bitmap, last_bitmap;
7862         unsigned int port;
7863         int size;
7864         u8 b;
7865
7866         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7867                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7868
7869         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7870
7871         port = exit_qualification >> 16;
7872         size = (exit_qualification & 7) + 1;
7873
7874         last_bitmap = (gpa_t)-1;
7875         b = -1;
7876
7877         while (size > 0) {
7878                 if (port < 0x8000)
7879                         bitmap = vmcs12->io_bitmap_a;
7880                 else if (port < 0x10000)
7881                         bitmap = vmcs12->io_bitmap_b;
7882                 else
7883                         return true;
7884                 bitmap += (port & 0x7fff) / 8;
7885
7886                 if (last_bitmap != bitmap)
7887                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7888                                 return true;
7889                 if (b & (1 << (port & 7)))
7890                         return true;
7891
7892                 port++;
7893                 size--;
7894                 last_bitmap = bitmap;
7895         }
7896
7897         return false;
7898 }
7899
7900 /*
7901  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7902  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7903  * disinterest in the current event (read or write a specific MSR) by using an
7904  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7905  */
7906 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7907         struct vmcs12 *vmcs12, u32 exit_reason)
7908 {
7909         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7910         gpa_t bitmap;
7911
7912         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7913                 return true;
7914
7915         /*
7916          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7917          * for the four combinations of read/write and low/high MSR numbers.
7918          * First we need to figure out which of the four to use:
7919          */
7920         bitmap = vmcs12->msr_bitmap;
7921         if (exit_reason == EXIT_REASON_MSR_WRITE)
7922                 bitmap += 2048;
7923         if (msr_index >= 0xc0000000) {
7924                 msr_index -= 0xc0000000;
7925                 bitmap += 1024;
7926         }
7927
7928         /* Then read the msr_index'th bit from this bitmap: */
7929         if (msr_index < 1024*8) {
7930                 unsigned char b;
7931                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7932                         return true;
7933                 return 1 & (b >> (msr_index & 7));
7934         } else
7935                 return true; /* let L1 handle the wrong parameter */
7936 }
7937
7938 /*
7939  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7940  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7941  * intercept (via guest_host_mask etc.) the current event.
7942  */
7943 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7944         struct vmcs12 *vmcs12)
7945 {
7946         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7947         int cr = exit_qualification & 15;
7948         int reg = (exit_qualification >> 8) & 15;
7949         unsigned long val = kvm_register_readl(vcpu, reg);
7950
7951         switch ((exit_qualification >> 4) & 3) {
7952         case 0: /* mov to cr */
7953                 switch (cr) {
7954                 case 0:
7955                         if (vmcs12->cr0_guest_host_mask &
7956                             (val ^ vmcs12->cr0_read_shadow))
7957                                 return true;
7958                         break;
7959                 case 3:
7960                         if ((vmcs12->cr3_target_count >= 1 &&
7961                                         vmcs12->cr3_target_value0 == val) ||
7962                                 (vmcs12->cr3_target_count >= 2 &&
7963                                         vmcs12->cr3_target_value1 == val) ||
7964                                 (vmcs12->cr3_target_count >= 3 &&
7965                                         vmcs12->cr3_target_value2 == val) ||
7966                                 (vmcs12->cr3_target_count >= 4 &&
7967                                         vmcs12->cr3_target_value3 == val))
7968                                 return false;
7969                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7970                                 return true;
7971                         break;
7972                 case 4:
7973                         if (vmcs12->cr4_guest_host_mask &
7974                             (vmcs12->cr4_read_shadow ^ val))
7975                                 return true;
7976                         break;
7977                 case 8:
7978                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7979                                 return true;
7980                         break;
7981                 }
7982                 break;
7983         case 2: /* clts */
7984                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7985                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7986                         return true;
7987                 break;
7988         case 1: /* mov from cr */
7989                 switch (cr) {
7990                 case 3:
7991                         if (vmcs12->cpu_based_vm_exec_control &
7992                             CPU_BASED_CR3_STORE_EXITING)
7993                                 return true;
7994                         break;
7995                 case 8:
7996                         if (vmcs12->cpu_based_vm_exec_control &
7997                             CPU_BASED_CR8_STORE_EXITING)
7998                                 return true;
7999                         break;
8000                 }
8001                 break;
8002         case 3: /* lmsw */
8003                 /*
8004                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8005                  * cr0. Other attempted changes are ignored, with no exit.
8006                  */
8007                 if (vmcs12->cr0_guest_host_mask & 0xe &
8008                     (val ^ vmcs12->cr0_read_shadow))
8009                         return true;
8010                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8011                     !(vmcs12->cr0_read_shadow & 0x1) &&
8012                     (val & 0x1))
8013                         return true;
8014                 break;
8015         }
8016         return false;
8017 }
8018
8019 /*
8020  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8021  * should handle it ourselves in L0 (and then continue L2). Only call this
8022  * when in is_guest_mode (L2).
8023  */
8024 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8025 {
8026         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8027         struct vcpu_vmx *vmx = to_vmx(vcpu);
8028         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8029         u32 exit_reason = vmx->exit_reason;
8030
8031         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8032                                 vmcs_readl(EXIT_QUALIFICATION),
8033                                 vmx->idt_vectoring_info,
8034                                 intr_info,
8035                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8036                                 KVM_ISA_VMX);
8037
8038         if (vmx->nested.nested_run_pending)
8039                 return false;
8040
8041         if (unlikely(vmx->fail)) {
8042                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8043                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8044                 return true;
8045         }
8046
8047         switch (exit_reason) {
8048         case EXIT_REASON_EXCEPTION_NMI:
8049                 if (is_nmi(intr_info))
8050                         return false;
8051                 else if (is_page_fault(intr_info))
8052                         return enable_ept;
8053                 else if (is_no_device(intr_info) &&
8054                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8055                         return false;
8056                 else if (is_debug(intr_info) &&
8057                          vcpu->guest_debug &
8058                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8059                         return false;
8060                 else if (is_breakpoint(intr_info) &&
8061                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8062                         return false;
8063                 return vmcs12->exception_bitmap &
8064                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8065         case EXIT_REASON_EXTERNAL_INTERRUPT:
8066                 return false;
8067         case EXIT_REASON_TRIPLE_FAULT:
8068                 return true;
8069         case EXIT_REASON_PENDING_INTERRUPT:
8070                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8071         case EXIT_REASON_NMI_WINDOW:
8072                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8073         case EXIT_REASON_TASK_SWITCH:
8074                 return true;
8075         case EXIT_REASON_CPUID:
8076                 return true;
8077         case EXIT_REASON_HLT:
8078                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8079         case EXIT_REASON_INVD:
8080                 return true;
8081         case EXIT_REASON_INVLPG:
8082                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8083         case EXIT_REASON_RDPMC:
8084                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8085         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8086                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8087         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8088         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8089         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8090         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8091         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8092         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8093                 /*
8094                  * VMX instructions trap unconditionally. This allows L1 to
8095                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8096                  */
8097                 return true;
8098         case EXIT_REASON_CR_ACCESS:
8099                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8100         case EXIT_REASON_DR_ACCESS:
8101                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8102         case EXIT_REASON_IO_INSTRUCTION:
8103                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8104         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8105                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8106         case EXIT_REASON_MSR_READ:
8107         case EXIT_REASON_MSR_WRITE:
8108                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8109         case EXIT_REASON_INVALID_STATE:
8110                 return true;
8111         case EXIT_REASON_MWAIT_INSTRUCTION:
8112                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8113         case EXIT_REASON_MONITOR_TRAP_FLAG:
8114                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8115         case EXIT_REASON_MONITOR_INSTRUCTION:
8116                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8117         case EXIT_REASON_PAUSE_INSTRUCTION:
8118                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8119                         nested_cpu_has2(vmcs12,
8120                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8121         case EXIT_REASON_MCE_DURING_VMENTRY:
8122                 return false;
8123         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8124                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8125         case EXIT_REASON_APIC_ACCESS:
8126                 return nested_cpu_has2(vmcs12,
8127                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8128         case EXIT_REASON_APIC_WRITE:
8129         case EXIT_REASON_EOI_INDUCED:
8130                 /* apic_write and eoi_induced should exit unconditionally. */
8131                 return true;
8132         case EXIT_REASON_EPT_VIOLATION:
8133                 /*
8134                  * L0 always deals with the EPT violation. If nested EPT is
8135                  * used, and the nested mmu code discovers that the address is
8136                  * missing in the guest EPT table (EPT12), the EPT violation
8137                  * will be injected with nested_ept_inject_page_fault()
8138                  */
8139                 return false;
8140         case EXIT_REASON_EPT_MISCONFIG:
8141                 /*
8142                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8143                  * table (shadow on EPT) or a merged EPT table that L0 built
8144                  * (EPT on EPT). So any problems with the structure of the
8145                  * table is L0's fault.
8146                  */
8147                 return false;
8148         case EXIT_REASON_WBINVD:
8149                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8150         case EXIT_REASON_XSETBV:
8151                 return true;
8152         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8153                 /*
8154                  * This should never happen, since it is not possible to
8155                  * set XSS to a non-zero value---neither in L1 nor in L2.
8156                  * If if it were, XSS would have to be checked against
8157                  * the XSS exit bitmap in vmcs12.
8158                  */
8159                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8160         case EXIT_REASON_PREEMPTION_TIMER:
8161                 return false;
8162         default:
8163                 return true;
8164         }
8165 }
8166
8167 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8168 {
8169         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8170         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8171 }
8172
8173 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8174 {
8175         if (vmx->pml_pg) {
8176                 __free_page(vmx->pml_pg);
8177                 vmx->pml_pg = NULL;
8178         }
8179 }
8180
8181 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8182 {
8183         struct vcpu_vmx *vmx = to_vmx(vcpu);
8184         u64 *pml_buf;
8185         u16 pml_idx;
8186
8187         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8188
8189         /* Do nothing if PML buffer is empty */
8190         if (pml_idx == (PML_ENTITY_NUM - 1))
8191                 return;
8192
8193         /* PML index always points to next available PML buffer entity */
8194         if (pml_idx >= PML_ENTITY_NUM)
8195                 pml_idx = 0;
8196         else
8197                 pml_idx++;
8198
8199         pml_buf = page_address(vmx->pml_pg);
8200         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8201                 u64 gpa;
8202
8203                 gpa = pml_buf[pml_idx];
8204                 WARN_ON(gpa & (PAGE_SIZE - 1));
8205                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8206         }
8207
8208         /* reset PML index */
8209         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8210 }
8211
8212 /*
8213  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8214  * Called before reporting dirty_bitmap to userspace.
8215  */
8216 static void kvm_flush_pml_buffers(struct kvm *kvm)
8217 {
8218         int i;
8219         struct kvm_vcpu *vcpu;
8220         /*
8221          * We only need to kick vcpu out of guest mode here, as PML buffer
8222          * is flushed at beginning of all VMEXITs, and it's obvious that only
8223          * vcpus running in guest are possible to have unflushed GPAs in PML
8224          * buffer.
8225          */
8226         kvm_for_each_vcpu(i, vcpu, kvm)
8227                 kvm_vcpu_kick(vcpu);
8228 }
8229
8230 static void vmx_dump_sel(char *name, uint32_t sel)
8231 {
8232         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8233                name, vmcs_read16(sel),
8234                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8235                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8236                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8237 }
8238
8239 static void vmx_dump_dtsel(char *name, uint32_t limit)
8240 {
8241         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8242                name, vmcs_read32(limit),
8243                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8244 }
8245
8246 static void dump_vmcs(void)
8247 {
8248         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8249         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8250         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8251         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8252         u32 secondary_exec_control = 0;
8253         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8254         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8255         int i, n;
8256
8257         if (cpu_has_secondary_exec_ctrls())
8258                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8259
8260         pr_err("*** Guest State ***\n");
8261         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8262                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8263                vmcs_readl(CR0_GUEST_HOST_MASK));
8264         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8265                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8266         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8267         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8268             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8269         {
8270                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8271                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8272                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8273                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8274         }
8275         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8276                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8277         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8278                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8279         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8280                vmcs_readl(GUEST_SYSENTER_ESP),
8281                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8282         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8283         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8284         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8285         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8286         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8287         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8288         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8289         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8290         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8291         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8292         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8293             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8294                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8295                        efer, vmcs_read64(GUEST_IA32_PAT));
8296         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8297                vmcs_read64(GUEST_IA32_DEBUGCTL),
8298                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8299         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8300                 pr_err("PerfGlobCtl = 0x%016llx\n",
8301                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8302         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8303                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8304         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8305                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8306                vmcs_read32(GUEST_ACTIVITY_STATE));
8307         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8308                 pr_err("InterruptStatus = %04x\n",
8309                        vmcs_read16(GUEST_INTR_STATUS));
8310
8311         pr_err("*** Host State ***\n");
8312         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8313                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8314         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8315                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8316                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8317                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8318                vmcs_read16(HOST_TR_SELECTOR));
8319         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8320                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8321                vmcs_readl(HOST_TR_BASE));
8322         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8323                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8324         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8325                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8326                vmcs_readl(HOST_CR4));
8327         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8328                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8329                vmcs_read32(HOST_IA32_SYSENTER_CS),
8330                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8331         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8332                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8333                        vmcs_read64(HOST_IA32_EFER),
8334                        vmcs_read64(HOST_IA32_PAT));
8335         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8336                 pr_err("PerfGlobCtl = 0x%016llx\n",
8337                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8338
8339         pr_err("*** Control State ***\n");
8340         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8341                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8342         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8343         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8344                vmcs_read32(EXCEPTION_BITMAP),
8345                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8346                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8347         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8348                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8349                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8350                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8351         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8352                vmcs_read32(VM_EXIT_INTR_INFO),
8353                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8354                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8355         pr_err("        reason=%08x qualification=%016lx\n",
8356                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8357         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8358                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8359                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8360         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8361         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8362                 pr_err("TSC Multiplier = 0x%016llx\n",
8363                        vmcs_read64(TSC_MULTIPLIER));
8364         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8365                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8366         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8367                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8368         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8369                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8370         n = vmcs_read32(CR3_TARGET_COUNT);
8371         for (i = 0; i + 1 < n; i += 4)
8372                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8373                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8374                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8375         if (i < n)
8376                 pr_err("CR3 target%u=%016lx\n",
8377                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8378         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8379                 pr_err("PLE Gap=%08x Window=%08x\n",
8380                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8381         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8382                 pr_err("Virtual processor ID = 0x%04x\n",
8383                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8384 }
8385
8386 /*
8387  * The guest has exited.  See if we can fix it or if we need userspace
8388  * assistance.
8389  */
8390 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8391 {
8392         struct vcpu_vmx *vmx = to_vmx(vcpu);
8393         u32 exit_reason = vmx->exit_reason;
8394         u32 vectoring_info = vmx->idt_vectoring_info;
8395
8396         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8397         vcpu->arch.gpa_available = false;
8398
8399         /*
8400          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8401          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8402          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8403          * mode as if vcpus is in root mode, the PML buffer must has been
8404          * flushed already.
8405          */
8406         if (enable_pml)
8407                 vmx_flush_pml_buffer(vcpu);
8408
8409         /* If guest state is invalid, start emulating */
8410         if (vmx->emulation_required)
8411                 return handle_invalid_guest_state(vcpu);
8412
8413         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8414                 nested_vmx_vmexit(vcpu, exit_reason,
8415                                   vmcs_read32(VM_EXIT_INTR_INFO),
8416                                   vmcs_readl(EXIT_QUALIFICATION));
8417                 return 1;
8418         }
8419
8420         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8421                 dump_vmcs();
8422                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8423                 vcpu->run->fail_entry.hardware_entry_failure_reason
8424                         = exit_reason;
8425                 return 0;
8426         }
8427
8428         if (unlikely(vmx->fail)) {
8429                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8430                 vcpu->run->fail_entry.hardware_entry_failure_reason
8431                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8432                 return 0;
8433         }
8434
8435         /*
8436          * Note:
8437          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8438          * delivery event since it indicates guest is accessing MMIO.
8439          * The vm-exit can be triggered again after return to guest that
8440          * will cause infinite loop.
8441          */
8442         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8443                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8444                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8445                         exit_reason != EXIT_REASON_PML_FULL &&
8446                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8447                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8448                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8449                 vcpu->run->internal.ndata = 2;
8450                 vcpu->run->internal.data[0] = vectoring_info;
8451                 vcpu->run->internal.data[1] = exit_reason;
8452                 return 0;
8453         }
8454
8455         if (exit_reason < kvm_vmx_max_exit_handlers
8456             && kvm_vmx_exit_handlers[exit_reason])
8457                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8458         else {
8459                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8460                                 exit_reason);
8461                 kvm_queue_exception(vcpu, UD_VECTOR);
8462                 return 1;
8463         }
8464 }
8465
8466 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8467 {
8468         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8469
8470         if (is_guest_mode(vcpu) &&
8471                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8472                 return;
8473
8474         if (irr == -1 || tpr < irr) {
8475                 vmcs_write32(TPR_THRESHOLD, 0);
8476                 return;
8477         }
8478
8479         vmcs_write32(TPR_THRESHOLD, irr);
8480 }
8481
8482 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8483 {
8484         u32 sec_exec_control;
8485
8486         /* Postpone execution until vmcs01 is the current VMCS. */
8487         if (is_guest_mode(vcpu)) {
8488                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8489                 return;
8490         }
8491
8492         if (!cpu_has_vmx_virtualize_x2apic_mode())
8493                 return;
8494
8495         if (!cpu_need_tpr_shadow(vcpu))
8496                 return;
8497
8498         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8499
8500         if (set) {
8501                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8502                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8503         } else {
8504                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8505                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8506                 vmx_flush_tlb_ept_only(vcpu);
8507         }
8508         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8509
8510         vmx_set_msr_bitmap(vcpu);
8511 }
8512
8513 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8514 {
8515         struct vcpu_vmx *vmx = to_vmx(vcpu);
8516
8517         /*
8518          * Currently we do not handle the nested case where L2 has an
8519          * APIC access page of its own; that page is still pinned.
8520          * Hence, we skip the case where the VCPU is in guest mode _and_
8521          * L1 prepared an APIC access page for L2.
8522          *
8523          * For the case where L1 and L2 share the same APIC access page
8524          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8525          * in the vmcs12), this function will only update either the vmcs01
8526          * or the vmcs02.  If the former, the vmcs02 will be updated by
8527          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8528          * the next L2->L1 exit.
8529          */
8530         if (!is_guest_mode(vcpu) ||
8531             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8532                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8533                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8534                 vmx_flush_tlb_ept_only(vcpu);
8535         }
8536 }
8537
8538 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8539 {
8540         u16 status;
8541         u8 old;
8542
8543         if (max_isr == -1)
8544                 max_isr = 0;
8545
8546         status = vmcs_read16(GUEST_INTR_STATUS);
8547         old = status >> 8;
8548         if (max_isr != old) {
8549                 status &= 0xff;
8550                 status |= max_isr << 8;
8551                 vmcs_write16(GUEST_INTR_STATUS, status);
8552         }
8553 }
8554
8555 static void vmx_set_rvi(int vector)
8556 {
8557         u16 status;
8558         u8 old;
8559
8560         if (vector == -1)
8561                 vector = 0;
8562
8563         status = vmcs_read16(GUEST_INTR_STATUS);
8564         old = (u8)status & 0xff;
8565         if ((u8)vector != old) {
8566                 status &= ~0xff;
8567                 status |= (u8)vector;
8568                 vmcs_write16(GUEST_INTR_STATUS, status);
8569         }
8570 }
8571
8572 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8573 {
8574         if (!is_guest_mode(vcpu)) {
8575                 vmx_set_rvi(max_irr);
8576                 return;
8577         }
8578
8579         if (max_irr == -1)
8580                 return;
8581
8582         /*
8583          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8584          * handles it.
8585          */
8586         if (nested_exit_on_intr(vcpu))
8587                 return;
8588
8589         /*
8590          * Else, fall back to pre-APICv interrupt injection since L2
8591          * is run without virtual interrupt delivery.
8592          */
8593         if (!kvm_event_needs_reinjection(vcpu) &&
8594             vmx_interrupt_allowed(vcpu)) {
8595                 kvm_queue_interrupt(vcpu, max_irr, false);
8596                 vmx_inject_irq(vcpu);
8597         }
8598 }
8599
8600 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8601 {
8602         struct vcpu_vmx *vmx = to_vmx(vcpu);
8603         int max_irr;
8604
8605         WARN_ON(!vcpu->arch.apicv_active);
8606         if (pi_test_on(&vmx->pi_desc)) {
8607                 pi_clear_on(&vmx->pi_desc);
8608                 /*
8609                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8610                  * But on x86 this is just a compiler barrier anyway.
8611                  */
8612                 smp_mb__after_atomic();
8613                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8614         } else {
8615                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8616         }
8617         vmx_hwapic_irr_update(vcpu, max_irr);
8618         return max_irr;
8619 }
8620
8621 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8622 {
8623         if (!kvm_vcpu_apicv_active(vcpu))
8624                 return;
8625
8626         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8627         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8628         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8629         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8630 }
8631
8632 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8633 {
8634         struct vcpu_vmx *vmx = to_vmx(vcpu);
8635
8636         pi_clear_on(&vmx->pi_desc);
8637         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8638 }
8639
8640 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8641 {
8642         u32 exit_intr_info;
8643
8644         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8645               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8646                 return;
8647
8648         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8649         exit_intr_info = vmx->exit_intr_info;
8650
8651         /* Handle machine checks before interrupts are enabled */
8652         if (is_machine_check(exit_intr_info))
8653                 kvm_machine_check();
8654
8655         /* We need to handle NMIs before interrupts are enabled */
8656         if (is_nmi(exit_intr_info)) {
8657                 kvm_before_handle_nmi(&vmx->vcpu);
8658                 asm("int $2");
8659                 kvm_after_handle_nmi(&vmx->vcpu);
8660         }
8661 }
8662
8663 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8664 {
8665         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8666         register void *__sp asm(_ASM_SP);
8667
8668         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8669                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8670                 unsigned int vector;
8671                 unsigned long entry;
8672                 gate_desc *desc;
8673                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8674 #ifdef CONFIG_X86_64
8675                 unsigned long tmp;
8676 #endif
8677
8678                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8679                 desc = (gate_desc *)vmx->host_idt_base + vector;
8680                 entry = gate_offset(*desc);
8681                 asm volatile(
8682 #ifdef CONFIG_X86_64
8683                         "mov %%" _ASM_SP ", %[sp]\n\t"
8684                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8685                         "push $%c[ss]\n\t"
8686                         "push %[sp]\n\t"
8687 #endif
8688                         "pushf\n\t"
8689                         __ASM_SIZE(push) " $%c[cs]\n\t"
8690                         "call *%[entry]\n\t"
8691                         :
8692 #ifdef CONFIG_X86_64
8693                         [sp]"=&r"(tmp),
8694 #endif
8695                         "+r"(__sp)
8696                         :
8697                         [entry]"r"(entry),
8698                         [ss]"i"(__KERNEL_DS),
8699                         [cs]"i"(__KERNEL_CS)
8700                         );
8701         }
8702 }
8703
8704 static bool vmx_has_high_real_mode_segbase(void)
8705 {
8706         return enable_unrestricted_guest || emulate_invalid_guest_state;
8707 }
8708
8709 static bool vmx_mpx_supported(void)
8710 {
8711         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8712                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8713 }
8714
8715 static bool vmx_xsaves_supported(void)
8716 {
8717         return vmcs_config.cpu_based_2nd_exec_ctrl &
8718                 SECONDARY_EXEC_XSAVES;
8719 }
8720
8721 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8722 {
8723         u32 exit_intr_info;
8724         bool unblock_nmi;
8725         u8 vector;
8726         bool idtv_info_valid;
8727
8728         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8729
8730         if (vmx->nmi_known_unmasked)
8731                 return;
8732         /*
8733          * Can't use vmx->exit_intr_info since we're not sure what
8734          * the exit reason is.
8735          */
8736         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8737         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8738         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8739         /*
8740          * SDM 3: 27.7.1.2 (September 2008)
8741          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8742          * a guest IRET fault.
8743          * SDM 3: 23.2.2 (September 2008)
8744          * Bit 12 is undefined in any of the following cases:
8745          *  If the VM exit sets the valid bit in the IDT-vectoring
8746          *   information field.
8747          *  If the VM exit is due to a double fault.
8748          */
8749         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8750             vector != DF_VECTOR && !idtv_info_valid)
8751                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8752                               GUEST_INTR_STATE_NMI);
8753         else
8754                 vmx->nmi_known_unmasked =
8755                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8756                           & GUEST_INTR_STATE_NMI);
8757 }
8758
8759 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8760                                       u32 idt_vectoring_info,
8761                                       int instr_len_field,
8762                                       int error_code_field)
8763 {
8764         u8 vector;
8765         int type;
8766         bool idtv_info_valid;
8767
8768         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8769
8770         vcpu->arch.nmi_injected = false;
8771         kvm_clear_exception_queue(vcpu);
8772         kvm_clear_interrupt_queue(vcpu);
8773
8774         if (!idtv_info_valid)
8775                 return;
8776
8777         kvm_make_request(KVM_REQ_EVENT, vcpu);
8778
8779         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8780         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8781
8782         switch (type) {
8783         case INTR_TYPE_NMI_INTR:
8784                 vcpu->arch.nmi_injected = true;
8785                 /*
8786                  * SDM 3: 27.7.1.2 (September 2008)
8787                  * Clear bit "block by NMI" before VM entry if a NMI
8788                  * delivery faulted.
8789                  */
8790                 vmx_set_nmi_mask(vcpu, false);
8791                 break;
8792         case INTR_TYPE_SOFT_EXCEPTION:
8793                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8794                 /* fall through */
8795         case INTR_TYPE_HARD_EXCEPTION:
8796                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8797                         u32 err = vmcs_read32(error_code_field);
8798                         kvm_requeue_exception_e(vcpu, vector, err);
8799                 } else
8800                         kvm_requeue_exception(vcpu, vector);
8801                 break;
8802         case INTR_TYPE_SOFT_INTR:
8803                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8804                 /* fall through */
8805         case INTR_TYPE_EXT_INTR:
8806                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8807                 break;
8808         default:
8809                 break;
8810         }
8811 }
8812
8813 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8814 {
8815         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8816                                   VM_EXIT_INSTRUCTION_LEN,
8817                                   IDT_VECTORING_ERROR_CODE);
8818 }
8819
8820 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8821 {
8822         __vmx_complete_interrupts(vcpu,
8823                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8824                                   VM_ENTRY_INSTRUCTION_LEN,
8825                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8826
8827         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8828 }
8829
8830 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8831 {
8832         int i, nr_msrs;
8833         struct perf_guest_switch_msr *msrs;
8834
8835         msrs = perf_guest_get_msrs(&nr_msrs);
8836
8837         if (!msrs)
8838                 return;
8839
8840         for (i = 0; i < nr_msrs; i++)
8841                 if (msrs[i].host == msrs[i].guest)
8842                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8843                 else
8844                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8845                                         msrs[i].host);
8846 }
8847
8848 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8849 {
8850         struct vcpu_vmx *vmx = to_vmx(vcpu);
8851         u64 tscl;
8852         u32 delta_tsc;
8853
8854         if (vmx->hv_deadline_tsc == -1)
8855                 return;
8856
8857         tscl = rdtsc();
8858         if (vmx->hv_deadline_tsc > tscl)
8859                 /* sure to be 32 bit only because checked on set_hv_timer */
8860                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8861                         cpu_preemption_timer_multi);
8862         else
8863                 delta_tsc = 0;
8864
8865         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8866 }
8867
8868 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8869 {
8870         struct vcpu_vmx *vmx = to_vmx(vcpu);
8871         unsigned long debugctlmsr, cr4;
8872
8873         /* Don't enter VMX if guest state is invalid, let the exit handler
8874            start emulation until we arrive back to a valid state */
8875         if (vmx->emulation_required)
8876                 return;
8877
8878         if (vmx->ple_window_dirty) {
8879                 vmx->ple_window_dirty = false;
8880                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8881         }
8882
8883         if (vmx->nested.sync_shadow_vmcs) {
8884                 copy_vmcs12_to_shadow(vmx);
8885                 vmx->nested.sync_shadow_vmcs = false;
8886         }
8887
8888         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8889                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8890         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8891                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8892
8893         cr4 = cr4_read_shadow();
8894         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8895                 vmcs_writel(HOST_CR4, cr4);
8896                 vmx->host_state.vmcs_host_cr4 = cr4;
8897         }
8898
8899         /* When single-stepping over STI and MOV SS, we must clear the
8900          * corresponding interruptibility bits in the guest state. Otherwise
8901          * vmentry fails as it then expects bit 14 (BS) in pending debug
8902          * exceptions being set, but that's not correct for the guest debugging
8903          * case. */
8904         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8905                 vmx_set_interrupt_shadow(vcpu, 0);
8906
8907         if (vmx->guest_pkru_valid)
8908                 __write_pkru(vmx->guest_pkru);
8909
8910         atomic_switch_perf_msrs(vmx);
8911         debugctlmsr = get_debugctlmsr();
8912
8913         vmx_arm_hv_timer(vcpu);
8914
8915         vmx->__launched = vmx->loaded_vmcs->launched;
8916         asm(
8917                 /* Store host registers */
8918                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8919                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8920                 "push %%" _ASM_CX " \n\t"
8921                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8922                 "je 1f \n\t"
8923                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8924                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8925                 "1: \n\t"
8926                 /* Reload cr2 if changed */
8927                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8928                 "mov %%cr2, %%" _ASM_DX " \n\t"
8929                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8930                 "je 2f \n\t"
8931                 "mov %%" _ASM_AX", %%cr2 \n\t"
8932                 "2: \n\t"
8933                 /* Check if vmlaunch of vmresume is needed */
8934                 "cmpl $0, %c[launched](%0) \n\t"
8935                 /* Load guest registers.  Don't clobber flags. */
8936                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8937                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8938                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8939                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8940                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8941                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8942 #ifdef CONFIG_X86_64
8943                 "mov %c[r8](%0),  %%r8  \n\t"
8944                 "mov %c[r9](%0),  %%r9  \n\t"
8945                 "mov %c[r10](%0), %%r10 \n\t"
8946                 "mov %c[r11](%0), %%r11 \n\t"
8947                 "mov %c[r12](%0), %%r12 \n\t"
8948                 "mov %c[r13](%0), %%r13 \n\t"
8949                 "mov %c[r14](%0), %%r14 \n\t"
8950                 "mov %c[r15](%0), %%r15 \n\t"
8951 #endif
8952                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8953
8954                 /* Enter guest mode */
8955                 "jne 1f \n\t"
8956                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8957                 "jmp 2f \n\t"
8958                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8959                 "2: "
8960                 /* Save guest registers, load host registers, keep flags */
8961                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8962                 "pop %0 \n\t"
8963                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8964                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8965                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8966                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8967                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8968                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8969                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8970 #ifdef CONFIG_X86_64
8971                 "mov %%r8,  %c[r8](%0) \n\t"
8972                 "mov %%r9,  %c[r9](%0) \n\t"
8973                 "mov %%r10, %c[r10](%0) \n\t"
8974                 "mov %%r11, %c[r11](%0) \n\t"
8975                 "mov %%r12, %c[r12](%0) \n\t"
8976                 "mov %%r13, %c[r13](%0) \n\t"
8977                 "mov %%r14, %c[r14](%0) \n\t"
8978                 "mov %%r15, %c[r15](%0) \n\t"
8979 #endif
8980                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8981                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8982
8983                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8984                 "setbe %c[fail](%0) \n\t"
8985                 ".pushsection .rodata \n\t"
8986                 ".global vmx_return \n\t"
8987                 "vmx_return: " _ASM_PTR " 2b \n\t"
8988                 ".popsection"
8989               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8990                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8991                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8992                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8993                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8994                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8995                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8996                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8997                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8998                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8999                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9000 #ifdef CONFIG_X86_64
9001                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9002                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9003                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9004                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9005                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9006                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9007                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9008                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9009 #endif
9010                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9011                 [wordsize]"i"(sizeof(ulong))
9012               : "cc", "memory"
9013 #ifdef CONFIG_X86_64
9014                 , "rax", "rbx", "rdi", "rsi"
9015                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9016 #else
9017                 , "eax", "ebx", "edi", "esi"
9018 #endif
9019               );
9020
9021         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9022         if (debugctlmsr)
9023                 update_debugctlmsr(debugctlmsr);
9024
9025 #ifndef CONFIG_X86_64
9026         /*
9027          * The sysexit path does not restore ds/es, so we must set them to
9028          * a reasonable value ourselves.
9029          *
9030          * We can't defer this to vmx_load_host_state() since that function
9031          * may be executed in interrupt context, which saves and restore segments
9032          * around it, nullifying its effect.
9033          */
9034         loadsegment(ds, __USER_DS);
9035         loadsegment(es, __USER_DS);
9036 #endif
9037
9038         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9039                                   | (1 << VCPU_EXREG_RFLAGS)
9040                                   | (1 << VCPU_EXREG_PDPTR)
9041                                   | (1 << VCPU_EXREG_SEGMENTS)
9042                                   | (1 << VCPU_EXREG_CR3));
9043         vcpu->arch.regs_dirty = 0;
9044
9045         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9046
9047         vmx->loaded_vmcs->launched = 1;
9048
9049         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9050
9051         /*
9052          * eager fpu is enabled if PKEY is supported and CR4 is switched
9053          * back on host, so it is safe to read guest PKRU from current
9054          * XSAVE.
9055          */
9056         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9057                 vmx->guest_pkru = __read_pkru();
9058                 if (vmx->guest_pkru != vmx->host_pkru) {
9059                         vmx->guest_pkru_valid = true;
9060                         __write_pkru(vmx->host_pkru);
9061                 } else
9062                         vmx->guest_pkru_valid = false;
9063         }
9064
9065         /*
9066          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9067          * we did not inject a still-pending event to L1 now because of
9068          * nested_run_pending, we need to re-enable this bit.
9069          */
9070         if (vmx->nested.nested_run_pending)
9071                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9072
9073         vmx->nested.nested_run_pending = 0;
9074
9075         vmx_complete_atomic_exit(vmx);
9076         vmx_recover_nmi_blocking(vmx);
9077         vmx_complete_interrupts(vmx);
9078 }
9079
9080 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9081 {
9082         struct vcpu_vmx *vmx = to_vmx(vcpu);
9083         int cpu;
9084
9085         if (vmx->loaded_vmcs == vmcs)
9086                 return;
9087
9088         cpu = get_cpu();
9089         vmx->loaded_vmcs = vmcs;
9090         vmx_vcpu_put(vcpu);
9091         vmx_vcpu_load(vcpu, cpu);
9092         vcpu->cpu = cpu;
9093         put_cpu();
9094 }
9095
9096 /*
9097  * Ensure that the current vmcs of the logical processor is the
9098  * vmcs01 of the vcpu before calling free_nested().
9099  */
9100 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9101 {
9102        struct vcpu_vmx *vmx = to_vmx(vcpu);
9103        int r;
9104
9105        r = vcpu_load(vcpu);
9106        BUG_ON(r);
9107        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9108        free_nested(vmx);
9109        vcpu_put(vcpu);
9110 }
9111
9112 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9113 {
9114         struct vcpu_vmx *vmx = to_vmx(vcpu);
9115
9116         if (enable_pml)
9117                 vmx_destroy_pml_buffer(vmx);
9118         free_vpid(vmx->vpid);
9119         leave_guest_mode(vcpu);
9120         vmx_free_vcpu_nested(vcpu);
9121         free_loaded_vmcs(vmx->loaded_vmcs);
9122         kfree(vmx->guest_msrs);
9123         kvm_vcpu_uninit(vcpu);
9124         kmem_cache_free(kvm_vcpu_cache, vmx);
9125 }
9126
9127 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9128 {
9129         int err;
9130         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9131         int cpu;
9132
9133         if (!vmx)
9134                 return ERR_PTR(-ENOMEM);
9135
9136         vmx->vpid = allocate_vpid();
9137
9138         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9139         if (err)
9140                 goto free_vcpu;
9141
9142         err = -ENOMEM;
9143
9144         /*
9145          * If PML is turned on, failure on enabling PML just results in failure
9146          * of creating the vcpu, therefore we can simplify PML logic (by
9147          * avoiding dealing with cases, such as enabling PML partially on vcpus
9148          * for the guest, etc.
9149          */
9150         if (enable_pml) {
9151                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9152                 if (!vmx->pml_pg)
9153                         goto uninit_vcpu;
9154         }
9155
9156         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9157         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9158                      > PAGE_SIZE);
9159
9160         if (!vmx->guest_msrs)
9161                 goto free_pml;
9162
9163         vmx->loaded_vmcs = &vmx->vmcs01;
9164         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9165         vmx->loaded_vmcs->shadow_vmcs = NULL;
9166         if (!vmx->loaded_vmcs->vmcs)
9167                 goto free_msrs;
9168         if (!vmm_exclusive)
9169                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9170         loaded_vmcs_init(vmx->loaded_vmcs);
9171         if (!vmm_exclusive)
9172                 kvm_cpu_vmxoff();
9173
9174         cpu = get_cpu();
9175         vmx_vcpu_load(&vmx->vcpu, cpu);
9176         vmx->vcpu.cpu = cpu;
9177         err = vmx_vcpu_setup(vmx);
9178         vmx_vcpu_put(&vmx->vcpu);
9179         put_cpu();
9180         if (err)
9181                 goto free_vmcs;
9182         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9183                 err = alloc_apic_access_page(kvm);
9184                 if (err)
9185                         goto free_vmcs;
9186         }
9187
9188         if (enable_ept) {
9189                 if (!kvm->arch.ept_identity_map_addr)
9190                         kvm->arch.ept_identity_map_addr =
9191                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9192                 err = init_rmode_identity_map(kvm);
9193                 if (err)
9194                         goto free_vmcs;
9195         }
9196
9197         if (nested) {
9198                 nested_vmx_setup_ctls_msrs(vmx);
9199                 vmx->nested.vpid02 = allocate_vpid();
9200         }
9201
9202         vmx->nested.posted_intr_nv = -1;
9203         vmx->nested.current_vmptr = -1ull;
9204         vmx->nested.current_vmcs12 = NULL;
9205
9206         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9207
9208         return &vmx->vcpu;
9209
9210 free_vmcs:
9211         free_vpid(vmx->nested.vpid02);
9212         free_loaded_vmcs(vmx->loaded_vmcs);
9213 free_msrs:
9214         kfree(vmx->guest_msrs);
9215 free_pml:
9216         vmx_destroy_pml_buffer(vmx);
9217 uninit_vcpu:
9218         kvm_vcpu_uninit(&vmx->vcpu);
9219 free_vcpu:
9220         free_vpid(vmx->vpid);
9221         kmem_cache_free(kvm_vcpu_cache, vmx);
9222         return ERR_PTR(err);
9223 }
9224
9225 static void __init vmx_check_processor_compat(void *rtn)
9226 {
9227         struct vmcs_config vmcs_conf;
9228
9229         *(int *)rtn = 0;
9230         if (setup_vmcs_config(&vmcs_conf) < 0)
9231                 *(int *)rtn = -EIO;
9232         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9233                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9234                                 smp_processor_id());
9235                 *(int *)rtn = -EIO;
9236         }
9237 }
9238
9239 static int get_ept_level(void)
9240 {
9241         return VMX_EPT_DEFAULT_GAW + 1;
9242 }
9243
9244 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9245 {
9246         u8 cache;
9247         u64 ipat = 0;
9248
9249         /* For VT-d and EPT combination
9250          * 1. MMIO: always map as UC
9251          * 2. EPT with VT-d:
9252          *   a. VT-d without snooping control feature: can't guarantee the
9253          *      result, try to trust guest.
9254          *   b. VT-d with snooping control feature: snooping control feature of
9255          *      VT-d engine can guarantee the cache correctness. Just set it
9256          *      to WB to keep consistent with host. So the same as item 3.
9257          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9258          *    consistent with host MTRR
9259          */
9260         if (is_mmio) {
9261                 cache = MTRR_TYPE_UNCACHABLE;
9262                 goto exit;
9263         }
9264
9265         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9266                 ipat = VMX_EPT_IPAT_BIT;
9267                 cache = MTRR_TYPE_WRBACK;
9268                 goto exit;
9269         }
9270
9271         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9272                 ipat = VMX_EPT_IPAT_BIT;
9273                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9274                         cache = MTRR_TYPE_WRBACK;
9275                 else
9276                         cache = MTRR_TYPE_UNCACHABLE;
9277                 goto exit;
9278         }
9279
9280         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9281
9282 exit:
9283         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9284 }
9285
9286 static int vmx_get_lpage_level(void)
9287 {
9288         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9289                 return PT_DIRECTORY_LEVEL;
9290         else
9291                 /* For shadow and EPT supported 1GB page */
9292                 return PT_PDPE_LEVEL;
9293 }
9294
9295 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9296 {
9297         /*
9298          * These bits in the secondary execution controls field
9299          * are dynamic, the others are mostly based on the hypervisor
9300          * architecture and the guest's CPUID.  Do not touch the
9301          * dynamic bits.
9302          */
9303         u32 mask =
9304                 SECONDARY_EXEC_SHADOW_VMCS |
9305                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9306                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9307
9308         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9309
9310         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9311                      (new_ctl & ~mask) | (cur_ctl & mask));
9312 }
9313
9314 /*
9315  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9316  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9317  */
9318 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9319 {
9320         struct vcpu_vmx *vmx = to_vmx(vcpu);
9321         struct kvm_cpuid_entry2 *entry;
9322
9323         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9324         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9325
9326 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9327         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9328                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9329 } while (0)
9330
9331         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9332         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9333         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9334         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9335         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9336         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9337         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9338         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9339         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9340         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9341         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9342         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9343         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9344         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9345         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9346
9347         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9348         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9349         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9350         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9351         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9352         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9353         cr4_fixed1_update(bit(11),            ecx, bit(2));
9354
9355 #undef cr4_fixed1_update
9356 }
9357
9358 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9359 {
9360         struct kvm_cpuid_entry2 *best;
9361         struct vcpu_vmx *vmx = to_vmx(vcpu);
9362         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9363
9364         if (vmx_rdtscp_supported()) {
9365                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9366                 if (!rdtscp_enabled)
9367                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9368
9369                 if (nested) {
9370                         if (rdtscp_enabled)
9371                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9372                                         SECONDARY_EXEC_RDTSCP;
9373                         else
9374                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9375                                         ~SECONDARY_EXEC_RDTSCP;
9376                 }
9377         }
9378
9379         /* Exposing INVPCID only when PCID is exposed */
9380         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9381         if (vmx_invpcid_supported() &&
9382             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9383             !guest_cpuid_has_pcid(vcpu))) {
9384                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9385
9386                 if (best)
9387                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9388         }
9389
9390         if (cpu_has_secondary_exec_ctrls())
9391                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9392
9393         if (nested_vmx_allowed(vcpu))
9394                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9395                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9396         else
9397                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9398                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9399
9400         if (nested_vmx_allowed(vcpu))
9401                 nested_vmx_cr_fixed1_bits_update(vcpu);
9402 }
9403
9404 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9405 {
9406         if (func == 1 && nested)
9407                 entry->ecx |= bit(X86_FEATURE_VMX);
9408 }
9409
9410 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9411                 struct x86_exception *fault)
9412 {
9413         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9414         u32 exit_reason;
9415
9416         if (fault->error_code & PFERR_RSVD_MASK)
9417                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9418         else
9419                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9420         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9421         vmcs12->guest_physical_address = fault->address;
9422 }
9423
9424 /* Callbacks for nested_ept_init_mmu_context: */
9425
9426 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9427 {
9428         /* return the page table to be shadowed - in our case, EPT12 */
9429         return get_vmcs12(vcpu)->ept_pointer;
9430 }
9431
9432 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9433 {
9434         u64 eptp;
9435
9436         WARN_ON(mmu_is_nested(vcpu));
9437         eptp = nested_ept_get_cr3(vcpu);
9438         if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits)
9439                 return 1;
9440
9441         kvm_mmu_unload(vcpu);
9442         kvm_init_shadow_ept_mmu(vcpu,
9443                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9444                         VMX_EPT_EXECUTE_ONLY_BIT,
9445                         eptp & VMX_EPT_AD_ENABLE_BIT);
9446         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9447         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9448         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9449
9450         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9451         return 0;
9452 }
9453
9454 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9455 {
9456         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9457 }
9458
9459 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9460                                             u16 error_code)
9461 {
9462         bool inequality, bit;
9463
9464         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9465         inequality =
9466                 (error_code & vmcs12->page_fault_error_code_mask) !=
9467                  vmcs12->page_fault_error_code_match;
9468         return inequality ^ bit;
9469 }
9470
9471 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9472                 struct x86_exception *fault)
9473 {
9474         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9475
9476         WARN_ON(!is_guest_mode(vcpu));
9477
9478         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9479                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9480                                   vmcs_read32(VM_EXIT_INTR_INFO),
9481                                   vmcs_readl(EXIT_QUALIFICATION));
9482         else
9483                 kvm_inject_page_fault(vcpu, fault);
9484 }
9485
9486 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9487                                                struct vmcs12 *vmcs12);
9488
9489 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9490                                         struct vmcs12 *vmcs12)
9491 {
9492         struct vcpu_vmx *vmx = to_vmx(vcpu);
9493         u64 hpa;
9494
9495         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9496                 /*
9497                  * Translate L1 physical address to host physical
9498                  * address for vmcs02. Keep the page pinned, so this
9499                  * physical address remains valid. We keep a reference
9500                  * to it so we can release it later.
9501                  */
9502                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9503                         nested_release_page(vmx->nested.apic_access_page);
9504                 vmx->nested.apic_access_page =
9505                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9506                 /*
9507                  * If translation failed, no matter: This feature asks
9508                  * to exit when accessing the given address, and if it
9509                  * can never be accessed, this feature won't do
9510                  * anything anyway.
9511                  */
9512                 if (vmx->nested.apic_access_page) {
9513                         hpa = page_to_phys(vmx->nested.apic_access_page);
9514                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9515                 } else {
9516                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9517                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9518                 }
9519         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9520                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9521                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9522                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9523                 kvm_vcpu_reload_apic_access_page(vcpu);
9524         }
9525
9526         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9527                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9528                         nested_release_page(vmx->nested.virtual_apic_page);
9529                 vmx->nested.virtual_apic_page =
9530                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9531
9532                 /*
9533                  * If translation failed, VM entry will fail because
9534                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9535                  * Failing the vm entry is _not_ what the processor
9536                  * does but it's basically the only possibility we
9537                  * have.  We could still enter the guest if CR8 load
9538                  * exits are enabled, CR8 store exits are enabled, and
9539                  * virtualize APIC access is disabled; in this case
9540                  * the processor would never use the TPR shadow and we
9541                  * could simply clear the bit from the execution
9542                  * control.  But such a configuration is useless, so
9543                  * let's keep the code simple.
9544                  */
9545                 if (vmx->nested.virtual_apic_page) {
9546                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9547                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9548                 }
9549         }
9550
9551         if (nested_cpu_has_posted_intr(vmcs12)) {
9552                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9553                         kunmap(vmx->nested.pi_desc_page);
9554                         nested_release_page(vmx->nested.pi_desc_page);
9555                 }
9556                 vmx->nested.pi_desc_page =
9557                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9558                 vmx->nested.pi_desc =
9559                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9560                 if (!vmx->nested.pi_desc) {
9561                         nested_release_page_clean(vmx->nested.pi_desc_page);
9562                         return;
9563                 }
9564                 vmx->nested.pi_desc =
9565                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9566                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9567                         (PAGE_SIZE - 1)));
9568                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9569                         page_to_phys(vmx->nested.pi_desc_page) +
9570                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9571                         (PAGE_SIZE - 1)));
9572         }
9573         if (cpu_has_vmx_msr_bitmap() &&
9574             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9575             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9576                 ;
9577         else
9578                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9579                                 CPU_BASED_USE_MSR_BITMAPS);
9580 }
9581
9582 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9583 {
9584         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9585         struct vcpu_vmx *vmx = to_vmx(vcpu);
9586
9587         if (vcpu->arch.virtual_tsc_khz == 0)
9588                 return;
9589
9590         /* Make sure short timeouts reliably trigger an immediate vmexit.
9591          * hrtimer_start does not guarantee this. */
9592         if (preemption_timeout <= 1) {
9593                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9594                 return;
9595         }
9596
9597         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9598         preemption_timeout *= 1000000;
9599         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9600         hrtimer_start(&vmx->nested.preemption_timer,
9601                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9602 }
9603
9604 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9605                                                 struct vmcs12 *vmcs12)
9606 {
9607         int maxphyaddr;
9608         u64 addr;
9609
9610         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9611                 return 0;
9612
9613         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9614                 WARN_ON(1);
9615                 return -EINVAL;
9616         }
9617         maxphyaddr = cpuid_maxphyaddr(vcpu);
9618
9619         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9620            ((addr + PAGE_SIZE) >> maxphyaddr))
9621                 return -EINVAL;
9622
9623         return 0;
9624 }
9625
9626 /*
9627  * Merge L0's and L1's MSR bitmap, return false to indicate that
9628  * we do not use the hardware.
9629  */
9630 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9631                                                struct vmcs12 *vmcs12)
9632 {
9633         int msr;
9634         struct page *page;
9635         unsigned long *msr_bitmap_l1;
9636         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9637
9638         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9639         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9640                 return false;
9641
9642         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9643         if (!page)
9644                 return false;
9645         msr_bitmap_l1 = (unsigned long *)kmap(page);
9646
9647         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9648
9649         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9650                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9651                         for (msr = 0x800; msr <= 0x8ff; msr++)
9652                                 nested_vmx_disable_intercept_for_msr(
9653                                         msr_bitmap_l1, msr_bitmap_l0,
9654                                         msr, MSR_TYPE_R);
9655
9656                 nested_vmx_disable_intercept_for_msr(
9657                                 msr_bitmap_l1, msr_bitmap_l0,
9658                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9659                                 MSR_TYPE_R | MSR_TYPE_W);
9660
9661                 if (nested_cpu_has_vid(vmcs12)) {
9662                         nested_vmx_disable_intercept_for_msr(
9663                                 msr_bitmap_l1, msr_bitmap_l0,
9664                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9665                                 MSR_TYPE_W);
9666                         nested_vmx_disable_intercept_for_msr(
9667                                 msr_bitmap_l1, msr_bitmap_l0,
9668                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9669                                 MSR_TYPE_W);
9670                 }
9671         }
9672         kunmap(page);
9673         nested_release_page_clean(page);
9674
9675         return true;
9676 }
9677
9678 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9679                                            struct vmcs12 *vmcs12)
9680 {
9681         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9682             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9683             !nested_cpu_has_vid(vmcs12) &&
9684             !nested_cpu_has_posted_intr(vmcs12))
9685                 return 0;
9686
9687         /*
9688          * If virtualize x2apic mode is enabled,
9689          * virtualize apic access must be disabled.
9690          */
9691         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9692             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9693                 return -EINVAL;
9694
9695         /*
9696          * If virtual interrupt delivery is enabled,
9697          * we must exit on external interrupts.
9698          */
9699         if (nested_cpu_has_vid(vmcs12) &&
9700            !nested_exit_on_intr(vcpu))
9701                 return -EINVAL;
9702
9703         /*
9704          * bits 15:8 should be zero in posted_intr_nv,
9705          * the descriptor address has been already checked
9706          * in nested_get_vmcs12_pages.
9707          */
9708         if (nested_cpu_has_posted_intr(vmcs12) &&
9709            (!nested_cpu_has_vid(vmcs12) ||
9710             !nested_exit_intr_ack_set(vcpu) ||
9711             vmcs12->posted_intr_nv & 0xff00))
9712                 return -EINVAL;
9713
9714         /* tpr shadow is needed by all apicv features. */
9715         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9716                 return -EINVAL;
9717
9718         return 0;
9719 }
9720
9721 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9722                                        unsigned long count_field,
9723                                        unsigned long addr_field)
9724 {
9725         int maxphyaddr;
9726         u64 count, addr;
9727
9728         if (vmcs12_read_any(vcpu, count_field, &count) ||
9729             vmcs12_read_any(vcpu, addr_field, &addr)) {
9730                 WARN_ON(1);
9731                 return -EINVAL;
9732         }
9733         if (count == 0)
9734                 return 0;
9735         maxphyaddr = cpuid_maxphyaddr(vcpu);
9736         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9737             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9738                 pr_debug_ratelimited(
9739                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9740                         addr_field, maxphyaddr, count, addr);
9741                 return -EINVAL;
9742         }
9743         return 0;
9744 }
9745
9746 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9747                                                 struct vmcs12 *vmcs12)
9748 {
9749         if (vmcs12->vm_exit_msr_load_count == 0 &&
9750             vmcs12->vm_exit_msr_store_count == 0 &&
9751             vmcs12->vm_entry_msr_load_count == 0)
9752                 return 0; /* Fast path */
9753         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9754                                         VM_EXIT_MSR_LOAD_ADDR) ||
9755             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9756                                         VM_EXIT_MSR_STORE_ADDR) ||
9757             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9758                                         VM_ENTRY_MSR_LOAD_ADDR))
9759                 return -EINVAL;
9760         return 0;
9761 }
9762
9763 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9764                                        struct vmx_msr_entry *e)
9765 {
9766         /* x2APIC MSR accesses are not allowed */
9767         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9768                 return -EINVAL;
9769         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9770             e->index == MSR_IA32_UCODE_REV)
9771                 return -EINVAL;
9772         if (e->reserved != 0)
9773                 return -EINVAL;
9774         return 0;
9775 }
9776
9777 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9778                                      struct vmx_msr_entry *e)
9779 {
9780         if (e->index == MSR_FS_BASE ||
9781             e->index == MSR_GS_BASE ||
9782             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9783             nested_vmx_msr_check_common(vcpu, e))
9784                 return -EINVAL;
9785         return 0;
9786 }
9787
9788 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9789                                       struct vmx_msr_entry *e)
9790 {
9791         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9792             nested_vmx_msr_check_common(vcpu, e))
9793                 return -EINVAL;
9794         return 0;
9795 }
9796
9797 /*
9798  * Load guest's/host's msr at nested entry/exit.
9799  * return 0 for success, entry index for failure.
9800  */
9801 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9802 {
9803         u32 i;
9804         struct vmx_msr_entry e;
9805         struct msr_data msr;
9806
9807         msr.host_initiated = false;
9808         for (i = 0; i < count; i++) {
9809                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9810                                         &e, sizeof(e))) {
9811                         pr_debug_ratelimited(
9812                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9813                                 __func__, i, gpa + i * sizeof(e));
9814                         goto fail;
9815                 }
9816                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9817                         pr_debug_ratelimited(
9818                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9819                                 __func__, i, e.index, e.reserved);
9820                         goto fail;
9821                 }
9822                 msr.index = e.index;
9823                 msr.data = e.value;
9824                 if (kvm_set_msr(vcpu, &msr)) {
9825                         pr_debug_ratelimited(
9826                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9827                                 __func__, i, e.index, e.value);
9828                         goto fail;
9829                 }
9830         }
9831         return 0;
9832 fail:
9833         return i + 1;
9834 }
9835
9836 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9837 {
9838         u32 i;
9839         struct vmx_msr_entry e;
9840
9841         for (i = 0; i < count; i++) {
9842                 struct msr_data msr_info;
9843                 if (kvm_vcpu_read_guest(vcpu,
9844                                         gpa + i * sizeof(e),
9845                                         &e, 2 * sizeof(u32))) {
9846                         pr_debug_ratelimited(
9847                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9848                                 __func__, i, gpa + i * sizeof(e));
9849                         return -EINVAL;
9850                 }
9851                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9852                         pr_debug_ratelimited(
9853                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9854                                 __func__, i, e.index, e.reserved);
9855                         return -EINVAL;
9856                 }
9857                 msr_info.host_initiated = false;
9858                 msr_info.index = e.index;
9859                 if (kvm_get_msr(vcpu, &msr_info)) {
9860                         pr_debug_ratelimited(
9861                                 "%s cannot read MSR (%u, 0x%x)\n",
9862                                 __func__, i, e.index);
9863                         return -EINVAL;
9864                 }
9865                 if (kvm_vcpu_write_guest(vcpu,
9866                                          gpa + i * sizeof(e) +
9867                                              offsetof(struct vmx_msr_entry, value),
9868                                          &msr_info.data, sizeof(msr_info.data))) {
9869                         pr_debug_ratelimited(
9870                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9871                                 __func__, i, e.index, msr_info.data);
9872                         return -EINVAL;
9873                 }
9874         }
9875         return 0;
9876 }
9877
9878 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9879 {
9880         unsigned long invalid_mask;
9881
9882         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9883         return (val & invalid_mask) == 0;
9884 }
9885
9886 /*
9887  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9888  * emulating VM entry into a guest with EPT enabled.
9889  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9890  * is assigned to entry_failure_code on failure.
9891  */
9892 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9893                                u32 *entry_failure_code)
9894 {
9895         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9896                 if (!nested_cr3_valid(vcpu, cr3)) {
9897                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9898                         return 1;
9899                 }
9900
9901                 /*
9902                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9903                  * must not be dereferenced.
9904                  */
9905                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9906                     !nested_ept) {
9907                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9908                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9909                                 return 1;
9910                         }
9911                 }
9912
9913                 vcpu->arch.cr3 = cr3;
9914                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9915         }
9916
9917         kvm_mmu_reset_context(vcpu);
9918         return 0;
9919 }
9920
9921 /*
9922  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9923  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9924  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9925  * guest in a way that will both be appropriate to L1's requests, and our
9926  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9927  * function also has additional necessary side-effects, like setting various
9928  * vcpu->arch fields.
9929  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9930  * is assigned to entry_failure_code on failure.
9931  */
9932 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9933                           bool from_vmentry, u32 *entry_failure_code)
9934 {
9935         struct vcpu_vmx *vmx = to_vmx(vcpu);
9936         u32 exec_control;
9937
9938         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9939         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9940         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9941         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9942         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9943         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9944         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9945         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9946         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9947         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9948         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9949         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9950         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9951         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9952         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9953         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9954         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9955         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9956         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9957         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9958         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9959         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9960         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9961         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9962         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9963         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9964         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9965         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9966         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9967         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9968         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9969         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9970         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9971         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9972         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9973         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9974
9975         if (from_vmentry &&
9976             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
9977                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9978                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9979         } else {
9980                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9981                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9982         }
9983         if (from_vmentry) {
9984                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9985                              vmcs12->vm_entry_intr_info_field);
9986                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9987                              vmcs12->vm_entry_exception_error_code);
9988                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9989                              vmcs12->vm_entry_instruction_len);
9990                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9991                              vmcs12->guest_interruptibility_info);
9992         } else {
9993                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9994         }
9995         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9996         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9997         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9998                 vmcs12->guest_pending_dbg_exceptions);
9999         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10000         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10001
10002         if (nested_cpu_has_xsaves(vmcs12))
10003                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10004         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10005
10006         exec_control = vmcs12->pin_based_vm_exec_control;
10007
10008         /* Preemption timer setting is only taken from vmcs01.  */
10009         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10010         exec_control |= vmcs_config.pin_based_exec_ctrl;
10011         if (vmx->hv_deadline_tsc == -1)
10012                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10013
10014         /* Posted interrupts setting is only taken from vmcs12.  */
10015         if (nested_cpu_has_posted_intr(vmcs12)) {
10016                 /*
10017                  * Note that we use L0's vector here and in
10018                  * vmx_deliver_nested_posted_interrupt.
10019                  */
10020                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10021                 vmx->nested.pi_pending = false;
10022                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10023         } else {
10024                 exec_control &= ~PIN_BASED_POSTED_INTR;
10025         }
10026
10027         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10028
10029         vmx->nested.preemption_timer_expired = false;
10030         if (nested_cpu_has_preemption_timer(vmcs12))
10031                 vmx_start_preemption_timer(vcpu);
10032
10033         /*
10034          * Whether page-faults are trapped is determined by a combination of
10035          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10036          * If enable_ept, L0 doesn't care about page faults and we should
10037          * set all of these to L1's desires. However, if !enable_ept, L0 does
10038          * care about (at least some) page faults, and because it is not easy
10039          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10040          * to exit on each and every L2 page fault. This is done by setting
10041          * MASK=MATCH=0 and (see below) EB.PF=1.
10042          * Note that below we don't need special code to set EB.PF beyond the
10043          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10044          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10045          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10046          *
10047          * A problem with this approach (when !enable_ept) is that L1 may be
10048          * injected with more page faults than it asked for. This could have
10049          * caused problems, but in practice existing hypervisors don't care.
10050          * To fix this, we will need to emulate the PFEC checking (on the L1
10051          * page tables), using walk_addr(), when injecting PFs to L1.
10052          */
10053         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10054                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10055         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10056                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10057
10058         if (cpu_has_secondary_exec_ctrls()) {
10059                 exec_control = vmx_secondary_exec_control(vmx);
10060
10061                 /* Take the following fields only from vmcs12 */
10062                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10063                                   SECONDARY_EXEC_RDTSCP |
10064                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10065                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10066                 if (nested_cpu_has(vmcs12,
10067                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10068                         exec_control |= vmcs12->secondary_vm_exec_control;
10069
10070                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10071                         vmcs_write64(EOI_EXIT_BITMAP0,
10072                                 vmcs12->eoi_exit_bitmap0);
10073                         vmcs_write64(EOI_EXIT_BITMAP1,
10074                                 vmcs12->eoi_exit_bitmap1);
10075                         vmcs_write64(EOI_EXIT_BITMAP2,
10076                                 vmcs12->eoi_exit_bitmap2);
10077                         vmcs_write64(EOI_EXIT_BITMAP3,
10078                                 vmcs12->eoi_exit_bitmap3);
10079                         vmcs_write16(GUEST_INTR_STATUS,
10080                                 vmcs12->guest_intr_status);
10081                 }
10082
10083                 /*
10084                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10085                  * nested_get_vmcs12_pages will either fix it up or
10086                  * remove the VM execution control.
10087                  */
10088                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10089                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10090
10091                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10092         }
10093
10094
10095         /*
10096          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10097          * Some constant fields are set here by vmx_set_constant_host_state().
10098          * Other fields are different per CPU, and will be set later when
10099          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10100          */
10101         vmx_set_constant_host_state(vmx);
10102
10103         /*
10104          * Set the MSR load/store lists to match L0's settings.
10105          */
10106         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10107         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10108         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10109         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10110         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10111
10112         /*
10113          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10114          * entry, but only if the current (host) sp changed from the value
10115          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10116          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10117          * here we just force the write to happen on entry.
10118          */
10119         vmx->host_rsp = 0;
10120
10121         exec_control = vmx_exec_control(vmx); /* L0's desires */
10122         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10123         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10124         exec_control &= ~CPU_BASED_TPR_SHADOW;
10125         exec_control |= vmcs12->cpu_based_vm_exec_control;
10126
10127         /*
10128          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10129          * nested_get_vmcs12_pages can't fix it up, the illegal value
10130          * will result in a VM entry failure.
10131          */
10132         if (exec_control & CPU_BASED_TPR_SHADOW) {
10133                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10134                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10135         }
10136
10137         /*
10138          * Merging of IO bitmap not currently supported.
10139          * Rather, exit every time.
10140          */
10141         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10142         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10143
10144         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10145
10146         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10147          * bitwise-or of what L1 wants to trap for L2, and what we want to
10148          * trap. Note that CR0.TS also needs updating - we do this later.
10149          */
10150         update_exception_bitmap(vcpu);
10151         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10152         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10153
10154         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10155          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10156          * bits are further modified by vmx_set_efer() below.
10157          */
10158         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10159
10160         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10161          * emulated by vmx_set_efer(), below.
10162          */
10163         vm_entry_controls_init(vmx,
10164                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10165                         ~VM_ENTRY_IA32E_MODE) |
10166                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10167
10168         if (from_vmentry &&
10169             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10170                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10171                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10172         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10173                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10174         }
10175
10176         set_cr4_guest_host_mask(vmx);
10177
10178         if (from_vmentry &&
10179             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10180                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10181
10182         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10183                 vmcs_write64(TSC_OFFSET,
10184                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10185         else
10186                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10187         if (kvm_has_tsc_control)
10188                 decache_tsc_multiplier(vmx);
10189
10190         if (enable_vpid) {
10191                 /*
10192                  * There is no direct mapping between vpid02 and vpid12, the
10193                  * vpid02 is per-vCPU for L0 and reused while the value of
10194                  * vpid12 is changed w/ one invvpid during nested vmentry.
10195                  * The vpid12 is allocated by L1 for L2, so it will not
10196                  * influence global bitmap(for vpid01 and vpid02 allocation)
10197                  * even if spawn a lot of nested vCPUs.
10198                  */
10199                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10200                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10201                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10202                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10203                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10204                         }
10205                 } else {
10206                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10207                         vmx_flush_tlb(vcpu);
10208                 }
10209
10210         }
10211
10212         if (nested_cpu_has_ept(vmcs12)) {
10213                 if (nested_ept_init_mmu_context(vcpu)) {
10214                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10215                         return 1;
10216                 }
10217         } else if (nested_cpu_has2(vmcs12,
10218                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10219                 vmx_flush_tlb_ept_only(vcpu);
10220         }
10221
10222         /*
10223          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10224          * bits which we consider mandatory enabled.
10225          * The CR0_READ_SHADOW is what L2 should have expected to read given
10226          * the specifications by L1; It's not enough to take
10227          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10228          * have more bits than L1 expected.
10229          */
10230         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10231         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10232
10233         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10234         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10235
10236         if (from_vmentry &&
10237             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10238                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10239         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10240                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10241         else
10242                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10243         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10244         vmx_set_efer(vcpu, vcpu->arch.efer);
10245
10246         /* Shadow page tables on either EPT or shadow page tables. */
10247         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10248                                 entry_failure_code))
10249                 return 1;
10250
10251         if (!enable_ept)
10252                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10253
10254         /*
10255          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10256          */
10257         if (enable_ept) {
10258                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10259                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10260                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10261                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10262         }
10263
10264         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10265         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10266         return 0;
10267 }
10268
10269 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10270 {
10271         struct vcpu_vmx *vmx = to_vmx(vcpu);
10272
10273         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10274             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10275                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10276
10277         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10278                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10279
10280         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10281                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10282
10283         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10284                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10285
10286         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10287                                 vmx->nested.nested_vmx_procbased_ctls_low,
10288                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10289             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10290                                 vmx->nested.nested_vmx_secondary_ctls_low,
10291                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10292             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10293                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10294                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10295             !vmx_control_verify(vmcs12->vm_exit_controls,
10296                                 vmx->nested.nested_vmx_exit_ctls_low,
10297                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10298             !vmx_control_verify(vmcs12->vm_entry_controls,
10299                                 vmx->nested.nested_vmx_entry_ctls_low,
10300                                 vmx->nested.nested_vmx_entry_ctls_high))
10301                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10302
10303         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10304             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10305             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10306                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10307
10308         return 0;
10309 }
10310
10311 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10312                                   u32 *exit_qual)
10313 {
10314         bool ia32e;
10315
10316         *exit_qual = ENTRY_FAIL_DEFAULT;
10317
10318         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10319             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10320                 return 1;
10321
10322         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10323             vmcs12->vmcs_link_pointer != -1ull) {
10324                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10325                 return 1;
10326         }
10327
10328         /*
10329          * If the load IA32_EFER VM-entry control is 1, the following checks
10330          * are performed on the field for the IA32_EFER MSR:
10331          * - Bits reserved in the IA32_EFER MSR must be 0.
10332          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10333          *   the IA-32e mode guest VM-exit control. It must also be identical
10334          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10335          *   CR0.PG) is 1.
10336          */
10337         if (to_vmx(vcpu)->nested.nested_run_pending &&
10338             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10339                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10340                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10341                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10342                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10343                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10344                         return 1;
10345         }
10346
10347         /*
10348          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10349          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10350          * the values of the LMA and LME bits in the field must each be that of
10351          * the host address-space size VM-exit control.
10352          */
10353         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10354                 ia32e = (vmcs12->vm_exit_controls &
10355                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10356                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10357                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10358                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10359                         return 1;
10360         }
10361
10362         return 0;
10363 }
10364
10365 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10366 {
10367         struct vcpu_vmx *vmx = to_vmx(vcpu);
10368         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10369         struct loaded_vmcs *vmcs02;
10370         u32 msr_entry_idx;
10371         u32 exit_qual;
10372
10373         vmcs02 = nested_get_current_vmcs02(vmx);
10374         if (!vmcs02)
10375                 return -ENOMEM;
10376
10377         enter_guest_mode(vcpu);
10378
10379         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10380                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10381
10382         vmx_switch_vmcs(vcpu, vmcs02);
10383         vmx_segment_cache_clear(vmx);
10384
10385         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10386                 leave_guest_mode(vcpu);
10387                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10388                 nested_vmx_entry_failure(vcpu, vmcs12,
10389                                          EXIT_REASON_INVALID_STATE, exit_qual);
10390                 return 1;
10391         }
10392
10393         nested_get_vmcs12_pages(vcpu, vmcs12);
10394
10395         msr_entry_idx = nested_vmx_load_msr(vcpu,
10396                                             vmcs12->vm_entry_msr_load_addr,
10397                                             vmcs12->vm_entry_msr_load_count);
10398         if (msr_entry_idx) {
10399                 leave_guest_mode(vcpu);
10400                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10401                 nested_vmx_entry_failure(vcpu, vmcs12,
10402                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10403                 return 1;
10404         }
10405
10406         vmcs12->launch_state = 1;
10407
10408         /*
10409          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10410          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10411          * returned as far as L1 is concerned. It will only return (and set
10412          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10413          */
10414         return 0;
10415 }
10416
10417 /*
10418  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10419  * for running an L2 nested guest.
10420  */
10421 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10422 {
10423         struct vmcs12 *vmcs12;
10424         struct vcpu_vmx *vmx = to_vmx(vcpu);
10425         u32 exit_qual;
10426         int ret;
10427
10428         if (!nested_vmx_check_permission(vcpu))
10429                 return 1;
10430
10431         if (!nested_vmx_check_vmcs12(vcpu))
10432                 goto out;
10433
10434         vmcs12 = get_vmcs12(vcpu);
10435
10436         if (enable_shadow_vmcs)
10437                 copy_shadow_to_vmcs12(vmx);
10438
10439         /*
10440          * The nested entry process starts with enforcing various prerequisites
10441          * on vmcs12 as required by the Intel SDM, and act appropriately when
10442          * they fail: As the SDM explains, some conditions should cause the
10443          * instruction to fail, while others will cause the instruction to seem
10444          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10445          * To speed up the normal (success) code path, we should avoid checking
10446          * for misconfigurations which will anyway be caught by the processor
10447          * when using the merged vmcs02.
10448          */
10449         if (vmcs12->launch_state == launch) {
10450                 nested_vmx_failValid(vcpu,
10451                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10452                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10453                 goto out;
10454         }
10455
10456         ret = check_vmentry_prereqs(vcpu, vmcs12);
10457         if (ret) {
10458                 nested_vmx_failValid(vcpu, ret);
10459                 goto out;
10460         }
10461
10462         /*
10463          * After this point, the trap flag no longer triggers a singlestep trap
10464          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10465          * This is not 100% correct; for performance reasons, we delegate most
10466          * of the checks on host state to the processor.  If those fail,
10467          * the singlestep trap is missed.
10468          */
10469         skip_emulated_instruction(vcpu);
10470
10471         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10472         if (ret) {
10473                 nested_vmx_entry_failure(vcpu, vmcs12,
10474                                          EXIT_REASON_INVALID_STATE, exit_qual);
10475                 return 1;
10476         }
10477
10478         /*
10479          * We're finally done with prerequisite checking, and can start with
10480          * the nested entry.
10481          */
10482
10483         ret = enter_vmx_non_root_mode(vcpu, true);
10484         if (ret)
10485                 return ret;
10486
10487         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10488                 return kvm_vcpu_halt(vcpu);
10489
10490         vmx->nested.nested_run_pending = 1;
10491
10492         return 1;
10493
10494 out:
10495         return kvm_skip_emulated_instruction(vcpu);
10496 }
10497
10498 /*
10499  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10500  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10501  * This function returns the new value we should put in vmcs12.guest_cr0.
10502  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10503  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10504  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10505  *     didn't trap the bit, because if L1 did, so would L0).
10506  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10507  *     been modified by L2, and L1 knows it. So just leave the old value of
10508  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10509  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10510  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10511  *     changed these bits, and therefore they need to be updated, but L0
10512  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10513  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10514  */
10515 static inline unsigned long
10516 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10517 {
10518         return
10519         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10520         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10521         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10522                         vcpu->arch.cr0_guest_owned_bits));
10523 }
10524
10525 static inline unsigned long
10526 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10527 {
10528         return
10529         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10530         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10531         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10532                         vcpu->arch.cr4_guest_owned_bits));
10533 }
10534
10535 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10536                                        struct vmcs12 *vmcs12)
10537 {
10538         u32 idt_vectoring;
10539         unsigned int nr;
10540
10541         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10542                 nr = vcpu->arch.exception.nr;
10543                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10544
10545                 if (kvm_exception_is_soft(nr)) {
10546                         vmcs12->vm_exit_instruction_len =
10547                                 vcpu->arch.event_exit_inst_len;
10548                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10549                 } else
10550                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10551
10552                 if (vcpu->arch.exception.has_error_code) {
10553                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10554                         vmcs12->idt_vectoring_error_code =
10555                                 vcpu->arch.exception.error_code;
10556                 }
10557
10558                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10559         } else if (vcpu->arch.nmi_injected) {
10560                 vmcs12->idt_vectoring_info_field =
10561                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10562         } else if (vcpu->arch.interrupt.pending) {
10563                 nr = vcpu->arch.interrupt.nr;
10564                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10565
10566                 if (vcpu->arch.interrupt.soft) {
10567                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10568                         vmcs12->vm_entry_instruction_len =
10569                                 vcpu->arch.event_exit_inst_len;
10570                 } else
10571                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10572
10573                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10574         }
10575 }
10576
10577 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10578 {
10579         struct vcpu_vmx *vmx = to_vmx(vcpu);
10580
10581         if (vcpu->arch.exception.pending ||
10582                 vcpu->arch.nmi_injected ||
10583                 vcpu->arch.interrupt.pending)
10584                 return -EBUSY;
10585
10586         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10587             vmx->nested.preemption_timer_expired) {
10588                 if (vmx->nested.nested_run_pending)
10589                         return -EBUSY;
10590                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10591                 return 0;
10592         }
10593
10594         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10595                 if (vmx->nested.nested_run_pending)
10596                         return -EBUSY;
10597                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10598                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10599                                   INTR_INFO_VALID_MASK, 0);
10600                 /*
10601                  * The NMI-triggered VM exit counts as injection:
10602                  * clear this one and block further NMIs.
10603                  */
10604                 vcpu->arch.nmi_pending = 0;
10605                 vmx_set_nmi_mask(vcpu, true);
10606                 return 0;
10607         }
10608
10609         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10610             nested_exit_on_intr(vcpu)) {
10611                 if (vmx->nested.nested_run_pending)
10612                         return -EBUSY;
10613                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10614                 return 0;
10615         }
10616
10617         vmx_complete_nested_posted_interrupt(vcpu);
10618         return 0;
10619 }
10620
10621 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10622 {
10623         ktime_t remaining =
10624                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10625         u64 value;
10626
10627         if (ktime_to_ns(remaining) <= 0)
10628                 return 0;
10629
10630         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10631         do_div(value, 1000000);
10632         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10633 }
10634
10635 /*
10636  * Update the guest state fields of vmcs12 to reflect changes that
10637  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10638  * VM-entry controls is also updated, since this is really a guest
10639  * state bit.)
10640  */
10641 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10642 {
10643         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10644         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10645
10646         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10647         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10648         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10649
10650         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10651         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10652         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10653         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10654         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10655         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10656         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10657         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10658         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10659         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10660         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10661         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10662         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10663         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10664         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10665         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10666         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10667         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10668         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10669         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10670         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10671         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10672         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10673         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10674         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10675         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10676         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10677         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10678         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10679         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10680         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10681         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10682         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10683         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10684         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10685         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10686
10687         vmcs12->guest_interruptibility_info =
10688                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10689         vmcs12->guest_pending_dbg_exceptions =
10690                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10691         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10692                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10693         else
10694                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10695
10696         if (nested_cpu_has_preemption_timer(vmcs12)) {
10697                 if (vmcs12->vm_exit_controls &
10698                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10699                         vmcs12->vmx_preemption_timer_value =
10700                                 vmx_get_preemption_timer_value(vcpu);
10701                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10702         }
10703
10704         /*
10705          * In some cases (usually, nested EPT), L2 is allowed to change its
10706          * own CR3 without exiting. If it has changed it, we must keep it.
10707          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10708          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10709          *
10710          * Additionally, restore L2's PDPTR to vmcs12.
10711          */
10712         if (enable_ept) {
10713                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10714                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10715                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10716                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10717                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10718         }
10719
10720         if (nested_cpu_has_ept(vmcs12))
10721                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10722
10723         if (nested_cpu_has_vid(vmcs12))
10724                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10725
10726         vmcs12->vm_entry_controls =
10727                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10728                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10729
10730         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10731                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10732                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10733         }
10734
10735         /* TODO: These cannot have changed unless we have MSR bitmaps and
10736          * the relevant bit asks not to trap the change */
10737         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10738                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10739         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10740                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10741         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10742         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10743         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10744         if (kvm_mpx_supported())
10745                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10746         if (nested_cpu_has_xsaves(vmcs12))
10747                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10748 }
10749
10750 /*
10751  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10752  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10753  * and this function updates it to reflect the changes to the guest state while
10754  * L2 was running (and perhaps made some exits which were handled directly by L0
10755  * without going back to L1), and to reflect the exit reason.
10756  * Note that we do not have to copy here all VMCS fields, just those that
10757  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10758  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10759  * which already writes to vmcs12 directly.
10760  */
10761 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10762                            u32 exit_reason, u32 exit_intr_info,
10763                            unsigned long exit_qualification)
10764 {
10765         /* update guest state fields: */
10766         sync_vmcs12(vcpu, vmcs12);
10767
10768         /* update exit information fields: */
10769
10770         vmcs12->vm_exit_reason = exit_reason;
10771         vmcs12->exit_qualification = exit_qualification;
10772
10773         vmcs12->vm_exit_intr_info = exit_intr_info;
10774         if ((vmcs12->vm_exit_intr_info &
10775              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10776             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10777                 vmcs12->vm_exit_intr_error_code =
10778                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10779         vmcs12->idt_vectoring_info_field = 0;
10780         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10781         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10782
10783         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10784                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10785                  * instead of reading the real value. */
10786                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10787
10788                 /*
10789                  * Transfer the event that L0 or L1 may wanted to inject into
10790                  * L2 to IDT_VECTORING_INFO_FIELD.
10791                  */
10792                 vmcs12_save_pending_event(vcpu, vmcs12);
10793         }
10794
10795         /*
10796          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10797          * preserved above and would only end up incorrectly in L1.
10798          */
10799         vcpu->arch.nmi_injected = false;
10800         kvm_clear_exception_queue(vcpu);
10801         kvm_clear_interrupt_queue(vcpu);
10802 }
10803
10804 /*
10805  * A part of what we need to when the nested L2 guest exits and we want to
10806  * run its L1 parent, is to reset L1's guest state to the host state specified
10807  * in vmcs12.
10808  * This function is to be called not only on normal nested exit, but also on
10809  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10810  * Failures During or After Loading Guest State").
10811  * This function should be called when the active VMCS is L1's (vmcs01).
10812  */
10813 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10814                                    struct vmcs12 *vmcs12)
10815 {
10816         struct kvm_segment seg;
10817         u32 entry_failure_code;
10818
10819         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10820                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10821         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10822                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10823         else
10824                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10825         vmx_set_efer(vcpu, vcpu->arch.efer);
10826
10827         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10828         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10829         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10830         /*
10831          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10832          * actually changed, because vmx_set_cr0 refers to efer set above.
10833          *
10834          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10835          * (KVM doesn't change it);
10836          */
10837         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10838         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10839
10840         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10841         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10842         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10843
10844         nested_ept_uninit_mmu_context(vcpu);
10845
10846         /*
10847          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10848          * couldn't have changed.
10849          */
10850         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10851                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10852
10853         if (!enable_ept)
10854                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10855
10856         if (enable_vpid) {
10857                 /*
10858                  * Trivially support vpid by letting L2s share their parent
10859                  * L1's vpid. TODO: move to a more elaborate solution, giving
10860                  * each L2 its own vpid and exposing the vpid feature to L1.
10861                  */
10862                 vmx_flush_tlb(vcpu);
10863         }
10864
10865
10866         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10867         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10868         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10869         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10870         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10871
10872         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10873         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10874                 vmcs_write64(GUEST_BNDCFGS, 0);
10875
10876         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10877                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10878                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10879         }
10880         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10881                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10882                         vmcs12->host_ia32_perf_global_ctrl);
10883
10884         /* Set L1 segment info according to Intel SDM
10885             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10886         seg = (struct kvm_segment) {
10887                 .base = 0,
10888                 .limit = 0xFFFFFFFF,
10889                 .selector = vmcs12->host_cs_selector,
10890                 .type = 11,
10891                 .present = 1,
10892                 .s = 1,
10893                 .g = 1
10894         };
10895         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10896                 seg.l = 1;
10897         else
10898                 seg.db = 1;
10899         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10900         seg = (struct kvm_segment) {
10901                 .base = 0,
10902                 .limit = 0xFFFFFFFF,
10903                 .type = 3,
10904                 .present = 1,
10905                 .s = 1,
10906                 .db = 1,
10907                 .g = 1
10908         };
10909         seg.selector = vmcs12->host_ds_selector;
10910         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10911         seg.selector = vmcs12->host_es_selector;
10912         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10913         seg.selector = vmcs12->host_ss_selector;
10914         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10915         seg.selector = vmcs12->host_fs_selector;
10916         seg.base = vmcs12->host_fs_base;
10917         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10918         seg.selector = vmcs12->host_gs_selector;
10919         seg.base = vmcs12->host_gs_base;
10920         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10921         seg = (struct kvm_segment) {
10922                 .base = vmcs12->host_tr_base,
10923                 .limit = 0x67,
10924                 .selector = vmcs12->host_tr_selector,
10925                 .type = 11,
10926                 .present = 1
10927         };
10928         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10929
10930         kvm_set_dr(vcpu, 7, 0x400);
10931         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10932
10933         if (cpu_has_vmx_msr_bitmap())
10934                 vmx_set_msr_bitmap(vcpu);
10935
10936         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10937                                 vmcs12->vm_exit_msr_load_count))
10938                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10939 }
10940
10941 /*
10942  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10943  * and modify vmcs12 to make it see what it would expect to see there if
10944  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10945  */
10946 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10947                               u32 exit_intr_info,
10948                               unsigned long exit_qualification)
10949 {
10950         struct vcpu_vmx *vmx = to_vmx(vcpu);
10951         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10952         u32 vm_inst_error = 0;
10953
10954         /* trying to cancel vmlaunch/vmresume is a bug */
10955         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10956
10957         leave_guest_mode(vcpu);
10958         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10959                        exit_qualification);
10960
10961         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10962                                  vmcs12->vm_exit_msr_store_count))
10963                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10964
10965         if (unlikely(vmx->fail))
10966                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10967
10968         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10969
10970         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10971             && nested_exit_intr_ack_set(vcpu)) {
10972                 int irq = kvm_cpu_get_interrupt(vcpu);
10973                 WARN_ON(irq < 0);
10974                 vmcs12->vm_exit_intr_info = irq |
10975                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10976         }
10977
10978         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10979                                        vmcs12->exit_qualification,
10980                                        vmcs12->idt_vectoring_info_field,
10981                                        vmcs12->vm_exit_intr_info,
10982                                        vmcs12->vm_exit_intr_error_code,
10983                                        KVM_ISA_VMX);
10984
10985         vm_entry_controls_reset_shadow(vmx);
10986         vm_exit_controls_reset_shadow(vmx);
10987         vmx_segment_cache_clear(vmx);
10988
10989         /* if no vmcs02 cache requested, remove the one we used */
10990         if (VMCS02_POOL_SIZE == 0)
10991                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10992
10993         load_vmcs12_host_state(vcpu, vmcs12);
10994
10995         /* Update any VMCS fields that might have changed while L2 ran */
10996         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10997         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10998         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10999         if (vmx->hv_deadline_tsc == -1)
11000                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11001                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11002         else
11003                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11004                               PIN_BASED_VMX_PREEMPTION_TIMER);
11005         if (kvm_has_tsc_control)
11006                 decache_tsc_multiplier(vmx);
11007
11008         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11009                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11010                 vmx_set_virtual_x2apic_mode(vcpu,
11011                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11012         } else if (!nested_cpu_has_ept(vmcs12) &&
11013                    nested_cpu_has2(vmcs12,
11014                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11015                 vmx_flush_tlb_ept_only(vcpu);
11016         }
11017
11018         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11019         vmx->host_rsp = 0;
11020
11021         /* Unpin physical memory we referred to in vmcs02 */
11022         if (vmx->nested.apic_access_page) {
11023                 nested_release_page(vmx->nested.apic_access_page);
11024                 vmx->nested.apic_access_page = NULL;
11025         }
11026         if (vmx->nested.virtual_apic_page) {
11027                 nested_release_page(vmx->nested.virtual_apic_page);
11028                 vmx->nested.virtual_apic_page = NULL;
11029         }
11030         if (vmx->nested.pi_desc_page) {
11031                 kunmap(vmx->nested.pi_desc_page);
11032                 nested_release_page(vmx->nested.pi_desc_page);
11033                 vmx->nested.pi_desc_page = NULL;
11034                 vmx->nested.pi_desc = NULL;
11035         }
11036
11037         /*
11038          * We are now running in L2, mmu_notifier will force to reload the
11039          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11040          */
11041         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11042
11043         /*
11044          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11045          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11046          * success or failure flag accordingly.
11047          */
11048         if (unlikely(vmx->fail)) {
11049                 vmx->fail = 0;
11050                 nested_vmx_failValid(vcpu, vm_inst_error);
11051         } else
11052                 nested_vmx_succeed(vcpu);
11053         if (enable_shadow_vmcs)
11054                 vmx->nested.sync_shadow_vmcs = true;
11055
11056         /* in case we halted in L2 */
11057         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11058 }
11059
11060 /*
11061  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11062  */
11063 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11064 {
11065         if (is_guest_mode(vcpu)) {
11066                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11067                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11068         }
11069         free_nested(to_vmx(vcpu));
11070 }
11071
11072 /*
11073  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11074  * 23.7 "VM-entry failures during or after loading guest state" (this also
11075  * lists the acceptable exit-reason and exit-qualification parameters).
11076  * It should only be called before L2 actually succeeded to run, and when
11077  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11078  */
11079 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11080                         struct vmcs12 *vmcs12,
11081                         u32 reason, unsigned long qualification)
11082 {
11083         load_vmcs12_host_state(vcpu, vmcs12);
11084         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11085         vmcs12->exit_qualification = qualification;
11086         nested_vmx_succeed(vcpu);
11087         if (enable_shadow_vmcs)
11088                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11089 }
11090
11091 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11092                                struct x86_instruction_info *info,
11093                                enum x86_intercept_stage stage)
11094 {
11095         return X86EMUL_CONTINUE;
11096 }
11097
11098 #ifdef CONFIG_X86_64
11099 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11100 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11101                                   u64 divisor, u64 *result)
11102 {
11103         u64 low = a << shift, high = a >> (64 - shift);
11104
11105         /* To avoid the overflow on divq */
11106         if (high >= divisor)
11107                 return 1;
11108
11109         /* Low hold the result, high hold rem which is discarded */
11110         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11111             "rm" (divisor), "0" (low), "1" (high));
11112         *result = low;
11113
11114         return 0;
11115 }
11116
11117 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11118 {
11119         struct vcpu_vmx *vmx = to_vmx(vcpu);
11120         u64 tscl = rdtsc();
11121         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11122         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11123
11124         /* Convert to host delta tsc if tsc scaling is enabled */
11125         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11126                         u64_shl_div_u64(delta_tsc,
11127                                 kvm_tsc_scaling_ratio_frac_bits,
11128                                 vcpu->arch.tsc_scaling_ratio,
11129                                 &delta_tsc))
11130                 return -ERANGE;
11131
11132         /*
11133          * If the delta tsc can't fit in the 32 bit after the multi shift,
11134          * we can't use the preemption timer.
11135          * It's possible that it fits on later vmentries, but checking
11136          * on every vmentry is costly so we just use an hrtimer.
11137          */
11138         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11139                 return -ERANGE;
11140
11141         vmx->hv_deadline_tsc = tscl + delta_tsc;
11142         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11143                         PIN_BASED_VMX_PREEMPTION_TIMER);
11144         return 0;
11145 }
11146
11147 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11148 {
11149         struct vcpu_vmx *vmx = to_vmx(vcpu);
11150         vmx->hv_deadline_tsc = -1;
11151         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11152                         PIN_BASED_VMX_PREEMPTION_TIMER);
11153 }
11154 #endif
11155
11156 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11157 {
11158         if (ple_gap)
11159                 shrink_ple_window(vcpu);
11160 }
11161
11162 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11163                                      struct kvm_memory_slot *slot)
11164 {
11165         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11166         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11167 }
11168
11169 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11170                                        struct kvm_memory_slot *slot)
11171 {
11172         kvm_mmu_slot_set_dirty(kvm, slot);
11173 }
11174
11175 static void vmx_flush_log_dirty(struct kvm *kvm)
11176 {
11177         kvm_flush_pml_buffers(kvm);
11178 }
11179
11180 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11181                                            struct kvm_memory_slot *memslot,
11182                                            gfn_t offset, unsigned long mask)
11183 {
11184         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11185 }
11186
11187 /*
11188  * This routine does the following things for vCPU which is going
11189  * to be blocked if VT-d PI is enabled.
11190  * - Store the vCPU to the wakeup list, so when interrupts happen
11191  *   we can find the right vCPU to wake up.
11192  * - Change the Posted-interrupt descriptor as below:
11193  *      'NDST' <-- vcpu->pre_pcpu
11194  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11195  * - If 'ON' is set during this process, which means at least one
11196  *   interrupt is posted for this vCPU, we cannot block it, in
11197  *   this case, return 1, otherwise, return 0.
11198  *
11199  */
11200 static int pi_pre_block(struct kvm_vcpu *vcpu)
11201 {
11202         unsigned long flags;
11203         unsigned int dest;
11204         struct pi_desc old, new;
11205         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11206
11207         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11208                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11209                 !kvm_vcpu_apicv_active(vcpu))
11210                 return 0;
11211
11212         vcpu->pre_pcpu = vcpu->cpu;
11213         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11214                           vcpu->pre_pcpu), flags);
11215         list_add_tail(&vcpu->blocked_vcpu_list,
11216                       &per_cpu(blocked_vcpu_on_cpu,
11217                       vcpu->pre_pcpu));
11218         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11219                                vcpu->pre_pcpu), flags);
11220
11221         do {
11222                 old.control = new.control = pi_desc->control;
11223
11224                 /*
11225                  * We should not block the vCPU if
11226                  * an interrupt is posted for it.
11227                  */
11228                 if (pi_test_on(pi_desc) == 1) {
11229                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11230                                           vcpu->pre_pcpu), flags);
11231                         list_del(&vcpu->blocked_vcpu_list);
11232                         spin_unlock_irqrestore(
11233                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11234                                         vcpu->pre_pcpu), flags);
11235                         vcpu->pre_pcpu = -1;
11236
11237                         return 1;
11238                 }
11239
11240                 WARN((pi_desc->sn == 1),
11241                      "Warning: SN field of posted-interrupts "
11242                      "is set before blocking\n");
11243
11244                 /*
11245                  * Since vCPU can be preempted during this process,
11246                  * vcpu->cpu could be different with pre_pcpu, we
11247                  * need to set pre_pcpu as the destination of wakeup
11248                  * notification event, then we can find the right vCPU
11249                  * to wakeup in wakeup handler if interrupts happen
11250                  * when the vCPU is in blocked state.
11251                  */
11252                 dest = cpu_physical_id(vcpu->pre_pcpu);
11253
11254                 if (x2apic_enabled())
11255                         new.ndst = dest;
11256                 else
11257                         new.ndst = (dest << 8) & 0xFF00;
11258
11259                 /* set 'NV' to 'wakeup vector' */
11260                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11261         } while (cmpxchg(&pi_desc->control, old.control,
11262                         new.control) != old.control);
11263
11264         return 0;
11265 }
11266
11267 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11268 {
11269         if (pi_pre_block(vcpu))
11270                 return 1;
11271
11272         if (kvm_lapic_hv_timer_in_use(vcpu))
11273                 kvm_lapic_switch_to_sw_timer(vcpu);
11274
11275         return 0;
11276 }
11277
11278 static void pi_post_block(struct kvm_vcpu *vcpu)
11279 {
11280         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11281         struct pi_desc old, new;
11282         unsigned int dest;
11283         unsigned long flags;
11284
11285         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11286                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11287                 !kvm_vcpu_apicv_active(vcpu))
11288                 return;
11289
11290         do {
11291                 old.control = new.control = pi_desc->control;
11292
11293                 dest = cpu_physical_id(vcpu->cpu);
11294
11295                 if (x2apic_enabled())
11296                         new.ndst = dest;
11297                 else
11298                         new.ndst = (dest << 8) & 0xFF00;
11299
11300                 /* Allow posting non-urgent interrupts */
11301                 new.sn = 0;
11302
11303                 /* set 'NV' to 'notification vector' */
11304                 new.nv = POSTED_INTR_VECTOR;
11305         } while (cmpxchg(&pi_desc->control, old.control,
11306                         new.control) != old.control);
11307
11308         if(vcpu->pre_pcpu != -1) {
11309                 spin_lock_irqsave(
11310                         &per_cpu(blocked_vcpu_on_cpu_lock,
11311                         vcpu->pre_pcpu), flags);
11312                 list_del(&vcpu->blocked_vcpu_list);
11313                 spin_unlock_irqrestore(
11314                         &per_cpu(blocked_vcpu_on_cpu_lock,
11315                         vcpu->pre_pcpu), flags);
11316                 vcpu->pre_pcpu = -1;
11317         }
11318 }
11319
11320 static void vmx_post_block(struct kvm_vcpu *vcpu)
11321 {
11322         if (kvm_x86_ops->set_hv_timer)
11323                 kvm_lapic_switch_to_hv_timer(vcpu);
11324
11325         pi_post_block(vcpu);
11326 }
11327
11328 /*
11329  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11330  *
11331  * @kvm: kvm
11332  * @host_irq: host irq of the interrupt
11333  * @guest_irq: gsi of the interrupt
11334  * @set: set or unset PI
11335  * returns 0 on success, < 0 on failure
11336  */
11337 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11338                               uint32_t guest_irq, bool set)
11339 {
11340         struct kvm_kernel_irq_routing_entry *e;
11341         struct kvm_irq_routing_table *irq_rt;
11342         struct kvm_lapic_irq irq;
11343         struct kvm_vcpu *vcpu;
11344         struct vcpu_data vcpu_info;
11345         int idx, ret = -EINVAL;
11346
11347         if (!kvm_arch_has_assigned_device(kvm) ||
11348                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11349                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11350                 return 0;
11351
11352         idx = srcu_read_lock(&kvm->irq_srcu);
11353         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11354         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11355
11356         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11357                 if (e->type != KVM_IRQ_ROUTING_MSI)
11358                         continue;
11359                 /*
11360                  * VT-d PI cannot support posting multicast/broadcast
11361                  * interrupts to a vCPU, we still use interrupt remapping
11362                  * for these kind of interrupts.
11363                  *
11364                  * For lowest-priority interrupts, we only support
11365                  * those with single CPU as the destination, e.g. user
11366                  * configures the interrupts via /proc/irq or uses
11367                  * irqbalance to make the interrupts single-CPU.
11368                  *
11369                  * We will support full lowest-priority interrupt later.
11370                  */
11371
11372                 kvm_set_msi_irq(kvm, e, &irq);
11373                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11374                         /*
11375                          * Make sure the IRTE is in remapped mode if
11376                          * we don't handle it in posted mode.
11377                          */
11378                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11379                         if (ret < 0) {
11380                                 printk(KERN_INFO
11381                                    "failed to back to remapped mode, irq: %u\n",
11382                                    host_irq);
11383                                 goto out;
11384                         }
11385
11386                         continue;
11387                 }
11388
11389                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11390                 vcpu_info.vector = irq.vector;
11391
11392                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11393                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11394
11395                 if (set)
11396                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11397                 else {
11398                         /* suppress notification event before unposting */
11399                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11400                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11401                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11402                 }
11403
11404                 if (ret < 0) {
11405                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11406                                         __func__);
11407                         goto out;
11408                 }
11409         }
11410
11411         ret = 0;
11412 out:
11413         srcu_read_unlock(&kvm->irq_srcu, idx);
11414         return ret;
11415 }
11416
11417 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11418 {
11419         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11420                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11421                         FEATURE_CONTROL_LMCE;
11422         else
11423                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11424                         ~FEATURE_CONTROL_LMCE;
11425 }
11426
11427 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11428         .cpu_has_kvm_support = cpu_has_kvm_support,
11429         .disabled_by_bios = vmx_disabled_by_bios,
11430         .hardware_setup = hardware_setup,
11431         .hardware_unsetup = hardware_unsetup,
11432         .check_processor_compatibility = vmx_check_processor_compat,
11433         .hardware_enable = hardware_enable,
11434         .hardware_disable = hardware_disable,
11435         .cpu_has_accelerated_tpr = report_flexpriority,
11436         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11437
11438         .vcpu_create = vmx_create_vcpu,
11439         .vcpu_free = vmx_free_vcpu,
11440         .vcpu_reset = vmx_vcpu_reset,
11441
11442         .prepare_guest_switch = vmx_save_host_state,
11443         .vcpu_load = vmx_vcpu_load,
11444         .vcpu_put = vmx_vcpu_put,
11445
11446         .update_bp_intercept = update_exception_bitmap,
11447         .get_msr = vmx_get_msr,
11448         .set_msr = vmx_set_msr,
11449         .get_segment_base = vmx_get_segment_base,
11450         .get_segment = vmx_get_segment,
11451         .set_segment = vmx_set_segment,
11452         .get_cpl = vmx_get_cpl,
11453         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11454         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11455         .decache_cr3 = vmx_decache_cr3,
11456         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11457         .set_cr0 = vmx_set_cr0,
11458         .set_cr3 = vmx_set_cr3,
11459         .set_cr4 = vmx_set_cr4,
11460         .set_efer = vmx_set_efer,
11461         .get_idt = vmx_get_idt,
11462         .set_idt = vmx_set_idt,
11463         .get_gdt = vmx_get_gdt,
11464         .set_gdt = vmx_set_gdt,
11465         .get_dr6 = vmx_get_dr6,
11466         .set_dr6 = vmx_set_dr6,
11467         .set_dr7 = vmx_set_dr7,
11468         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11469         .cache_reg = vmx_cache_reg,
11470         .get_rflags = vmx_get_rflags,
11471         .set_rflags = vmx_set_rflags,
11472
11473         .get_pkru = vmx_get_pkru,
11474
11475         .tlb_flush = vmx_flush_tlb,
11476
11477         .run = vmx_vcpu_run,
11478         .handle_exit = vmx_handle_exit,
11479         .skip_emulated_instruction = skip_emulated_instruction,
11480         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11481         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11482         .patch_hypercall = vmx_patch_hypercall,
11483         .set_irq = vmx_inject_irq,
11484         .set_nmi = vmx_inject_nmi,
11485         .queue_exception = vmx_queue_exception,
11486         .cancel_injection = vmx_cancel_injection,
11487         .interrupt_allowed = vmx_interrupt_allowed,
11488         .nmi_allowed = vmx_nmi_allowed,
11489         .get_nmi_mask = vmx_get_nmi_mask,
11490         .set_nmi_mask = vmx_set_nmi_mask,
11491         .enable_nmi_window = enable_nmi_window,
11492         .enable_irq_window = enable_irq_window,
11493         .update_cr8_intercept = update_cr8_intercept,
11494         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11495         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11496         .get_enable_apicv = vmx_get_enable_apicv,
11497         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11498         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11499         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11500         .hwapic_irr_update = vmx_hwapic_irr_update,
11501         .hwapic_isr_update = vmx_hwapic_isr_update,
11502         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11503         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11504
11505         .set_tss_addr = vmx_set_tss_addr,
11506         .get_tdp_level = get_ept_level,
11507         .get_mt_mask = vmx_get_mt_mask,
11508
11509         .get_exit_info = vmx_get_exit_info,
11510
11511         .get_lpage_level = vmx_get_lpage_level,
11512
11513         .cpuid_update = vmx_cpuid_update,
11514
11515         .rdtscp_supported = vmx_rdtscp_supported,
11516         .invpcid_supported = vmx_invpcid_supported,
11517
11518         .set_supported_cpuid = vmx_set_supported_cpuid,
11519
11520         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11521
11522         .write_tsc_offset = vmx_write_tsc_offset,
11523
11524         .set_tdp_cr3 = vmx_set_cr3,
11525
11526         .check_intercept = vmx_check_intercept,
11527         .handle_external_intr = vmx_handle_external_intr,
11528         .mpx_supported = vmx_mpx_supported,
11529         .xsaves_supported = vmx_xsaves_supported,
11530
11531         .check_nested_events = vmx_check_nested_events,
11532
11533         .sched_in = vmx_sched_in,
11534
11535         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11536         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11537         .flush_log_dirty = vmx_flush_log_dirty,
11538         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11539
11540         .pre_block = vmx_pre_block,
11541         .post_block = vmx_post_block,
11542
11543         .pmu_ops = &intel_pmu_ops,
11544
11545         .update_pi_irte = vmx_update_pi_irte,
11546
11547 #ifdef CONFIG_X86_64
11548         .set_hv_timer = vmx_set_hv_timer,
11549         .cancel_hv_timer = vmx_cancel_hv_timer,
11550 #endif
11551
11552         .setup_mce = vmx_setup_mce,
11553 };
11554
11555 static int __init vmx_init(void)
11556 {
11557         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11558                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11559         if (r)
11560                 return r;
11561
11562 #ifdef CONFIG_KEXEC_CORE
11563         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11564                            crash_vmclear_local_loaded_vmcss);
11565 #endif
11566
11567         return 0;
11568 }
11569
11570 static void __exit vmx_exit(void)
11571 {
11572 #ifdef CONFIG_KEXEC_CORE
11573         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11574         synchronize_rcu();
11575 #endif
11576
11577         kvm_exit();
11578 }
11579
11580 module_init(vmx_init)
11581 module_exit(vmx_exit)