2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
35 #include <asm/virtext.h>
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
45 static int __read_mostly bypass_guest_pf = 1;
46 module_param(bypass_guest_pf, bool, S_IRUGO);
48 static int __read_mostly enable_vpid = 1;
49 module_param_named(vpid, enable_vpid, bool, 0444);
51 static int __read_mostly flexpriority_enabled = 1;
52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
54 static int __read_mostly enable_ept = 1;
55 module_param_named(ept, enable_ept, bool, S_IRUGO);
57 static int __read_mostly enable_unrestricted_guest = 1;
58 module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
61 static int __read_mostly emulate_invalid_guest_state = 0;
62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66 #define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
70 #define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
72 #define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
90 #define KVM_VMX_DEFAULT_PLE_GAP 41
91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
93 module_param(ple_gap, int, S_IRUGO);
95 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
96 module_param(ple_window, int, S_IRUGO);
104 struct shared_msr_entry {
111 struct kvm_vcpu vcpu;
112 struct list_head local_vcpus_link;
113 unsigned long host_rsp;
116 u32 idt_vectoring_info;
117 struct shared_msr_entry *guest_msrs;
121 u64 msr_host_kernel_gs_base;
122 u64 msr_guest_kernel_gs_base;
127 u16 fs_sel, gs_sel, ldt_sel;
128 int gs_ldt_reload_needed;
129 int fs_reload_needed;
134 struct kvm_save_segment {
139 } tr, es, ds, fs, gs;
147 bool emulation_required;
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked;
152 s64 vnmi_blocked_time;
156 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
158 return container_of(vcpu, struct vcpu_vmx, vcpu);
161 static int init_rmode(struct kvm *kvm);
162 static u64 construct_eptp(unsigned long root_hpa);
164 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
165 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
166 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
168 static unsigned long *vmx_io_bitmap_a;
169 static unsigned long *vmx_io_bitmap_b;
170 static unsigned long *vmx_msr_bitmap_legacy;
171 static unsigned long *vmx_msr_bitmap_longmode;
173 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
174 static DEFINE_SPINLOCK(vmx_vpid_lock);
176 static struct vmcs_config {
180 u32 pin_based_exec_ctrl;
181 u32 cpu_based_exec_ctrl;
182 u32 cpu_based_2nd_exec_ctrl;
187 static struct vmx_capability {
192 #define VMX_SEGMENT_FIELD(seg) \
193 [VCPU_SREG_##seg] = { \
194 .selector = GUEST_##seg##_SELECTOR, \
195 .base = GUEST_##seg##_BASE, \
196 .limit = GUEST_##seg##_LIMIT, \
197 .ar_bytes = GUEST_##seg##_AR_BYTES, \
200 static struct kvm_vmx_segment_field {
205 } kvm_vmx_segment_fields[] = {
206 VMX_SEGMENT_FIELD(CS),
207 VMX_SEGMENT_FIELD(DS),
208 VMX_SEGMENT_FIELD(ES),
209 VMX_SEGMENT_FIELD(FS),
210 VMX_SEGMENT_FIELD(GS),
211 VMX_SEGMENT_FIELD(SS),
212 VMX_SEGMENT_FIELD(TR),
213 VMX_SEGMENT_FIELD(LDTR),
216 static u64 host_efer;
218 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
221 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
222 * away by decrementing the array size.
224 static const u32 vmx_msr_index[] = {
226 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
228 MSR_EFER, MSR_K6_STAR,
230 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
232 static inline int is_page_fault(u32 intr_info)
234 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
235 INTR_INFO_VALID_MASK)) ==
236 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
239 static inline int is_no_device(u32 intr_info)
241 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
242 INTR_INFO_VALID_MASK)) ==
243 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
246 static inline int is_invalid_opcode(u32 intr_info)
248 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
249 INTR_INFO_VALID_MASK)) ==
250 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
253 static inline int is_external_interrupt(u32 intr_info)
255 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
256 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
259 static inline int is_machine_check(u32 intr_info)
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
263 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
266 static inline int cpu_has_vmx_msr_bitmap(void)
268 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
271 static inline int cpu_has_vmx_tpr_shadow(void)
273 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
276 static inline int vm_need_tpr_shadow(struct kvm *kvm)
278 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
281 static inline int cpu_has_secondary_exec_ctrls(void)
283 return vmcs_config.cpu_based_exec_ctrl &
284 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
287 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
289 return vmcs_config.cpu_based_2nd_exec_ctrl &
290 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
293 static inline bool cpu_has_vmx_flexpriority(void)
295 return cpu_has_vmx_tpr_shadow() &&
296 cpu_has_vmx_virtualize_apic_accesses();
299 static inline bool cpu_has_vmx_ept_execute_only(void)
301 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
304 static inline bool cpu_has_vmx_eptp_uncacheable(void)
306 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
309 static inline bool cpu_has_vmx_eptp_writeback(void)
311 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
314 static inline bool cpu_has_vmx_ept_2m_page(void)
316 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
319 static inline int cpu_has_vmx_invept_individual_addr(void)
321 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
324 static inline int cpu_has_vmx_invept_context(void)
326 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
329 static inline int cpu_has_vmx_invept_global(void)
331 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
334 static inline int cpu_has_vmx_ept(void)
336 return vmcs_config.cpu_based_2nd_exec_ctrl &
337 SECONDARY_EXEC_ENABLE_EPT;
340 static inline int cpu_has_vmx_unrestricted_guest(void)
342 return vmcs_config.cpu_based_2nd_exec_ctrl &
343 SECONDARY_EXEC_UNRESTRICTED_GUEST;
346 static inline int cpu_has_vmx_ple(void)
348 return vmcs_config.cpu_based_2nd_exec_ctrl &
349 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
352 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
354 return flexpriority_enabled &&
355 (cpu_has_vmx_virtualize_apic_accesses()) &&
356 (irqchip_in_kernel(kvm));
359 static inline int cpu_has_vmx_vpid(void)
361 return vmcs_config.cpu_based_2nd_exec_ctrl &
362 SECONDARY_EXEC_ENABLE_VPID;
365 static inline int cpu_has_virtual_nmis(void)
367 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
370 static inline bool report_flexpriority(void)
372 return flexpriority_enabled;
375 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
379 for (i = 0; i < vmx->nmsrs; ++i)
380 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
385 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
391 } operand = { vpid, 0, gva };
393 asm volatile (__ex(ASM_VMX_INVVPID)
394 /* CF==1 or ZF==1 --> rc = -1 */
396 : : "a"(&operand), "c"(ext) : "cc", "memory");
399 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
403 } operand = {eptp, gpa};
405 asm volatile (__ex(ASM_VMX_INVEPT)
406 /* CF==1 or ZF==1 --> rc = -1 */
407 "; ja 1f ; ud2 ; 1:\n"
408 : : "a" (&operand), "c" (ext) : "cc", "memory");
411 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
415 i = __find_msr_index(vmx, msr);
417 return &vmx->guest_msrs[i];
421 static void vmcs_clear(struct vmcs *vmcs)
423 u64 phys_addr = __pa(vmcs);
426 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
427 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
430 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
434 static void __vcpu_clear(void *arg)
436 struct vcpu_vmx *vmx = arg;
437 int cpu = raw_smp_processor_id();
439 if (vmx->vcpu.cpu == cpu)
440 vmcs_clear(vmx->vmcs);
441 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
442 per_cpu(current_vmcs, cpu) = NULL;
443 rdtscll(vmx->vcpu.arch.host_tsc);
444 list_del(&vmx->local_vcpus_link);
449 static void vcpu_clear(struct vcpu_vmx *vmx)
451 if (vmx->vcpu.cpu == -1)
453 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
456 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
461 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
464 static inline void ept_sync_global(void)
466 if (cpu_has_vmx_invept_global())
467 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
470 static inline void ept_sync_context(u64 eptp)
473 if (cpu_has_vmx_invept_context())
474 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
480 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
483 if (cpu_has_vmx_invept_individual_addr())
484 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
487 ept_sync_context(eptp);
491 static unsigned long vmcs_readl(unsigned long field)
495 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
496 : "=a"(value) : "d"(field) : "cc");
500 static u16 vmcs_read16(unsigned long field)
502 return vmcs_readl(field);
505 static u32 vmcs_read32(unsigned long field)
507 return vmcs_readl(field);
510 static u64 vmcs_read64(unsigned long field)
513 return vmcs_readl(field);
515 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
519 static noinline void vmwrite_error(unsigned long field, unsigned long value)
521 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
522 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
526 static void vmcs_writel(unsigned long field, unsigned long value)
530 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
531 : "=q"(error) : "a"(value), "d"(field) : "cc");
533 vmwrite_error(field, value);
536 static void vmcs_write16(unsigned long field, u16 value)
538 vmcs_writel(field, value);
541 static void vmcs_write32(unsigned long field, u32 value)
543 vmcs_writel(field, value);
546 static void vmcs_write64(unsigned long field, u64 value)
548 vmcs_writel(field, value);
549 #ifndef CONFIG_X86_64
551 vmcs_writel(field+1, value >> 32);
555 static void vmcs_clear_bits(unsigned long field, u32 mask)
557 vmcs_writel(field, vmcs_readl(field) & ~mask);
560 static void vmcs_set_bits(unsigned long field, u32 mask)
562 vmcs_writel(field, vmcs_readl(field) | mask);
565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
570 if (!vcpu->fpu_active)
571 eb |= 1u << NM_VECTOR;
573 * Unconditionally intercept #DB so we can maintain dr6 without
574 * reading it every exit.
576 eb |= 1u << DB_VECTOR;
577 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
578 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
579 eb |= 1u << BP_VECTOR;
581 if (to_vmx(vcpu)->rmode.vm86_active)
584 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
585 vmcs_write32(EXCEPTION_BITMAP, eb);
588 static void reload_tss(void)
591 * VT restores TR but not its size. Useless.
593 struct descriptor_table gdt;
594 struct desc_struct *descs;
597 descs = (void *)gdt.base;
598 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
602 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
607 guest_efer = vmx->vcpu.arch.shadow_efer;
610 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
613 ignore_bits = EFER_NX | EFER_SCE;
615 ignore_bits |= EFER_LMA | EFER_LME;
616 /* SCE is meaningful only in long mode on Intel */
617 if (guest_efer & EFER_LMA)
618 ignore_bits &= ~(u64)EFER_SCE;
620 guest_efer &= ~ignore_bits;
621 guest_efer |= host_efer & ignore_bits;
622 vmx->guest_msrs[efer_offset].data = guest_efer;
623 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
627 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
629 struct vcpu_vmx *vmx = to_vmx(vcpu);
632 if (vmx->host_state.loaded)
635 vmx->host_state.loaded = 1;
637 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
638 * allow segment selectors with cpl > 0 or ti == 1.
640 vmx->host_state.ldt_sel = kvm_read_ldt();
641 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
642 vmx->host_state.fs_sel = kvm_read_fs();
643 if (!(vmx->host_state.fs_sel & 7)) {
644 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
645 vmx->host_state.fs_reload_needed = 0;
647 vmcs_write16(HOST_FS_SELECTOR, 0);
648 vmx->host_state.fs_reload_needed = 1;
650 vmx->host_state.gs_sel = kvm_read_gs();
651 if (!(vmx->host_state.gs_sel & 7))
652 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
654 vmcs_write16(HOST_GS_SELECTOR, 0);
655 vmx->host_state.gs_ldt_reload_needed = 1;
659 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
660 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
662 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
663 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
667 if (is_long_mode(&vmx->vcpu)) {
668 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
669 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
672 for (i = 0; i < vmx->save_nmsrs; ++i)
673 kvm_set_shared_msr(vmx->guest_msrs[i].index,
674 vmx->guest_msrs[i].data,
675 vmx->guest_msrs[i].mask);
678 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
682 if (!vmx->host_state.loaded)
685 ++vmx->vcpu.stat.host_state_reload;
686 vmx->host_state.loaded = 0;
687 if (vmx->host_state.fs_reload_needed)
688 kvm_load_fs(vmx->host_state.fs_sel);
689 if (vmx->host_state.gs_ldt_reload_needed) {
690 kvm_load_ldt(vmx->host_state.ldt_sel);
692 * If we have to reload gs, we must take care to
693 * preserve our gs base.
695 local_irq_save(flags);
696 kvm_load_gs(vmx->host_state.gs_sel);
698 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
700 local_irq_restore(flags);
704 if (is_long_mode(&vmx->vcpu)) {
705 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
706 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
711 static void vmx_load_host_state(struct vcpu_vmx *vmx)
714 __vmx_load_host_state(vmx);
719 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
720 * vcpu mutex is already taken.
722 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
724 struct vcpu_vmx *vmx = to_vmx(vcpu);
725 u64 phys_addr = __pa(vmx->vmcs);
726 u64 tsc_this, delta, new_offset;
728 if (vcpu->cpu != cpu) {
730 kvm_migrate_timers(vcpu);
731 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
733 list_add(&vmx->local_vcpus_link,
734 &per_cpu(vcpus_on_cpu, cpu));
738 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
741 per_cpu(current_vmcs, cpu) = vmx->vmcs;
742 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
743 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
746 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
747 vmx->vmcs, phys_addr);
750 if (vcpu->cpu != cpu) {
751 struct descriptor_table dt;
752 unsigned long sysenter_esp;
756 * Linux uses per-cpu TSS and GDT, so set these when switching
759 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
761 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
763 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
764 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
767 * Make sure the time stamp counter is monotonous.
770 if (tsc_this < vcpu->arch.host_tsc) {
771 delta = vcpu->arch.host_tsc - tsc_this;
772 new_offset = vmcs_read64(TSC_OFFSET) + delta;
773 vmcs_write64(TSC_OFFSET, new_offset);
778 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
780 __vmx_load_host_state(to_vmx(vcpu));
783 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
785 if (vcpu->fpu_active)
787 vcpu->fpu_active = 1;
788 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
789 if (vcpu->arch.cr0 & X86_CR0_TS)
790 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
791 update_exception_bitmap(vcpu);
794 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
796 if (!vcpu->fpu_active)
798 vcpu->fpu_active = 0;
799 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
800 update_exception_bitmap(vcpu);
803 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
805 unsigned long rflags;
807 rflags = vmcs_readl(GUEST_RFLAGS);
808 if (to_vmx(vcpu)->rmode.vm86_active)
809 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
813 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
815 if (to_vmx(vcpu)->rmode.vm86_active)
816 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
817 vmcs_writel(GUEST_RFLAGS, rflags);
820 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
822 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
825 if (interruptibility & GUEST_INTR_STATE_STI)
826 ret |= X86_SHADOW_INT_STI;
827 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
828 ret |= X86_SHADOW_INT_MOV_SS;
833 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
835 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
836 u32 interruptibility = interruptibility_old;
838 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
840 if (mask & X86_SHADOW_INT_MOV_SS)
841 interruptibility |= GUEST_INTR_STATE_MOV_SS;
842 if (mask & X86_SHADOW_INT_STI)
843 interruptibility |= GUEST_INTR_STATE_STI;
845 if ((interruptibility != interruptibility_old))
846 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
849 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
853 rip = kvm_rip_read(vcpu);
854 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
855 kvm_rip_write(vcpu, rip);
857 /* skipping an emulated instruction also counts */
858 vmx_set_interrupt_shadow(vcpu, 0);
861 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
862 bool has_error_code, u32 error_code)
864 struct vcpu_vmx *vmx = to_vmx(vcpu);
865 u32 intr_info = nr | INTR_INFO_VALID_MASK;
867 if (has_error_code) {
868 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
869 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
872 if (vmx->rmode.vm86_active) {
873 vmx->rmode.irq.pending = true;
874 vmx->rmode.irq.vector = nr;
875 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
876 if (kvm_exception_is_soft(nr))
877 vmx->rmode.irq.rip +=
878 vmx->vcpu.arch.event_exit_inst_len;
879 intr_info |= INTR_TYPE_SOFT_INTR;
880 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
881 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
882 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
886 if (kvm_exception_is_soft(nr)) {
887 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
888 vmx->vcpu.arch.event_exit_inst_len);
889 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
891 intr_info |= INTR_TYPE_HARD_EXCEPTION;
893 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
897 * Swap MSR entry in host/guest MSR entry array.
899 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
901 struct shared_msr_entry tmp;
903 tmp = vmx->guest_msrs[to];
904 vmx->guest_msrs[to] = vmx->guest_msrs[from];
905 vmx->guest_msrs[from] = tmp;
909 * Set up the vmcs to automatically save and restore system
910 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
911 * mode, as fiddling with msrs is very expensive.
913 static void setup_msrs(struct vcpu_vmx *vmx)
915 int save_nmsrs, index;
916 unsigned long *msr_bitmap;
918 vmx_load_host_state(vmx);
921 if (is_long_mode(&vmx->vcpu)) {
922 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
924 move_msr_up(vmx, index, save_nmsrs++);
925 index = __find_msr_index(vmx, MSR_LSTAR);
927 move_msr_up(vmx, index, save_nmsrs++);
928 index = __find_msr_index(vmx, MSR_CSTAR);
930 move_msr_up(vmx, index, save_nmsrs++);
932 * MSR_K6_STAR is only needed on long mode guests, and only
933 * if efer.sce is enabled.
935 index = __find_msr_index(vmx, MSR_K6_STAR);
936 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
937 move_msr_up(vmx, index, save_nmsrs++);
940 index = __find_msr_index(vmx, MSR_EFER);
941 if (index >= 0 && update_transition_efer(vmx, index))
942 move_msr_up(vmx, index, save_nmsrs++);
944 vmx->save_nmsrs = save_nmsrs;
946 if (cpu_has_vmx_msr_bitmap()) {
947 if (is_long_mode(&vmx->vcpu))
948 msr_bitmap = vmx_msr_bitmap_longmode;
950 msr_bitmap = vmx_msr_bitmap_legacy;
952 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
957 * reads and returns guest's timestamp counter "register"
958 * guest_tsc = host_tsc + tsc_offset -- 21.3
960 static u64 guest_read_tsc(void)
962 u64 host_tsc, tsc_offset;
965 tsc_offset = vmcs_read64(TSC_OFFSET);
966 return host_tsc + tsc_offset;
970 * writes 'guest_tsc' into guest's timestamp counter "register"
971 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
973 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
975 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
979 * Reads an msr value (of 'msr_index') into 'pdata'.
980 * Returns 0 on success, non-0 otherwise.
981 * Assumes vcpu_load() was already called.
983 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
986 struct shared_msr_entry *msr;
989 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
996 data = vmcs_readl(GUEST_FS_BASE);
999 data = vmcs_readl(GUEST_GS_BASE);
1001 case MSR_KERNEL_GS_BASE:
1002 vmx_load_host_state(to_vmx(vcpu));
1003 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1007 return kvm_get_msr_common(vcpu, msr_index, pdata);
1009 data = guest_read_tsc();
1011 case MSR_IA32_SYSENTER_CS:
1012 data = vmcs_read32(GUEST_SYSENTER_CS);
1014 case MSR_IA32_SYSENTER_EIP:
1015 data = vmcs_readl(GUEST_SYSENTER_EIP);
1017 case MSR_IA32_SYSENTER_ESP:
1018 data = vmcs_readl(GUEST_SYSENTER_ESP);
1021 vmx_load_host_state(to_vmx(vcpu));
1022 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1024 vmx_load_host_state(to_vmx(vcpu));
1028 return kvm_get_msr_common(vcpu, msr_index, pdata);
1036 * Writes msr value into into the appropriate "register".
1037 * Returns 0 on success, non-0 otherwise.
1038 * Assumes vcpu_load() was already called.
1040 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1042 struct vcpu_vmx *vmx = to_vmx(vcpu);
1043 struct shared_msr_entry *msr;
1047 switch (msr_index) {
1049 vmx_load_host_state(vmx);
1050 ret = kvm_set_msr_common(vcpu, msr_index, data);
1052 #ifdef CONFIG_X86_64
1054 vmcs_writel(GUEST_FS_BASE, data);
1057 vmcs_writel(GUEST_GS_BASE, data);
1059 case MSR_KERNEL_GS_BASE:
1060 vmx_load_host_state(vmx);
1061 vmx->msr_guest_kernel_gs_base = data;
1064 case MSR_IA32_SYSENTER_CS:
1065 vmcs_write32(GUEST_SYSENTER_CS, data);
1067 case MSR_IA32_SYSENTER_EIP:
1068 vmcs_writel(GUEST_SYSENTER_EIP, data);
1070 case MSR_IA32_SYSENTER_ESP:
1071 vmcs_writel(GUEST_SYSENTER_ESP, data);
1075 guest_write_tsc(data, host_tsc);
1077 case MSR_IA32_CR_PAT:
1078 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1079 vmcs_write64(GUEST_IA32_PAT, data);
1080 vcpu->arch.pat = data;
1083 /* Otherwise falls through to kvm_set_msr_common */
1085 msr = find_msr_entry(vmx, msr_index);
1087 vmx_load_host_state(vmx);
1091 ret = kvm_set_msr_common(vcpu, msr_index, data);
1097 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1099 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1102 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1105 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1107 case VCPU_EXREG_PDPTR:
1109 ept_save_pdptrs(vcpu);
1116 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1118 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1119 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1121 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1123 update_exception_bitmap(vcpu);
1126 static __init int cpu_has_kvm_support(void)
1128 return cpu_has_vmx();
1131 static __init int vmx_disabled_by_bios(void)
1135 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1136 return (msr & (FEATURE_CONTROL_LOCKED |
1137 FEATURE_CONTROL_VMXON_ENABLED))
1138 == FEATURE_CONTROL_LOCKED;
1139 /* locked but not enabled */
1142 static int hardware_enable(void *garbage)
1144 int cpu = raw_smp_processor_id();
1145 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1148 if (read_cr4() & X86_CR4_VMXE)
1151 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1152 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1153 if ((old & (FEATURE_CONTROL_LOCKED |
1154 FEATURE_CONTROL_VMXON_ENABLED))
1155 != (FEATURE_CONTROL_LOCKED |
1156 FEATURE_CONTROL_VMXON_ENABLED))
1157 /* enable and lock */
1158 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1159 FEATURE_CONTROL_LOCKED |
1160 FEATURE_CONTROL_VMXON_ENABLED);
1161 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1162 asm volatile (ASM_VMX_VMXON_RAX
1163 : : "a"(&phys_addr), "m"(phys_addr)
1171 static void vmclear_local_vcpus(void)
1173 int cpu = raw_smp_processor_id();
1174 struct vcpu_vmx *vmx, *n;
1176 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1182 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1185 static void kvm_cpu_vmxoff(void)
1187 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1188 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1191 static void hardware_disable(void *garbage)
1193 vmclear_local_vcpus();
1197 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1198 u32 msr, u32 *result)
1200 u32 vmx_msr_low, vmx_msr_high;
1201 u32 ctl = ctl_min | ctl_opt;
1203 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1205 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1206 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1208 /* Ensure minimum (required) set of control bits are supported. */
1216 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1218 u32 vmx_msr_low, vmx_msr_high;
1219 u32 min, opt, min2, opt2;
1220 u32 _pin_based_exec_control = 0;
1221 u32 _cpu_based_exec_control = 0;
1222 u32 _cpu_based_2nd_exec_control = 0;
1223 u32 _vmexit_control = 0;
1224 u32 _vmentry_control = 0;
1226 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1227 opt = PIN_BASED_VIRTUAL_NMIS;
1228 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1229 &_pin_based_exec_control) < 0)
1232 min = CPU_BASED_HLT_EXITING |
1233 #ifdef CONFIG_X86_64
1234 CPU_BASED_CR8_LOAD_EXITING |
1235 CPU_BASED_CR8_STORE_EXITING |
1237 CPU_BASED_CR3_LOAD_EXITING |
1238 CPU_BASED_CR3_STORE_EXITING |
1239 CPU_BASED_USE_IO_BITMAPS |
1240 CPU_BASED_MOV_DR_EXITING |
1241 CPU_BASED_USE_TSC_OFFSETING |
1242 CPU_BASED_MWAIT_EXITING |
1243 CPU_BASED_MONITOR_EXITING |
1244 CPU_BASED_INVLPG_EXITING;
1245 opt = CPU_BASED_TPR_SHADOW |
1246 CPU_BASED_USE_MSR_BITMAPS |
1247 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1248 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1249 &_cpu_based_exec_control) < 0)
1251 #ifdef CONFIG_X86_64
1252 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1253 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1254 ~CPU_BASED_CR8_STORE_EXITING;
1256 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1258 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1259 SECONDARY_EXEC_WBINVD_EXITING |
1260 SECONDARY_EXEC_ENABLE_VPID |
1261 SECONDARY_EXEC_ENABLE_EPT |
1262 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1263 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1264 if (adjust_vmx_controls(min2, opt2,
1265 MSR_IA32_VMX_PROCBASED_CTLS2,
1266 &_cpu_based_2nd_exec_control) < 0)
1269 #ifndef CONFIG_X86_64
1270 if (!(_cpu_based_2nd_exec_control &
1271 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1272 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1274 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1275 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1277 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1278 CPU_BASED_CR3_STORE_EXITING |
1279 CPU_BASED_INVLPG_EXITING);
1280 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1281 vmx_capability.ept, vmx_capability.vpid);
1285 #ifdef CONFIG_X86_64
1286 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1288 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1289 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1290 &_vmexit_control) < 0)
1294 opt = VM_ENTRY_LOAD_IA32_PAT;
1295 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1296 &_vmentry_control) < 0)
1299 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1301 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1302 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1305 #ifdef CONFIG_X86_64
1306 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1307 if (vmx_msr_high & (1u<<16))
1311 /* Require Write-Back (WB) memory type for VMCS accesses. */
1312 if (((vmx_msr_high >> 18) & 15) != 6)
1315 vmcs_conf->size = vmx_msr_high & 0x1fff;
1316 vmcs_conf->order = get_order(vmcs_config.size);
1317 vmcs_conf->revision_id = vmx_msr_low;
1319 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1320 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1321 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1322 vmcs_conf->vmexit_ctrl = _vmexit_control;
1323 vmcs_conf->vmentry_ctrl = _vmentry_control;
1328 static struct vmcs *alloc_vmcs_cpu(int cpu)
1330 int node = cpu_to_node(cpu);
1334 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1337 vmcs = page_address(pages);
1338 memset(vmcs, 0, vmcs_config.size);
1339 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1343 static struct vmcs *alloc_vmcs(void)
1345 return alloc_vmcs_cpu(raw_smp_processor_id());
1348 static void free_vmcs(struct vmcs *vmcs)
1350 free_pages((unsigned long)vmcs, vmcs_config.order);
1353 static void free_kvm_area(void)
1357 for_each_possible_cpu(cpu) {
1358 free_vmcs(per_cpu(vmxarea, cpu));
1359 per_cpu(vmxarea, cpu) = NULL;
1363 static __init int alloc_kvm_area(void)
1367 for_each_possible_cpu(cpu) {
1370 vmcs = alloc_vmcs_cpu(cpu);
1376 per_cpu(vmxarea, cpu) = vmcs;
1381 static __init int hardware_setup(void)
1383 if (setup_vmcs_config(&vmcs_config) < 0)
1386 if (boot_cpu_has(X86_FEATURE_NX))
1387 kvm_enable_efer_bits(EFER_NX);
1389 if (!cpu_has_vmx_vpid())
1392 if (!cpu_has_vmx_ept()) {
1394 enable_unrestricted_guest = 0;
1397 if (!cpu_has_vmx_unrestricted_guest())
1398 enable_unrestricted_guest = 0;
1400 if (!cpu_has_vmx_flexpriority())
1401 flexpriority_enabled = 0;
1403 if (!cpu_has_vmx_tpr_shadow())
1404 kvm_x86_ops->update_cr8_intercept = NULL;
1406 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1407 kvm_disable_largepages();
1409 if (!cpu_has_vmx_ple())
1412 return alloc_kvm_area();
1415 static __exit void hardware_unsetup(void)
1420 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1422 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1424 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1425 vmcs_write16(sf->selector, save->selector);
1426 vmcs_writel(sf->base, save->base);
1427 vmcs_write32(sf->limit, save->limit);
1428 vmcs_write32(sf->ar_bytes, save->ar);
1430 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1432 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1436 static void enter_pmode(struct kvm_vcpu *vcpu)
1438 unsigned long flags;
1439 struct vcpu_vmx *vmx = to_vmx(vcpu);
1441 vmx->emulation_required = 1;
1442 vmx->rmode.vm86_active = 0;
1444 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1445 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1446 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1448 flags = vmcs_readl(GUEST_RFLAGS);
1449 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1450 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1451 vmcs_writel(GUEST_RFLAGS, flags);
1453 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1454 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1456 update_exception_bitmap(vcpu);
1458 if (emulate_invalid_guest_state)
1461 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1462 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1463 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1464 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1466 vmcs_write16(GUEST_SS_SELECTOR, 0);
1467 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1469 vmcs_write16(GUEST_CS_SELECTOR,
1470 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1471 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1474 static gva_t rmode_tss_base(struct kvm *kvm)
1476 if (!kvm->arch.tss_addr) {
1477 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1478 kvm->memslots[0].npages - 3;
1479 return base_gfn << PAGE_SHIFT;
1481 return kvm->arch.tss_addr;
1484 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1486 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1488 save->selector = vmcs_read16(sf->selector);
1489 save->base = vmcs_readl(sf->base);
1490 save->limit = vmcs_read32(sf->limit);
1491 save->ar = vmcs_read32(sf->ar_bytes);
1492 vmcs_write16(sf->selector, save->base >> 4);
1493 vmcs_write32(sf->base, save->base & 0xfffff);
1494 vmcs_write32(sf->limit, 0xffff);
1495 vmcs_write32(sf->ar_bytes, 0xf3);
1498 static void enter_rmode(struct kvm_vcpu *vcpu)
1500 unsigned long flags;
1501 struct vcpu_vmx *vmx = to_vmx(vcpu);
1503 if (enable_unrestricted_guest)
1506 vmx->emulation_required = 1;
1507 vmx->rmode.vm86_active = 1;
1509 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1510 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1512 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1513 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1515 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1516 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1518 flags = vmcs_readl(GUEST_RFLAGS);
1519 vmx->rmode.save_iopl
1520 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1522 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1524 vmcs_writel(GUEST_RFLAGS, flags);
1525 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1526 update_exception_bitmap(vcpu);
1528 if (emulate_invalid_guest_state)
1529 goto continue_rmode;
1531 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1532 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1533 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1535 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1536 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1537 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1538 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1539 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1541 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1542 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1543 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1544 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1547 kvm_mmu_reset_context(vcpu);
1548 init_rmode(vcpu->kvm);
1551 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1553 struct vcpu_vmx *vmx = to_vmx(vcpu);
1554 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1560 * Force kernel_gs_base reloading before EFER changes, as control
1561 * of this msr depends on is_long_mode().
1563 vmx_load_host_state(to_vmx(vcpu));
1564 vcpu->arch.shadow_efer = efer;
1567 if (efer & EFER_LMA) {
1568 vmcs_write32(VM_ENTRY_CONTROLS,
1569 vmcs_read32(VM_ENTRY_CONTROLS) |
1570 VM_ENTRY_IA32E_MODE);
1573 vmcs_write32(VM_ENTRY_CONTROLS,
1574 vmcs_read32(VM_ENTRY_CONTROLS) &
1575 ~VM_ENTRY_IA32E_MODE);
1577 msr->data = efer & ~EFER_LME;
1582 #ifdef CONFIG_X86_64
1584 static void enter_lmode(struct kvm_vcpu *vcpu)
1588 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1589 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1590 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1592 vmcs_write32(GUEST_TR_AR_BYTES,
1593 (guest_tr_ar & ~AR_TYPE_MASK)
1594 | AR_TYPE_BUSY_64_TSS);
1596 vcpu->arch.shadow_efer |= EFER_LMA;
1597 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1600 static void exit_lmode(struct kvm_vcpu *vcpu)
1602 vcpu->arch.shadow_efer &= ~EFER_LMA;
1604 vmcs_write32(VM_ENTRY_CONTROLS,
1605 vmcs_read32(VM_ENTRY_CONTROLS)
1606 & ~VM_ENTRY_IA32E_MODE);
1611 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1613 vpid_sync_vcpu_all(to_vmx(vcpu));
1615 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1618 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1620 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1622 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1623 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1626 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1628 if (!test_bit(VCPU_EXREG_PDPTR,
1629 (unsigned long *)&vcpu->arch.regs_dirty))
1632 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1633 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1634 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1635 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1636 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1640 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1642 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1643 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1644 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1645 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1646 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1649 __set_bit(VCPU_EXREG_PDPTR,
1650 (unsigned long *)&vcpu->arch.regs_avail);
1651 __set_bit(VCPU_EXREG_PDPTR,
1652 (unsigned long *)&vcpu->arch.regs_dirty);
1655 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1657 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1659 struct kvm_vcpu *vcpu)
1661 if (!(cr0 & X86_CR0_PG)) {
1662 /* From paging/starting to nonpaging */
1663 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1664 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1665 (CPU_BASED_CR3_LOAD_EXITING |
1666 CPU_BASED_CR3_STORE_EXITING));
1667 vcpu->arch.cr0 = cr0;
1668 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1669 } else if (!is_paging(vcpu)) {
1670 /* From nonpaging to paging */
1671 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1672 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1673 ~(CPU_BASED_CR3_LOAD_EXITING |
1674 CPU_BASED_CR3_STORE_EXITING));
1675 vcpu->arch.cr0 = cr0;
1676 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1679 if (!(cr0 & X86_CR0_WP))
1680 *hw_cr0 &= ~X86_CR0_WP;
1683 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1684 struct kvm_vcpu *vcpu)
1686 if (!is_paging(vcpu)) {
1687 *hw_cr4 &= ~X86_CR4_PAE;
1688 *hw_cr4 |= X86_CR4_PSE;
1689 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1690 *hw_cr4 &= ~X86_CR4_PAE;
1693 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1695 struct vcpu_vmx *vmx = to_vmx(vcpu);
1696 unsigned long hw_cr0;
1698 if (enable_unrestricted_guest)
1699 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1700 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1702 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1704 vmx_fpu_deactivate(vcpu);
1706 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1709 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1712 #ifdef CONFIG_X86_64
1713 if (vcpu->arch.shadow_efer & EFER_LME) {
1714 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1716 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1722 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1724 vmcs_writel(CR0_READ_SHADOW, cr0);
1725 vmcs_writel(GUEST_CR0, hw_cr0);
1726 vcpu->arch.cr0 = cr0;
1728 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1729 vmx_fpu_activate(vcpu);
1732 static u64 construct_eptp(unsigned long root_hpa)
1736 /* TODO write the value reading from MSR */
1737 eptp = VMX_EPT_DEFAULT_MT |
1738 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1739 eptp |= (root_hpa & PAGE_MASK);
1744 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1746 unsigned long guest_cr3;
1751 eptp = construct_eptp(cr3);
1752 vmcs_write64(EPT_POINTER, eptp);
1753 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1754 vcpu->kvm->arch.ept_identity_map_addr;
1755 ept_load_pdptrs(vcpu);
1758 vmx_flush_tlb(vcpu);
1759 vmcs_writel(GUEST_CR3, guest_cr3);
1760 if (vcpu->arch.cr0 & X86_CR0_PE)
1761 vmx_fpu_deactivate(vcpu);
1764 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1766 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1767 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1769 vcpu->arch.cr4 = cr4;
1771 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1773 vmcs_writel(CR4_READ_SHADOW, cr4);
1774 vmcs_writel(GUEST_CR4, hw_cr4);
1777 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1779 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1781 return vmcs_readl(sf->base);
1784 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1785 struct kvm_segment *var, int seg)
1787 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1790 var->base = vmcs_readl(sf->base);
1791 var->limit = vmcs_read32(sf->limit);
1792 var->selector = vmcs_read16(sf->selector);
1793 ar = vmcs_read32(sf->ar_bytes);
1794 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1796 var->type = ar & 15;
1797 var->s = (ar >> 4) & 1;
1798 var->dpl = (ar >> 5) & 3;
1799 var->present = (ar >> 7) & 1;
1800 var->avl = (ar >> 12) & 1;
1801 var->l = (ar >> 13) & 1;
1802 var->db = (ar >> 14) & 1;
1803 var->g = (ar >> 15) & 1;
1804 var->unusable = (ar >> 16) & 1;
1807 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1809 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1812 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1815 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1818 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1825 ar = var->type & 15;
1826 ar |= (var->s & 1) << 4;
1827 ar |= (var->dpl & 3) << 5;
1828 ar |= (var->present & 1) << 7;
1829 ar |= (var->avl & 1) << 12;
1830 ar |= (var->l & 1) << 13;
1831 ar |= (var->db & 1) << 14;
1832 ar |= (var->g & 1) << 15;
1834 if (ar == 0) /* a 0 value means unusable */
1835 ar = AR_UNUSABLE_MASK;
1840 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1841 struct kvm_segment *var, int seg)
1843 struct vcpu_vmx *vmx = to_vmx(vcpu);
1844 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1847 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1848 vmx->rmode.tr.selector = var->selector;
1849 vmx->rmode.tr.base = var->base;
1850 vmx->rmode.tr.limit = var->limit;
1851 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1854 vmcs_writel(sf->base, var->base);
1855 vmcs_write32(sf->limit, var->limit);
1856 vmcs_write16(sf->selector, var->selector);
1857 if (vmx->rmode.vm86_active && var->s) {
1859 * Hack real-mode segments into vm86 compatibility.
1861 if (var->base == 0xffff0000 && var->selector == 0xf000)
1862 vmcs_writel(sf->base, 0xf0000);
1865 ar = vmx_segment_access_rights(var);
1868 * Fix the "Accessed" bit in AR field of segment registers for older
1870 * IA32 arch specifies that at the time of processor reset the
1871 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1872 * is setting it to 0 in the usedland code. This causes invalid guest
1873 * state vmexit when "unrestricted guest" mode is turned on.
1874 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1875 * tree. Newer qemu binaries with that qemu fix would not need this
1878 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1879 ar |= 0x1; /* Accessed */
1881 vmcs_write32(sf->ar_bytes, ar);
1884 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1886 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1888 *db = (ar >> 14) & 1;
1889 *l = (ar >> 13) & 1;
1892 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1894 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1895 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1898 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1900 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1901 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1904 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1906 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1907 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1910 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1912 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1913 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1916 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1918 struct kvm_segment var;
1921 vmx_get_segment(vcpu, &var, seg);
1922 ar = vmx_segment_access_rights(&var);
1924 if (var.base != (var.selector << 4))
1926 if (var.limit != 0xffff)
1934 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1936 struct kvm_segment cs;
1937 unsigned int cs_rpl;
1939 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1940 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1944 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1948 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1949 if (cs.dpl > cs_rpl)
1952 if (cs.dpl != cs_rpl)
1958 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1962 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1964 struct kvm_segment ss;
1965 unsigned int ss_rpl;
1967 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1968 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1972 if (ss.type != 3 && ss.type != 7)
1976 if (ss.dpl != ss_rpl) /* DPL != RPL */
1984 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1986 struct kvm_segment var;
1989 vmx_get_segment(vcpu, &var, seg);
1990 rpl = var.selector & SELECTOR_RPL_MASK;
1998 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1999 if (var.dpl < rpl) /* DPL < RPL */
2003 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2009 static bool tr_valid(struct kvm_vcpu *vcpu)
2011 struct kvm_segment tr;
2013 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2017 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2019 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2027 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2029 struct kvm_segment ldtr;
2031 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2035 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2045 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2047 struct kvm_segment cs, ss;
2049 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2050 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2052 return ((cs.selector & SELECTOR_RPL_MASK) ==
2053 (ss.selector & SELECTOR_RPL_MASK));
2057 * Check if guest state is valid. Returns true if valid, false if
2059 * We assume that registers are always usable
2061 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2063 /* real mode guest state checks */
2064 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2065 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2067 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2069 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2071 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2073 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2075 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2078 /* protected mode guest state checks */
2079 if (!cs_ss_rpl_check(vcpu))
2081 if (!code_segment_valid(vcpu))
2083 if (!stack_segment_valid(vcpu))
2085 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2087 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2089 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2091 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2093 if (!tr_valid(vcpu))
2095 if (!ldtr_valid(vcpu))
2099 * - Add checks on RIP
2100 * - Add checks on RFLAGS
2106 static int init_rmode_tss(struct kvm *kvm)
2108 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2113 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2116 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2117 r = kvm_write_guest_page(kvm, fn++, &data,
2118 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2121 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2124 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2128 r = kvm_write_guest_page(kvm, fn, &data,
2129 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2139 static int init_rmode_identity_map(struct kvm *kvm)
2142 pfn_t identity_map_pfn;
2147 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2148 printk(KERN_ERR "EPT: identity-mapping pagetable "
2149 "haven't been allocated!\n");
2152 if (likely(kvm->arch.ept_identity_pagetable_done))
2155 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2156 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2159 /* Set up identity-mapping pagetable for EPT in real mode */
2160 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2161 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2162 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2163 r = kvm_write_guest_page(kvm, identity_map_pfn,
2164 &tmp, i * sizeof(tmp), sizeof(tmp));
2168 kvm->arch.ept_identity_pagetable_done = true;
2174 static void seg_setup(int seg)
2176 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2179 vmcs_write16(sf->selector, 0);
2180 vmcs_writel(sf->base, 0);
2181 vmcs_write32(sf->limit, 0xffff);
2182 if (enable_unrestricted_guest) {
2184 if (seg == VCPU_SREG_CS)
2185 ar |= 0x08; /* code segment */
2189 vmcs_write32(sf->ar_bytes, ar);
2192 static int alloc_apic_access_page(struct kvm *kvm)
2194 struct kvm_userspace_memory_region kvm_userspace_mem;
2197 down_write(&kvm->slots_lock);
2198 if (kvm->arch.apic_access_page)
2200 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2201 kvm_userspace_mem.flags = 0;
2202 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2203 kvm_userspace_mem.memory_size = PAGE_SIZE;
2204 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2208 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2210 up_write(&kvm->slots_lock);
2214 static int alloc_identity_pagetable(struct kvm *kvm)
2216 struct kvm_userspace_memory_region kvm_userspace_mem;
2219 down_write(&kvm->slots_lock);
2220 if (kvm->arch.ept_identity_pagetable)
2222 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2223 kvm_userspace_mem.flags = 0;
2224 kvm_userspace_mem.guest_phys_addr =
2225 kvm->arch.ept_identity_map_addr;
2226 kvm_userspace_mem.memory_size = PAGE_SIZE;
2227 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2231 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2232 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2234 up_write(&kvm->slots_lock);
2238 static void allocate_vpid(struct vcpu_vmx *vmx)
2245 spin_lock(&vmx_vpid_lock);
2246 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2247 if (vpid < VMX_NR_VPIDS) {
2249 __set_bit(vpid, vmx_vpid_bitmap);
2251 spin_unlock(&vmx_vpid_lock);
2254 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2256 int f = sizeof(unsigned long);
2258 if (!cpu_has_vmx_msr_bitmap())
2262 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2263 * have the write-low and read-high bitmap offsets the wrong way round.
2264 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2266 if (msr <= 0x1fff) {
2267 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2268 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2269 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2271 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2272 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2276 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2279 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2280 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2284 * Sets up the vmcs for emulated real mode.
2286 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2288 u32 host_sysenter_cs, msr_low, msr_high;
2290 u64 host_pat, tsc_this, tsc_base;
2292 struct descriptor_table dt;
2294 unsigned long kvm_vmx_return;
2298 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2299 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2301 if (cpu_has_vmx_msr_bitmap())
2302 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2304 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2307 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2308 vmcs_config.pin_based_exec_ctrl);
2310 exec_control = vmcs_config.cpu_based_exec_ctrl;
2311 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2312 exec_control &= ~CPU_BASED_TPR_SHADOW;
2313 #ifdef CONFIG_X86_64
2314 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2315 CPU_BASED_CR8_LOAD_EXITING;
2319 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2320 CPU_BASED_CR3_LOAD_EXITING |
2321 CPU_BASED_INVLPG_EXITING;
2322 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2324 if (cpu_has_secondary_exec_ctrls()) {
2325 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2326 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2328 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2330 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2332 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2333 enable_unrestricted_guest = 0;
2335 if (!enable_unrestricted_guest)
2336 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2338 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2339 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2343 vmcs_write32(PLE_GAP, ple_gap);
2344 vmcs_write32(PLE_WINDOW, ple_window);
2347 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2348 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2349 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2351 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2352 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2353 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2355 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2356 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2357 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2358 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2359 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2360 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2361 #ifdef CONFIG_X86_64
2362 rdmsrl(MSR_FS_BASE, a);
2363 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2364 rdmsrl(MSR_GS_BASE, a);
2365 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2367 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2368 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2371 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2374 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2376 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2377 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2378 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2379 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2380 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2382 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2383 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2384 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2385 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2386 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2387 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2389 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2390 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2391 host_pat = msr_low | ((u64) msr_high << 32);
2392 vmcs_write64(HOST_IA32_PAT, host_pat);
2394 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2395 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2396 host_pat = msr_low | ((u64) msr_high << 32);
2397 /* Write the default value follow host pat */
2398 vmcs_write64(GUEST_IA32_PAT, host_pat);
2399 /* Keep arch.pat sync with GUEST_IA32_PAT */
2400 vmx->vcpu.arch.pat = host_pat;
2403 for (i = 0; i < NR_VMX_MSR; ++i) {
2404 u32 index = vmx_msr_index[i];
2405 u32 data_low, data_high;
2409 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2411 if (wrmsr_safe(index, data_low, data_high) < 0)
2413 data = data_low | ((u64)data_high << 32);
2414 vmx->guest_msrs[j].index = i;
2415 vmx->guest_msrs[j].data = 0;
2416 vmx->guest_msrs[j].mask = -1ull;
2420 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2422 /* 22.2.1, 20.8.1 */
2423 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2425 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2426 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2428 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2429 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2431 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2433 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2434 tsc_base = tsc_this;
2436 guest_write_tsc(0, tsc_base);
2441 static int init_rmode(struct kvm *kvm)
2443 if (!init_rmode_tss(kvm))
2445 if (!init_rmode_identity_map(kvm))
2450 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2452 struct vcpu_vmx *vmx = to_vmx(vcpu);
2456 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2457 down_read(&vcpu->kvm->slots_lock);
2458 if (!init_rmode(vmx->vcpu.kvm)) {
2463 vmx->rmode.vm86_active = 0;
2465 vmx->soft_vnmi_blocked = 0;
2467 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2468 kvm_set_cr8(&vmx->vcpu, 0);
2469 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2470 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2471 msr |= MSR_IA32_APICBASE_BSP;
2472 kvm_set_apic_base(&vmx->vcpu, msr);
2474 fx_init(&vmx->vcpu);
2476 seg_setup(VCPU_SREG_CS);
2478 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2479 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2481 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2482 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2483 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2485 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2486 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2489 seg_setup(VCPU_SREG_DS);
2490 seg_setup(VCPU_SREG_ES);
2491 seg_setup(VCPU_SREG_FS);
2492 seg_setup(VCPU_SREG_GS);
2493 seg_setup(VCPU_SREG_SS);
2495 vmcs_write16(GUEST_TR_SELECTOR, 0);
2496 vmcs_writel(GUEST_TR_BASE, 0);
2497 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2498 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2500 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2501 vmcs_writel(GUEST_LDTR_BASE, 0);
2502 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2503 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2505 vmcs_write32(GUEST_SYSENTER_CS, 0);
2506 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2507 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2509 vmcs_writel(GUEST_RFLAGS, 0x02);
2510 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2511 kvm_rip_write(vcpu, 0xfff0);
2513 kvm_rip_write(vcpu, 0);
2514 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2516 vmcs_writel(GUEST_DR7, 0x400);
2518 vmcs_writel(GUEST_GDTR_BASE, 0);
2519 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2521 vmcs_writel(GUEST_IDTR_BASE, 0);
2522 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2524 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2525 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2526 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2528 /* Special registers */
2529 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2533 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2535 if (cpu_has_vmx_tpr_shadow()) {
2536 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2537 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2538 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2539 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2540 vmcs_write32(TPR_THRESHOLD, 0);
2543 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2544 vmcs_write64(APIC_ACCESS_ADDR,
2545 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2548 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2550 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2551 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2552 vmx_set_cr4(&vmx->vcpu, 0);
2553 vmx_set_efer(&vmx->vcpu, 0);
2554 vmx_fpu_activate(&vmx->vcpu);
2555 update_exception_bitmap(&vmx->vcpu);
2557 vpid_sync_vcpu_all(vmx);
2561 /* HACK: Don't enable emulation on guest boot/reset */
2562 vmx->emulation_required = 0;
2565 up_read(&vcpu->kvm->slots_lock);
2569 static void enable_irq_window(struct kvm_vcpu *vcpu)
2571 u32 cpu_based_vm_exec_control;
2573 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2574 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2575 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2578 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2580 u32 cpu_based_vm_exec_control;
2582 if (!cpu_has_virtual_nmis()) {
2583 enable_irq_window(vcpu);
2587 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2588 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2589 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2592 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2594 struct vcpu_vmx *vmx = to_vmx(vcpu);
2596 int irq = vcpu->arch.interrupt.nr;
2598 trace_kvm_inj_virq(irq);
2600 ++vcpu->stat.irq_injections;
2601 if (vmx->rmode.vm86_active) {
2602 vmx->rmode.irq.pending = true;
2603 vmx->rmode.irq.vector = irq;
2604 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2605 if (vcpu->arch.interrupt.soft)
2606 vmx->rmode.irq.rip +=
2607 vmx->vcpu.arch.event_exit_inst_len;
2608 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2609 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2610 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2611 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2614 intr = irq | INTR_INFO_VALID_MASK;
2615 if (vcpu->arch.interrupt.soft) {
2616 intr |= INTR_TYPE_SOFT_INTR;
2617 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2618 vmx->vcpu.arch.event_exit_inst_len);
2620 intr |= INTR_TYPE_EXT_INTR;
2621 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2624 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2626 struct vcpu_vmx *vmx = to_vmx(vcpu);
2628 if (!cpu_has_virtual_nmis()) {
2630 * Tracking the NMI-blocked state in software is built upon
2631 * finding the next open IRQ window. This, in turn, depends on
2632 * well-behaving guests: They have to keep IRQs disabled at
2633 * least as long as the NMI handler runs. Otherwise we may
2634 * cause NMI nesting, maybe breaking the guest. But as this is
2635 * highly unlikely, we can live with the residual risk.
2637 vmx->soft_vnmi_blocked = 1;
2638 vmx->vnmi_blocked_time = 0;
2641 ++vcpu->stat.nmi_injections;
2642 if (vmx->rmode.vm86_active) {
2643 vmx->rmode.irq.pending = true;
2644 vmx->rmode.irq.vector = NMI_VECTOR;
2645 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2646 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2647 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2648 INTR_INFO_VALID_MASK);
2649 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2650 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2653 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2654 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2657 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2659 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2662 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2663 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2664 GUEST_INTR_STATE_NMI));
2667 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2669 if (!cpu_has_virtual_nmis())
2670 return to_vmx(vcpu)->soft_vnmi_blocked;
2672 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2673 GUEST_INTR_STATE_NMI);
2676 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2678 struct vcpu_vmx *vmx = to_vmx(vcpu);
2680 if (!cpu_has_virtual_nmis()) {
2681 if (vmx->soft_vnmi_blocked != masked) {
2682 vmx->soft_vnmi_blocked = masked;
2683 vmx->vnmi_blocked_time = 0;
2687 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2688 GUEST_INTR_STATE_NMI);
2690 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2691 GUEST_INTR_STATE_NMI);
2695 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2697 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2698 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2699 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2702 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2705 struct kvm_userspace_memory_region tss_mem = {
2706 .slot = TSS_PRIVATE_MEMSLOT,
2707 .guest_phys_addr = addr,
2708 .memory_size = PAGE_SIZE * 3,
2712 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2715 kvm->arch.tss_addr = addr;
2719 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2720 int vec, u32 err_code)
2723 * Instruction with address size override prefix opcode 0x67
2724 * Cause the #SS fault with 0 error code in VM86 mode.
2726 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2727 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2730 * Forward all other exceptions that are valid in real mode.
2731 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2732 * the required debugging infrastructure rework.
2736 if (vcpu->guest_debug &
2737 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2739 kvm_queue_exception(vcpu, vec);
2742 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2753 kvm_queue_exception(vcpu, vec);
2760 * Trigger machine check on the host. We assume all the MSRs are already set up
2761 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2762 * We pass a fake environment to the machine check handler because we want
2763 * the guest to be always treated like user space, no matter what context
2764 * it used internally.
2766 static void kvm_machine_check(void)
2768 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2769 struct pt_regs regs = {
2770 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2771 .flags = X86_EFLAGS_IF,
2774 do_machine_check(®s, 0);
2778 static int handle_machine_check(struct kvm_vcpu *vcpu)
2780 /* already handled by vcpu_run */
2784 static int handle_exception(struct kvm_vcpu *vcpu)
2786 struct vcpu_vmx *vmx = to_vmx(vcpu);
2787 struct kvm_run *kvm_run = vcpu->run;
2788 u32 intr_info, ex_no, error_code;
2789 unsigned long cr2, rip, dr6;
2791 enum emulation_result er;
2793 vect_info = vmx->idt_vectoring_info;
2794 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2796 if (is_machine_check(intr_info))
2797 return handle_machine_check(vcpu);
2799 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2800 !is_page_fault(intr_info)) {
2801 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2802 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2803 vcpu->run->internal.ndata = 2;
2804 vcpu->run->internal.data[0] = vect_info;
2805 vcpu->run->internal.data[1] = intr_info;
2809 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2810 return 1; /* already handled by vmx_vcpu_run() */
2812 if (is_no_device(intr_info)) {
2813 vmx_fpu_activate(vcpu);
2817 if (is_invalid_opcode(intr_info)) {
2818 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2819 if (er != EMULATE_DONE)
2820 kvm_queue_exception(vcpu, UD_VECTOR);
2825 rip = kvm_rip_read(vcpu);
2826 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2827 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2828 if (is_page_fault(intr_info)) {
2829 /* EPT won't cause page fault directly */
2832 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2833 trace_kvm_page_fault(cr2, error_code);
2835 if (kvm_event_needs_reinjection(vcpu))
2836 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2837 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2840 if (vmx->rmode.vm86_active &&
2841 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2843 if (vcpu->arch.halt_request) {
2844 vcpu->arch.halt_request = 0;
2845 return kvm_emulate_halt(vcpu);
2850 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2853 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2854 if (!(vcpu->guest_debug &
2855 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2856 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2857 kvm_queue_exception(vcpu, DB_VECTOR);
2860 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2861 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2864 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2865 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2866 kvm_run->debug.arch.exception = ex_no;
2869 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2870 kvm_run->ex.exception = ex_no;
2871 kvm_run->ex.error_code = error_code;
2877 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2879 ++vcpu->stat.irq_exits;
2883 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2885 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2889 static int handle_io(struct kvm_vcpu *vcpu)
2891 unsigned long exit_qualification;
2892 int size, in, string;
2895 ++vcpu->stat.io_exits;
2896 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2897 string = (exit_qualification & 16) != 0;
2900 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2905 size = (exit_qualification & 7) + 1;
2906 in = (exit_qualification & 8) != 0;
2907 port = exit_qualification >> 16;
2909 skip_emulated_instruction(vcpu);
2910 return kvm_emulate_pio(vcpu, in, size, port);
2914 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2917 * Patch in the VMCALL instruction:
2919 hypercall[0] = 0x0f;
2920 hypercall[1] = 0x01;
2921 hypercall[2] = 0xc1;
2924 static int handle_cr(struct kvm_vcpu *vcpu)
2926 unsigned long exit_qualification, val;
2930 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2931 cr = exit_qualification & 15;
2932 reg = (exit_qualification >> 8) & 15;
2933 switch ((exit_qualification >> 4) & 3) {
2934 case 0: /* mov to cr */
2935 val = kvm_register_read(vcpu, reg);
2936 trace_kvm_cr_write(cr, val);
2939 kvm_set_cr0(vcpu, val);
2940 skip_emulated_instruction(vcpu);
2943 kvm_set_cr3(vcpu, val);
2944 skip_emulated_instruction(vcpu);
2947 kvm_set_cr4(vcpu, val);
2948 skip_emulated_instruction(vcpu);
2951 u8 cr8_prev = kvm_get_cr8(vcpu);
2952 u8 cr8 = kvm_register_read(vcpu, reg);
2953 kvm_set_cr8(vcpu, cr8);
2954 skip_emulated_instruction(vcpu);
2955 if (irqchip_in_kernel(vcpu->kvm))
2957 if (cr8_prev <= cr8)
2959 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2965 vmx_fpu_deactivate(vcpu);
2966 vcpu->arch.cr0 &= ~X86_CR0_TS;
2967 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2968 vmx_fpu_activate(vcpu);
2969 skip_emulated_instruction(vcpu);
2971 case 1: /*mov from cr*/
2974 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2975 trace_kvm_cr_read(cr, vcpu->arch.cr3);
2976 skip_emulated_instruction(vcpu);
2979 val = kvm_get_cr8(vcpu);
2980 kvm_register_write(vcpu, reg, val);
2981 trace_kvm_cr_read(cr, val);
2982 skip_emulated_instruction(vcpu);
2987 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2989 skip_emulated_instruction(vcpu);
2994 vcpu->run->exit_reason = 0;
2995 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2996 (int)(exit_qualification >> 4) & 3, cr);
3000 static int handle_dr(struct kvm_vcpu *vcpu)
3002 unsigned long exit_qualification;
3006 if (!kvm_require_cpl(vcpu, 0))
3008 dr = vmcs_readl(GUEST_DR7);
3011 * As the vm-exit takes precedence over the debug trap, we
3012 * need to emulate the latter, either for the host or the
3013 * guest debugging itself.
3015 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3016 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3017 vcpu->run->debug.arch.dr7 = dr;
3018 vcpu->run->debug.arch.pc =
3019 vmcs_readl(GUEST_CS_BASE) +
3020 vmcs_readl(GUEST_RIP);
3021 vcpu->run->debug.arch.exception = DB_VECTOR;
3022 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3025 vcpu->arch.dr7 &= ~DR7_GD;
3026 vcpu->arch.dr6 |= DR6_BD;
3027 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3028 kvm_queue_exception(vcpu, DB_VECTOR);
3033 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3034 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3035 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3036 if (exit_qualification & TYPE_MOV_FROM_DR) {
3039 val = vcpu->arch.db[dr];
3042 val = vcpu->arch.dr6;
3045 val = vcpu->arch.dr7;
3050 kvm_register_write(vcpu, reg, val);
3052 val = vcpu->arch.regs[reg];
3055 vcpu->arch.db[dr] = val;
3056 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3057 vcpu->arch.eff_db[dr] = val;
3060 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
3061 kvm_queue_exception(vcpu, UD_VECTOR);
3064 if (val & 0xffffffff00000000ULL) {
3065 kvm_queue_exception(vcpu, GP_VECTOR);
3068 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3071 if (val & 0xffffffff00000000ULL) {
3072 kvm_queue_exception(vcpu, GP_VECTOR);
3075 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3076 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3077 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3078 vcpu->arch.switch_db_regs =
3079 (val & DR7_BP_EN_MASK);
3084 skip_emulated_instruction(vcpu);
3088 static int handle_cpuid(struct kvm_vcpu *vcpu)
3090 kvm_emulate_cpuid(vcpu);
3094 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3096 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3099 if (vmx_get_msr(vcpu, ecx, &data)) {
3100 kvm_inject_gp(vcpu, 0);
3104 trace_kvm_msr_read(ecx, data);
3106 /* FIXME: handling of bits 32:63 of rax, rdx */
3107 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3108 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3109 skip_emulated_instruction(vcpu);
3113 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3115 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3116 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3117 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3119 trace_kvm_msr_write(ecx, data);
3121 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3122 kvm_inject_gp(vcpu, 0);
3126 skip_emulated_instruction(vcpu);
3130 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3135 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3137 u32 cpu_based_vm_exec_control;
3139 /* clear pending irq */
3140 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3141 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3142 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3144 ++vcpu->stat.irq_window_exits;
3147 * If the user space waits to inject interrupts, exit as soon as
3150 if (!irqchip_in_kernel(vcpu->kvm) &&
3151 vcpu->run->request_interrupt_window &&
3152 !kvm_cpu_has_interrupt(vcpu)) {
3153 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3159 static int handle_halt(struct kvm_vcpu *vcpu)
3161 skip_emulated_instruction(vcpu);
3162 return kvm_emulate_halt(vcpu);
3165 static int handle_vmcall(struct kvm_vcpu *vcpu)
3167 skip_emulated_instruction(vcpu);
3168 kvm_emulate_hypercall(vcpu);
3172 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3174 kvm_queue_exception(vcpu, UD_VECTOR);
3178 static int handle_invlpg(struct kvm_vcpu *vcpu)
3180 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3182 kvm_mmu_invlpg(vcpu, exit_qualification);
3183 skip_emulated_instruction(vcpu);
3187 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3189 skip_emulated_instruction(vcpu);
3190 /* TODO: Add support for VT-d/pass-through device */
3194 static int handle_apic_access(struct kvm_vcpu *vcpu)
3196 unsigned long exit_qualification;
3197 enum emulation_result er;
3198 unsigned long offset;
3200 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3201 offset = exit_qualification & 0xffful;
3203 er = emulate_instruction(vcpu, 0, 0, 0);
3205 if (er != EMULATE_DONE) {
3207 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3214 static int handle_task_switch(struct kvm_vcpu *vcpu)
3216 struct vcpu_vmx *vmx = to_vmx(vcpu);
3217 unsigned long exit_qualification;
3219 int reason, type, idt_v;
3221 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3222 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3224 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3226 reason = (u32)exit_qualification >> 30;
3227 if (reason == TASK_SWITCH_GATE && idt_v) {
3229 case INTR_TYPE_NMI_INTR:
3230 vcpu->arch.nmi_injected = false;
3231 if (cpu_has_virtual_nmis())
3232 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3233 GUEST_INTR_STATE_NMI);
3235 case INTR_TYPE_EXT_INTR:
3236 case INTR_TYPE_SOFT_INTR:
3237 kvm_clear_interrupt_queue(vcpu);
3239 case INTR_TYPE_HARD_EXCEPTION:
3240 case INTR_TYPE_SOFT_EXCEPTION:
3241 kvm_clear_exception_queue(vcpu);
3247 tss_selector = exit_qualification;
3249 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3250 type != INTR_TYPE_EXT_INTR &&
3251 type != INTR_TYPE_NMI_INTR))
3252 skip_emulated_instruction(vcpu);
3254 if (!kvm_task_switch(vcpu, tss_selector, reason))
3257 /* clear all local breakpoint enable flags */
3258 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3261 * TODO: What about debug traps on tss switch?
3262 * Are we supposed to inject them and update dr6?
3268 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3270 unsigned long exit_qualification;
3274 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3276 if (exit_qualification & (1 << 6)) {
3277 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3281 gla_validity = (exit_qualification >> 7) & 0x3;
3282 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3283 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3284 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3285 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3286 vmcs_readl(GUEST_LINEAR_ADDRESS));
3287 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3288 (long unsigned int)exit_qualification);
3289 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3290 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3294 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3295 trace_kvm_page_fault(gpa, exit_qualification);
3296 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3299 static u64 ept_rsvd_mask(u64 spte, int level)
3304 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3305 mask |= (1ULL << i);
3308 /* bits 7:3 reserved */
3310 else if (level == 2) {
3311 if (spte & (1ULL << 7))
3312 /* 2MB ref, bits 20:12 reserved */
3315 /* bits 6:3 reserved */
3322 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3325 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3327 /* 010b (write-only) */
3328 WARN_ON((spte & 0x7) == 0x2);
3330 /* 110b (write/execute) */
3331 WARN_ON((spte & 0x7) == 0x6);
3333 /* 100b (execute-only) and value not supported by logical processor */
3334 if (!cpu_has_vmx_ept_execute_only())
3335 WARN_ON((spte & 0x7) == 0x4);
3339 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3341 if (rsvd_bits != 0) {
3342 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3343 __func__, rsvd_bits);
3347 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3348 u64 ept_mem_type = (spte & 0x38) >> 3;
3350 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3351 ept_mem_type == 7) {
3352 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3353 __func__, ept_mem_type);
3360 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3366 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3368 printk(KERN_ERR "EPT: Misconfiguration.\n");
3369 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3371 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3373 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3374 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3376 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3377 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3382 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3384 u32 cpu_based_vm_exec_control;
3386 /* clear pending NMI */
3387 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3388 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3389 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3390 ++vcpu->stat.nmi_window_exits;
3395 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3397 struct vcpu_vmx *vmx = to_vmx(vcpu);
3398 enum emulation_result err = EMULATE_DONE;
3401 while (!guest_state_valid(vcpu)) {
3402 err = emulate_instruction(vcpu, 0, 0, 0);
3404 if (err == EMULATE_DO_MMIO) {
3409 if (err != EMULATE_DONE) {
3410 kvm_report_emulation_failure(vcpu, "emulation failure");
3411 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3412 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3413 vcpu->run->internal.ndata = 0;
3418 if (signal_pending(current))
3424 vmx->emulation_required = 0;
3430 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3431 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3433 static int handle_pause(struct kvm_vcpu *vcpu)
3435 skip_emulated_instruction(vcpu);
3436 kvm_vcpu_on_spin(vcpu);
3441 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3443 kvm_queue_exception(vcpu, UD_VECTOR);
3448 * The exit handlers return 1 if the exit was handled fully and guest execution
3449 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3450 * to be done to userspace and return 0.
3452 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3453 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3454 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3455 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3456 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3457 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3458 [EXIT_REASON_CR_ACCESS] = handle_cr,
3459 [EXIT_REASON_DR_ACCESS] = handle_dr,
3460 [EXIT_REASON_CPUID] = handle_cpuid,
3461 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3462 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3463 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3464 [EXIT_REASON_HLT] = handle_halt,
3465 [EXIT_REASON_INVLPG] = handle_invlpg,
3466 [EXIT_REASON_VMCALL] = handle_vmcall,
3467 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3468 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3469 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3470 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3471 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3472 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3473 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3474 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3475 [EXIT_REASON_VMON] = handle_vmx_insn,
3476 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3477 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3478 [EXIT_REASON_WBINVD] = handle_wbinvd,
3479 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3480 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3481 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3482 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3483 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3484 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3485 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3488 static const int kvm_vmx_max_exit_handlers =
3489 ARRAY_SIZE(kvm_vmx_exit_handlers);
3492 * The guest has exited. See if we can fix it or if we need userspace
3495 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3497 struct vcpu_vmx *vmx = to_vmx(vcpu);
3498 u32 exit_reason = vmx->exit_reason;
3499 u32 vectoring_info = vmx->idt_vectoring_info;
3501 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3503 /* If guest state is invalid, start emulating */
3504 if (vmx->emulation_required && emulate_invalid_guest_state)
3505 return handle_invalid_guest_state(vcpu);
3507 /* Access CR3 don't cause VMExit in paging mode, so we need
3508 * to sync with guest real CR3. */
3509 if (enable_ept && is_paging(vcpu))
3510 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3512 if (unlikely(vmx->fail)) {
3513 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3514 vcpu->run->fail_entry.hardware_entry_failure_reason
3515 = vmcs_read32(VM_INSTRUCTION_ERROR);
3519 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3520 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3521 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3522 exit_reason != EXIT_REASON_TASK_SWITCH))
3523 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3524 "(0x%x) and exit reason is 0x%x\n",
3525 __func__, vectoring_info, exit_reason);
3527 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3528 if (vmx_interrupt_allowed(vcpu)) {
3529 vmx->soft_vnmi_blocked = 0;
3530 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3531 vcpu->arch.nmi_pending) {
3533 * This CPU don't support us in finding the end of an
3534 * NMI-blocked window if the guest runs with IRQs
3535 * disabled. So we pull the trigger after 1 s of
3536 * futile waiting, but inform the user about this.
3538 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3539 "state on VCPU %d after 1 s timeout\n",
3540 __func__, vcpu->vcpu_id);
3541 vmx->soft_vnmi_blocked = 0;
3545 if (exit_reason < kvm_vmx_max_exit_handlers
3546 && kvm_vmx_exit_handlers[exit_reason])
3547 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3549 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3550 vcpu->run->hw.hardware_exit_reason = exit_reason;
3555 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3557 if (irr == -1 || tpr < irr) {
3558 vmcs_write32(TPR_THRESHOLD, 0);
3562 vmcs_write32(TPR_THRESHOLD, irr);
3565 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3568 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3572 bool idtv_info_valid;
3574 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3576 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3578 /* Handle machine checks before interrupts are enabled */
3579 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3580 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3581 && is_machine_check(exit_intr_info)))
3582 kvm_machine_check();
3584 /* We need to handle NMIs before interrupts are enabled */
3585 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3586 (exit_intr_info & INTR_INFO_VALID_MASK))
3589 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3591 if (cpu_has_virtual_nmis()) {
3592 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3593 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3595 * SDM 3: 27.7.1.2 (September 2008)
3596 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3597 * a guest IRET fault.
3598 * SDM 3: 23.2.2 (September 2008)
3599 * Bit 12 is undefined in any of the following cases:
3600 * If the VM exit sets the valid bit in the IDT-vectoring
3601 * information field.
3602 * If the VM exit is due to a double fault.
3604 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3605 vector != DF_VECTOR && !idtv_info_valid)
3606 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3607 GUEST_INTR_STATE_NMI);
3608 } else if (unlikely(vmx->soft_vnmi_blocked))
3609 vmx->vnmi_blocked_time +=
3610 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3612 vmx->vcpu.arch.nmi_injected = false;
3613 kvm_clear_exception_queue(&vmx->vcpu);
3614 kvm_clear_interrupt_queue(&vmx->vcpu);
3616 if (!idtv_info_valid)
3619 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3620 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3623 case INTR_TYPE_NMI_INTR:
3624 vmx->vcpu.arch.nmi_injected = true;
3626 * SDM 3: 27.7.1.2 (September 2008)
3627 * Clear bit "block by NMI" before VM entry if a NMI
3630 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3631 GUEST_INTR_STATE_NMI);
3633 case INTR_TYPE_SOFT_EXCEPTION:
3634 vmx->vcpu.arch.event_exit_inst_len =
3635 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3637 case INTR_TYPE_HARD_EXCEPTION:
3638 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3639 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3640 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3642 kvm_queue_exception(&vmx->vcpu, vector);
3644 case INTR_TYPE_SOFT_INTR:
3645 vmx->vcpu.arch.event_exit_inst_len =
3646 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3648 case INTR_TYPE_EXT_INTR:
3649 kvm_queue_interrupt(&vmx->vcpu, vector,
3650 type == INTR_TYPE_SOFT_INTR);
3658 * Failure to inject an interrupt should give us the information
3659 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3660 * when fetching the interrupt redirection bitmap in the real-mode
3661 * tss, this doesn't happen. So we do it ourselves.
3663 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3665 vmx->rmode.irq.pending = 0;
3666 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3668 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3669 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3670 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3671 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3674 vmx->idt_vectoring_info =
3675 VECTORING_INFO_VALID_MASK
3676 | INTR_TYPE_EXT_INTR
3677 | vmx->rmode.irq.vector;
3680 #ifdef CONFIG_X86_64
3688 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3690 struct vcpu_vmx *vmx = to_vmx(vcpu);
3692 /* Record the guest's net vcpu time for enforced NMI injections. */
3693 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3694 vmx->entry_time = ktime_get();
3696 /* Don't enter VMX if guest state is invalid, let the exit handler
3697 start emulation until we arrive back to a valid state */
3698 if (vmx->emulation_required && emulate_invalid_guest_state)
3701 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3702 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3703 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3704 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3706 /* When single-stepping over STI and MOV SS, we must clear the
3707 * corresponding interruptibility bits in the guest state. Otherwise
3708 * vmentry fails as it then expects bit 14 (BS) in pending debug
3709 * exceptions being set, but that's not correct for the guest debugging
3711 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3712 vmx_set_interrupt_shadow(vcpu, 0);
3715 * Loading guest fpu may have cleared host cr0.ts
3717 vmcs_writel(HOST_CR0, read_cr0());
3719 if (vcpu->arch.switch_db_regs)
3720 set_debugreg(vcpu->arch.dr6, 6);
3723 /* Store host registers */
3724 "push %%"R"dx; push %%"R"bp;"
3726 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3728 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3729 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3731 /* Reload cr2 if changed */
3732 "mov %c[cr2](%0), %%"R"ax \n\t"
3733 "mov %%cr2, %%"R"dx \n\t"
3734 "cmp %%"R"ax, %%"R"dx \n\t"
3736 "mov %%"R"ax, %%cr2 \n\t"
3738 /* Check if vmlaunch of vmresume is needed */
3739 "cmpl $0, %c[launched](%0) \n\t"
3740 /* Load guest registers. Don't clobber flags. */
3741 "mov %c[rax](%0), %%"R"ax \n\t"
3742 "mov %c[rbx](%0), %%"R"bx \n\t"
3743 "mov %c[rdx](%0), %%"R"dx \n\t"
3744 "mov %c[rsi](%0), %%"R"si \n\t"
3745 "mov %c[rdi](%0), %%"R"di \n\t"
3746 "mov %c[rbp](%0), %%"R"bp \n\t"
3747 #ifdef CONFIG_X86_64
3748 "mov %c[r8](%0), %%r8 \n\t"
3749 "mov %c[r9](%0), %%r9 \n\t"
3750 "mov %c[r10](%0), %%r10 \n\t"
3751 "mov %c[r11](%0), %%r11 \n\t"
3752 "mov %c[r12](%0), %%r12 \n\t"
3753 "mov %c[r13](%0), %%r13 \n\t"
3754 "mov %c[r14](%0), %%r14 \n\t"
3755 "mov %c[r15](%0), %%r15 \n\t"
3757 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3759 /* Enter guest mode */
3760 "jne .Llaunched \n\t"
3761 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3762 "jmp .Lkvm_vmx_return \n\t"
3763 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3764 ".Lkvm_vmx_return: "
3765 /* Save guest registers, load host registers, keep flags */
3766 "xchg %0, (%%"R"sp) \n\t"
3767 "mov %%"R"ax, %c[rax](%0) \n\t"
3768 "mov %%"R"bx, %c[rbx](%0) \n\t"
3769 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3770 "mov %%"R"dx, %c[rdx](%0) \n\t"
3771 "mov %%"R"si, %c[rsi](%0) \n\t"
3772 "mov %%"R"di, %c[rdi](%0) \n\t"
3773 "mov %%"R"bp, %c[rbp](%0) \n\t"
3774 #ifdef CONFIG_X86_64
3775 "mov %%r8, %c[r8](%0) \n\t"
3776 "mov %%r9, %c[r9](%0) \n\t"
3777 "mov %%r10, %c[r10](%0) \n\t"
3778 "mov %%r11, %c[r11](%0) \n\t"
3779 "mov %%r12, %c[r12](%0) \n\t"
3780 "mov %%r13, %c[r13](%0) \n\t"
3781 "mov %%r14, %c[r14](%0) \n\t"
3782 "mov %%r15, %c[r15](%0) \n\t"
3784 "mov %%cr2, %%"R"ax \n\t"
3785 "mov %%"R"ax, %c[cr2](%0) \n\t"
3787 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3788 "setbe %c[fail](%0) \n\t"
3789 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3790 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3791 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3792 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3793 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3794 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3795 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3796 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3797 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3798 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3799 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3800 #ifdef CONFIG_X86_64
3801 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3802 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3803 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3804 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3805 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3806 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3807 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3808 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3810 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3812 , R"bx", R"di", R"si"
3813 #ifdef CONFIG_X86_64
3814 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3818 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3819 | (1 << VCPU_EXREG_PDPTR));
3820 vcpu->arch.regs_dirty = 0;
3822 if (vcpu->arch.switch_db_regs)
3823 get_debugreg(vcpu->arch.dr6, 6);
3825 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3826 if (vmx->rmode.irq.pending)
3827 fixup_rmode_irq(vmx);
3829 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3832 vmx_complete_interrupts(vmx);
3838 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3840 struct vcpu_vmx *vmx = to_vmx(vcpu);
3844 free_vmcs(vmx->vmcs);
3849 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3851 struct vcpu_vmx *vmx = to_vmx(vcpu);
3853 spin_lock(&vmx_vpid_lock);
3855 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3856 spin_unlock(&vmx_vpid_lock);
3857 vmx_free_vmcs(vcpu);
3858 kfree(vmx->guest_msrs);
3859 kvm_vcpu_uninit(vcpu);
3860 kmem_cache_free(kvm_vcpu_cache, vmx);
3863 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3866 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3870 return ERR_PTR(-ENOMEM);
3874 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3878 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3879 if (!vmx->guest_msrs) {
3884 vmx->vmcs = alloc_vmcs();
3888 vmcs_clear(vmx->vmcs);
3891 vmx_vcpu_load(&vmx->vcpu, cpu);
3892 err = vmx_vcpu_setup(vmx);
3893 vmx_vcpu_put(&vmx->vcpu);
3897 if (vm_need_virtualize_apic_accesses(kvm))
3898 if (alloc_apic_access_page(kvm) != 0)
3902 if (!kvm->arch.ept_identity_map_addr)
3903 kvm->arch.ept_identity_map_addr =
3904 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3905 if (alloc_identity_pagetable(kvm) != 0)
3912 free_vmcs(vmx->vmcs);
3914 kfree(vmx->guest_msrs);
3916 kvm_vcpu_uninit(&vmx->vcpu);
3918 kmem_cache_free(kvm_vcpu_cache, vmx);
3919 return ERR_PTR(err);
3922 static void __init vmx_check_processor_compat(void *rtn)
3924 struct vmcs_config vmcs_conf;
3927 if (setup_vmcs_config(&vmcs_conf) < 0)
3929 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3930 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3931 smp_processor_id());
3936 static int get_ept_level(void)
3938 return VMX_EPT_DEFAULT_GAW + 1;
3941 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3945 /* For VT-d and EPT combination
3946 * 1. MMIO: always map as UC
3948 * a. VT-d without snooping control feature: can't guarantee the
3949 * result, try to trust guest.
3950 * b. VT-d with snooping control feature: snooping control feature of
3951 * VT-d engine can guarantee the cache correctness. Just set it
3952 * to WB to keep consistent with host. So the same as item 3.
3953 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3954 * consistent with host MTRR
3957 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3958 else if (vcpu->kvm->arch.iommu_domain &&
3959 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3960 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3961 VMX_EPT_MT_EPTE_SHIFT;
3963 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3969 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3970 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3971 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3972 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3973 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3974 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3975 { EXIT_REASON_CR_ACCESS, "cr_access" },
3976 { EXIT_REASON_DR_ACCESS, "dr_access" },
3977 { EXIT_REASON_CPUID, "cpuid" },
3978 { EXIT_REASON_MSR_READ, "rdmsr" },
3979 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3980 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3981 { EXIT_REASON_HLT, "halt" },
3982 { EXIT_REASON_INVLPG, "invlpg" },
3983 { EXIT_REASON_VMCALL, "hypercall" },
3984 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3985 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3986 { EXIT_REASON_WBINVD, "wbinvd" },
3987 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3988 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3992 static bool vmx_gb_page_enable(void)
3997 static struct kvm_x86_ops vmx_x86_ops = {
3998 .cpu_has_kvm_support = cpu_has_kvm_support,
3999 .disabled_by_bios = vmx_disabled_by_bios,
4000 .hardware_setup = hardware_setup,
4001 .hardware_unsetup = hardware_unsetup,
4002 .check_processor_compatibility = vmx_check_processor_compat,
4003 .hardware_enable = hardware_enable,
4004 .hardware_disable = hardware_disable,
4005 .cpu_has_accelerated_tpr = report_flexpriority,
4007 .vcpu_create = vmx_create_vcpu,
4008 .vcpu_free = vmx_free_vcpu,
4009 .vcpu_reset = vmx_vcpu_reset,
4011 .prepare_guest_switch = vmx_save_host_state,
4012 .vcpu_load = vmx_vcpu_load,
4013 .vcpu_put = vmx_vcpu_put,
4015 .set_guest_debug = set_guest_debug,
4016 .get_msr = vmx_get_msr,
4017 .set_msr = vmx_set_msr,
4018 .get_segment_base = vmx_get_segment_base,
4019 .get_segment = vmx_get_segment,
4020 .set_segment = vmx_set_segment,
4021 .get_cpl = vmx_get_cpl,
4022 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4023 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4024 .set_cr0 = vmx_set_cr0,
4025 .set_cr3 = vmx_set_cr3,
4026 .set_cr4 = vmx_set_cr4,
4027 .set_efer = vmx_set_efer,
4028 .get_idt = vmx_get_idt,
4029 .set_idt = vmx_set_idt,
4030 .get_gdt = vmx_get_gdt,
4031 .set_gdt = vmx_set_gdt,
4032 .cache_reg = vmx_cache_reg,
4033 .get_rflags = vmx_get_rflags,
4034 .set_rflags = vmx_set_rflags,
4036 .tlb_flush = vmx_flush_tlb,
4038 .run = vmx_vcpu_run,
4039 .handle_exit = vmx_handle_exit,
4040 .skip_emulated_instruction = skip_emulated_instruction,
4041 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4042 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4043 .patch_hypercall = vmx_patch_hypercall,
4044 .set_irq = vmx_inject_irq,
4045 .set_nmi = vmx_inject_nmi,
4046 .queue_exception = vmx_queue_exception,
4047 .interrupt_allowed = vmx_interrupt_allowed,
4048 .nmi_allowed = vmx_nmi_allowed,
4049 .get_nmi_mask = vmx_get_nmi_mask,
4050 .set_nmi_mask = vmx_set_nmi_mask,
4051 .enable_nmi_window = enable_nmi_window,
4052 .enable_irq_window = enable_irq_window,
4053 .update_cr8_intercept = update_cr8_intercept,
4055 .set_tss_addr = vmx_set_tss_addr,
4056 .get_tdp_level = get_ept_level,
4057 .get_mt_mask = vmx_get_mt_mask,
4059 .exit_reasons_str = vmx_exit_reasons_str,
4060 .gb_page_enable = vmx_gb_page_enable,
4063 static int __init vmx_init(void)
4067 rdmsrl_safe(MSR_EFER, &host_efer);
4069 for (i = 0; i < NR_VMX_MSR; ++i)
4070 kvm_define_shared_msr(i, vmx_msr_index[i]);
4072 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4073 if (!vmx_io_bitmap_a)
4076 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4077 if (!vmx_io_bitmap_b) {
4082 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4083 if (!vmx_msr_bitmap_legacy) {
4088 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4089 if (!vmx_msr_bitmap_longmode) {
4095 * Allow direct access to the PC debug port (it is often used for I/O
4096 * delays, but the vmexits simply slow things down).
4098 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4099 clear_bit(0x80, vmx_io_bitmap_a);
4101 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4103 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4104 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4106 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4108 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4112 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4113 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4114 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4115 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4116 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4117 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4120 bypass_guest_pf = 0;
4121 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4122 VMX_EPT_WRITABLE_MASK);
4123 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4124 VMX_EPT_EXECUTABLE_MASK);
4129 if (bypass_guest_pf)
4130 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4135 free_page((unsigned long)vmx_msr_bitmap_longmode);
4137 free_page((unsigned long)vmx_msr_bitmap_legacy);
4139 free_page((unsigned long)vmx_io_bitmap_b);
4141 free_page((unsigned long)vmx_io_bitmap_a);
4145 static void __exit vmx_exit(void)
4147 free_page((unsigned long)vmx_msr_bitmap_legacy);
4148 free_page((unsigned long)vmx_msr_bitmap_longmode);
4149 free_page((unsigned long)vmx_io_bitmap_b);
4150 free_page((unsigned long)vmx_io_bitmap_a);
4155 module_init(vmx_init)
4156 module_exit(vmx_exit)