arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly fasteoi = 1;
  88 module_param(fasteoi, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_apicv = 1;
  91 module_param(enable_apicv, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_shadow_vmcs = 1;
  94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  95 /*
  96  * If nested=1, nested virtualization is supported, i.e., guests may use
  97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  98  * use VMX instructions.
  99  */
 100 static bool __read_mostly nested = 0;
 101 module_param(nested, bool, S_IRUGO);
 102
 103 static u64 __read_mostly host_xss;
 104
 105 static bool __read_mostly enable_pml = 1;
 106 module_param_named(pml, enable_pml, bool, S_IRUGO);
 107
 108 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 109
 110 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 111 static int __read_mostly cpu_preemption_timer_multi;
 112 static bool __read_mostly enable_preemption_timer = 1;
 113 #ifdef CONFIG_X86_64
 114 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 115 #endif
 116
 117 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 118 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 119 #define KVM_VM_CR0_ALWAYS_ON                                            \
 120         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 121 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 122         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 123          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 124
 125 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 126 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 127
 128 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 129
 130 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 131
 132 /*
 133  * Hyper-V requires all of these, so mark them as supported even though
 134  * they are just treated the same as all-context.
 135  */
 136 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 137         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 138         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 139         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 140         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 141
 142 /*
 143  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 144  * ple_gap:    upper bound on the amount of time between two successive
 145  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 146  *             According to test, this time is usually smaller than 128 cycles.
 147  * ple_window: upper bound on the amount of time a guest is allowed to execute
 148  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 149  *             less than 2^12 cycles
 150  * Time is measured based on a counter that runs at the same rate as the TSC,
 151  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 152  */
 153 #define KVM_VMX_DEFAULT_PLE_GAP           128
 154 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 155 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 158                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 159
 160 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 161 module_param(ple_gap, int, S_IRUGO);
 162
 163 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 164 module_param(ple_window, int, S_IRUGO);
 165
 166 /* Default doubles per-vcpu window every exit. */
 167 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 168 module_param(ple_window_grow, int, S_IRUGO);
 169
 170 /* Default resets per-vcpu window every exit to ple_window. */
 171 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 172 module_param(ple_window_shrink, int, S_IRUGO);
 173
 174 /* Default is to compute the maximum so we can never overflow. */
 175 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 176 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 177 module_param(ple_window_max, int, S_IRUGO);
 178
 179 extern const ulong vmx_return;
 180
 181 #define NR_AUTOLOAD_MSRS 8
 182 #define VMCS02_POOL_SIZE 1
 183
 184 struct vmcs {
 185         u32 revision_id;
 186         u32 abort;
 187         char data[0];
 188 };
 189
 190 /*
 191  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 192  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 193  * loaded on this CPU (so we can clear them if the CPU goes down).
 194  */
 195 struct loaded_vmcs {
 196         struct vmcs *vmcs;
 197         struct vmcs *shadow_vmcs;
 198         int cpu;
 199         int launched;
 200         struct list_head loaded_vmcss_on_cpu_link;
 201 };
 202
 203 struct shared_msr_entry {
 204         unsigned index;
 205         u64 data;
 206         u64 mask;
 207 };
 208
 209 /*
 210  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 211  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 212  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 213  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 214  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 215  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 216  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 217  * underlying hardware which will be used to run L2.
 218  * This structure is packed to ensure that its layout is identical across
 219  * machines (necessary for live migration).
 220  * If there are changes in this struct, VMCS12_REVISION must be changed.
 221  */
 222 typedef u64 natural_width;
 223 struct __packed vmcs12 {
 224         /* According to the Intel spec, a VMCS region must start with the
 225          * following two fields. Then follow implementation-specific data.
 226          */
 227         u32 revision_id;
 228         u32 abort;
 229
 230         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 231         u32 padding[7]; /* room for future expansion */
 232
 233         u64 io_bitmap_a;
 234         u64 io_bitmap_b;
 235         u64 msr_bitmap;
 236         u64 vm_exit_msr_store_addr;
 237         u64 vm_exit_msr_load_addr;
 238         u64 vm_entry_msr_load_addr;
 239         u64 tsc_offset;
 240         u64 virtual_apic_page_addr;
 241         u64 apic_access_addr;
 242         u64 posted_intr_desc_addr;
 243         u64 ept_pointer;
 244         u64 eoi_exit_bitmap0;
 245         u64 eoi_exit_bitmap1;
 246         u64 eoi_exit_bitmap2;
 247         u64 eoi_exit_bitmap3;
 248         u64 xss_exit_bitmap;
 249         u64 guest_physical_address;
 250         u64 vmcs_link_pointer;
 251         u64 guest_ia32_debugctl;
 252         u64 guest_ia32_pat;
 253         u64 guest_ia32_efer;
 254         u64 guest_ia32_perf_global_ctrl;
 255         u64 guest_pdptr0;
 256         u64 guest_pdptr1;
 257         u64 guest_pdptr2;
 258         u64 guest_pdptr3;
 259         u64 guest_bndcfgs;
 260         u64 host_ia32_pat;
 261         u64 host_ia32_efer;
 262         u64 host_ia32_perf_global_ctrl;
 263         u64 padding64[8]; /* room for future expansion */
 264         /*
 265          * To allow migration of L1 (complete with its L2 guests) between
 266          * machines of different natural widths (32 or 64 bit), we cannot have
 267          * unsigned long fields with no explict size. We use u64 (aliased
 268          * natural_width) instead. Luckily, x86 is little-endian.
 269          */
 270         natural_width cr0_guest_host_mask;
 271         natural_width cr4_guest_host_mask;
 272         natural_width cr0_read_shadow;
 273         natural_width cr4_read_shadow;
 274         natural_width cr3_target_value0;
 275         natural_width cr3_target_value1;
 276         natural_width cr3_target_value2;
 277         natural_width cr3_target_value3;
 278         natural_width exit_qualification;
 279         natural_width guest_linear_address;
 280         natural_width guest_cr0;
 281         natural_width guest_cr3;
 282         natural_width guest_cr4;
 283         natural_width guest_es_base;
 284         natural_width guest_cs_base;
 285         natural_width guest_ss_base;
 286         natural_width guest_ds_base;
 287         natural_width guest_fs_base;
 288         natural_width guest_gs_base;
 289         natural_width guest_ldtr_base;
 290         natural_width guest_tr_base;
 291         natural_width guest_gdtr_base;
 292         natural_width guest_idtr_base;
 293         natural_width guest_dr7;
 294         natural_width guest_rsp;
 295         natural_width guest_rip;
 296         natural_width guest_rflags;
 297         natural_width guest_pending_dbg_exceptions;
 298         natural_width guest_sysenter_esp;
 299         natural_width guest_sysenter_eip;
 300         natural_width host_cr0;
 301         natural_width host_cr3;
 302         natural_width host_cr4;
 303         natural_width host_fs_base;
 304         natural_width host_gs_base;
 305         natural_width host_tr_base;
 306         natural_width host_gdtr_base;
 307         natural_width host_idtr_base;
 308         natural_width host_ia32_sysenter_esp;
 309         natural_width host_ia32_sysenter_eip;
 310         natural_width host_rsp;
 311         natural_width host_rip;
 312         natural_width paddingl[8]; /* room for future expansion */
 313         u32 pin_based_vm_exec_control;
 314         u32 cpu_based_vm_exec_control;
 315         u32 exception_bitmap;
 316         u32 page_fault_error_code_mask;
 317         u32 page_fault_error_code_match;
 318         u32 cr3_target_count;
 319         u32 vm_exit_controls;
 320         u32 vm_exit_msr_store_count;
 321         u32 vm_exit_msr_load_count;
 322         u32 vm_entry_controls;
 323         u32 vm_entry_msr_load_count;
 324         u32 vm_entry_intr_info_field;
 325         u32 vm_entry_exception_error_code;
 326         u32 vm_entry_instruction_len;
 327         u32 tpr_threshold;
 328         u32 secondary_vm_exec_control;
 329         u32 vm_instruction_error;
 330         u32 vm_exit_reason;
 331         u32 vm_exit_intr_info;
 332         u32 vm_exit_intr_error_code;
 333         u32 idt_vectoring_info_field;
 334         u32 idt_vectoring_error_code;
 335         u32 vm_exit_instruction_len;
 336         u32 vmx_instruction_info;
 337         u32 guest_es_limit;
 338         u32 guest_cs_limit;
 339         u32 guest_ss_limit;
 340         u32 guest_ds_limit;
 341         u32 guest_fs_limit;
 342         u32 guest_gs_limit;
 343         u32 guest_ldtr_limit;
 344         u32 guest_tr_limit;
 345         u32 guest_gdtr_limit;
 346         u32 guest_idtr_limit;
 347         u32 guest_es_ar_bytes;
 348         u32 guest_cs_ar_bytes;
 349         u32 guest_ss_ar_bytes;
 350         u32 guest_ds_ar_bytes;
 351         u32 guest_fs_ar_bytes;
 352         u32 guest_gs_ar_bytes;
 353         u32 guest_ldtr_ar_bytes;
 354         u32 guest_tr_ar_bytes;
 355         u32 guest_interruptibility_info;
 356         u32 guest_activity_state;
 357         u32 guest_sysenter_cs;
 358         u32 host_ia32_sysenter_cs;
 359         u32 vmx_preemption_timer_value;
 360         u32 padding32[7]; /* room for future expansion */
 361         u16 virtual_processor_id;
 362         u16 posted_intr_nv;
 363         u16 guest_es_selector;
 364         u16 guest_cs_selector;
 365         u16 guest_ss_selector;
 366         u16 guest_ds_selector;
 367         u16 guest_fs_selector;
 368         u16 guest_gs_selector;
 369         u16 guest_ldtr_selector;
 370         u16 guest_tr_selector;
 371         u16 guest_intr_status;
 372         u16 host_es_selector;
 373         u16 host_cs_selector;
 374         u16 host_ss_selector;
 375         u16 host_ds_selector;
 376         u16 host_fs_selector;
 377         u16 host_gs_selector;
 378         u16 host_tr_selector;
 379 };
 380
 381 /*
 382  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 383  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 384  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 385  */
 386 #define VMCS12_REVISION 0x11e57ed0
 387
 388 /*
 389  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 390  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 391  * current implementation, 4K are reserved to avoid future complications.
 392  */
 393 #define VMCS12_SIZE 0x1000
 394
 395 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 396 struct vmcs02_list {
 397         struct list_head list;
 398         gpa_t vmptr;
 399         struct loaded_vmcs vmcs02;
 400 };
 401
 402 /*
 403  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 404  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 405  */
 406 struct nested_vmx {
 407         /* Has the level1 guest done vmxon? */
 408         bool vmxon;
 409         gpa_t vmxon_ptr;
 410
 411         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 412         gpa_t current_vmptr;
 413         /* The host-usable pointer to the above */
 414         struct page *current_vmcs12_page;
 415         struct vmcs12 *current_vmcs12;
 416         /*
 417          * Cache of the guest's VMCS, existing outside of guest memory.
 418          * Loaded from guest memory during VMPTRLD. Flushed to guest
 419          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 420          */
 421         struct vmcs12 *cached_vmcs12;
 422         /*
 423          * Indicates if the shadow vmcs must be updated with the
 424          * data hold by vmcs12
 425          */
 426         bool sync_shadow_vmcs;
 427
 428         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 429         struct list_head vmcs02_pool;
 430         int vmcs02_num;
 431         bool change_vmcs01_virtual_x2apic_mode;
 432         /* L2 must run next, and mustn't decide to exit to L1. */
 433         bool nested_run_pending;
 434         /*
 435          * Guest pages referred to in vmcs02 with host-physical pointers, so
 436          * we must keep them pinned while L2 runs.
 437          */
 438         struct page *apic_access_page;
 439         struct page *virtual_apic_page;
 440         struct page *pi_desc_page;
 441         struct pi_desc *pi_desc;
 442         bool pi_pending;
 443         u16 posted_intr_nv;
 444
 445         unsigned long *msr_bitmap;
 446
 447         struct hrtimer preemption_timer;
 448         bool preemption_timer_expired;
 449
 450         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 451         u64 vmcs01_debugctl;
 452
 453         u16 vpid02;
 454         u16 last_vpid;
 455
 456         /*
 457          * We only store the "true" versions of the VMX capability MSRs. We
 458          * generate the "non-true" versions by setting the must-be-1 bits
 459          * according to the SDM.
 460          */
 461         u32 nested_vmx_procbased_ctls_low;
 462         u32 nested_vmx_procbased_ctls_high;
 463         u32 nested_vmx_secondary_ctls_low;
 464         u32 nested_vmx_secondary_ctls_high;
 465         u32 nested_vmx_pinbased_ctls_low;
 466         u32 nested_vmx_pinbased_ctls_high;
 467         u32 nested_vmx_exit_ctls_low;
 468         u32 nested_vmx_exit_ctls_high;
 469         u32 nested_vmx_entry_ctls_low;
 470         u32 nested_vmx_entry_ctls_high;
 471         u32 nested_vmx_misc_low;
 472         u32 nested_vmx_misc_high;
 473         u32 nested_vmx_ept_caps;
 474         u32 nested_vmx_vpid_caps;
 475         u64 nested_vmx_basic;
 476         u64 nested_vmx_cr0_fixed0;
 477         u64 nested_vmx_cr0_fixed1;
 478         u64 nested_vmx_cr4_fixed0;
 479         u64 nested_vmx_cr4_fixed1;
 480         u64 nested_vmx_vmcs_enum;
 481 };
 482
 483 #define POSTED_INTR_ON  0
 484 #define POSTED_INTR_SN  1
 485
 486 /* Posted-Interrupt Descriptor */
 487 struct pi_desc {
 488         u32 pir[8];     /* Posted interrupt requested */
 489         union {
 490                 struct {
 491                                 /* bit 256 - Outstanding Notification */
 492                         u16     on      : 1,
 493                                 /* bit 257 - Suppress Notification */
 494                                 sn      : 1,
 495                                 /* bit 271:258 - Reserved */
 496                                 rsvd_1  : 14;
 497                                 /* bit 279:272 - Notification Vector */
 498                         u8      nv;
 499                                 /* bit 287:280 - Reserved */
 500                         u8      rsvd_2;
 501                                 /* bit 319:288 - Notification Destination */
 502                         u32     ndst;
 503                 };
 504                 u64 control;
 505         };
 506         u32 rsvd[6];
 507 } __aligned(64);
 508
 509 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 510 {
 511         return test_and_set_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 516 {
 517         return test_and_clear_bit(POSTED_INTR_ON,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 522 {
 523         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 524 }
 525
 526 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 527 {
 528         return clear_bit(POSTED_INTR_SN,
 529                         (unsigned long *)&pi_desc->control);
 530 }
 531
 532 static inline void pi_set_sn(struct pi_desc *pi_desc)
 533 {
 534         return set_bit(POSTED_INTR_SN,
 535                         (unsigned long *)&pi_desc->control);
 536 }
 537
 538 static inline void pi_clear_on(struct pi_desc *pi_desc)
 539 {
 540         clear_bit(POSTED_INTR_ON,
 541                   (unsigned long *)&pi_desc->control);
 542 }
 543
 544 static inline int pi_test_on(struct pi_desc *pi_desc)
 545 {
 546         return test_bit(POSTED_INTR_ON,
 547                         (unsigned long *)&pi_desc->control);
 548 }
 549
 550 static inline int pi_test_sn(struct pi_desc *pi_desc)
 551 {
 552         return test_bit(POSTED_INTR_SN,
 553                         (unsigned long *)&pi_desc->control);
 554 }
 555
 556 struct vcpu_vmx {
 557         struct kvm_vcpu       vcpu;
 558         unsigned long         host_rsp;
 559         u8                    fail;
 560         bool                  nmi_known_unmasked;
 561         u32                   exit_intr_info;
 562         u32                   idt_vectoring_info;
 563         ulong                 rflags;
 564         struct shared_msr_entry *guest_msrs;
 565         int                   nmsrs;
 566         int                   save_nmsrs;
 567         unsigned long         host_idt_base;
 568 #ifdef CONFIG_X86_64
 569         u64                   msr_host_kernel_gs_base;
 570         u64                   msr_guest_kernel_gs_base;
 571 #endif
 572         u32 vm_entry_controls_shadow;
 573         u32 vm_exit_controls_shadow;
 574         /*
 575          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 576          * non-nested (L1) guest, it always points to vmcs01. For a nested
 577          * guest (L2), it points to a different VMCS.
 578          */
 579         struct loaded_vmcs    vmcs01;
 580         struct loaded_vmcs   *loaded_vmcs;
 581         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 582         struct msr_autoload {
 583                 unsigned nr;
 584                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 585                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 586         } msr_autoload;
 587         struct {
 588                 int           loaded;
 589                 u16           fs_sel, gs_sel, ldt_sel;
 590 #ifdef CONFIG_X86_64
 591                 u16           ds_sel, es_sel;
 592 #endif
 593                 int           gs_ldt_reload_needed;
 594                 int           fs_reload_needed;
 595                 u64           msr_host_bndcfgs;
 596                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 597         } host_state;
 598         struct {
 599                 int vm86_active;
 600                 ulong save_rflags;
 601                 struct kvm_segment segs[8];
 602         } rmode;
 603         struct {
 604                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 605                 struct kvm_save_segment {
 606                         u16 selector;
 607                         unsigned long base;
 608                         u32 limit;
 609                         u32 ar;
 610                 } seg[8];
 611         } segment_cache;
 612         int vpid;
 613         bool emulation_required;
 614
 615         u32 exit_reason;
 616
 617         /* Posted interrupt descriptor */
 618         struct pi_desc pi_desc;
 619
 620         /* Support for a guest hypervisor (nested VMX) */
 621         struct nested_vmx nested;
 622
 623         /* Dynamic PLE window. */
 624         int ple_window;
 625         bool ple_window_dirty;
 626
 627         /* Support for PML */
 628 #define PML_ENTITY_NUM          512
 629         struct page *pml_pg;
 630
 631         /* apic deadline value in host tsc */
 632         u64 hv_deadline_tsc;
 633
 634         u64 current_tsc_ratio;
 635
 636         bool guest_pkru_valid;
 637         u32 guest_pkru;
 638         u32 host_pkru;
 639
 640         /*
 641          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 642          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 643          * in msr_ia32_feature_control_valid_bits.
 644          */
 645         u64 msr_ia32_feature_control;
 646         u64 msr_ia32_feature_control_valid_bits;
 647 };
 648
 649 enum segment_cache_field {
 650         SEG_FIELD_SEL = 0,
 651         SEG_FIELD_BASE = 1,
 652         SEG_FIELD_LIMIT = 2,
 653         SEG_FIELD_AR = 3,
 654
 655         SEG_FIELD_NR = 4
 656 };
 657
 658 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 659 {
 660         return container_of(vcpu, struct vcpu_vmx, vcpu);
 661 }
 662
 663 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 664 {
 665         return &(to_vmx(vcpu)->pi_desc);
 666 }
 667
 668 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 669 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 670 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 671                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 672
 673
 674 static unsigned long shadow_read_only_fields[] = {
 675         /*
 676          * We do NOT shadow fields that are modified when L0
 677          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 678          * VMXON...) executed by L1.
 679          * For example, VM_INSTRUCTION_ERROR is read
 680          * by L1 if a vmx instruction fails (part of the error path).
 681          * Note the code assumes this logic. If for some reason
 682          * we start shadowing these fields then we need to
 683          * force a shadow sync when L0 emulates vmx instructions
 684          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 685          * by nested_vmx_failValid)
 686          */
 687         VM_EXIT_REASON,
 688         VM_EXIT_INTR_INFO,
 689         VM_EXIT_INSTRUCTION_LEN,
 690         IDT_VECTORING_INFO_FIELD,
 691         IDT_VECTORING_ERROR_CODE,
 692         VM_EXIT_INTR_ERROR_CODE,
 693         EXIT_QUALIFICATION,
 694         GUEST_LINEAR_ADDRESS,
 695         GUEST_PHYSICAL_ADDRESS
 696 };
 697 static int max_shadow_read_only_fields =
 698         ARRAY_SIZE(shadow_read_only_fields);
 699
 700 static unsigned long shadow_read_write_fields[] = {
 701         TPR_THRESHOLD,
 702         GUEST_RIP,
 703         GUEST_RSP,
 704         GUEST_CR0,
 705         GUEST_CR3,
 706         GUEST_CR4,
 707         GUEST_INTERRUPTIBILITY_INFO,
 708         GUEST_RFLAGS,
 709         GUEST_CS_SELECTOR,
 710         GUEST_CS_AR_BYTES,
 711         GUEST_CS_LIMIT,
 712         GUEST_CS_BASE,
 713         GUEST_ES_BASE,
 714         GUEST_BNDCFGS,
 715         CR0_GUEST_HOST_MASK,
 716         CR0_READ_SHADOW,
 717         CR4_READ_SHADOW,
 718         TSC_OFFSET,
 719         EXCEPTION_BITMAP,
 720         CPU_BASED_VM_EXEC_CONTROL,
 721         VM_ENTRY_EXCEPTION_ERROR_CODE,
 722         VM_ENTRY_INTR_INFO_FIELD,
 723         VM_ENTRY_INSTRUCTION_LEN,
 724         VM_ENTRY_EXCEPTION_ERROR_CODE,
 725         HOST_FS_BASE,
 726         HOST_GS_BASE,
 727         HOST_FS_SELECTOR,
 728         HOST_GS_SELECTOR
 729 };
 730 static int max_shadow_read_write_fields =
 731         ARRAY_SIZE(shadow_read_write_fields);
 732
 733 static const unsigned short vmcs_field_to_offset_table[] = {
 734         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 735         FIELD(POSTED_INTR_NV, posted_intr_nv),
 736         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 737         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 738         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 739         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 740         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 741         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 742         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 743         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 744         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 745         FIELD(HOST_ES_SELECTOR, host_es_selector),
 746         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 747         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 748         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 749         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 750         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 751         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 752         FIELD64(IO_BITMAP_A, io_bitmap_a),
 753         FIELD64(IO_BITMAP_B, io_bitmap_b),
 754         FIELD64(MSR_BITMAP, msr_bitmap),
 755         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 756         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 757         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 758         FIELD64(TSC_OFFSET, tsc_offset),
 759         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 760         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 761         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 762         FIELD64(EPT_POINTER, ept_pointer),
 763         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 764         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 765         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 766         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 767         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 768         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 769         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 770         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 771         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 772         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 773         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 774         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 775         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 776         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 777         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 778         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 779         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 780         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 781         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 782         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 783         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 784         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 785         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 786         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 787         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 788         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 789         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 790         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 791         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 792         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 793         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 794         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 795         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 796         FIELD(TPR_THRESHOLD, tpr_threshold),
 797         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 798         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 799         FIELD(VM_EXIT_REASON, vm_exit_reason),
 800         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 801         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 802         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 803         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 804         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 805         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 806         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 807         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 808         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 809         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 810         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 811         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 812         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 813         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 814         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 815         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 816         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 817         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 818         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 819         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 820         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 821         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 822         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 823         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 824         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 825         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 826         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 827         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 828         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 829         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 830         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 831         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 832         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 833         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 834         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 835         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 836         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 837         FIELD(EXIT_QUALIFICATION, exit_qualification),
 838         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 839         FIELD(GUEST_CR0, guest_cr0),
 840         FIELD(GUEST_CR3, guest_cr3),
 841         FIELD(GUEST_CR4, guest_cr4),
 842         FIELD(GUEST_ES_BASE, guest_es_base),
 843         FIELD(GUEST_CS_BASE, guest_cs_base),
 844         FIELD(GUEST_SS_BASE, guest_ss_base),
 845         FIELD(GUEST_DS_BASE, guest_ds_base),
 846         FIELD(GUEST_FS_BASE, guest_fs_base),
 847         FIELD(GUEST_GS_BASE, guest_gs_base),
 848         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 849         FIELD(GUEST_TR_BASE, guest_tr_base),
 850         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 851         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 852         FIELD(GUEST_DR7, guest_dr7),
 853         FIELD(GUEST_RSP, guest_rsp),
 854         FIELD(GUEST_RIP, guest_rip),
 855         FIELD(GUEST_RFLAGS, guest_rflags),
 856         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 857         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 858         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 859         FIELD(HOST_CR0, host_cr0),
 860         FIELD(HOST_CR3, host_cr3),
 861         FIELD(HOST_CR4, host_cr4),
 862         FIELD(HOST_FS_BASE, host_fs_base),
 863         FIELD(HOST_GS_BASE, host_gs_base),
 864         FIELD(HOST_TR_BASE, host_tr_base),
 865         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 866         FIELD(HOST_IDTR_BASE, host_idtr_base),
 867         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 868         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 869         FIELD(HOST_RSP, host_rsp),
 870         FIELD(HOST_RIP, host_rip),
 871 };
 872
 873 static inline short vmcs_field_to_offset(unsigned long field)
 874 {
 875         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 876
 877         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 878             vmcs_field_to_offset_table[field] == 0)
 879                 return -ENOENT;
 880
 881         return vmcs_field_to_offset_table[field];
 882 }
 883
 884 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 885 {
 886         return to_vmx(vcpu)->nested.cached_vmcs12;
 887 }
 888
 889 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 890 {
 891         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 892         if (is_error_page(page))
 893                 return NULL;
 894
 895         return page;
 896 }
 897
 898 static void nested_release_page(struct page *page)
 899 {
 900         kvm_release_page_dirty(page);
 901 }
 902
 903 static void nested_release_page_clean(struct page *page)
 904 {
 905         kvm_release_page_clean(page);
 906 }
 907
 908 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 909 static u64 construct_eptp(unsigned long root_hpa);
 910 static bool vmx_xsaves_supported(void);
 911 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 912 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 913                             struct kvm_segment *var, int seg);
 914 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 915                             struct kvm_segment *var, int seg);
 916 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 917 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 918 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 919 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 920 static int alloc_identity_pagetable(struct kvm *kvm);
 921
 922 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 923 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 924 /*
 925  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 926  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 927  */
 928 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 929 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 930
 931 /*
 932  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 933  * can find which vCPU should be waken up.
 934  */
 935 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 936 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 937
 938 enum {
 939         VMX_IO_BITMAP_A,
 940         VMX_IO_BITMAP_B,
 941         VMX_MSR_BITMAP_LEGACY,
 942         VMX_MSR_BITMAP_LONGMODE,
 943         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 944         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 945         VMX_MSR_BITMAP_LEGACY_X2APIC,
 946         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 947         VMX_VMREAD_BITMAP,
 948         VMX_VMWRITE_BITMAP,
 949         VMX_BITMAP_NR
 950 };
 951
 952 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 953
 954 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 955 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 956 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 957 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 958 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 959 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 960 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 961 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 962 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 963 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 964
 965 static bool cpu_has_load_ia32_efer;
 966 static bool cpu_has_load_perf_global_ctrl;
 967
 968 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 969 static DEFINE_SPINLOCK(vmx_vpid_lock);
 970
 971 static struct vmcs_config {
 972         int size;
 973         int order;
 974         u32 basic_cap;
 975         u32 revision_id;
 976         u32 pin_based_exec_ctrl;
 977         u32 cpu_based_exec_ctrl;
 978         u32 cpu_based_2nd_exec_ctrl;
 979         u32 vmexit_ctrl;
 980         u32 vmentry_ctrl;
 981 } vmcs_config;
 982
 983 static struct vmx_capability {
 984         u32 ept;
 985         u32 vpid;
 986 } vmx_capability;
 987
 988 #define VMX_SEGMENT_FIELD(seg)                                  \
 989         [VCPU_SREG_##seg] = {                                   \
 990                 .selector = GUEST_##seg##_SELECTOR,             \
 991                 .base = GUEST_##seg##_BASE,                     \
 992                 .limit = GUEST_##seg##_LIMIT,                   \
 993                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 994         }
 995
 996 static const struct kvm_vmx_segment_field {
 997         unsigned selector;
 998         unsigned base;
 999         unsigned limit;
1000         unsigned ar_bytes;
1001 } kvm_vmx_segment_fields[] = {
1002         VMX_SEGMENT_FIELD(CS),
1003         VMX_SEGMENT_FIELD(DS),
1004         VMX_SEGMENT_FIELD(ES),
1005         VMX_SEGMENT_FIELD(FS),
1006         VMX_SEGMENT_FIELD(GS),
1007         VMX_SEGMENT_FIELD(SS),
1008         VMX_SEGMENT_FIELD(TR),
1009         VMX_SEGMENT_FIELD(LDTR),
1010 };
1011
1012 static u64 host_efer;
1013
1014 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1015
1016 /*
1017  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1018  * away by decrementing the array size.
1019  */
1020 static const u32 vmx_msr_index[] = {
1021 #ifdef CONFIG_X86_64
1022         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1023 #endif
1024         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1025 };
1026
1027 static inline bool is_exception_n(u32 intr_info, u8 vector)
1028 {
1029         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1030                              INTR_INFO_VALID_MASK)) ==
1031                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1032 }
1033
1034 static inline bool is_debug(u32 intr_info)
1035 {
1036         return is_exception_n(intr_info, DB_VECTOR);
1037 }
1038
1039 static inline bool is_breakpoint(u32 intr_info)
1040 {
1041         return is_exception_n(intr_info, BP_VECTOR);
1042 }
1043
1044 static inline bool is_page_fault(u32 intr_info)
1045 {
1046         return is_exception_n(intr_info, PF_VECTOR);
1047 }
1048
1049 static inline bool is_no_device(u32 intr_info)
1050 {
1051         return is_exception_n(intr_info, NM_VECTOR);
1052 }
1053
1054 static inline bool is_invalid_opcode(u32 intr_info)
1055 {
1056         return is_exception_n(intr_info, UD_VECTOR);
1057 }
1058
1059 static inline bool is_external_interrupt(u32 intr_info)
1060 {
1061         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1062                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1063 }
1064
1065 static inline bool is_machine_check(u32 intr_info)
1066 {
1067         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1068                              INTR_INFO_VALID_MASK)) ==
1069                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1070 }
1071
1072 static inline bool cpu_has_vmx_msr_bitmap(void)
1073 {
1074         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1075 }
1076
1077 static inline bool cpu_has_vmx_tpr_shadow(void)
1078 {
1079         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1080 }
1081
1082 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1083 {
1084         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1085 }
1086
1087 static inline bool cpu_has_secondary_exec_ctrls(void)
1088 {
1089         return vmcs_config.cpu_based_exec_ctrl &
1090                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1091 }
1092
1093 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1097 }
1098
1099 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1100 {
1101         return vmcs_config.cpu_based_2nd_exec_ctrl &
1102                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1103 }
1104
1105 static inline bool cpu_has_vmx_apic_register_virt(void)
1106 {
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1109 }
1110
1111 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl &
1114                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1115 }
1116
1117 /*
1118  * Comment's format: document - errata name - stepping - processor name.
1119  * Refer from
1120  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1121  */
1122 static u32 vmx_preemption_cpu_tfms[] = {
1123 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1124 0x000206E6,
1125 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1126 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1127 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1128 0x00020652,
1129 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1130 0x00020655,
1131 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1132 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1133 /*
1134  * 320767.pdf - AAP86  - B1 -
1135  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1136  */
1137 0x000106E5,
1138 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1139 0x000106A0,
1140 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1141 0x000106A1,
1142 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1143 0x000106A4,
1144  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1145  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1146  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1147 0x000106A5,
1148 };
1149
1150 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1151 {
1152         u32 eax = cpuid_eax(0x00000001), i;
1153
1154         /* Clear the reserved bits */
1155         eax &= ~(0x3U << 14 | 0xfU << 28);
1156         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1157                 if (eax == vmx_preemption_cpu_tfms[i])
1158                         return true;
1159
1160         return false;
1161 }
1162
1163 static inline bool cpu_has_vmx_preemption_timer(void)
1164 {
1165         return vmcs_config.pin_based_exec_ctrl &
1166                 PIN_BASED_VMX_PREEMPTION_TIMER;
1167 }
1168
1169 static inline bool cpu_has_vmx_posted_intr(void)
1170 {
1171         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1172                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1173 }
1174
1175 static inline bool cpu_has_vmx_apicv(void)
1176 {
1177         return cpu_has_vmx_apic_register_virt() &&
1178                 cpu_has_vmx_virtual_intr_delivery() &&
1179                 cpu_has_vmx_posted_intr();
1180 }
1181
1182 static inline bool cpu_has_vmx_flexpriority(void)
1183 {
1184         return cpu_has_vmx_tpr_shadow() &&
1185                 cpu_has_vmx_virtualize_apic_accesses();
1186 }
1187
1188 static inline bool cpu_has_vmx_ept_execute_only(void)
1189 {
1190         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1191 }
1192
1193 static inline bool cpu_has_vmx_ept_2m_page(void)
1194 {
1195         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept_1g_page(void)
1199 {
1200         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1201 }
1202
1203 static inline bool cpu_has_vmx_ept_4levels(void)
1204 {
1205         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_ept_ad_bits(void)
1209 {
1210         return vmx_capability.ept & VMX_EPT_AD_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_invept_context(void)
1214 {
1215         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_invept_global(void)
1219 {
1220         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_invvpid_single(void)
1224 {
1225         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1226 }
1227
1228 static inline bool cpu_has_vmx_invvpid_global(void)
1229 {
1230         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1231 }
1232
1233 static inline bool cpu_has_vmx_invvpid(void)
1234 {
1235         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1236 }
1237
1238 static inline bool cpu_has_vmx_ept(void)
1239 {
1240         return vmcs_config.cpu_based_2nd_exec_ctrl &
1241                 SECONDARY_EXEC_ENABLE_EPT;
1242 }
1243
1244 static inline bool cpu_has_vmx_unrestricted_guest(void)
1245 {
1246         return vmcs_config.cpu_based_2nd_exec_ctrl &
1247                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1248 }
1249
1250 static inline bool cpu_has_vmx_ple(void)
1251 {
1252         return vmcs_config.cpu_based_2nd_exec_ctrl &
1253                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1254 }
1255
1256 static inline bool cpu_has_vmx_basic_inout(void)
1257 {
1258         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1259 }
1260
1261 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1262 {
1263         return flexpriority_enabled && lapic_in_kernel(vcpu);
1264 }
1265
1266 static inline bool cpu_has_vmx_vpid(void)
1267 {
1268         return vmcs_config.cpu_based_2nd_exec_ctrl &
1269                 SECONDARY_EXEC_ENABLE_VPID;
1270 }
1271
1272 static inline bool cpu_has_vmx_rdtscp(void)
1273 {
1274         return vmcs_config.cpu_based_2nd_exec_ctrl &
1275                 SECONDARY_EXEC_RDTSCP;
1276 }
1277
1278 static inline bool cpu_has_vmx_invpcid(void)
1279 {
1280         return vmcs_config.cpu_based_2nd_exec_ctrl &
1281                 SECONDARY_EXEC_ENABLE_INVPCID;
1282 }
1283
1284 static inline bool cpu_has_vmx_wbinvd_exit(void)
1285 {
1286         return vmcs_config.cpu_based_2nd_exec_ctrl &
1287                 SECONDARY_EXEC_WBINVD_EXITING;
1288 }
1289
1290 static inline bool cpu_has_vmx_shadow_vmcs(void)
1291 {
1292         u64 vmx_msr;
1293         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1294         /* check if the cpu supports writing r/o exit information fields */
1295         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1296                 return false;
1297
1298         return vmcs_config.cpu_based_2nd_exec_ctrl &
1299                 SECONDARY_EXEC_SHADOW_VMCS;
1300 }
1301
1302 static inline bool cpu_has_vmx_pml(void)
1303 {
1304         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1305 }
1306
1307 static inline bool cpu_has_vmx_tsc_scaling(void)
1308 {
1309         return vmcs_config.cpu_based_2nd_exec_ctrl &
1310                 SECONDARY_EXEC_TSC_SCALING;
1311 }
1312
1313 static inline bool report_flexpriority(void)
1314 {
1315         return flexpriority_enabled;
1316 }
1317
1318 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1319 {
1320         return vmcs12->cpu_based_vm_exec_control & bit;
1321 }
1322
1323 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1324 {
1325         return (vmcs12->cpu_based_vm_exec_control &
1326                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1327                 (vmcs12->secondary_vm_exec_control & bit);
1328 }
1329
1330 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1331 {
1332         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1333 }
1334
1335 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1336 {
1337         return vmcs12->pin_based_vm_exec_control &
1338                 PIN_BASED_VMX_PREEMPTION_TIMER;
1339 }
1340
1341 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1342 {
1343         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1344 }
1345
1346 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1347 {
1348         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1349                 vmx_xsaves_supported();
1350 }
1351
1352 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1353 {
1354         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1355 }
1356
1357 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1358 {
1359         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1360 }
1361
1362 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1363 {
1364         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1365 }
1366
1367 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1368 {
1369         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1370 }
1371
1372 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1373 {
1374         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1375 }
1376
1377 static inline bool is_nmi(u32 intr_info)
1378 {
1379         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1380                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1381 }
1382
1383 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1384                               u32 exit_intr_info,
1385                               unsigned long exit_qualification);
1386 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1387                         struct vmcs12 *vmcs12,
1388                         u32 reason, unsigned long qualification);
1389
1390 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1391 {
1392         int i;
1393
1394         for (i = 0; i < vmx->nmsrs; ++i)
1395                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1396                         return i;
1397         return -1;
1398 }
1399
1400 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1401 {
1402     struct {
1403         u64 vpid : 16;
1404         u64 rsvd : 48;
1405         u64 gva;
1406     } operand = { vpid, 0, gva };
1407
1408     asm volatile (__ex(ASM_VMX_INVVPID)
1409                   /* CF==1 or ZF==1 --> rc = -1 */
1410                   "; ja 1f ; ud2 ; 1:"
1411                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1412 }
1413
1414 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1415 {
1416         struct {
1417                 u64 eptp, gpa;
1418         } operand = {eptp, gpa};
1419
1420         asm volatile (__ex(ASM_VMX_INVEPT)
1421                         /* CF==1 or ZF==1 --> rc = -1 */
1422                         "; ja 1f ; ud2 ; 1:\n"
1423                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1424 }
1425
1426 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1427 {
1428         int i;
1429
1430         i = __find_msr_index(vmx, msr);
1431         if (i >= 0)
1432                 return &vmx->guest_msrs[i];
1433         return NULL;
1434 }
1435
1436 static void vmcs_clear(struct vmcs *vmcs)
1437 {
1438         u64 phys_addr = __pa(vmcs);
1439         u8 error;
1440
1441         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1442                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1443                       : "cc", "memory");
1444         if (error)
1445                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1446                        vmcs, phys_addr);
1447 }
1448
1449 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1450 {
1451         vmcs_clear(loaded_vmcs->vmcs);
1452         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1453                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1454         loaded_vmcs->cpu = -1;
1455         loaded_vmcs->launched = 0;
1456 }
1457
1458 static void vmcs_load(struct vmcs *vmcs)
1459 {
1460         u64 phys_addr = __pa(vmcs);
1461         u8 error;
1462
1463         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1464                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1465                         : "cc", "memory");
1466         if (error)
1467                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1468                        vmcs, phys_addr);
1469 }
1470
1471 #ifdef CONFIG_KEXEC_CORE
1472 /*
1473  * This bitmap is used to indicate whether the vmclear
1474  * operation is enabled on all cpus. All disabled by
1475  * default.
1476  */
1477 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1478
1479 static inline void crash_enable_local_vmclear(int cpu)
1480 {
1481         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1482 }
1483
1484 static inline void crash_disable_local_vmclear(int cpu)
1485 {
1486         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1487 }
1488
1489 static inline int crash_local_vmclear_enabled(int cpu)
1490 {
1491         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1492 }
1493
1494 static void crash_vmclear_local_loaded_vmcss(void)
1495 {
1496         int cpu = raw_smp_processor_id();
1497         struct loaded_vmcs *v;
1498
1499         if (!crash_local_vmclear_enabled(cpu))
1500                 return;
1501
1502         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1503                             loaded_vmcss_on_cpu_link)
1504                 vmcs_clear(v->vmcs);
1505 }
1506 #else
1507 static inline void crash_enable_local_vmclear(int cpu) { }
1508 static inline void crash_disable_local_vmclear(int cpu) { }
1509 #endif /* CONFIG_KEXEC_CORE */
1510
1511 static void __loaded_vmcs_clear(void *arg)
1512 {
1513         struct loaded_vmcs *loaded_vmcs = arg;
1514         int cpu = raw_smp_processor_id();
1515
1516         if (loaded_vmcs->cpu != cpu)
1517                 return; /* vcpu migration can race with cpu offline */
1518         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1519                 per_cpu(current_vmcs, cpu) = NULL;
1520         crash_disable_local_vmclear(cpu);
1521         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1522
1523         /*
1524          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1525          * is before setting loaded_vmcs->vcpu to -1 which is done in
1526          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1527          * then adds the vmcs into percpu list before it is deleted.
1528          */
1529         smp_wmb();
1530
1531         loaded_vmcs_init(loaded_vmcs);
1532         crash_enable_local_vmclear(cpu);
1533 }
1534
1535 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1536 {
1537         int cpu = loaded_vmcs->cpu;
1538
1539         if (cpu != -1)
1540                 smp_call_function_single(cpu,
1541                          __loaded_vmcs_clear, loaded_vmcs, 1);
1542 }
1543
1544 static inline void vpid_sync_vcpu_single(int vpid)
1545 {
1546         if (vpid == 0)
1547                 return;
1548
1549         if (cpu_has_vmx_invvpid_single())
1550                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1551 }
1552
1553 static inline void vpid_sync_vcpu_global(void)
1554 {
1555         if (cpu_has_vmx_invvpid_global())
1556                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1557 }
1558
1559 static inline void vpid_sync_context(int vpid)
1560 {
1561         if (cpu_has_vmx_invvpid_single())
1562                 vpid_sync_vcpu_single(vpid);
1563         else
1564                 vpid_sync_vcpu_global();
1565 }
1566
1567 static inline void ept_sync_global(void)
1568 {
1569         if (cpu_has_vmx_invept_global())
1570                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1571 }
1572
1573 static inline void ept_sync_context(u64 eptp)
1574 {
1575         if (enable_ept) {
1576                 if (cpu_has_vmx_invept_context())
1577                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1578                 else
1579                         ept_sync_global();
1580         }
1581 }
1582
1583 static __always_inline void vmcs_check16(unsigned long field)
1584 {
1585         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1586                          "16-bit accessor invalid for 64-bit field");
1587         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1588                          "16-bit accessor invalid for 64-bit high field");
1589         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1590                          "16-bit accessor invalid for 32-bit high field");
1591         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1592                          "16-bit accessor invalid for natural width field");
1593 }
1594
1595 static __always_inline void vmcs_check32(unsigned long field)
1596 {
1597         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1598                          "32-bit accessor invalid for 16-bit field");
1599         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1600                          "32-bit accessor invalid for natural width field");
1601 }
1602
1603 static __always_inline void vmcs_check64(unsigned long field)
1604 {
1605         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1606                          "64-bit accessor invalid for 16-bit field");
1607         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1608                          "64-bit accessor invalid for 64-bit high field");
1609         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1610                          "64-bit accessor invalid for 32-bit field");
1611         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1612                          "64-bit accessor invalid for natural width field");
1613 }
1614
1615 static __always_inline void vmcs_checkl(unsigned long field)
1616 {
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1618                          "Natural width accessor invalid for 16-bit field");
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1620                          "Natural width accessor invalid for 64-bit field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1622                          "Natural width accessor invalid for 64-bit high field");
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1624                          "Natural width accessor invalid for 32-bit field");
1625 }
1626
1627 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1628 {
1629         unsigned long value;
1630
1631         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1632                       : "=a"(value) : "d"(field) : "cc");
1633         return value;
1634 }
1635
1636 static __always_inline u16 vmcs_read16(unsigned long field)
1637 {
1638         vmcs_check16(field);
1639         return __vmcs_readl(field);
1640 }
1641
1642 static __always_inline u32 vmcs_read32(unsigned long field)
1643 {
1644         vmcs_check32(field);
1645         return __vmcs_readl(field);
1646 }
1647
1648 static __always_inline u64 vmcs_read64(unsigned long field)
1649 {
1650         vmcs_check64(field);
1651 #ifdef CONFIG_X86_64
1652         return __vmcs_readl(field);
1653 #else
1654         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1655 #endif
1656 }
1657
1658 static __always_inline unsigned long vmcs_readl(unsigned long field)
1659 {
1660         vmcs_checkl(field);
1661         return __vmcs_readl(field);
1662 }
1663
1664 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1665 {
1666         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1667                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1668         dump_stack();
1669 }
1670
1671 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1672 {
1673         u8 error;
1674
1675         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1676                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1677         if (unlikely(error))
1678                 vmwrite_error(field, value);
1679 }
1680
1681 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1682 {
1683         vmcs_check16(field);
1684         __vmcs_writel(field, value);
1685 }
1686
1687 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1688 {
1689         vmcs_check32(field);
1690         __vmcs_writel(field, value);
1691 }
1692
1693 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1694 {
1695         vmcs_check64(field);
1696         __vmcs_writel(field, value);
1697 #ifndef CONFIG_X86_64
1698         asm volatile ("");
1699         __vmcs_writel(field+1, value >> 32);
1700 #endif
1701 }
1702
1703 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1704 {
1705         vmcs_checkl(field);
1706         __vmcs_writel(field, value);
1707 }
1708
1709 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1710 {
1711         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1712                          "vmcs_clear_bits does not support 64-bit fields");
1713         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1714 }
1715
1716 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1717 {
1718         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1719                          "vmcs_set_bits does not support 64-bit fields");
1720         __vmcs_writel(field, __vmcs_readl(field) | mask);
1721 }
1722
1723 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1724 {
1725         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1726 }
1727
1728 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1729 {
1730         vmcs_write32(VM_ENTRY_CONTROLS, val);
1731         vmx->vm_entry_controls_shadow = val;
1732 }
1733
1734 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1735 {
1736         if (vmx->vm_entry_controls_shadow != val)
1737                 vm_entry_controls_init(vmx, val);
1738 }
1739
1740 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1741 {
1742         return vmx->vm_entry_controls_shadow;
1743 }
1744
1745
1746 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1747 {
1748         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1749 }
1750
1751 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1752 {
1753         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1754 }
1755
1756 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1757 {
1758         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1759 }
1760
1761 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1762 {
1763         vmcs_write32(VM_EXIT_CONTROLS, val);
1764         vmx->vm_exit_controls_shadow = val;
1765 }
1766
1767 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1768 {
1769         if (vmx->vm_exit_controls_shadow != val)
1770                 vm_exit_controls_init(vmx, val);
1771 }
1772
1773 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1774 {
1775         return vmx->vm_exit_controls_shadow;
1776 }
1777
1778
1779 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1780 {
1781         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1782 }
1783
1784 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1785 {
1786         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1787 }
1788
1789 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1790 {
1791         vmx->segment_cache.bitmask = 0;
1792 }
1793
1794 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1795                                        unsigned field)
1796 {
1797         bool ret;
1798         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1799
1800         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1801                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1802                 vmx->segment_cache.bitmask = 0;
1803         }
1804         ret = vmx->segment_cache.bitmask & mask;
1805         vmx->segment_cache.bitmask |= mask;
1806         return ret;
1807 }
1808
1809 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1810 {
1811         u16 *p = &vmx->segment_cache.seg[seg].selector;
1812
1813         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1814                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1815         return *p;
1816 }
1817
1818 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1819 {
1820         ulong *p = &vmx->segment_cache.seg[seg].base;
1821
1822         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1823                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1824         return *p;
1825 }
1826
1827 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         u32 *p = &vmx->segment_cache.seg[seg].limit;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1832                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1833         return *p;
1834 }
1835
1836 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         u32 *p = &vmx->segment_cache.seg[seg].ar;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1841                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1842         return *p;
1843 }
1844
1845 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1846 {
1847         u32 eb;
1848
1849         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1850              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1851         if ((vcpu->guest_debug &
1852              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1853             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1854                 eb |= 1u << BP_VECTOR;
1855         if (to_vmx(vcpu)->rmode.vm86_active)
1856                 eb = ~0;
1857         if (enable_ept)
1858                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1859
1860         /* When we are running a nested L2 guest and L1 specified for it a
1861          * certain exception bitmap, we must trap the same exceptions and pass
1862          * them to L1. When running L2, we will only handle the exceptions
1863          * specified above if L1 did not want them.
1864          */
1865         if (is_guest_mode(vcpu))
1866                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1867
1868         vmcs_write32(EXCEPTION_BITMAP, eb);
1869 }
1870
1871 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1872                 unsigned long entry, unsigned long exit)
1873 {
1874         vm_entry_controls_clearbit(vmx, entry);
1875         vm_exit_controls_clearbit(vmx, exit);
1876 }
1877
1878 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1879 {
1880         unsigned i;
1881         struct msr_autoload *m = &vmx->msr_autoload;
1882
1883         switch (msr) {
1884         case MSR_EFER:
1885                 if (cpu_has_load_ia32_efer) {
1886                         clear_atomic_switch_msr_special(vmx,
1887                                         VM_ENTRY_LOAD_IA32_EFER,
1888                                         VM_EXIT_LOAD_IA32_EFER);
1889                         return;
1890                 }
1891                 break;
1892         case MSR_CORE_PERF_GLOBAL_CTRL:
1893                 if (cpu_has_load_perf_global_ctrl) {
1894                         clear_atomic_switch_msr_special(vmx,
1895                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1896                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1897                         return;
1898                 }
1899                 break;
1900         }
1901
1902         for (i = 0; i < m->nr; ++i)
1903                 if (m->guest[i].index == msr)
1904                         break;
1905
1906         if (i == m->nr)
1907                 return;
1908         --m->nr;
1909         m->guest[i] = m->guest[m->nr];
1910         m->host[i] = m->host[m->nr];
1911         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1912         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1913 }
1914
1915 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1916                 unsigned long entry, unsigned long exit,
1917                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1918                 u64 guest_val, u64 host_val)
1919 {
1920         vmcs_write64(guest_val_vmcs, guest_val);
1921         vmcs_write64(host_val_vmcs, host_val);
1922         vm_entry_controls_setbit(vmx, entry);
1923         vm_exit_controls_setbit(vmx, exit);
1924 }
1925
1926 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1927                                   u64 guest_val, u64 host_val)
1928 {
1929         unsigned i;
1930         struct msr_autoload *m = &vmx->msr_autoload;
1931
1932         switch (msr) {
1933         case MSR_EFER:
1934                 if (cpu_has_load_ia32_efer) {
1935                         add_atomic_switch_msr_special(vmx,
1936                                         VM_ENTRY_LOAD_IA32_EFER,
1937                                         VM_EXIT_LOAD_IA32_EFER,
1938                                         GUEST_IA32_EFER,
1939                                         HOST_IA32_EFER,
1940                                         guest_val, host_val);
1941                         return;
1942                 }
1943                 break;
1944         case MSR_CORE_PERF_GLOBAL_CTRL:
1945                 if (cpu_has_load_perf_global_ctrl) {
1946                         add_atomic_switch_msr_special(vmx,
1947                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1948                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1949                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1950                                         HOST_IA32_PERF_GLOBAL_CTRL,
1951                                         guest_val, host_val);
1952                         return;
1953                 }
1954                 break;
1955         case MSR_IA32_PEBS_ENABLE:
1956                 /* PEBS needs a quiescent period after being disabled (to write
1957                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1958                  * provide that period, so a CPU could write host's record into
1959                  * guest's memory.
1960                  */
1961                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1962         }
1963
1964         for (i = 0; i < m->nr; ++i)
1965                 if (m->guest[i].index == msr)
1966                         break;
1967
1968         if (i == NR_AUTOLOAD_MSRS) {
1969                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1970                                 "Can't add msr %x\n", msr);
1971                 return;
1972         } else if (i == m->nr) {
1973                 ++m->nr;
1974                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1975                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1976         }
1977
1978         m->guest[i].index = msr;
1979         m->guest[i].value = guest_val;
1980         m->host[i].index = msr;
1981         m->host[i].value = host_val;
1982 }
1983
1984 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1985 {
1986         u64 guest_efer = vmx->vcpu.arch.efer;
1987         u64 ignore_bits = 0;
1988
1989         if (!enable_ept) {
1990                 /*
1991                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1992                  * host CPUID is more efficient than testing guest CPUID
1993                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1994                  */
1995                 if (boot_cpu_has(X86_FEATURE_SMEP))
1996                         guest_efer |= EFER_NX;
1997                 else if (!(guest_efer & EFER_NX))
1998                         ignore_bits |= EFER_NX;
1999         }
2000
2001         /*
2002          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2003          */
2004         ignore_bits |= EFER_SCE;
2005 #ifdef CONFIG_X86_64
2006         ignore_bits |= EFER_LMA | EFER_LME;
2007         /* SCE is meaningful only in long mode on Intel */
2008         if (guest_efer & EFER_LMA)
2009                 ignore_bits &= ~(u64)EFER_SCE;
2010 #endif
2011
2012         clear_atomic_switch_msr(vmx, MSR_EFER);
2013
2014         /*
2015          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2016          * On CPUs that support "load IA32_EFER", always switch EFER
2017          * atomically, since it's faster than switching it manually.
2018          */
2019         if (cpu_has_load_ia32_efer ||
2020             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2021                 if (!(guest_efer & EFER_LMA))
2022                         guest_efer &= ~EFER_LME;
2023                 if (guest_efer != host_efer)
2024                         add_atomic_switch_msr(vmx, MSR_EFER,
2025                                               guest_efer, host_efer);
2026                 return false;
2027         } else {
2028                 guest_efer &= ~ignore_bits;
2029                 guest_efer |= host_efer & ignore_bits;
2030
2031                 vmx->guest_msrs[efer_offset].data = guest_efer;
2032                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2033
2034                 return true;
2035         }
2036 }
2037
2038 #ifdef CONFIG_X86_32
2039 /*
2040  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2041  * VMCS rather than the segment table.  KVM uses this helper to figure
2042  * out the current bases to poke them into the VMCS before entry.
2043  */
2044 static unsigned long segment_base(u16 selector)
2045 {
2046         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2047         struct desc_struct *table;
2048         unsigned long v;
2049
2050         if (!(selector & ~SEGMENT_RPL_MASK))
2051                 return 0;
2052
2053         table = (struct desc_struct *)gdt->address;
2054
2055         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2056                 u16 ldt_selector = kvm_read_ldt();
2057
2058                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2059                         return 0;
2060
2061                 table = (struct desc_struct *)segment_base(ldt_selector);
2062         }
2063         v = get_desc_base(&table[selector >> 3]);
2064         return v;
2065 }
2066 #endif
2067
2068 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2069 {
2070         struct vcpu_vmx *vmx = to_vmx(vcpu);
2071         int i;
2072
2073         if (vmx->host_state.loaded)
2074                 return;
2075
2076         vmx->host_state.loaded = 1;
2077         /*
2078          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2079          * allow segment selectors with cpl > 0 or ti == 1.
2080          */
2081         vmx->host_state.ldt_sel = kvm_read_ldt();
2082         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2083         savesegment(fs, vmx->host_state.fs_sel);
2084         if (!(vmx->host_state.fs_sel & 7)) {
2085                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2086                 vmx->host_state.fs_reload_needed = 0;
2087         } else {
2088                 vmcs_write16(HOST_FS_SELECTOR, 0);
2089                 vmx->host_state.fs_reload_needed = 1;
2090         }
2091         savesegment(gs, vmx->host_state.gs_sel);
2092         if (!(vmx->host_state.gs_sel & 7))
2093                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2094         else {
2095                 vmcs_write16(HOST_GS_SELECTOR, 0);
2096                 vmx->host_state.gs_ldt_reload_needed = 1;
2097         }
2098
2099 #ifdef CONFIG_X86_64
2100         savesegment(ds, vmx->host_state.ds_sel);
2101         savesegment(es, vmx->host_state.es_sel);
2102 #endif
2103
2104 #ifdef CONFIG_X86_64
2105         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2106         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2107 #else
2108         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2109         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2110 #endif
2111
2112 #ifdef CONFIG_X86_64
2113         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2114         if (is_long_mode(&vmx->vcpu))
2115                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2116 #endif
2117         if (boot_cpu_has(X86_FEATURE_MPX))
2118                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2119         for (i = 0; i < vmx->save_nmsrs; ++i)
2120                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2121                                    vmx->guest_msrs[i].data,
2122                                    vmx->guest_msrs[i].mask);
2123 }
2124
2125 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2126 {
2127         if (!vmx->host_state.loaded)
2128                 return;
2129
2130         ++vmx->vcpu.stat.host_state_reload;
2131         vmx->host_state.loaded = 0;
2132 #ifdef CONFIG_X86_64
2133         if (is_long_mode(&vmx->vcpu))
2134                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2135 #endif
2136         if (vmx->host_state.gs_ldt_reload_needed) {
2137                 kvm_load_ldt(vmx->host_state.ldt_sel);
2138 #ifdef CONFIG_X86_64
2139                 load_gs_index(vmx->host_state.gs_sel);
2140 #else
2141                 loadsegment(gs, vmx->host_state.gs_sel);
2142 #endif
2143         }
2144         if (vmx->host_state.fs_reload_needed)
2145                 loadsegment(fs, vmx->host_state.fs_sel);
2146 #ifdef CONFIG_X86_64
2147         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2148                 loadsegment(ds, vmx->host_state.ds_sel);
2149                 loadsegment(es, vmx->host_state.es_sel);
2150         }
2151 #endif
2152         invalidate_tss_limit();
2153 #ifdef CONFIG_X86_64
2154         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2155 #endif
2156         if (vmx->host_state.msr_host_bndcfgs)
2157                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2158         load_gdt(this_cpu_ptr(&host_gdt));
2159 }
2160
2161 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2162 {
2163         preempt_disable();
2164         __vmx_load_host_state(vmx);
2165         preempt_enable();
2166 }
2167
2168 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2169 {
2170         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2171         struct pi_desc old, new;
2172         unsigned int dest;
2173
2174         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2175                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2176                 !kvm_vcpu_apicv_active(vcpu))
2177                 return;
2178
2179         do {
2180                 old.control = new.control = pi_desc->control;
2181
2182                 /*
2183                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2184                  * are two possible cases:
2185                  * 1. After running 'pre_block', context switch
2186                  *    happened. For this case, 'sn' was set in
2187                  *    vmx_vcpu_put(), so we need to clear it here.
2188                  * 2. After running 'pre_block', we were blocked,
2189                  *    and woken up by some other guy. For this case,
2190                  *    we don't need to do anything, 'pi_post_block'
2191                  *    will do everything for us. However, we cannot
2192                  *    check whether it is case #1 or case #2 here
2193                  *    (maybe, not needed), so we also clear sn here,
2194                  *    I think it is not a big deal.
2195                  */
2196                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2197                         if (vcpu->cpu != cpu) {
2198                                 dest = cpu_physical_id(cpu);
2199
2200                                 if (x2apic_enabled())
2201                                         new.ndst = dest;
2202                                 else
2203                                         new.ndst = (dest << 8) & 0xFF00;
2204                         }
2205
2206                         /* set 'NV' to 'notification vector' */
2207                         new.nv = POSTED_INTR_VECTOR;
2208                 }
2209
2210                 /* Allow posting non-urgent interrupts */
2211                 new.sn = 0;
2212         } while (cmpxchg(&pi_desc->control, old.control,
2213                         new.control) != old.control);
2214 }
2215
2216 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2217 {
2218         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2219         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2220 }
2221
2222 /*
2223  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2224  * vcpu mutex is already taken.
2225  */
2226 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2227 {
2228         struct vcpu_vmx *vmx = to_vmx(vcpu);
2229         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2230
2231         if (!already_loaded) {
2232                 loaded_vmcs_clear(vmx->loaded_vmcs);
2233                 local_irq_disable();
2234                 crash_disable_local_vmclear(cpu);
2235
2236                 /*
2237                  * Read loaded_vmcs->cpu should be before fetching
2238                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2239                  * See the comments in __loaded_vmcs_clear().
2240                  */
2241                 smp_rmb();
2242
2243                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2244                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2245                 crash_enable_local_vmclear(cpu);
2246                 local_irq_enable();
2247         }
2248
2249         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2250                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2251                 vmcs_load(vmx->loaded_vmcs->vmcs);
2252         }
2253
2254         if (!already_loaded) {
2255                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2256                 unsigned long sysenter_esp;
2257
2258                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2259
2260                 /*
2261                  * Linux uses per-cpu TSS and GDT, so set these when switching
2262                  * processors.  See 22.2.4.
2263                  */
2264                 vmcs_writel(HOST_TR_BASE,
2265                             (unsigned long)this_cpu_ptr(&cpu_tss));
2266                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2267
2268                 /*
2269                  * VM exits change the host TR limit to 0x67 after a VM
2270                  * exit.  This is okay, since 0x67 covers everything except
2271                  * the IO bitmap and have have code to handle the IO bitmap
2272                  * being lost after a VM exit.
2273                  */
2274                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2275
2276                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2277                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2278
2279                 vmx->loaded_vmcs->cpu = cpu;
2280         }
2281
2282         /* Setup TSC multiplier */
2283         if (kvm_has_tsc_control &&
2284             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2285                 decache_tsc_multiplier(vmx);
2286
2287         vmx_vcpu_pi_load(vcpu, cpu);
2288         vmx->host_pkru = read_pkru();
2289 }
2290
2291 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2292 {
2293         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2294
2295         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2296                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2297                 !kvm_vcpu_apicv_active(vcpu))
2298                 return;
2299
2300         /* Set SN when the vCPU is preempted */
2301         if (vcpu->preempted)
2302                 pi_set_sn(pi_desc);
2303 }
2304
2305 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2306 {
2307         vmx_vcpu_pi_put(vcpu);
2308
2309         __vmx_load_host_state(to_vmx(vcpu));
2310 }
2311
2312 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2313
2314 /*
2315  * Return the cr0 value that a nested guest would read. This is a combination
2316  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2317  * its hypervisor (cr0_read_shadow).
2318  */
2319 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2320 {
2321         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2322                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2323 }
2324 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2325 {
2326         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2327                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2328 }
2329
2330 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2331 {
2332         unsigned long rflags, save_rflags;
2333
2334         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2335                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2336                 rflags = vmcs_readl(GUEST_RFLAGS);
2337                 if (to_vmx(vcpu)->rmode.vm86_active) {
2338                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2339                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2340                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2341                 }
2342                 to_vmx(vcpu)->rflags = rflags;
2343         }
2344         return to_vmx(vcpu)->rflags;
2345 }
2346
2347 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2348 {
2349         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2350         to_vmx(vcpu)->rflags = rflags;
2351         if (to_vmx(vcpu)->rmode.vm86_active) {
2352                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2353                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2354         }
2355         vmcs_writel(GUEST_RFLAGS, rflags);
2356 }
2357
2358 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2359 {
2360         return to_vmx(vcpu)->guest_pkru;
2361 }
2362
2363 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2364 {
2365         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2366         int ret = 0;
2367
2368         if (interruptibility & GUEST_INTR_STATE_STI)
2369                 ret |= KVM_X86_SHADOW_INT_STI;
2370         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2371                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2372
2373         return ret;
2374 }
2375
2376 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2377 {
2378         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2379         u32 interruptibility = interruptibility_old;
2380
2381         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2382
2383         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2384                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2385         else if (mask & KVM_X86_SHADOW_INT_STI)
2386                 interruptibility |= GUEST_INTR_STATE_STI;
2387
2388         if ((interruptibility != interruptibility_old))
2389                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2390 }
2391
2392 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2393 {
2394         unsigned long rip;
2395
2396         rip = kvm_rip_read(vcpu);
2397         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2398         kvm_rip_write(vcpu, rip);
2399
2400         /* skipping an emulated instruction also counts */
2401         vmx_set_interrupt_shadow(vcpu, 0);
2402 }
2403
2404 /*
2405  * KVM wants to inject page-faults which it got to the guest. This function
2406  * checks whether in a nested guest, we need to inject them to L1 or L2.
2407  */
2408 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2409 {
2410         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2411
2412         if (!(vmcs12->exception_bitmap & (1u << nr)))
2413                 return 0;
2414
2415         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2416                           vmcs_read32(VM_EXIT_INTR_INFO),
2417                           vmcs_readl(EXIT_QUALIFICATION));
2418         return 1;
2419 }
2420
2421 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2422                                 bool has_error_code, u32 error_code,
2423                                 bool reinject)
2424 {
2425         struct vcpu_vmx *vmx = to_vmx(vcpu);
2426         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2427
2428         if (!reinject && is_guest_mode(vcpu) &&
2429             nested_vmx_check_exception(vcpu, nr))
2430                 return;
2431
2432         if (has_error_code) {
2433                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2434                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2435         }
2436
2437         if (vmx->rmode.vm86_active) {
2438                 int inc_eip = 0;
2439                 if (kvm_exception_is_soft(nr))
2440                         inc_eip = vcpu->arch.event_exit_inst_len;
2441                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2442                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2443                 return;
2444         }
2445
2446         if (kvm_exception_is_soft(nr)) {
2447                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2448                              vmx->vcpu.arch.event_exit_inst_len);
2449                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2450         } else
2451                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2452
2453         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2454 }
2455
2456 static bool vmx_rdtscp_supported(void)
2457 {
2458         return cpu_has_vmx_rdtscp();
2459 }
2460
2461 static bool vmx_invpcid_supported(void)
2462 {
2463         return cpu_has_vmx_invpcid() && enable_ept;
2464 }
2465
2466 /*
2467  * Swap MSR entry in host/guest MSR entry array.
2468  */
2469 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2470 {
2471         struct shared_msr_entry tmp;
2472
2473         tmp = vmx->guest_msrs[to];
2474         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2475         vmx->guest_msrs[from] = tmp;
2476 }
2477
2478 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2479 {
2480         unsigned long *msr_bitmap;
2481
2482         if (is_guest_mode(vcpu))
2483                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2484         else if (cpu_has_secondary_exec_ctrls() &&
2485                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2486                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2487                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2488                         if (is_long_mode(vcpu))
2489                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2490                         else
2491                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2492                 } else {
2493                         if (is_long_mode(vcpu))
2494                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2495                         else
2496                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2497                 }
2498         } else {
2499                 if (is_long_mode(vcpu))
2500                         msr_bitmap = vmx_msr_bitmap_longmode;
2501                 else
2502                         msr_bitmap = vmx_msr_bitmap_legacy;
2503         }
2504
2505         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2506 }
2507
2508 /*
2509  * Set up the vmcs to automatically save and restore system
2510  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2511  * mode, as fiddling with msrs is very expensive.
2512  */
2513 static void setup_msrs(struct vcpu_vmx *vmx)
2514 {
2515         int save_nmsrs, index;
2516
2517         save_nmsrs = 0;
2518 #ifdef CONFIG_X86_64
2519         if (is_long_mode(&vmx->vcpu)) {
2520                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2521                 if (index >= 0)
2522                         move_msr_up(vmx, index, save_nmsrs++);
2523                 index = __find_msr_index(vmx, MSR_LSTAR);
2524                 if (index >= 0)
2525                         move_msr_up(vmx, index, save_nmsrs++);
2526                 index = __find_msr_index(vmx, MSR_CSTAR);
2527                 if (index >= 0)
2528                         move_msr_up(vmx, index, save_nmsrs++);
2529                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2530                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2531                         move_msr_up(vmx, index, save_nmsrs++);
2532                 /*
2533                  * MSR_STAR is only needed on long mode guests, and only
2534                  * if efer.sce is enabled.
2535                  */
2536                 index = __find_msr_index(vmx, MSR_STAR);
2537                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2538                         move_msr_up(vmx, index, save_nmsrs++);
2539         }
2540 #endif
2541         index = __find_msr_index(vmx, MSR_EFER);
2542         if (index >= 0 && update_transition_efer(vmx, index))
2543                 move_msr_up(vmx, index, save_nmsrs++);
2544
2545         vmx->save_nmsrs = save_nmsrs;
2546
2547         if (cpu_has_vmx_msr_bitmap())
2548                 vmx_set_msr_bitmap(&vmx->vcpu);
2549 }
2550
2551 /*
2552  * reads and returns guest's timestamp counter "register"
2553  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2554  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2555  */
2556 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2557 {
2558         u64 host_tsc, tsc_offset;
2559
2560         host_tsc = rdtsc();
2561         tsc_offset = vmcs_read64(TSC_OFFSET);
2562         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2563 }
2564
2565 /*
2566  * writes 'offset' into guest's timestamp counter offset register
2567  */
2568 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2569 {
2570         if (is_guest_mode(vcpu)) {
2571                 /*
2572                  * We're here if L1 chose not to trap WRMSR to TSC. According
2573                  * to the spec, this should set L1's TSC; The offset that L1
2574                  * set for L2 remains unchanged, and still needs to be added
2575                  * to the newly set TSC to get L2's TSC.
2576                  */
2577                 struct vmcs12 *vmcs12;
2578                 /* recalculate vmcs02.TSC_OFFSET: */
2579                 vmcs12 = get_vmcs12(vcpu);
2580                 vmcs_write64(TSC_OFFSET, offset +
2581                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2582                          vmcs12->tsc_offset : 0));
2583         } else {
2584                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2585                                            vmcs_read64(TSC_OFFSET), offset);
2586                 vmcs_write64(TSC_OFFSET, offset);
2587         }
2588 }
2589
2590 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2591 {
2592         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2593         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2594 }
2595
2596 /*
2597  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2598  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2599  * all guests if the "nested" module option is off, and can also be disabled
2600  * for a single guest by disabling its VMX cpuid bit.
2601  */
2602 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2603 {
2604         return nested && guest_cpuid_has_vmx(vcpu);
2605 }
2606
2607 /*
2608  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2609  * returned for the various VMX controls MSRs when nested VMX is enabled.
2610  * The same values should also be used to verify that vmcs12 control fields are
2611  * valid during nested entry from L1 to L2.
2612  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2613  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2614  * bit in the high half is on if the corresponding bit in the control field
2615  * may be on. See also vmx_control_verify().
2616  */
2617 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2618 {
2619         /*
2620          * Note that as a general rule, the high half of the MSRs (bits in
2621          * the control fields which may be 1) should be initialized by the
2622          * intersection of the underlying hardware's MSR (i.e., features which
2623          * can be supported) and the list of features we want to expose -
2624          * because they are known to be properly supported in our code.
2625          * Also, usually, the low half of the MSRs (bits which must be 1) can
2626          * be set to 0, meaning that L1 may turn off any of these bits. The
2627          * reason is that if one of these bits is necessary, it will appear
2628          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2629          * fields of vmcs01 and vmcs02, will turn these bits off - and
2630          * nested_vmx_exit_handled() will not pass related exits to L1.
2631          * These rules have exceptions below.
2632          */
2633
2634         /* pin-based controls */
2635         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2636                 vmx->nested.nested_vmx_pinbased_ctls_low,
2637                 vmx->nested.nested_vmx_pinbased_ctls_high);
2638         vmx->nested.nested_vmx_pinbased_ctls_low |=
2639                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2640         vmx->nested.nested_vmx_pinbased_ctls_high &=
2641                 PIN_BASED_EXT_INTR_MASK |
2642                 PIN_BASED_NMI_EXITING |
2643                 PIN_BASED_VIRTUAL_NMIS;
2644         vmx->nested.nested_vmx_pinbased_ctls_high |=
2645                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2646                 PIN_BASED_VMX_PREEMPTION_TIMER;
2647         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2648                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2649                         PIN_BASED_POSTED_INTR;
2650
2651         /* exit controls */
2652         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2653                 vmx->nested.nested_vmx_exit_ctls_low,
2654                 vmx->nested.nested_vmx_exit_ctls_high);
2655         vmx->nested.nested_vmx_exit_ctls_low =
2656                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2657
2658         vmx->nested.nested_vmx_exit_ctls_high &=
2659 #ifdef CONFIG_X86_64
2660                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2661 #endif
2662                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2663         vmx->nested.nested_vmx_exit_ctls_high |=
2664                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2665                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2666                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2667
2668         if (kvm_mpx_supported())
2669                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2670
2671         /* We support free control of debug control saving. */
2672         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2673
2674         /* entry controls */
2675         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2676                 vmx->nested.nested_vmx_entry_ctls_low,
2677                 vmx->nested.nested_vmx_entry_ctls_high);
2678         vmx->nested.nested_vmx_entry_ctls_low =
2679                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2680         vmx->nested.nested_vmx_entry_ctls_high &=
2681 #ifdef CONFIG_X86_64
2682                 VM_ENTRY_IA32E_MODE |
2683 #endif
2684                 VM_ENTRY_LOAD_IA32_PAT;
2685         vmx->nested.nested_vmx_entry_ctls_high |=
2686                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2687         if (kvm_mpx_supported())
2688                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2689
2690         /* We support free control of debug control loading. */
2691         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2692
2693         /* cpu-based controls */
2694         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2695                 vmx->nested.nested_vmx_procbased_ctls_low,
2696                 vmx->nested.nested_vmx_procbased_ctls_high);
2697         vmx->nested.nested_vmx_procbased_ctls_low =
2698                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2699         vmx->nested.nested_vmx_procbased_ctls_high &=
2700                 CPU_BASED_VIRTUAL_INTR_PENDING |
2701                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2702                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2703                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2704                 CPU_BASED_CR3_STORE_EXITING |
2705 #ifdef CONFIG_X86_64
2706                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2707 #endif
2708                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2709                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2710                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2711                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2712                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2713         /*
2714          * We can allow some features even when not supported by the
2715          * hardware. For example, L1 can specify an MSR bitmap - and we
2716          * can use it to avoid exits to L1 - even when L0 runs L2
2717          * without MSR bitmaps.
2718          */
2719         vmx->nested.nested_vmx_procbased_ctls_high |=
2720                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2721                 CPU_BASED_USE_MSR_BITMAPS;
2722
2723         /* We support free control of CR3 access interception. */
2724         vmx->nested.nested_vmx_procbased_ctls_low &=
2725                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2726
2727         /* secondary cpu-based controls */
2728         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2729                 vmx->nested.nested_vmx_secondary_ctls_low,
2730                 vmx->nested.nested_vmx_secondary_ctls_high);
2731         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2732         vmx->nested.nested_vmx_secondary_ctls_high &=
2733                 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2734                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2735                 SECONDARY_EXEC_RDTSCP |
2736                 SECONDARY_EXEC_DESC |
2737                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2738                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2739                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2740                 SECONDARY_EXEC_WBINVD_EXITING |
2741                 SECONDARY_EXEC_XSAVES;
2742
2743         if (enable_ept) {
2744                 /* nested EPT: emulate EPT also to L1 */
2745                 vmx->nested.nested_vmx_secondary_ctls_high |=
2746                         SECONDARY_EXEC_ENABLE_EPT;
2747                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2748                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2749                 if (cpu_has_vmx_ept_execute_only())
2750                         vmx->nested.nested_vmx_ept_caps |=
2751                                 VMX_EPT_EXECUTE_ONLY_BIT;
2752                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2753                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2754                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2755                         VMX_EPT_1GB_PAGE_BIT;
2756                if (enable_ept_ad_bits)
2757                        vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2758         } else
2759                 vmx->nested.nested_vmx_ept_caps = 0;
2760
2761         /*
2762          * Old versions of KVM use the single-context version without
2763          * checking for support, so declare that it is supported even
2764          * though it is treated as global context.  The alternative is
2765          * not failing the single-context invvpid, and it is worse.
2766          */
2767         if (enable_vpid) {
2768                 vmx->nested.nested_vmx_secondary_ctls_high |=
2769                         SECONDARY_EXEC_ENABLE_VPID;
2770                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2771                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2772         } else
2773                 vmx->nested.nested_vmx_vpid_caps = 0;
2774
2775         if (enable_unrestricted_guest)
2776                 vmx->nested.nested_vmx_secondary_ctls_high |=
2777                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2778
2779         /* miscellaneous data */
2780         rdmsr(MSR_IA32_VMX_MISC,
2781                 vmx->nested.nested_vmx_misc_low,
2782                 vmx->nested.nested_vmx_misc_high);
2783         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2784         vmx->nested.nested_vmx_misc_low |=
2785                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2786                 VMX_MISC_ACTIVITY_HLT;
2787         vmx->nested.nested_vmx_misc_high = 0;
2788
2789         /*
2790          * This MSR reports some information about VMX support. We
2791          * should return information about the VMX we emulate for the
2792          * guest, and the VMCS structure we give it - not about the
2793          * VMX support of the underlying hardware.
2794          */
2795         vmx->nested.nested_vmx_basic =
2796                 VMCS12_REVISION |
2797                 VMX_BASIC_TRUE_CTLS |
2798                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2799                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2800
2801         if (cpu_has_vmx_basic_inout())
2802                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2803
2804         /*
2805          * These MSRs specify bits which the guest must keep fixed on
2806          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2807          * We picked the standard core2 setting.
2808          */
2809 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2810 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2811         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2812         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2813
2814         /* These MSRs specify bits which the guest must keep fixed off. */
2815         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2816         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2817
2818         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2819         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2820 }
2821
2822 /*
2823  * if fixed0[i] == 1: val[i] must be 1
2824  * if fixed1[i] == 0: val[i] must be 0
2825  */
2826 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2827 {
2828         return ((val & fixed1) | fixed0) == val;
2829 }
2830
2831 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2832 {
2833         return fixed_bits_valid(control, low, high);
2834 }
2835
2836 static inline u64 vmx_control_msr(u32 low, u32 high)
2837 {
2838         return low | ((u64)high << 32);
2839 }
2840
2841 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2842 {
2843         superset &= mask;
2844         subset &= mask;
2845
2846         return (superset | subset) == superset;
2847 }
2848
2849 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2850 {
2851         const u64 feature_and_reserved =
2852                 /* feature (except bit 48; see below) */
2853                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2854                 /* reserved */
2855                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2856         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2857
2858         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2859                 return -EINVAL;
2860
2861         /*
2862          * KVM does not emulate a version of VMX that constrains physical
2863          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2864          */
2865         if (data & BIT_ULL(48))
2866                 return -EINVAL;
2867
2868         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2869             vmx_basic_vmcs_revision_id(data))
2870                 return -EINVAL;
2871
2872         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2873                 return -EINVAL;
2874
2875         vmx->nested.nested_vmx_basic = data;
2876         return 0;
2877 }
2878
2879 static int
2880 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2881 {
2882         u64 supported;
2883         u32 *lowp, *highp;
2884
2885         switch (msr_index) {
2886         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2887                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2888                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2889                 break;
2890         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2891                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2892                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2893                 break;
2894         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2895                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2896                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2897                 break;
2898         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2899                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2900                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2901                 break;
2902         case MSR_IA32_VMX_PROCBASED_CTLS2:
2903                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2904                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2905                 break;
2906         default:
2907                 BUG();
2908         }
2909
2910         supported = vmx_control_msr(*lowp, *highp);
2911
2912         /* Check must-be-1 bits are still 1. */
2913         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2914                 return -EINVAL;
2915
2916         /* Check must-be-0 bits are still 0. */
2917         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2918                 return -EINVAL;
2919
2920         *lowp = data;
2921         *highp = data >> 32;
2922         return 0;
2923 }
2924
2925 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2926 {
2927         const u64 feature_and_reserved_bits =
2928                 /* feature */
2929                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2930                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2931                 /* reserved */
2932                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2933         u64 vmx_misc;
2934
2935         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2936                                    vmx->nested.nested_vmx_misc_high);
2937
2938         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2939                 return -EINVAL;
2940
2941         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2942              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2943             vmx_misc_preemption_timer_rate(data) !=
2944             vmx_misc_preemption_timer_rate(vmx_misc))
2945                 return -EINVAL;
2946
2947         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2948                 return -EINVAL;
2949
2950         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2951                 return -EINVAL;
2952
2953         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2954                 return -EINVAL;
2955
2956         vmx->nested.nested_vmx_misc_low = data;
2957         vmx->nested.nested_vmx_misc_high = data >> 32;
2958         return 0;
2959 }
2960
2961 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2962 {
2963         u64 vmx_ept_vpid_cap;
2964
2965         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2966                                            vmx->nested.nested_vmx_vpid_caps);
2967
2968         /* Every bit is either reserved or a feature bit. */
2969         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2970                 return -EINVAL;
2971
2972         vmx->nested.nested_vmx_ept_caps = data;
2973         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2974         return 0;
2975 }
2976
2977 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2978 {
2979         u64 *msr;
2980
2981         switch (msr_index) {
2982         case MSR_IA32_VMX_CR0_FIXED0:
2983                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
2984                 break;
2985         case MSR_IA32_VMX_CR4_FIXED0:
2986                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
2987                 break;
2988         default:
2989                 BUG();
2990         }
2991
2992         /*
2993          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
2994          * must be 1 in the restored value.
2995          */
2996         if (!is_bitwise_subset(data, *msr, -1ULL))
2997                 return -EINVAL;
2998
2999         *msr = data;
3000         return 0;
3001 }
3002
3003 /*
3004  * Called when userspace is restoring VMX MSRs.
3005  *
3006  * Returns 0 on success, non-0 otherwise.
3007  */
3008 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3009 {
3010         struct vcpu_vmx *vmx = to_vmx(vcpu);
3011
3012         switch (msr_index) {
3013         case MSR_IA32_VMX_BASIC:
3014                 return vmx_restore_vmx_basic(vmx, data);
3015         case MSR_IA32_VMX_PINBASED_CTLS:
3016         case MSR_IA32_VMX_PROCBASED_CTLS:
3017         case MSR_IA32_VMX_EXIT_CTLS:
3018         case MSR_IA32_VMX_ENTRY_CTLS:
3019                 /*
3020                  * The "non-true" VMX capability MSRs are generated from the
3021                  * "true" MSRs, so we do not support restoring them directly.
3022                  *
3023                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3024                  * should restore the "true" MSRs with the must-be-1 bits
3025                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3026                  * DEFAULT SETTINGS".
3027                  */
3028                 return -EINVAL;
3029         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3030         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3031         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3032         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3033         case MSR_IA32_VMX_PROCBASED_CTLS2:
3034                 return vmx_restore_control_msr(vmx, msr_index, data);
3035         case MSR_IA32_VMX_MISC:
3036                 return vmx_restore_vmx_misc(vmx, data);
3037         case MSR_IA32_VMX_CR0_FIXED0:
3038         case MSR_IA32_VMX_CR4_FIXED0:
3039                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3040         case MSR_IA32_VMX_CR0_FIXED1:
3041         case MSR_IA32_VMX_CR4_FIXED1:
3042                 /*
3043                  * These MSRs are generated based on the vCPU's CPUID, so we
3044                  * do not support restoring them directly.
3045                  */
3046                 return -EINVAL;
3047         case MSR_IA32_VMX_EPT_VPID_CAP:
3048                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3049         case MSR_IA32_VMX_VMCS_ENUM:
3050                 vmx->nested.nested_vmx_vmcs_enum = data;
3051                 return 0;
3052         default:
3053                 /*
3054                  * The rest of the VMX capability MSRs do not support restore.
3055                  */
3056                 return -EINVAL;
3057         }
3058 }
3059
3060 /* Returns 0 on success, non-0 otherwise. */
3061 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3062 {
3063         struct vcpu_vmx *vmx = to_vmx(vcpu);
3064
3065         switch (msr_index) {
3066         case MSR_IA32_VMX_BASIC:
3067                 *pdata = vmx->nested.nested_vmx_basic;
3068                 break;
3069         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3070         case MSR_IA32_VMX_PINBASED_CTLS:
3071                 *pdata = vmx_control_msr(
3072                         vmx->nested.nested_vmx_pinbased_ctls_low,
3073                         vmx->nested.nested_vmx_pinbased_ctls_high);
3074                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3075                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3076                 break;
3077         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3078         case MSR_IA32_VMX_PROCBASED_CTLS:
3079                 *pdata = vmx_control_msr(
3080                         vmx->nested.nested_vmx_procbased_ctls_low,
3081                         vmx->nested.nested_vmx_procbased_ctls_high);
3082                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3083                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3084                 break;
3085         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3086         case MSR_IA32_VMX_EXIT_CTLS:
3087                 *pdata = vmx_control_msr(
3088                         vmx->nested.nested_vmx_exit_ctls_low,
3089                         vmx->nested.nested_vmx_exit_ctls_high);
3090                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3091                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3092                 break;
3093         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3094         case MSR_IA32_VMX_ENTRY_CTLS:
3095                 *pdata = vmx_control_msr(
3096                         vmx->nested.nested_vmx_entry_ctls_low,
3097                         vmx->nested.nested_vmx_entry_ctls_high);
3098                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3099                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3100                 break;
3101         case MSR_IA32_VMX_MISC:
3102                 *pdata = vmx_control_msr(
3103                         vmx->nested.nested_vmx_misc_low,
3104                         vmx->nested.nested_vmx_misc_high);
3105                 break;
3106         case MSR_IA32_VMX_CR0_FIXED0:
3107                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3108                 break;
3109         case MSR_IA32_VMX_CR0_FIXED1:
3110                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3111                 break;
3112         case MSR_IA32_VMX_CR4_FIXED0:
3113                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3114                 break;
3115         case MSR_IA32_VMX_CR4_FIXED1:
3116                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3117                 break;
3118         case MSR_IA32_VMX_VMCS_ENUM:
3119                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3120                 break;
3121         case MSR_IA32_VMX_PROCBASED_CTLS2:
3122                 *pdata = vmx_control_msr(
3123                         vmx->nested.nested_vmx_secondary_ctls_low,
3124                         vmx->nested.nested_vmx_secondary_ctls_high);
3125                 break;
3126         case MSR_IA32_VMX_EPT_VPID_CAP:
3127                 *pdata = vmx->nested.nested_vmx_ept_caps |
3128                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3129                 break;
3130         default:
3131                 return 1;
3132         }
3133
3134         return 0;
3135 }
3136
3137 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3138                                                  uint64_t val)
3139 {
3140         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3141
3142         return !(val & ~valid_bits);
3143 }
3144
3145 /*
3146  * Reads an msr value (of 'msr_index') into 'pdata'.
3147  * Returns 0 on success, non-0 otherwise.
3148  * Assumes vcpu_load() was already called.
3149  */
3150 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3151 {
3152         struct shared_msr_entry *msr;
3153
3154         switch (msr_info->index) {
3155 #ifdef CONFIG_X86_64
3156         case MSR_FS_BASE:
3157                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3158                 break;
3159         case MSR_GS_BASE:
3160                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3161                 break;
3162         case MSR_KERNEL_GS_BASE:
3163                 vmx_load_host_state(to_vmx(vcpu));
3164                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3165                 break;
3166 #endif
3167         case MSR_EFER:
3168                 return kvm_get_msr_common(vcpu, msr_info);
3169         case MSR_IA32_TSC:
3170                 msr_info->data = guest_read_tsc(vcpu);
3171                 break;
3172         case MSR_IA32_SYSENTER_CS:
3173                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3174                 break;
3175         case MSR_IA32_SYSENTER_EIP:
3176                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3177                 break;
3178         case MSR_IA32_SYSENTER_ESP:
3179                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3180                 break;
3181         case MSR_IA32_BNDCFGS:
3182                 if (!kvm_mpx_supported())
3183                         return 1;
3184                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3185                 break;
3186         case MSR_IA32_MCG_EXT_CTL:
3187                 if (!msr_info->host_initiated &&
3188                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3189                       FEATURE_CONTROL_LMCE))
3190                         return 1;
3191                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3192                 break;
3193         case MSR_IA32_FEATURE_CONTROL:
3194                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3195                 break;
3196         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3197                 if (!nested_vmx_allowed(vcpu))
3198                         return 1;
3199                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3200         case MSR_IA32_XSS:
3201                 if (!vmx_xsaves_supported())
3202                         return 1;
3203                 msr_info->data = vcpu->arch.ia32_xss;
3204                 break;
3205         case MSR_TSC_AUX:
3206                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3207                         return 1;
3208                 /* Otherwise falls through */
3209         default:
3210                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3211                 if (msr) {
3212                         msr_info->data = msr->data;
3213                         break;
3214                 }
3215                 return kvm_get_msr_common(vcpu, msr_info);
3216         }
3217
3218         return 0;
3219 }
3220
3221 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3222
3223 /*
3224  * Writes msr value into into the appropriate "register".
3225  * Returns 0 on success, non-0 otherwise.
3226  * Assumes vcpu_load() was already called.
3227  */
3228 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3229 {
3230         struct vcpu_vmx *vmx = to_vmx(vcpu);
3231         struct shared_msr_entry *msr;
3232         int ret = 0;
3233         u32 msr_index = msr_info->index;
3234         u64 data = msr_info->data;
3235
3236         switch (msr_index) {
3237         case MSR_EFER:
3238                 ret = kvm_set_msr_common(vcpu, msr_info);
3239                 break;
3240 #ifdef CONFIG_X86_64
3241         case MSR_FS_BASE:
3242                 vmx_segment_cache_clear(vmx);
3243                 vmcs_writel(GUEST_FS_BASE, data);
3244                 break;
3245         case MSR_GS_BASE:
3246                 vmx_segment_cache_clear(vmx);
3247                 vmcs_writel(GUEST_GS_BASE, data);
3248                 break;
3249         case MSR_KERNEL_GS_BASE:
3250                 vmx_load_host_state(vmx);
3251                 vmx->msr_guest_kernel_gs_base = data;
3252                 break;
3253 #endif
3254         case MSR_IA32_SYSENTER_CS:
3255                 vmcs_write32(GUEST_SYSENTER_CS, data);
3256                 break;
3257         case MSR_IA32_SYSENTER_EIP:
3258                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3259                 break;
3260         case MSR_IA32_SYSENTER_ESP:
3261                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3262                 break;
3263         case MSR_IA32_BNDCFGS:
3264                 if (!kvm_mpx_supported())
3265                         return 1;
3266                 vmcs_write64(GUEST_BNDCFGS, data);
3267                 break;
3268         case MSR_IA32_TSC:
3269                 kvm_write_tsc(vcpu, msr_info);
3270                 break;
3271         case MSR_IA32_CR_PAT:
3272                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3273                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3274                                 return 1;
3275                         vmcs_write64(GUEST_IA32_PAT, data);
3276                         vcpu->arch.pat = data;
3277                         break;
3278                 }
3279                 ret = kvm_set_msr_common(vcpu, msr_info);
3280                 break;
3281         case MSR_IA32_TSC_ADJUST:
3282                 ret = kvm_set_msr_common(vcpu, msr_info);
3283                 break;
3284         case MSR_IA32_MCG_EXT_CTL:
3285                 if ((!msr_info->host_initiated &&
3286                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3287                        FEATURE_CONTROL_LMCE)) ||
3288                     (data & ~MCG_EXT_CTL_LMCE_EN))
3289                         return 1;
3290                 vcpu->arch.mcg_ext_ctl = data;
3291                 break;
3292         case MSR_IA32_FEATURE_CONTROL:
3293                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3294                     (to_vmx(vcpu)->msr_ia32_feature_control &
3295                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3296                         return 1;
3297                 vmx->msr_ia32_feature_control = data;
3298                 if (msr_info->host_initiated && data == 0)
3299                         vmx_leave_nested(vcpu);
3300                 break;
3301         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3302                 if (!msr_info->host_initiated)
3303                         return 1; /* they are read-only */
3304                 if (!nested_vmx_allowed(vcpu))
3305                         return 1;
3306                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3307         case MSR_IA32_XSS:
3308                 if (!vmx_xsaves_supported())
3309                         return 1;
3310                 /*
3311                  * The only supported bit as of Skylake is bit 8, but
3312                  * it is not supported on KVM.
3313                  */
3314                 if (data != 0)
3315                         return 1;
3316                 vcpu->arch.ia32_xss = data;
3317                 if (vcpu->arch.ia32_xss != host_xss)
3318                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3319                                 vcpu->arch.ia32_xss, host_xss);
3320                 else
3321                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3322                 break;
3323         case MSR_TSC_AUX:
3324                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3325                         return 1;
3326                 /* Check reserved bit, higher 32 bits should be zero */
3327                 if ((data >> 32) != 0)
3328                         return 1;
3329                 /* Otherwise falls through */
3330         default:
3331                 msr = find_msr_entry(vmx, msr_index);
3332                 if (msr) {
3333                         u64 old_msr_data = msr->data;
3334                         msr->data = data;
3335                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3336                                 preempt_disable();
3337                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3338                                                          msr->mask);
3339                                 preempt_enable();
3340                                 if (ret)
3341                                         msr->data = old_msr_data;
3342                         }
3343                         break;
3344                 }
3345                 ret = kvm_set_msr_common(vcpu, msr_info);
3346         }
3347
3348         return ret;
3349 }
3350
3351 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3352 {
3353         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3354         switch (reg) {
3355         case VCPU_REGS_RSP:
3356                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3357                 break;
3358         case VCPU_REGS_RIP:
3359                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3360                 break;
3361         case VCPU_EXREG_PDPTR:
3362                 if (enable_ept)
3363                         ept_save_pdptrs(vcpu);
3364                 break;
3365         default:
3366                 break;
3367         }
3368 }
3369
3370 static __init int cpu_has_kvm_support(void)
3371 {
3372         return cpu_has_vmx();
3373 }
3374
3375 static __init int vmx_disabled_by_bios(void)
3376 {
3377         u64 msr;
3378
3379         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3380         if (msr & FEATURE_CONTROL_LOCKED) {
3381                 /* launched w/ TXT and VMX disabled */
3382                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3383                         && tboot_enabled())
3384                         return 1;
3385                 /* launched w/o TXT and VMX only enabled w/ TXT */
3386                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3387                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3388                         && !tboot_enabled()) {
3389                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3390                                 "activate TXT before enabling KVM\n");
3391                         return 1;
3392                 }
3393                 /* launched w/o TXT and VMX disabled */
3394                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3395                         && !tboot_enabled())
3396                         return 1;
3397         }
3398
3399         return 0;
3400 }
3401
3402 static void kvm_cpu_vmxon(u64 addr)
3403 {
3404         cr4_set_bits(X86_CR4_VMXE);
3405         intel_pt_handle_vmx(1);
3406
3407         asm volatile (ASM_VMX_VMXON_RAX
3408                         : : "a"(&addr), "m"(addr)
3409                         : "memory", "cc");
3410 }
3411
3412 static int hardware_enable(void)
3413 {
3414         int cpu = raw_smp_processor_id();
3415         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3416         u64 old, test_bits;
3417
3418         if (cr4_read_shadow() & X86_CR4_VMXE)
3419                 return -EBUSY;
3420
3421         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3422         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3423         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3424
3425         /*
3426          * Now we can enable the vmclear operation in kdump
3427          * since the loaded_vmcss_on_cpu list on this cpu
3428          * has been initialized.
3429          *
3430          * Though the cpu is not in VMX operation now, there
3431          * is no problem to enable the vmclear operation
3432          * for the loaded_vmcss_on_cpu list is empty!
3433          */
3434         crash_enable_local_vmclear(cpu);
3435
3436         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3437
3438         test_bits = FEATURE_CONTROL_LOCKED;
3439         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3440         if (tboot_enabled())
3441                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3442
3443         if ((old & test_bits) != test_bits) {
3444                 /* enable and lock */
3445                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3446         }
3447         kvm_cpu_vmxon(phys_addr);
3448         ept_sync_global();
3449
3450         native_store_gdt(this_cpu_ptr(&host_gdt));
3451
3452         return 0;
3453 }
3454
3455 static void vmclear_local_loaded_vmcss(void)
3456 {
3457         int cpu = raw_smp_processor_id();
3458         struct loaded_vmcs *v, *n;
3459
3460         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3461                                  loaded_vmcss_on_cpu_link)
3462                 __loaded_vmcs_clear(v);
3463 }
3464
3465
3466 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3467  * tricks.
3468  */
3469 static void kvm_cpu_vmxoff(void)
3470 {
3471         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3472
3473         intel_pt_handle_vmx(0);
3474         cr4_clear_bits(X86_CR4_VMXE);
3475 }
3476
3477 static void hardware_disable(void)
3478 {
3479         vmclear_local_loaded_vmcss();
3480         kvm_cpu_vmxoff();
3481 }
3482
3483 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3484                                       u32 msr, u32 *result)
3485 {
3486         u32 vmx_msr_low, vmx_msr_high;
3487         u32 ctl = ctl_min | ctl_opt;
3488
3489         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3490
3491         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3492         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3493
3494         /* Ensure minimum (required) set of control bits are supported. */
3495         if (ctl_min & ~ctl)
3496                 return -EIO;
3497
3498         *result = ctl;
3499         return 0;
3500 }
3501
3502 static __init bool allow_1_setting(u32 msr, u32 ctl)
3503 {
3504         u32 vmx_msr_low, vmx_msr_high;
3505
3506         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3507         return vmx_msr_high & ctl;
3508 }
3509
3510 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3511 {
3512         u32 vmx_msr_low, vmx_msr_high;
3513         u32 min, opt, min2, opt2;
3514         u32 _pin_based_exec_control = 0;
3515         u32 _cpu_based_exec_control = 0;
3516         u32 _cpu_based_2nd_exec_control = 0;
3517         u32 _vmexit_control = 0;
3518         u32 _vmentry_control = 0;
3519
3520         min = CPU_BASED_HLT_EXITING |
3521 #ifdef CONFIG_X86_64
3522               CPU_BASED_CR8_LOAD_EXITING |
3523               CPU_BASED_CR8_STORE_EXITING |
3524 #endif
3525               CPU_BASED_CR3_LOAD_EXITING |
3526               CPU_BASED_CR3_STORE_EXITING |
3527               CPU_BASED_USE_IO_BITMAPS |
3528               CPU_BASED_MOV_DR_EXITING |
3529               CPU_BASED_USE_TSC_OFFSETING |
3530               CPU_BASED_MWAIT_EXITING |
3531               CPU_BASED_MONITOR_EXITING |
3532               CPU_BASED_INVLPG_EXITING |
3533               CPU_BASED_RDPMC_EXITING;
3534
3535         opt = CPU_BASED_TPR_SHADOW |
3536               CPU_BASED_USE_MSR_BITMAPS |
3537               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3538         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3539                                 &_cpu_based_exec_control) < 0)
3540                 return -EIO;
3541 #ifdef CONFIG_X86_64
3542         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3543                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3544                                            ~CPU_BASED_CR8_STORE_EXITING;
3545 #endif
3546         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3547                 min2 = 0;
3548                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3549                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3550                         SECONDARY_EXEC_WBINVD_EXITING |
3551                         SECONDARY_EXEC_ENABLE_VPID |
3552                         SECONDARY_EXEC_ENABLE_EPT |
3553                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3554                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3555                         SECONDARY_EXEC_RDTSCP |
3556                         SECONDARY_EXEC_ENABLE_INVPCID |
3557                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3558                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3559                         SECONDARY_EXEC_SHADOW_VMCS |
3560                         SECONDARY_EXEC_XSAVES |
3561                         SECONDARY_EXEC_ENABLE_PML |
3562                         SECONDARY_EXEC_TSC_SCALING;
3563                 if (adjust_vmx_controls(min2, opt2,
3564                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3565                                         &_cpu_based_2nd_exec_control) < 0)
3566                         return -EIO;
3567         }
3568 #ifndef CONFIG_X86_64
3569         if (!(_cpu_based_2nd_exec_control &
3570                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3571                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3572 #endif
3573
3574         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3575                 _cpu_based_2nd_exec_control &= ~(
3576                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3577                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3578                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3579
3580         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3581                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3582                    enabled */
3583                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3584                                              CPU_BASED_CR3_STORE_EXITING |
3585                                              CPU_BASED_INVLPG_EXITING);
3586                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3587                       vmx_capability.ept, vmx_capability.vpid);
3588         }
3589
3590         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3591 #ifdef CONFIG_X86_64
3592         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3593 #endif
3594         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3595                 VM_EXIT_CLEAR_BNDCFGS;
3596         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3597                                 &_vmexit_control) < 0)
3598                 return -EIO;
3599
3600         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3601                 PIN_BASED_VIRTUAL_NMIS;
3602         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3603         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3604                                 &_pin_based_exec_control) < 0)
3605                 return -EIO;
3606
3607         if (cpu_has_broken_vmx_preemption_timer())
3608                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3609         if (!(_cpu_based_2nd_exec_control &
3610                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3611                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3612
3613         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3614         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3615         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3616                                 &_vmentry_control) < 0)
3617                 return -EIO;
3618
3619         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3620
3621         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3622         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3623                 return -EIO;
3624
3625 #ifdef CONFIG_X86_64
3626         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3627         if (vmx_msr_high & (1u<<16))
3628                 return -EIO;
3629 #endif
3630
3631         /* Require Write-Back (WB) memory type for VMCS accesses. */
3632         if (((vmx_msr_high >> 18) & 15) != 6)
3633                 return -EIO;
3634
3635         vmcs_conf->size = vmx_msr_high & 0x1fff;
3636         vmcs_conf->order = get_order(vmcs_conf->size);
3637         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3638         vmcs_conf->revision_id = vmx_msr_low;
3639
3640         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3641         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3642         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3643         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3644         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3645
3646         cpu_has_load_ia32_efer =
3647                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3648                                 VM_ENTRY_LOAD_IA32_EFER)
3649                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3650                                    VM_EXIT_LOAD_IA32_EFER);
3651
3652         cpu_has_load_perf_global_ctrl =
3653                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3654                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3655                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3656                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3657
3658         /*
3659          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3660          * but due to errata below it can't be used. Workaround is to use
3661          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3662          *
3663          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3664          *
3665          * AAK155             (model 26)
3666          * AAP115             (model 30)
3667          * AAT100             (model 37)
3668          * BC86,AAY89,BD102   (model 44)
3669          * BA97               (model 46)
3670          *
3671          */
3672         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3673                 switch (boot_cpu_data.x86_model) {
3674                 case 26:
3675                 case 30:
3676                 case 37:
3677                 case 44:
3678                 case 46:
3679                         cpu_has_load_perf_global_ctrl = false;
3680                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3681                                         "does not work properly. Using workaround\n");
3682                         break;
3683                 default:
3684                         break;
3685                 }
3686         }
3687
3688         if (boot_cpu_has(X86_FEATURE_XSAVES))
3689                 rdmsrl(MSR_IA32_XSS, host_xss);
3690
3691         return 0;
3692 }
3693
3694 static struct vmcs *alloc_vmcs_cpu(int cpu)
3695 {
3696         int node = cpu_to_node(cpu);
3697         struct page *pages;
3698         struct vmcs *vmcs;
3699
3700         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3701         if (!pages)
3702                 return NULL;
3703         vmcs = page_address(pages);
3704         memset(vmcs, 0, vmcs_config.size);
3705         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3706         return vmcs;
3707 }
3708
3709 static struct vmcs *alloc_vmcs(void)
3710 {
3711         return alloc_vmcs_cpu(raw_smp_processor_id());
3712 }
3713
3714 static void free_vmcs(struct vmcs *vmcs)
3715 {
3716         free_pages((unsigned long)vmcs, vmcs_config.order);
3717 }
3718
3719 /*
3720  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3721  */
3722 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3723 {
3724         if (!loaded_vmcs->vmcs)
3725                 return;
3726         loaded_vmcs_clear(loaded_vmcs);
3727         free_vmcs(loaded_vmcs->vmcs);
3728         loaded_vmcs->vmcs = NULL;
3729         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3730 }
3731
3732 static void free_kvm_area(void)
3733 {
3734         int cpu;
3735
3736         for_each_possible_cpu(cpu) {
3737                 free_vmcs(per_cpu(vmxarea, cpu));
3738                 per_cpu(vmxarea, cpu) = NULL;
3739         }
3740 }
3741
3742 static void init_vmcs_shadow_fields(void)
3743 {
3744         int i, j;
3745
3746         /* No checks for read only fields yet */
3747
3748         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3749                 switch (shadow_read_write_fields[i]) {
3750                 case GUEST_BNDCFGS:
3751                         if (!kvm_mpx_supported())
3752                                 continue;
3753                         break;
3754                 default:
3755                         break;
3756                 }
3757
3758                 if (j < i)
3759                         shadow_read_write_fields[j] =
3760                                 shadow_read_write_fields[i];
3761                 j++;
3762         }
3763         max_shadow_read_write_fields = j;
3764
3765         /* shadowed fields guest access without vmexit */
3766         for (i = 0; i < max_shadow_read_write_fields; i++) {
3767                 clear_bit(shadow_read_write_fields[i],
3768                           vmx_vmwrite_bitmap);
3769                 clear_bit(shadow_read_write_fields[i],
3770                           vmx_vmread_bitmap);
3771         }
3772         for (i = 0; i < max_shadow_read_only_fields; i++)
3773                 clear_bit(shadow_read_only_fields[i],
3774                           vmx_vmread_bitmap);
3775 }
3776
3777 static __init int alloc_kvm_area(void)
3778 {
3779         int cpu;
3780
3781         for_each_possible_cpu(cpu) {
3782                 struct vmcs *vmcs;
3783
3784                 vmcs = alloc_vmcs_cpu(cpu);
3785                 if (!vmcs) {
3786                         free_kvm_area();
3787                         return -ENOMEM;
3788                 }
3789
3790                 per_cpu(vmxarea, cpu) = vmcs;
3791         }
3792         return 0;
3793 }
3794
3795 static bool emulation_required(struct kvm_vcpu *vcpu)
3796 {
3797         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3798 }
3799
3800 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3801                 struct kvm_segment *save)
3802 {
3803         if (!emulate_invalid_guest_state) {
3804                 /*
3805                  * CS and SS RPL should be equal during guest entry according
3806                  * to VMX spec, but in reality it is not always so. Since vcpu
3807                  * is in the middle of the transition from real mode to
3808                  * protected mode it is safe to assume that RPL 0 is a good
3809                  * default value.
3810                  */
3811                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3812                         save->selector &= ~SEGMENT_RPL_MASK;
3813                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3814                 save->s = 1;
3815         }
3816         vmx_set_segment(vcpu, save, seg);
3817 }
3818
3819 static void enter_pmode(struct kvm_vcpu *vcpu)
3820 {
3821         unsigned long flags;
3822         struct vcpu_vmx *vmx = to_vmx(vcpu);
3823
3824         /*
3825          * Update real mode segment cache. It may be not up-to-date if sement
3826          * register was written while vcpu was in a guest mode.
3827          */
3828         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3829         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3830         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3831         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3832         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3833         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3834
3835         vmx->rmode.vm86_active = 0;
3836
3837         vmx_segment_cache_clear(vmx);
3838
3839         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3840
3841         flags = vmcs_readl(GUEST_RFLAGS);
3842         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3843         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3844         vmcs_writel(GUEST_RFLAGS, flags);
3845
3846         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3847                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3848
3849         update_exception_bitmap(vcpu);
3850
3851         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3852         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3853         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3854         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3855         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3856         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3857 }
3858
3859 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3860 {
3861         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3862         struct kvm_segment var = *save;
3863
3864         var.dpl = 0x3;
3865         if (seg == VCPU_SREG_CS)
3866                 var.type = 0x3;
3867
3868         if (!emulate_invalid_guest_state) {
3869                 var.selector = var.base >> 4;
3870                 var.base = var.base & 0xffff0;
3871                 var.limit = 0xffff;
3872                 var.g = 0;
3873                 var.db = 0;
3874                 var.present = 1;
3875                 var.s = 1;
3876                 var.l = 0;
3877                 var.unusable = 0;
3878                 var.type = 0x3;
3879                 var.avl = 0;
3880                 if (save->base & 0xf)
3881                         printk_once(KERN_WARNING "kvm: segment base is not "
3882                                         "paragraph aligned when entering "
3883                                         "protected mode (seg=%d)", seg);
3884         }
3885
3886         vmcs_write16(sf->selector, var.selector);
3887         vmcs_writel(sf->base, var.base);
3888         vmcs_write32(sf->limit, var.limit);
3889         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3890 }
3891
3892 static void enter_rmode(struct kvm_vcpu *vcpu)
3893 {
3894         unsigned long flags;
3895         struct vcpu_vmx *vmx = to_vmx(vcpu);
3896
3897         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3898         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3899         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3900         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3901         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3902         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3903         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3904
3905         vmx->rmode.vm86_active = 1;
3906
3907         /*
3908          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3909          * vcpu. Warn the user that an update is overdue.
3910          */
3911         if (!vcpu->kvm->arch.tss_addr)
3912                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3913                              "called before entering vcpu\n");
3914
3915         vmx_segment_cache_clear(vmx);
3916
3917         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3918         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3919         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3920
3921         flags = vmcs_readl(GUEST_RFLAGS);
3922         vmx->rmode.save_rflags = flags;
3923
3924         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3925
3926         vmcs_writel(GUEST_RFLAGS, flags);
3927         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3928         update_exception_bitmap(vcpu);
3929
3930         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3931         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3932         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3933         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3934         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3935         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3936
3937         kvm_mmu_reset_context(vcpu);
3938 }
3939
3940 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3941 {
3942         struct vcpu_vmx *vmx = to_vmx(vcpu);
3943         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3944
3945         if (!msr)
3946                 return;
3947
3948         /*
3949          * Force kernel_gs_base reloading before EFER changes, as control
3950          * of this msr depends on is_long_mode().
3951          */
3952         vmx_load_host_state(to_vmx(vcpu));
3953         vcpu->arch.efer = efer;
3954         if (efer & EFER_LMA) {
3955                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3956                 msr->data = efer;
3957         } else {
3958                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3959
3960                 msr->data = efer & ~EFER_LME;
3961         }
3962         setup_msrs(vmx);
3963 }
3964
3965 #ifdef CONFIG_X86_64
3966
3967 static void enter_lmode(struct kvm_vcpu *vcpu)
3968 {
3969         u32 guest_tr_ar;
3970
3971         vmx_segment_cache_clear(to_vmx(vcpu));
3972
3973         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3974         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3975                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3976                                      __func__);
3977                 vmcs_write32(GUEST_TR_AR_BYTES,
3978                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3979                              | VMX_AR_TYPE_BUSY_64_TSS);
3980         }
3981         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3982 }
3983
3984 static void exit_lmode(struct kvm_vcpu *vcpu)
3985 {
3986         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3987         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3988 }
3989
3990 #endif
3991
3992 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3993 {
3994         if (enable_ept) {
3995                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3996                         return;
3997                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3998         } else {
3999                 vpid_sync_context(vpid);
4000         }
4001 }
4002
4003 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4004 {
4005         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4006 }
4007
4008 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4009 {
4010         if (enable_ept)
4011                 vmx_flush_tlb(vcpu);
4012 }
4013
4014 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4015 {
4016         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4017
4018         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4019         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4020 }
4021
4022 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4023 {
4024         if (enable_ept && is_paging(vcpu))
4025                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4026         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4027 }
4028
4029 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4030 {
4031         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4032
4033         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4034         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4035 }
4036
4037 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4038 {
4039         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4040
4041         if (!test_bit(VCPU_EXREG_PDPTR,
4042                       (unsigned long *)&vcpu->arch.regs_dirty))
4043                 return;
4044
4045         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4046                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4047                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4048                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4049                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4050         }
4051 }
4052
4053 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4054 {
4055         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4056
4057         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4058                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4059                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4060                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4061                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4062         }
4063
4064         __set_bit(VCPU_EXREG_PDPTR,
4065                   (unsigned long *)&vcpu->arch.regs_avail);
4066         __set_bit(VCPU_EXREG_PDPTR,
4067                   (unsigned long *)&vcpu->arch.regs_dirty);
4068 }
4069
4070 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4071 {
4072         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4073         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4074         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4075
4076         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4077                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4078             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4079                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4080
4081         return fixed_bits_valid(val, fixed0, fixed1);
4082 }
4083
4084 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4085 {
4086         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4087         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4088
4089         return fixed_bits_valid(val, fixed0, fixed1);
4090 }
4091
4092 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4093 {
4094         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4095         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4096
4097         return fixed_bits_valid(val, fixed0, fixed1);
4098 }
4099
4100 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4101 #define nested_guest_cr4_valid  nested_cr4_valid
4102 #define nested_host_cr4_valid   nested_cr4_valid
4103
4104 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4105
4106 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4107                                         unsigned long cr0,
4108                                         struct kvm_vcpu *vcpu)
4109 {
4110         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4111                 vmx_decache_cr3(vcpu);
4112         if (!(cr0 & X86_CR0_PG)) {
4113                 /* From paging/starting to nonpaging */
4114                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4115                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4116                              (CPU_BASED_CR3_LOAD_EXITING |
4117                               CPU_BASED_CR3_STORE_EXITING));
4118                 vcpu->arch.cr0 = cr0;
4119                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4120         } else if (!is_paging(vcpu)) {
4121                 /* From nonpaging to paging */
4122                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4123                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4124                              ~(CPU_BASED_CR3_LOAD_EXITING |
4125                                CPU_BASED_CR3_STORE_EXITING));
4126                 vcpu->arch.cr0 = cr0;
4127                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4128         }
4129
4130         if (!(cr0 & X86_CR0_WP))
4131                 *hw_cr0 &= ~X86_CR0_WP;
4132 }
4133
4134 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4135 {
4136         struct vcpu_vmx *vmx = to_vmx(vcpu);
4137         unsigned long hw_cr0;
4138
4139         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4140         if (enable_unrestricted_guest)
4141                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4142         else {
4143                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4144
4145                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4146                         enter_pmode(vcpu);
4147
4148                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4149                         enter_rmode(vcpu);
4150         }
4151
4152 #ifdef CONFIG_X86_64
4153         if (vcpu->arch.efer & EFER_LME) {
4154                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4155                         enter_lmode(vcpu);
4156                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4157                         exit_lmode(vcpu);
4158         }
4159 #endif
4160
4161         if (enable_ept)
4162                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4163
4164         vmcs_writel(CR0_READ_SHADOW, cr0);
4165         vmcs_writel(GUEST_CR0, hw_cr0);
4166         vcpu->arch.cr0 = cr0;
4167
4168         /* depends on vcpu->arch.cr0 to be set to a new value */
4169         vmx->emulation_required = emulation_required(vcpu);
4170 }
4171
4172 static u64 construct_eptp(unsigned long root_hpa)
4173 {
4174         u64 eptp;
4175
4176         /* TODO write the value reading from MSR */
4177         eptp = VMX_EPT_DEFAULT_MT |
4178                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4179         if (enable_ept_ad_bits)
4180                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4181         eptp |= (root_hpa & PAGE_MASK);
4182
4183         return eptp;
4184 }
4185
4186 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4187 {
4188         unsigned long guest_cr3;
4189         u64 eptp;
4190
4191         guest_cr3 = cr3;
4192         if (enable_ept) {
4193                 eptp = construct_eptp(cr3);
4194                 vmcs_write64(EPT_POINTER, eptp);
4195                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4196                         guest_cr3 = kvm_read_cr3(vcpu);
4197                 else
4198                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4199                 ept_load_pdptrs(vcpu);
4200         }
4201
4202         vmx_flush_tlb(vcpu);
4203         vmcs_writel(GUEST_CR3, guest_cr3);
4204 }
4205
4206 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4207 {
4208         /*
4209          * Pass through host's Machine Check Enable value to hw_cr4, which
4210          * is in force while we are in guest mode.  Do not let guests control
4211          * this bit, even if host CR4.MCE == 0.
4212          */
4213         unsigned long hw_cr4 =
4214                 (cr4_read_shadow() & X86_CR4_MCE) |
4215                 (cr4 & ~X86_CR4_MCE) |
4216                 (to_vmx(vcpu)->rmode.vm86_active ?
4217                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4218
4219         if (cr4 & X86_CR4_VMXE) {
4220                 /*
4221                  * To use VMXON (and later other VMX instructions), a guest
4222                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4223                  * So basically the check on whether to allow nested VMX
4224                  * is here.
4225                  */
4226                 if (!nested_vmx_allowed(vcpu))
4227                         return 1;
4228         }
4229
4230         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4231                 return 1;
4232
4233         vcpu->arch.cr4 = cr4;
4234         if (enable_ept) {
4235                 if (!is_paging(vcpu)) {
4236                         hw_cr4 &= ~X86_CR4_PAE;
4237                         hw_cr4 |= X86_CR4_PSE;
4238                 } else if (!(cr4 & X86_CR4_PAE)) {
4239                         hw_cr4 &= ~X86_CR4_PAE;
4240                 }
4241         }
4242
4243         if (!enable_unrestricted_guest && !is_paging(vcpu))
4244                 /*
4245                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4246                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4247                  * to be manually disabled when guest switches to non-paging
4248                  * mode.
4249                  *
4250                  * If !enable_unrestricted_guest, the CPU is always running
4251                  * with CR0.PG=1 and CR4 needs to be modified.
4252                  * If enable_unrestricted_guest, the CPU automatically
4253                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4254                  */
4255                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4256
4257         vmcs_writel(CR4_READ_SHADOW, cr4);
4258         vmcs_writel(GUEST_CR4, hw_cr4);
4259         return 0;
4260 }
4261
4262 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4263                             struct kvm_segment *var, int seg)
4264 {
4265         struct vcpu_vmx *vmx = to_vmx(vcpu);
4266         u32 ar;
4267
4268         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4269                 *var = vmx->rmode.segs[seg];
4270                 if (seg == VCPU_SREG_TR
4271                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4272                         return;
4273                 var->base = vmx_read_guest_seg_base(vmx, seg);
4274                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4275                 return;
4276         }
4277         var->base = vmx_read_guest_seg_base(vmx, seg);
4278         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4279         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4280         ar = vmx_read_guest_seg_ar(vmx, seg);
4281         var->unusable = (ar >> 16) & 1;
4282         var->type = ar & 15;
4283         var->s = (ar >> 4) & 1;
4284         var->dpl = (ar >> 5) & 3;
4285         /*
4286          * Some userspaces do not preserve unusable property. Since usable
4287          * segment has to be present according to VMX spec we can use present
4288          * property to amend userspace bug by making unusable segment always
4289          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4290          * segment as unusable.
4291          */
4292         var->present = !var->unusable;
4293         var->avl = (ar >> 12) & 1;
4294         var->l = (ar >> 13) & 1;
4295         var->db = (ar >> 14) & 1;
4296         var->g = (ar >> 15) & 1;
4297 }
4298
4299 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4300 {
4301         struct kvm_segment s;
4302
4303         if (to_vmx(vcpu)->rmode.vm86_active) {
4304                 vmx_get_segment(vcpu, &s, seg);
4305                 return s.base;
4306         }
4307         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4308 }
4309
4310 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4311 {
4312         struct vcpu_vmx *vmx = to_vmx(vcpu);
4313
4314         if (unlikely(vmx->rmode.vm86_active))
4315                 return 0;
4316         else {
4317                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4318                 return VMX_AR_DPL(ar);
4319         }
4320 }
4321
4322 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4323 {
4324         u32 ar;
4325
4326         if (var->unusable || !var->present)
4327                 ar = 1 << 16;
4328         else {
4329                 ar = var->type & 15;
4330                 ar |= (var->s & 1) << 4;
4331                 ar |= (var->dpl & 3) << 5;
4332                 ar |= (var->present & 1) << 7;
4333                 ar |= (var->avl & 1) << 12;
4334                 ar |= (var->l & 1) << 13;
4335                 ar |= (var->db & 1) << 14;
4336                 ar |= (var->g & 1) << 15;
4337         }
4338
4339         return ar;
4340 }
4341
4342 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4343                             struct kvm_segment *var, int seg)
4344 {
4345         struct vcpu_vmx *vmx = to_vmx(vcpu);
4346         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4347
4348         vmx_segment_cache_clear(vmx);
4349
4350         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4351                 vmx->rmode.segs[seg] = *var;
4352                 if (seg == VCPU_SREG_TR)
4353                         vmcs_write16(sf->selector, var->selector);
4354                 else if (var->s)
4355                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4356                 goto out;
4357         }
4358
4359         vmcs_writel(sf->base, var->base);
4360         vmcs_write32(sf->limit, var->limit);
4361         vmcs_write16(sf->selector, var->selector);
4362
4363         /*
4364          *   Fix the "Accessed" bit in AR field of segment registers for older
4365          * qemu binaries.
4366          *   IA32 arch specifies that at the time of processor reset the
4367          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4368          * is setting it to 0 in the userland code. This causes invalid guest
4369          * state vmexit when "unrestricted guest" mode is turned on.
4370          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4371          * tree. Newer qemu binaries with that qemu fix would not need this
4372          * kvm hack.
4373          */
4374         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4375                 var->type |= 0x1; /* Accessed */
4376
4377         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4378
4379 out:
4380         vmx->emulation_required = emulation_required(vcpu);
4381 }
4382
4383 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4384 {
4385         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4386
4387         *db = (ar >> 14) & 1;
4388         *l = (ar >> 13) & 1;
4389 }
4390
4391 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4392 {
4393         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4394         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4395 }
4396
4397 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4398 {
4399         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4400         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4401 }
4402
4403 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4404 {
4405         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4406         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4407 }
4408
4409 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4410 {
4411         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4412         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4413 }
4414
4415 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4416 {
4417         struct kvm_segment var;
4418         u32 ar;
4419
4420         vmx_get_segment(vcpu, &var, seg);
4421         var.dpl = 0x3;
4422         if (seg == VCPU_SREG_CS)
4423                 var.type = 0x3;
4424         ar = vmx_segment_access_rights(&var);
4425
4426         if (var.base != (var.selector << 4))
4427                 return false;
4428         if (var.limit != 0xffff)
4429                 return false;
4430         if (ar != 0xf3)
4431                 return false;
4432
4433         return true;
4434 }
4435
4436 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4437 {
4438         struct kvm_segment cs;
4439         unsigned int cs_rpl;
4440
4441         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4442         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4443
4444         if (cs.unusable)
4445                 return false;
4446         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4447                 return false;
4448         if (!cs.s)
4449                 return false;
4450         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4451                 if (cs.dpl > cs_rpl)
4452                         return false;
4453         } else {
4454                 if (cs.dpl != cs_rpl)
4455                         return false;
4456         }
4457         if (!cs.present)
4458                 return false;
4459
4460         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4461         return true;
4462 }
4463
4464 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4465 {
4466         struct kvm_segment ss;
4467         unsigned int ss_rpl;
4468
4469         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4470         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4471
4472         if (ss.unusable)
4473                 return true;
4474         if (ss.type != 3 && ss.type != 7)
4475                 return false;
4476         if (!ss.s)
4477                 return false;
4478         if (ss.dpl != ss_rpl) /* DPL != RPL */
4479                 return false;
4480         if (!ss.present)
4481                 return false;
4482
4483         return true;
4484 }
4485
4486 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4487 {
4488         struct kvm_segment var;
4489         unsigned int rpl;
4490
4491         vmx_get_segment(vcpu, &var, seg);
4492         rpl = var.selector & SEGMENT_RPL_MASK;
4493
4494         if (var.unusable)
4495                 return true;
4496         if (!var.s)
4497                 return false;
4498         if (!var.present)
4499                 return false;
4500         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4501                 if (var.dpl < rpl) /* DPL < RPL */
4502                         return false;
4503         }
4504
4505         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4506          * rights flags
4507          */
4508         return true;
4509 }
4510
4511 static bool tr_valid(struct kvm_vcpu *vcpu)
4512 {
4513         struct kvm_segment tr;
4514
4515         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4516
4517         if (tr.unusable)
4518                 return false;
4519         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4520                 return false;
4521         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4522                 return false;
4523         if (!tr.present)
4524                 return false;
4525
4526         return true;
4527 }
4528
4529 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4530 {
4531         struct kvm_segment ldtr;
4532
4533         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4534
4535         if (ldtr.unusable)
4536                 return true;
4537         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4538                 return false;
4539         if (ldtr.type != 2)
4540                 return false;
4541         if (!ldtr.present)
4542                 return false;
4543
4544         return true;
4545 }
4546
4547 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4548 {
4549         struct kvm_segment cs, ss;
4550
4551         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4552         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4553
4554         return ((cs.selector & SEGMENT_RPL_MASK) ==
4555                  (ss.selector & SEGMENT_RPL_MASK));
4556 }
4557
4558 /*
4559  * Check if guest state is valid. Returns true if valid, false if
4560  * not.
4561  * We assume that registers are always usable
4562  */
4563 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4564 {
4565         if (enable_unrestricted_guest)
4566                 return true;
4567
4568         /* real mode guest state checks */
4569         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4570                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4571                         return false;
4572                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4573                         return false;
4574                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4575                         return false;
4576                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4577                         return false;
4578                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4579                         return false;
4580                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4581                         return false;
4582         } else {
4583         /* protected mode guest state checks */
4584                 if (!cs_ss_rpl_check(vcpu))
4585                         return false;
4586                 if (!code_segment_valid(vcpu))
4587                         return false;
4588                 if (!stack_segment_valid(vcpu))
4589                         return false;
4590                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4591                         return false;
4592                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4593                         return false;
4594                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4595                         return false;
4596                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4597                         return false;
4598                 if (!tr_valid(vcpu))
4599                         return false;
4600                 if (!ldtr_valid(vcpu))
4601                         return false;
4602         }
4603         /* TODO:
4604          * - Add checks on RIP
4605          * - Add checks on RFLAGS
4606          */
4607
4608         return true;
4609 }
4610
4611 static int init_rmode_tss(struct kvm *kvm)
4612 {
4613         gfn_t fn;
4614         u16 data = 0;
4615         int idx, r;
4616
4617         idx = srcu_read_lock(&kvm->srcu);
4618         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4619         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4620         if (r < 0)
4621                 goto out;
4622         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4623         r = kvm_write_guest_page(kvm, fn++, &data,
4624                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4625         if (r < 0)
4626                 goto out;
4627         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4628         if (r < 0)
4629                 goto out;
4630         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4631         if (r < 0)
4632                 goto out;
4633         data = ~0;
4634         r = kvm_write_guest_page(kvm, fn, &data,
4635                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4636                                  sizeof(u8));
4637 out:
4638         srcu_read_unlock(&kvm->srcu, idx);
4639         return r;
4640 }
4641
4642 static int init_rmode_identity_map(struct kvm *kvm)
4643 {
4644         int i, idx, r = 0;
4645         kvm_pfn_t identity_map_pfn;
4646         u32 tmp;
4647
4648         if (!enable_ept)
4649                 return 0;
4650
4651         /* Protect kvm->arch.ept_identity_pagetable_done. */
4652         mutex_lock(&kvm->slots_lock);
4653
4654         if (likely(kvm->arch.ept_identity_pagetable_done))
4655                 goto out2;
4656
4657         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4658
4659         r = alloc_identity_pagetable(kvm);
4660         if (r < 0)
4661                 goto out2;
4662
4663         idx = srcu_read_lock(&kvm->srcu);
4664         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4665         if (r < 0)
4666                 goto out;
4667         /* Set up identity-mapping pagetable for EPT in real mode */
4668         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4669                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4670                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4671                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4672                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4673                 if (r < 0)
4674                         goto out;
4675         }
4676         kvm->arch.ept_identity_pagetable_done = true;
4677
4678 out:
4679         srcu_read_unlock(&kvm->srcu, idx);
4680
4681 out2:
4682         mutex_unlock(&kvm->slots_lock);
4683         return r;
4684 }
4685
4686 static void seg_setup(int seg)
4687 {
4688         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4689         unsigned int ar;
4690
4691         vmcs_write16(sf->selector, 0);
4692         vmcs_writel(sf->base, 0);
4693         vmcs_write32(sf->limit, 0xffff);
4694         ar = 0x93;
4695         if (seg == VCPU_SREG_CS)
4696                 ar |= 0x08; /* code segment */
4697
4698         vmcs_write32(sf->ar_bytes, ar);
4699 }
4700
4701 static int alloc_apic_access_page(struct kvm *kvm)
4702 {
4703         struct page *page;
4704         int r = 0;
4705
4706         mutex_lock(&kvm->slots_lock);
4707         if (kvm->arch.apic_access_page_done)
4708                 goto out;
4709         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4710                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4711         if (r)
4712                 goto out;
4713
4714         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4715         if (is_error_page(page)) {
4716                 r = -EFAULT;
4717                 goto out;
4718         }
4719
4720         /*
4721          * Do not pin the page in memory, so that memory hot-unplug
4722          * is able to migrate it.
4723          */
4724         put_page(page);
4725         kvm->arch.apic_access_page_done = true;
4726 out:
4727         mutex_unlock(&kvm->slots_lock);
4728         return r;
4729 }
4730
4731 static int alloc_identity_pagetable(struct kvm *kvm)
4732 {
4733         /* Called with kvm->slots_lock held. */
4734
4735         int r = 0;
4736
4737         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4738
4739         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4740                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4741
4742         return r;
4743 }
4744
4745 static int allocate_vpid(void)
4746 {
4747         int vpid;
4748
4749         if (!enable_vpid)
4750                 return 0;
4751         spin_lock(&vmx_vpid_lock);
4752         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4753         if (vpid < VMX_NR_VPIDS)
4754                 __set_bit(vpid, vmx_vpid_bitmap);
4755         else
4756                 vpid = 0;
4757         spin_unlock(&vmx_vpid_lock);
4758         return vpid;
4759 }
4760
4761 static void free_vpid(int vpid)
4762 {
4763         if (!enable_vpid || vpid == 0)
4764                 return;
4765         spin_lock(&vmx_vpid_lock);
4766         __clear_bit(vpid, vmx_vpid_bitmap);
4767         spin_unlock(&vmx_vpid_lock);
4768 }
4769
4770 #define MSR_TYPE_R      1
4771 #define MSR_TYPE_W      2
4772 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4773                                                 u32 msr, int type)
4774 {
4775         int f = sizeof(unsigned long);
4776
4777         if (!cpu_has_vmx_msr_bitmap())
4778                 return;
4779
4780         /*
4781          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4782          * have the write-low and read-high bitmap offsets the wrong way round.
4783          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4784          */
4785         if (msr <= 0x1fff) {
4786                 if (type & MSR_TYPE_R)
4787                         /* read-low */
4788                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4789
4790                 if (type & MSR_TYPE_W)
4791                         /* write-low */
4792                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4793
4794         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4795                 msr &= 0x1fff;
4796                 if (type & MSR_TYPE_R)
4797                         /* read-high */
4798                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4799
4800                 if (type & MSR_TYPE_W)
4801                         /* write-high */
4802                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4803
4804         }
4805 }
4806
4807 /*
4808  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4809  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4810  */
4811 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4812                                                unsigned long *msr_bitmap_nested,
4813                                                u32 msr, int type)
4814 {
4815         int f = sizeof(unsigned long);
4816
4817         if (!cpu_has_vmx_msr_bitmap()) {
4818                 WARN_ON(1);
4819                 return;
4820         }
4821
4822         /*
4823          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4824          * have the write-low and read-high bitmap offsets the wrong way round.
4825          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4826          */
4827         if (msr <= 0x1fff) {
4828                 if (type & MSR_TYPE_R &&
4829                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4830                         /* read-low */
4831                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4832
4833                 if (type & MSR_TYPE_W &&
4834                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4835                         /* write-low */
4836                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4837
4838         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4839                 msr &= 0x1fff;
4840                 if (type & MSR_TYPE_R &&
4841                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4842                         /* read-high */
4843                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4844
4845                 if (type & MSR_TYPE_W &&
4846                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4847                         /* write-high */
4848                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4849
4850         }
4851 }
4852
4853 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4854 {
4855         if (!longmode_only)
4856                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4857                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4858         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4859                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4860 }
4861
4862 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4863 {
4864         if (apicv_active) {
4865                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4866                                 msr, type);
4867                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4868                                 msr, type);
4869         } else {
4870                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4871                                 msr, type);
4872                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4873                                 msr, type);
4874         }
4875 }
4876
4877 static bool vmx_get_enable_apicv(void)
4878 {
4879         return enable_apicv;
4880 }
4881
4882 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4883 {
4884         struct vcpu_vmx *vmx = to_vmx(vcpu);
4885         int max_irr;
4886         void *vapic_page;
4887         u16 status;
4888
4889         if (vmx->nested.pi_desc &&
4890             vmx->nested.pi_pending) {
4891                 vmx->nested.pi_pending = false;
4892                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4893                         return;
4894
4895                 max_irr = find_last_bit(
4896                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4897
4898                 if (max_irr == 256)
4899                         return;
4900
4901                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4902                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4903                 kunmap(vmx->nested.virtual_apic_page);
4904
4905                 status = vmcs_read16(GUEST_INTR_STATUS);
4906                 if ((u8)max_irr > ((u8)status & 0xff)) {
4907                         status &= ~0xff;
4908                         status |= (u8)max_irr;
4909                         vmcs_write16(GUEST_INTR_STATUS, status);
4910                 }
4911         }
4912 }
4913
4914 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4915 {
4916 #ifdef CONFIG_SMP
4917         if (vcpu->mode == IN_GUEST_MODE) {
4918                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4919
4920                 /*
4921                  * Currently, we don't support urgent interrupt,
4922                  * all interrupts are recognized as non-urgent
4923                  * interrupt, so we cannot post interrupts when
4924                  * 'SN' is set.
4925                  *
4926                  * If the vcpu is in guest mode, it means it is
4927                  * running instead of being scheduled out and
4928                  * waiting in the run queue, and that's the only
4929                  * case when 'SN' is set currently, warning if
4930                  * 'SN' is set.
4931                  */
4932                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4933
4934                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4935                                 POSTED_INTR_VECTOR);
4936                 return true;
4937         }
4938 #endif
4939         return false;
4940 }
4941
4942 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4943                                                 int vector)
4944 {
4945         struct vcpu_vmx *vmx = to_vmx(vcpu);
4946
4947         if (is_guest_mode(vcpu) &&
4948             vector == vmx->nested.posted_intr_nv) {
4949                 /* the PIR and ON have been set by L1. */
4950                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4951                 /*
4952                  * If a posted intr is not recognized by hardware,
4953                  * we will accomplish it in the next vmentry.
4954                  */
4955                 vmx->nested.pi_pending = true;
4956                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4957                 return 0;
4958         }
4959         return -1;
4960 }
4961 /*
4962  * Send interrupt to vcpu via posted interrupt way.
4963  * 1. If target vcpu is running(non-root mode), send posted interrupt
4964  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4965  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4966  * interrupt from PIR in next vmentry.
4967  */
4968 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4969 {
4970         struct vcpu_vmx *vmx = to_vmx(vcpu);
4971         int r;
4972
4973         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4974         if (!r)
4975                 return;
4976
4977         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4978                 return;
4979
4980         /* If a previous notification has sent the IPI, nothing to do.  */
4981         if (pi_test_and_set_on(&vmx->pi_desc))
4982                 return;
4983
4984         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
4985                 kvm_vcpu_kick(vcpu);
4986 }
4987
4988 /*
4989  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4990  * will not change in the lifetime of the guest.
4991  * Note that host-state that does change is set elsewhere. E.g., host-state
4992  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4993  */
4994 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4995 {
4996         u32 low32, high32;
4997         unsigned long tmpl;
4998         struct desc_ptr dt;
4999         unsigned long cr0, cr4;
5000
5001         cr0 = read_cr0();
5002         WARN_ON(cr0 & X86_CR0_TS);
5003         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5004         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5005
5006         /* Save the most likely value for this task's CR4 in the VMCS. */
5007         cr4 = cr4_read_shadow();
5008         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5009         vmx->host_state.vmcs_host_cr4 = cr4;
5010
5011         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5012 #ifdef CONFIG_X86_64
5013         /*
5014          * Load null selectors, so we can avoid reloading them in
5015          * __vmx_load_host_state(), in case userspace uses the null selectors
5016          * too (the expected case).
5017          */
5018         vmcs_write16(HOST_DS_SELECTOR, 0);
5019         vmcs_write16(HOST_ES_SELECTOR, 0);
5020 #else
5021         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5022         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5023 #endif
5024         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5025         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5026
5027         native_store_idt(&dt);
5028         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5029         vmx->host_idt_base = dt.address;
5030
5031         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5032
5033         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5034         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5035         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5036         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5037
5038         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5039                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5040                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5041         }
5042 }
5043
5044 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5045 {
5046         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5047         if (enable_ept)
5048                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5049         if (is_guest_mode(&vmx->vcpu))
5050                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5051                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5052         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5053 }
5054
5055 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5056 {
5057         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5058
5059         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5060                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5061         /* Enable the preemption timer dynamically */
5062         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5063         return pin_based_exec_ctrl;
5064 }
5065
5066 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5067 {
5068         struct vcpu_vmx *vmx = to_vmx(vcpu);
5069
5070         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5071         if (cpu_has_secondary_exec_ctrls()) {
5072                 if (kvm_vcpu_apicv_active(vcpu))
5073                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5074                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5075                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5076                 else
5077                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5078                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5079                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5080         }
5081
5082         if (cpu_has_vmx_msr_bitmap())
5083                 vmx_set_msr_bitmap(vcpu);
5084 }
5085
5086 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5087 {
5088         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5089
5090         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5091                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5092
5093         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5094                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5095 #ifdef CONFIG_X86_64
5096                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5097                                 CPU_BASED_CR8_LOAD_EXITING;
5098 #endif
5099         }
5100         if (!enable_ept)
5101                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5102                                 CPU_BASED_CR3_LOAD_EXITING  |
5103                                 CPU_BASED_INVLPG_EXITING;
5104         return exec_control;
5105 }
5106
5107 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5108 {
5109         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5110         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5111                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5112         if (vmx->vpid == 0)
5113                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5114         if (!enable_ept) {
5115                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5116                 enable_unrestricted_guest = 0;
5117                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5118                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5119         }
5120         if (!enable_unrestricted_guest)
5121                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5122         if (!ple_gap)
5123                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5124         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5125                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5126                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5127         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5128         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5129            (handle_vmptrld).
5130            We can NOT enable shadow_vmcs here because we don't have yet
5131            a current VMCS12
5132         */
5133         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5134
5135         if (!enable_pml)
5136                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5137
5138         return exec_control;
5139 }
5140
5141 static void ept_set_mmio_spte_mask(void)
5142 {
5143         /*
5144          * EPT Misconfigurations can be generated if the value of bits 2:0
5145          * of an EPT paging-structure entry is 110b (write/execute).
5146          */
5147         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5148 }
5149
5150 #define VMX_XSS_EXIT_BITMAP 0
5151 /*
5152  * Sets up the vmcs for emulated real mode.
5153  */
5154 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5155 {
5156 #ifdef CONFIG_X86_64
5157         unsigned long a;
5158 #endif
5159         int i;
5160
5161         /* I/O */
5162         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5163         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5164
5165         if (enable_shadow_vmcs) {
5166                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5167                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5168         }
5169         if (cpu_has_vmx_msr_bitmap())
5170                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5171
5172         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5173
5174         /* Control */
5175         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5176         vmx->hv_deadline_tsc = -1;
5177
5178         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5179
5180         if (cpu_has_secondary_exec_ctrls()) {
5181                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5182                                 vmx_secondary_exec_control(vmx));
5183         }
5184
5185         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5186                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5187                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5188                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5189                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5190
5191                 vmcs_write16(GUEST_INTR_STATUS, 0);
5192
5193                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5194                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5195         }
5196
5197         if (ple_gap) {
5198                 vmcs_write32(PLE_GAP, ple_gap);
5199                 vmx->ple_window = ple_window;
5200                 vmx->ple_window_dirty = true;
5201         }
5202
5203         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5204         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5205         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5206
5207         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5208         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5209         vmx_set_constant_host_state(vmx);
5210 #ifdef CONFIG_X86_64
5211         rdmsrl(MSR_FS_BASE, a);
5212         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5213         rdmsrl(MSR_GS_BASE, a);
5214         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5215 #else
5216         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5217         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5218 #endif
5219
5220         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5221         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5222         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5223         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5224         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5225
5226         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5227                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5228
5229         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5230                 u32 index = vmx_msr_index[i];
5231                 u32 data_low, data_high;
5232                 int j = vmx->nmsrs;
5233
5234                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5235                         continue;
5236                 if (wrmsr_safe(index, data_low, data_high) < 0)
5237                         continue;
5238                 vmx->guest_msrs[j].index = i;
5239                 vmx->guest_msrs[j].data = 0;
5240                 vmx->guest_msrs[j].mask = -1ull;
5241                 ++vmx->nmsrs;
5242         }
5243
5244
5245         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5246
5247         /* 22.2.1, 20.8.1 */
5248         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5249
5250         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5251         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5252
5253         set_cr4_guest_host_mask(vmx);
5254
5255         if (vmx_xsaves_supported())
5256                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5257
5258         if (enable_pml) {
5259                 ASSERT(vmx->pml_pg);
5260                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5261                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5262         }
5263
5264         return 0;
5265 }
5266
5267 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5268 {
5269         struct vcpu_vmx *vmx = to_vmx(vcpu);
5270         struct msr_data apic_base_msr;
5271         u64 cr0;
5272
5273         vmx->rmode.vm86_active = 0;
5274
5275         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5276         kvm_set_cr8(vcpu, 0);
5277
5278         if (!init_event) {
5279                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5280                                      MSR_IA32_APICBASE_ENABLE;
5281                 if (kvm_vcpu_is_reset_bsp(vcpu))
5282                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5283                 apic_base_msr.host_initiated = true;
5284                 kvm_set_apic_base(vcpu, &apic_base_msr);
5285         }
5286
5287         vmx_segment_cache_clear(vmx);
5288
5289         seg_setup(VCPU_SREG_CS);
5290         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5291         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5292
5293         seg_setup(VCPU_SREG_DS);
5294         seg_setup(VCPU_SREG_ES);
5295         seg_setup(VCPU_SREG_FS);
5296         seg_setup(VCPU_SREG_GS);
5297         seg_setup(VCPU_SREG_SS);
5298
5299         vmcs_write16(GUEST_TR_SELECTOR, 0);
5300         vmcs_writel(GUEST_TR_BASE, 0);
5301         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5302         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5303
5304         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5305         vmcs_writel(GUEST_LDTR_BASE, 0);
5306         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5307         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5308
5309         if (!init_event) {
5310                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5311                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5312                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5313                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5314         }
5315
5316         vmcs_writel(GUEST_RFLAGS, 0x02);
5317         kvm_rip_write(vcpu, 0xfff0);
5318
5319         vmcs_writel(GUEST_GDTR_BASE, 0);
5320         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5321
5322         vmcs_writel(GUEST_IDTR_BASE, 0);
5323         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5324
5325         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5326         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5327         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5328
5329         setup_msrs(vmx);
5330
5331         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5332
5333         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5334                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5335                 if (cpu_need_tpr_shadow(vcpu))
5336                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5337                                      __pa(vcpu->arch.apic->regs));
5338                 vmcs_write32(TPR_THRESHOLD, 0);
5339         }
5340
5341         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5342
5343         if (kvm_vcpu_apicv_active(vcpu))
5344                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5345
5346         if (vmx->vpid != 0)
5347                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5348
5349         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5350         vmx->vcpu.arch.cr0 = cr0;
5351         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5352         vmx_set_cr4(vcpu, 0);
5353         vmx_set_efer(vcpu, 0);
5354
5355         update_exception_bitmap(vcpu);
5356
5357         vpid_sync_context(vmx->vpid);
5358 }
5359
5360 /*
5361  * In nested virtualization, check if L1 asked to exit on external interrupts.
5362  * For most existing hypervisors, this will always return true.
5363  */
5364 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5365 {
5366         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5367                 PIN_BASED_EXT_INTR_MASK;
5368 }
5369
5370 /*
5371  * In nested virtualization, check if L1 has set
5372  * VM_EXIT_ACK_INTR_ON_EXIT
5373  */
5374 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5375 {
5376         return get_vmcs12(vcpu)->vm_exit_controls &
5377                 VM_EXIT_ACK_INTR_ON_EXIT;
5378 }
5379
5380 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5381 {
5382         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5383                 PIN_BASED_NMI_EXITING;
5384 }
5385
5386 static void enable_irq_window(struct kvm_vcpu *vcpu)
5387 {
5388         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5389                       CPU_BASED_VIRTUAL_INTR_PENDING);
5390 }
5391
5392 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5393 {
5394         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5395                 enable_irq_window(vcpu);
5396                 return;
5397         }
5398
5399         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5400                       CPU_BASED_VIRTUAL_NMI_PENDING);
5401 }
5402
5403 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5404 {
5405         struct vcpu_vmx *vmx = to_vmx(vcpu);
5406         uint32_t intr;
5407         int irq = vcpu->arch.interrupt.nr;
5408
5409         trace_kvm_inj_virq(irq);
5410
5411         ++vcpu->stat.irq_injections;
5412         if (vmx->rmode.vm86_active) {
5413                 int inc_eip = 0;
5414                 if (vcpu->arch.interrupt.soft)
5415                         inc_eip = vcpu->arch.event_exit_inst_len;
5416                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5417                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5418                 return;
5419         }
5420         intr = irq | INTR_INFO_VALID_MASK;
5421         if (vcpu->arch.interrupt.soft) {
5422                 intr |= INTR_TYPE_SOFT_INTR;
5423                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5424                              vmx->vcpu.arch.event_exit_inst_len);
5425         } else
5426                 intr |= INTR_TYPE_EXT_INTR;
5427         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5428 }
5429
5430 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5431 {
5432         struct vcpu_vmx *vmx = to_vmx(vcpu);
5433
5434         if (!is_guest_mode(vcpu)) {
5435                 ++vcpu->stat.nmi_injections;
5436                 vmx->nmi_known_unmasked = false;
5437         }
5438
5439         if (vmx->rmode.vm86_active) {
5440                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5441                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5442                 return;
5443         }
5444
5445         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5446                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5447 }
5448
5449 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5450 {
5451         if (to_vmx(vcpu)->nmi_known_unmasked)
5452                 return false;
5453         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5454 }
5455
5456 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5457 {
5458         struct vcpu_vmx *vmx = to_vmx(vcpu);
5459
5460         vmx->nmi_known_unmasked = !masked;
5461         if (masked)
5462                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5463                               GUEST_INTR_STATE_NMI);
5464         else
5465                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5466                                 GUEST_INTR_STATE_NMI);
5467 }
5468
5469 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5470 {
5471         if (to_vmx(vcpu)->nested.nested_run_pending)
5472                 return 0;
5473
5474         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5475                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5476                    | GUEST_INTR_STATE_NMI));
5477 }
5478
5479 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5480 {
5481         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5482                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5483                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5484                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5485 }
5486
5487 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5488 {
5489         int ret;
5490
5491         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5492                                     PAGE_SIZE * 3);
5493         if (ret)
5494                 return ret;
5495         kvm->arch.tss_addr = addr;
5496         return init_rmode_tss(kvm);
5497 }
5498
5499 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5500 {
5501         switch (vec) {
5502         case BP_VECTOR:
5503                 /*
5504                  * Update instruction length as we may reinject the exception
5505                  * from user space while in guest debugging mode.
5506                  */
5507                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5508                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5509                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5510                         return false;
5511                 /* fall through */
5512         case DB_VECTOR:
5513                 if (vcpu->guest_debug &
5514                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5515                         return false;
5516                 /* fall through */
5517         case DE_VECTOR:
5518         case OF_VECTOR:
5519         case BR_VECTOR:
5520         case UD_VECTOR:
5521         case DF_VECTOR:
5522         case SS_VECTOR:
5523         case GP_VECTOR:
5524         case MF_VECTOR:
5525                 return true;
5526         break;
5527         }
5528         return false;
5529 }
5530
5531 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5532                                   int vec, u32 err_code)
5533 {
5534         /*
5535          * Instruction with address size override prefix opcode 0x67
5536          * Cause the #SS fault with 0 error code in VM86 mode.
5537          */
5538         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5539                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5540                         if (vcpu->arch.halt_request) {
5541                                 vcpu->arch.halt_request = 0;
5542                                 return kvm_vcpu_halt(vcpu);
5543                         }
5544                         return 1;
5545                 }
5546                 return 0;
5547         }
5548
5549         /*
5550          * Forward all other exceptions that are valid in real mode.
5551          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5552          *        the required debugging infrastructure rework.
5553          */
5554         kvm_queue_exception(vcpu, vec);
5555         return 1;
5556 }
5557
5558 /*
5559  * Trigger machine check on the host. We assume all the MSRs are already set up
5560  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5561  * We pass a fake environment to the machine check handler because we want
5562  * the guest to be always treated like user space, no matter what context
5563  * it used internally.
5564  */
5565 static void kvm_machine_check(void)
5566 {
5567 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5568         struct pt_regs regs = {
5569                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5570                 .flags = X86_EFLAGS_IF,
5571         };
5572
5573         do_machine_check(&regs, 0);
5574 #endif
5575 }
5576
5577 static int handle_machine_check(struct kvm_vcpu *vcpu)
5578 {
5579         /* already handled by vcpu_run */
5580         return 1;
5581 }
5582
5583 static int handle_exception(struct kvm_vcpu *vcpu)
5584 {
5585         struct vcpu_vmx *vmx = to_vmx(vcpu);
5586         struct kvm_run *kvm_run = vcpu->run;
5587         u32 intr_info, ex_no, error_code;
5588         unsigned long cr2, rip, dr6;
5589         u32 vect_info;
5590         enum emulation_result er;
5591
5592         vect_info = vmx->idt_vectoring_info;
5593         intr_info = vmx->exit_intr_info;
5594
5595         if (is_machine_check(intr_info))
5596                 return handle_machine_check(vcpu);
5597
5598         if (is_nmi(intr_info))
5599                 return 1;  /* already handled by vmx_vcpu_run() */
5600
5601         if (is_invalid_opcode(intr_info)) {
5602                 if (is_guest_mode(vcpu)) {
5603                         kvm_queue_exception(vcpu, UD_VECTOR);
5604                         return 1;
5605                 }
5606                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5607                 if (er != EMULATE_DONE)
5608                         kvm_queue_exception(vcpu, UD_VECTOR);
5609                 return 1;
5610         }
5611
5612         error_code = 0;
5613         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5614                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5615
5616         /*
5617          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5618          * MMIO, it is better to report an internal error.
5619          * See the comments in vmx_handle_exit.
5620          */
5621         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5622             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5623                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5624                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5625                 vcpu->run->internal.ndata = 3;
5626                 vcpu->run->internal.data[0] = vect_info;
5627                 vcpu->run->internal.data[1] = intr_info;
5628                 vcpu->run->internal.data[2] = error_code;
5629                 return 0;
5630         }
5631
5632         if (is_page_fault(intr_info)) {
5633                 /* EPT won't cause page fault directly */
5634                 BUG_ON(enable_ept);
5635                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5636                 trace_kvm_page_fault(cr2, error_code);
5637
5638                 if (kvm_event_needs_reinjection(vcpu))
5639                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5640                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5641         }
5642
5643         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5644
5645         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5646                 return handle_rmode_exception(vcpu, ex_no, error_code);
5647
5648         switch (ex_no) {
5649         case AC_VECTOR:
5650                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5651                 return 1;
5652         case DB_VECTOR:
5653                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5654                 if (!(vcpu->guest_debug &
5655                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5656                         vcpu->arch.dr6 &= ~15;
5657                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5658                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5659                                 skip_emulated_instruction(vcpu);
5660
5661                         kvm_queue_exception(vcpu, DB_VECTOR);
5662                         return 1;
5663                 }
5664                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5665                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5666                 /* fall through */
5667         case BP_VECTOR:
5668                 /*
5669                  * Update instruction length as we may reinject #BP from
5670                  * user space while in guest debugging mode. Reading it for
5671                  * #DB as well causes no harm, it is not used in that case.
5672                  */
5673                 vmx->vcpu.arch.event_exit_inst_len =
5674                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5675                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5676                 rip = kvm_rip_read(vcpu);
5677                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5678                 kvm_run->debug.arch.exception = ex_no;
5679                 break;
5680         default:
5681                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5682                 kvm_run->ex.exception = ex_no;
5683                 kvm_run->ex.error_code = error_code;
5684                 break;
5685         }
5686         return 0;
5687 }
5688
5689 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5690 {
5691         ++vcpu->stat.irq_exits;
5692         return 1;
5693 }
5694
5695 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5696 {
5697         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5698         return 0;
5699 }
5700
5701 static int handle_io(struct kvm_vcpu *vcpu)
5702 {
5703         unsigned long exit_qualification;
5704         int size, in, string, ret;
5705         unsigned port;
5706
5707         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5708         string = (exit_qualification & 16) != 0;
5709         in = (exit_qualification & 8) != 0;
5710
5711         ++vcpu->stat.io_exits;
5712
5713         if (string || in)
5714                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5715
5716         port = exit_qualification >> 16;
5717         size = (exit_qualification & 7) + 1;
5718
5719         ret = kvm_skip_emulated_instruction(vcpu);
5720
5721         /*
5722          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5723          * KVM_EXIT_DEBUG here.
5724          */
5725         return kvm_fast_pio_out(vcpu, size, port) && ret;
5726 }
5727
5728 static void
5729 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5730 {
5731         /*
5732          * Patch in the VMCALL instruction:
5733          */
5734         hypercall[0] = 0x0f;
5735         hypercall[1] = 0x01;
5736         hypercall[2] = 0xc1;
5737 }
5738
5739 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5740 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5741 {
5742         if (is_guest_mode(vcpu)) {
5743                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5744                 unsigned long orig_val = val;
5745
5746                 /*
5747                  * We get here when L2 changed cr0 in a way that did not change
5748                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5749                  * but did change L0 shadowed bits. So we first calculate the
5750                  * effective cr0 value that L1 would like to write into the
5751                  * hardware. It consists of the L2-owned bits from the new
5752                  * value combined with the L1-owned bits from L1's guest_cr0.
5753                  */
5754                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5755                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5756
5757                 if (!nested_guest_cr0_valid(vcpu, val))
5758                         return 1;
5759
5760                 if (kvm_set_cr0(vcpu, val))
5761                         return 1;
5762                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5763                 return 0;
5764         } else {
5765                 if (to_vmx(vcpu)->nested.vmxon &&
5766                     !nested_host_cr0_valid(vcpu, val))
5767                         return 1;
5768
5769                 return kvm_set_cr0(vcpu, val);
5770         }
5771 }
5772
5773 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5774 {
5775         if (is_guest_mode(vcpu)) {
5776                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5777                 unsigned long orig_val = val;
5778
5779                 /* analogously to handle_set_cr0 */
5780                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5781                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5782                 if (kvm_set_cr4(vcpu, val))
5783                         return 1;
5784                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5785                 return 0;
5786         } else
5787                 return kvm_set_cr4(vcpu, val);
5788 }
5789
5790 static int handle_cr(struct kvm_vcpu *vcpu)
5791 {
5792         unsigned long exit_qualification, val;
5793         int cr;
5794         int reg;
5795         int err;
5796         int ret;
5797
5798         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5799         cr = exit_qualification & 15;
5800         reg = (exit_qualification >> 8) & 15;
5801         switch ((exit_qualification >> 4) & 3) {
5802         case 0: /* mov to cr */
5803                 val = kvm_register_readl(vcpu, reg);
5804                 trace_kvm_cr_write(cr, val);
5805                 switch (cr) {
5806                 case 0:
5807                         err = handle_set_cr0(vcpu, val);
5808                         return kvm_complete_insn_gp(vcpu, err);
5809                 case 3:
5810                         err = kvm_set_cr3(vcpu, val);
5811                         return kvm_complete_insn_gp(vcpu, err);
5812                 case 4:
5813                         err = handle_set_cr4(vcpu, val);
5814                         return kvm_complete_insn_gp(vcpu, err);
5815                 case 8: {
5816                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5817                                 u8 cr8 = (u8)val;
5818                                 err = kvm_set_cr8(vcpu, cr8);
5819                                 ret = kvm_complete_insn_gp(vcpu, err);
5820                                 if (lapic_in_kernel(vcpu))
5821                                         return ret;
5822                                 if (cr8_prev <= cr8)
5823                                         return ret;
5824                                 /*
5825                                  * TODO: we might be squashing a
5826                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5827                                  * KVM_EXIT_DEBUG here.
5828                                  */
5829                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5830                                 return 0;
5831                         }
5832                 }
5833                 break;
5834         case 2: /* clts */
5835                 WARN_ONCE(1, "Guest should always own CR0.TS");
5836                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5837                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5838                 return kvm_skip_emulated_instruction(vcpu);
5839         case 1: /*mov from cr*/
5840                 switch (cr) {
5841                 case 3:
5842                         val = kvm_read_cr3(vcpu);
5843                         kvm_register_write(vcpu, reg, val);
5844                         trace_kvm_cr_read(cr, val);
5845                         return kvm_skip_emulated_instruction(vcpu);
5846                 case 8:
5847                         val = kvm_get_cr8(vcpu);
5848                         kvm_register_write(vcpu, reg, val);
5849                         trace_kvm_cr_read(cr, val);
5850                         return kvm_skip_emulated_instruction(vcpu);
5851                 }
5852                 break;
5853         case 3: /* lmsw */
5854                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5855                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5856                 kvm_lmsw(vcpu, val);
5857
5858                 return kvm_skip_emulated_instruction(vcpu);
5859         default:
5860                 break;
5861         }
5862         vcpu->run->exit_reason = 0;
5863         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5864                (int)(exit_qualification >> 4) & 3, cr);
5865         return 0;
5866 }
5867
5868 static int handle_dr(struct kvm_vcpu *vcpu)
5869 {
5870         unsigned long exit_qualification;
5871         int dr, dr7, reg;
5872
5873         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5874         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5875
5876         /* First, if DR does not exist, trigger UD */
5877         if (!kvm_require_dr(vcpu, dr))
5878                 return 1;
5879
5880         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5881         if (!kvm_require_cpl(vcpu, 0))
5882                 return 1;
5883         dr7 = vmcs_readl(GUEST_DR7);
5884         if (dr7 & DR7_GD) {
5885                 /*
5886                  * As the vm-exit takes precedence over the debug trap, we
5887                  * need to emulate the latter, either for the host or the
5888                  * guest debugging itself.
5889                  */
5890                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5891                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5892                         vcpu->run->debug.arch.dr7 = dr7;
5893                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5894                         vcpu->run->debug.arch.exception = DB_VECTOR;
5895                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5896                         return 0;
5897                 } else {
5898                         vcpu->arch.dr6 &= ~15;
5899                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5900                         kvm_queue_exception(vcpu, DB_VECTOR);
5901                         return 1;
5902                 }
5903         }
5904
5905         if (vcpu->guest_debug == 0) {
5906                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5907                                 CPU_BASED_MOV_DR_EXITING);
5908
5909                 /*
5910                  * No more DR vmexits; force a reload of the debug registers
5911                  * and reenter on this instruction.  The next vmexit will
5912                  * retrieve the full state of the debug registers.
5913                  */
5914                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5915                 return 1;
5916         }
5917
5918         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5919         if (exit_qualification & TYPE_MOV_FROM_DR) {
5920                 unsigned long val;
5921
5922                 if (kvm_get_dr(vcpu, dr, &val))
5923                         return 1;
5924                 kvm_register_write(vcpu, reg, val);
5925         } else
5926                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5927                         return 1;
5928
5929         return kvm_skip_emulated_instruction(vcpu);
5930 }
5931
5932 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5933 {
5934         return vcpu->arch.dr6;
5935 }
5936
5937 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5938 {
5939 }
5940
5941 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5942 {
5943         get_debugreg(vcpu->arch.db[0], 0);
5944         get_debugreg(vcpu->arch.db[1], 1);
5945         get_debugreg(vcpu->arch.db[2], 2);
5946         get_debugreg(vcpu->arch.db[3], 3);
5947         get_debugreg(vcpu->arch.dr6, 6);
5948         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5949
5950         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5951         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5952 }
5953
5954 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5955 {
5956         vmcs_writel(GUEST_DR7, val);
5957 }
5958
5959 static int handle_cpuid(struct kvm_vcpu *vcpu)
5960 {
5961         return kvm_emulate_cpuid(vcpu);
5962 }
5963
5964 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5965 {
5966         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5967         struct msr_data msr_info;
5968
5969         msr_info.index = ecx;
5970         msr_info.host_initiated = false;
5971         if (vmx_get_msr(vcpu, &msr_info)) {
5972                 trace_kvm_msr_read_ex(ecx);
5973                 kvm_inject_gp(vcpu, 0);
5974                 return 1;
5975         }
5976
5977         trace_kvm_msr_read(ecx, msr_info.data);
5978
5979         /* FIXME: handling of bits 32:63 of rax, rdx */
5980         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5981         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5982         return kvm_skip_emulated_instruction(vcpu);
5983 }
5984
5985 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5986 {
5987         struct msr_data msr;
5988         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5989         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5990                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5991
5992         msr.data = data;
5993         msr.index = ecx;
5994         msr.host_initiated = false;
5995         if (kvm_set_msr(vcpu, &msr) != 0) {
5996                 trace_kvm_msr_write_ex(ecx, data);
5997                 kvm_inject_gp(vcpu, 0);
5998                 return 1;
5999         }
6000
6001         trace_kvm_msr_write(ecx, data);
6002         return kvm_skip_emulated_instruction(vcpu);
6003 }
6004
6005 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6006 {
6007         kvm_apic_update_ppr(vcpu);
6008         return 1;
6009 }
6010
6011 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6012 {
6013         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6014                         CPU_BASED_VIRTUAL_INTR_PENDING);
6015
6016         kvm_make_request(KVM_REQ_EVENT, vcpu);
6017
6018         ++vcpu->stat.irq_window_exits;
6019         return 1;
6020 }
6021
6022 static int handle_halt(struct kvm_vcpu *vcpu)
6023 {
6024         return kvm_emulate_halt(vcpu);
6025 }
6026
6027 static int handle_vmcall(struct kvm_vcpu *vcpu)
6028 {
6029         return kvm_emulate_hypercall(vcpu);
6030 }
6031
6032 static int handle_invd(struct kvm_vcpu *vcpu)
6033 {
6034         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6035 }
6036
6037 static int handle_invlpg(struct kvm_vcpu *vcpu)
6038 {
6039         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6040
6041         kvm_mmu_invlpg(vcpu, exit_qualification);
6042         return kvm_skip_emulated_instruction(vcpu);
6043 }
6044
6045 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6046 {
6047         int err;
6048
6049         err = kvm_rdpmc(vcpu);
6050         return kvm_complete_insn_gp(vcpu, err);
6051 }
6052
6053 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6054 {
6055         return kvm_emulate_wbinvd(vcpu);
6056 }
6057
6058 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6059 {
6060         u64 new_bv = kvm_read_edx_eax(vcpu);
6061         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6062
6063         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6064                 return kvm_skip_emulated_instruction(vcpu);
6065         return 1;
6066 }
6067
6068 static int handle_xsaves(struct kvm_vcpu *vcpu)
6069 {
6070         kvm_skip_emulated_instruction(vcpu);
6071         WARN(1, "this should never happen\n");
6072         return 1;
6073 }
6074
6075 static int handle_xrstors(struct kvm_vcpu *vcpu)
6076 {
6077         kvm_skip_emulated_instruction(vcpu);
6078         WARN(1, "this should never happen\n");
6079         return 1;
6080 }
6081
6082 static int handle_apic_access(struct kvm_vcpu *vcpu)
6083 {
6084         if (likely(fasteoi)) {
6085                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6086                 int access_type, offset;
6087
6088                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6089                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6090                 /*
6091                  * Sane guest uses MOV to write EOI, with written value
6092                  * not cared. So make a short-circuit here by avoiding
6093                  * heavy instruction emulation.
6094                  */
6095                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6096                     (offset == APIC_EOI)) {
6097                         kvm_lapic_set_eoi(vcpu);
6098                         return kvm_skip_emulated_instruction(vcpu);
6099                 }
6100         }
6101         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6102 }
6103
6104 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6105 {
6106         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6107         int vector = exit_qualification & 0xff;
6108
6109         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6110         kvm_apic_set_eoi_accelerated(vcpu, vector);
6111         return 1;
6112 }
6113
6114 static int handle_apic_write(struct kvm_vcpu *vcpu)
6115 {
6116         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6117         u32 offset = exit_qualification & 0xfff;
6118
6119         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6120         kvm_apic_write_nodecode(vcpu, offset);
6121         return 1;
6122 }
6123
6124 static int handle_task_switch(struct kvm_vcpu *vcpu)
6125 {
6126         struct vcpu_vmx *vmx = to_vmx(vcpu);
6127         unsigned long exit_qualification;
6128         bool has_error_code = false;
6129         u32 error_code = 0;
6130         u16 tss_selector;
6131         int reason, type, idt_v, idt_index;
6132
6133         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6134         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6135         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6136
6137         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6138
6139         reason = (u32)exit_qualification >> 30;
6140         if (reason == TASK_SWITCH_GATE && idt_v) {
6141                 switch (type) {
6142                 case INTR_TYPE_NMI_INTR:
6143                         vcpu->arch.nmi_injected = false;
6144                         vmx_set_nmi_mask(vcpu, true);
6145                         break;
6146                 case INTR_TYPE_EXT_INTR:
6147                 case INTR_TYPE_SOFT_INTR:
6148                         kvm_clear_interrupt_queue(vcpu);
6149                         break;
6150                 case INTR_TYPE_HARD_EXCEPTION:
6151                         if (vmx->idt_vectoring_info &
6152                             VECTORING_INFO_DELIVER_CODE_MASK) {
6153                                 has_error_code = true;
6154                                 error_code =
6155                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6156                         }
6157                         /* fall through */
6158                 case INTR_TYPE_SOFT_EXCEPTION:
6159                         kvm_clear_exception_queue(vcpu);
6160                         break;
6161                 default:
6162                         break;
6163                 }
6164         }
6165         tss_selector = exit_qualification;
6166
6167         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6168                        type != INTR_TYPE_EXT_INTR &&
6169                        type != INTR_TYPE_NMI_INTR))
6170                 skip_emulated_instruction(vcpu);
6171
6172         if (kvm_task_switch(vcpu, tss_selector,
6173                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6174                             has_error_code, error_code) == EMULATE_FAIL) {
6175                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6176                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6177                 vcpu->run->internal.ndata = 0;
6178                 return 0;
6179         }
6180
6181         /*
6182          * TODO: What about debug traps on tss switch?
6183          *       Are we supposed to inject them and update dr6?
6184          */
6185
6186         return 1;
6187 }
6188
6189 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6190 {
6191         unsigned long exit_qualification;
6192         gpa_t gpa;
6193         u32 error_code;
6194
6195         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6196
6197         if (is_guest_mode(vcpu)
6198             && !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
6199                 /*
6200                  * Fix up exit_qualification according to whether guest
6201                  * page table accesses are reads or writes.
6202                  */
6203                 u64 eptp = nested_ept_get_cr3(vcpu);
6204                 if (!(eptp & VMX_EPT_AD_ENABLE_BIT))
6205                         exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
6206         }
6207
6208         /*
6209          * EPT violation happened while executing iret from NMI,
6210          * "blocked by NMI" bit has to be set before next VM entry.
6211          * There are errata that may cause this bit to not be set:
6212          * AAK134, BY25.
6213          */
6214         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6215                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6216                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6217
6218         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6219         trace_kvm_page_fault(gpa, exit_qualification);
6220
6221         /* Is it a read fault? */
6222         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6223                      ? PFERR_USER_MASK : 0;
6224         /* Is it a write fault? */
6225         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6226                       ? PFERR_WRITE_MASK : 0;
6227         /* Is it a fetch fault? */
6228         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6229                       ? PFERR_FETCH_MASK : 0;
6230         /* ept page table entry is present? */
6231         error_code |= (exit_qualification &
6232                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6233                         EPT_VIOLATION_EXECUTABLE))
6234                       ? PFERR_PRESENT_MASK : 0;
6235
6236         vcpu->arch.gpa_available = true;
6237         vcpu->arch.exit_qualification = exit_qualification;
6238
6239         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6240 }
6241
6242 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6243 {
6244         int ret;
6245         gpa_t gpa;
6246
6247         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6248         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6249                 trace_kvm_fast_mmio(gpa);
6250                 return kvm_skip_emulated_instruction(vcpu);
6251         }
6252
6253         ret = handle_mmio_page_fault(vcpu, gpa, true);
6254         vcpu->arch.gpa_available = true;
6255         if (likely(ret == RET_MMIO_PF_EMULATE))
6256                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6257                                               EMULATE_DONE;
6258
6259         if (unlikely(ret == RET_MMIO_PF_INVALID))
6260                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6261
6262         if (unlikely(ret == RET_MMIO_PF_RETRY))
6263                 return 1;
6264
6265         /* It is the real ept misconfig */
6266         WARN_ON(1);
6267
6268         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6269         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6270
6271         return 0;
6272 }
6273
6274 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6275 {
6276         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6277                         CPU_BASED_VIRTUAL_NMI_PENDING);
6278         ++vcpu->stat.nmi_window_exits;
6279         kvm_make_request(KVM_REQ_EVENT, vcpu);
6280
6281         return 1;
6282 }
6283
6284 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6285 {
6286         struct vcpu_vmx *vmx = to_vmx(vcpu);
6287         enum emulation_result err = EMULATE_DONE;
6288         int ret = 1;
6289         u32 cpu_exec_ctrl;
6290         bool intr_window_requested;
6291         unsigned count = 130;
6292
6293         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6294         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6295
6296         while (vmx->emulation_required && count-- != 0) {
6297                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6298                         return handle_interrupt_window(&vmx->vcpu);
6299
6300                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6301                         return 1;
6302
6303                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6304
6305                 if (err == EMULATE_USER_EXIT) {
6306                         ++vcpu->stat.mmio_exits;
6307                         ret = 0;
6308                         goto out;
6309                 }
6310
6311                 if (err != EMULATE_DONE) {
6312                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6313                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6314                         vcpu->run->internal.ndata = 0;
6315                         return 0;
6316                 }
6317
6318                 if (vcpu->arch.halt_request) {
6319                         vcpu->arch.halt_request = 0;
6320                         ret = kvm_vcpu_halt(vcpu);
6321                         goto out;
6322                 }
6323
6324                 if (signal_pending(current))
6325                         goto out;
6326                 if (need_resched())
6327                         schedule();
6328         }
6329
6330 out:
6331         return ret;
6332 }
6333
6334 static int __grow_ple_window(int val)
6335 {
6336         if (ple_window_grow < 1)
6337                 return ple_window;
6338
6339         val = min(val, ple_window_actual_max);
6340
6341         if (ple_window_grow < ple_window)
6342                 val *= ple_window_grow;
6343         else
6344                 val += ple_window_grow;
6345
6346         return val;
6347 }
6348
6349 static int __shrink_ple_window(int val, int modifier, int minimum)
6350 {
6351         if (modifier < 1)
6352                 return ple_window;
6353
6354         if (modifier < ple_window)
6355                 val /= modifier;
6356         else
6357                 val -= modifier;
6358
6359         return max(val, minimum);
6360 }
6361
6362 static void grow_ple_window(struct kvm_vcpu *vcpu)
6363 {
6364         struct vcpu_vmx *vmx = to_vmx(vcpu);
6365         int old = vmx->ple_window;
6366
6367         vmx->ple_window = __grow_ple_window(old);
6368
6369         if (vmx->ple_window != old)
6370                 vmx->ple_window_dirty = true;
6371
6372         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6373 }
6374
6375 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6376 {
6377         struct vcpu_vmx *vmx = to_vmx(vcpu);
6378         int old = vmx->ple_window;
6379
6380         vmx->ple_window = __shrink_ple_window(old,
6381                                               ple_window_shrink, ple_window);
6382
6383         if (vmx->ple_window != old)
6384                 vmx->ple_window_dirty = true;
6385
6386         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6387 }
6388
6389 /*
6390  * ple_window_actual_max is computed to be one grow_ple_window() below
6391  * ple_window_max. (See __grow_ple_window for the reason.)
6392  * This prevents overflows, because ple_window_max is int.
6393  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6394  * this process.
6395  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6396  */
6397 static void update_ple_window_actual_max(void)
6398 {
6399         ple_window_actual_max =
6400                         __shrink_ple_window(max(ple_window_max, ple_window),
6401                                             ple_window_grow, INT_MIN);
6402 }
6403
6404 /*
6405  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6406  */
6407 static void wakeup_handler(void)
6408 {
6409         struct kvm_vcpu *vcpu;
6410         int cpu = smp_processor_id();
6411
6412         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6413         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6414                         blocked_vcpu_list) {
6415                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6416
6417                 if (pi_test_on(pi_desc) == 1)
6418                         kvm_vcpu_kick(vcpu);
6419         }
6420         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6421 }
6422
6423 void vmx_enable_tdp(void)
6424 {
6425         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6426                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6427                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6428                 0ull, VMX_EPT_EXECUTABLE_MASK,
6429                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6430                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6431
6432         ept_set_mmio_spte_mask();
6433         kvm_enable_tdp();
6434 }
6435
6436 static __init int hardware_setup(void)
6437 {
6438         int r = -ENOMEM, i, msr;
6439
6440         rdmsrl_safe(MSR_EFER, &host_efer);
6441
6442         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6443                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6444
6445         for (i = 0; i < VMX_BITMAP_NR; i++) {
6446                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6447                 if (!vmx_bitmap[i])
6448                         goto out;
6449         }
6450
6451         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6452         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6453         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6454
6455         /*
6456          * Allow direct access to the PC debug port (it is often used for I/O
6457          * delays, but the vmexits simply slow things down).
6458          */
6459         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6460         clear_bit(0x80, vmx_io_bitmap_a);
6461
6462         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6463
6464         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6465         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6466
6467         if (setup_vmcs_config(&vmcs_config) < 0) {
6468                 r = -EIO;
6469                 goto out;
6470         }
6471
6472         if (boot_cpu_has(X86_FEATURE_NX))
6473                 kvm_enable_efer_bits(EFER_NX);
6474
6475         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6476                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6477                 enable_vpid = 0;
6478
6479         if (!cpu_has_vmx_shadow_vmcs())
6480                 enable_shadow_vmcs = 0;
6481         if (enable_shadow_vmcs)
6482                 init_vmcs_shadow_fields();
6483
6484         if (!cpu_has_vmx_ept() ||
6485             !cpu_has_vmx_ept_4levels()) {
6486                 enable_ept = 0;
6487                 enable_unrestricted_guest = 0;
6488                 enable_ept_ad_bits = 0;
6489         }
6490
6491         if (!cpu_has_vmx_ept_ad_bits())
6492                 enable_ept_ad_bits = 0;
6493
6494         if (!cpu_has_vmx_unrestricted_guest())
6495                 enable_unrestricted_guest = 0;
6496
6497         if (!cpu_has_vmx_flexpriority())
6498                 flexpriority_enabled = 0;
6499
6500         /*
6501          * set_apic_access_page_addr() is used to reload apic access
6502          * page upon invalidation.  No need to do anything if not
6503          * using the APIC_ACCESS_ADDR VMCS field.
6504          */
6505         if (!flexpriority_enabled)
6506                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6507
6508         if (!cpu_has_vmx_tpr_shadow())
6509                 kvm_x86_ops->update_cr8_intercept = NULL;
6510
6511         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6512                 kvm_disable_largepages();
6513
6514         if (!cpu_has_vmx_ple())
6515                 ple_gap = 0;
6516
6517         if (!cpu_has_vmx_apicv()) {
6518                 enable_apicv = 0;
6519                 kvm_x86_ops->sync_pir_to_irr = NULL;
6520         }
6521
6522         if (cpu_has_vmx_tsc_scaling()) {
6523                 kvm_has_tsc_control = true;
6524                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6525                 kvm_tsc_scaling_ratio_frac_bits = 48;
6526         }
6527
6528         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6529         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6530         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6531         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6532         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6533         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6534         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6535
6536         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6537                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6538         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6539                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6540         memcpy(vmx_msr_bitmap_legacy_x2apic,
6541                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6542         memcpy(vmx_msr_bitmap_longmode_x2apic,
6543                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6544
6545         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6546
6547         for (msr = 0x800; msr <= 0x8ff; msr++) {
6548                 if (msr == 0x839 /* TMCCT */)
6549                         continue;
6550                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6551         }
6552
6553         /*
6554          * TPR reads and writes can be virtualized even if virtual interrupt
6555          * delivery is not in use.
6556          */
6557         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6558         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6559
6560         /* EOI */
6561         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6562         /* SELF-IPI */
6563         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6564
6565         if (enable_ept)
6566                 vmx_enable_tdp();
6567         else
6568                 kvm_disable_tdp();
6569
6570         update_ple_window_actual_max();
6571
6572         /*
6573          * Only enable PML when hardware supports PML feature, and both EPT
6574          * and EPT A/D bit features are enabled -- PML depends on them to work.
6575          */
6576         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6577                 enable_pml = 0;
6578
6579         if (!enable_pml) {
6580                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6581                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6582                 kvm_x86_ops->flush_log_dirty = NULL;
6583                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6584         }
6585
6586         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6587                 u64 vmx_msr;
6588
6589                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6590                 cpu_preemption_timer_multi =
6591                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6592         } else {
6593                 kvm_x86_ops->set_hv_timer = NULL;
6594                 kvm_x86_ops->cancel_hv_timer = NULL;
6595         }
6596
6597         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6598
6599         kvm_mce_cap_supported |= MCG_LMCE_P;
6600
6601         return alloc_kvm_area();
6602
6603 out:
6604         for (i = 0; i < VMX_BITMAP_NR; i++)
6605                 free_page((unsigned long)vmx_bitmap[i]);
6606
6607     return r;
6608 }
6609
6610 static __exit void hardware_unsetup(void)
6611 {
6612         int i;
6613
6614         for (i = 0; i < VMX_BITMAP_NR; i++)
6615                 free_page((unsigned long)vmx_bitmap[i]);
6616
6617         free_kvm_area();
6618 }
6619
6620 /*
6621  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6622  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6623  */
6624 static int handle_pause(struct kvm_vcpu *vcpu)
6625 {
6626         if (ple_gap)
6627                 grow_ple_window(vcpu);
6628
6629         kvm_vcpu_on_spin(vcpu);
6630         return kvm_skip_emulated_instruction(vcpu);
6631 }
6632
6633 static int handle_nop(struct kvm_vcpu *vcpu)
6634 {
6635         return kvm_skip_emulated_instruction(vcpu);
6636 }
6637
6638 static int handle_mwait(struct kvm_vcpu *vcpu)
6639 {
6640         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6641         return handle_nop(vcpu);
6642 }
6643
6644 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6645 {
6646         return 1;
6647 }
6648
6649 static int handle_monitor(struct kvm_vcpu *vcpu)
6650 {
6651         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6652         return handle_nop(vcpu);
6653 }
6654
6655 /*
6656  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6657  * We could reuse a single VMCS for all the L2 guests, but we also want the
6658  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6659  * allows keeping them loaded on the processor, and in the future will allow
6660  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6661  * every entry if they never change.
6662  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6663  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6664  *
6665  * The following functions allocate and free a vmcs02 in this pool.
6666  */
6667
6668 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6669 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6670 {
6671         struct vmcs02_list *item;
6672         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6673                 if (item->vmptr == vmx->nested.current_vmptr) {
6674                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6675                         return &item->vmcs02;
6676                 }
6677
6678         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6679                 /* Recycle the least recently used VMCS. */
6680                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6681                                        struct vmcs02_list, list);
6682                 item->vmptr = vmx->nested.current_vmptr;
6683                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6684                 return &item->vmcs02;
6685         }
6686
6687         /* Create a new VMCS */
6688         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6689         if (!item)
6690                 return NULL;
6691         item->vmcs02.vmcs = alloc_vmcs();
6692         item->vmcs02.shadow_vmcs = NULL;
6693         if (!item->vmcs02.vmcs) {
6694                 kfree(item);
6695                 return NULL;
6696         }
6697         loaded_vmcs_init(&item->vmcs02);
6698         item->vmptr = vmx->nested.current_vmptr;
6699         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6700         vmx->nested.vmcs02_num++;
6701         return &item->vmcs02;
6702 }
6703
6704 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6705 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6706 {
6707         struct vmcs02_list *item;
6708         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6709                 if (item->vmptr == vmptr) {
6710                         free_loaded_vmcs(&item->vmcs02);
6711                         list_del(&item->list);
6712                         kfree(item);
6713                         vmx->nested.vmcs02_num--;
6714                         return;
6715                 }
6716 }
6717
6718 /*
6719  * Free all VMCSs saved for this vcpu, except the one pointed by
6720  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6721  * must be &vmx->vmcs01.
6722  */
6723 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6724 {
6725         struct vmcs02_list *item, *n;
6726
6727         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6728         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6729                 /*
6730                  * Something will leak if the above WARN triggers.  Better than
6731                  * a use-after-free.
6732                  */
6733                 if (vmx->loaded_vmcs == &item->vmcs02)
6734                         continue;
6735
6736                 free_loaded_vmcs(&item->vmcs02);
6737                 list_del(&item->list);
6738                 kfree(item);
6739                 vmx->nested.vmcs02_num--;
6740         }
6741 }
6742
6743 /*
6744  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6745  * set the success or error code of an emulated VMX instruction, as specified
6746  * by Vol 2B, VMX Instruction Reference, "Conventions".
6747  */
6748 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6749 {
6750         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6751                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6752                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6753 }
6754
6755 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6756 {
6757         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6758                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6759                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6760                         | X86_EFLAGS_CF);
6761 }
6762
6763 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6764                                         u32 vm_instruction_error)
6765 {
6766         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6767                 /*
6768                  * failValid writes the error number to the current VMCS, which
6769                  * can't be done there isn't a current VMCS.
6770                  */
6771                 nested_vmx_failInvalid(vcpu);
6772                 return;
6773         }
6774         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6775                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6776                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6777                         | X86_EFLAGS_ZF);
6778         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6779         /*
6780          * We don't need to force a shadow sync because
6781          * VM_INSTRUCTION_ERROR is not shadowed
6782          */
6783 }
6784
6785 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6786 {
6787         /* TODO: not to reset guest simply here. */
6788         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6789         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6790 }
6791
6792 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6793 {
6794         struct vcpu_vmx *vmx =
6795                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6796
6797         vmx->nested.preemption_timer_expired = true;
6798         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6799         kvm_vcpu_kick(&vmx->vcpu);
6800
6801         return HRTIMER_NORESTART;
6802 }
6803
6804 /*
6805  * Decode the memory-address operand of a vmx instruction, as recorded on an
6806  * exit caused by such an instruction (run by a guest hypervisor).
6807  * On success, returns 0. When the operand is invalid, returns 1 and throws
6808  * #UD or #GP.
6809  */
6810 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6811                                  unsigned long exit_qualification,
6812                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6813 {
6814         gva_t off;
6815         bool exn;
6816         struct kvm_segment s;
6817
6818         /*
6819          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6820          * Execution", on an exit, vmx_instruction_info holds most of the
6821          * addressing components of the operand. Only the displacement part
6822          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6823          * For how an actual address is calculated from all these components,
6824          * refer to Vol. 1, "Operand Addressing".
6825          */
6826         int  scaling = vmx_instruction_info & 3;
6827         int  addr_size = (vmx_instruction_info >> 7) & 7;
6828         bool is_reg = vmx_instruction_info & (1u << 10);
6829         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6830         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6831         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6832         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6833         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6834
6835         if (is_reg) {
6836                 kvm_queue_exception(vcpu, UD_VECTOR);
6837                 return 1;
6838         }
6839
6840         /* Addr = segment_base + offset */
6841         /* offset = base + [index * scale] + displacement */
6842         off = exit_qualification; /* holds the displacement */
6843         if (base_is_valid)
6844                 off += kvm_register_read(vcpu, base_reg);
6845         if (index_is_valid)
6846                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6847         vmx_get_segment(vcpu, &s, seg_reg);
6848         *ret = s.base + off;
6849
6850         if (addr_size == 1) /* 32 bit */
6851                 *ret &= 0xffffffff;
6852
6853         /* Checks for #GP/#SS exceptions. */
6854         exn = false;
6855         if (is_long_mode(vcpu)) {
6856                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6857                  * non-canonical form. This is the only check on the memory
6858                  * destination for long mode!
6859                  */
6860                 exn = is_noncanonical_address(*ret);
6861         } else if (is_protmode(vcpu)) {
6862                 /* Protected mode: apply checks for segment validity in the
6863                  * following order:
6864                  * - segment type check (#GP(0) may be thrown)
6865                  * - usability check (#GP(0)/#SS(0))
6866                  * - limit check (#GP(0)/#SS(0))
6867                  */
6868                 if (wr)
6869                         /* #GP(0) if the destination operand is located in a
6870                          * read-only data segment or any code segment.
6871                          */
6872                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6873                 else
6874                         /* #GP(0) if the source operand is located in an
6875                          * execute-only code segment
6876                          */
6877                         exn = ((s.type & 0xa) == 8);
6878                 if (exn) {
6879                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6880                         return 1;
6881                 }
6882                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6883                  */
6884                 exn = (s.unusable != 0);
6885                 /* Protected mode: #GP(0)/#SS(0) if the memory
6886                  * operand is outside the segment limit.
6887                  */
6888                 exn = exn || (off + sizeof(u64) > s.limit);
6889         }
6890         if (exn) {
6891                 kvm_queue_exception_e(vcpu,
6892                                       seg_reg == VCPU_SREG_SS ?
6893                                                 SS_VECTOR : GP_VECTOR,
6894                                       0);
6895                 return 1;
6896         }
6897
6898         return 0;
6899 }
6900
6901 /*
6902  * This function performs the various checks including
6903  * - if it's 4KB aligned
6904  * - No bits beyond the physical address width are set
6905  * - Returns 0 on success or else 1
6906  * (Intel SDM Section 30.3)
6907  */
6908 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6909                                   gpa_t *vmpointer)
6910 {
6911         gva_t gva;
6912         gpa_t vmptr;
6913         struct x86_exception e;
6914         struct page *page;
6915         struct vcpu_vmx *vmx = to_vmx(vcpu);
6916         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6917
6918         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6919                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6920                 return 1;
6921
6922         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6923                                 sizeof(vmptr), &e)) {
6924                 kvm_inject_page_fault(vcpu, &e);
6925                 return 1;
6926         }
6927
6928         switch (exit_reason) {
6929         case EXIT_REASON_VMON:
6930                 /*
6931                  * SDM 3: 24.11.5
6932                  * The first 4 bytes of VMXON region contain the supported
6933                  * VMCS revision identifier
6934                  *
6935                  * Note - IA32_VMX_BASIC[48] will never be 1
6936                  * for the nested case;
6937                  * which replaces physical address width with 32
6938                  *
6939                  */
6940                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6941                         nested_vmx_failInvalid(vcpu);
6942                         return kvm_skip_emulated_instruction(vcpu);
6943                 }
6944
6945                 page = nested_get_page(vcpu, vmptr);
6946                 if (page == NULL) {
6947                         nested_vmx_failInvalid(vcpu);
6948                         return kvm_skip_emulated_instruction(vcpu);
6949                 }
6950                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6951                         kunmap(page);
6952                         nested_release_page_clean(page);
6953                         nested_vmx_failInvalid(vcpu);
6954                         return kvm_skip_emulated_instruction(vcpu);
6955                 }
6956                 kunmap(page);
6957                 nested_release_page_clean(page);
6958                 vmx->nested.vmxon_ptr = vmptr;
6959                 break;
6960         case EXIT_REASON_VMCLEAR:
6961                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6962                         nested_vmx_failValid(vcpu,
6963                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6964                         return kvm_skip_emulated_instruction(vcpu);
6965                 }
6966
6967                 if (vmptr == vmx->nested.vmxon_ptr) {
6968                         nested_vmx_failValid(vcpu,
6969                                              VMXERR_VMCLEAR_VMXON_POINTER);
6970                         return kvm_skip_emulated_instruction(vcpu);
6971                 }
6972                 break;
6973         case EXIT_REASON_VMPTRLD:
6974                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6975                         nested_vmx_failValid(vcpu,
6976                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6977                         return kvm_skip_emulated_instruction(vcpu);
6978                 }
6979
6980                 if (vmptr == vmx->nested.vmxon_ptr) {
6981                         nested_vmx_failValid(vcpu,
6982                                              VMXERR_VMPTRLD_VMXON_POINTER);
6983                         return kvm_skip_emulated_instruction(vcpu);
6984                 }
6985                 break;
6986         default:
6987                 return 1; /* shouldn't happen */
6988         }
6989
6990         if (vmpointer)
6991                 *vmpointer = vmptr;
6992         return 0;
6993 }
6994
6995 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6996 {
6997         struct vcpu_vmx *vmx = to_vmx(vcpu);
6998         struct vmcs *shadow_vmcs;
6999
7000         if (cpu_has_vmx_msr_bitmap()) {
7001                 vmx->nested.msr_bitmap =
7002                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7003                 if (!vmx->nested.msr_bitmap)
7004                         goto out_msr_bitmap;
7005         }
7006
7007         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7008         if (!vmx->nested.cached_vmcs12)
7009                 goto out_cached_vmcs12;
7010
7011         if (enable_shadow_vmcs) {
7012                 shadow_vmcs = alloc_vmcs();
7013                 if (!shadow_vmcs)
7014                         goto out_shadow_vmcs;
7015                 /* mark vmcs as shadow */
7016                 shadow_vmcs->revision_id |= (1u << 31);
7017                 /* init shadow vmcs */
7018                 vmcs_clear(shadow_vmcs);
7019                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7020         }
7021
7022         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7023         vmx->nested.vmcs02_num = 0;
7024
7025         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7026                      HRTIMER_MODE_REL_PINNED);
7027         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7028
7029         vmx->nested.vmxon = true;
7030         return 0;
7031
7032 out_shadow_vmcs:
7033         kfree(vmx->nested.cached_vmcs12);
7034
7035 out_cached_vmcs12:
7036         free_page((unsigned long)vmx->nested.msr_bitmap);
7037
7038 out_msr_bitmap:
7039         return -ENOMEM;
7040 }
7041
7042 /*
7043  * Emulate the VMXON instruction.
7044  * Currently, we just remember that VMX is active, and do not save or even
7045  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7046  * do not currently need to store anything in that guest-allocated memory
7047  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7048  * argument is different from the VMXON pointer (which the spec says they do).
7049  */
7050 static int handle_vmon(struct kvm_vcpu *vcpu)
7051 {
7052         int ret;
7053         struct kvm_segment cs;
7054         struct vcpu_vmx *vmx = to_vmx(vcpu);
7055         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7056                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7057
7058         /* The Intel VMX Instruction Reference lists a bunch of bits that
7059          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7060          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7061          * Otherwise, we should fail with #UD. We test these now:
7062          */
7063         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7064             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7065             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7066                 kvm_queue_exception(vcpu, UD_VECTOR);
7067                 return 1;
7068         }
7069
7070         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7071         if (is_long_mode(vcpu) && !cs.l) {
7072                 kvm_queue_exception(vcpu, UD_VECTOR);
7073                 return 1;
7074         }
7075
7076         if (vmx_get_cpl(vcpu)) {
7077                 kvm_inject_gp(vcpu, 0);
7078                 return 1;
7079         }
7080
7081         if (vmx->nested.vmxon) {
7082                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7083                 return kvm_skip_emulated_instruction(vcpu);
7084         }
7085
7086         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7087                         != VMXON_NEEDED_FEATURES) {
7088                 kvm_inject_gp(vcpu, 0);
7089                 return 1;
7090         }
7091
7092         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7093                 return 1;
7094
7095         ret = enter_vmx_operation(vcpu);
7096         if (ret)
7097                 return ret;
7098
7099         nested_vmx_succeed(vcpu);
7100         return kvm_skip_emulated_instruction(vcpu);
7101 }
7102
7103 /*
7104  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7105  * for running VMX instructions (except VMXON, whose prerequisites are
7106  * slightly different). It also specifies what exception to inject otherwise.
7107  */
7108 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7109 {
7110         struct kvm_segment cs;
7111         struct vcpu_vmx *vmx = to_vmx(vcpu);
7112
7113         if (!vmx->nested.vmxon) {
7114                 kvm_queue_exception(vcpu, UD_VECTOR);
7115                 return 0;
7116         }
7117
7118         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7119         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7120             (is_long_mode(vcpu) && !cs.l)) {
7121                 kvm_queue_exception(vcpu, UD_VECTOR);
7122                 return 0;
7123         }
7124
7125         if (vmx_get_cpl(vcpu)) {
7126                 kvm_inject_gp(vcpu, 0);
7127                 return 0;
7128         }
7129
7130         return 1;
7131 }
7132
7133 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7134 {
7135         if (vmx->nested.current_vmptr == -1ull)
7136                 return;
7137
7138         /* current_vmptr and current_vmcs12 are always set/reset together */
7139         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7140                 return;
7141
7142         if (enable_shadow_vmcs) {
7143                 /* copy to memory all shadowed fields in case
7144                    they were modified */
7145                 copy_shadow_to_vmcs12(vmx);
7146                 vmx->nested.sync_shadow_vmcs = false;
7147                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7148                                 SECONDARY_EXEC_SHADOW_VMCS);
7149                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7150         }
7151         vmx->nested.posted_intr_nv = -1;
7152
7153         /* Flush VMCS12 to guest memory */
7154         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7155                VMCS12_SIZE);
7156
7157         kunmap(vmx->nested.current_vmcs12_page);
7158         nested_release_page(vmx->nested.current_vmcs12_page);
7159         vmx->nested.current_vmptr = -1ull;
7160         vmx->nested.current_vmcs12 = NULL;
7161 }
7162
7163 /*
7164  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7165  * just stops using VMX.
7166  */
7167 static void free_nested(struct vcpu_vmx *vmx)
7168 {
7169         if (!vmx->nested.vmxon)
7170                 return;
7171
7172         vmx->nested.vmxon = false;
7173         free_vpid(vmx->nested.vpid02);
7174         nested_release_vmcs12(vmx);
7175         if (vmx->nested.msr_bitmap) {
7176                 free_page((unsigned long)vmx->nested.msr_bitmap);
7177                 vmx->nested.msr_bitmap = NULL;
7178         }
7179         if (enable_shadow_vmcs) {
7180                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7181                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7182                 vmx->vmcs01.shadow_vmcs = NULL;
7183         }
7184         kfree(vmx->nested.cached_vmcs12);
7185         /* Unpin physical memory we referred to in current vmcs02 */
7186         if (vmx->nested.apic_access_page) {
7187                 nested_release_page(vmx->nested.apic_access_page);
7188                 vmx->nested.apic_access_page = NULL;
7189         }
7190         if (vmx->nested.virtual_apic_page) {
7191                 nested_release_page(vmx->nested.virtual_apic_page);
7192                 vmx->nested.virtual_apic_page = NULL;
7193         }
7194         if (vmx->nested.pi_desc_page) {
7195                 kunmap(vmx->nested.pi_desc_page);
7196                 nested_release_page(vmx->nested.pi_desc_page);
7197                 vmx->nested.pi_desc_page = NULL;
7198                 vmx->nested.pi_desc = NULL;
7199         }
7200
7201         nested_free_all_saved_vmcss(vmx);
7202 }
7203
7204 /* Emulate the VMXOFF instruction */
7205 static int handle_vmoff(struct kvm_vcpu *vcpu)
7206 {
7207         if (!nested_vmx_check_permission(vcpu))
7208                 return 1;
7209         free_nested(to_vmx(vcpu));
7210         nested_vmx_succeed(vcpu);
7211         return kvm_skip_emulated_instruction(vcpu);
7212 }
7213
7214 /* Emulate the VMCLEAR instruction */
7215 static int handle_vmclear(struct kvm_vcpu *vcpu)
7216 {
7217         struct vcpu_vmx *vmx = to_vmx(vcpu);
7218         u32 zero = 0;
7219         gpa_t vmptr;
7220
7221         if (!nested_vmx_check_permission(vcpu))
7222                 return 1;
7223
7224         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7225                 return 1;
7226
7227         if (vmptr == vmx->nested.current_vmptr)
7228                 nested_release_vmcs12(vmx);
7229
7230         kvm_vcpu_write_guest(vcpu,
7231                         vmptr + offsetof(struct vmcs12, launch_state),
7232                         &zero, sizeof(zero));
7233
7234         nested_free_vmcs02(vmx, vmptr);
7235
7236         nested_vmx_succeed(vcpu);
7237         return kvm_skip_emulated_instruction(vcpu);
7238 }
7239
7240 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7241
7242 /* Emulate the VMLAUNCH instruction */
7243 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7244 {
7245         return nested_vmx_run(vcpu, true);
7246 }
7247
7248 /* Emulate the VMRESUME instruction */
7249 static int handle_vmresume(struct kvm_vcpu *vcpu)
7250 {
7251
7252         return nested_vmx_run(vcpu, false);
7253 }
7254
7255 enum vmcs_field_type {
7256         VMCS_FIELD_TYPE_U16 = 0,
7257         VMCS_FIELD_TYPE_U64 = 1,
7258         VMCS_FIELD_TYPE_U32 = 2,
7259         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7260 };
7261
7262 static inline int vmcs_field_type(unsigned long field)
7263 {
7264         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7265                 return VMCS_FIELD_TYPE_U32;
7266         return (field >> 13) & 0x3 ;
7267 }
7268
7269 static inline int vmcs_field_readonly(unsigned long field)
7270 {
7271         return (((field >> 10) & 0x3) == 1);
7272 }
7273
7274 /*
7275  * Read a vmcs12 field. Since these can have varying lengths and we return
7276  * one type, we chose the biggest type (u64) and zero-extend the return value
7277  * to that size. Note that the caller, handle_vmread, might need to use only
7278  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7279  * 64-bit fields are to be returned).
7280  */
7281 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7282                                   unsigned long field, u64 *ret)
7283 {
7284         short offset = vmcs_field_to_offset(field);
7285         char *p;
7286
7287         if (offset < 0)
7288                 return offset;
7289
7290         p = ((char *)(get_vmcs12(vcpu))) + offset;
7291
7292         switch (vmcs_field_type(field)) {
7293         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7294                 *ret = *((natural_width *)p);
7295                 return 0;
7296         case VMCS_FIELD_TYPE_U16:
7297                 *ret = *((u16 *)p);
7298                 return 0;
7299         case VMCS_FIELD_TYPE_U32:
7300                 *ret = *((u32 *)p);
7301                 return 0;
7302         case VMCS_FIELD_TYPE_U64:
7303                 *ret = *((u64 *)p);
7304                 return 0;
7305         default:
7306                 WARN_ON(1);
7307                 return -ENOENT;
7308         }
7309 }
7310
7311
7312 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7313                                    unsigned long field, u64 field_value){
7314         short offset = vmcs_field_to_offset(field);
7315         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7316         if (offset < 0)
7317                 return offset;
7318
7319         switch (vmcs_field_type(field)) {
7320         case VMCS_FIELD_TYPE_U16:
7321                 *(u16 *)p = field_value;
7322                 return 0;
7323         case VMCS_FIELD_TYPE_U32:
7324                 *(u32 *)p = field_value;
7325                 return 0;
7326         case VMCS_FIELD_TYPE_U64:
7327                 *(u64 *)p = field_value;
7328                 return 0;
7329         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7330                 *(natural_width *)p = field_value;
7331                 return 0;
7332         default:
7333                 WARN_ON(1);
7334                 return -ENOENT;
7335         }
7336
7337 }
7338
7339 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7340 {
7341         int i;
7342         unsigned long field;
7343         u64 field_value;
7344         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7345         const unsigned long *fields = shadow_read_write_fields;
7346         const int num_fields = max_shadow_read_write_fields;
7347
7348         preempt_disable();
7349
7350         vmcs_load(shadow_vmcs);
7351
7352         for (i = 0; i < num_fields; i++) {
7353                 field = fields[i];
7354                 switch (vmcs_field_type(field)) {
7355                 case VMCS_FIELD_TYPE_U16:
7356                         field_value = vmcs_read16(field);
7357                         break;
7358                 case VMCS_FIELD_TYPE_U32:
7359                         field_value = vmcs_read32(field);
7360                         break;
7361                 case VMCS_FIELD_TYPE_U64:
7362                         field_value = vmcs_read64(field);
7363                         break;
7364                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7365                         field_value = vmcs_readl(field);
7366                         break;
7367                 default:
7368                         WARN_ON(1);
7369                         continue;
7370                 }
7371                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7372         }
7373
7374         vmcs_clear(shadow_vmcs);
7375         vmcs_load(vmx->loaded_vmcs->vmcs);
7376
7377         preempt_enable();
7378 }
7379
7380 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7381 {
7382         const unsigned long *fields[] = {
7383                 shadow_read_write_fields,
7384                 shadow_read_only_fields
7385         };
7386         const int max_fields[] = {
7387                 max_shadow_read_write_fields,
7388                 max_shadow_read_only_fields
7389         };
7390         int i, q;
7391         unsigned long field;
7392         u64 field_value = 0;
7393         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7394
7395         vmcs_load(shadow_vmcs);
7396
7397         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7398                 for (i = 0; i < max_fields[q]; i++) {
7399                         field = fields[q][i];
7400                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7401
7402                         switch (vmcs_field_type(field)) {
7403                         case VMCS_FIELD_TYPE_U16:
7404                                 vmcs_write16(field, (u16)field_value);
7405                                 break;
7406                         case VMCS_FIELD_TYPE_U32:
7407                                 vmcs_write32(field, (u32)field_value);
7408                                 break;
7409                         case VMCS_FIELD_TYPE_U64:
7410                                 vmcs_write64(field, (u64)field_value);
7411                                 break;
7412                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7413                                 vmcs_writel(field, (long)field_value);
7414                                 break;
7415                         default:
7416                                 WARN_ON(1);
7417                                 break;
7418                         }
7419                 }
7420         }
7421
7422         vmcs_clear(shadow_vmcs);
7423         vmcs_load(vmx->loaded_vmcs->vmcs);
7424 }
7425
7426 /*
7427  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7428  * used before) all generate the same failure when it is missing.
7429  */
7430 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7431 {
7432         struct vcpu_vmx *vmx = to_vmx(vcpu);
7433         if (vmx->nested.current_vmptr == -1ull) {
7434                 nested_vmx_failInvalid(vcpu);
7435                 return 0;
7436         }
7437         return 1;
7438 }
7439
7440 static int handle_vmread(struct kvm_vcpu *vcpu)
7441 {
7442         unsigned long field;
7443         u64 field_value;
7444         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7445         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7446         gva_t gva = 0;
7447
7448         if (!nested_vmx_check_permission(vcpu))
7449                 return 1;
7450
7451         if (!nested_vmx_check_vmcs12(vcpu))
7452                 return kvm_skip_emulated_instruction(vcpu);
7453
7454         /* Decode instruction info and find the field to read */
7455         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7456         /* Read the field, zero-extended to a u64 field_value */
7457         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7458                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7459                 return kvm_skip_emulated_instruction(vcpu);
7460         }
7461         /*
7462          * Now copy part of this value to register or memory, as requested.
7463          * Note that the number of bits actually copied is 32 or 64 depending
7464          * on the guest's mode (32 or 64 bit), not on the given field's length.
7465          */
7466         if (vmx_instruction_info & (1u << 10)) {
7467                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7468                         field_value);
7469         } else {
7470                 if (get_vmx_mem_address(vcpu, exit_qualification,
7471                                 vmx_instruction_info, true, &gva))
7472                         return 1;
7473                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7474                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7475                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7476         }
7477
7478         nested_vmx_succeed(vcpu);
7479         return kvm_skip_emulated_instruction(vcpu);
7480 }
7481
7482
7483 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7484 {
7485         unsigned long field;
7486         gva_t gva;
7487         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7488         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7489         /* The value to write might be 32 or 64 bits, depending on L1's long
7490          * mode, and eventually we need to write that into a field of several
7491          * possible lengths. The code below first zero-extends the value to 64
7492          * bit (field_value), and then copies only the appropriate number of
7493          * bits into the vmcs12 field.
7494          */
7495         u64 field_value = 0;
7496         struct x86_exception e;
7497
7498         if (!nested_vmx_check_permission(vcpu))
7499                 return 1;
7500
7501         if (!nested_vmx_check_vmcs12(vcpu))
7502                 return kvm_skip_emulated_instruction(vcpu);
7503
7504         if (vmx_instruction_info & (1u << 10))
7505                 field_value = kvm_register_readl(vcpu,
7506                         (((vmx_instruction_info) >> 3) & 0xf));
7507         else {
7508                 if (get_vmx_mem_address(vcpu, exit_qualification,
7509                                 vmx_instruction_info, false, &gva))
7510                         return 1;
7511                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7512                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7513                         kvm_inject_page_fault(vcpu, &e);
7514                         return 1;
7515                 }
7516         }
7517
7518
7519         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7520         if (vmcs_field_readonly(field)) {
7521                 nested_vmx_failValid(vcpu,
7522                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7523                 return kvm_skip_emulated_instruction(vcpu);
7524         }
7525
7526         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7527                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7528                 return kvm_skip_emulated_instruction(vcpu);
7529         }
7530
7531         nested_vmx_succeed(vcpu);
7532         return kvm_skip_emulated_instruction(vcpu);
7533 }
7534
7535 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7536 {
7537         vmx->nested.current_vmptr = vmptr;
7538         if (enable_shadow_vmcs) {
7539                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7540                               SECONDARY_EXEC_SHADOW_VMCS);
7541                 vmcs_write64(VMCS_LINK_POINTER,
7542                              __pa(vmx->vmcs01.shadow_vmcs));
7543                 vmx->nested.sync_shadow_vmcs = true;
7544         }
7545 }
7546
7547 /* Emulate the VMPTRLD instruction */
7548 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7549 {
7550         struct vcpu_vmx *vmx = to_vmx(vcpu);
7551         gpa_t vmptr;
7552
7553         if (!nested_vmx_check_permission(vcpu))
7554                 return 1;
7555
7556         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7557                 return 1;
7558
7559         if (vmx->nested.current_vmptr != vmptr) {
7560                 struct vmcs12 *new_vmcs12;
7561                 struct page *page;
7562                 page = nested_get_page(vcpu, vmptr);
7563                 if (page == NULL) {
7564                         nested_vmx_failInvalid(vcpu);
7565                         return kvm_skip_emulated_instruction(vcpu);
7566                 }
7567                 new_vmcs12 = kmap(page);
7568                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7569                         kunmap(page);
7570                         nested_release_page_clean(page);
7571                         nested_vmx_failValid(vcpu,
7572                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7573                         return kvm_skip_emulated_instruction(vcpu);
7574                 }
7575
7576                 nested_release_vmcs12(vmx);
7577                 vmx->nested.current_vmcs12 = new_vmcs12;
7578                 vmx->nested.current_vmcs12_page = page;
7579                 /*
7580                  * Load VMCS12 from guest memory since it is not already
7581                  * cached.
7582                  */
7583                 memcpy(vmx->nested.cached_vmcs12,
7584                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7585                 set_current_vmptr(vmx, vmptr);
7586         }
7587
7588         nested_vmx_succeed(vcpu);
7589         return kvm_skip_emulated_instruction(vcpu);
7590 }
7591
7592 /* Emulate the VMPTRST instruction */
7593 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7594 {
7595         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7596         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7597         gva_t vmcs_gva;
7598         struct x86_exception e;
7599
7600         if (!nested_vmx_check_permission(vcpu))
7601                 return 1;
7602
7603         if (get_vmx_mem_address(vcpu, exit_qualification,
7604                         vmx_instruction_info, true, &vmcs_gva))
7605                 return 1;
7606         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7607         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7608                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7609                                  sizeof(u64), &e)) {
7610                 kvm_inject_page_fault(vcpu, &e);
7611                 return 1;
7612         }
7613         nested_vmx_succeed(vcpu);
7614         return kvm_skip_emulated_instruction(vcpu);
7615 }
7616
7617 /* Emulate the INVEPT instruction */
7618 static int handle_invept(struct kvm_vcpu *vcpu)
7619 {
7620         struct vcpu_vmx *vmx = to_vmx(vcpu);
7621         u32 vmx_instruction_info, types;
7622         unsigned long type;
7623         gva_t gva;
7624         struct x86_exception e;
7625         struct {
7626                 u64 eptp, gpa;
7627         } operand;
7628
7629         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7630               SECONDARY_EXEC_ENABLE_EPT) ||
7631             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7632                 kvm_queue_exception(vcpu, UD_VECTOR);
7633                 return 1;
7634         }
7635
7636         if (!nested_vmx_check_permission(vcpu))
7637                 return 1;
7638
7639         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7640                 kvm_queue_exception(vcpu, UD_VECTOR);
7641                 return 1;
7642         }
7643
7644         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7645         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7646
7647         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7648
7649         if (type >= 32 || !(types & (1 << type))) {
7650                 nested_vmx_failValid(vcpu,
7651                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7652                 return kvm_skip_emulated_instruction(vcpu);
7653         }
7654
7655         /* According to the Intel VMX instruction reference, the memory
7656          * operand is read even if it isn't needed (e.g., for type==global)
7657          */
7658         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7659                         vmx_instruction_info, false, &gva))
7660                 return 1;
7661         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7662                                 sizeof(operand), &e)) {
7663                 kvm_inject_page_fault(vcpu, &e);
7664                 return 1;
7665         }
7666
7667         switch (type) {
7668         case VMX_EPT_EXTENT_GLOBAL:
7669         /*
7670          * TODO: track mappings and invalidate
7671          * single context requests appropriately
7672          */
7673         case VMX_EPT_EXTENT_CONTEXT:
7674                 kvm_mmu_sync_roots(vcpu);
7675                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7676                 nested_vmx_succeed(vcpu);
7677                 break;
7678         default:
7679                 BUG_ON(1);
7680                 break;
7681         }
7682
7683         return kvm_skip_emulated_instruction(vcpu);
7684 }
7685
7686 static int handle_invvpid(struct kvm_vcpu *vcpu)
7687 {
7688         struct vcpu_vmx *vmx = to_vmx(vcpu);
7689         u32 vmx_instruction_info;
7690         unsigned long type, types;
7691         gva_t gva;
7692         struct x86_exception e;
7693         int vpid;
7694
7695         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7696               SECONDARY_EXEC_ENABLE_VPID) ||
7697                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7698                 kvm_queue_exception(vcpu, UD_VECTOR);
7699                 return 1;
7700         }
7701
7702         if (!nested_vmx_check_permission(vcpu))
7703                 return 1;
7704
7705         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7706         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7707
7708         types = (vmx->nested.nested_vmx_vpid_caps &
7709                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7710
7711         if (type >= 32 || !(types & (1 << type))) {
7712                 nested_vmx_failValid(vcpu,
7713                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7714                 return kvm_skip_emulated_instruction(vcpu);
7715         }
7716
7717         /* according to the intel vmx instruction reference, the memory
7718          * operand is read even if it isn't needed (e.g., for type==global)
7719          */
7720         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7721                         vmx_instruction_info, false, &gva))
7722                 return 1;
7723         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7724                                 sizeof(u32), &e)) {
7725                 kvm_inject_page_fault(vcpu, &e);
7726                 return 1;
7727         }
7728
7729         switch (type) {
7730         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7731         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7732         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7733                 if (!vpid) {
7734                         nested_vmx_failValid(vcpu,
7735                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7736                         return kvm_skip_emulated_instruction(vcpu);
7737                 }
7738                 break;
7739         case VMX_VPID_EXTENT_ALL_CONTEXT:
7740                 break;
7741         default:
7742                 WARN_ON_ONCE(1);
7743                 return kvm_skip_emulated_instruction(vcpu);
7744         }
7745
7746         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7747         nested_vmx_succeed(vcpu);
7748
7749         return kvm_skip_emulated_instruction(vcpu);
7750 }
7751
7752 static int handle_pml_full(struct kvm_vcpu *vcpu)
7753 {
7754         unsigned long exit_qualification;
7755
7756         trace_kvm_pml_full(vcpu->vcpu_id);
7757
7758         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7759
7760         /*
7761          * PML buffer FULL happened while executing iret from NMI,
7762          * "blocked by NMI" bit has to be set before next VM entry.
7763          */
7764         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7765                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7766                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7767                                 GUEST_INTR_STATE_NMI);
7768
7769         /*
7770          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7771          * here.., and there's no userspace involvement needed for PML.
7772          */
7773         return 1;
7774 }
7775
7776 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7777 {
7778         kvm_lapic_expired_hv_timer(vcpu);
7779         return 1;
7780 }
7781
7782 /*
7783  * The exit handlers return 1 if the exit was handled fully and guest execution
7784  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7785  * to be done to userspace and return 0.
7786  */
7787 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7788         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7789         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7790         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7791         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7792         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7793         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7794         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7795         [EXIT_REASON_CPUID]                   = handle_cpuid,
7796         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7797         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7798         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7799         [EXIT_REASON_HLT]                     = handle_halt,
7800         [EXIT_REASON_INVD]                    = handle_invd,
7801         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7802         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7803         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7804         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7805         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7806         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7807         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7808         [EXIT_REASON_VMREAD]                  = handle_vmread,
7809         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7810         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7811         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7812         [EXIT_REASON_VMON]                    = handle_vmon,
7813         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7814         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7815         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7816         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7817         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7818         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7819         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7820         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7821         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7822         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7823         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7824         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7825         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7826         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7827         [EXIT_REASON_INVEPT]                  = handle_invept,
7828         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7829         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7830         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7831         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7832         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7833 };
7834
7835 static const int kvm_vmx_max_exit_handlers =
7836         ARRAY_SIZE(kvm_vmx_exit_handlers);
7837
7838 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7839                                        struct vmcs12 *vmcs12)
7840 {
7841         unsigned long exit_qualification;
7842         gpa_t bitmap, last_bitmap;
7843         unsigned int port;
7844         int size;
7845         u8 b;
7846
7847         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7848                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7849
7850         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7851
7852         port = exit_qualification >> 16;
7853         size = (exit_qualification & 7) + 1;
7854
7855         last_bitmap = (gpa_t)-1;
7856         b = -1;
7857
7858         while (size > 0) {
7859                 if (port < 0x8000)
7860                         bitmap = vmcs12->io_bitmap_a;
7861                 else if (port < 0x10000)
7862                         bitmap = vmcs12->io_bitmap_b;
7863                 else
7864                         return true;
7865                 bitmap += (port & 0x7fff) / 8;
7866
7867                 if (last_bitmap != bitmap)
7868                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7869                                 return true;
7870                 if (b & (1 << (port & 7)))
7871                         return true;
7872
7873                 port++;
7874                 size--;
7875                 last_bitmap = bitmap;
7876         }
7877
7878         return false;
7879 }
7880
7881 /*
7882  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7883  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7884  * disinterest in the current event (read or write a specific MSR) by using an
7885  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7886  */
7887 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7888         struct vmcs12 *vmcs12, u32 exit_reason)
7889 {
7890         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7891         gpa_t bitmap;
7892
7893         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7894                 return true;
7895
7896         /*
7897          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7898          * for the four combinations of read/write and low/high MSR numbers.
7899          * First we need to figure out which of the four to use:
7900          */
7901         bitmap = vmcs12->msr_bitmap;
7902         if (exit_reason == EXIT_REASON_MSR_WRITE)
7903                 bitmap += 2048;
7904         if (msr_index >= 0xc0000000) {
7905                 msr_index -= 0xc0000000;
7906                 bitmap += 1024;
7907         }
7908
7909         /* Then read the msr_index'th bit from this bitmap: */
7910         if (msr_index < 1024*8) {
7911                 unsigned char b;
7912                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7913                         return true;
7914                 return 1 & (b >> (msr_index & 7));
7915         } else
7916                 return true; /* let L1 handle the wrong parameter */
7917 }
7918
7919 /*
7920  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7921  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7922  * intercept (via guest_host_mask etc.) the current event.
7923  */
7924 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7925         struct vmcs12 *vmcs12)
7926 {
7927         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7928         int cr = exit_qualification & 15;
7929         int reg = (exit_qualification >> 8) & 15;
7930         unsigned long val = kvm_register_readl(vcpu, reg);
7931
7932         switch ((exit_qualification >> 4) & 3) {
7933         case 0: /* mov to cr */
7934                 switch (cr) {
7935                 case 0:
7936                         if (vmcs12->cr0_guest_host_mask &
7937                             (val ^ vmcs12->cr0_read_shadow))
7938                                 return true;
7939                         break;
7940                 case 3:
7941                         if ((vmcs12->cr3_target_count >= 1 &&
7942                                         vmcs12->cr3_target_value0 == val) ||
7943                                 (vmcs12->cr3_target_count >= 2 &&
7944                                         vmcs12->cr3_target_value1 == val) ||
7945                                 (vmcs12->cr3_target_count >= 3 &&
7946                                         vmcs12->cr3_target_value2 == val) ||
7947                                 (vmcs12->cr3_target_count >= 4 &&
7948                                         vmcs12->cr3_target_value3 == val))
7949                                 return false;
7950                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7951                                 return true;
7952                         break;
7953                 case 4:
7954                         if (vmcs12->cr4_guest_host_mask &
7955                             (vmcs12->cr4_read_shadow ^ val))
7956                                 return true;
7957                         break;
7958                 case 8:
7959                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7960                                 return true;
7961                         break;
7962                 }
7963                 break;
7964         case 2: /* clts */
7965                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7966                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7967                         return true;
7968                 break;
7969         case 1: /* mov from cr */
7970                 switch (cr) {
7971                 case 3:
7972                         if (vmcs12->cpu_based_vm_exec_control &
7973                             CPU_BASED_CR3_STORE_EXITING)
7974                                 return true;
7975                         break;
7976                 case 8:
7977                         if (vmcs12->cpu_based_vm_exec_control &
7978                             CPU_BASED_CR8_STORE_EXITING)
7979                                 return true;
7980                         break;
7981                 }
7982                 break;
7983         case 3: /* lmsw */
7984                 /*
7985                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7986                  * cr0. Other attempted changes are ignored, with no exit.
7987                  */
7988                 if (vmcs12->cr0_guest_host_mask & 0xe &
7989                     (val ^ vmcs12->cr0_read_shadow))
7990                         return true;
7991                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7992                     !(vmcs12->cr0_read_shadow & 0x1) &&
7993                     (val & 0x1))
7994                         return true;
7995                 break;
7996         }
7997         return false;
7998 }
7999
8000 /*
8001  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8002  * should handle it ourselves in L0 (and then continue L2). Only call this
8003  * when in is_guest_mode (L2).
8004  */
8005 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8006 {
8007         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8008         struct vcpu_vmx *vmx = to_vmx(vcpu);
8009         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8010         u32 exit_reason = vmx->exit_reason;
8011
8012         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8013                                 vmcs_readl(EXIT_QUALIFICATION),
8014                                 vmx->idt_vectoring_info,
8015                                 intr_info,
8016                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8017                                 KVM_ISA_VMX);
8018
8019         if (vmx->nested.nested_run_pending)
8020                 return false;
8021
8022         if (unlikely(vmx->fail)) {
8023                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8024                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8025                 return true;
8026         }
8027
8028         switch (exit_reason) {
8029         case EXIT_REASON_EXCEPTION_NMI:
8030                 if (is_nmi(intr_info))
8031                         return false;
8032                 else if (is_page_fault(intr_info))
8033                         return enable_ept;
8034                 else if (is_no_device(intr_info) &&
8035                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8036                         return false;
8037                 else if (is_debug(intr_info) &&
8038                          vcpu->guest_debug &
8039                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8040                         return false;
8041                 else if (is_breakpoint(intr_info) &&
8042                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8043                         return false;
8044                 return vmcs12->exception_bitmap &
8045                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8046         case EXIT_REASON_EXTERNAL_INTERRUPT:
8047                 return false;
8048         case EXIT_REASON_TRIPLE_FAULT:
8049                 return true;
8050         case EXIT_REASON_PENDING_INTERRUPT:
8051                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8052         case EXIT_REASON_NMI_WINDOW:
8053                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8054         case EXIT_REASON_TASK_SWITCH:
8055                 return true;
8056         case EXIT_REASON_CPUID:
8057                 return true;
8058         case EXIT_REASON_HLT:
8059                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8060         case EXIT_REASON_INVD:
8061                 return true;
8062         case EXIT_REASON_INVLPG:
8063                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8064         case EXIT_REASON_RDPMC:
8065                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8066         case EXIT_REASON_RDRAND:
8067                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8068         case EXIT_REASON_RDSEED:
8069                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8070         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8071                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8072         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8073         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8074         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8075         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8076         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8077         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8078                 /*
8079                  * VMX instructions trap unconditionally. This allows L1 to
8080                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8081                  */
8082                 return true;
8083         case EXIT_REASON_CR_ACCESS:
8084                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8085         case EXIT_REASON_DR_ACCESS:
8086                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8087         case EXIT_REASON_IO_INSTRUCTION:
8088                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8089         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8090                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8091         case EXIT_REASON_MSR_READ:
8092         case EXIT_REASON_MSR_WRITE:
8093                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8094         case EXIT_REASON_INVALID_STATE:
8095                 return true;
8096         case EXIT_REASON_MWAIT_INSTRUCTION:
8097                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8098         case EXIT_REASON_MONITOR_TRAP_FLAG:
8099                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8100         case EXIT_REASON_MONITOR_INSTRUCTION:
8101                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8102         case EXIT_REASON_PAUSE_INSTRUCTION:
8103                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8104                         nested_cpu_has2(vmcs12,
8105                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8106         case EXIT_REASON_MCE_DURING_VMENTRY:
8107                 return false;
8108         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8109                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8110         case EXIT_REASON_APIC_ACCESS:
8111                 return nested_cpu_has2(vmcs12,
8112                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8113         case EXIT_REASON_APIC_WRITE:
8114         case EXIT_REASON_EOI_INDUCED:
8115                 /* apic_write and eoi_induced should exit unconditionally. */
8116                 return true;
8117         case EXIT_REASON_EPT_VIOLATION:
8118                 /*
8119                  * L0 always deals with the EPT violation. If nested EPT is
8120                  * used, and the nested mmu code discovers that the address is
8121                  * missing in the guest EPT table (EPT12), the EPT violation
8122                  * will be injected with nested_ept_inject_page_fault()
8123                  */
8124                 return false;
8125         case EXIT_REASON_EPT_MISCONFIG:
8126                 /*
8127                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8128                  * table (shadow on EPT) or a merged EPT table that L0 built
8129                  * (EPT on EPT). So any problems with the structure of the
8130                  * table is L0's fault.
8131                  */
8132                 return false;
8133         case EXIT_REASON_WBINVD:
8134                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8135         case EXIT_REASON_XSETBV:
8136                 return true;
8137         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8138                 /*
8139                  * This should never happen, since it is not possible to
8140                  * set XSS to a non-zero value---neither in L1 nor in L2.
8141                  * If if it were, XSS would have to be checked against
8142                  * the XSS exit bitmap in vmcs12.
8143                  */
8144                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8145         case EXIT_REASON_PREEMPTION_TIMER:
8146                 return false;
8147         default:
8148                 return true;
8149         }
8150 }
8151
8152 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8153 {
8154         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8155         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8156 }
8157
8158 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8159 {
8160         if (vmx->pml_pg) {
8161                 __free_page(vmx->pml_pg);
8162                 vmx->pml_pg = NULL;
8163         }
8164 }
8165
8166 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8167 {
8168         struct vcpu_vmx *vmx = to_vmx(vcpu);
8169         u64 *pml_buf;
8170         u16 pml_idx;
8171
8172         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8173
8174         /* Do nothing if PML buffer is empty */
8175         if (pml_idx == (PML_ENTITY_NUM - 1))
8176                 return;
8177
8178         /* PML index always points to next available PML buffer entity */
8179         if (pml_idx >= PML_ENTITY_NUM)
8180                 pml_idx = 0;
8181         else
8182                 pml_idx++;
8183
8184         pml_buf = page_address(vmx->pml_pg);
8185         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8186                 u64 gpa;
8187
8188                 gpa = pml_buf[pml_idx];
8189                 WARN_ON(gpa & (PAGE_SIZE - 1));
8190                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8191         }
8192
8193         /* reset PML index */
8194         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8195 }
8196
8197 /*
8198  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8199  * Called before reporting dirty_bitmap to userspace.
8200  */
8201 static void kvm_flush_pml_buffers(struct kvm *kvm)
8202 {
8203         int i;
8204         struct kvm_vcpu *vcpu;
8205         /*
8206          * We only need to kick vcpu out of guest mode here, as PML buffer
8207          * is flushed at beginning of all VMEXITs, and it's obvious that only
8208          * vcpus running in guest are possible to have unflushed GPAs in PML
8209          * buffer.
8210          */
8211         kvm_for_each_vcpu(i, vcpu, kvm)
8212                 kvm_vcpu_kick(vcpu);
8213 }
8214
8215 static void vmx_dump_sel(char *name, uint32_t sel)
8216 {
8217         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8218                name, vmcs_read16(sel),
8219                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8220                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8221                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8222 }
8223
8224 static void vmx_dump_dtsel(char *name, uint32_t limit)
8225 {
8226         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8227                name, vmcs_read32(limit),
8228                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8229 }
8230
8231 static void dump_vmcs(void)
8232 {
8233         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8234         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8235         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8236         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8237         u32 secondary_exec_control = 0;
8238         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8239         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8240         int i, n;
8241
8242         if (cpu_has_secondary_exec_ctrls())
8243                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8244
8245         pr_err("*** Guest State ***\n");
8246         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8247                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8248                vmcs_readl(CR0_GUEST_HOST_MASK));
8249         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8250                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8251         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8252         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8253             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8254         {
8255                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8256                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8257                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8258                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8259         }
8260         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8261                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8262         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8263                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8264         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8265                vmcs_readl(GUEST_SYSENTER_ESP),
8266                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8267         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8268         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8269         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8270         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8271         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8272         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8273         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8274         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8275         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8276         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8277         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8278             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8279                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8280                        efer, vmcs_read64(GUEST_IA32_PAT));
8281         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8282                vmcs_read64(GUEST_IA32_DEBUGCTL),
8283                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8284         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8285                 pr_err("PerfGlobCtl = 0x%016llx\n",
8286                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8287         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8288                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8289         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8290                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8291                vmcs_read32(GUEST_ACTIVITY_STATE));
8292         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8293                 pr_err("InterruptStatus = %04x\n",
8294                        vmcs_read16(GUEST_INTR_STATUS));
8295
8296         pr_err("*** Host State ***\n");
8297         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8298                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8299         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8300                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8301                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8302                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8303                vmcs_read16(HOST_TR_SELECTOR));
8304         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8305                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8306                vmcs_readl(HOST_TR_BASE));
8307         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8308                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8309         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8310                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8311                vmcs_readl(HOST_CR4));
8312         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8313                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8314                vmcs_read32(HOST_IA32_SYSENTER_CS),
8315                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8316         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8317                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8318                        vmcs_read64(HOST_IA32_EFER),
8319                        vmcs_read64(HOST_IA32_PAT));
8320         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8321                 pr_err("PerfGlobCtl = 0x%016llx\n",
8322                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8323
8324         pr_err("*** Control State ***\n");
8325         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8326                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8327         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8328         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8329                vmcs_read32(EXCEPTION_BITMAP),
8330                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8331                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8332         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8333                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8334                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8335                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8336         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8337                vmcs_read32(VM_EXIT_INTR_INFO),
8338                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8339                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8340         pr_err("        reason=%08x qualification=%016lx\n",
8341                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8342         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8343                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8344                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8345         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8346         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8347                 pr_err("TSC Multiplier = 0x%016llx\n",
8348                        vmcs_read64(TSC_MULTIPLIER));
8349         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8350                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8351         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8352                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8353         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8354                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8355         n = vmcs_read32(CR3_TARGET_COUNT);
8356         for (i = 0; i + 1 < n; i += 4)
8357                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8358                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8359                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8360         if (i < n)
8361                 pr_err("CR3 target%u=%016lx\n",
8362                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8363         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8364                 pr_err("PLE Gap=%08x Window=%08x\n",
8365                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8366         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8367                 pr_err("Virtual processor ID = 0x%04x\n",
8368                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8369 }
8370
8371 /*
8372  * The guest has exited.  See if we can fix it or if we need userspace
8373  * assistance.
8374  */
8375 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8376 {
8377         struct vcpu_vmx *vmx = to_vmx(vcpu);
8378         u32 exit_reason = vmx->exit_reason;
8379         u32 vectoring_info = vmx->idt_vectoring_info;
8380
8381         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8382         vcpu->arch.gpa_available = false;
8383
8384         /*
8385          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8386          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8387          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8388          * mode as if vcpus is in root mode, the PML buffer must has been
8389          * flushed already.
8390          */
8391         if (enable_pml)
8392                 vmx_flush_pml_buffer(vcpu);
8393
8394         /* If guest state is invalid, start emulating */
8395         if (vmx->emulation_required)
8396                 return handle_invalid_guest_state(vcpu);
8397
8398         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8399                 nested_vmx_vmexit(vcpu, exit_reason,
8400                                   vmcs_read32(VM_EXIT_INTR_INFO),
8401                                   vmcs_readl(EXIT_QUALIFICATION));
8402                 return 1;
8403         }
8404
8405         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8406                 dump_vmcs();
8407                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8408                 vcpu->run->fail_entry.hardware_entry_failure_reason
8409                         = exit_reason;
8410                 return 0;
8411         }
8412
8413         if (unlikely(vmx->fail)) {
8414                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8415                 vcpu->run->fail_entry.hardware_entry_failure_reason
8416                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8417                 return 0;
8418         }
8419
8420         /*
8421          * Note:
8422          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8423          * delivery event since it indicates guest is accessing MMIO.
8424          * The vm-exit can be triggered again after return to guest that
8425          * will cause infinite loop.
8426          */
8427         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8428                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8429                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8430                         exit_reason != EXIT_REASON_PML_FULL &&
8431                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8432                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8433                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8434                 vcpu->run->internal.ndata = 2;
8435                 vcpu->run->internal.data[0] = vectoring_info;
8436                 vcpu->run->internal.data[1] = exit_reason;
8437                 return 0;
8438         }
8439
8440         if (exit_reason < kvm_vmx_max_exit_handlers
8441             && kvm_vmx_exit_handlers[exit_reason])
8442                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8443         else {
8444                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8445                                 exit_reason);
8446                 kvm_queue_exception(vcpu, UD_VECTOR);
8447                 return 1;
8448         }
8449 }
8450
8451 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8452 {
8453         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8454
8455         if (is_guest_mode(vcpu) &&
8456                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8457                 return;
8458
8459         if (irr == -1 || tpr < irr) {
8460                 vmcs_write32(TPR_THRESHOLD, 0);
8461                 return;
8462         }
8463
8464         vmcs_write32(TPR_THRESHOLD, irr);
8465 }
8466
8467 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8468 {
8469         u32 sec_exec_control;
8470
8471         /* Postpone execution until vmcs01 is the current VMCS. */
8472         if (is_guest_mode(vcpu)) {
8473                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8474                 return;
8475         }
8476
8477         if (!cpu_has_vmx_virtualize_x2apic_mode())
8478                 return;
8479
8480         if (!cpu_need_tpr_shadow(vcpu))
8481                 return;
8482
8483         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8484
8485         if (set) {
8486                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8487                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8488         } else {
8489                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8490                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8491                 vmx_flush_tlb_ept_only(vcpu);
8492         }
8493         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8494
8495         vmx_set_msr_bitmap(vcpu);
8496 }
8497
8498 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8499 {
8500         struct vcpu_vmx *vmx = to_vmx(vcpu);
8501
8502         /*
8503          * Currently we do not handle the nested case where L2 has an
8504          * APIC access page of its own; that page is still pinned.
8505          * Hence, we skip the case where the VCPU is in guest mode _and_
8506          * L1 prepared an APIC access page for L2.
8507          *
8508          * For the case where L1 and L2 share the same APIC access page
8509          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8510          * in the vmcs12), this function will only update either the vmcs01
8511          * or the vmcs02.  If the former, the vmcs02 will be updated by
8512          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8513          * the next L2->L1 exit.
8514          */
8515         if (!is_guest_mode(vcpu) ||
8516             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8517                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8518                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8519                 vmx_flush_tlb_ept_only(vcpu);
8520         }
8521 }
8522
8523 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8524 {
8525         u16 status;
8526         u8 old;
8527
8528         if (max_isr == -1)
8529                 max_isr = 0;
8530
8531         status = vmcs_read16(GUEST_INTR_STATUS);
8532         old = status >> 8;
8533         if (max_isr != old) {
8534                 status &= 0xff;
8535                 status |= max_isr << 8;
8536                 vmcs_write16(GUEST_INTR_STATUS, status);
8537         }
8538 }
8539
8540 static void vmx_set_rvi(int vector)
8541 {
8542         u16 status;
8543         u8 old;
8544
8545         if (vector == -1)
8546                 vector = 0;
8547
8548         status = vmcs_read16(GUEST_INTR_STATUS);
8549         old = (u8)status & 0xff;
8550         if ((u8)vector != old) {
8551                 status &= ~0xff;
8552                 status |= (u8)vector;
8553                 vmcs_write16(GUEST_INTR_STATUS, status);
8554         }
8555 }
8556
8557 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8558 {
8559         if (!is_guest_mode(vcpu)) {
8560                 vmx_set_rvi(max_irr);
8561                 return;
8562         }
8563
8564         if (max_irr == -1)
8565                 return;
8566
8567         /*
8568          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8569          * handles it.
8570          */
8571         if (nested_exit_on_intr(vcpu))
8572                 return;
8573
8574         /*
8575          * Else, fall back to pre-APICv interrupt injection since L2
8576          * is run without virtual interrupt delivery.
8577          */
8578         if (!kvm_event_needs_reinjection(vcpu) &&
8579             vmx_interrupt_allowed(vcpu)) {
8580                 kvm_queue_interrupt(vcpu, max_irr, false);
8581                 vmx_inject_irq(vcpu);
8582         }
8583 }
8584
8585 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8586 {
8587         struct vcpu_vmx *vmx = to_vmx(vcpu);
8588         int max_irr;
8589
8590         WARN_ON(!vcpu->arch.apicv_active);
8591         if (pi_test_on(&vmx->pi_desc)) {
8592                 pi_clear_on(&vmx->pi_desc);
8593                 /*
8594                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8595                  * But on x86 this is just a compiler barrier anyway.
8596                  */
8597                 smp_mb__after_atomic();
8598                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8599         } else {
8600                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8601         }
8602         vmx_hwapic_irr_update(vcpu, max_irr);
8603         return max_irr;
8604 }
8605
8606 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8607 {
8608         if (!kvm_vcpu_apicv_active(vcpu))
8609                 return;
8610
8611         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8612         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8613         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8614         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8615 }
8616
8617 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8618 {
8619         struct vcpu_vmx *vmx = to_vmx(vcpu);
8620
8621         pi_clear_on(&vmx->pi_desc);
8622         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8623 }
8624
8625 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8626 {
8627         u32 exit_intr_info;
8628
8629         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8630               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8631                 return;
8632
8633         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8634         exit_intr_info = vmx->exit_intr_info;
8635
8636         /* Handle machine checks before interrupts are enabled */
8637         if (is_machine_check(exit_intr_info))
8638                 kvm_machine_check();
8639
8640         /* We need to handle NMIs before interrupts are enabled */
8641         if (is_nmi(exit_intr_info)) {
8642                 kvm_before_handle_nmi(&vmx->vcpu);
8643                 asm("int $2");
8644                 kvm_after_handle_nmi(&vmx->vcpu);
8645         }
8646 }
8647
8648 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8649 {
8650         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8651         register void *__sp asm(_ASM_SP);
8652
8653         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8654                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8655                 unsigned int vector;
8656                 unsigned long entry;
8657                 gate_desc *desc;
8658                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8659 #ifdef CONFIG_X86_64
8660                 unsigned long tmp;
8661 #endif
8662
8663                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8664                 desc = (gate_desc *)vmx->host_idt_base + vector;
8665                 entry = gate_offset(*desc);
8666                 asm volatile(
8667 #ifdef CONFIG_X86_64
8668                         "mov %%" _ASM_SP ", %[sp]\n\t"
8669                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8670                         "push $%c[ss]\n\t"
8671                         "push %[sp]\n\t"
8672 #endif
8673                         "pushf\n\t"
8674                         __ASM_SIZE(push) " $%c[cs]\n\t"
8675                         "call *%[entry]\n\t"
8676                         :
8677 #ifdef CONFIG_X86_64
8678                         [sp]"=&r"(tmp),
8679 #endif
8680                         "+r"(__sp)
8681                         :
8682                         [entry]"r"(entry),
8683                         [ss]"i"(__KERNEL_DS),
8684                         [cs]"i"(__KERNEL_CS)
8685                         );
8686         }
8687 }
8688
8689 static bool vmx_has_high_real_mode_segbase(void)
8690 {
8691         return enable_unrestricted_guest || emulate_invalid_guest_state;
8692 }
8693
8694 static bool vmx_mpx_supported(void)
8695 {
8696         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8697                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8698 }
8699
8700 static bool vmx_xsaves_supported(void)
8701 {
8702         return vmcs_config.cpu_based_2nd_exec_ctrl &
8703                 SECONDARY_EXEC_XSAVES;
8704 }
8705
8706 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8707 {
8708         u32 exit_intr_info;
8709         bool unblock_nmi;
8710         u8 vector;
8711         bool idtv_info_valid;
8712
8713         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8714
8715         if (vmx->nmi_known_unmasked)
8716                 return;
8717         /*
8718          * Can't use vmx->exit_intr_info since we're not sure what
8719          * the exit reason is.
8720          */
8721         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8722         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8723         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8724         /*
8725          * SDM 3: 27.7.1.2 (September 2008)
8726          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8727          * a guest IRET fault.
8728          * SDM 3: 23.2.2 (September 2008)
8729          * Bit 12 is undefined in any of the following cases:
8730          *  If the VM exit sets the valid bit in the IDT-vectoring
8731          *   information field.
8732          *  If the VM exit is due to a double fault.
8733          */
8734         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8735             vector != DF_VECTOR && !idtv_info_valid)
8736                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8737                               GUEST_INTR_STATE_NMI);
8738         else
8739                 vmx->nmi_known_unmasked =
8740                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8741                           & GUEST_INTR_STATE_NMI);
8742 }
8743
8744 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8745                                       u32 idt_vectoring_info,
8746                                       int instr_len_field,
8747                                       int error_code_field)
8748 {
8749         u8 vector;
8750         int type;
8751         bool idtv_info_valid;
8752
8753         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8754
8755         vcpu->arch.nmi_injected = false;
8756         kvm_clear_exception_queue(vcpu);
8757         kvm_clear_interrupt_queue(vcpu);
8758
8759         if (!idtv_info_valid)
8760                 return;
8761
8762         kvm_make_request(KVM_REQ_EVENT, vcpu);
8763
8764         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8765         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8766
8767         switch (type) {
8768         case INTR_TYPE_NMI_INTR:
8769                 vcpu->arch.nmi_injected = true;
8770                 /*
8771                  * SDM 3: 27.7.1.2 (September 2008)
8772                  * Clear bit "block by NMI" before VM entry if a NMI
8773                  * delivery faulted.
8774                  */
8775                 vmx_set_nmi_mask(vcpu, false);
8776                 break;
8777         case INTR_TYPE_SOFT_EXCEPTION:
8778                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8779                 /* fall through */
8780         case INTR_TYPE_HARD_EXCEPTION:
8781                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8782                         u32 err = vmcs_read32(error_code_field);
8783                         kvm_requeue_exception_e(vcpu, vector, err);
8784                 } else
8785                         kvm_requeue_exception(vcpu, vector);
8786                 break;
8787         case INTR_TYPE_SOFT_INTR:
8788                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8789                 /* fall through */
8790         case INTR_TYPE_EXT_INTR:
8791                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8792                 break;
8793         default:
8794                 break;
8795         }
8796 }
8797
8798 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8799 {
8800         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8801                                   VM_EXIT_INSTRUCTION_LEN,
8802                                   IDT_VECTORING_ERROR_CODE);
8803 }
8804
8805 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8806 {
8807         __vmx_complete_interrupts(vcpu,
8808                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8809                                   VM_ENTRY_INSTRUCTION_LEN,
8810                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8811
8812         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8813 }
8814
8815 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8816 {
8817         int i, nr_msrs;
8818         struct perf_guest_switch_msr *msrs;
8819
8820         msrs = perf_guest_get_msrs(&nr_msrs);
8821
8822         if (!msrs)
8823                 return;
8824
8825         for (i = 0; i < nr_msrs; i++)
8826                 if (msrs[i].host == msrs[i].guest)
8827                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8828                 else
8829                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8830                                         msrs[i].host);
8831 }
8832
8833 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8834 {
8835         struct vcpu_vmx *vmx = to_vmx(vcpu);
8836         u64 tscl;
8837         u32 delta_tsc;
8838
8839         if (vmx->hv_deadline_tsc == -1)
8840                 return;
8841
8842         tscl = rdtsc();
8843         if (vmx->hv_deadline_tsc > tscl)
8844                 /* sure to be 32 bit only because checked on set_hv_timer */
8845                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8846                         cpu_preemption_timer_multi);
8847         else
8848                 delta_tsc = 0;
8849
8850         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8851 }
8852
8853 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8854 {
8855         struct vcpu_vmx *vmx = to_vmx(vcpu);
8856         unsigned long debugctlmsr, cr4;
8857
8858         /* Don't enter VMX if guest state is invalid, let the exit handler
8859            start emulation until we arrive back to a valid state */
8860         if (vmx->emulation_required)
8861                 return;
8862
8863         if (vmx->ple_window_dirty) {
8864                 vmx->ple_window_dirty = false;
8865                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8866         }
8867
8868         if (vmx->nested.sync_shadow_vmcs) {
8869                 copy_vmcs12_to_shadow(vmx);
8870                 vmx->nested.sync_shadow_vmcs = false;
8871         }
8872
8873         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8874                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8875         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8876                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8877
8878         cr4 = cr4_read_shadow();
8879         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8880                 vmcs_writel(HOST_CR4, cr4);
8881                 vmx->host_state.vmcs_host_cr4 = cr4;
8882         }
8883
8884         /* When single-stepping over STI and MOV SS, we must clear the
8885          * corresponding interruptibility bits in the guest state. Otherwise
8886          * vmentry fails as it then expects bit 14 (BS) in pending debug
8887          * exceptions being set, but that's not correct for the guest debugging
8888          * case. */
8889         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8890                 vmx_set_interrupt_shadow(vcpu, 0);
8891
8892         if (vmx->guest_pkru_valid)
8893                 __write_pkru(vmx->guest_pkru);
8894
8895         atomic_switch_perf_msrs(vmx);
8896         debugctlmsr = get_debugctlmsr();
8897
8898         vmx_arm_hv_timer(vcpu);
8899
8900         vmx->__launched = vmx->loaded_vmcs->launched;
8901         asm(
8902                 /* Store host registers */
8903                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8904                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8905                 "push %%" _ASM_CX " \n\t"
8906                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8907                 "je 1f \n\t"
8908                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8909                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8910                 "1: \n\t"
8911                 /* Reload cr2 if changed */
8912                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8913                 "mov %%cr2, %%" _ASM_DX " \n\t"
8914                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8915                 "je 2f \n\t"
8916                 "mov %%" _ASM_AX", %%cr2 \n\t"
8917                 "2: \n\t"
8918                 /* Check if vmlaunch of vmresume is needed */
8919                 "cmpl $0, %c[launched](%0) \n\t"
8920                 /* Load guest registers.  Don't clobber flags. */
8921                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8922                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8923                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8924                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8925                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8926                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8927 #ifdef CONFIG_X86_64
8928                 "mov %c[r8](%0),  %%r8  \n\t"
8929                 "mov %c[r9](%0),  %%r9  \n\t"
8930                 "mov %c[r10](%0), %%r10 \n\t"
8931                 "mov %c[r11](%0), %%r11 \n\t"
8932                 "mov %c[r12](%0), %%r12 \n\t"
8933                 "mov %c[r13](%0), %%r13 \n\t"
8934                 "mov %c[r14](%0), %%r14 \n\t"
8935                 "mov %c[r15](%0), %%r15 \n\t"
8936 #endif
8937                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8938
8939                 /* Enter guest mode */
8940                 "jne 1f \n\t"
8941                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8942                 "jmp 2f \n\t"
8943                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8944                 "2: "
8945                 /* Save guest registers, load host registers, keep flags */
8946                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8947                 "pop %0 \n\t"
8948                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8949                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8950                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8951                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8952                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8953                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8954                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8955 #ifdef CONFIG_X86_64
8956                 "mov %%r8,  %c[r8](%0) \n\t"
8957                 "mov %%r9,  %c[r9](%0) \n\t"
8958                 "mov %%r10, %c[r10](%0) \n\t"
8959                 "mov %%r11, %c[r11](%0) \n\t"
8960                 "mov %%r12, %c[r12](%0) \n\t"
8961                 "mov %%r13, %c[r13](%0) \n\t"
8962                 "mov %%r14, %c[r14](%0) \n\t"
8963                 "mov %%r15, %c[r15](%0) \n\t"
8964 #endif
8965                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8966                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8967
8968                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8969                 "setbe %c[fail](%0) \n\t"
8970                 ".pushsection .rodata \n\t"
8971                 ".global vmx_return \n\t"
8972                 "vmx_return: " _ASM_PTR " 2b \n\t"
8973                 ".popsection"
8974               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8975                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8976                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8977                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8978                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8979                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8980                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8981                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8982                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8983                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8984                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8985 #ifdef CONFIG_X86_64
8986                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8987                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8988                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8989                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8990                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8991                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8992                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8993                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8994 #endif
8995                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8996                 [wordsize]"i"(sizeof(ulong))
8997               : "cc", "memory"
8998 #ifdef CONFIG_X86_64
8999                 , "rax", "rbx", "rdi", "rsi"
9000                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9001 #else
9002                 , "eax", "ebx", "edi", "esi"
9003 #endif
9004               );
9005
9006         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9007         if (debugctlmsr)
9008                 update_debugctlmsr(debugctlmsr);
9009
9010 #ifndef CONFIG_X86_64
9011         /*
9012          * The sysexit path does not restore ds/es, so we must set them to
9013          * a reasonable value ourselves.
9014          *
9015          * We can't defer this to vmx_load_host_state() since that function
9016          * may be executed in interrupt context, which saves and restore segments
9017          * around it, nullifying its effect.
9018          */
9019         loadsegment(ds, __USER_DS);
9020         loadsegment(es, __USER_DS);
9021 #endif
9022
9023         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9024                                   | (1 << VCPU_EXREG_RFLAGS)
9025                                   | (1 << VCPU_EXREG_PDPTR)
9026                                   | (1 << VCPU_EXREG_SEGMENTS)
9027                                   | (1 << VCPU_EXREG_CR3));
9028         vcpu->arch.regs_dirty = 0;
9029
9030         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9031
9032         vmx->loaded_vmcs->launched = 1;
9033
9034         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9035
9036         /*
9037          * eager fpu is enabled if PKEY is supported and CR4 is switched
9038          * back on host, so it is safe to read guest PKRU from current
9039          * XSAVE.
9040          */
9041         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9042                 vmx->guest_pkru = __read_pkru();
9043                 if (vmx->guest_pkru != vmx->host_pkru) {
9044                         vmx->guest_pkru_valid = true;
9045                         __write_pkru(vmx->host_pkru);
9046                 } else
9047                         vmx->guest_pkru_valid = false;
9048         }
9049
9050         /*
9051          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9052          * we did not inject a still-pending event to L1 now because of
9053          * nested_run_pending, we need to re-enable this bit.
9054          */
9055         if (vmx->nested.nested_run_pending)
9056                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9057
9058         vmx->nested.nested_run_pending = 0;
9059
9060         vmx_complete_atomic_exit(vmx);
9061         vmx_recover_nmi_blocking(vmx);
9062         vmx_complete_interrupts(vmx);
9063 }
9064
9065 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9066 {
9067         struct vcpu_vmx *vmx = to_vmx(vcpu);
9068         int cpu;
9069
9070         if (vmx->loaded_vmcs == vmcs)
9071                 return;
9072
9073         cpu = get_cpu();
9074         vmx->loaded_vmcs = vmcs;
9075         vmx_vcpu_put(vcpu);
9076         vmx_vcpu_load(vcpu, cpu);
9077         vcpu->cpu = cpu;
9078         put_cpu();
9079 }
9080
9081 /*
9082  * Ensure that the current vmcs of the logical processor is the
9083  * vmcs01 of the vcpu before calling free_nested().
9084  */
9085 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9086 {
9087        struct vcpu_vmx *vmx = to_vmx(vcpu);
9088        int r;
9089
9090        r = vcpu_load(vcpu);
9091        BUG_ON(r);
9092        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9093        free_nested(vmx);
9094        vcpu_put(vcpu);
9095 }
9096
9097 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9098 {
9099         struct vcpu_vmx *vmx = to_vmx(vcpu);
9100
9101         if (enable_pml)
9102                 vmx_destroy_pml_buffer(vmx);
9103         free_vpid(vmx->vpid);
9104         leave_guest_mode(vcpu);
9105         vmx_free_vcpu_nested(vcpu);
9106         free_loaded_vmcs(vmx->loaded_vmcs);
9107         kfree(vmx->guest_msrs);
9108         kvm_vcpu_uninit(vcpu);
9109         kmem_cache_free(kvm_vcpu_cache, vmx);
9110 }
9111
9112 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9113 {
9114         int err;
9115         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9116         int cpu;
9117
9118         if (!vmx)
9119                 return ERR_PTR(-ENOMEM);
9120
9121         vmx->vpid = allocate_vpid();
9122
9123         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9124         if (err)
9125                 goto free_vcpu;
9126
9127         err = -ENOMEM;
9128
9129         /*
9130          * If PML is turned on, failure on enabling PML just results in failure
9131          * of creating the vcpu, therefore we can simplify PML logic (by
9132          * avoiding dealing with cases, such as enabling PML partially on vcpus
9133          * for the guest, etc.
9134          */
9135         if (enable_pml) {
9136                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9137                 if (!vmx->pml_pg)
9138                         goto uninit_vcpu;
9139         }
9140
9141         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9142         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9143                      > PAGE_SIZE);
9144
9145         if (!vmx->guest_msrs)
9146                 goto free_pml;
9147
9148         vmx->loaded_vmcs = &vmx->vmcs01;
9149         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9150         vmx->loaded_vmcs->shadow_vmcs = NULL;
9151         if (!vmx->loaded_vmcs->vmcs)
9152                 goto free_msrs;
9153         loaded_vmcs_init(vmx->loaded_vmcs);
9154
9155         cpu = get_cpu();
9156         vmx_vcpu_load(&vmx->vcpu, cpu);
9157         vmx->vcpu.cpu = cpu;
9158         err = vmx_vcpu_setup(vmx);
9159         vmx_vcpu_put(&vmx->vcpu);
9160         put_cpu();
9161         if (err)
9162                 goto free_vmcs;
9163         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9164                 err = alloc_apic_access_page(kvm);
9165                 if (err)
9166                         goto free_vmcs;
9167         }
9168
9169         if (enable_ept) {
9170                 if (!kvm->arch.ept_identity_map_addr)
9171                         kvm->arch.ept_identity_map_addr =
9172                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9173                 err = init_rmode_identity_map(kvm);
9174                 if (err)
9175                         goto free_vmcs;
9176         }
9177
9178         if (nested) {
9179                 nested_vmx_setup_ctls_msrs(vmx);
9180                 vmx->nested.vpid02 = allocate_vpid();
9181         }
9182
9183         vmx->nested.posted_intr_nv = -1;
9184         vmx->nested.current_vmptr = -1ull;
9185         vmx->nested.current_vmcs12 = NULL;
9186
9187         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9188
9189         return &vmx->vcpu;
9190
9191 free_vmcs:
9192         free_vpid(vmx->nested.vpid02);
9193         free_loaded_vmcs(vmx->loaded_vmcs);
9194 free_msrs:
9195         kfree(vmx->guest_msrs);
9196 free_pml:
9197         vmx_destroy_pml_buffer(vmx);
9198 uninit_vcpu:
9199         kvm_vcpu_uninit(&vmx->vcpu);
9200 free_vcpu:
9201         free_vpid(vmx->vpid);
9202         kmem_cache_free(kvm_vcpu_cache, vmx);
9203         return ERR_PTR(err);
9204 }
9205
9206 static void __init vmx_check_processor_compat(void *rtn)
9207 {
9208         struct vmcs_config vmcs_conf;
9209
9210         *(int *)rtn = 0;
9211         if (setup_vmcs_config(&vmcs_conf) < 0)
9212                 *(int *)rtn = -EIO;
9213         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9214                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9215                                 smp_processor_id());
9216                 *(int *)rtn = -EIO;
9217         }
9218 }
9219
9220 static int get_ept_level(void)
9221 {
9222         return VMX_EPT_DEFAULT_GAW + 1;
9223 }
9224
9225 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9226 {
9227         u8 cache;
9228         u64 ipat = 0;
9229
9230         /* For VT-d and EPT combination
9231          * 1. MMIO: always map as UC
9232          * 2. EPT with VT-d:
9233          *   a. VT-d without snooping control feature: can't guarantee the
9234          *      result, try to trust guest.
9235          *   b. VT-d with snooping control feature: snooping control feature of
9236          *      VT-d engine can guarantee the cache correctness. Just set it
9237          *      to WB to keep consistent with host. So the same as item 3.
9238          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9239          *    consistent with host MTRR
9240          */
9241         if (is_mmio) {
9242                 cache = MTRR_TYPE_UNCACHABLE;
9243                 goto exit;
9244         }
9245
9246         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9247                 ipat = VMX_EPT_IPAT_BIT;
9248                 cache = MTRR_TYPE_WRBACK;
9249                 goto exit;
9250         }
9251
9252         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9253                 ipat = VMX_EPT_IPAT_BIT;
9254                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9255                         cache = MTRR_TYPE_WRBACK;
9256                 else
9257                         cache = MTRR_TYPE_UNCACHABLE;
9258                 goto exit;
9259         }
9260
9261         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9262
9263 exit:
9264         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9265 }
9266
9267 static int vmx_get_lpage_level(void)
9268 {
9269         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9270                 return PT_DIRECTORY_LEVEL;
9271         else
9272                 /* For shadow and EPT supported 1GB page */
9273                 return PT_PDPE_LEVEL;
9274 }
9275
9276 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9277 {
9278         /*
9279          * These bits in the secondary execution controls field
9280          * are dynamic, the others are mostly based on the hypervisor
9281          * architecture and the guest's CPUID.  Do not touch the
9282          * dynamic bits.
9283          */
9284         u32 mask =
9285                 SECONDARY_EXEC_SHADOW_VMCS |
9286                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9287                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9288
9289         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9290
9291         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9292                      (new_ctl & ~mask) | (cur_ctl & mask));
9293 }
9294
9295 /*
9296  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9297  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9298  */
9299 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9300 {
9301         struct vcpu_vmx *vmx = to_vmx(vcpu);
9302         struct kvm_cpuid_entry2 *entry;
9303
9304         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9305         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9306
9307 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9308         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9309                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9310 } while (0)
9311
9312         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9313         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9314         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9315         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9316         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9317         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9318         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9319         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9320         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9321         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9322         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9323         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9324         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9325         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9326         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9327
9328         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9329         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9330         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9331         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9332         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9333         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9334         cr4_fixed1_update(bit(11),            ecx, bit(2));
9335
9336 #undef cr4_fixed1_update
9337 }
9338
9339 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9340 {
9341         struct kvm_cpuid_entry2 *best;
9342         struct vcpu_vmx *vmx = to_vmx(vcpu);
9343         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9344
9345         if (vmx_rdtscp_supported()) {
9346                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9347                 if (!rdtscp_enabled)
9348                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9349
9350                 if (nested) {
9351                         if (rdtscp_enabled)
9352                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9353                                         SECONDARY_EXEC_RDTSCP;
9354                         else
9355                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9356                                         ~SECONDARY_EXEC_RDTSCP;
9357                 }
9358         }
9359
9360         /* Exposing INVPCID only when PCID is exposed */
9361         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9362         if (vmx_invpcid_supported() &&
9363             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9364             !guest_cpuid_has_pcid(vcpu))) {
9365                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9366
9367                 if (best)
9368                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9369         }
9370
9371         if (cpu_has_secondary_exec_ctrls())
9372                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9373
9374         if (nested_vmx_allowed(vcpu))
9375                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9376                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9377         else
9378                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9379                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9380
9381         if (nested_vmx_allowed(vcpu))
9382                 nested_vmx_cr_fixed1_bits_update(vcpu);
9383 }
9384
9385 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9386 {
9387         if (func == 1 && nested)
9388                 entry->ecx |= bit(X86_FEATURE_VMX);
9389 }
9390
9391 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9392                 struct x86_exception *fault)
9393 {
9394         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9395         u32 exit_reason;
9396
9397         if (fault->error_code & PFERR_RSVD_MASK)
9398                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9399         else
9400                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9401         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9402         vmcs12->guest_physical_address = fault->address;
9403 }
9404
9405 /* Callbacks for nested_ept_init_mmu_context: */
9406
9407 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9408 {
9409         /* return the page table to be shadowed - in our case, EPT12 */
9410         return get_vmcs12(vcpu)->ept_pointer;
9411 }
9412
9413 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9414 {
9415         u64 eptp;
9416
9417         WARN_ON(mmu_is_nested(vcpu));
9418         eptp = nested_ept_get_cr3(vcpu);
9419         if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits)
9420                 return 1;
9421
9422         kvm_mmu_unload(vcpu);
9423         kvm_init_shadow_ept_mmu(vcpu,
9424                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9425                         VMX_EPT_EXECUTE_ONLY_BIT,
9426                         eptp & VMX_EPT_AD_ENABLE_BIT);
9427         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9428         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9429         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9430
9431         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9432         return 0;
9433 }
9434
9435 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9436 {
9437         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9438 }
9439
9440 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9441                                             u16 error_code)
9442 {
9443         bool inequality, bit;
9444
9445         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9446         inequality =
9447                 (error_code & vmcs12->page_fault_error_code_mask) !=
9448                  vmcs12->page_fault_error_code_match;
9449         return inequality ^ bit;
9450 }
9451
9452 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9453                 struct x86_exception *fault)
9454 {
9455         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9456
9457         WARN_ON(!is_guest_mode(vcpu));
9458
9459         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9460                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9461                                   vmcs_read32(VM_EXIT_INTR_INFO),
9462                                   vmcs_readl(EXIT_QUALIFICATION));
9463         else
9464                 kvm_inject_page_fault(vcpu, fault);
9465 }
9466
9467 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9468                                                struct vmcs12 *vmcs12);
9469
9470 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9471                                         struct vmcs12 *vmcs12)
9472 {
9473         struct vcpu_vmx *vmx = to_vmx(vcpu);
9474         u64 hpa;
9475
9476         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9477                 /*
9478                  * Translate L1 physical address to host physical
9479                  * address for vmcs02. Keep the page pinned, so this
9480                  * physical address remains valid. We keep a reference
9481                  * to it so we can release it later.
9482                  */
9483                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9484                         nested_release_page(vmx->nested.apic_access_page);
9485                 vmx->nested.apic_access_page =
9486                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9487                 /*
9488                  * If translation failed, no matter: This feature asks
9489                  * to exit when accessing the given address, and if it
9490                  * can never be accessed, this feature won't do
9491                  * anything anyway.
9492                  */
9493                 if (vmx->nested.apic_access_page) {
9494                         hpa = page_to_phys(vmx->nested.apic_access_page);
9495                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9496                 } else {
9497                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9498                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9499                 }
9500         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9501                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9502                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9503                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9504                 kvm_vcpu_reload_apic_access_page(vcpu);
9505         }
9506
9507         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9508                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9509                         nested_release_page(vmx->nested.virtual_apic_page);
9510                 vmx->nested.virtual_apic_page =
9511                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9512
9513                 /*
9514                  * If translation failed, VM entry will fail because
9515                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9516                  * Failing the vm entry is _not_ what the processor
9517                  * does but it's basically the only possibility we
9518                  * have.  We could still enter the guest if CR8 load
9519                  * exits are enabled, CR8 store exits are enabled, and
9520                  * virtualize APIC access is disabled; in this case
9521                  * the processor would never use the TPR shadow and we
9522                  * could simply clear the bit from the execution
9523                  * control.  But such a configuration is useless, so
9524                  * let's keep the code simple.
9525                  */
9526                 if (vmx->nested.virtual_apic_page) {
9527                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9528                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9529                 }
9530         }
9531
9532         if (nested_cpu_has_posted_intr(vmcs12)) {
9533                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9534                         kunmap(vmx->nested.pi_desc_page);
9535                         nested_release_page(vmx->nested.pi_desc_page);
9536                 }
9537                 vmx->nested.pi_desc_page =
9538                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9539                 vmx->nested.pi_desc =
9540                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9541                 if (!vmx->nested.pi_desc) {
9542                         nested_release_page_clean(vmx->nested.pi_desc_page);
9543                         return;
9544                 }
9545                 vmx->nested.pi_desc =
9546                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9547                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9548                         (PAGE_SIZE - 1)));
9549                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9550                         page_to_phys(vmx->nested.pi_desc_page) +
9551                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9552                         (PAGE_SIZE - 1)));
9553         }
9554         if (cpu_has_vmx_msr_bitmap() &&
9555             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9556             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9557                 ;
9558         else
9559                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9560                                 CPU_BASED_USE_MSR_BITMAPS);
9561 }
9562
9563 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9564 {
9565         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9566         struct vcpu_vmx *vmx = to_vmx(vcpu);
9567
9568         if (vcpu->arch.virtual_tsc_khz == 0)
9569                 return;
9570
9571         /* Make sure short timeouts reliably trigger an immediate vmexit.
9572          * hrtimer_start does not guarantee this. */
9573         if (preemption_timeout <= 1) {
9574                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9575                 return;
9576         }
9577
9578         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9579         preemption_timeout *= 1000000;
9580         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9581         hrtimer_start(&vmx->nested.preemption_timer,
9582                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9583 }
9584
9585 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9586                                                 struct vmcs12 *vmcs12)
9587 {
9588         int maxphyaddr;
9589         u64 addr;
9590
9591         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9592                 return 0;
9593
9594         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9595                 WARN_ON(1);
9596                 return -EINVAL;
9597         }
9598         maxphyaddr = cpuid_maxphyaddr(vcpu);
9599
9600         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9601            ((addr + PAGE_SIZE) >> maxphyaddr))
9602                 return -EINVAL;
9603
9604         return 0;
9605 }
9606
9607 /*
9608  * Merge L0's and L1's MSR bitmap, return false to indicate that
9609  * we do not use the hardware.
9610  */
9611 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9612                                                struct vmcs12 *vmcs12)
9613 {
9614         int msr;
9615         struct page *page;
9616         unsigned long *msr_bitmap_l1;
9617         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9618
9619         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9620         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9621                 return false;
9622
9623         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9624         if (!page)
9625                 return false;
9626         msr_bitmap_l1 = (unsigned long *)kmap(page);
9627
9628         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9629
9630         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9631                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9632                         for (msr = 0x800; msr <= 0x8ff; msr++)
9633                                 nested_vmx_disable_intercept_for_msr(
9634                                         msr_bitmap_l1, msr_bitmap_l0,
9635                                         msr, MSR_TYPE_R);
9636
9637                 nested_vmx_disable_intercept_for_msr(
9638                                 msr_bitmap_l1, msr_bitmap_l0,
9639                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9640                                 MSR_TYPE_R | MSR_TYPE_W);
9641
9642                 if (nested_cpu_has_vid(vmcs12)) {
9643                         nested_vmx_disable_intercept_for_msr(
9644                                 msr_bitmap_l1, msr_bitmap_l0,
9645                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9646                                 MSR_TYPE_W);
9647                         nested_vmx_disable_intercept_for_msr(
9648                                 msr_bitmap_l1, msr_bitmap_l0,
9649                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9650                                 MSR_TYPE_W);
9651                 }
9652         }
9653         kunmap(page);
9654         nested_release_page_clean(page);
9655
9656         return true;
9657 }
9658
9659 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9660                                            struct vmcs12 *vmcs12)
9661 {
9662         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9663             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9664             !nested_cpu_has_vid(vmcs12) &&
9665             !nested_cpu_has_posted_intr(vmcs12))
9666                 return 0;
9667
9668         /*
9669          * If virtualize x2apic mode is enabled,
9670          * virtualize apic access must be disabled.
9671          */
9672         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9673             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9674                 return -EINVAL;
9675
9676         /*
9677          * If virtual interrupt delivery is enabled,
9678          * we must exit on external interrupts.
9679          */
9680         if (nested_cpu_has_vid(vmcs12) &&
9681            !nested_exit_on_intr(vcpu))
9682                 return -EINVAL;
9683
9684         /*
9685          * bits 15:8 should be zero in posted_intr_nv,
9686          * the descriptor address has been already checked
9687          * in nested_get_vmcs12_pages.
9688          */
9689         if (nested_cpu_has_posted_intr(vmcs12) &&
9690            (!nested_cpu_has_vid(vmcs12) ||
9691             !nested_exit_intr_ack_set(vcpu) ||
9692             vmcs12->posted_intr_nv & 0xff00))
9693                 return -EINVAL;
9694
9695         /* tpr shadow is needed by all apicv features. */
9696         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9697                 return -EINVAL;
9698
9699         return 0;
9700 }
9701
9702 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9703                                        unsigned long count_field,
9704                                        unsigned long addr_field)
9705 {
9706         int maxphyaddr;
9707         u64 count, addr;
9708
9709         if (vmcs12_read_any(vcpu, count_field, &count) ||
9710             vmcs12_read_any(vcpu, addr_field, &addr)) {
9711                 WARN_ON(1);
9712                 return -EINVAL;
9713         }
9714         if (count == 0)
9715                 return 0;
9716         maxphyaddr = cpuid_maxphyaddr(vcpu);
9717         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9718             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9719                 pr_debug_ratelimited(
9720                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9721                         addr_field, maxphyaddr, count, addr);
9722                 return -EINVAL;
9723         }
9724         return 0;
9725 }
9726
9727 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9728                                                 struct vmcs12 *vmcs12)
9729 {
9730         if (vmcs12->vm_exit_msr_load_count == 0 &&
9731             vmcs12->vm_exit_msr_store_count == 0 &&
9732             vmcs12->vm_entry_msr_load_count == 0)
9733                 return 0; /* Fast path */
9734         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9735                                         VM_EXIT_MSR_LOAD_ADDR) ||
9736             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9737                                         VM_EXIT_MSR_STORE_ADDR) ||
9738             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9739                                         VM_ENTRY_MSR_LOAD_ADDR))
9740                 return -EINVAL;
9741         return 0;
9742 }
9743
9744 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9745                                        struct vmx_msr_entry *e)
9746 {
9747         /* x2APIC MSR accesses are not allowed */
9748         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9749                 return -EINVAL;
9750         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9751             e->index == MSR_IA32_UCODE_REV)
9752                 return -EINVAL;
9753         if (e->reserved != 0)
9754                 return -EINVAL;
9755         return 0;
9756 }
9757
9758 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9759                                      struct vmx_msr_entry *e)
9760 {
9761         if (e->index == MSR_FS_BASE ||
9762             e->index == MSR_GS_BASE ||
9763             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9764             nested_vmx_msr_check_common(vcpu, e))
9765                 return -EINVAL;
9766         return 0;
9767 }
9768
9769 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9770                                       struct vmx_msr_entry *e)
9771 {
9772         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9773             nested_vmx_msr_check_common(vcpu, e))
9774                 return -EINVAL;
9775         return 0;
9776 }
9777
9778 /*
9779  * Load guest's/host's msr at nested entry/exit.
9780  * return 0 for success, entry index for failure.
9781  */
9782 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9783 {
9784         u32 i;
9785         struct vmx_msr_entry e;
9786         struct msr_data msr;
9787
9788         msr.host_initiated = false;
9789         for (i = 0; i < count; i++) {
9790                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9791                                         &e, sizeof(e))) {
9792                         pr_debug_ratelimited(
9793                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9794                                 __func__, i, gpa + i * sizeof(e));
9795                         goto fail;
9796                 }
9797                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9798                         pr_debug_ratelimited(
9799                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9800                                 __func__, i, e.index, e.reserved);
9801                         goto fail;
9802                 }
9803                 msr.index = e.index;
9804                 msr.data = e.value;
9805                 if (kvm_set_msr(vcpu, &msr)) {
9806                         pr_debug_ratelimited(
9807                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9808                                 __func__, i, e.index, e.value);
9809                         goto fail;
9810                 }
9811         }
9812         return 0;
9813 fail:
9814         return i + 1;
9815 }
9816
9817 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9818 {
9819         u32 i;
9820         struct vmx_msr_entry e;
9821
9822         for (i = 0; i < count; i++) {
9823                 struct msr_data msr_info;
9824                 if (kvm_vcpu_read_guest(vcpu,
9825                                         gpa + i * sizeof(e),
9826                                         &e, 2 * sizeof(u32))) {
9827                         pr_debug_ratelimited(
9828                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9829                                 __func__, i, gpa + i * sizeof(e));
9830                         return -EINVAL;
9831                 }
9832                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9833                         pr_debug_ratelimited(
9834                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9835                                 __func__, i, e.index, e.reserved);
9836                         return -EINVAL;
9837                 }
9838                 msr_info.host_initiated = false;
9839                 msr_info.index = e.index;
9840                 if (kvm_get_msr(vcpu, &msr_info)) {
9841                         pr_debug_ratelimited(
9842                                 "%s cannot read MSR (%u, 0x%x)\n",
9843                                 __func__, i, e.index);
9844                         return -EINVAL;
9845                 }
9846                 if (kvm_vcpu_write_guest(vcpu,
9847                                          gpa + i * sizeof(e) +
9848                                              offsetof(struct vmx_msr_entry, value),
9849                                          &msr_info.data, sizeof(msr_info.data))) {
9850                         pr_debug_ratelimited(
9851                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9852                                 __func__, i, e.index, msr_info.data);
9853                         return -EINVAL;
9854                 }
9855         }
9856         return 0;
9857 }
9858
9859 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9860 {
9861         unsigned long invalid_mask;
9862
9863         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9864         return (val & invalid_mask) == 0;
9865 }
9866
9867 /*
9868  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9869  * emulating VM entry into a guest with EPT enabled.
9870  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9871  * is assigned to entry_failure_code on failure.
9872  */
9873 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9874                                u32 *entry_failure_code)
9875 {
9876         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9877                 if (!nested_cr3_valid(vcpu, cr3)) {
9878                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9879                         return 1;
9880                 }
9881
9882                 /*
9883                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9884                  * must not be dereferenced.
9885                  */
9886                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9887                     !nested_ept) {
9888                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9889                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9890                                 return 1;
9891                         }
9892                 }
9893
9894                 vcpu->arch.cr3 = cr3;
9895                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9896         }
9897
9898         kvm_mmu_reset_context(vcpu);
9899         return 0;
9900 }
9901
9902 /*
9903  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9904  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9905  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9906  * guest in a way that will both be appropriate to L1's requests, and our
9907  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9908  * function also has additional necessary side-effects, like setting various
9909  * vcpu->arch fields.
9910  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9911  * is assigned to entry_failure_code on failure.
9912  */
9913 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9914                           bool from_vmentry, u32 *entry_failure_code)
9915 {
9916         struct vcpu_vmx *vmx = to_vmx(vcpu);
9917         u32 exec_control;
9918
9919         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9920         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9921         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9922         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9923         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9924         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9925         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9926         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9927         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9928         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9929         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9930         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9931         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9932         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9933         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9934         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9935         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9936         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9937         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9938         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9939         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9940         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9941         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9942         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9943         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9944         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9945         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9946         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9947         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9948         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9949         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9950         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9951         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9952         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9953         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9954         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9955
9956         if (from_vmentry &&
9957             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
9958                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9959                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9960         } else {
9961                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9962                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9963         }
9964         if (from_vmentry) {
9965                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9966                              vmcs12->vm_entry_intr_info_field);
9967                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9968                              vmcs12->vm_entry_exception_error_code);
9969                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9970                              vmcs12->vm_entry_instruction_len);
9971                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9972                              vmcs12->guest_interruptibility_info);
9973         } else {
9974                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9975         }
9976         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9977         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9978         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9979                 vmcs12->guest_pending_dbg_exceptions);
9980         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9981         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9982
9983         if (nested_cpu_has_xsaves(vmcs12))
9984                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9985         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9986
9987         exec_control = vmcs12->pin_based_vm_exec_control;
9988
9989         /* Preemption timer setting is only taken from vmcs01.  */
9990         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9991         exec_control |= vmcs_config.pin_based_exec_ctrl;
9992         if (vmx->hv_deadline_tsc == -1)
9993                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9994
9995         /* Posted interrupts setting is only taken from vmcs12.  */
9996         if (nested_cpu_has_posted_intr(vmcs12)) {
9997                 /*
9998                  * Note that we use L0's vector here and in
9999                  * vmx_deliver_nested_posted_interrupt.
10000                  */
10001                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10002                 vmx->nested.pi_pending = false;
10003                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10004         } else {
10005                 exec_control &= ~PIN_BASED_POSTED_INTR;
10006         }
10007
10008         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10009
10010         vmx->nested.preemption_timer_expired = false;
10011         if (nested_cpu_has_preemption_timer(vmcs12))
10012                 vmx_start_preemption_timer(vcpu);
10013
10014         /*
10015          * Whether page-faults are trapped is determined by a combination of
10016          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10017          * If enable_ept, L0 doesn't care about page faults and we should
10018          * set all of these to L1's desires. However, if !enable_ept, L0 does
10019          * care about (at least some) page faults, and because it is not easy
10020          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10021          * to exit on each and every L2 page fault. This is done by setting
10022          * MASK=MATCH=0 and (see below) EB.PF=1.
10023          * Note that below we don't need special code to set EB.PF beyond the
10024          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10025          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10026          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10027          *
10028          * A problem with this approach (when !enable_ept) is that L1 may be
10029          * injected with more page faults than it asked for. This could have
10030          * caused problems, but in practice existing hypervisors don't care.
10031          * To fix this, we will need to emulate the PFEC checking (on the L1
10032          * page tables), using walk_addr(), when injecting PFs to L1.
10033          */
10034         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10035                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10036         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10037                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10038
10039         if (cpu_has_secondary_exec_ctrls()) {
10040                 exec_control = vmx_secondary_exec_control(vmx);
10041
10042                 /* Take the following fields only from vmcs12 */
10043                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10044                                   SECONDARY_EXEC_RDTSCP |
10045                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10046                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10047                 if (nested_cpu_has(vmcs12,
10048                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10049                         exec_control |= vmcs12->secondary_vm_exec_control;
10050
10051                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10052                         vmcs_write64(EOI_EXIT_BITMAP0,
10053                                 vmcs12->eoi_exit_bitmap0);
10054                         vmcs_write64(EOI_EXIT_BITMAP1,
10055                                 vmcs12->eoi_exit_bitmap1);
10056                         vmcs_write64(EOI_EXIT_BITMAP2,
10057                                 vmcs12->eoi_exit_bitmap2);
10058                         vmcs_write64(EOI_EXIT_BITMAP3,
10059                                 vmcs12->eoi_exit_bitmap3);
10060                         vmcs_write16(GUEST_INTR_STATUS,
10061                                 vmcs12->guest_intr_status);
10062                 }
10063
10064                 /*
10065                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10066                  * nested_get_vmcs12_pages will either fix it up or
10067                  * remove the VM execution control.
10068                  */
10069                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10070                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10071
10072                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10073         }
10074
10075
10076         /*
10077          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10078          * Some constant fields are set here by vmx_set_constant_host_state().
10079          * Other fields are different per CPU, and will be set later when
10080          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10081          */
10082         vmx_set_constant_host_state(vmx);
10083
10084         /*
10085          * Set the MSR load/store lists to match L0's settings.
10086          */
10087         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10088         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10089         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10090         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10091         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10092
10093         /*
10094          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10095          * entry, but only if the current (host) sp changed from the value
10096          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10097          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10098          * here we just force the write to happen on entry.
10099          */
10100         vmx->host_rsp = 0;
10101
10102         exec_control = vmx_exec_control(vmx); /* L0's desires */
10103         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10104         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10105         exec_control &= ~CPU_BASED_TPR_SHADOW;
10106         exec_control |= vmcs12->cpu_based_vm_exec_control;
10107
10108         /*
10109          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10110          * nested_get_vmcs12_pages can't fix it up, the illegal value
10111          * will result in a VM entry failure.
10112          */
10113         if (exec_control & CPU_BASED_TPR_SHADOW) {
10114                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10115                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10116         }
10117
10118         /*
10119          * Merging of IO bitmap not currently supported.
10120          * Rather, exit every time.
10121          */
10122         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10123         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10124
10125         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10126
10127         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10128          * bitwise-or of what L1 wants to trap for L2, and what we want to
10129          * trap. Note that CR0.TS also needs updating - we do this later.
10130          */
10131         update_exception_bitmap(vcpu);
10132         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10133         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10134
10135         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10136          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10137          * bits are further modified by vmx_set_efer() below.
10138          */
10139         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10140
10141         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10142          * emulated by vmx_set_efer(), below.
10143          */
10144         vm_entry_controls_init(vmx,
10145                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10146                         ~VM_ENTRY_IA32E_MODE) |
10147                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10148
10149         if (from_vmentry &&
10150             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10151                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10152                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10153         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10154                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10155         }
10156
10157         set_cr4_guest_host_mask(vmx);
10158
10159         if (from_vmentry &&
10160             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10161                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10162
10163         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10164                 vmcs_write64(TSC_OFFSET,
10165                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10166         else
10167                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10168         if (kvm_has_tsc_control)
10169                 decache_tsc_multiplier(vmx);
10170
10171         if (enable_vpid) {
10172                 /*
10173                  * There is no direct mapping between vpid02 and vpid12, the
10174                  * vpid02 is per-vCPU for L0 and reused while the value of
10175                  * vpid12 is changed w/ one invvpid during nested vmentry.
10176                  * The vpid12 is allocated by L1 for L2, so it will not
10177                  * influence global bitmap(for vpid01 and vpid02 allocation)
10178                  * even if spawn a lot of nested vCPUs.
10179                  */
10180                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10181                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10182                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10183                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10184                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10185                         }
10186                 } else {
10187                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10188                         vmx_flush_tlb(vcpu);
10189                 }
10190
10191         }
10192
10193         if (nested_cpu_has_ept(vmcs12)) {
10194                 if (nested_ept_init_mmu_context(vcpu)) {
10195                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10196                         return 1;
10197                 }
10198         } else if (nested_cpu_has2(vmcs12,
10199                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10200                 vmx_flush_tlb_ept_only(vcpu);
10201         }
10202
10203         /*
10204          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10205          * bits which we consider mandatory enabled.
10206          * The CR0_READ_SHADOW is what L2 should have expected to read given
10207          * the specifications by L1; It's not enough to take
10208          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10209          * have more bits than L1 expected.
10210          */
10211         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10212         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10213
10214         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10215         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10216
10217         if (from_vmentry &&
10218             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10219                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10220         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10221                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10222         else
10223                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10224         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10225         vmx_set_efer(vcpu, vcpu->arch.efer);
10226
10227         /* Shadow page tables on either EPT or shadow page tables. */
10228         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10229                                 entry_failure_code))
10230                 return 1;
10231
10232         if (!enable_ept)
10233                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10234
10235         /*
10236          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10237          */
10238         if (enable_ept) {
10239                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10240                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10241                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10242                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10243         }
10244
10245         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10246         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10247         return 0;
10248 }
10249
10250 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10251 {
10252         struct vcpu_vmx *vmx = to_vmx(vcpu);
10253
10254         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10255             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10256                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10257
10258         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10259                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10260
10261         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10262                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10263
10264         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10265                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10266
10267         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10268                                 vmx->nested.nested_vmx_procbased_ctls_low,
10269                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10270             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10271                                 vmx->nested.nested_vmx_secondary_ctls_low,
10272                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10273             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10274                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10275                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10276             !vmx_control_verify(vmcs12->vm_exit_controls,
10277                                 vmx->nested.nested_vmx_exit_ctls_low,
10278                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10279             !vmx_control_verify(vmcs12->vm_entry_controls,
10280                                 vmx->nested.nested_vmx_entry_ctls_low,
10281                                 vmx->nested.nested_vmx_entry_ctls_high))
10282                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10283
10284         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10285             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10286             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10287                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10288
10289         return 0;
10290 }
10291
10292 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10293                                   u32 *exit_qual)
10294 {
10295         bool ia32e;
10296
10297         *exit_qual = ENTRY_FAIL_DEFAULT;
10298
10299         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10300             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10301                 return 1;
10302
10303         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10304             vmcs12->vmcs_link_pointer != -1ull) {
10305                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10306                 return 1;
10307         }
10308
10309         /*
10310          * If the load IA32_EFER VM-entry control is 1, the following checks
10311          * are performed on the field for the IA32_EFER MSR:
10312          * - Bits reserved in the IA32_EFER MSR must be 0.
10313          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10314          *   the IA-32e mode guest VM-exit control. It must also be identical
10315          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10316          *   CR0.PG) is 1.
10317          */
10318         if (to_vmx(vcpu)->nested.nested_run_pending &&
10319             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10320                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10321                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10322                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10323                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10324                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10325                         return 1;
10326         }
10327
10328         /*
10329          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10330          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10331          * the values of the LMA and LME bits in the field must each be that of
10332          * the host address-space size VM-exit control.
10333          */
10334         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10335                 ia32e = (vmcs12->vm_exit_controls &
10336                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10337                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10338                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10339                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10340                         return 1;
10341         }
10342
10343         return 0;
10344 }
10345
10346 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10347 {
10348         struct vcpu_vmx *vmx = to_vmx(vcpu);
10349         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10350         struct loaded_vmcs *vmcs02;
10351         u32 msr_entry_idx;
10352         u32 exit_qual;
10353
10354         vmcs02 = nested_get_current_vmcs02(vmx);
10355         if (!vmcs02)
10356                 return -ENOMEM;
10357
10358         enter_guest_mode(vcpu);
10359
10360         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10361                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10362
10363         vmx_switch_vmcs(vcpu, vmcs02);
10364         vmx_segment_cache_clear(vmx);
10365
10366         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10367                 leave_guest_mode(vcpu);
10368                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10369                 nested_vmx_entry_failure(vcpu, vmcs12,
10370                                          EXIT_REASON_INVALID_STATE, exit_qual);
10371                 return 1;
10372         }
10373
10374         nested_get_vmcs12_pages(vcpu, vmcs12);
10375
10376         msr_entry_idx = nested_vmx_load_msr(vcpu,
10377                                             vmcs12->vm_entry_msr_load_addr,
10378                                             vmcs12->vm_entry_msr_load_count);
10379         if (msr_entry_idx) {
10380                 leave_guest_mode(vcpu);
10381                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10382                 nested_vmx_entry_failure(vcpu, vmcs12,
10383                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10384                 return 1;
10385         }
10386
10387         vmcs12->launch_state = 1;
10388
10389         /*
10390          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10391          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10392          * returned as far as L1 is concerned. It will only return (and set
10393          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10394          */
10395         return 0;
10396 }
10397
10398 /*
10399  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10400  * for running an L2 nested guest.
10401  */
10402 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10403 {
10404         struct vmcs12 *vmcs12;
10405         struct vcpu_vmx *vmx = to_vmx(vcpu);
10406         u32 exit_qual;
10407         int ret;
10408
10409         if (!nested_vmx_check_permission(vcpu))
10410                 return 1;
10411
10412         if (!nested_vmx_check_vmcs12(vcpu))
10413                 goto out;
10414
10415         vmcs12 = get_vmcs12(vcpu);
10416
10417         if (enable_shadow_vmcs)
10418                 copy_shadow_to_vmcs12(vmx);
10419
10420         /*
10421          * The nested entry process starts with enforcing various prerequisites
10422          * on vmcs12 as required by the Intel SDM, and act appropriately when
10423          * they fail: As the SDM explains, some conditions should cause the
10424          * instruction to fail, while others will cause the instruction to seem
10425          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10426          * To speed up the normal (success) code path, we should avoid checking
10427          * for misconfigurations which will anyway be caught by the processor
10428          * when using the merged vmcs02.
10429          */
10430         if (vmcs12->launch_state == launch) {
10431                 nested_vmx_failValid(vcpu,
10432                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10433                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10434                 goto out;
10435         }
10436
10437         ret = check_vmentry_prereqs(vcpu, vmcs12);
10438         if (ret) {
10439                 nested_vmx_failValid(vcpu, ret);
10440                 goto out;
10441         }
10442
10443         /*
10444          * After this point, the trap flag no longer triggers a singlestep trap
10445          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10446          * This is not 100% correct; for performance reasons, we delegate most
10447          * of the checks on host state to the processor.  If those fail,
10448          * the singlestep trap is missed.
10449          */
10450         skip_emulated_instruction(vcpu);
10451
10452         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10453         if (ret) {
10454                 nested_vmx_entry_failure(vcpu, vmcs12,
10455                                          EXIT_REASON_INVALID_STATE, exit_qual);
10456                 return 1;
10457         }
10458
10459         /*
10460          * We're finally done with prerequisite checking, and can start with
10461          * the nested entry.
10462          */
10463
10464         ret = enter_vmx_non_root_mode(vcpu, true);
10465         if (ret)
10466                 return ret;
10467
10468         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10469                 return kvm_vcpu_halt(vcpu);
10470
10471         vmx->nested.nested_run_pending = 1;
10472
10473         return 1;
10474
10475 out:
10476         return kvm_skip_emulated_instruction(vcpu);
10477 }
10478
10479 /*
10480  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10481  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10482  * This function returns the new value we should put in vmcs12.guest_cr0.
10483  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10484  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10485  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10486  *     didn't trap the bit, because if L1 did, so would L0).
10487  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10488  *     been modified by L2, and L1 knows it. So just leave the old value of
10489  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10490  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10491  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10492  *     changed these bits, and therefore they need to be updated, but L0
10493  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10494  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10495  */
10496 static inline unsigned long
10497 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10498 {
10499         return
10500         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10501         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10502         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10503                         vcpu->arch.cr0_guest_owned_bits));
10504 }
10505
10506 static inline unsigned long
10507 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10508 {
10509         return
10510         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10511         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10512         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10513                         vcpu->arch.cr4_guest_owned_bits));
10514 }
10515
10516 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10517                                        struct vmcs12 *vmcs12)
10518 {
10519         u32 idt_vectoring;
10520         unsigned int nr;
10521
10522         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10523                 nr = vcpu->arch.exception.nr;
10524                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10525
10526                 if (kvm_exception_is_soft(nr)) {
10527                         vmcs12->vm_exit_instruction_len =
10528                                 vcpu->arch.event_exit_inst_len;
10529                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10530                 } else
10531                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10532
10533                 if (vcpu->arch.exception.has_error_code) {
10534                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10535                         vmcs12->idt_vectoring_error_code =
10536                                 vcpu->arch.exception.error_code;
10537                 }
10538
10539                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10540         } else if (vcpu->arch.nmi_injected) {
10541                 vmcs12->idt_vectoring_info_field =
10542                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10543         } else if (vcpu->arch.interrupt.pending) {
10544                 nr = vcpu->arch.interrupt.nr;
10545                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10546
10547                 if (vcpu->arch.interrupt.soft) {
10548                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10549                         vmcs12->vm_entry_instruction_len =
10550                                 vcpu->arch.event_exit_inst_len;
10551                 } else
10552                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10553
10554                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10555         }
10556 }
10557
10558 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10559 {
10560         struct vcpu_vmx *vmx = to_vmx(vcpu);
10561
10562         if (vcpu->arch.exception.pending ||
10563                 vcpu->arch.nmi_injected ||
10564                 vcpu->arch.interrupt.pending)
10565                 return -EBUSY;
10566
10567         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10568             vmx->nested.preemption_timer_expired) {
10569                 if (vmx->nested.nested_run_pending)
10570                         return -EBUSY;
10571                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10572                 return 0;
10573         }
10574
10575         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10576                 if (vmx->nested.nested_run_pending)
10577                         return -EBUSY;
10578                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10579                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10580                                   INTR_INFO_VALID_MASK, 0);
10581                 /*
10582                  * The NMI-triggered VM exit counts as injection:
10583                  * clear this one and block further NMIs.
10584                  */
10585                 vcpu->arch.nmi_pending = 0;
10586                 vmx_set_nmi_mask(vcpu, true);
10587                 return 0;
10588         }
10589
10590         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10591             nested_exit_on_intr(vcpu)) {
10592                 if (vmx->nested.nested_run_pending)
10593                         return -EBUSY;
10594                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10595                 return 0;
10596         }
10597
10598         vmx_complete_nested_posted_interrupt(vcpu);
10599         return 0;
10600 }
10601
10602 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10603 {
10604         ktime_t remaining =
10605                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10606         u64 value;
10607
10608         if (ktime_to_ns(remaining) <= 0)
10609                 return 0;
10610
10611         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10612         do_div(value, 1000000);
10613         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10614 }
10615
10616 /*
10617  * Update the guest state fields of vmcs12 to reflect changes that
10618  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10619  * VM-entry controls is also updated, since this is really a guest
10620  * state bit.)
10621  */
10622 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10623 {
10624         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10625         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10626
10627         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10628         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10629         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10630
10631         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10632         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10633         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10634         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10635         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10636         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10637         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10638         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10639         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10640         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10641         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10642         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10643         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10644         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10645         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10646         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10647         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10648         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10649         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10650         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10651         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10652         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10653         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10654         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10655         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10656         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10657         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10658         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10659         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10660         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10661         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10662         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10663         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10664         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10665         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10666         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10667
10668         vmcs12->guest_interruptibility_info =
10669                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10670         vmcs12->guest_pending_dbg_exceptions =
10671                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10672         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10673                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10674         else
10675                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10676
10677         if (nested_cpu_has_preemption_timer(vmcs12)) {
10678                 if (vmcs12->vm_exit_controls &
10679                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10680                         vmcs12->vmx_preemption_timer_value =
10681                                 vmx_get_preemption_timer_value(vcpu);
10682                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10683         }
10684
10685         /*
10686          * In some cases (usually, nested EPT), L2 is allowed to change its
10687          * own CR3 without exiting. If it has changed it, we must keep it.
10688          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10689          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10690          *
10691          * Additionally, restore L2's PDPTR to vmcs12.
10692          */
10693         if (enable_ept) {
10694                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10695                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10696                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10697                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10698                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10699         }
10700
10701         if (nested_cpu_has_ept(vmcs12))
10702                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10703
10704         if (nested_cpu_has_vid(vmcs12))
10705                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10706
10707         vmcs12->vm_entry_controls =
10708                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10709                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10710
10711         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10712                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10713                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10714         }
10715
10716         /* TODO: These cannot have changed unless we have MSR bitmaps and
10717          * the relevant bit asks not to trap the change */
10718         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10719                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10720         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10721                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10722         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10723         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10724         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10725         if (kvm_mpx_supported())
10726                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10727         if (nested_cpu_has_xsaves(vmcs12))
10728                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10729 }
10730
10731 /*
10732  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10733  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10734  * and this function updates it to reflect the changes to the guest state while
10735  * L2 was running (and perhaps made some exits which were handled directly by L0
10736  * without going back to L1), and to reflect the exit reason.
10737  * Note that we do not have to copy here all VMCS fields, just those that
10738  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10739  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10740  * which already writes to vmcs12 directly.
10741  */
10742 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10743                            u32 exit_reason, u32 exit_intr_info,
10744                            unsigned long exit_qualification)
10745 {
10746         /* update guest state fields: */
10747         sync_vmcs12(vcpu, vmcs12);
10748
10749         /* update exit information fields: */
10750
10751         vmcs12->vm_exit_reason = exit_reason;
10752         vmcs12->exit_qualification = exit_qualification;
10753
10754         vmcs12->vm_exit_intr_info = exit_intr_info;
10755         if ((vmcs12->vm_exit_intr_info &
10756              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10757             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10758                 vmcs12->vm_exit_intr_error_code =
10759                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10760         vmcs12->idt_vectoring_info_field = 0;
10761         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10762         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10763
10764         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10765                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10766                  * instead of reading the real value. */
10767                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10768
10769                 /*
10770                  * Transfer the event that L0 or L1 may wanted to inject into
10771                  * L2 to IDT_VECTORING_INFO_FIELD.
10772                  */
10773                 vmcs12_save_pending_event(vcpu, vmcs12);
10774         }
10775
10776         /*
10777          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10778          * preserved above and would only end up incorrectly in L1.
10779          */
10780         vcpu->arch.nmi_injected = false;
10781         kvm_clear_exception_queue(vcpu);
10782         kvm_clear_interrupt_queue(vcpu);
10783 }
10784
10785 /*
10786  * A part of what we need to when the nested L2 guest exits and we want to
10787  * run its L1 parent, is to reset L1's guest state to the host state specified
10788  * in vmcs12.
10789  * This function is to be called not only on normal nested exit, but also on
10790  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10791  * Failures During or After Loading Guest State").
10792  * This function should be called when the active VMCS is L1's (vmcs01).
10793  */
10794 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10795                                    struct vmcs12 *vmcs12)
10796 {
10797         struct kvm_segment seg;
10798         u32 entry_failure_code;
10799
10800         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10801                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10802         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10803                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10804         else
10805                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10806         vmx_set_efer(vcpu, vcpu->arch.efer);
10807
10808         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10809         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10810         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10811         /*
10812          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10813          * actually changed, because vmx_set_cr0 refers to efer set above.
10814          *
10815          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10816          * (KVM doesn't change it);
10817          */
10818         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10819         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10820
10821         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10822         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10823         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10824
10825         nested_ept_uninit_mmu_context(vcpu);
10826
10827         /*
10828          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10829          * couldn't have changed.
10830          */
10831         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10832                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10833
10834         if (!enable_ept)
10835                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10836
10837         if (enable_vpid) {
10838                 /*
10839                  * Trivially support vpid by letting L2s share their parent
10840                  * L1's vpid. TODO: move to a more elaborate solution, giving
10841                  * each L2 its own vpid and exposing the vpid feature to L1.
10842                  */
10843                 vmx_flush_tlb(vcpu);
10844         }
10845
10846
10847         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10848         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10849         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10850         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10851         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10852
10853         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10854         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10855                 vmcs_write64(GUEST_BNDCFGS, 0);
10856
10857         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10858                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10859                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10860         }
10861         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10862                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10863                         vmcs12->host_ia32_perf_global_ctrl);
10864
10865         /* Set L1 segment info according to Intel SDM
10866             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10867         seg = (struct kvm_segment) {
10868                 .base = 0,
10869                 .limit = 0xFFFFFFFF,
10870                 .selector = vmcs12->host_cs_selector,
10871                 .type = 11,
10872                 .present = 1,
10873                 .s = 1,
10874                 .g = 1
10875         };
10876         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10877                 seg.l = 1;
10878         else
10879                 seg.db = 1;
10880         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10881         seg = (struct kvm_segment) {
10882                 .base = 0,
10883                 .limit = 0xFFFFFFFF,
10884                 .type = 3,
10885                 .present = 1,
10886                 .s = 1,
10887                 .db = 1,
10888                 .g = 1
10889         };
10890         seg.selector = vmcs12->host_ds_selector;
10891         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10892         seg.selector = vmcs12->host_es_selector;
10893         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10894         seg.selector = vmcs12->host_ss_selector;
10895         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10896         seg.selector = vmcs12->host_fs_selector;
10897         seg.base = vmcs12->host_fs_base;
10898         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10899         seg.selector = vmcs12->host_gs_selector;
10900         seg.base = vmcs12->host_gs_base;
10901         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10902         seg = (struct kvm_segment) {
10903                 .base = vmcs12->host_tr_base,
10904                 .limit = 0x67,
10905                 .selector = vmcs12->host_tr_selector,
10906                 .type = 11,
10907                 .present = 1
10908         };
10909         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10910
10911         kvm_set_dr(vcpu, 7, 0x400);
10912         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10913
10914         if (cpu_has_vmx_msr_bitmap())
10915                 vmx_set_msr_bitmap(vcpu);
10916
10917         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10918                                 vmcs12->vm_exit_msr_load_count))
10919                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10920 }
10921
10922 /*
10923  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10924  * and modify vmcs12 to make it see what it would expect to see there if
10925  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10926  */
10927 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10928                               u32 exit_intr_info,
10929                               unsigned long exit_qualification)
10930 {
10931         struct vcpu_vmx *vmx = to_vmx(vcpu);
10932         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10933         u32 vm_inst_error = 0;
10934
10935         /* trying to cancel vmlaunch/vmresume is a bug */
10936         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10937
10938         leave_guest_mode(vcpu);
10939         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10940                        exit_qualification);
10941
10942         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10943                                  vmcs12->vm_exit_msr_store_count))
10944                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10945
10946         if (unlikely(vmx->fail))
10947                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10948
10949         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10950
10951         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10952             && nested_exit_intr_ack_set(vcpu)) {
10953                 int irq = kvm_cpu_get_interrupt(vcpu);
10954                 WARN_ON(irq < 0);
10955                 vmcs12->vm_exit_intr_info = irq |
10956                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10957         }
10958
10959         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10960                                        vmcs12->exit_qualification,
10961                                        vmcs12->idt_vectoring_info_field,
10962                                        vmcs12->vm_exit_intr_info,
10963                                        vmcs12->vm_exit_intr_error_code,
10964                                        KVM_ISA_VMX);
10965
10966         vm_entry_controls_reset_shadow(vmx);
10967         vm_exit_controls_reset_shadow(vmx);
10968         vmx_segment_cache_clear(vmx);
10969
10970         /* if no vmcs02 cache requested, remove the one we used */
10971         if (VMCS02_POOL_SIZE == 0)
10972                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10973
10974         load_vmcs12_host_state(vcpu, vmcs12);
10975
10976         /* Update any VMCS fields that might have changed while L2 ran */
10977         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10978         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10979         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10980         if (vmx->hv_deadline_tsc == -1)
10981                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10982                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10983         else
10984                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10985                               PIN_BASED_VMX_PREEMPTION_TIMER);
10986         if (kvm_has_tsc_control)
10987                 decache_tsc_multiplier(vmx);
10988
10989         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10990                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10991                 vmx_set_virtual_x2apic_mode(vcpu,
10992                                 vcpu->arch.apic_base & X2APIC_ENABLE);
10993         } else if (!nested_cpu_has_ept(vmcs12) &&
10994                    nested_cpu_has2(vmcs12,
10995                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10996                 vmx_flush_tlb_ept_only(vcpu);
10997         }
10998
10999         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11000         vmx->host_rsp = 0;
11001
11002         /* Unpin physical memory we referred to in vmcs02 */
11003         if (vmx->nested.apic_access_page) {
11004                 nested_release_page(vmx->nested.apic_access_page);
11005                 vmx->nested.apic_access_page = NULL;
11006         }
11007         if (vmx->nested.virtual_apic_page) {
11008                 nested_release_page(vmx->nested.virtual_apic_page);
11009                 vmx->nested.virtual_apic_page = NULL;
11010         }
11011         if (vmx->nested.pi_desc_page) {
11012                 kunmap(vmx->nested.pi_desc_page);
11013                 nested_release_page(vmx->nested.pi_desc_page);
11014                 vmx->nested.pi_desc_page = NULL;
11015                 vmx->nested.pi_desc = NULL;
11016         }
11017
11018         /*
11019          * We are now running in L2, mmu_notifier will force to reload the
11020          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11021          */
11022         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11023
11024         /*
11025          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11026          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11027          * success or failure flag accordingly.
11028          */
11029         if (unlikely(vmx->fail)) {
11030                 vmx->fail = 0;
11031                 nested_vmx_failValid(vcpu, vm_inst_error);
11032         } else
11033                 nested_vmx_succeed(vcpu);
11034         if (enable_shadow_vmcs)
11035                 vmx->nested.sync_shadow_vmcs = true;
11036
11037         /* in case we halted in L2 */
11038         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11039 }
11040
11041 /*
11042  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11043  */
11044 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11045 {
11046         if (is_guest_mode(vcpu)) {
11047                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11048                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11049         }
11050         free_nested(to_vmx(vcpu));
11051 }
11052
11053 /*
11054  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11055  * 23.7 "VM-entry failures during or after loading guest state" (this also
11056  * lists the acceptable exit-reason and exit-qualification parameters).
11057  * It should only be called before L2 actually succeeded to run, and when
11058  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11059  */
11060 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11061                         struct vmcs12 *vmcs12,
11062                         u32 reason, unsigned long qualification)
11063 {
11064         load_vmcs12_host_state(vcpu, vmcs12);
11065         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11066         vmcs12->exit_qualification = qualification;
11067         nested_vmx_succeed(vcpu);
11068         if (enable_shadow_vmcs)
11069                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11070 }
11071
11072 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11073                                struct x86_instruction_info *info,
11074                                enum x86_intercept_stage stage)
11075 {
11076         return X86EMUL_CONTINUE;
11077 }
11078
11079 #ifdef CONFIG_X86_64
11080 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11081 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11082                                   u64 divisor, u64 *result)
11083 {
11084         u64 low = a << shift, high = a >> (64 - shift);
11085
11086         /* To avoid the overflow on divq */
11087         if (high >= divisor)
11088                 return 1;
11089
11090         /* Low hold the result, high hold rem which is discarded */
11091         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11092             "rm" (divisor), "0" (low), "1" (high));
11093         *result = low;
11094
11095         return 0;
11096 }
11097
11098 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11099 {
11100         struct vcpu_vmx *vmx = to_vmx(vcpu);
11101         u64 tscl = rdtsc();
11102         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11103         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11104
11105         /* Convert to host delta tsc if tsc scaling is enabled */
11106         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11107                         u64_shl_div_u64(delta_tsc,
11108                                 kvm_tsc_scaling_ratio_frac_bits,
11109                                 vcpu->arch.tsc_scaling_ratio,
11110                                 &delta_tsc))
11111                 return -ERANGE;
11112
11113         /*
11114          * If the delta tsc can't fit in the 32 bit after the multi shift,
11115          * we can't use the preemption timer.
11116          * It's possible that it fits on later vmentries, but checking
11117          * on every vmentry is costly so we just use an hrtimer.
11118          */
11119         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11120                 return -ERANGE;
11121
11122         vmx->hv_deadline_tsc = tscl + delta_tsc;
11123         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11124                         PIN_BASED_VMX_PREEMPTION_TIMER);
11125         return 0;
11126 }
11127
11128 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11129 {
11130         struct vcpu_vmx *vmx = to_vmx(vcpu);
11131         vmx->hv_deadline_tsc = -1;
11132         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11133                         PIN_BASED_VMX_PREEMPTION_TIMER);
11134 }
11135 #endif
11136
11137 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11138 {
11139         if (ple_gap)
11140                 shrink_ple_window(vcpu);
11141 }
11142
11143 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11144                                      struct kvm_memory_slot *slot)
11145 {
11146         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11147         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11148 }
11149
11150 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11151                                        struct kvm_memory_slot *slot)
11152 {
11153         kvm_mmu_slot_set_dirty(kvm, slot);
11154 }
11155
11156 static void vmx_flush_log_dirty(struct kvm *kvm)
11157 {
11158         kvm_flush_pml_buffers(kvm);
11159 }
11160
11161 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11162                                            struct kvm_memory_slot *memslot,
11163                                            gfn_t offset, unsigned long mask)
11164 {
11165         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11166 }
11167
11168 /*
11169  * This routine does the following things for vCPU which is going
11170  * to be blocked if VT-d PI is enabled.
11171  * - Store the vCPU to the wakeup list, so when interrupts happen
11172  *   we can find the right vCPU to wake up.
11173  * - Change the Posted-interrupt descriptor as below:
11174  *      'NDST' <-- vcpu->pre_pcpu
11175  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11176  * - If 'ON' is set during this process, which means at least one
11177  *   interrupt is posted for this vCPU, we cannot block it, in
11178  *   this case, return 1, otherwise, return 0.
11179  *
11180  */
11181 static int pi_pre_block(struct kvm_vcpu *vcpu)
11182 {
11183         unsigned long flags;
11184         unsigned int dest;
11185         struct pi_desc old, new;
11186         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11187
11188         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11189                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11190                 !kvm_vcpu_apicv_active(vcpu))
11191                 return 0;
11192
11193         vcpu->pre_pcpu = vcpu->cpu;
11194         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11195                           vcpu->pre_pcpu), flags);
11196         list_add_tail(&vcpu->blocked_vcpu_list,
11197                       &per_cpu(blocked_vcpu_on_cpu,
11198                       vcpu->pre_pcpu));
11199         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11200                                vcpu->pre_pcpu), flags);
11201
11202         do {
11203                 old.control = new.control = pi_desc->control;
11204
11205                 /*
11206                  * We should not block the vCPU if
11207                  * an interrupt is posted for it.
11208                  */
11209                 if (pi_test_on(pi_desc) == 1) {
11210                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11211                                           vcpu->pre_pcpu), flags);
11212                         list_del(&vcpu->blocked_vcpu_list);
11213                         spin_unlock_irqrestore(
11214                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11215                                         vcpu->pre_pcpu), flags);
11216                         vcpu->pre_pcpu = -1;
11217
11218                         return 1;
11219                 }
11220
11221                 WARN((pi_desc->sn == 1),
11222                      "Warning: SN field of posted-interrupts "
11223                      "is set before blocking\n");
11224
11225                 /*
11226                  * Since vCPU can be preempted during this process,
11227                  * vcpu->cpu could be different with pre_pcpu, we
11228                  * need to set pre_pcpu as the destination of wakeup
11229                  * notification event, then we can find the right vCPU
11230                  * to wakeup in wakeup handler if interrupts happen
11231                  * when the vCPU is in blocked state.
11232                  */
11233                 dest = cpu_physical_id(vcpu->pre_pcpu);
11234
11235                 if (x2apic_enabled())
11236                         new.ndst = dest;
11237                 else
11238                         new.ndst = (dest << 8) & 0xFF00;
11239
11240                 /* set 'NV' to 'wakeup vector' */
11241                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11242         } while (cmpxchg(&pi_desc->control, old.control,
11243                         new.control) != old.control);
11244
11245         return 0;
11246 }
11247
11248 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11249 {
11250         if (pi_pre_block(vcpu))
11251                 return 1;
11252
11253         if (kvm_lapic_hv_timer_in_use(vcpu))
11254                 kvm_lapic_switch_to_sw_timer(vcpu);
11255
11256         return 0;
11257 }
11258
11259 static void pi_post_block(struct kvm_vcpu *vcpu)
11260 {
11261         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11262         struct pi_desc old, new;
11263         unsigned int dest;
11264         unsigned long flags;
11265
11266         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11267                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11268                 !kvm_vcpu_apicv_active(vcpu))
11269                 return;
11270
11271         do {
11272                 old.control = new.control = pi_desc->control;
11273
11274                 dest = cpu_physical_id(vcpu->cpu);
11275
11276                 if (x2apic_enabled())
11277                         new.ndst = dest;
11278                 else
11279                         new.ndst = (dest << 8) & 0xFF00;
11280
11281                 /* Allow posting non-urgent interrupts */
11282                 new.sn = 0;
11283
11284                 /* set 'NV' to 'notification vector' */
11285                 new.nv = POSTED_INTR_VECTOR;
11286         } while (cmpxchg(&pi_desc->control, old.control,
11287                         new.control) != old.control);
11288
11289         if(vcpu->pre_pcpu != -1) {
11290                 spin_lock_irqsave(
11291                         &per_cpu(blocked_vcpu_on_cpu_lock,
11292                         vcpu->pre_pcpu), flags);
11293                 list_del(&vcpu->blocked_vcpu_list);
11294                 spin_unlock_irqrestore(
11295                         &per_cpu(blocked_vcpu_on_cpu_lock,
11296                         vcpu->pre_pcpu), flags);
11297                 vcpu->pre_pcpu = -1;
11298         }
11299 }
11300
11301 static void vmx_post_block(struct kvm_vcpu *vcpu)
11302 {
11303         if (kvm_x86_ops->set_hv_timer)
11304                 kvm_lapic_switch_to_hv_timer(vcpu);
11305
11306         pi_post_block(vcpu);
11307 }
11308
11309 /*
11310  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11311  *
11312  * @kvm: kvm
11313  * @host_irq: host irq of the interrupt
11314  * @guest_irq: gsi of the interrupt
11315  * @set: set or unset PI
11316  * returns 0 on success, < 0 on failure
11317  */
11318 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11319                               uint32_t guest_irq, bool set)
11320 {
11321         struct kvm_kernel_irq_routing_entry *e;
11322         struct kvm_irq_routing_table *irq_rt;
11323         struct kvm_lapic_irq irq;
11324         struct kvm_vcpu *vcpu;
11325         struct vcpu_data vcpu_info;
11326         int idx, ret = -EINVAL;
11327
11328         if (!kvm_arch_has_assigned_device(kvm) ||
11329                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11330                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11331                 return 0;
11332
11333         idx = srcu_read_lock(&kvm->irq_srcu);
11334         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11335         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11336
11337         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11338                 if (e->type != KVM_IRQ_ROUTING_MSI)
11339                         continue;
11340                 /*
11341                  * VT-d PI cannot support posting multicast/broadcast
11342                  * interrupts to a vCPU, we still use interrupt remapping
11343                  * for these kind of interrupts.
11344                  *
11345                  * For lowest-priority interrupts, we only support
11346                  * those with single CPU as the destination, e.g. user
11347                  * configures the interrupts via /proc/irq or uses
11348                  * irqbalance to make the interrupts single-CPU.
11349                  *
11350                  * We will support full lowest-priority interrupt later.
11351                  */
11352
11353                 kvm_set_msi_irq(kvm, e, &irq);
11354                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11355                         /*
11356                          * Make sure the IRTE is in remapped mode if
11357                          * we don't handle it in posted mode.
11358                          */
11359                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11360                         if (ret < 0) {
11361                                 printk(KERN_INFO
11362                                    "failed to back to remapped mode, irq: %u\n",
11363                                    host_irq);
11364                                 goto out;
11365                         }
11366
11367                         continue;
11368                 }
11369
11370                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11371                 vcpu_info.vector = irq.vector;
11372
11373                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11374                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11375
11376                 if (set)
11377                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11378                 else {
11379                         /* suppress notification event before unposting */
11380                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11381                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11382                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11383                 }
11384
11385                 if (ret < 0) {
11386                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11387                                         __func__);
11388                         goto out;
11389                 }
11390         }
11391
11392         ret = 0;
11393 out:
11394         srcu_read_unlock(&kvm->irq_srcu, idx);
11395         return ret;
11396 }
11397
11398 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11399 {
11400         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11401                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11402                         FEATURE_CONTROL_LMCE;
11403         else
11404                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11405                         ~FEATURE_CONTROL_LMCE;
11406 }
11407
11408 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11409         .cpu_has_kvm_support = cpu_has_kvm_support,
11410         .disabled_by_bios = vmx_disabled_by_bios,
11411         .hardware_setup = hardware_setup,
11412         .hardware_unsetup = hardware_unsetup,
11413         .check_processor_compatibility = vmx_check_processor_compat,
11414         .hardware_enable = hardware_enable,
11415         .hardware_disable = hardware_disable,
11416         .cpu_has_accelerated_tpr = report_flexpriority,
11417         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11418
11419         .vcpu_create = vmx_create_vcpu,
11420         .vcpu_free = vmx_free_vcpu,
11421         .vcpu_reset = vmx_vcpu_reset,
11422
11423         .prepare_guest_switch = vmx_save_host_state,
11424         .vcpu_load = vmx_vcpu_load,
11425         .vcpu_put = vmx_vcpu_put,
11426
11427         .update_bp_intercept = update_exception_bitmap,
11428         .get_msr = vmx_get_msr,
11429         .set_msr = vmx_set_msr,
11430         .get_segment_base = vmx_get_segment_base,
11431         .get_segment = vmx_get_segment,
11432         .set_segment = vmx_set_segment,
11433         .get_cpl = vmx_get_cpl,
11434         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11435         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11436         .decache_cr3 = vmx_decache_cr3,
11437         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11438         .set_cr0 = vmx_set_cr0,
11439         .set_cr3 = vmx_set_cr3,
11440         .set_cr4 = vmx_set_cr4,
11441         .set_efer = vmx_set_efer,
11442         .get_idt = vmx_get_idt,
11443         .set_idt = vmx_set_idt,
11444         .get_gdt = vmx_get_gdt,
11445         .set_gdt = vmx_set_gdt,
11446         .get_dr6 = vmx_get_dr6,
11447         .set_dr6 = vmx_set_dr6,
11448         .set_dr7 = vmx_set_dr7,
11449         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11450         .cache_reg = vmx_cache_reg,
11451         .get_rflags = vmx_get_rflags,
11452         .set_rflags = vmx_set_rflags,
11453
11454         .get_pkru = vmx_get_pkru,
11455
11456         .tlb_flush = vmx_flush_tlb,
11457
11458         .run = vmx_vcpu_run,
11459         .handle_exit = vmx_handle_exit,
11460         .skip_emulated_instruction = skip_emulated_instruction,
11461         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11462         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11463         .patch_hypercall = vmx_patch_hypercall,
11464         .set_irq = vmx_inject_irq,
11465         .set_nmi = vmx_inject_nmi,
11466         .queue_exception = vmx_queue_exception,
11467         .cancel_injection = vmx_cancel_injection,
11468         .interrupt_allowed = vmx_interrupt_allowed,
11469         .nmi_allowed = vmx_nmi_allowed,
11470         .get_nmi_mask = vmx_get_nmi_mask,
11471         .set_nmi_mask = vmx_set_nmi_mask,
11472         .enable_nmi_window = enable_nmi_window,
11473         .enable_irq_window = enable_irq_window,
11474         .update_cr8_intercept = update_cr8_intercept,
11475         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11476         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11477         .get_enable_apicv = vmx_get_enable_apicv,
11478         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11479         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11480         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11481         .hwapic_irr_update = vmx_hwapic_irr_update,
11482         .hwapic_isr_update = vmx_hwapic_isr_update,
11483         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11484         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11485
11486         .set_tss_addr = vmx_set_tss_addr,
11487         .get_tdp_level = get_ept_level,
11488         .get_mt_mask = vmx_get_mt_mask,
11489
11490         .get_exit_info = vmx_get_exit_info,
11491
11492         .get_lpage_level = vmx_get_lpage_level,
11493
11494         .cpuid_update = vmx_cpuid_update,
11495
11496         .rdtscp_supported = vmx_rdtscp_supported,
11497         .invpcid_supported = vmx_invpcid_supported,
11498
11499         .set_supported_cpuid = vmx_set_supported_cpuid,
11500
11501         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11502
11503         .write_tsc_offset = vmx_write_tsc_offset,
11504
11505         .set_tdp_cr3 = vmx_set_cr3,
11506
11507         .check_intercept = vmx_check_intercept,
11508         .handle_external_intr = vmx_handle_external_intr,
11509         .mpx_supported = vmx_mpx_supported,
11510         .xsaves_supported = vmx_xsaves_supported,
11511
11512         .check_nested_events = vmx_check_nested_events,
11513
11514         .sched_in = vmx_sched_in,
11515
11516         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11517         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11518         .flush_log_dirty = vmx_flush_log_dirty,
11519         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11520
11521         .pre_block = vmx_pre_block,
11522         .post_block = vmx_post_block,
11523
11524         .pmu_ops = &intel_pmu_ops,
11525
11526         .update_pi_irte = vmx_update_pi_irte,
11527
11528 #ifdef CONFIG_X86_64
11529         .set_hv_timer = vmx_set_hv_timer,
11530         .cancel_hv_timer = vmx_cancel_hv_timer,
11531 #endif
11532
11533         .setup_mce = vmx_setup_mce,
11534 };
11535
11536 static int __init vmx_init(void)
11537 {
11538         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11539                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11540         if (r)
11541                 return r;
11542
11543 #ifdef CONFIG_KEXEC_CORE
11544         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11545                            crash_vmclear_local_loaded_vmcss);
11546 #endif
11547
11548         return 0;
11549 }
11550
11551 static void __exit vmx_exit(void)
11552 {
11553 #ifdef CONFIG_KEXEC_CORE
11554         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11555         synchronize_rcu();
11556 #endif
11557
11558         kvm_exit();
11559 }
11560
11561 module_init(vmx_init)
11562 module_exit(vmx_exit)