2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
58 #include <trace/events/kvm.h>
60 #include <asm/debugreg.h>
64 #include <linux/kernel_stat.h>
65 #include <asm/fpu/internal.h> /* Ugh! */
66 #include <asm/pvclock.h>
67 #include <asm/div64.h>
68 #include <asm/irq_remapping.h>
70 #define CREATE_TRACE_POINTS
73 #define MAX_IO_MSRS 256
74 #define KVM_MAX_MCE_BANKS 32
75 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78 #define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
87 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
89 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
92 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
99 static void process_nmi(struct kvm_vcpu *vcpu);
100 static void enter_smm(struct kvm_vcpu *vcpu);
101 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
104 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106 static bool __read_mostly ignore_msrs = 0;
107 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109 unsigned int min_timer_period_us = 500;
110 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112 static bool __read_mostly kvmclock_periodic_sync = true;
113 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115 bool __read_mostly kvm_has_tsc_control;
116 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
117 u32 __read_mostly kvm_max_guest_tsc_khz;
118 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
119 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121 u64 __read_mostly kvm_max_tsc_scaling_ratio;
122 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
123 u64 __read_mostly kvm_default_tsc_scaling_ratio;
124 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
126 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
127 static u32 __read_mostly tsc_tolerance_ppm = 250;
128 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
131 unsigned int __read_mostly lapic_timer_advance_ns = 0;
132 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134 static bool __read_mostly vector_hashing = true;
135 module_param(vector_hashing, bool, S_IRUGO);
137 static bool __read_mostly backwards_tsc_observed = false;
139 #define KVM_NR_SHARED_MSRS 16
141 struct kvm_shared_msrs_global {
143 u32 msrs[KVM_NR_SHARED_MSRS];
146 struct kvm_shared_msrs {
147 struct user_return_notifier urn;
149 struct kvm_shared_msr_values {
152 } values[KVM_NR_SHARED_MSRS];
155 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
156 static struct kvm_shared_msrs __percpu *shared_msrs;
158 struct kvm_stats_debugfs_item debugfs_entries[] = {
159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
169 { "halt_exits", VCPU_STAT(halt_exits) },
170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
174 { "hypercalls", VCPU_STAT(hypercalls) },
175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
182 { "irq_injections", VCPU_STAT(irq_injections) },
183 { "nmi_injections", VCPU_STAT(nmi_injections) },
184 { "req_event", VCPU_STAT(req_event) },
185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
192 { "mmu_unsync", VM_STAT(mmu_unsync) },
193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
194 { "largepages", VM_STAT(lpages) },
195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
200 u64 __read_mostly host_xcr0;
202 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
204 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
211 static void kvm_on_user_return(struct user_return_notifier *urn)
214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
216 struct kvm_shared_msr_values *values;
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
228 local_irq_restore(flags);
229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
238 static void shared_msr_update(unsigned slot, u32 msr)
241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
255 void kvm_define_shared_msr(unsigned slot, u32 msr)
257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
258 shared_msrs_global.msrs[slot] = msr;
259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
262 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
264 static void kvm_shared_msr_cpu_online(void)
268 for (i = 0; i < shared_msrs_global.nr; ++i)
269 shared_msr_update(i, shared_msrs_global.msrs[i]);
272 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
280 smsr->values[slot].curr = value;
281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
292 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
294 static void drop_user_return_notifiers(void)
296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
303 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
305 return vcpu->arch.apic_base;
307 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
309 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 kvm_lapic_set_base(vcpu, msr_info->data);
330 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
332 asmlinkage __visible void kvm_spurious_fault(void)
334 /* Fault while not rebooting. We want the trace. */
337 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
339 #define EXCPT_BENIGN 0
340 #define EXCPT_CONTRIBUTORY 1
343 static int exception_class(int vector)
353 return EXCPT_CONTRIBUTORY;
360 #define EXCPT_FAULT 0
362 #define EXCPT_ABORT 2
363 #define EXCPT_INTERRUPT 3
365 static int exception_type(int vector)
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 /* Reserved exceptions will result in fault */
385 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
386 unsigned nr, bool has_error, u32 error_code,
392 kvm_make_request(KVM_REQ_EVENT, vcpu);
394 if (!vcpu->arch.exception.pending) {
396 if (has_error && !is_protmode(vcpu))
398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
402 vcpu->arch.exception.reinject = reinject;
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
429 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
431 kvm_multiple_exception(vcpu, nr, false, 0, false);
433 EXPORT_SYMBOL_GPL(kvm_queue_exception);
435 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
439 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
441 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
444 kvm_inject_gp(vcpu, 0);
446 return kvm_skip_emulated_instruction(vcpu);
450 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
452 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
454 ++vcpu->stat.pf_guest;
455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
458 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
460 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
467 return fault->nested_page_fault;
470 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
475 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
477 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
481 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
483 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
487 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
493 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
500 EXPORT_SYMBOL_GPL(kvm_require_cpl);
502 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
507 kvm_queue_exception(vcpu, UD_VECTOR);
510 EXPORT_SYMBOL_GPL(kvm_require_dr);
513 * This function will be used to read from the physical memory of the currently
514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
515 * can read from guest physical or from the guest's guest physical memory.
517 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
521 struct x86_exception exception;
525 ngpa = gfn_to_gpa(ngfn);
526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
527 if (real_gfn == UNMAPPED_GVA)
530 real_gfn = gpa_to_gfn(real_gfn);
532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
534 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
536 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
537 void *data, int offset, int len, u32 access)
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
544 * Load the pae pdptrs. Return true is they are all valid.
546 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
562 if ((pdpte[i] & PT_PRESENT_MASK) &&
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
580 EXPORT_SYMBOL_GPL(load_pdptrs);
582 bool pdptrs_changed(struct kvm_vcpu *vcpu)
584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
608 EXPORT_SYMBOL_GPL(pdptrs_changed);
610 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
618 if (cr0 & 0xffffffff00000000UL)
622 cr0 &= ~CR0_RESERVED_BITS;
624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
632 if ((vcpu->arch.efer & EFER_LME)) {
637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
650 kvm_x86_ops->set_cr0(vcpu, cr0);
652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
653 kvm_clear_async_pf_completion_queue(vcpu);
654 kvm_async_pf_hash_reset(vcpu);
657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
667 EXPORT_SYMBOL_GPL(kvm_set_cr0);
669 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
673 EXPORT_SYMBOL_GPL(kvm_lmsw);
675 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
685 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
694 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
697 u64 old_xcr0 = vcpu->arch.xcr0;
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
703 if (!(xcr0 & XFEATURE_MASK_FP))
705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
714 if (xcr0 & ~valid_bits)
717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
727 vcpu->arch.xcr0 = xcr0;
729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
730 kvm_update_cpuid(vcpu);
734 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
738 kvm_inject_gp(vcpu, 0);
743 EXPORT_SYMBOL_GPL(kvm_set_xcr);
745 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
751 if (cr4 & CR4_RESERVED_BITS)
754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
769 if (is_long_mode(vcpu)) {
770 if (!(cr4 & X86_CR4_PAE))
772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
792 kvm_mmu_reset_context(vcpu);
794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
795 kvm_update_cpuid(vcpu);
799 EXPORT_SYMBOL_GPL(kvm_set_cr4);
801 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
804 cr3 &= ~CR3_PCID_INVD;
807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
808 kvm_mmu_sync_roots(vcpu);
809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
813 if (is_long_mode(vcpu)) {
814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
820 vcpu->arch.cr3 = cr3;
821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
822 kvm_mmu_new_cr3(vcpu);
825 EXPORT_SYMBOL_GPL(kvm_set_cr3);
827 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
829 if (cr8 & CR8_RESERVED_BITS)
831 if (lapic_in_kernel(vcpu))
832 kvm_lapic_set_tpr(vcpu, cr8);
834 vcpu->arch.cr8 = cr8;
837 EXPORT_SYMBOL_GPL(kvm_set_cr8);
839 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
841 if (lapic_in_kernel(vcpu))
842 return kvm_lapic_get_cr8(vcpu);
844 return vcpu->arch.cr8;
846 EXPORT_SYMBOL_GPL(kvm_get_cr8);
848 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
859 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
865 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
879 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
881 u64 fixed = DR6_FIXED_1;
883 if (!guest_cpuid_has_rtm(vcpu))
888 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
899 if (val & 0xffffffff00000000ULL)
901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
902 kvm_update_dr6(vcpu);
907 if (val & 0xffffffff00000000ULL)
909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
910 kvm_update_dr7(vcpu);
917 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
919 if (__kvm_set_dr(vcpu, dr, val)) {
920 kvm_inject_gp(vcpu, 0);
925 EXPORT_SYMBOL_GPL(kvm_set_dr);
927 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
931 *val = vcpu->arch.db[dr];
936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
939 *val = kvm_x86_ops->get_dr6(vcpu);
944 *val = vcpu->arch.dr7;
949 EXPORT_SYMBOL_GPL(kvm_get_dr);
951 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
964 EXPORT_SYMBOL_GPL(kvm_rdpmc);
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
970 * This list is modified at module load time to reflect the
971 * capabilities of the host cpu. This capabilities test skips MSRs that are
972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
976 static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
986 static unsigned num_msrs_to_save;
988 static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
997 HV_X64_MSR_VP_RUNTIME,
999 HV_X64_MSR_STIMER0_CONFIG,
1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1003 MSR_IA32_TSC_ADJUST,
1004 MSR_IA32_TSCDEADLINE,
1005 MSR_IA32_MISC_ENABLE,
1006 MSR_IA32_MCG_STATUS,
1008 MSR_IA32_MCG_EXT_CTL,
1011 MSR_MISC_FEATURES_ENABLES,
1014 static unsigned num_emulated_msrs;
1016 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1018 if (efer & efer_reserved_bits)
1021 if (efer & EFER_FFXSR) {
1022 struct kvm_cpuid_entry2 *feat;
1024 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1025 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1029 if (efer & EFER_SVME) {
1030 struct kvm_cpuid_entry2 *feat;
1032 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1033 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1039 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1041 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1043 u64 old_efer = vcpu->arch.efer;
1045 if (!kvm_valid_efer(vcpu, efer))
1049 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1053 efer |= vcpu->arch.efer & EFER_LMA;
1055 kvm_x86_ops->set_efer(vcpu, efer);
1057 /* Update reserved bits */
1058 if ((efer ^ old_efer) & EFER_NX)
1059 kvm_mmu_reset_context(vcpu);
1064 void kvm_enable_efer_bits(u64 mask)
1066 efer_reserved_bits &= ~mask;
1068 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1071 * Writes msr value into into the appropriate "register".
1072 * Returns 0 on success, non-0 otherwise.
1073 * Assumes vcpu_load() was already called.
1075 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1077 switch (msr->index) {
1080 case MSR_KERNEL_GS_BASE:
1083 if (is_noncanonical_address(msr->data))
1086 case MSR_IA32_SYSENTER_EIP:
1087 case MSR_IA32_SYSENTER_ESP:
1089 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1090 * non-canonical address is written on Intel but not on
1091 * AMD (which ignores the top 32-bits, because it does
1092 * not implement 64-bit SYSENTER).
1094 * 64-bit code should hence be able to write a non-canonical
1095 * value on AMD. Making the address canonical ensures that
1096 * vmentry does not fail on Intel after writing a non-canonical
1097 * value, and that something deterministic happens if the guest
1098 * invokes 64-bit SYSENTER.
1100 msr->data = get_canonical(msr->data);
1102 return kvm_x86_ops->set_msr(vcpu, msr);
1104 EXPORT_SYMBOL_GPL(kvm_set_msr);
1107 * Adapt set_msr() to msr_io()'s calling convention
1109 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1111 struct msr_data msr;
1115 msr.host_initiated = true;
1116 r = kvm_get_msr(vcpu, &msr);
1124 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1126 struct msr_data msr;
1130 msr.host_initiated = true;
1131 return kvm_set_msr(vcpu, &msr);
1134 #ifdef CONFIG_X86_64
1135 struct pvclock_gtod_data {
1138 struct { /* extract of a clocksource struct */
1151 static struct pvclock_gtod_data pvclock_gtod_data;
1153 static void update_pvclock_gtod(struct timekeeper *tk)
1155 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1158 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1160 write_seqcount_begin(&vdata->seq);
1162 /* copy pvclock gtod data */
1163 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1164 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1165 vdata->clock.mask = tk->tkr_mono.mask;
1166 vdata->clock.mult = tk->tkr_mono.mult;
1167 vdata->clock.shift = tk->tkr_mono.shift;
1169 vdata->boot_ns = boot_ns;
1170 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1172 vdata->wall_time_sec = tk->xtime_sec;
1174 write_seqcount_end(&vdata->seq);
1178 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1181 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1182 * vcpu_enter_guest. This function is only called from
1183 * the physical CPU that is running vcpu.
1185 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1188 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1192 struct pvclock_wall_clock wc;
1193 struct timespec64 boot;
1198 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1203 ++version; /* first time write, random junk */
1207 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1211 * The guest calculates current wall clock time by adding
1212 * system time (updated by kvm_guest_time_update below) to the
1213 * wall clock specified here. guest system time equals host
1214 * system time for us, thus we must fill in host boot time here.
1216 getboottime64(&boot);
1218 if (kvm->arch.kvmclock_offset) {
1219 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1220 boot = timespec64_sub(boot, ts);
1222 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1223 wc.nsec = boot.tv_nsec;
1224 wc.version = version;
1226 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1229 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1232 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1234 do_shl32_div32(dividend, divisor);
1238 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1239 s8 *pshift, u32 *pmultiplier)
1247 scaled64 = scaled_hz;
1248 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1253 tps32 = (uint32_t)tps64;
1254 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1255 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1263 *pmultiplier = div_frac(scaled64, tps32);
1265 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1266 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1269 #ifdef CONFIG_X86_64
1270 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1273 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1274 static unsigned long max_tsc_khz;
1276 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1278 u64 v = (u64)khz * (1000000 + ppm);
1283 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1287 /* Guest TSC same frequency as host TSC? */
1289 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1293 /* TSC scaling supported? */
1294 if (!kvm_has_tsc_control) {
1295 if (user_tsc_khz > tsc_khz) {
1296 vcpu->arch.tsc_catchup = 1;
1297 vcpu->arch.tsc_always_catchup = 1;
1300 WARN(1, "user requested TSC rate below hardware speed\n");
1305 /* TSC scaling required - calculate ratio */
1306 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1307 user_tsc_khz, tsc_khz);
1309 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1310 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1315 vcpu->arch.tsc_scaling_ratio = ratio;
1319 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1321 u32 thresh_lo, thresh_hi;
1322 int use_scaling = 0;
1324 /* tsc_khz can be zero if TSC calibration fails */
1325 if (user_tsc_khz == 0) {
1326 /* set tsc_scaling_ratio to a safe value */
1327 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1331 /* Compute a scale to convert nanoseconds in TSC cycles */
1332 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1333 &vcpu->arch.virtual_tsc_shift,
1334 &vcpu->arch.virtual_tsc_mult);
1335 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1338 * Compute the variation in TSC rate which is acceptable
1339 * within the range of tolerance and decide if the
1340 * rate being applied is within that bounds of the hardware
1341 * rate. If so, no scaling or compensation need be done.
1343 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1344 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1345 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1346 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1349 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1352 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1354 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1355 vcpu->arch.virtual_tsc_mult,
1356 vcpu->arch.virtual_tsc_shift);
1357 tsc += vcpu->arch.this_tsc_write;
1361 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1363 #ifdef CONFIG_X86_64
1365 struct kvm_arch *ka = &vcpu->kvm->arch;
1366 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1368 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1369 atomic_read(&vcpu->kvm->online_vcpus));
1372 * Once the masterclock is enabled, always perform request in
1373 * order to update it.
1375 * In order to enable masterclock, the host clocksource must be TSC
1376 * and the vcpus need to have matched TSCs. When that happens,
1377 * perform request to enable masterclock.
1379 if (ka->use_master_clock ||
1380 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1381 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1383 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1384 atomic_read(&vcpu->kvm->online_vcpus),
1385 ka->use_master_clock, gtod->clock.vclock_mode);
1389 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1391 u64 curr_offset = vcpu->arch.tsc_offset;
1392 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1396 * Multiply tsc by a fixed point number represented by ratio.
1398 * The most significant 64-N bits (mult) of ratio represent the
1399 * integral part of the fixed point number; the remaining N bits
1400 * (frac) represent the fractional part, ie. ratio represents a fixed
1401 * point number (mult + frac * 2^(-N)).
1403 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1405 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1407 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1410 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1413 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1415 if (ratio != kvm_default_tsc_scaling_ratio)
1416 _tsc = __scale_tsc(ratio, tsc);
1420 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1422 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1426 tsc = kvm_scale_tsc(vcpu, rdtsc());
1428 return target_tsc - tsc;
1431 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1433 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1435 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1437 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1439 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1440 vcpu->arch.tsc_offset = offset;
1443 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1445 struct kvm *kvm = vcpu->kvm;
1446 u64 offset, ns, elapsed;
1447 unsigned long flags;
1449 bool already_matched;
1450 u64 data = msr->data;
1451 bool synchronizing = false;
1453 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1454 offset = kvm_compute_tsc_offset(vcpu, data);
1455 ns = ktime_get_boot_ns();
1456 elapsed = ns - kvm->arch.last_tsc_nsec;
1458 if (vcpu->arch.virtual_tsc_khz) {
1459 if (data == 0 && msr->host_initiated) {
1461 * detection of vcpu initialization -- need to sync
1462 * with other vCPUs. This particularly helps to keep
1463 * kvm_clock stable after CPU hotplug
1465 synchronizing = true;
1467 u64 tsc_exp = kvm->arch.last_tsc_write +
1468 nsec_to_cycles(vcpu, elapsed);
1469 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1471 * Special case: TSC write with a small delta (1 second)
1472 * of virtual cycle time against real time is
1473 * interpreted as an attempt to synchronize the CPU.
1475 synchronizing = data < tsc_exp + tsc_hz &&
1476 data + tsc_hz > tsc_exp;
1481 * For a reliable TSC, we can match TSC offsets, and for an unstable
1482 * TSC, we add elapsed time in this computation. We could let the
1483 * compensation code attempt to catch up if we fall behind, but
1484 * it's better to try to match offsets from the beginning.
1486 if (synchronizing &&
1487 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1488 if (!check_tsc_unstable()) {
1489 offset = kvm->arch.cur_tsc_offset;
1490 pr_debug("kvm: matched tsc offset for %llu\n", data);
1492 u64 delta = nsec_to_cycles(vcpu, elapsed);
1494 offset = kvm_compute_tsc_offset(vcpu, data);
1495 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1498 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1501 * We split periods of matched TSC writes into generations.
1502 * For each generation, we track the original measured
1503 * nanosecond time, offset, and write, so if TSCs are in
1504 * sync, we can match exact offset, and if not, we can match
1505 * exact software computation in compute_guest_tsc()
1507 * These values are tracked in kvm->arch.cur_xxx variables.
1509 kvm->arch.cur_tsc_generation++;
1510 kvm->arch.cur_tsc_nsec = ns;
1511 kvm->arch.cur_tsc_write = data;
1512 kvm->arch.cur_tsc_offset = offset;
1514 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1515 kvm->arch.cur_tsc_generation, data);
1519 * We also track th most recent recorded KHZ, write and time to
1520 * allow the matching interval to be extended at each write.
1522 kvm->arch.last_tsc_nsec = ns;
1523 kvm->arch.last_tsc_write = data;
1524 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1526 vcpu->arch.last_guest_tsc = data;
1528 /* Keep track of which generation this VCPU has synchronized to */
1529 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1530 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1531 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1533 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1534 update_ia32_tsc_adjust_msr(vcpu, offset);
1535 kvm_vcpu_write_tsc_offset(vcpu, offset);
1536 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1538 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1540 kvm->arch.nr_vcpus_matched_tsc = 0;
1541 } else if (!already_matched) {
1542 kvm->arch.nr_vcpus_matched_tsc++;
1545 kvm_track_tsc_matching(vcpu);
1546 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1549 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1551 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1554 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1557 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1559 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1560 WARN_ON(adjustment < 0);
1561 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1562 adjust_tsc_offset_guest(vcpu, adjustment);
1565 #ifdef CONFIG_X86_64
1567 static u64 read_tsc(void)
1569 u64 ret = (u64)rdtsc_ordered();
1570 u64 last = pvclock_gtod_data.clock.cycle_last;
1572 if (likely(ret >= last))
1576 * GCC likes to generate cmov here, but this branch is extremely
1577 * predictable (it's just a function of time and the likely is
1578 * very likely) and there's a data dependence, so force GCC
1579 * to generate a branch instead. I don't barrier() because
1580 * we don't actually need a barrier, and if this function
1581 * ever gets inlined it will generate worse code.
1587 static inline u64 vgettsc(u64 *cycle_now)
1590 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1592 *cycle_now = read_tsc();
1594 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1595 return v * gtod->clock.mult;
1598 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1600 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1606 seq = read_seqcount_begin(>od->seq);
1607 mode = gtod->clock.vclock_mode;
1608 ns = gtod->nsec_base;
1609 ns += vgettsc(cycle_now);
1610 ns >>= gtod->clock.shift;
1611 ns += gtod->boot_ns;
1612 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1618 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1626 seq = read_seqcount_begin(>od->seq);
1627 mode = gtod->clock.vclock_mode;
1628 ts->tv_sec = gtod->wall_time_sec;
1629 ns = gtod->nsec_base;
1630 ns += vgettsc(cycle_now);
1631 ns >>= gtod->clock.shift;
1632 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1634 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1640 /* returns true if host is using tsc clocksource */
1641 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1643 /* checked again under seqlock below */
1644 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1647 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1650 /* returns true if host is using tsc clocksource */
1651 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1654 /* checked again under seqlock below */
1655 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1658 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1664 * Assuming a stable TSC across physical CPUS, and a stable TSC
1665 * across virtual CPUs, the following condition is possible.
1666 * Each numbered line represents an event visible to both
1667 * CPUs at the next numbered event.
1669 * "timespecX" represents host monotonic time. "tscX" represents
1672 * VCPU0 on CPU0 | VCPU1 on CPU1
1674 * 1. read timespec0,tsc0
1675 * 2. | timespec1 = timespec0 + N
1677 * 3. transition to guest | transition to guest
1678 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1679 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1680 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1682 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1685 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1687 * - 0 < N - M => M < N
1689 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1690 * always the case (the difference between two distinct xtime instances
1691 * might be smaller then the difference between corresponding TSC reads,
1692 * when updating guest vcpus pvclock areas).
1694 * To avoid that problem, do not allow visibility of distinct
1695 * system_timestamp/tsc_timestamp values simultaneously: use a master
1696 * copy of host monotonic time values. Update that master copy
1699 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1703 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1705 #ifdef CONFIG_X86_64
1706 struct kvm_arch *ka = &kvm->arch;
1708 bool host_tsc_clocksource, vcpus_matched;
1710 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1711 atomic_read(&kvm->online_vcpus));
1714 * If the host uses TSC clock, then passthrough TSC as stable
1717 host_tsc_clocksource = kvm_get_time_and_clockread(
1718 &ka->master_kernel_ns,
1719 &ka->master_cycle_now);
1721 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1722 && !backwards_tsc_observed
1723 && !ka->boot_vcpu_runs_old_kvmclock;
1725 if (ka->use_master_clock)
1726 atomic_set(&kvm_guest_has_master_clock, 1);
1728 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1729 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1734 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1736 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1739 static void kvm_gen_update_masterclock(struct kvm *kvm)
1741 #ifdef CONFIG_X86_64
1743 struct kvm_vcpu *vcpu;
1744 struct kvm_arch *ka = &kvm->arch;
1746 spin_lock(&ka->pvclock_gtod_sync_lock);
1747 kvm_make_mclock_inprogress_request(kvm);
1748 /* no guest entries from this point */
1749 pvclock_update_vm_gtod_copy(kvm);
1751 kvm_for_each_vcpu(i, vcpu, kvm)
1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1754 /* guest entries allowed */
1755 kvm_for_each_vcpu(i, vcpu, kvm)
1756 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1758 spin_unlock(&ka->pvclock_gtod_sync_lock);
1762 static u64 __get_kvmclock_ns(struct kvm *kvm)
1764 struct kvm_arch *ka = &kvm->arch;
1765 struct pvclock_vcpu_time_info hv_clock;
1767 spin_lock(&ka->pvclock_gtod_sync_lock);
1768 if (!ka->use_master_clock) {
1769 spin_unlock(&ka->pvclock_gtod_sync_lock);
1770 return ktime_get_boot_ns() + ka->kvmclock_offset;
1773 hv_clock.tsc_timestamp = ka->master_cycle_now;
1774 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1775 spin_unlock(&ka->pvclock_gtod_sync_lock);
1777 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1778 &hv_clock.tsc_shift,
1779 &hv_clock.tsc_to_system_mul);
1780 return __pvclock_read_cycles(&hv_clock, rdtsc());
1783 u64 get_kvmclock_ns(struct kvm *kvm)
1785 unsigned long flags;
1788 local_irq_save(flags);
1789 ns = __get_kvmclock_ns(kvm);
1790 local_irq_restore(flags);
1795 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1797 struct kvm_vcpu_arch *vcpu = &v->arch;
1798 struct pvclock_vcpu_time_info guest_hv_clock;
1800 if (unlikely(kvm_vcpu_read_guest_cached(v, &vcpu->pv_time,
1801 &guest_hv_clock, sizeof(guest_hv_clock))))
1804 /* This VCPU is paused, but it's legal for a guest to read another
1805 * VCPU's kvmclock, so we really have to follow the specification where
1806 * it says that version is odd if data is being modified, and even after
1809 * Version field updates must be kept separate. This is because
1810 * kvm_write_guest_cached might use a "rep movs" instruction, and
1811 * writes within a string instruction are weakly ordered. So there
1812 * are three writes overall.
1814 * As a small optimization, only write the version field in the first
1815 * and third write. The vcpu->pv_time cache is still valid, because the
1816 * version field is the first in the struct.
1818 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1820 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1821 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1823 sizeof(vcpu->hv_clock.version));
1827 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1828 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1830 if (vcpu->pvclock_set_guest_stopped_request) {
1831 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1832 vcpu->pvclock_set_guest_stopped_request = false;
1835 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1839 sizeof(vcpu->hv_clock));
1843 vcpu->hv_clock.version++;
1844 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1846 sizeof(vcpu->hv_clock.version));
1849 static int kvm_guest_time_update(struct kvm_vcpu *v)
1851 unsigned long flags, tgt_tsc_khz;
1852 struct kvm_vcpu_arch *vcpu = &v->arch;
1853 struct kvm_arch *ka = &v->kvm->arch;
1855 u64 tsc_timestamp, host_tsc;
1857 bool use_master_clock;
1863 * If the host uses TSC clock, then passthrough TSC as stable
1866 spin_lock(&ka->pvclock_gtod_sync_lock);
1867 use_master_clock = ka->use_master_clock;
1868 if (use_master_clock) {
1869 host_tsc = ka->master_cycle_now;
1870 kernel_ns = ka->master_kernel_ns;
1872 spin_unlock(&ka->pvclock_gtod_sync_lock);
1874 /* Keep irq disabled to prevent changes to the clock */
1875 local_irq_save(flags);
1876 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1877 if (unlikely(tgt_tsc_khz == 0)) {
1878 local_irq_restore(flags);
1879 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1882 if (!use_master_clock) {
1884 kernel_ns = ktime_get_boot_ns();
1887 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1890 * We may have to catch up the TSC to match elapsed wall clock
1891 * time for two reasons, even if kvmclock is used.
1892 * 1) CPU could have been running below the maximum TSC rate
1893 * 2) Broken TSC compensation resets the base at each VCPU
1894 * entry to avoid unknown leaps of TSC even when running
1895 * again on the same CPU. This may cause apparent elapsed
1896 * time to disappear, and the guest to stand still or run
1899 if (vcpu->tsc_catchup) {
1900 u64 tsc = compute_guest_tsc(v, kernel_ns);
1901 if (tsc > tsc_timestamp) {
1902 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1903 tsc_timestamp = tsc;
1907 local_irq_restore(flags);
1909 /* With all the info we got, fill in the values */
1911 if (kvm_has_tsc_control)
1912 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1914 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1915 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1916 &vcpu->hv_clock.tsc_shift,
1917 &vcpu->hv_clock.tsc_to_system_mul);
1918 vcpu->hw_tsc_khz = tgt_tsc_khz;
1921 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1922 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1923 vcpu->last_guest_tsc = tsc_timestamp;
1925 /* If the host uses TSC clocksource, then it is stable */
1927 if (use_master_clock)
1928 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1930 vcpu->hv_clock.flags = pvclock_flags;
1932 if (vcpu->pv_time_enabled)
1933 kvm_setup_pvclock_page(v);
1934 if (v == kvm_get_vcpu(v->kvm, 0))
1935 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1940 * kvmclock updates which are isolated to a given vcpu, such as
1941 * vcpu->cpu migration, should not allow system_timestamp from
1942 * the rest of the vcpus to remain static. Otherwise ntp frequency
1943 * correction applies to one vcpu's system_timestamp but not
1946 * So in those cases, request a kvmclock update for all vcpus.
1947 * We need to rate-limit these requests though, as they can
1948 * considerably slow guests that have a large number of vcpus.
1949 * The time for a remote vcpu to update its kvmclock is bound
1950 * by the delay we use to rate-limit the updates.
1953 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1955 static void kvmclock_update_fn(struct work_struct *work)
1958 struct delayed_work *dwork = to_delayed_work(work);
1959 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1960 kvmclock_update_work);
1961 struct kvm *kvm = container_of(ka, struct kvm, arch);
1962 struct kvm_vcpu *vcpu;
1964 kvm_for_each_vcpu(i, vcpu, kvm) {
1965 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1966 kvm_vcpu_kick(vcpu);
1970 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1972 struct kvm *kvm = v->kvm;
1974 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1975 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1976 KVMCLOCK_UPDATE_DELAY);
1979 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1981 static void kvmclock_sync_fn(struct work_struct *work)
1983 struct delayed_work *dwork = to_delayed_work(work);
1984 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1985 kvmclock_sync_work);
1986 struct kvm *kvm = container_of(ka, struct kvm, arch);
1988 if (!kvmclock_periodic_sync)
1991 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1992 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1993 KVMCLOCK_SYNC_PERIOD);
1996 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1998 u64 mcg_cap = vcpu->arch.mcg_cap;
1999 unsigned bank_num = mcg_cap & 0xff;
2002 case MSR_IA32_MCG_STATUS:
2003 vcpu->arch.mcg_status = data;
2005 case MSR_IA32_MCG_CTL:
2006 if (!(mcg_cap & MCG_CTL_P))
2008 if (data != 0 && data != ~(u64)0)
2010 vcpu->arch.mcg_ctl = data;
2013 if (msr >= MSR_IA32_MC0_CTL &&
2014 msr < MSR_IA32_MCx_CTL(bank_num)) {
2015 u32 offset = msr - MSR_IA32_MC0_CTL;
2016 /* only 0 or all 1s can be written to IA32_MCi_CTL
2017 * some Linux kernels though clear bit 10 in bank 4 to
2018 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2019 * this to avoid an uncatched #GP in the guest
2021 if ((offset & 0x3) == 0 &&
2022 data != 0 && (data | (1 << 10)) != ~(u64)0)
2024 vcpu->arch.mce_banks[offset] = data;
2032 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2034 struct kvm *kvm = vcpu->kvm;
2035 int lm = is_long_mode(vcpu);
2036 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2037 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2038 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2039 : kvm->arch.xen_hvm_config.blob_size_32;
2040 u32 page_num = data & ~PAGE_MASK;
2041 u64 page_addr = data & PAGE_MASK;
2046 if (page_num >= blob_size)
2049 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2054 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2063 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2065 gpa_t gpa = data & ~0x3f;
2067 /* Bits 2:5 are reserved, Should be zero */
2071 vcpu->arch.apf.msr_val = data;
2073 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2074 kvm_clear_async_pf_completion_queue(vcpu);
2075 kvm_async_pf_hash_reset(vcpu);
2079 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.apf.data, gpa,
2083 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2084 kvm_async_pf_wakeup_all(vcpu);
2088 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2090 vcpu->arch.pv_time_enabled = false;
2093 static void record_steal_time(struct kvm_vcpu *vcpu)
2095 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2098 if (unlikely(kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.st.stime,
2099 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2102 vcpu->arch.st.steal.preempted = 0;
2104 if (vcpu->arch.st.steal.version & 1)
2105 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2107 vcpu->arch.st.steal.version += 1;
2109 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
2110 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2114 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2115 vcpu->arch.st.last_steal;
2116 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2118 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
2119 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2123 vcpu->arch.st.steal.version += 1;
2125 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
2126 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2129 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2132 u32 msr = msr_info->index;
2133 u64 data = msr_info->data;
2136 case MSR_AMD64_NB_CFG:
2137 case MSR_IA32_UCODE_REV:
2138 case MSR_IA32_UCODE_WRITE:
2139 case MSR_VM_HSAVE_PA:
2140 case MSR_AMD64_PATCH_LOADER:
2141 case MSR_AMD64_BU_CFG2:
2142 case MSR_AMD64_DC_CFG:
2146 return set_efer(vcpu, data);
2148 data &= ~(u64)0x40; /* ignore flush filter disable */
2149 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2150 data &= ~(u64)0x8; /* ignore TLB cache disable */
2151 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2153 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2158 case MSR_FAM10H_MMIO_CONF_BASE:
2160 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2165 case MSR_IA32_DEBUGCTLMSR:
2167 /* We support the non-activated case already */
2169 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2170 /* Values other than LBR and BTF are vendor-specific,
2171 thus reserved and should throw a #GP */
2174 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2177 case 0x200 ... 0x2ff:
2178 return kvm_mtrr_set_msr(vcpu, msr, data);
2179 case MSR_IA32_APICBASE:
2180 return kvm_set_apic_base(vcpu, msr_info);
2181 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2182 return kvm_x2apic_msr_write(vcpu, msr, data);
2183 case MSR_IA32_TSCDEADLINE:
2184 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2186 case MSR_IA32_TSC_ADJUST:
2187 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2188 if (!msr_info->host_initiated) {
2189 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2190 adjust_tsc_offset_guest(vcpu, adj);
2192 vcpu->arch.ia32_tsc_adjust_msr = data;
2195 case MSR_IA32_MISC_ENABLE:
2196 vcpu->arch.ia32_misc_enable_msr = data;
2198 case MSR_IA32_SMBASE:
2199 if (!msr_info->host_initiated)
2201 vcpu->arch.smbase = data;
2203 case MSR_KVM_WALL_CLOCK_NEW:
2204 case MSR_KVM_WALL_CLOCK:
2205 vcpu->kvm->arch.wall_clock = data;
2206 kvm_write_wall_clock(vcpu->kvm, data);
2208 case MSR_KVM_SYSTEM_TIME_NEW:
2209 case MSR_KVM_SYSTEM_TIME: {
2210 struct kvm_arch *ka = &vcpu->kvm->arch;
2212 kvmclock_reset(vcpu);
2214 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2215 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2217 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2218 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2221 ka->boot_vcpu_runs_old_kvmclock = tmp;
2224 vcpu->arch.time = data;
2225 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2227 /* we verify if the enable bit is set... */
2231 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
2232 &vcpu->arch.pv_time, data & ~1ULL,
2233 sizeof(struct pvclock_vcpu_time_info)))
2234 vcpu->arch.pv_time_enabled = false;
2236 vcpu->arch.pv_time_enabled = true;
2240 case MSR_KVM_ASYNC_PF_EN:
2241 if (kvm_pv_enable_async_pf(vcpu, data))
2244 case MSR_KVM_STEAL_TIME:
2246 if (unlikely(!sched_info_on()))
2249 if (data & KVM_STEAL_RESERVED_MASK)
2252 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.st.stime,
2253 data & KVM_STEAL_VALID_BITS,
2254 sizeof(struct kvm_steal_time)))
2257 vcpu->arch.st.msr_val = data;
2259 if (!(data & KVM_MSR_ENABLED))
2262 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2265 case MSR_KVM_PV_EOI_EN:
2266 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2270 case MSR_IA32_MCG_CTL:
2271 case MSR_IA32_MCG_STATUS:
2272 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2273 return set_msr_mce(vcpu, msr, data);
2275 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2276 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2277 pr = true; /* fall through */
2278 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2279 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2280 if (kvm_pmu_is_valid_msr(vcpu, msr))
2281 return kvm_pmu_set_msr(vcpu, msr_info);
2283 if (pr || data != 0)
2284 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2285 "0x%x data 0x%llx\n", msr, data);
2287 case MSR_K7_CLK_CTL:
2289 * Ignore all writes to this no longer documented MSR.
2290 * Writes are only relevant for old K7 processors,
2291 * all pre-dating SVM, but a recommended workaround from
2292 * AMD for these chips. It is possible to specify the
2293 * affected processor models on the command line, hence
2294 * the need to ignore the workaround.
2297 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2298 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2299 case HV_X64_MSR_CRASH_CTL:
2300 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2301 return kvm_hv_set_msr_common(vcpu, msr, data,
2302 msr_info->host_initiated);
2303 case MSR_IA32_BBL_CR_CTL3:
2304 /* Drop writes to this legacy MSR -- see rdmsr
2305 * counterpart for further detail.
2307 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2309 case MSR_AMD64_OSVW_ID_LENGTH:
2310 if (!guest_cpuid_has_osvw(vcpu))
2312 vcpu->arch.osvw.length = data;
2314 case MSR_AMD64_OSVW_STATUS:
2315 if (!guest_cpuid_has_osvw(vcpu))
2317 vcpu->arch.osvw.status = data;
2319 case MSR_PLATFORM_INFO:
2320 if (!msr_info->host_initiated ||
2321 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2322 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2323 cpuid_fault_enabled(vcpu)))
2325 vcpu->arch.msr_platform_info = data;
2327 case MSR_MISC_FEATURES_ENABLES:
2328 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2329 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2330 !supports_cpuid_fault(vcpu)))
2332 vcpu->arch.msr_misc_features_enables = data;
2335 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2336 return xen_hvm_config(vcpu, data);
2337 if (kvm_pmu_is_valid_msr(vcpu, msr))
2338 return kvm_pmu_set_msr(vcpu, msr_info);
2340 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2344 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2351 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2355 * Reads an msr value (of 'msr_index') into 'pdata'.
2356 * Returns 0 on success, non-0 otherwise.
2357 * Assumes vcpu_load() was already called.
2359 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2361 return kvm_x86_ops->get_msr(vcpu, msr);
2363 EXPORT_SYMBOL_GPL(kvm_get_msr);
2365 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2368 u64 mcg_cap = vcpu->arch.mcg_cap;
2369 unsigned bank_num = mcg_cap & 0xff;
2372 case MSR_IA32_P5_MC_ADDR:
2373 case MSR_IA32_P5_MC_TYPE:
2376 case MSR_IA32_MCG_CAP:
2377 data = vcpu->arch.mcg_cap;
2379 case MSR_IA32_MCG_CTL:
2380 if (!(mcg_cap & MCG_CTL_P))
2382 data = vcpu->arch.mcg_ctl;
2384 case MSR_IA32_MCG_STATUS:
2385 data = vcpu->arch.mcg_status;
2388 if (msr >= MSR_IA32_MC0_CTL &&
2389 msr < MSR_IA32_MCx_CTL(bank_num)) {
2390 u32 offset = msr - MSR_IA32_MC0_CTL;
2391 data = vcpu->arch.mce_banks[offset];
2400 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2402 switch (msr_info->index) {
2403 case MSR_IA32_PLATFORM_ID:
2404 case MSR_IA32_EBL_CR_POWERON:
2405 case MSR_IA32_DEBUGCTLMSR:
2406 case MSR_IA32_LASTBRANCHFROMIP:
2407 case MSR_IA32_LASTBRANCHTOIP:
2408 case MSR_IA32_LASTINTFROMIP:
2409 case MSR_IA32_LASTINTTOIP:
2411 case MSR_K8_TSEG_ADDR:
2412 case MSR_K8_TSEG_MASK:
2414 case MSR_VM_HSAVE_PA:
2415 case MSR_K8_INT_PENDING_MSG:
2416 case MSR_AMD64_NB_CFG:
2417 case MSR_FAM10H_MMIO_CONF_BASE:
2418 case MSR_AMD64_BU_CFG2:
2419 case MSR_IA32_PERF_CTL:
2420 case MSR_AMD64_DC_CFG:
2423 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2424 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2425 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2426 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2427 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2428 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2431 case MSR_IA32_UCODE_REV:
2432 msr_info->data = 0x100000000ULL;
2435 case 0x200 ... 0x2ff:
2436 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2437 case 0xcd: /* fsb frequency */
2441 * MSR_EBC_FREQUENCY_ID
2442 * Conservative value valid for even the basic CPU models.
2443 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2444 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2445 * and 266MHz for model 3, or 4. Set Core Clock
2446 * Frequency to System Bus Frequency Ratio to 1 (bits
2447 * 31:24) even though these are only valid for CPU
2448 * models > 2, however guests may end up dividing or
2449 * multiplying by zero otherwise.
2451 case MSR_EBC_FREQUENCY_ID:
2452 msr_info->data = 1 << 24;
2454 case MSR_IA32_APICBASE:
2455 msr_info->data = kvm_get_apic_base(vcpu);
2457 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2458 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2460 case MSR_IA32_TSCDEADLINE:
2461 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2463 case MSR_IA32_TSC_ADJUST:
2464 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2466 case MSR_IA32_MISC_ENABLE:
2467 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2469 case MSR_IA32_SMBASE:
2470 if (!msr_info->host_initiated)
2472 msr_info->data = vcpu->arch.smbase;
2474 case MSR_IA32_PERF_STATUS:
2475 /* TSC increment by tick */
2476 msr_info->data = 1000ULL;
2477 /* CPU multiplier */
2478 msr_info->data |= (((uint64_t)4ULL) << 40);
2481 msr_info->data = vcpu->arch.efer;
2483 case MSR_KVM_WALL_CLOCK:
2484 case MSR_KVM_WALL_CLOCK_NEW:
2485 msr_info->data = vcpu->kvm->arch.wall_clock;
2487 case MSR_KVM_SYSTEM_TIME:
2488 case MSR_KVM_SYSTEM_TIME_NEW:
2489 msr_info->data = vcpu->arch.time;
2491 case MSR_KVM_ASYNC_PF_EN:
2492 msr_info->data = vcpu->arch.apf.msr_val;
2494 case MSR_KVM_STEAL_TIME:
2495 msr_info->data = vcpu->arch.st.msr_val;
2497 case MSR_KVM_PV_EOI_EN:
2498 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2500 case MSR_IA32_P5_MC_ADDR:
2501 case MSR_IA32_P5_MC_TYPE:
2502 case MSR_IA32_MCG_CAP:
2503 case MSR_IA32_MCG_CTL:
2504 case MSR_IA32_MCG_STATUS:
2505 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2506 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2507 case MSR_K7_CLK_CTL:
2509 * Provide expected ramp-up count for K7. All other
2510 * are set to zero, indicating minimum divisors for
2513 * This prevents guest kernels on AMD host with CPU
2514 * type 6, model 8 and higher from exploding due to
2515 * the rdmsr failing.
2517 msr_info->data = 0x20000000;
2519 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2520 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2521 case HV_X64_MSR_CRASH_CTL:
2522 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2523 return kvm_hv_get_msr_common(vcpu,
2524 msr_info->index, &msr_info->data);
2526 case MSR_IA32_BBL_CR_CTL3:
2527 /* This legacy MSR exists but isn't fully documented in current
2528 * silicon. It is however accessed by winxp in very narrow
2529 * scenarios where it sets bit #19, itself documented as
2530 * a "reserved" bit. Best effort attempt to source coherent
2531 * read data here should the balance of the register be
2532 * interpreted by the guest:
2534 * L2 cache control register 3: 64GB range, 256KB size,
2535 * enabled, latency 0x1, configured
2537 msr_info->data = 0xbe702111;
2539 case MSR_AMD64_OSVW_ID_LENGTH:
2540 if (!guest_cpuid_has_osvw(vcpu))
2542 msr_info->data = vcpu->arch.osvw.length;
2544 case MSR_AMD64_OSVW_STATUS:
2545 if (!guest_cpuid_has_osvw(vcpu))
2547 msr_info->data = vcpu->arch.osvw.status;
2549 case MSR_PLATFORM_INFO:
2550 msr_info->data = vcpu->arch.msr_platform_info;
2552 case MSR_MISC_FEATURES_ENABLES:
2553 msr_info->data = vcpu->arch.msr_misc_features_enables;
2556 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2557 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2559 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2563 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2570 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2573 * Read or write a bunch of msrs. All parameters are kernel addresses.
2575 * @return number of msrs set successfully.
2577 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2578 struct kvm_msr_entry *entries,
2579 int (*do_msr)(struct kvm_vcpu *vcpu,
2580 unsigned index, u64 *data))
2584 idx = srcu_read_lock(&vcpu->kvm->srcu);
2585 for (i = 0; i < msrs->nmsrs; ++i)
2586 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2588 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2594 * Read or write a bunch of msrs. Parameters are user addresses.
2596 * @return number of msrs set successfully.
2598 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2599 int (*do_msr)(struct kvm_vcpu *vcpu,
2600 unsigned index, u64 *data),
2603 struct kvm_msrs msrs;
2604 struct kvm_msr_entry *entries;
2609 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2613 if (msrs.nmsrs >= MAX_IO_MSRS)
2616 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2617 entries = memdup_user(user_msrs->entries, size);
2618 if (IS_ERR(entries)) {
2619 r = PTR_ERR(entries);
2623 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2628 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2639 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2644 case KVM_CAP_IRQCHIP:
2646 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2647 case KVM_CAP_SET_TSS_ADDR:
2648 case KVM_CAP_EXT_CPUID:
2649 case KVM_CAP_EXT_EMUL_CPUID:
2650 case KVM_CAP_CLOCKSOURCE:
2652 case KVM_CAP_NOP_IO_DELAY:
2653 case KVM_CAP_MP_STATE:
2654 case KVM_CAP_SYNC_MMU:
2655 case KVM_CAP_USER_NMI:
2656 case KVM_CAP_REINJECT_CONTROL:
2657 case KVM_CAP_IRQ_INJECT_STATUS:
2658 case KVM_CAP_IOEVENTFD:
2659 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2661 case KVM_CAP_PIT_STATE2:
2662 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2663 case KVM_CAP_XEN_HVM:
2664 case KVM_CAP_VCPU_EVENTS:
2665 case KVM_CAP_HYPERV:
2666 case KVM_CAP_HYPERV_VAPIC:
2667 case KVM_CAP_HYPERV_SPIN:
2668 case KVM_CAP_HYPERV_SYNIC:
2669 case KVM_CAP_PCI_SEGMENT:
2670 case KVM_CAP_DEBUGREGS:
2671 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2673 case KVM_CAP_ASYNC_PF:
2674 case KVM_CAP_GET_TSC_KHZ:
2675 case KVM_CAP_KVMCLOCK_CTRL:
2676 case KVM_CAP_READONLY_MEM:
2677 case KVM_CAP_HYPERV_TIME:
2678 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2679 case KVM_CAP_TSC_DEADLINE_TIMER:
2680 case KVM_CAP_ENABLE_CAP_VM:
2681 case KVM_CAP_DISABLE_QUIRKS:
2682 case KVM_CAP_SET_BOOT_CPU_ID:
2683 case KVM_CAP_SPLIT_IRQCHIP:
2684 case KVM_CAP_IMMEDIATE_EXIT:
2687 case KVM_CAP_ADJUST_CLOCK:
2688 r = KVM_CLOCK_TSC_STABLE;
2690 case KVM_CAP_X86_GUEST_MWAIT:
2691 r = kvm_mwait_in_guest();
2693 case KVM_CAP_X86_SMM:
2694 /* SMBASE is usually relocated above 1M on modern chipsets,
2695 * and SMM handlers might indeed rely on 4G segment limits,
2696 * so do not report SMM to be available if real mode is
2697 * emulated via vm86 mode. Still, do not go to great lengths
2698 * to avoid userspace's usage of the feature, because it is a
2699 * fringe case that is not enabled except via specific settings
2700 * of the module parameters.
2702 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2705 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2707 case KVM_CAP_NR_VCPUS:
2708 r = KVM_SOFT_MAX_VCPUS;
2710 case KVM_CAP_MAX_VCPUS:
2713 case KVM_CAP_NR_MEMSLOTS:
2714 r = KVM_USER_MEM_SLOTS;
2716 case KVM_CAP_PV_MMU: /* obsolete */
2720 r = KVM_MAX_MCE_BANKS;
2723 r = boot_cpu_has(X86_FEATURE_XSAVE);
2725 case KVM_CAP_TSC_CONTROL:
2726 r = kvm_has_tsc_control;
2728 case KVM_CAP_X2APIC_API:
2729 r = KVM_X2APIC_API_VALID_FLAGS;
2739 long kvm_arch_dev_ioctl(struct file *filp,
2740 unsigned int ioctl, unsigned long arg)
2742 void __user *argp = (void __user *)arg;
2746 case KVM_GET_MSR_INDEX_LIST: {
2747 struct kvm_msr_list __user *user_msr_list = argp;
2748 struct kvm_msr_list msr_list;
2752 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2755 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2756 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2759 if (n < msr_list.nmsrs)
2762 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2763 num_msrs_to_save * sizeof(u32)))
2765 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2767 num_emulated_msrs * sizeof(u32)))
2772 case KVM_GET_SUPPORTED_CPUID:
2773 case KVM_GET_EMULATED_CPUID: {
2774 struct kvm_cpuid2 __user *cpuid_arg = argp;
2775 struct kvm_cpuid2 cpuid;
2778 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2781 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2787 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2792 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2794 if (copy_to_user(argp, &kvm_mce_cap_supported,
2795 sizeof(kvm_mce_cap_supported)))
2807 static void wbinvd_ipi(void *garbage)
2812 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2814 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2817 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2819 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2822 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2824 /* Address WBINVD may be executed by guest */
2825 if (need_emulate_wbinvd(vcpu)) {
2826 if (kvm_x86_ops->has_wbinvd_exit())
2827 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2828 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2829 smp_call_function_single(vcpu->cpu,
2830 wbinvd_ipi, NULL, 1);
2833 kvm_x86_ops->vcpu_load(vcpu, cpu);
2835 /* Apply any externally detected TSC adjustments (due to suspend) */
2836 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2837 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2838 vcpu->arch.tsc_offset_adjustment = 0;
2839 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2842 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2843 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2844 rdtsc() - vcpu->arch.last_host_tsc;
2846 mark_tsc_unstable("KVM discovered backwards TSC");
2848 if (check_tsc_unstable()) {
2849 u64 offset = kvm_compute_tsc_offset(vcpu,
2850 vcpu->arch.last_guest_tsc);
2851 kvm_vcpu_write_tsc_offset(vcpu, offset);
2852 vcpu->arch.tsc_catchup = 1;
2854 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2855 kvm_x86_ops->set_hv_timer(vcpu,
2856 kvm_get_lapic_target_expiration_tsc(vcpu)))
2857 kvm_lapic_switch_to_sw_timer(vcpu);
2859 * On a host with synchronized TSC, there is no need to update
2860 * kvmclock on vcpu->cpu migration
2862 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2863 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2864 if (vcpu->cpu != cpu)
2865 kvm_migrate_timers(vcpu);
2869 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2872 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2874 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2877 vcpu->arch.st.steal.preempted = 1;
2879 kvm_vcpu_write_guest_offset_cached(vcpu, &vcpu->arch.st.stime,
2880 &vcpu->arch.st.steal.preempted,
2881 offsetof(struct kvm_steal_time, preempted),
2882 sizeof(vcpu->arch.st.steal.preempted));
2885 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2889 * Disable page faults because we're in atomic context here.
2890 * kvm_write_guest_offset_cached() would call might_fault()
2891 * that relies on pagefault_disable() to tell if there's a
2892 * bug. NOTE: the write to guest memory may not go through if
2893 * during postcopy live migration or if there's heavy guest
2896 pagefault_disable();
2898 * kvm_memslots() will be called by
2899 * kvm_write_guest_offset_cached() so take the srcu lock.
2901 idx = srcu_read_lock(&vcpu->kvm->srcu);
2902 kvm_steal_time_set_preempted(vcpu);
2903 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2905 kvm_x86_ops->vcpu_put(vcpu);
2906 kvm_put_guest_fpu(vcpu);
2907 vcpu->arch.last_host_tsc = rdtsc();
2910 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2911 struct kvm_lapic_state *s)
2913 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
2914 kvm_x86_ops->sync_pir_to_irr(vcpu);
2916 return kvm_apic_get_state(vcpu, s);
2919 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2920 struct kvm_lapic_state *s)
2924 r = kvm_apic_set_state(vcpu, s);
2927 update_cr8_intercept(vcpu);
2932 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2934 return (!lapic_in_kernel(vcpu) ||
2935 kvm_apic_accept_pic_intr(vcpu));
2939 * if userspace requested an interrupt window, check that the
2940 * interrupt window is open.
2942 * No need to exit to userspace if we already have an interrupt queued.
2944 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2946 return kvm_arch_interrupt_allowed(vcpu) &&
2947 !kvm_cpu_has_interrupt(vcpu) &&
2948 !kvm_event_needs_reinjection(vcpu) &&
2949 kvm_cpu_accept_dm_intr(vcpu);
2952 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2953 struct kvm_interrupt *irq)
2955 if (irq->irq >= KVM_NR_INTERRUPTS)
2958 if (!irqchip_in_kernel(vcpu->kvm)) {
2959 kvm_queue_interrupt(vcpu, irq->irq, false);
2960 kvm_make_request(KVM_REQ_EVENT, vcpu);
2965 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2966 * fail for in-kernel 8259.
2968 if (pic_in_kernel(vcpu->kvm))
2971 if (vcpu->arch.pending_external_vector != -1)
2974 vcpu->arch.pending_external_vector = irq->irq;
2975 kvm_make_request(KVM_REQ_EVENT, vcpu);
2979 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2981 kvm_inject_nmi(vcpu);
2986 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2988 kvm_make_request(KVM_REQ_SMI, vcpu);
2993 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2994 struct kvm_tpr_access_ctl *tac)
2998 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3002 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3006 unsigned bank_num = mcg_cap & 0xff, bank;
3009 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3011 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3014 vcpu->arch.mcg_cap = mcg_cap;
3015 /* Init IA32_MCG_CTL to all 1s */
3016 if (mcg_cap & MCG_CTL_P)
3017 vcpu->arch.mcg_ctl = ~(u64)0;
3018 /* Init IA32_MCi_CTL to all 1s */
3019 for (bank = 0; bank < bank_num; bank++)
3020 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3022 if (kvm_x86_ops->setup_mce)
3023 kvm_x86_ops->setup_mce(vcpu);
3028 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3029 struct kvm_x86_mce *mce)
3031 u64 mcg_cap = vcpu->arch.mcg_cap;
3032 unsigned bank_num = mcg_cap & 0xff;
3033 u64 *banks = vcpu->arch.mce_banks;
3035 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3038 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3039 * reporting is disabled
3041 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3042 vcpu->arch.mcg_ctl != ~(u64)0)
3044 banks += 4 * mce->bank;
3046 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3047 * reporting is disabled for the bank
3049 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3051 if (mce->status & MCI_STATUS_UC) {
3052 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3053 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3054 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3057 if (banks[1] & MCI_STATUS_VAL)
3058 mce->status |= MCI_STATUS_OVER;
3059 banks[2] = mce->addr;
3060 banks[3] = mce->misc;
3061 vcpu->arch.mcg_status = mce->mcg_status;
3062 banks[1] = mce->status;
3063 kvm_queue_exception(vcpu, MC_VECTOR);
3064 } else if (!(banks[1] & MCI_STATUS_VAL)
3065 || !(banks[1] & MCI_STATUS_UC)) {
3066 if (banks[1] & MCI_STATUS_VAL)
3067 mce->status |= MCI_STATUS_OVER;
3068 banks[2] = mce->addr;
3069 banks[3] = mce->misc;
3070 banks[1] = mce->status;
3072 banks[1] |= MCI_STATUS_OVER;
3076 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3077 struct kvm_vcpu_events *events)
3080 events->exception.injected =
3081 vcpu->arch.exception.pending &&
3082 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3083 events->exception.nr = vcpu->arch.exception.nr;
3084 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3085 events->exception.pad = 0;
3086 events->exception.error_code = vcpu->arch.exception.error_code;
3088 events->interrupt.injected =
3089 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3090 events->interrupt.nr = vcpu->arch.interrupt.nr;
3091 events->interrupt.soft = 0;
3092 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3094 events->nmi.injected = vcpu->arch.nmi_injected;
3095 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3096 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3097 events->nmi.pad = 0;
3099 events->sipi_vector = 0; /* never valid when reporting to user space */
3101 events->smi.smm = is_smm(vcpu);
3102 events->smi.pending = vcpu->arch.smi_pending;
3103 events->smi.smm_inside_nmi =
3104 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3105 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3107 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3108 | KVM_VCPUEVENT_VALID_SHADOW
3109 | KVM_VCPUEVENT_VALID_SMM);
3110 memset(&events->reserved, 0, sizeof(events->reserved));
3113 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3115 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3116 struct kvm_vcpu_events *events)
3118 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3119 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3120 | KVM_VCPUEVENT_VALID_SHADOW
3121 | KVM_VCPUEVENT_VALID_SMM))
3124 if (events->exception.injected &&
3125 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3126 is_guest_mode(vcpu)))
3129 /* INITs are latched while in SMM */
3130 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3131 (events->smi.smm || events->smi.pending) &&
3132 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3136 vcpu->arch.exception.pending = events->exception.injected;
3137 vcpu->arch.exception.nr = events->exception.nr;
3138 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3139 vcpu->arch.exception.error_code = events->exception.error_code;
3141 vcpu->arch.interrupt.pending = events->interrupt.injected;
3142 vcpu->arch.interrupt.nr = events->interrupt.nr;
3143 vcpu->arch.interrupt.soft = events->interrupt.soft;
3144 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3145 kvm_x86_ops->set_interrupt_shadow(vcpu,
3146 events->interrupt.shadow);
3148 vcpu->arch.nmi_injected = events->nmi.injected;
3149 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3150 vcpu->arch.nmi_pending = events->nmi.pending;
3151 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3153 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3154 lapic_in_kernel(vcpu))
3155 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3157 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3158 u32 hflags = vcpu->arch.hflags;
3159 if (events->smi.smm)
3160 hflags |= HF_SMM_MASK;
3162 hflags &= ~HF_SMM_MASK;
3163 kvm_set_hflags(vcpu, hflags);
3165 vcpu->arch.smi_pending = events->smi.pending;
3166 if (events->smi.smm_inside_nmi)
3167 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3169 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3170 if (lapic_in_kernel(vcpu)) {
3171 if (events->smi.latched_init)
3172 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3174 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3178 kvm_make_request(KVM_REQ_EVENT, vcpu);
3183 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3184 struct kvm_debugregs *dbgregs)
3188 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3189 kvm_get_dr(vcpu, 6, &val);
3191 dbgregs->dr7 = vcpu->arch.dr7;
3193 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3196 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3197 struct kvm_debugregs *dbgregs)
3202 if (dbgregs->dr6 & ~0xffffffffull)
3204 if (dbgregs->dr7 & ~0xffffffffull)
3207 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3208 kvm_update_dr0123(vcpu);
3209 vcpu->arch.dr6 = dbgregs->dr6;
3210 kvm_update_dr6(vcpu);
3211 vcpu->arch.dr7 = dbgregs->dr7;
3212 kvm_update_dr7(vcpu);
3217 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3219 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3221 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3222 u64 xstate_bv = xsave->header.xfeatures;
3226 * Copy legacy XSAVE area, to avoid complications with CPUID
3227 * leaves 0 and 1 in the loop below.
3229 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3232 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3233 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3236 * Copy each region from the possibly compacted offset to the
3237 * non-compacted offset.
3239 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3241 u64 feature = valid & -valid;
3242 int index = fls64(feature) - 1;
3243 void *src = get_xsave_addr(xsave, feature);
3246 u32 size, offset, ecx, edx;
3247 cpuid_count(XSTATE_CPUID, index,
3248 &size, &offset, &ecx, &edx);
3249 memcpy(dest + offset, src, size);
3256 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3258 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3259 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3263 * Copy legacy XSAVE area, to avoid complications with CPUID
3264 * leaves 0 and 1 in the loop below.
3266 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3268 /* Set XSTATE_BV and possibly XCOMP_BV. */
3269 xsave->header.xfeatures = xstate_bv;
3270 if (boot_cpu_has(X86_FEATURE_XSAVES))
3271 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3274 * Copy each region from the non-compacted offset to the
3275 * possibly compacted offset.
3277 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3279 u64 feature = valid & -valid;
3280 int index = fls64(feature) - 1;
3281 void *dest = get_xsave_addr(xsave, feature);
3284 u32 size, offset, ecx, edx;
3285 cpuid_count(XSTATE_CPUID, index,
3286 &size, &offset, &ecx, &edx);
3287 memcpy(dest, src + offset, size);
3294 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3295 struct kvm_xsave *guest_xsave)
3297 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3298 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3299 fill_xsave((u8 *) guest_xsave->region, vcpu);
3301 memcpy(guest_xsave->region,
3302 &vcpu->arch.guest_fpu.state.fxsave,
3303 sizeof(struct fxregs_state));
3304 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3305 XFEATURE_MASK_FPSSE;
3309 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3310 struct kvm_xsave *guest_xsave)
3313 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3315 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3317 * Here we allow setting states that are not present in
3318 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3319 * with old userspace.
3321 if (xstate_bv & ~kvm_supported_xcr0())
3323 load_xsave(vcpu, (u8 *)guest_xsave->region);
3325 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3327 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3328 guest_xsave->region, sizeof(struct fxregs_state));
3333 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3334 struct kvm_xcrs *guest_xcrs)
3336 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3337 guest_xcrs->nr_xcrs = 0;
3341 guest_xcrs->nr_xcrs = 1;
3342 guest_xcrs->flags = 0;
3343 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3344 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3347 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3348 struct kvm_xcrs *guest_xcrs)
3352 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3355 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3358 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3359 /* Only support XCR0 currently */
3360 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3361 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3362 guest_xcrs->xcrs[i].value);
3371 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3372 * stopped by the hypervisor. This function will be called from the host only.
3373 * EINVAL is returned when the host attempts to set the flag for a guest that
3374 * does not support pv clocks.
3376 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3378 if (!vcpu->arch.pv_time_enabled)
3380 vcpu->arch.pvclock_set_guest_stopped_request = true;
3381 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3385 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3386 struct kvm_enable_cap *cap)
3392 case KVM_CAP_HYPERV_SYNIC:
3393 if (!irqchip_in_kernel(vcpu->kvm))
3395 return kvm_hv_activate_synic(vcpu);
3401 long kvm_arch_vcpu_ioctl(struct file *filp,
3402 unsigned int ioctl, unsigned long arg)
3404 struct kvm_vcpu *vcpu = filp->private_data;
3405 void __user *argp = (void __user *)arg;
3408 struct kvm_lapic_state *lapic;
3409 struct kvm_xsave *xsave;
3410 struct kvm_xcrs *xcrs;
3416 case KVM_GET_LAPIC: {
3418 if (!lapic_in_kernel(vcpu))
3420 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3425 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3429 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3434 case KVM_SET_LAPIC: {
3436 if (!lapic_in_kernel(vcpu))
3438 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3439 if (IS_ERR(u.lapic))
3440 return PTR_ERR(u.lapic);
3442 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3445 case KVM_INTERRUPT: {
3446 struct kvm_interrupt irq;
3449 if (copy_from_user(&irq, argp, sizeof irq))
3451 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3455 r = kvm_vcpu_ioctl_nmi(vcpu);
3459 r = kvm_vcpu_ioctl_smi(vcpu);
3462 case KVM_SET_CPUID: {
3463 struct kvm_cpuid __user *cpuid_arg = argp;
3464 struct kvm_cpuid cpuid;
3467 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3469 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3472 case KVM_SET_CPUID2: {
3473 struct kvm_cpuid2 __user *cpuid_arg = argp;
3474 struct kvm_cpuid2 cpuid;
3477 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3479 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3480 cpuid_arg->entries);
3483 case KVM_GET_CPUID2: {
3484 struct kvm_cpuid2 __user *cpuid_arg = argp;
3485 struct kvm_cpuid2 cpuid;
3488 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3490 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3491 cpuid_arg->entries);
3495 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3501 r = msr_io(vcpu, argp, do_get_msr, 1);
3504 r = msr_io(vcpu, argp, do_set_msr, 0);
3506 case KVM_TPR_ACCESS_REPORTING: {
3507 struct kvm_tpr_access_ctl tac;
3510 if (copy_from_user(&tac, argp, sizeof tac))
3512 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3516 if (copy_to_user(argp, &tac, sizeof tac))
3521 case KVM_SET_VAPIC_ADDR: {
3522 struct kvm_vapic_addr va;
3526 if (!lapic_in_kernel(vcpu))
3529 if (copy_from_user(&va, argp, sizeof va))
3531 idx = srcu_read_lock(&vcpu->kvm->srcu);
3532 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3533 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3536 case KVM_X86_SETUP_MCE: {
3540 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3542 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3545 case KVM_X86_SET_MCE: {
3546 struct kvm_x86_mce mce;
3549 if (copy_from_user(&mce, argp, sizeof mce))
3551 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3554 case KVM_GET_VCPU_EVENTS: {
3555 struct kvm_vcpu_events events;
3557 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3560 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3565 case KVM_SET_VCPU_EVENTS: {
3566 struct kvm_vcpu_events events;
3569 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3572 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3575 case KVM_GET_DEBUGREGS: {
3576 struct kvm_debugregs dbgregs;
3578 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3581 if (copy_to_user(argp, &dbgregs,
3582 sizeof(struct kvm_debugregs)))
3587 case KVM_SET_DEBUGREGS: {
3588 struct kvm_debugregs dbgregs;
3591 if (copy_from_user(&dbgregs, argp,
3592 sizeof(struct kvm_debugregs)))
3595 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3598 case KVM_GET_XSAVE: {
3599 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3604 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3607 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3612 case KVM_SET_XSAVE: {
3613 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3614 if (IS_ERR(u.xsave))
3615 return PTR_ERR(u.xsave);
3617 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3620 case KVM_GET_XCRS: {
3621 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3626 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3629 if (copy_to_user(argp, u.xcrs,
3630 sizeof(struct kvm_xcrs)))
3635 case KVM_SET_XCRS: {
3636 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3638 return PTR_ERR(u.xcrs);
3640 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3643 case KVM_SET_TSC_KHZ: {
3647 user_tsc_khz = (u32)arg;
3649 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3652 if (user_tsc_khz == 0)
3653 user_tsc_khz = tsc_khz;
3655 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3660 case KVM_GET_TSC_KHZ: {
3661 r = vcpu->arch.virtual_tsc_khz;
3664 case KVM_KVMCLOCK_CTRL: {
3665 r = kvm_set_guest_paused(vcpu);
3668 case KVM_ENABLE_CAP: {
3669 struct kvm_enable_cap cap;
3672 if (copy_from_user(&cap, argp, sizeof(cap)))
3674 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3685 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3687 return VM_FAULT_SIGBUS;
3690 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3694 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3696 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3700 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3703 kvm->arch.ept_identity_map_addr = ident_addr;
3707 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3708 u32 kvm_nr_mmu_pages)
3710 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3713 mutex_lock(&kvm->slots_lock);
3715 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3716 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3718 mutex_unlock(&kvm->slots_lock);
3722 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3724 return kvm->arch.n_max_mmu_pages;
3727 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3729 struct kvm_pic *pic = kvm->arch.vpic;
3733 switch (chip->chip_id) {
3734 case KVM_IRQCHIP_PIC_MASTER:
3735 memcpy(&chip->chip.pic, &pic->pics[0],
3736 sizeof(struct kvm_pic_state));
3738 case KVM_IRQCHIP_PIC_SLAVE:
3739 memcpy(&chip->chip.pic, &pic->pics[1],
3740 sizeof(struct kvm_pic_state));
3742 case KVM_IRQCHIP_IOAPIC:
3743 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3752 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3754 struct kvm_pic *pic = kvm->arch.vpic;
3758 switch (chip->chip_id) {
3759 case KVM_IRQCHIP_PIC_MASTER:
3760 spin_lock(&pic->lock);
3761 memcpy(&pic->pics[0], &chip->chip.pic,
3762 sizeof(struct kvm_pic_state));
3763 spin_unlock(&pic->lock);
3765 case KVM_IRQCHIP_PIC_SLAVE:
3766 spin_lock(&pic->lock);
3767 memcpy(&pic->pics[1], &chip->chip.pic,
3768 sizeof(struct kvm_pic_state));
3769 spin_unlock(&pic->lock);
3771 case KVM_IRQCHIP_IOAPIC:
3772 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3778 kvm_pic_update_irq(pic);
3782 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3784 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3786 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3788 mutex_lock(&kps->lock);
3789 memcpy(ps, &kps->channels, sizeof(*ps));
3790 mutex_unlock(&kps->lock);
3794 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3797 struct kvm_pit *pit = kvm->arch.vpit;
3799 mutex_lock(&pit->pit_state.lock);
3800 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3801 for (i = 0; i < 3; i++)
3802 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3803 mutex_unlock(&pit->pit_state.lock);
3807 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3809 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3810 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3811 sizeof(ps->channels));
3812 ps->flags = kvm->arch.vpit->pit_state.flags;
3813 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3814 memset(&ps->reserved, 0, sizeof(ps->reserved));
3818 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3822 u32 prev_legacy, cur_legacy;
3823 struct kvm_pit *pit = kvm->arch.vpit;
3825 mutex_lock(&pit->pit_state.lock);
3826 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3827 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3828 if (!prev_legacy && cur_legacy)
3830 memcpy(&pit->pit_state.channels, &ps->channels,
3831 sizeof(pit->pit_state.channels));
3832 pit->pit_state.flags = ps->flags;
3833 for (i = 0; i < 3; i++)
3834 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3836 mutex_unlock(&pit->pit_state.lock);
3840 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3841 struct kvm_reinject_control *control)
3843 struct kvm_pit *pit = kvm->arch.vpit;
3848 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3849 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3850 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3852 mutex_lock(&pit->pit_state.lock);
3853 kvm_pit_set_reinject(pit, control->pit_reinject);
3854 mutex_unlock(&pit->pit_state.lock);
3860 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3861 * @kvm: kvm instance
3862 * @log: slot id and address to which we copy the log
3864 * Steps 1-4 below provide general overview of dirty page logging. See
3865 * kvm_get_dirty_log_protect() function description for additional details.
3867 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3868 * always flush the TLB (step 4) even if previous step failed and the dirty
3869 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3870 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3871 * writes will be marked dirty for next log read.
3873 * 1. Take a snapshot of the bit and clear it if needed.
3874 * 2. Write protect the corresponding page.
3875 * 3. Copy the snapshot to the userspace.
3876 * 4. Flush TLB's if needed.
3878 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3880 bool is_dirty = false;
3883 mutex_lock(&kvm->slots_lock);
3886 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3888 if (kvm_x86_ops->flush_log_dirty)
3889 kvm_x86_ops->flush_log_dirty(kvm);
3891 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3894 * All the TLBs can be flushed out of mmu lock, see the comments in
3895 * kvm_mmu_slot_remove_write_access().
3897 lockdep_assert_held(&kvm->slots_lock);
3899 kvm_flush_remote_tlbs(kvm);
3901 mutex_unlock(&kvm->slots_lock);
3905 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3908 if (!irqchip_in_kernel(kvm))
3911 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3912 irq_event->irq, irq_event->level,
3917 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3918 struct kvm_enable_cap *cap)
3926 case KVM_CAP_DISABLE_QUIRKS:
3927 kvm->arch.disabled_quirks = cap->args[0];
3930 case KVM_CAP_SPLIT_IRQCHIP: {
3931 mutex_lock(&kvm->lock);
3933 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3934 goto split_irqchip_unlock;
3936 if (irqchip_in_kernel(kvm))
3937 goto split_irqchip_unlock;
3938 if (kvm->created_vcpus)
3939 goto split_irqchip_unlock;
3940 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
3941 r = kvm_setup_empty_irq_routing(kvm);
3943 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
3944 /* Pairs with smp_rmb() when reading irqchip_mode */
3946 goto split_irqchip_unlock;
3948 /* Pairs with irqchip_in_kernel. */
3950 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
3951 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3953 split_irqchip_unlock:
3954 mutex_unlock(&kvm->lock);
3957 case KVM_CAP_X2APIC_API:
3959 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3962 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3963 kvm->arch.x2apic_format = true;
3964 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3965 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3976 long kvm_arch_vm_ioctl(struct file *filp,
3977 unsigned int ioctl, unsigned long arg)
3979 struct kvm *kvm = filp->private_data;
3980 void __user *argp = (void __user *)arg;
3983 * This union makes it completely explicit to gcc-3.x
3984 * that these two variables' stack usage should be
3985 * combined, not added together.
3988 struct kvm_pit_state ps;
3989 struct kvm_pit_state2 ps2;
3990 struct kvm_pit_config pit_config;
3994 case KVM_SET_TSS_ADDR:
3995 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3997 case KVM_SET_IDENTITY_MAP_ADDR: {
4001 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4003 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4006 case KVM_SET_NR_MMU_PAGES:
4007 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4009 case KVM_GET_NR_MMU_PAGES:
4010 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4012 case KVM_CREATE_IRQCHIP: {
4013 mutex_lock(&kvm->lock);
4016 if (irqchip_in_kernel(kvm))
4017 goto create_irqchip_unlock;
4020 if (kvm->created_vcpus)
4021 goto create_irqchip_unlock;
4023 r = kvm_pic_init(kvm);
4025 goto create_irqchip_unlock;
4027 r = kvm_ioapic_init(kvm);
4029 kvm_pic_destroy(kvm);
4030 goto create_irqchip_unlock;
4033 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
4034 r = kvm_setup_default_irq_routing(kvm);
4036 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
4037 /* Pairs with smp_rmb() when reading irqchip_mode */
4039 kvm_ioapic_destroy(kvm);
4040 kvm_pic_destroy(kvm);
4041 goto create_irqchip_unlock;
4043 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4045 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4046 create_irqchip_unlock:
4047 mutex_unlock(&kvm->lock);
4050 case KVM_CREATE_PIT:
4051 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4053 case KVM_CREATE_PIT2:
4055 if (copy_from_user(&u.pit_config, argp,
4056 sizeof(struct kvm_pit_config)))
4059 mutex_lock(&kvm->lock);
4062 goto create_pit_unlock;
4064 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4068 mutex_unlock(&kvm->lock);
4070 case KVM_GET_IRQCHIP: {
4071 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4072 struct kvm_irqchip *chip;
4074 chip = memdup_user(argp, sizeof(*chip));
4081 if (!irqchip_kernel(kvm))
4082 goto get_irqchip_out;
4083 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4085 goto get_irqchip_out;
4087 if (copy_to_user(argp, chip, sizeof *chip))
4088 goto get_irqchip_out;
4094 case KVM_SET_IRQCHIP: {
4095 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4096 struct kvm_irqchip *chip;
4098 chip = memdup_user(argp, sizeof(*chip));
4105 if (!irqchip_kernel(kvm))
4106 goto set_irqchip_out;
4107 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4109 goto set_irqchip_out;
4117 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4120 if (!kvm->arch.vpit)
4122 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4126 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4133 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4136 if (!kvm->arch.vpit)
4138 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4141 case KVM_GET_PIT2: {
4143 if (!kvm->arch.vpit)
4145 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4149 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4154 case KVM_SET_PIT2: {
4156 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4159 if (!kvm->arch.vpit)
4161 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4164 case KVM_REINJECT_CONTROL: {
4165 struct kvm_reinject_control control;
4167 if (copy_from_user(&control, argp, sizeof(control)))
4169 r = kvm_vm_ioctl_reinject(kvm, &control);
4172 case KVM_SET_BOOT_CPU_ID:
4174 mutex_lock(&kvm->lock);
4175 if (kvm->created_vcpus)
4178 kvm->arch.bsp_vcpu_id = arg;
4179 mutex_unlock(&kvm->lock);
4181 case KVM_XEN_HVM_CONFIG: {
4183 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4184 sizeof(struct kvm_xen_hvm_config)))
4187 if (kvm->arch.xen_hvm_config.flags)
4192 case KVM_SET_CLOCK: {
4193 struct kvm_clock_data user_ns;
4197 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4205 local_irq_disable();
4206 now_ns = __get_kvmclock_ns(kvm);
4207 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4209 kvm_gen_update_masterclock(kvm);
4212 case KVM_GET_CLOCK: {
4213 struct kvm_clock_data user_ns;
4216 local_irq_disable();
4217 now_ns = __get_kvmclock_ns(kvm);
4218 user_ns.clock = now_ns;
4219 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4221 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4224 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4229 case KVM_ENABLE_CAP: {
4230 struct kvm_enable_cap cap;
4233 if (copy_from_user(&cap, argp, sizeof(cap)))
4235 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4245 static void kvm_init_msr_list(void)
4250 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4251 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4255 * Even MSRs that are valid in the host may not be exposed
4256 * to the guests in some cases.
4258 switch (msrs_to_save[i]) {
4259 case MSR_IA32_BNDCFGS:
4260 if (!kvm_x86_ops->mpx_supported())
4264 if (!kvm_x86_ops->rdtscp_supported())
4272 msrs_to_save[j] = msrs_to_save[i];
4275 num_msrs_to_save = j;
4277 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4278 switch (emulated_msrs[i]) {
4279 case MSR_IA32_SMBASE:
4280 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4288 emulated_msrs[j] = emulated_msrs[i];
4291 num_emulated_msrs = j;
4294 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4302 if (!(lapic_in_kernel(vcpu) &&
4303 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4304 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4315 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4322 if (!(lapic_in_kernel(vcpu) &&
4323 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4325 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4327 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4337 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4338 struct kvm_segment *var, int seg)
4340 kvm_x86_ops->set_segment(vcpu, var, seg);
4343 void kvm_get_segment(struct kvm_vcpu *vcpu,
4344 struct kvm_segment *var, int seg)
4346 kvm_x86_ops->get_segment(vcpu, var, seg);
4349 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4350 struct x86_exception *exception)
4354 BUG_ON(!mmu_is_nested(vcpu));
4356 /* NPT walks are always user-walks */
4357 access |= PFERR_USER_MASK;
4358 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4363 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4364 struct x86_exception *exception)
4366 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4367 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4370 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4371 struct x86_exception *exception)
4373 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4374 access |= PFERR_FETCH_MASK;
4375 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4378 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4379 struct x86_exception *exception)
4381 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4382 access |= PFERR_WRITE_MASK;
4383 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4386 /* uses this to access any guest's mapped memory without checking CPL */
4387 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4388 struct x86_exception *exception)
4390 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4393 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4394 struct kvm_vcpu *vcpu, u32 access,
4395 struct x86_exception *exception)
4398 int r = X86EMUL_CONTINUE;
4401 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4403 unsigned offset = addr & (PAGE_SIZE-1);
4404 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4407 if (gpa == UNMAPPED_GVA)
4408 return X86EMUL_PROPAGATE_FAULT;
4409 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4412 r = X86EMUL_IO_NEEDED;
4424 /* used for instruction fetching */
4425 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4426 gva_t addr, void *val, unsigned int bytes,
4427 struct x86_exception *exception)
4429 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4430 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4434 /* Inline kvm_read_guest_virt_helper for speed. */
4435 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4437 if (unlikely(gpa == UNMAPPED_GVA))
4438 return X86EMUL_PROPAGATE_FAULT;
4440 offset = addr & (PAGE_SIZE-1);
4441 if (WARN_ON(offset + bytes > PAGE_SIZE))
4442 bytes = (unsigned)PAGE_SIZE - offset;
4443 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4445 if (unlikely(ret < 0))
4446 return X86EMUL_IO_NEEDED;
4448 return X86EMUL_CONTINUE;
4451 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4452 gva_t addr, void *val, unsigned int bytes,
4453 struct x86_exception *exception)
4455 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4456 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4458 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4461 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4463 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4464 gva_t addr, void *val, unsigned int bytes,
4465 struct x86_exception *exception)
4467 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4468 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4471 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4472 unsigned long addr, void *val, unsigned int bytes)
4474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4475 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4477 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4480 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4481 gva_t addr, void *val,
4483 struct x86_exception *exception)
4485 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4487 int r = X86EMUL_CONTINUE;
4490 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4493 unsigned offset = addr & (PAGE_SIZE-1);
4494 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4497 if (gpa == UNMAPPED_GVA)
4498 return X86EMUL_PROPAGATE_FAULT;
4499 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4501 r = X86EMUL_IO_NEEDED;
4512 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4514 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4515 gpa_t gpa, bool write)
4517 /* For APIC access vmexit */
4518 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4521 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4522 trace_vcpu_match_mmio(gva, gpa, write, true);
4529 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4530 gpa_t *gpa, struct x86_exception *exception,
4533 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4534 | (write ? PFERR_WRITE_MASK : 0);
4537 * currently PKRU is only applied to ept enabled guest so
4538 * there is no pkey in EPT page table for L1 guest or EPT
4539 * shadow page table for L2 guest.
4541 if (vcpu_match_mmio_gva(vcpu, gva)
4542 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4543 vcpu->arch.access, 0, access)) {
4544 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4545 (gva & (PAGE_SIZE - 1));
4546 trace_vcpu_match_mmio(gva, *gpa, write, false);
4550 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4552 if (*gpa == UNMAPPED_GVA)
4555 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4558 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4559 const void *val, int bytes)
4563 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4566 kvm_page_track_write(vcpu, gpa, val, bytes);
4570 struct read_write_emulator_ops {
4571 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4573 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4574 void *val, int bytes);
4575 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4576 int bytes, void *val);
4577 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4578 void *val, int bytes);
4582 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4584 if (vcpu->mmio_read_completed) {
4585 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4586 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4587 vcpu->mmio_read_completed = 0;
4594 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4595 void *val, int bytes)
4597 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4600 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4601 void *val, int bytes)
4603 return emulator_write_phys(vcpu, gpa, val, bytes);
4606 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4608 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4609 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4612 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4613 void *val, int bytes)
4615 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4616 return X86EMUL_IO_NEEDED;
4619 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4620 void *val, int bytes)
4622 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4624 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4625 return X86EMUL_CONTINUE;
4628 static const struct read_write_emulator_ops read_emultor = {
4629 .read_write_prepare = read_prepare,
4630 .read_write_emulate = read_emulate,
4631 .read_write_mmio = vcpu_mmio_read,
4632 .read_write_exit_mmio = read_exit_mmio,
4635 static const struct read_write_emulator_ops write_emultor = {
4636 .read_write_emulate = write_emulate,
4637 .read_write_mmio = write_mmio,
4638 .read_write_exit_mmio = write_exit_mmio,
4642 static int emulator_read_write_onepage(unsigned long addr, void *val,
4644 struct x86_exception *exception,
4645 struct kvm_vcpu *vcpu,
4646 const struct read_write_emulator_ops *ops)
4650 bool write = ops->write;
4651 struct kvm_mmio_fragment *frag;
4652 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4655 * If the exit was due to a NPF we may already have a GPA.
4656 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4657 * Note, this cannot be used on string operations since string
4658 * operation using rep will only have the initial GPA from the NPF
4661 if (vcpu->arch.gpa_available &&
4662 emulator_can_use_gpa(ctxt) &&
4663 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4664 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4665 gpa = exception->address;
4669 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4672 return X86EMUL_PROPAGATE_FAULT;
4674 /* For APIC access vmexit */
4678 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4679 return X86EMUL_CONTINUE;
4683 * Is this MMIO handled locally?
4685 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4686 if (handled == bytes)
4687 return X86EMUL_CONTINUE;
4693 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4694 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4698 return X86EMUL_CONTINUE;
4701 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4703 void *val, unsigned int bytes,
4704 struct x86_exception *exception,
4705 const struct read_write_emulator_ops *ops)
4707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4711 if (ops->read_write_prepare &&
4712 ops->read_write_prepare(vcpu, val, bytes))
4713 return X86EMUL_CONTINUE;
4715 vcpu->mmio_nr_fragments = 0;
4717 /* Crossing a page boundary? */
4718 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4721 now = -addr & ~PAGE_MASK;
4722 rc = emulator_read_write_onepage(addr, val, now, exception,
4725 if (rc != X86EMUL_CONTINUE)
4728 if (ctxt->mode != X86EMUL_MODE_PROT64)
4734 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4736 if (rc != X86EMUL_CONTINUE)
4739 if (!vcpu->mmio_nr_fragments)
4742 gpa = vcpu->mmio_fragments[0].gpa;
4744 vcpu->mmio_needed = 1;
4745 vcpu->mmio_cur_fragment = 0;
4747 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4748 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4749 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4750 vcpu->run->mmio.phys_addr = gpa;
4752 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4755 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4759 struct x86_exception *exception)
4761 return emulator_read_write(ctxt, addr, val, bytes,
4762 exception, &read_emultor);
4765 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4769 struct x86_exception *exception)
4771 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4772 exception, &write_emultor);
4775 #define CMPXCHG_TYPE(t, ptr, old, new) \
4776 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4778 #ifdef CONFIG_X86_64
4779 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4781 # define CMPXCHG64(ptr, old, new) \
4782 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4785 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4790 struct x86_exception *exception)
4792 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4798 /* guests cmpxchg8b have to be emulated atomically */
4799 if (bytes > 8 || (bytes & (bytes - 1)))
4802 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4804 if (gpa == UNMAPPED_GVA ||
4805 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4808 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4811 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4812 if (is_error_page(page))
4815 kaddr = kmap_atomic(page);
4816 kaddr += offset_in_page(gpa);
4819 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4822 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4825 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4828 exchanged = CMPXCHG64(kaddr, old, new);
4833 kunmap_atomic(kaddr);
4834 kvm_release_page_dirty(page);
4837 return X86EMUL_CMPXCHG_FAILED;
4839 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4840 kvm_page_track_write(vcpu, gpa, new, bytes);
4842 return X86EMUL_CONTINUE;
4845 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4847 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4850 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4852 /* TODO: String I/O for in kernel device */
4855 if (vcpu->arch.pio.in)
4856 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4857 vcpu->arch.pio.size, pd);
4859 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4860 vcpu->arch.pio.port, vcpu->arch.pio.size,
4865 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4866 unsigned short port, void *val,
4867 unsigned int count, bool in)
4869 vcpu->arch.pio.port = port;
4870 vcpu->arch.pio.in = in;
4871 vcpu->arch.pio.count = count;
4872 vcpu->arch.pio.size = size;
4874 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4875 vcpu->arch.pio.count = 0;
4879 vcpu->run->exit_reason = KVM_EXIT_IO;
4880 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4881 vcpu->run->io.size = size;
4882 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4883 vcpu->run->io.count = count;
4884 vcpu->run->io.port = port;
4889 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4890 int size, unsigned short port, void *val,
4893 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4896 if (vcpu->arch.pio.count)
4899 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4902 memcpy(val, vcpu->arch.pio_data, size * count);
4903 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4904 vcpu->arch.pio.count = 0;
4911 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4912 int size, unsigned short port,
4913 const void *val, unsigned int count)
4915 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4917 memcpy(vcpu->arch.pio_data, val, size * count);
4918 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4919 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4922 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4924 return kvm_x86_ops->get_segment_base(vcpu, seg);
4927 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4929 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4932 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4934 if (!need_emulate_wbinvd(vcpu))
4935 return X86EMUL_CONTINUE;
4937 if (kvm_x86_ops->has_wbinvd_exit()) {
4938 int cpu = get_cpu();
4940 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4941 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4942 wbinvd_ipi, NULL, 1);
4944 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4947 return X86EMUL_CONTINUE;
4950 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4952 kvm_emulate_wbinvd_noskip(vcpu);
4953 return kvm_skip_emulated_instruction(vcpu);
4955 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4959 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4961 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4964 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4965 unsigned long *dest)
4967 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4970 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4971 unsigned long value)
4974 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4977 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4979 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4982 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4985 unsigned long value;
4989 value = kvm_read_cr0(vcpu);
4992 value = vcpu->arch.cr2;
4995 value = kvm_read_cr3(vcpu);
4998 value = kvm_read_cr4(vcpu);
5001 value = kvm_get_cr8(vcpu);
5004 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5011 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5013 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5018 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5021 vcpu->arch.cr2 = val;
5024 res = kvm_set_cr3(vcpu, val);
5027 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5030 res = kvm_set_cr8(vcpu, val);
5033 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5040 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5042 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5045 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5047 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5050 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5052 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5055 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5057 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5060 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5062 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5065 static unsigned long emulator_get_cached_segment_base(
5066 struct x86_emulate_ctxt *ctxt, int seg)
5068 return get_segment_base(emul_to_vcpu(ctxt), seg);
5071 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5072 struct desc_struct *desc, u32 *base3,
5075 struct kvm_segment var;
5077 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5078 *selector = var.selector;
5081 memset(desc, 0, sizeof(*desc));
5087 set_desc_limit(desc, var.limit);
5088 set_desc_base(desc, (unsigned long)var.base);
5089 #ifdef CONFIG_X86_64
5091 *base3 = var.base >> 32;
5093 desc->type = var.type;
5095 desc->dpl = var.dpl;
5096 desc->p = var.present;
5097 desc->avl = var.avl;
5105 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5106 struct desc_struct *desc, u32 base3,
5109 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5110 struct kvm_segment var;
5112 var.selector = selector;
5113 var.base = get_desc_base(desc);
5114 #ifdef CONFIG_X86_64
5115 var.base |= ((u64)base3) << 32;
5117 var.limit = get_desc_limit(desc);
5119 var.limit = (var.limit << 12) | 0xfff;
5120 var.type = desc->type;
5121 var.dpl = desc->dpl;
5126 var.avl = desc->avl;
5127 var.present = desc->p;
5128 var.unusable = !var.present;
5131 kvm_set_segment(vcpu, &var, seg);
5135 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5136 u32 msr_index, u64 *pdata)
5138 struct msr_data msr;
5141 msr.index = msr_index;
5142 msr.host_initiated = false;
5143 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5151 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5152 u32 msr_index, u64 data)
5154 struct msr_data msr;
5157 msr.index = msr_index;
5158 msr.host_initiated = false;
5159 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5162 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5164 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5166 return vcpu->arch.smbase;
5169 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5171 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5173 vcpu->arch.smbase = smbase;
5176 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5179 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5182 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5183 u32 pmc, u64 *pdata)
5185 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5188 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5190 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5193 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5196 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5199 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5204 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5205 struct x86_instruction_info *info,
5206 enum x86_intercept_stage stage)
5208 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5211 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5212 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5214 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5217 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5219 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5222 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5224 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5227 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5229 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5232 static const struct x86_emulate_ops emulate_ops = {
5233 .read_gpr = emulator_read_gpr,
5234 .write_gpr = emulator_write_gpr,
5235 .read_std = kvm_read_guest_virt_system,
5236 .write_std = kvm_write_guest_virt_system,
5237 .read_phys = kvm_read_guest_phys_system,
5238 .fetch = kvm_fetch_guest_virt,
5239 .read_emulated = emulator_read_emulated,
5240 .write_emulated = emulator_write_emulated,
5241 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5242 .invlpg = emulator_invlpg,
5243 .pio_in_emulated = emulator_pio_in_emulated,
5244 .pio_out_emulated = emulator_pio_out_emulated,
5245 .get_segment = emulator_get_segment,
5246 .set_segment = emulator_set_segment,
5247 .get_cached_segment_base = emulator_get_cached_segment_base,
5248 .get_gdt = emulator_get_gdt,
5249 .get_idt = emulator_get_idt,
5250 .set_gdt = emulator_set_gdt,
5251 .set_idt = emulator_set_idt,
5252 .get_cr = emulator_get_cr,
5253 .set_cr = emulator_set_cr,
5254 .cpl = emulator_get_cpl,
5255 .get_dr = emulator_get_dr,
5256 .set_dr = emulator_set_dr,
5257 .get_smbase = emulator_get_smbase,
5258 .set_smbase = emulator_set_smbase,
5259 .set_msr = emulator_set_msr,
5260 .get_msr = emulator_get_msr,
5261 .check_pmc = emulator_check_pmc,
5262 .read_pmc = emulator_read_pmc,
5263 .halt = emulator_halt,
5264 .wbinvd = emulator_wbinvd,
5265 .fix_hypercall = emulator_fix_hypercall,
5266 .get_fpu = emulator_get_fpu,
5267 .put_fpu = emulator_put_fpu,
5268 .intercept = emulator_intercept,
5269 .get_cpuid = emulator_get_cpuid,
5270 .set_nmi_mask = emulator_set_nmi_mask,
5273 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5275 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5277 * an sti; sti; sequence only disable interrupts for the first
5278 * instruction. So, if the last instruction, be it emulated or
5279 * not, left the system with the INT_STI flag enabled, it
5280 * means that the last instruction is an sti. We should not
5281 * leave the flag on in this case. The same goes for mov ss
5283 if (int_shadow & mask)
5285 if (unlikely(int_shadow || mask)) {
5286 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5288 kvm_make_request(KVM_REQ_EVENT, vcpu);
5292 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5294 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5295 if (ctxt->exception.vector == PF_VECTOR)
5296 return kvm_propagate_fault(vcpu, &ctxt->exception);
5298 if (ctxt->exception.error_code_valid)
5299 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5300 ctxt->exception.error_code);
5302 kvm_queue_exception(vcpu, ctxt->exception.vector);
5306 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5308 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5311 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5313 ctxt->eflags = kvm_get_rflags(vcpu);
5314 ctxt->eip = kvm_rip_read(vcpu);
5315 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5316 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5317 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5318 cs_db ? X86EMUL_MODE_PROT32 :
5319 X86EMUL_MODE_PROT16;
5320 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5321 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5322 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5323 ctxt->emul_flags = vcpu->arch.hflags;
5325 init_decode_cache(ctxt);
5326 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5329 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5331 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5334 init_emulate_ctxt(vcpu);
5338 ctxt->_eip = ctxt->eip + inc_eip;
5339 ret = emulate_int_real(ctxt, irq);
5341 if (ret != X86EMUL_CONTINUE)
5342 return EMULATE_FAIL;
5344 ctxt->eip = ctxt->_eip;
5345 kvm_rip_write(vcpu, ctxt->eip);
5346 kvm_set_rflags(vcpu, ctxt->eflags);
5348 if (irq == NMI_VECTOR)
5349 vcpu->arch.nmi_pending = 0;
5351 vcpu->arch.interrupt.pending = false;
5353 return EMULATE_DONE;
5355 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5357 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5359 int r = EMULATE_DONE;
5361 ++vcpu->stat.insn_emulation_fail;
5362 trace_kvm_emulate_insn_failed(vcpu);
5363 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5364 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5365 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5366 vcpu->run->internal.ndata = 0;
5369 kvm_queue_exception(vcpu, UD_VECTOR);
5374 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5375 bool write_fault_to_shadow_pgtable,
5381 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5384 if (!vcpu->arch.mmu.direct_map) {
5386 * Write permission should be allowed since only
5387 * write access need to be emulated.
5389 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5392 * If the mapping is invalid in guest, let cpu retry
5393 * it to generate fault.
5395 if (gpa == UNMAPPED_GVA)
5400 * Do not retry the unhandleable instruction if it faults on the
5401 * readonly host memory, otherwise it will goto a infinite loop:
5402 * retry instruction -> write #PF -> emulation fail -> retry
5403 * instruction -> ...
5405 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5408 * If the instruction failed on the error pfn, it can not be fixed,
5409 * report the error to userspace.
5411 if (is_error_noslot_pfn(pfn))
5414 kvm_release_pfn_clean(pfn);
5416 /* The instructions are well-emulated on direct mmu. */
5417 if (vcpu->arch.mmu.direct_map) {
5418 unsigned int indirect_shadow_pages;
5420 spin_lock(&vcpu->kvm->mmu_lock);
5421 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5422 spin_unlock(&vcpu->kvm->mmu_lock);
5424 if (indirect_shadow_pages)
5425 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5431 * if emulation was due to access to shadowed page table
5432 * and it failed try to unshadow page and re-enter the
5433 * guest to let CPU execute the instruction.
5435 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5438 * If the access faults on its page table, it can not
5439 * be fixed by unprotecting shadow page and it should
5440 * be reported to userspace.
5442 return !write_fault_to_shadow_pgtable;
5445 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5446 unsigned long cr2, int emulation_type)
5448 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5449 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5451 last_retry_eip = vcpu->arch.last_retry_eip;
5452 last_retry_addr = vcpu->arch.last_retry_addr;
5455 * If the emulation is caused by #PF and it is non-page_table
5456 * writing instruction, it means the VM-EXIT is caused by shadow
5457 * page protected, we can zap the shadow page and retry this
5458 * instruction directly.
5460 * Note: if the guest uses a non-page-table modifying instruction
5461 * on the PDE that points to the instruction, then we will unmap
5462 * the instruction and go to an infinite loop. So, we cache the
5463 * last retried eip and the last fault address, if we meet the eip
5464 * and the address again, we can break out of the potential infinite
5467 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5469 if (!(emulation_type & EMULTYPE_RETRY))
5472 if (x86_page_table_writing_insn(ctxt))
5475 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5478 vcpu->arch.last_retry_eip = ctxt->eip;
5479 vcpu->arch.last_retry_addr = cr2;
5481 if (!vcpu->arch.mmu.direct_map)
5482 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5484 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5489 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5490 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5492 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5494 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5495 /* This is a good place to trace that we are exiting SMM. */
5496 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5498 /* Process a latched INIT or SMI, if any. */
5499 kvm_make_request(KVM_REQ_EVENT, vcpu);
5502 kvm_mmu_reset_context(vcpu);
5505 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5507 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5509 vcpu->arch.hflags = emul_flags;
5511 if (changed & HF_SMM_MASK)
5512 kvm_smm_changed(vcpu);
5515 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5524 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5525 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5530 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5532 struct kvm_run *kvm_run = vcpu->run;
5535 * rflags is the old, "raw" value of the flags. The new value has
5536 * not been saved yet.
5538 * This is correct even for TF set by the guest, because "the
5539 * processor will not generate this exception after the instruction
5540 * that sets the TF flag".
5542 if (unlikely(rflags & X86_EFLAGS_TF)) {
5543 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5544 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5546 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5547 kvm_run->debug.arch.exception = DB_VECTOR;
5548 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5549 *r = EMULATE_USER_EXIT;
5552 * "Certain debug exceptions may clear bit 0-3. The
5553 * remaining contents of the DR6 register are never
5554 * cleared by the processor".
5556 vcpu->arch.dr6 &= ~15;
5557 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5558 kvm_queue_exception(vcpu, DB_VECTOR);
5563 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5565 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5566 int r = EMULATE_DONE;
5568 kvm_x86_ops->skip_emulated_instruction(vcpu);
5569 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5570 return r == EMULATE_DONE;
5572 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5574 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5576 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5577 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5578 struct kvm_run *kvm_run = vcpu->run;
5579 unsigned long eip = kvm_get_linear_rip(vcpu);
5580 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5581 vcpu->arch.guest_debug_dr7,
5585 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5586 kvm_run->debug.arch.pc = eip;
5587 kvm_run->debug.arch.exception = DB_VECTOR;
5588 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5589 *r = EMULATE_USER_EXIT;
5594 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5595 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5596 unsigned long eip = kvm_get_linear_rip(vcpu);
5597 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5602 vcpu->arch.dr6 &= ~15;
5603 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5604 kvm_queue_exception(vcpu, DB_VECTOR);
5613 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5620 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5621 bool writeback = true;
5622 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5625 * Clear write_fault_to_shadow_pgtable here to ensure it is
5628 vcpu->arch.write_fault_to_shadow_pgtable = false;
5629 kvm_clear_exception_queue(vcpu);
5631 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5632 init_emulate_ctxt(vcpu);
5635 * We will reenter on the same instruction since
5636 * we do not set complete_userspace_io. This does not
5637 * handle watchpoints yet, those would be handled in
5640 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5643 ctxt->interruptibility = 0;
5644 ctxt->have_exception = false;
5645 ctxt->exception.vector = -1;
5646 ctxt->perm_ok = false;
5648 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5650 r = x86_decode_insn(ctxt, insn, insn_len);
5652 trace_kvm_emulate_insn_start(vcpu);
5653 ++vcpu->stat.insn_emulation;
5654 if (r != EMULATION_OK) {
5655 if (emulation_type & EMULTYPE_TRAP_UD)
5656 return EMULATE_FAIL;
5657 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5659 return EMULATE_DONE;
5660 if (emulation_type & EMULTYPE_SKIP)
5661 return EMULATE_FAIL;
5662 return handle_emulation_failure(vcpu);
5666 if (emulation_type & EMULTYPE_SKIP) {
5667 kvm_rip_write(vcpu, ctxt->_eip);
5668 if (ctxt->eflags & X86_EFLAGS_RF)
5669 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5670 return EMULATE_DONE;
5673 if (retry_instruction(ctxt, cr2, emulation_type))
5674 return EMULATE_DONE;
5676 /* this is needed for vmware backdoor interface to work since it
5677 changes registers values during IO operation */
5678 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5679 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5680 emulator_invalidate_register_cache(ctxt);
5684 /* Save the faulting GPA (cr2) in the address field */
5685 ctxt->exception.address = cr2;
5687 r = x86_emulate_insn(ctxt);
5689 if (r == EMULATION_INTERCEPTED)
5690 return EMULATE_DONE;
5692 if (r == EMULATION_FAILED) {
5693 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5695 return EMULATE_DONE;
5697 return handle_emulation_failure(vcpu);
5700 if (ctxt->have_exception) {
5702 if (inject_emulated_exception(vcpu))
5704 } else if (vcpu->arch.pio.count) {
5705 if (!vcpu->arch.pio.in) {
5706 /* FIXME: return into emulator if single-stepping. */
5707 vcpu->arch.pio.count = 0;
5710 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5712 r = EMULATE_USER_EXIT;
5713 } else if (vcpu->mmio_needed) {
5714 if (!vcpu->mmio_is_write)
5716 r = EMULATE_USER_EXIT;
5717 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5718 } else if (r == EMULATION_RESTART)
5724 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5725 toggle_interruptibility(vcpu, ctxt->interruptibility);
5726 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5727 if (vcpu->arch.hflags != ctxt->emul_flags)
5728 kvm_set_hflags(vcpu, ctxt->emul_flags);
5729 kvm_rip_write(vcpu, ctxt->eip);
5730 if (r == EMULATE_DONE)
5731 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5732 if (!ctxt->have_exception ||
5733 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5734 __kvm_set_rflags(vcpu, ctxt->eflags);
5737 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5738 * do nothing, and it will be requested again as soon as
5739 * the shadow expires. But we still need to check here,
5740 * because POPF has no interrupt shadow.
5742 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5743 kvm_make_request(KVM_REQ_EVENT, vcpu);
5745 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5749 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5751 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5753 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5754 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5755 size, port, &val, 1);
5756 /* do not return to emulator after return from userspace */
5757 vcpu->arch.pio.count = 0;
5760 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5762 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5766 /* We should only ever be called with arch.pio.count equal to 1 */
5767 BUG_ON(vcpu->arch.pio.count != 1);
5769 /* For size less than 4 we merge, else we zero extend */
5770 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5774 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5775 * the copy and tracing
5777 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5778 vcpu->arch.pio.port, &val, 1);
5779 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5784 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5789 /* For size less than 4 we merge, else we zero extend */
5790 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5792 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5795 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5799 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5803 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5805 static int kvmclock_cpu_down_prep(unsigned int cpu)
5807 __this_cpu_write(cpu_tsc_khz, 0);
5811 static void tsc_khz_changed(void *data)
5813 struct cpufreq_freqs *freq = data;
5814 unsigned long khz = 0;
5818 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5819 khz = cpufreq_quick_get(raw_smp_processor_id());
5822 __this_cpu_write(cpu_tsc_khz, khz);
5825 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5828 struct cpufreq_freqs *freq = data;
5830 struct kvm_vcpu *vcpu;
5831 int i, send_ipi = 0;
5834 * We allow guests to temporarily run on slowing clocks,
5835 * provided we notify them after, or to run on accelerating
5836 * clocks, provided we notify them before. Thus time never
5839 * However, we have a problem. We can't atomically update
5840 * the frequency of a given CPU from this function; it is
5841 * merely a notifier, which can be called from any CPU.
5842 * Changing the TSC frequency at arbitrary points in time
5843 * requires a recomputation of local variables related to
5844 * the TSC for each VCPU. We must flag these local variables
5845 * to be updated and be sure the update takes place with the
5846 * new frequency before any guests proceed.
5848 * Unfortunately, the combination of hotplug CPU and frequency
5849 * change creates an intractable locking scenario; the order
5850 * of when these callouts happen is undefined with respect to
5851 * CPU hotplug, and they can race with each other. As such,
5852 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5853 * undefined; you can actually have a CPU frequency change take
5854 * place in between the computation of X and the setting of the
5855 * variable. To protect against this problem, all updates of
5856 * the per_cpu tsc_khz variable are done in an interrupt
5857 * protected IPI, and all callers wishing to update the value
5858 * must wait for a synchronous IPI to complete (which is trivial
5859 * if the caller is on the CPU already). This establishes the
5860 * necessary total order on variable updates.
5862 * Note that because a guest time update may take place
5863 * anytime after the setting of the VCPU's request bit, the
5864 * correct TSC value must be set before the request. However,
5865 * to ensure the update actually makes it to any guest which
5866 * starts running in hardware virtualization between the set
5867 * and the acquisition of the spinlock, we must also ping the
5868 * CPU after setting the request bit.
5872 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5874 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5877 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5879 spin_lock(&kvm_lock);
5880 list_for_each_entry(kvm, &vm_list, vm_list) {
5881 kvm_for_each_vcpu(i, vcpu, kvm) {
5882 if (vcpu->cpu != freq->cpu)
5884 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5885 if (vcpu->cpu != smp_processor_id())
5889 spin_unlock(&kvm_lock);
5891 if (freq->old < freq->new && send_ipi) {
5893 * We upscale the frequency. Must make the guest
5894 * doesn't see old kvmclock values while running with
5895 * the new frequency, otherwise we risk the guest sees
5896 * time go backwards.
5898 * In case we update the frequency for another cpu
5899 * (which might be in guest context) send an interrupt
5900 * to kick the cpu out of guest context. Next time
5901 * guest context is entered kvmclock will be updated,
5902 * so the guest will not see stale values.
5904 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5909 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5910 .notifier_call = kvmclock_cpufreq_notifier
5913 static int kvmclock_cpu_online(unsigned int cpu)
5915 tsc_khz_changed(NULL);
5919 static void kvm_timer_init(void)
5921 max_tsc_khz = tsc_khz;
5923 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5924 #ifdef CONFIG_CPU_FREQ
5925 struct cpufreq_policy policy;
5928 memset(&policy, 0, sizeof(policy));
5930 cpufreq_get_policy(&policy, cpu);
5931 if (policy.cpuinfo.max_freq)
5932 max_tsc_khz = policy.cpuinfo.max_freq;
5935 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5936 CPUFREQ_TRANSITION_NOTIFIER);
5938 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5940 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
5941 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5944 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5946 int kvm_is_in_guest(void)
5948 return __this_cpu_read(current_vcpu) != NULL;
5951 static int kvm_is_user_mode(void)
5955 if (__this_cpu_read(current_vcpu))
5956 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5958 return user_mode != 0;
5961 static unsigned long kvm_get_guest_ip(void)
5963 unsigned long ip = 0;
5965 if (__this_cpu_read(current_vcpu))
5966 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5971 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5972 .is_in_guest = kvm_is_in_guest,
5973 .is_user_mode = kvm_is_user_mode,
5974 .get_guest_ip = kvm_get_guest_ip,
5977 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5979 __this_cpu_write(current_vcpu, vcpu);
5981 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5983 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5985 __this_cpu_write(current_vcpu, NULL);
5987 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5989 static void kvm_set_mmio_spte_mask(void)
5992 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5995 * Set the reserved bits and the present bit of an paging-structure
5996 * entry to generate page fault with PFER.RSV = 1.
5998 /* Mask the reserved physical address bits. */
5999 mask = rsvd_bits(maxphyaddr, 51);
6001 /* Set the present bit. */
6004 #ifdef CONFIG_X86_64
6006 * If reserved bit is not supported, clear the present bit to disable
6009 if (maxphyaddr == 52)
6013 kvm_mmu_set_mmio_spte_mask(mask);
6016 #ifdef CONFIG_X86_64
6017 static void pvclock_gtod_update_fn(struct work_struct *work)
6021 struct kvm_vcpu *vcpu;
6024 spin_lock(&kvm_lock);
6025 list_for_each_entry(kvm, &vm_list, vm_list)
6026 kvm_for_each_vcpu(i, vcpu, kvm)
6027 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6028 atomic_set(&kvm_guest_has_master_clock, 0);
6029 spin_unlock(&kvm_lock);
6032 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6035 * Notification about pvclock gtod data update.
6037 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6040 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6041 struct timekeeper *tk = priv;
6043 update_pvclock_gtod(tk);
6045 /* disable master clock if host does not trust, or does not
6046 * use, TSC clocksource
6048 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6049 atomic_read(&kvm_guest_has_master_clock) != 0)
6050 queue_work(system_long_wq, &pvclock_gtod_work);
6055 static struct notifier_block pvclock_gtod_notifier = {
6056 .notifier_call = pvclock_gtod_notify,
6060 int kvm_arch_init(void *opaque)
6063 struct kvm_x86_ops *ops = opaque;
6066 printk(KERN_ERR "kvm: already loaded the other module\n");
6071 if (!ops->cpu_has_kvm_support()) {
6072 printk(KERN_ERR "kvm: no hardware support\n");
6076 if (ops->disabled_by_bios()) {
6077 printk(KERN_ERR "kvm: disabled by bios\n");
6083 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6085 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6089 r = kvm_mmu_module_init();
6091 goto out_free_percpu;
6093 kvm_set_mmio_spte_mask();
6097 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6098 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6099 PT_PRESENT_MASK, 0);
6102 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6104 if (boot_cpu_has(X86_FEATURE_XSAVE))
6105 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6108 #ifdef CONFIG_X86_64
6109 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6115 free_percpu(shared_msrs);
6120 void kvm_arch_exit(void)
6123 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6125 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6126 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6127 CPUFREQ_TRANSITION_NOTIFIER);
6128 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6129 #ifdef CONFIG_X86_64
6130 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6133 kvm_mmu_module_exit();
6134 free_percpu(shared_msrs);
6137 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6139 ++vcpu->stat.halt_exits;
6140 if (lapic_in_kernel(vcpu)) {
6141 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6144 vcpu->run->exit_reason = KVM_EXIT_HLT;
6148 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6150 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6152 int ret = kvm_skip_emulated_instruction(vcpu);
6154 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6155 * KVM_EXIT_DEBUG here.
6157 return kvm_vcpu_halt(vcpu) && ret;
6159 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6161 #ifdef CONFIG_X86_64
6162 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6163 unsigned long clock_type)
6165 struct kvm_clock_pairing clock_pairing;
6170 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6171 return -KVM_EOPNOTSUPP;
6173 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6174 return -KVM_EOPNOTSUPP;
6176 clock_pairing.sec = ts.tv_sec;
6177 clock_pairing.nsec = ts.tv_nsec;
6178 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6179 clock_pairing.flags = 0;
6182 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6183 sizeof(struct kvm_clock_pairing)))
6191 * kvm_pv_kick_cpu_op: Kick a vcpu.
6193 * @apicid - apicid of vcpu to be kicked.
6195 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6197 struct kvm_lapic_irq lapic_irq;
6199 lapic_irq.shorthand = 0;
6200 lapic_irq.dest_mode = 0;
6201 lapic_irq.dest_id = apicid;
6202 lapic_irq.msi_redir_hint = false;
6204 lapic_irq.delivery_mode = APIC_DM_REMRD;
6205 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6208 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6210 vcpu->arch.apicv_active = false;
6211 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6214 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6216 unsigned long nr, a0, a1, a2, a3, ret;
6219 r = kvm_skip_emulated_instruction(vcpu);
6221 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6222 return kvm_hv_hypercall(vcpu);
6224 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6225 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6226 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6227 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6228 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6230 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6232 op_64_bit = is_64_bit_mode(vcpu);
6241 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6247 case KVM_HC_VAPIC_POLL_IRQ:
6250 case KVM_HC_KICK_CPU:
6251 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6254 #ifdef CONFIG_X86_64
6255 case KVM_HC_CLOCK_PAIRING:
6256 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6266 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6267 ++vcpu->stat.hypercalls;
6270 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6272 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6274 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6275 char instruction[3];
6276 unsigned long rip = kvm_rip_read(vcpu);
6278 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6280 return emulator_write_emulated(ctxt, rip, instruction, 3,
6284 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6286 return vcpu->run->request_interrupt_window &&
6287 likely(!pic_in_kernel(vcpu->kvm));
6290 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6292 struct kvm_run *kvm_run = vcpu->run;
6294 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6295 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6296 kvm_run->cr8 = kvm_get_cr8(vcpu);
6297 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6298 kvm_run->ready_for_interrupt_injection =
6299 pic_in_kernel(vcpu->kvm) ||
6300 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6303 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6307 if (!kvm_x86_ops->update_cr8_intercept)
6310 if (!lapic_in_kernel(vcpu))
6313 if (vcpu->arch.apicv_active)
6316 if (!vcpu->arch.apic->vapic_addr)
6317 max_irr = kvm_lapic_find_highest_irr(vcpu);
6324 tpr = kvm_lapic_get_cr8(vcpu);
6326 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6329 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6333 /* try to reinject previous events if any */
6334 if (vcpu->arch.exception.pending) {
6335 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6336 vcpu->arch.exception.has_error_code,
6337 vcpu->arch.exception.error_code);
6339 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6340 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6343 if (vcpu->arch.exception.nr == DB_VECTOR &&
6344 (vcpu->arch.dr7 & DR7_GD)) {
6345 vcpu->arch.dr7 &= ~DR7_GD;
6346 kvm_update_dr7(vcpu);
6349 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6350 vcpu->arch.exception.has_error_code,
6351 vcpu->arch.exception.error_code,
6352 vcpu->arch.exception.reinject);
6356 if (vcpu->arch.nmi_injected) {
6357 kvm_x86_ops->set_nmi(vcpu);
6361 if (vcpu->arch.interrupt.pending) {
6362 kvm_x86_ops->set_irq(vcpu);
6366 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6367 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6372 /* try to inject new event if pending */
6373 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6374 vcpu->arch.smi_pending = false;
6376 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6377 --vcpu->arch.nmi_pending;
6378 vcpu->arch.nmi_injected = true;
6379 kvm_x86_ops->set_nmi(vcpu);
6380 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6382 * Because interrupts can be injected asynchronously, we are
6383 * calling check_nested_events again here to avoid a race condition.
6384 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6385 * proposal and current concerns. Perhaps we should be setting
6386 * KVM_REQ_EVENT only on certain events and not unconditionally?
6388 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6389 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6393 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6394 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6396 kvm_x86_ops->set_irq(vcpu);
6403 static void process_nmi(struct kvm_vcpu *vcpu)
6408 * x86 is limited to one NMI running, and one NMI pending after it.
6409 * If an NMI is already in progress, limit further NMIs to just one.
6410 * Otherwise, allow two (and we'll inject the first one immediately).
6412 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6415 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6416 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6417 kvm_make_request(KVM_REQ_EVENT, vcpu);
6420 #define put_smstate(type, buf, offset, val) \
6421 *(type *)((buf) + (offset) - 0x7e00) = val
6423 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6426 flags |= seg->g << 23;
6427 flags |= seg->db << 22;
6428 flags |= seg->l << 21;
6429 flags |= seg->avl << 20;
6430 flags |= seg->present << 15;
6431 flags |= seg->dpl << 13;
6432 flags |= seg->s << 12;
6433 flags |= seg->type << 8;
6437 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6439 struct kvm_segment seg;
6442 kvm_get_segment(vcpu, &seg, n);
6443 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6446 offset = 0x7f84 + n * 12;
6448 offset = 0x7f2c + (n - 3) * 12;
6450 put_smstate(u32, buf, offset + 8, seg.base);
6451 put_smstate(u32, buf, offset + 4, seg.limit);
6452 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6455 #ifdef CONFIG_X86_64
6456 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6458 struct kvm_segment seg;
6462 kvm_get_segment(vcpu, &seg, n);
6463 offset = 0x7e00 + n * 16;
6465 flags = enter_smm_get_segment_flags(&seg) >> 8;
6466 put_smstate(u16, buf, offset, seg.selector);
6467 put_smstate(u16, buf, offset + 2, flags);
6468 put_smstate(u32, buf, offset + 4, seg.limit);
6469 put_smstate(u64, buf, offset + 8, seg.base);
6473 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6476 struct kvm_segment seg;
6480 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6481 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6482 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6483 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6485 for (i = 0; i < 8; i++)
6486 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6488 kvm_get_dr(vcpu, 6, &val);
6489 put_smstate(u32, buf, 0x7fcc, (u32)val);
6490 kvm_get_dr(vcpu, 7, &val);
6491 put_smstate(u32, buf, 0x7fc8, (u32)val);
6493 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6494 put_smstate(u32, buf, 0x7fc4, seg.selector);
6495 put_smstate(u32, buf, 0x7f64, seg.base);
6496 put_smstate(u32, buf, 0x7f60, seg.limit);
6497 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6499 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6500 put_smstate(u32, buf, 0x7fc0, seg.selector);
6501 put_smstate(u32, buf, 0x7f80, seg.base);
6502 put_smstate(u32, buf, 0x7f7c, seg.limit);
6503 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6505 kvm_x86_ops->get_gdt(vcpu, &dt);
6506 put_smstate(u32, buf, 0x7f74, dt.address);
6507 put_smstate(u32, buf, 0x7f70, dt.size);
6509 kvm_x86_ops->get_idt(vcpu, &dt);
6510 put_smstate(u32, buf, 0x7f58, dt.address);
6511 put_smstate(u32, buf, 0x7f54, dt.size);
6513 for (i = 0; i < 6; i++)
6514 enter_smm_save_seg_32(vcpu, buf, i);
6516 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6519 put_smstate(u32, buf, 0x7efc, 0x00020000);
6520 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6523 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6525 #ifdef CONFIG_X86_64
6527 struct kvm_segment seg;
6531 for (i = 0; i < 16; i++)
6532 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6534 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6535 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6537 kvm_get_dr(vcpu, 6, &val);
6538 put_smstate(u64, buf, 0x7f68, val);
6539 kvm_get_dr(vcpu, 7, &val);
6540 put_smstate(u64, buf, 0x7f60, val);
6542 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6543 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6544 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6546 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6549 put_smstate(u32, buf, 0x7efc, 0x00020064);
6551 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6553 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6554 put_smstate(u16, buf, 0x7e90, seg.selector);
6555 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6556 put_smstate(u32, buf, 0x7e94, seg.limit);
6557 put_smstate(u64, buf, 0x7e98, seg.base);
6559 kvm_x86_ops->get_idt(vcpu, &dt);
6560 put_smstate(u32, buf, 0x7e84, dt.size);
6561 put_smstate(u64, buf, 0x7e88, dt.address);
6563 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6564 put_smstate(u16, buf, 0x7e70, seg.selector);
6565 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6566 put_smstate(u32, buf, 0x7e74, seg.limit);
6567 put_smstate(u64, buf, 0x7e78, seg.base);
6569 kvm_x86_ops->get_gdt(vcpu, &dt);
6570 put_smstate(u32, buf, 0x7e64, dt.size);
6571 put_smstate(u64, buf, 0x7e68, dt.address);
6573 for (i = 0; i < 6; i++)
6574 enter_smm_save_seg_64(vcpu, buf, i);
6580 static void enter_smm(struct kvm_vcpu *vcpu)
6582 struct kvm_segment cs, ds;
6587 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6588 vcpu->arch.hflags |= HF_SMM_MASK;
6589 memset(buf, 0, 512);
6590 if (guest_cpuid_has_longmode(vcpu))
6591 enter_smm_save_state_64(vcpu, buf);
6593 enter_smm_save_state_32(vcpu, buf);
6595 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6597 if (kvm_x86_ops->get_nmi_mask(vcpu))
6598 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6600 kvm_x86_ops->set_nmi_mask(vcpu, true);
6602 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6603 kvm_rip_write(vcpu, 0x8000);
6605 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6606 kvm_x86_ops->set_cr0(vcpu, cr0);
6607 vcpu->arch.cr0 = cr0;
6609 kvm_x86_ops->set_cr4(vcpu, 0);
6611 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6612 dt.address = dt.size = 0;
6613 kvm_x86_ops->set_idt(vcpu, &dt);
6615 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6617 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6618 cs.base = vcpu->arch.smbase;
6623 cs.limit = ds.limit = 0xffffffff;
6624 cs.type = ds.type = 0x3;
6625 cs.dpl = ds.dpl = 0;
6630 cs.avl = ds.avl = 0;
6631 cs.present = ds.present = 1;
6632 cs.unusable = ds.unusable = 0;
6633 cs.padding = ds.padding = 0;
6635 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6636 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6637 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6638 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6639 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6640 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6642 if (guest_cpuid_has_longmode(vcpu))
6643 kvm_x86_ops->set_efer(vcpu, 0);
6645 kvm_update_cpuid(vcpu);
6646 kvm_mmu_reset_context(vcpu);
6649 static void process_smi(struct kvm_vcpu *vcpu)
6651 vcpu->arch.smi_pending = true;
6652 kvm_make_request(KVM_REQ_EVENT, vcpu);
6655 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6657 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6660 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6662 u64 eoi_exit_bitmap[4];
6664 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6667 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6669 if (irqchip_split(vcpu->kvm))
6670 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6672 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6673 kvm_x86_ops->sync_pir_to_irr(vcpu);
6674 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6676 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6677 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6678 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6681 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6683 ++vcpu->stat.tlb_flush;
6684 kvm_x86_ops->tlb_flush(vcpu);
6687 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6689 struct page *page = NULL;
6691 if (!lapic_in_kernel(vcpu))
6694 if (!kvm_x86_ops->set_apic_access_page_addr)
6697 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6698 if (is_error_page(page))
6700 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6703 * Do not pin apic access page in memory, the MMU notifier
6704 * will call us again if it is migrated or swapped out.
6708 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6710 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6711 unsigned long address)
6714 * The physical address of apic access page is stored in the VMCS.
6715 * Update it when it becomes invalid.
6717 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6718 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6722 * Returns 1 to let vcpu_run() continue the guest execution loop without
6723 * exiting to the userspace. Otherwise, the value will be returned to the
6726 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6730 dm_request_for_irq_injection(vcpu) &&
6731 kvm_cpu_accept_dm_intr(vcpu);
6733 bool req_immediate_exit = false;
6735 if (vcpu->requests) {
6736 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6737 kvm_mmu_unload(vcpu);
6738 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6739 __kvm_migrate_timers(vcpu);
6740 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6741 kvm_gen_update_masterclock(vcpu->kvm);
6742 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6743 kvm_gen_kvmclock_update(vcpu);
6744 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6745 r = kvm_guest_time_update(vcpu);
6749 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6750 kvm_mmu_sync_roots(vcpu);
6751 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6752 kvm_vcpu_flush_tlb(vcpu);
6753 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6754 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6758 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6759 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6763 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6764 /* Page is swapped out. Do synthetic halt */
6765 vcpu->arch.apf.halted = true;
6769 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6770 record_steal_time(vcpu);
6771 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6773 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6775 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6776 kvm_pmu_handle_event(vcpu);
6777 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6778 kvm_pmu_deliver_pmi(vcpu);
6779 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6780 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6781 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6782 vcpu->arch.ioapic_handled_vectors)) {
6783 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6784 vcpu->run->eoi.vector =
6785 vcpu->arch.pending_ioapic_eoi;
6790 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6791 vcpu_scan_ioapic(vcpu);
6792 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6793 kvm_vcpu_reload_apic_access_page(vcpu);
6794 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6795 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6796 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6800 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6801 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6802 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6806 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6807 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6808 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6814 * KVM_REQ_HV_STIMER has to be processed after
6815 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6816 * depend on the guest clock being up-to-date
6818 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6819 kvm_hv_process_stimers(vcpu);
6822 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6823 ++vcpu->stat.req_event;
6824 kvm_apic_accept_events(vcpu);
6825 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6830 if (inject_pending_event(vcpu, req_int_win) != 0)
6831 req_immediate_exit = true;
6833 /* Enable NMI/IRQ window open exits if needed.
6835 * SMIs have two cases: 1) they can be nested, and
6836 * then there is nothing to do here because RSM will
6837 * cause a vmexit anyway; 2) or the SMI can be pending
6838 * because inject_pending_event has completed the
6839 * injection of an IRQ or NMI from the previous vmexit,
6840 * and then we request an immediate exit to inject the SMI.
6842 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6843 req_immediate_exit = true;
6844 if (vcpu->arch.nmi_pending)
6845 kvm_x86_ops->enable_nmi_window(vcpu);
6846 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6847 kvm_x86_ops->enable_irq_window(vcpu);
6850 if (kvm_lapic_enabled(vcpu)) {
6851 update_cr8_intercept(vcpu);
6852 kvm_lapic_sync_to_vapic(vcpu);
6856 r = kvm_mmu_reload(vcpu);
6858 goto cancel_injection;
6863 kvm_x86_ops->prepare_guest_switch(vcpu);
6864 kvm_load_guest_fpu(vcpu);
6867 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6868 * IPI are then delayed after guest entry, which ensures that they
6869 * result in virtual interrupt delivery.
6871 local_irq_disable();
6872 vcpu->mode = IN_GUEST_MODE;
6874 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6877 * 1) We should set ->mode before checking ->requests. Please see
6878 * the comment in kvm_make_all_cpus_request.
6880 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6881 * pairs with the memory barrier implicit in pi_test_and_set_on
6882 * (see vmx_deliver_posted_interrupt).
6884 * 3) This also orders the write to mode from any reads to the page
6885 * tables done while the VCPU is running. Please see the comment
6886 * in kvm_flush_remote_tlbs.
6888 smp_mb__after_srcu_read_unlock();
6891 * This handles the case where a posted interrupt was
6892 * notified with kvm_vcpu_kick.
6894 if (kvm_lapic_enabled(vcpu)) {
6895 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6896 kvm_x86_ops->sync_pir_to_irr(vcpu);
6899 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6900 || need_resched() || signal_pending(current)) {
6901 vcpu->mode = OUTSIDE_GUEST_MODE;
6905 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6907 goto cancel_injection;
6910 kvm_load_guest_xcr0(vcpu);
6912 if (req_immediate_exit) {
6913 kvm_make_request(KVM_REQ_EVENT, vcpu);
6914 smp_send_reschedule(vcpu->cpu);
6917 trace_kvm_entry(vcpu->vcpu_id);
6918 wait_lapic_expire(vcpu);
6919 guest_enter_irqoff();
6921 if (unlikely(vcpu->arch.switch_db_regs)) {
6923 set_debugreg(vcpu->arch.eff_db[0], 0);
6924 set_debugreg(vcpu->arch.eff_db[1], 1);
6925 set_debugreg(vcpu->arch.eff_db[2], 2);
6926 set_debugreg(vcpu->arch.eff_db[3], 3);
6927 set_debugreg(vcpu->arch.dr6, 6);
6928 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6931 kvm_x86_ops->run(vcpu);
6934 * Do this here before restoring debug registers on the host. And
6935 * since we do this before handling the vmexit, a DR access vmexit
6936 * can (a) read the correct value of the debug registers, (b) set
6937 * KVM_DEBUGREG_WONT_EXIT again.
6939 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6940 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6941 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6942 kvm_update_dr0123(vcpu);
6943 kvm_update_dr6(vcpu);
6944 kvm_update_dr7(vcpu);
6945 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6949 * If the guest has used debug registers, at least dr7
6950 * will be disabled while returning to the host.
6951 * If we don't have active breakpoints in the host, we don't
6952 * care about the messed up debug address registers. But if
6953 * we have some of them active, restore the old state.
6955 if (hw_breakpoint_active())
6956 hw_breakpoint_restore();
6958 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6960 vcpu->mode = OUTSIDE_GUEST_MODE;
6963 kvm_put_guest_xcr0(vcpu);
6965 kvm_x86_ops->handle_external_intr(vcpu);
6969 guest_exit_irqoff();
6974 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6977 * Profile KVM exit RIPs:
6979 if (unlikely(prof_on == KVM_PROFILING)) {
6980 unsigned long rip = kvm_rip_read(vcpu);
6981 profile_hit(KVM_PROFILING, (void *)rip);
6984 if (unlikely(vcpu->arch.tsc_always_catchup))
6985 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6987 if (vcpu->arch.apic_attention)
6988 kvm_lapic_sync_from_vapic(vcpu);
6990 r = kvm_x86_ops->handle_exit(vcpu);
6994 kvm_x86_ops->cancel_injection(vcpu);
6995 if (unlikely(vcpu->arch.apic_attention))
6996 kvm_lapic_sync_from_vapic(vcpu);
7001 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7003 if (!kvm_arch_vcpu_runnable(vcpu) &&
7004 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7005 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7006 kvm_vcpu_block(vcpu);
7007 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7009 if (kvm_x86_ops->post_block)
7010 kvm_x86_ops->post_block(vcpu);
7012 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7016 kvm_apic_accept_events(vcpu);
7017 switch(vcpu->arch.mp_state) {
7018 case KVM_MP_STATE_HALTED:
7019 vcpu->arch.pv.pv_unhalted = false;
7020 vcpu->arch.mp_state =
7021 KVM_MP_STATE_RUNNABLE;
7022 case KVM_MP_STATE_RUNNABLE:
7023 vcpu->arch.apf.halted = false;
7025 case KVM_MP_STATE_INIT_RECEIVED:
7034 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7036 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7037 kvm_x86_ops->check_nested_events(vcpu, false);
7039 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7040 !vcpu->arch.apf.halted);
7043 static int vcpu_run(struct kvm_vcpu *vcpu)
7046 struct kvm *kvm = vcpu->kvm;
7048 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7051 if (kvm_vcpu_running(vcpu)) {
7052 r = vcpu_enter_guest(vcpu);
7054 r = vcpu_block(kvm, vcpu);
7060 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7061 if (kvm_cpu_has_pending_timer(vcpu))
7062 kvm_inject_pending_timer_irqs(vcpu);
7064 if (dm_request_for_irq_injection(vcpu) &&
7065 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7067 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7068 ++vcpu->stat.request_irq_exits;
7072 kvm_check_async_pf_completion(vcpu);
7074 if (signal_pending(current)) {
7076 vcpu->run->exit_reason = KVM_EXIT_INTR;
7077 ++vcpu->stat.signal_exits;
7080 if (need_resched()) {
7081 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7083 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7087 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7092 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7095 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7096 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7097 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7098 if (r != EMULATE_DONE)
7103 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7105 BUG_ON(!vcpu->arch.pio.count);
7107 return complete_emulated_io(vcpu);
7111 * Implements the following, as a state machine:
7115 * for each mmio piece in the fragment
7123 * for each mmio piece in the fragment
7128 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7130 struct kvm_run *run = vcpu->run;
7131 struct kvm_mmio_fragment *frag;
7134 BUG_ON(!vcpu->mmio_needed);
7136 /* Complete previous fragment */
7137 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7138 len = min(8u, frag->len);
7139 if (!vcpu->mmio_is_write)
7140 memcpy(frag->data, run->mmio.data, len);
7142 if (frag->len <= 8) {
7143 /* Switch to the next fragment. */
7145 vcpu->mmio_cur_fragment++;
7147 /* Go forward to the next mmio piece. */
7153 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7154 vcpu->mmio_needed = 0;
7156 /* FIXME: return into emulator if single-stepping. */
7157 if (vcpu->mmio_is_write)
7159 vcpu->mmio_read_completed = 1;
7160 return complete_emulated_io(vcpu);
7163 run->exit_reason = KVM_EXIT_MMIO;
7164 run->mmio.phys_addr = frag->gpa;
7165 if (vcpu->mmio_is_write)
7166 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7167 run->mmio.len = min(8u, frag->len);
7168 run->mmio.is_write = vcpu->mmio_is_write;
7169 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7174 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7176 struct fpu *fpu = ¤t->thread.fpu;
7180 fpu__activate_curr(fpu);
7182 if (vcpu->sigset_active)
7183 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7185 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7186 kvm_vcpu_block(vcpu);
7187 kvm_apic_accept_events(vcpu);
7188 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
7193 /* re-sync apic's tpr */
7194 if (!lapic_in_kernel(vcpu)) {
7195 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7201 if (unlikely(vcpu->arch.complete_userspace_io)) {
7202 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7203 vcpu->arch.complete_userspace_io = NULL;
7208 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7210 if (kvm_run->immediate_exit)
7216 post_kvm_run_save(vcpu);
7217 if (vcpu->sigset_active)
7218 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7223 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7225 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7227 * We are here if userspace calls get_regs() in the middle of
7228 * instruction emulation. Registers state needs to be copied
7229 * back from emulation context to vcpu. Userspace shouldn't do
7230 * that usually, but some bad designed PV devices (vmware
7231 * backdoor interface) need this to work
7233 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7234 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7236 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7237 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7238 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7239 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7240 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7241 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7242 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7243 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7244 #ifdef CONFIG_X86_64
7245 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7246 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7247 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7248 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7249 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7250 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7251 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7252 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7255 regs->rip = kvm_rip_read(vcpu);
7256 regs->rflags = kvm_get_rflags(vcpu);
7261 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7263 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7264 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7266 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7267 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7268 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7269 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7270 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7271 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7272 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7273 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7274 #ifdef CONFIG_X86_64
7275 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7276 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7277 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7278 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7279 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7280 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7281 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7282 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7285 kvm_rip_write(vcpu, regs->rip);
7286 kvm_set_rflags(vcpu, regs->rflags);
7288 vcpu->arch.exception.pending = false;
7290 kvm_make_request(KVM_REQ_EVENT, vcpu);
7295 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7297 struct kvm_segment cs;
7299 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7303 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7305 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7306 struct kvm_sregs *sregs)
7310 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7311 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7312 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7313 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7314 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7315 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7317 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7318 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7320 kvm_x86_ops->get_idt(vcpu, &dt);
7321 sregs->idt.limit = dt.size;
7322 sregs->idt.base = dt.address;
7323 kvm_x86_ops->get_gdt(vcpu, &dt);
7324 sregs->gdt.limit = dt.size;
7325 sregs->gdt.base = dt.address;
7327 sregs->cr0 = kvm_read_cr0(vcpu);
7328 sregs->cr2 = vcpu->arch.cr2;
7329 sregs->cr3 = kvm_read_cr3(vcpu);
7330 sregs->cr4 = kvm_read_cr4(vcpu);
7331 sregs->cr8 = kvm_get_cr8(vcpu);
7332 sregs->efer = vcpu->arch.efer;
7333 sregs->apic_base = kvm_get_apic_base(vcpu);
7335 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7337 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7338 set_bit(vcpu->arch.interrupt.nr,
7339 (unsigned long *)sregs->interrupt_bitmap);
7344 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7345 struct kvm_mp_state *mp_state)
7347 kvm_apic_accept_events(vcpu);
7348 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7349 vcpu->arch.pv.pv_unhalted)
7350 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7352 mp_state->mp_state = vcpu->arch.mp_state;
7357 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7358 struct kvm_mp_state *mp_state)
7360 if (!lapic_in_kernel(vcpu) &&
7361 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7364 /* INITs are latched while in SMM */
7365 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7366 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7367 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7370 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7371 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7372 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7374 vcpu->arch.mp_state = mp_state->mp_state;
7375 kvm_make_request(KVM_REQ_EVENT, vcpu);
7379 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7380 int reason, bool has_error_code, u32 error_code)
7382 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7385 init_emulate_ctxt(vcpu);
7387 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7388 has_error_code, error_code);
7391 return EMULATE_FAIL;
7393 kvm_rip_write(vcpu, ctxt->eip);
7394 kvm_set_rflags(vcpu, ctxt->eflags);
7395 kvm_make_request(KVM_REQ_EVENT, vcpu);
7396 return EMULATE_DONE;
7398 EXPORT_SYMBOL_GPL(kvm_task_switch);
7400 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7401 struct kvm_sregs *sregs)
7403 struct msr_data apic_base_msr;
7404 int mmu_reset_needed = 0;
7405 int pending_vec, max_bits, idx;
7408 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7411 dt.size = sregs->idt.limit;
7412 dt.address = sregs->idt.base;
7413 kvm_x86_ops->set_idt(vcpu, &dt);
7414 dt.size = sregs->gdt.limit;
7415 dt.address = sregs->gdt.base;
7416 kvm_x86_ops->set_gdt(vcpu, &dt);
7418 vcpu->arch.cr2 = sregs->cr2;
7419 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7420 vcpu->arch.cr3 = sregs->cr3;
7421 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7423 kvm_set_cr8(vcpu, sregs->cr8);
7425 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7426 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7427 apic_base_msr.data = sregs->apic_base;
7428 apic_base_msr.host_initiated = true;
7429 kvm_set_apic_base(vcpu, &apic_base_msr);
7431 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7432 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7433 vcpu->arch.cr0 = sregs->cr0;
7435 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7436 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7437 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7438 kvm_update_cpuid(vcpu);
7440 idx = srcu_read_lock(&vcpu->kvm->srcu);
7441 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7442 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7443 mmu_reset_needed = 1;
7445 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7447 if (mmu_reset_needed)
7448 kvm_mmu_reset_context(vcpu);
7450 max_bits = KVM_NR_INTERRUPTS;
7451 pending_vec = find_first_bit(
7452 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7453 if (pending_vec < max_bits) {
7454 kvm_queue_interrupt(vcpu, pending_vec, false);
7455 pr_debug("Set back pending irq %d\n", pending_vec);
7458 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7459 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7460 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7461 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7462 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7463 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7465 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7466 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7468 update_cr8_intercept(vcpu);
7470 /* Older userspace won't unhalt the vcpu on reset. */
7471 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7472 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7474 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7476 kvm_make_request(KVM_REQ_EVENT, vcpu);
7481 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7482 struct kvm_guest_debug *dbg)
7484 unsigned long rflags;
7487 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7489 if (vcpu->arch.exception.pending)
7491 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7492 kvm_queue_exception(vcpu, DB_VECTOR);
7494 kvm_queue_exception(vcpu, BP_VECTOR);
7498 * Read rflags as long as potentially injected trace flags are still
7501 rflags = kvm_get_rflags(vcpu);
7503 vcpu->guest_debug = dbg->control;
7504 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7505 vcpu->guest_debug = 0;
7507 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7508 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7509 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7510 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7512 for (i = 0; i < KVM_NR_DB_REGS; i++)
7513 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7515 kvm_update_dr7(vcpu);
7517 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7518 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7519 get_segment_base(vcpu, VCPU_SREG_CS);
7522 * Trigger an rflags update that will inject or remove the trace
7525 kvm_set_rflags(vcpu, rflags);
7527 kvm_x86_ops->update_bp_intercept(vcpu);
7537 * Translate a guest virtual address to a guest physical address.
7539 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7540 struct kvm_translation *tr)
7542 unsigned long vaddr = tr->linear_address;
7546 idx = srcu_read_lock(&vcpu->kvm->srcu);
7547 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7548 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7549 tr->physical_address = gpa;
7550 tr->valid = gpa != UNMAPPED_GVA;
7557 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7559 struct fxregs_state *fxsave =
7560 &vcpu->arch.guest_fpu.state.fxsave;
7562 memcpy(fpu->fpr, fxsave->st_space, 128);
7563 fpu->fcw = fxsave->cwd;
7564 fpu->fsw = fxsave->swd;
7565 fpu->ftwx = fxsave->twd;
7566 fpu->last_opcode = fxsave->fop;
7567 fpu->last_ip = fxsave->rip;
7568 fpu->last_dp = fxsave->rdp;
7569 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7574 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7576 struct fxregs_state *fxsave =
7577 &vcpu->arch.guest_fpu.state.fxsave;
7579 memcpy(fxsave->st_space, fpu->fpr, 128);
7580 fxsave->cwd = fpu->fcw;
7581 fxsave->swd = fpu->fsw;
7582 fxsave->twd = fpu->ftwx;
7583 fxsave->fop = fpu->last_opcode;
7584 fxsave->rip = fpu->last_ip;
7585 fxsave->rdp = fpu->last_dp;
7586 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7591 static void fx_init(struct kvm_vcpu *vcpu)
7593 fpstate_init(&vcpu->arch.guest_fpu.state);
7594 if (boot_cpu_has(X86_FEATURE_XSAVES))
7595 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7596 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7599 * Ensure guest xcr0 is valid for loading
7601 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7603 vcpu->arch.cr0 |= X86_CR0_ET;
7606 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7608 if (vcpu->guest_fpu_loaded)
7612 * Restore all possible states in the guest,
7613 * and assume host would use all available bits.
7614 * Guest xcr0 would be loaded later.
7616 vcpu->guest_fpu_loaded = 1;
7617 __kernel_fpu_begin();
7618 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7622 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7624 if (!vcpu->guest_fpu_loaded)
7627 vcpu->guest_fpu_loaded = 0;
7628 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7630 ++vcpu->stat.fpu_reload;
7634 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7636 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7638 kvmclock_reset(vcpu);
7640 kvm_x86_ops->vcpu_free(vcpu);
7641 free_cpumask_var(wbinvd_dirty_mask);
7644 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7647 struct kvm_vcpu *vcpu;
7649 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7650 printk_once(KERN_WARNING
7651 "kvm: SMP vm created on host with unstable TSC; "
7652 "guest TSC will not be reliable\n");
7654 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7659 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7663 kvm_vcpu_mtrr_init(vcpu);
7664 r = vcpu_load(vcpu);
7667 kvm_vcpu_reset(vcpu, false);
7668 kvm_mmu_setup(vcpu);
7673 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7675 struct msr_data msr;
7676 struct kvm *kvm = vcpu->kvm;
7678 if (vcpu_load(vcpu))
7681 msr.index = MSR_IA32_TSC;
7682 msr.host_initiated = true;
7683 kvm_write_tsc(vcpu, &msr);
7686 if (!kvmclock_periodic_sync)
7689 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7690 KVMCLOCK_SYNC_PERIOD);
7693 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7696 vcpu->arch.apf.msr_val = 0;
7698 r = vcpu_load(vcpu);
7700 kvm_mmu_unload(vcpu);
7703 kvm_x86_ops->vcpu_free(vcpu);
7706 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7708 vcpu->arch.hflags = 0;
7710 vcpu->arch.smi_pending = 0;
7711 atomic_set(&vcpu->arch.nmi_queued, 0);
7712 vcpu->arch.nmi_pending = 0;
7713 vcpu->arch.nmi_injected = false;
7714 kvm_clear_interrupt_queue(vcpu);
7715 kvm_clear_exception_queue(vcpu);
7717 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7718 kvm_update_dr0123(vcpu);
7719 vcpu->arch.dr6 = DR6_INIT;
7720 kvm_update_dr6(vcpu);
7721 vcpu->arch.dr7 = DR7_FIXED_1;
7722 kvm_update_dr7(vcpu);
7726 kvm_make_request(KVM_REQ_EVENT, vcpu);
7727 vcpu->arch.apf.msr_val = 0;
7728 vcpu->arch.st.msr_val = 0;
7730 kvmclock_reset(vcpu);
7732 kvm_clear_async_pf_completion_queue(vcpu);
7733 kvm_async_pf_hash_reset(vcpu);
7734 vcpu->arch.apf.halted = false;
7737 kvm_pmu_reset(vcpu);
7738 vcpu->arch.smbase = 0x30000;
7740 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7741 vcpu->arch.msr_misc_features_enables = 0;
7744 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7745 vcpu->arch.regs_avail = ~0;
7746 vcpu->arch.regs_dirty = ~0;
7748 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7751 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7753 struct kvm_segment cs;
7755 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7756 cs.selector = vector << 8;
7757 cs.base = vector << 12;
7758 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7759 kvm_rip_write(vcpu, 0);
7762 int kvm_arch_hardware_enable(void)
7765 struct kvm_vcpu *vcpu;
7770 bool stable, backwards_tsc = false;
7772 kvm_shared_msr_cpu_online();
7773 ret = kvm_x86_ops->hardware_enable();
7777 local_tsc = rdtsc();
7778 stable = !check_tsc_unstable();
7779 list_for_each_entry(kvm, &vm_list, vm_list) {
7780 kvm_for_each_vcpu(i, vcpu, kvm) {
7781 if (!stable && vcpu->cpu == smp_processor_id())
7782 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7783 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7784 backwards_tsc = true;
7785 if (vcpu->arch.last_host_tsc > max_tsc)
7786 max_tsc = vcpu->arch.last_host_tsc;
7792 * Sometimes, even reliable TSCs go backwards. This happens on
7793 * platforms that reset TSC during suspend or hibernate actions, but
7794 * maintain synchronization. We must compensate. Fortunately, we can
7795 * detect that condition here, which happens early in CPU bringup,
7796 * before any KVM threads can be running. Unfortunately, we can't
7797 * bring the TSCs fully up to date with real time, as we aren't yet far
7798 * enough into CPU bringup that we know how much real time has actually
7799 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7800 * variables that haven't been updated yet.
7802 * So we simply find the maximum observed TSC above, then record the
7803 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7804 * the adjustment will be applied. Note that we accumulate
7805 * adjustments, in case multiple suspend cycles happen before some VCPU
7806 * gets a chance to run again. In the event that no KVM threads get a
7807 * chance to run, we will miss the entire elapsed period, as we'll have
7808 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7809 * loose cycle time. This isn't too big a deal, since the loss will be
7810 * uniform across all VCPUs (not to mention the scenario is extremely
7811 * unlikely). It is possible that a second hibernate recovery happens
7812 * much faster than a first, causing the observed TSC here to be
7813 * smaller; this would require additional padding adjustment, which is
7814 * why we set last_host_tsc to the local tsc observed here.
7816 * N.B. - this code below runs only on platforms with reliable TSC,
7817 * as that is the only way backwards_tsc is set above. Also note
7818 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7819 * have the same delta_cyc adjustment applied if backwards_tsc
7820 * is detected. Note further, this adjustment is only done once,
7821 * as we reset last_host_tsc on all VCPUs to stop this from being
7822 * called multiple times (one for each physical CPU bringup).
7824 * Platforms with unreliable TSCs don't have to deal with this, they
7825 * will be compensated by the logic in vcpu_load, which sets the TSC to
7826 * catchup mode. This will catchup all VCPUs to real time, but cannot
7827 * guarantee that they stay in perfect synchronization.
7829 if (backwards_tsc) {
7830 u64 delta_cyc = max_tsc - local_tsc;
7831 backwards_tsc_observed = true;
7832 list_for_each_entry(kvm, &vm_list, vm_list) {
7833 kvm_for_each_vcpu(i, vcpu, kvm) {
7834 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7835 vcpu->arch.last_host_tsc = local_tsc;
7836 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7840 * We have to disable TSC offset matching.. if you were
7841 * booting a VM while issuing an S4 host suspend....
7842 * you may have some problem. Solving this issue is
7843 * left as an exercise to the reader.
7845 kvm->arch.last_tsc_nsec = 0;
7846 kvm->arch.last_tsc_write = 0;
7853 void kvm_arch_hardware_disable(void)
7855 kvm_x86_ops->hardware_disable();
7856 drop_user_return_notifiers();
7859 int kvm_arch_hardware_setup(void)
7863 r = kvm_x86_ops->hardware_setup();
7867 if (kvm_has_tsc_control) {
7869 * Make sure the user can only configure tsc_khz values that
7870 * fit into a signed integer.
7871 * A min value is not calculated needed because it will always
7872 * be 1 on all machines.
7874 u64 max = min(0x7fffffffULL,
7875 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7876 kvm_max_guest_tsc_khz = max;
7878 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7881 kvm_init_msr_list();
7885 void kvm_arch_hardware_unsetup(void)
7887 kvm_x86_ops->hardware_unsetup();
7890 void kvm_arch_check_processor_compat(void *rtn)
7892 kvm_x86_ops->check_processor_compatibility(rtn);
7895 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7897 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7899 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7901 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7903 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7906 struct static_key kvm_no_apic_vcpu __read_mostly;
7907 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7909 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7915 BUG_ON(vcpu->kvm == NULL);
7918 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7919 vcpu->arch.pv.pv_unhalted = false;
7920 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7921 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7922 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7924 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7926 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7931 vcpu->arch.pio_data = page_address(page);
7933 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7935 r = kvm_mmu_create(vcpu);
7937 goto fail_free_pio_data;
7939 if (irqchip_in_kernel(kvm)) {
7940 r = kvm_create_lapic(vcpu);
7942 goto fail_mmu_destroy;
7944 static_key_slow_inc(&kvm_no_apic_vcpu);
7946 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7948 if (!vcpu->arch.mce_banks) {
7950 goto fail_free_lapic;
7952 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7954 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7956 goto fail_free_mce_banks;
7961 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7962 vcpu->arch.pv_time_enabled = false;
7964 vcpu->arch.guest_supported_xcr0 = 0;
7965 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7967 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7969 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7971 kvm_async_pf_hash_reset(vcpu);
7974 vcpu->arch.pending_external_vector = -1;
7976 kvm_hv_vcpu_init(vcpu);
7980 fail_free_mce_banks:
7981 kfree(vcpu->arch.mce_banks);
7983 kvm_free_lapic(vcpu);
7985 kvm_mmu_destroy(vcpu);
7987 free_page((unsigned long)vcpu->arch.pio_data);
7992 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7996 kvm_hv_vcpu_uninit(vcpu);
7997 kvm_pmu_destroy(vcpu);
7998 kfree(vcpu->arch.mce_banks);
7999 kvm_free_lapic(vcpu);
8000 idx = srcu_read_lock(&vcpu->kvm->srcu);
8001 kvm_mmu_destroy(vcpu);
8002 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8003 free_page((unsigned long)vcpu->arch.pio_data);
8004 if (!lapic_in_kernel(vcpu))
8005 static_key_slow_dec(&kvm_no_apic_vcpu);
8008 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8010 kvm_x86_ops->sched_in(vcpu, cpu);
8013 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8018 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8019 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8020 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8021 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8022 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8024 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8025 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8026 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8027 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8028 &kvm->arch.irq_sources_bitmap);
8030 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8031 mutex_init(&kvm->arch.apic_map_lock);
8032 mutex_init(&kvm->arch.hyperv.hv_lock);
8033 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8035 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8036 pvclock_update_vm_gtod_copy(kvm);
8038 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8039 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8041 kvm_page_track_init(kvm);
8042 kvm_mmu_init_vm(kvm);
8044 if (kvm_x86_ops->vm_init)
8045 return kvm_x86_ops->vm_init(kvm);
8050 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8053 r = vcpu_load(vcpu);
8055 kvm_mmu_unload(vcpu);
8059 static void kvm_free_vcpus(struct kvm *kvm)
8062 struct kvm_vcpu *vcpu;
8065 * Unpin any mmu pages first.
8067 kvm_for_each_vcpu(i, vcpu, kvm) {
8068 kvm_clear_async_pf_completion_queue(vcpu);
8069 kvm_unload_vcpu_mmu(vcpu);
8071 kvm_for_each_vcpu(i, vcpu, kvm)
8072 kvm_arch_vcpu_free(vcpu);
8074 mutex_lock(&kvm->lock);
8075 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8076 kvm->vcpus[i] = NULL;
8078 atomic_set(&kvm->online_vcpus, 0);
8079 mutex_unlock(&kvm->lock);
8082 void kvm_arch_sync_events(struct kvm *kvm)
8084 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8085 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8089 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8093 struct kvm_memslots *slots = kvm_memslots(kvm);
8094 struct kvm_memory_slot *slot, old;
8096 /* Called with kvm->slots_lock held. */
8097 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8100 slot = id_to_memslot(slots, id);
8106 * MAP_SHARED to prevent internal slot pages from being moved
8109 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8110 MAP_SHARED | MAP_ANONYMOUS, 0);
8111 if (IS_ERR((void *)hva))
8112 return PTR_ERR((void *)hva);
8121 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8122 struct kvm_userspace_memory_region m;
8124 m.slot = id | (i << 16);
8126 m.guest_phys_addr = gpa;
8127 m.userspace_addr = hva;
8128 m.memory_size = size;
8129 r = __kvm_set_memory_region(kvm, &m);
8135 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8141 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8143 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8147 mutex_lock(&kvm->slots_lock);
8148 r = __x86_set_memory_region(kvm, id, gpa, size);
8149 mutex_unlock(&kvm->slots_lock);
8153 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8155 void kvm_arch_destroy_vm(struct kvm *kvm)
8157 if (current->mm == kvm->mm) {
8159 * Free memory regions allocated on behalf of userspace,
8160 * unless the the memory map has changed due to process exit
8163 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8164 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8165 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8167 if (kvm_x86_ops->vm_destroy)
8168 kvm_x86_ops->vm_destroy(kvm);
8169 kvm_pic_destroy(kvm);
8170 kvm_ioapic_destroy(kvm);
8171 kvm_free_vcpus(kvm);
8172 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8173 kvm_mmu_uninit_vm(kvm);
8174 kvm_page_track_cleanup(kvm);
8177 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8178 struct kvm_memory_slot *dont)
8182 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8183 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8184 kvfree(free->arch.rmap[i]);
8185 free->arch.rmap[i] = NULL;
8190 if (!dont || free->arch.lpage_info[i - 1] !=
8191 dont->arch.lpage_info[i - 1]) {
8192 kvfree(free->arch.lpage_info[i - 1]);
8193 free->arch.lpage_info[i - 1] = NULL;
8197 kvm_page_track_free_memslot(free, dont);
8200 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8201 unsigned long npages)
8205 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8206 struct kvm_lpage_info *linfo;
8211 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8212 slot->base_gfn, level) + 1;
8214 slot->arch.rmap[i] =
8215 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8216 if (!slot->arch.rmap[i])
8221 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8225 slot->arch.lpage_info[i - 1] = linfo;
8227 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8228 linfo[0].disallow_lpage = 1;
8229 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8230 linfo[lpages - 1].disallow_lpage = 1;
8231 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8233 * If the gfn and userspace address are not aligned wrt each
8234 * other, or if explicitly asked to, disable large page
8235 * support for this slot
8237 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8238 !kvm_largepages_enabled()) {
8241 for (j = 0; j < lpages; ++j)
8242 linfo[j].disallow_lpage = 1;
8246 if (kvm_page_track_create_memslot(slot, npages))
8252 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8253 kvfree(slot->arch.rmap[i]);
8254 slot->arch.rmap[i] = NULL;
8258 kvfree(slot->arch.lpage_info[i - 1]);
8259 slot->arch.lpage_info[i - 1] = NULL;
8264 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8267 * memslots->generation has been incremented.
8268 * mmio generation may have reached its maximum value.
8270 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8273 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8274 struct kvm_memory_slot *memslot,
8275 const struct kvm_userspace_memory_region *mem,
8276 enum kvm_mr_change change)
8281 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8282 struct kvm_memory_slot *new)
8284 /* Still write protect RO slot */
8285 if (new->flags & KVM_MEM_READONLY) {
8286 kvm_mmu_slot_remove_write_access(kvm, new);
8291 * Call kvm_x86_ops dirty logging hooks when they are valid.
8293 * kvm_x86_ops->slot_disable_log_dirty is called when:
8295 * - KVM_MR_CREATE with dirty logging is disabled
8296 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8298 * The reason is, in case of PML, we need to set D-bit for any slots
8299 * with dirty logging disabled in order to eliminate unnecessary GPA
8300 * logging in PML buffer (and potential PML buffer full VMEXT). This
8301 * guarantees leaving PML enabled during guest's lifetime won't have
8302 * any additonal overhead from PML when guest is running with dirty
8303 * logging disabled for memory slots.
8305 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8306 * to dirty logging mode.
8308 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8310 * In case of write protect:
8312 * Write protect all pages for dirty logging.
8314 * All the sptes including the large sptes which point to this
8315 * slot are set to readonly. We can not create any new large
8316 * spte on this slot until the end of the logging.
8318 * See the comments in fast_page_fault().
8320 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8321 if (kvm_x86_ops->slot_enable_log_dirty)
8322 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8324 kvm_mmu_slot_remove_write_access(kvm, new);
8326 if (kvm_x86_ops->slot_disable_log_dirty)
8327 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8331 void kvm_arch_commit_memory_region(struct kvm *kvm,
8332 const struct kvm_userspace_memory_region *mem,
8333 const struct kvm_memory_slot *old,
8334 const struct kvm_memory_slot *new,
8335 enum kvm_mr_change change)
8337 int nr_mmu_pages = 0;
8339 if (!kvm->arch.n_requested_mmu_pages)
8340 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8343 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8346 * Dirty logging tracks sptes in 4k granularity, meaning that large
8347 * sptes have to be split. If live migration is successful, the guest
8348 * in the source machine will be destroyed and large sptes will be
8349 * created in the destination. However, if the guest continues to run
8350 * in the source machine (for example if live migration fails), small
8351 * sptes will remain around and cause bad performance.
8353 * Scan sptes if dirty logging has been stopped, dropping those
8354 * which can be collapsed into a single large-page spte. Later
8355 * page faults will create the large-page sptes.
8357 if ((change != KVM_MR_DELETE) &&
8358 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8359 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8360 kvm_mmu_zap_collapsible_sptes(kvm, new);
8363 * Set up write protection and/or dirty logging for the new slot.
8365 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8366 * been zapped so no dirty logging staff is needed for old slot. For
8367 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8368 * new and it's also covered when dealing with the new slot.
8370 * FIXME: const-ify all uses of struct kvm_memory_slot.
8372 if (change != KVM_MR_DELETE)
8373 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8376 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8378 kvm_mmu_invalidate_zap_all_pages(kvm);
8381 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8382 struct kvm_memory_slot *slot)
8384 kvm_page_track_flush_slot(kvm, slot);
8387 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8389 if (!list_empty_careful(&vcpu->async_pf.done))
8392 if (kvm_apic_has_events(vcpu))
8395 if (vcpu->arch.pv.pv_unhalted)
8398 if (atomic_read(&vcpu->arch.nmi_queued))
8401 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8404 if (kvm_arch_interrupt_allowed(vcpu) &&
8405 kvm_cpu_has_interrupt(vcpu))
8408 if (kvm_hv_has_stimer_pending(vcpu))
8414 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8416 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8419 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8421 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8424 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8426 return kvm_x86_ops->interrupt_allowed(vcpu);
8429 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8431 if (is_64_bit_mode(vcpu))
8432 return kvm_rip_read(vcpu);
8433 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8434 kvm_rip_read(vcpu));
8436 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8438 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8440 return kvm_get_linear_rip(vcpu) == linear_rip;
8442 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8444 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8446 unsigned long rflags;
8448 rflags = kvm_x86_ops->get_rflags(vcpu);
8449 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8450 rflags &= ~X86_EFLAGS_TF;
8453 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8455 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8457 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8458 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8459 rflags |= X86_EFLAGS_TF;
8460 kvm_x86_ops->set_rflags(vcpu, rflags);
8463 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8465 __kvm_set_rflags(vcpu, rflags);
8466 kvm_make_request(KVM_REQ_EVENT, vcpu);
8468 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8470 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8474 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8478 r = kvm_mmu_reload(vcpu);
8482 if (!vcpu->arch.mmu.direct_map &&
8483 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8486 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8489 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8491 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8494 static inline u32 kvm_async_pf_next_probe(u32 key)
8496 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8499 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8501 u32 key = kvm_async_pf_hash_fn(gfn);
8503 while (vcpu->arch.apf.gfns[key] != ~0)
8504 key = kvm_async_pf_next_probe(key);
8506 vcpu->arch.apf.gfns[key] = gfn;
8509 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8512 u32 key = kvm_async_pf_hash_fn(gfn);
8514 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8515 (vcpu->arch.apf.gfns[key] != gfn &&
8516 vcpu->arch.apf.gfns[key] != ~0); i++)
8517 key = kvm_async_pf_next_probe(key);
8522 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8524 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8527 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8531 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8533 vcpu->arch.apf.gfns[i] = ~0;
8535 j = kvm_async_pf_next_probe(j);
8536 if (vcpu->arch.apf.gfns[j] == ~0)
8538 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8540 * k lies cyclically in ]i,j]
8542 * |....j i.k.| or |.k..j i...|
8544 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8545 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8550 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8552 return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apf.data, &val,
8556 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8557 struct kvm_async_pf *work)
8559 struct x86_exception fault;
8561 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8562 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8564 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8565 (vcpu->arch.apf.send_user_only &&
8566 kvm_x86_ops->get_cpl(vcpu) == 0))
8567 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8568 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8569 fault.vector = PF_VECTOR;
8570 fault.error_code_valid = true;
8571 fault.error_code = 0;
8572 fault.nested_page_fault = false;
8573 fault.address = work->arch.token;
8574 kvm_inject_page_fault(vcpu, &fault);
8578 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8579 struct kvm_async_pf *work)
8581 struct x86_exception fault;
8583 if (work->wakeup_all)
8584 work->arch.token = ~0; /* broadcast wakeup */
8586 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8587 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8589 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8590 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8591 fault.vector = PF_VECTOR;
8592 fault.error_code_valid = true;
8593 fault.error_code = 0;
8594 fault.nested_page_fault = false;
8595 fault.address = work->arch.token;
8596 kvm_inject_page_fault(vcpu, &fault);
8598 vcpu->arch.apf.halted = false;
8599 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8602 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8604 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8607 return !kvm_event_needs_reinjection(vcpu) &&
8608 kvm_x86_ops->interrupt_allowed(vcpu);
8611 void kvm_arch_start_assignment(struct kvm *kvm)
8613 atomic_inc(&kvm->arch.assigned_device_count);
8615 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8617 void kvm_arch_end_assignment(struct kvm *kvm)
8619 atomic_dec(&kvm->arch.assigned_device_count);
8621 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8623 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8625 return atomic_read(&kvm->arch.assigned_device_count);
8627 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8629 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8631 atomic_inc(&kvm->arch.noncoherent_dma_count);
8633 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8635 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8637 atomic_dec(&kvm->arch.noncoherent_dma_count);
8639 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8641 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8643 return atomic_read(&kvm->arch.noncoherent_dma_count);
8645 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8647 bool kvm_arch_has_irq_bypass(void)
8649 return kvm_x86_ops->update_pi_irte != NULL;
8652 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8653 struct irq_bypass_producer *prod)
8655 struct kvm_kernel_irqfd *irqfd =
8656 container_of(cons, struct kvm_kernel_irqfd, consumer);
8658 irqfd->producer = prod;
8660 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8661 prod->irq, irqfd->gsi, 1);
8664 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8665 struct irq_bypass_producer *prod)
8668 struct kvm_kernel_irqfd *irqfd =
8669 container_of(cons, struct kvm_kernel_irqfd, consumer);
8671 WARN_ON(irqfd->producer != prod);
8672 irqfd->producer = NULL;
8675 * When producer of consumer is unregistered, we change back to
8676 * remapped mode, so we can re-use the current implementation
8677 * when the irq is masked/disabled or the consumer side (KVM
8678 * int this case doesn't want to receive the interrupts.
8680 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8682 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8683 " fails: %d\n", irqfd->consumer.token, ret);
8686 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8687 uint32_t guest_irq, bool set)
8689 if (!kvm_x86_ops->update_pi_irte)
8692 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8695 bool kvm_vector_hashing_enabled(void)
8697 return vector_hashing;
8699 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8701 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8702 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8703 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8704 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8705 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8706 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8707 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8708 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8709 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8710 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8711 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8712 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8713 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8714 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8715 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8716 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8717 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8718 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8719 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);