2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include "assigned-dev.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
58 #define CREATE_TRACE_POINTS
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64 __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
126 static bool __read_mostly vector_hashing = true;
127 module_param(vector_hashing, bool, S_IRUGO);
129 static bool __read_mostly backwards_tsc_observed = false;
131 #define KVM_NR_SHARED_MSRS 16
133 struct kvm_shared_msrs_global {
135 u32 msrs[KVM_NR_SHARED_MSRS];
138 struct kvm_shared_msrs {
139 struct user_return_notifier urn;
141 struct kvm_shared_msr_values {
144 } values[KVM_NR_SHARED_MSRS];
147 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
148 static struct kvm_shared_msrs __percpu *shared_msrs;
150 struct kvm_stats_debugfs_item debugfs_entries[] = {
151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
161 { "halt_exits", VCPU_STAT(halt_exits) },
162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
165 { "hypercalls", VCPU_STAT(hypercalls) },
166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
173 { "irq_injections", VCPU_STAT(irq_injections) },
174 { "nmi_injections", VCPU_STAT(nmi_injections) },
175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
182 { "mmu_unsync", VM_STAT(mmu_unsync) },
183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
184 { "largepages", VM_STAT(lpages) },
188 u64 __read_mostly host_xcr0;
190 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
192 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
199 static void kvm_on_user_return(struct user_return_notifier *urn)
202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
204 struct kvm_shared_msr_values *values;
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
217 static void shared_msr_update(unsigned slot, u32 msr)
220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
234 void kvm_define_shared_msr(unsigned slot, u32 msr)
236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
237 shared_msrs_global.msrs[slot] = msr;
238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
241 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
243 static void kvm_shared_msr_cpu_online(void)
247 for (i = 0; i < shared_msrs_global.nr; ++i)
248 shared_msr_update(i, shared_msrs_global.msrs[i]);
251 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
259 smsr->values[slot].curr = value;
260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
271 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
273 static void drop_user_return_notifiers(void)
275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
282 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
284 return vcpu->arch.apic_base;
286 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
288 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
306 kvm_lapic_set_base(vcpu, msr_info->data);
309 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
311 asmlinkage __visible void kvm_spurious_fault(void)
313 /* Fault while not rebooting. We want the trace. */
316 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
318 #define EXCPT_BENIGN 0
319 #define EXCPT_CONTRIBUTORY 1
322 static int exception_class(int vector)
332 return EXCPT_CONTRIBUTORY;
339 #define EXCPT_FAULT 0
341 #define EXCPT_ABORT 2
342 #define EXCPT_INTERRUPT 3
344 static int exception_type(int vector)
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
360 /* Reserved exceptions will result in fault */
364 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
365 unsigned nr, bool has_error, u32 error_code,
371 kvm_make_request(KVM_REQ_EVENT, vcpu);
373 if (!vcpu->arch.exception.pending) {
375 if (has_error && !is_protmode(vcpu))
377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
381 vcpu->arch.exception.reinject = reinject;
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
408 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
410 kvm_multiple_exception(vcpu, nr, false, 0, false);
412 EXPORT_SYMBOL_GPL(kvm_queue_exception);
414 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
418 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
420 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
423 kvm_inject_gp(vcpu, 0);
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
427 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
429 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
431 ++vcpu->stat.pf_guest;
432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
435 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
437 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
444 return fault->nested_page_fault;
447 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
452 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
454 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
458 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
460 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
464 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
470 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
477 EXPORT_SYMBOL_GPL(kvm_require_cpl);
479 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
484 kvm_queue_exception(vcpu, UD_VECTOR);
487 EXPORT_SYMBOL_GPL(kvm_require_dr);
490 * This function will be used to read from the physical memory of the currently
491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
492 * can read from guest physical or from the guest's guest physical memory.
494 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
498 struct x86_exception exception;
502 ngpa = gfn_to_gpa(ngfn);
503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
504 if (real_gfn == UNMAPPED_GVA)
507 real_gfn = gpa_to_gfn(real_gfn);
509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
511 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
513 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
514 void *data, int offset, int len, u32 access)
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
521 * Load the pae pdptrs. Return true is they are all valid.
523 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
539 if (is_present_gpte(pdpte[i]) &&
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
557 EXPORT_SYMBOL_GPL(load_pdptrs);
559 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
586 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
594 if (cr0 & 0xffffffff00000000UL)
598 cr0 &= ~CR0_RESERVED_BITS;
600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
608 if ((vcpu->arch.efer & EFER_LME)) {
613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
626 kvm_x86_ops->set_cr0(vcpu, cr0);
628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
629 kvm_clear_async_pf_completion_queue(vcpu);
630 kvm_async_pf_hash_reset(vcpu);
633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
643 EXPORT_SYMBOL_GPL(kvm_set_cr0);
645 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
649 EXPORT_SYMBOL_GPL(kvm_lmsw);
651 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
661 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
670 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
673 u64 old_xcr0 = vcpu->arch.xcr0;
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
679 if (!(xcr0 & XFEATURE_MASK_FP))
681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
690 if (xcr0 & ~valid_bits)
693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
703 kvm_put_guest_xcr0(vcpu);
704 vcpu->arch.xcr0 = xcr0;
706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
707 kvm_update_cpuid(vcpu);
711 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
715 kvm_inject_gp(vcpu, 0);
720 EXPORT_SYMBOL_GPL(kvm_set_xcr);
722 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
728 if (cr4 & CR4_RESERVED_BITS)
731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
746 if (is_long_mode(vcpu)) {
747 if (!(cr4 & X86_CR4_PAE))
749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
750 && ((cr4 ^ old_cr4) & pdptr_bits)
751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
756 if (!guest_cpuid_has_pcid(vcpu))
759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
764 if (kvm_x86_ops->set_cr4(vcpu, cr4))
767 if (((cr4 ^ old_cr4) & pdptr_bits) ||
768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
769 kvm_mmu_reset_context(vcpu);
771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
772 kvm_update_cpuid(vcpu);
776 EXPORT_SYMBOL_GPL(kvm_set_cr4);
778 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
781 cr3 &= ~CR3_PCID_INVD;
784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
785 kvm_mmu_sync_roots(vcpu);
786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
790 if (is_long_mode(vcpu)) {
791 if (cr3 & CR3_L_MODE_RESERVED_BITS)
793 } else if (is_pae(vcpu) && is_paging(vcpu) &&
794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
797 vcpu->arch.cr3 = cr3;
798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
799 kvm_mmu_new_cr3(vcpu);
802 EXPORT_SYMBOL_GPL(kvm_set_cr3);
804 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
806 if (cr8 & CR8_RESERVED_BITS)
808 if (lapic_in_kernel(vcpu))
809 kvm_lapic_set_tpr(vcpu, cr8);
811 vcpu->arch.cr8 = cr8;
814 EXPORT_SYMBOL_GPL(kvm_set_cr8);
816 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
818 if (lapic_in_kernel(vcpu))
819 return kvm_lapic_get_cr8(vcpu);
821 return vcpu->arch.cr8;
823 EXPORT_SYMBOL_GPL(kvm_get_cr8);
825 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
830 for (i = 0; i < KVM_NR_DB_REGS; i++)
831 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
836 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
842 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
847 dr7 = vcpu->arch.guest_debug_dr7;
849 dr7 = vcpu->arch.dr7;
850 kvm_x86_ops->set_dr7(vcpu, dr7);
851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
852 if (dr7 & DR7_BP_EN_MASK)
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
856 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
858 u64 fixed = DR6_FIXED_1;
860 if (!guest_cpuid_has_rtm(vcpu))
865 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
869 vcpu->arch.db[dr] = val;
870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
871 vcpu->arch.eff_db[dr] = val;
876 if (val & 0xffffffff00000000ULL)
878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
879 kvm_update_dr6(vcpu);
884 if (val & 0xffffffff00000000ULL)
886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
887 kvm_update_dr7(vcpu);
894 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
896 if (__kvm_set_dr(vcpu, dr, val)) {
897 kvm_inject_gp(vcpu, 0);
902 EXPORT_SYMBOL_GPL(kvm_set_dr);
904 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
908 *val = vcpu->arch.db[dr];
913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
914 *val = vcpu->arch.dr6;
916 *val = kvm_x86_ops->get_dr6(vcpu);
921 *val = vcpu->arch.dr7;
926 EXPORT_SYMBOL_GPL(kvm_get_dr);
928 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
934 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
941 EXPORT_SYMBOL_GPL(kvm_rdpmc);
944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
947 * This list is modified at module load time to reflect the
948 * capabilities of the host cpu. This capabilities test skips MSRs that are
949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
950 * may depend on host virtualization features rather than host cpu features.
953 static u32 msrs_to_save[] = {
954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
963 static unsigned num_msrs_to_save;
965 static u32 emulated_msrs[] = {
966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
974 HV_X64_MSR_VP_RUNTIME,
976 HV_X64_MSR_STIMER0_CONFIG,
977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
981 MSR_IA32_TSCDEADLINE,
982 MSR_IA32_MISC_ENABLE,
988 static unsigned num_emulated_msrs;
990 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
992 if (efer & efer_reserved_bits)
995 if (efer & EFER_FFXSR) {
996 struct kvm_cpuid_entry2 *feat;
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1003 if (efer & EFER_SVME) {
1004 struct kvm_cpuid_entry2 *feat;
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1013 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1015 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1017 u64 old_efer = vcpu->arch.efer;
1019 if (!kvm_valid_efer(vcpu, efer))
1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1027 efer |= vcpu->arch.efer & EFER_LMA;
1029 kvm_x86_ops->set_efer(vcpu, efer);
1031 /* Update reserved bits */
1032 if ((efer ^ old_efer) & EFER_NX)
1033 kvm_mmu_reset_context(vcpu);
1038 void kvm_enable_efer_bits(u64 mask)
1040 efer_reserved_bits &= ~mask;
1042 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1045 * Writes msr value into into the appropriate "register".
1046 * Returns 0 on success, non-0 otherwise.
1047 * Assumes vcpu_load() was already called.
1049 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1051 switch (msr->index) {
1054 case MSR_KERNEL_GS_BASE:
1057 if (is_noncanonical_address(msr->data))
1060 case MSR_IA32_SYSENTER_EIP:
1061 case MSR_IA32_SYSENTER_ESP:
1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1064 * non-canonical address is written on Intel but not on
1065 * AMD (which ignores the top 32-bits, because it does
1066 * not implement 64-bit SYSENTER).
1068 * 64-bit code should hence be able to write a non-canonical
1069 * value on AMD. Making the address canonical ensures that
1070 * vmentry does not fail on Intel after writing a non-canonical
1071 * value, and that something deterministic happens if the guest
1072 * invokes 64-bit SYSENTER.
1074 msr->data = get_canonical(msr->data);
1076 return kvm_x86_ops->set_msr(vcpu, msr);
1078 EXPORT_SYMBOL_GPL(kvm_set_msr);
1081 * Adapt set_msr() to msr_io()'s calling convention
1083 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1085 struct msr_data msr;
1089 msr.host_initiated = true;
1090 r = kvm_get_msr(vcpu, &msr);
1098 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1100 struct msr_data msr;
1104 msr.host_initiated = true;
1105 return kvm_set_msr(vcpu, &msr);
1108 #ifdef CONFIG_X86_64
1109 struct pvclock_gtod_data {
1112 struct { /* extract of a clocksource struct */
1124 static struct pvclock_gtod_data pvclock_gtod_data;
1126 static void update_pvclock_gtod(struct timekeeper *tk)
1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1133 write_seqcount_begin(&vdata->seq);
1135 /* copy pvclock gtod data */
1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1138 vdata->clock.mask = tk->tkr_mono.mask;
1139 vdata->clock.mult = tk->tkr_mono.mult;
1140 vdata->clock.shift = tk->tkr_mono.shift;
1142 vdata->boot_ns = boot_ns;
1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1145 write_seqcount_end(&vdata->seq);
1149 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1153 * vcpu_enter_guest. This function is only called from
1154 * the physical CPU that is running vcpu.
1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1159 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1163 struct pvclock_wall_clock wc;
1164 struct timespec boot;
1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1174 ++version; /* first time write, random junk */
1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1182 * The guest calculates current wall clock time by adding
1183 * system time (updated by kvm_guest_time_update below) to the
1184 * wall clock specified here. guest system time equals host
1185 * system time for us, thus we must fill in host boot time here.
1189 if (kvm->arch.kvmclock_offset) {
1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1191 boot = timespec_sub(boot, ts);
1193 wc.sec = boot.tv_sec;
1194 wc.nsec = boot.tv_nsec;
1195 wc.version = version;
1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1203 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1205 do_shl32_div32(dividend, divisor);
1209 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1210 s8 *pshift, u32 *pmultiplier)
1218 scaled64 = scaled_hz;
1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1224 tps32 = (uint32_t)tps64;
1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1234 *pmultiplier = div_frac(scaled64, tps32);
1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1237 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1240 #ifdef CONFIG_X86_64
1241 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1244 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1245 static unsigned long max_tsc_khz;
1247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
1253 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1255 u64 v = (u64)khz * (1000000 + ppm);
1260 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1264 /* Guest TSC same frequency as host TSC? */
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1296 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
1301 /* tsc_khz can be zero if TSC calibration fails */
1302 if (user_tsc_khz == 0) {
1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1308 /* Compute a scale to convert nanoseconds in TSC cycles */
1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1329 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
1334 tsc += vcpu->arch.this_tsc_write;
1338 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1340 #ifdef CONFIG_X86_64
1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1366 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1373 * Multiply tsc by a fixed point number represented by ratio.
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1382 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1397 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1399 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1405 return target_tsc - tsc;
1408 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1412 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1414 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1416 struct kvm *kvm = vcpu->kvm;
1417 u64 offset, ns, elapsed;
1418 unsigned long flags;
1421 bool already_matched;
1422 u64 data = msr->data;
1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1425 offset = kvm_compute_tsc_offset(vcpu, data);
1426 ns = get_kernel_ns();
1427 elapsed = ns - kvm->arch.last_tsc_nsec;
1429 if (vcpu->arch.virtual_tsc_khz) {
1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
1434 #ifdef CONFIG_X86_64
1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1437 /* do_div() only does unsigned */
1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1447 _ASM_EXTABLE(1b, 4b)
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1453 do_div(elapsed, 1000);
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1460 usdiff = USEC_PER_SEC;
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1474 if (usdiff < USEC_PER_SEC &&
1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1476 if (!check_tsc_unstable()) {
1477 offset = kvm->arch.cur_tsc_offset;
1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
1482 offset = kvm_compute_tsc_offset(vcpu, data);
1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
1493 * exact software computation in compute_guest_tsc()
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1503 kvm->arch.cur_tsc_generation, data);
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1514 vcpu->arch.last_guest_tsc = data;
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1528 kvm->arch.nr_vcpus_matched_tsc = 0;
1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1537 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1539 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1545 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1553 #ifdef CONFIG_X86_64
1555 static cycle_t read_tsc(void)
1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
1560 if (likely(ret >= last))
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a function of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1575 static inline u64 vgettsc(cycle_t *cycle_now)
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1580 *cycle_now = read_tsc();
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1586 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1594 seq = read_seqcount_begin(>od->seq);
1595 mode = gtod->clock.vclock_mode;
1596 ns = gtod->nsec_base;
1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
1599 ns += gtod->boot_ns;
1600 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1606 /* returns true if host is using tsc clocksource */
1607 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
1622 * CPUs at the next numbered event.
1624 * "timespecX" represents host monotonic time. "tscX" represents
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1642 * - 0 < N - M => M < N
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1658 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1660 #ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1663 bool host_tsc_clocksource, vcpus_matched;
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
1669 * If the host uses TSC clock, then passthrough TSC as stable
1672 host_tsc_clocksource = kvm_get_time_and_clockread(
1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1689 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1694 static void kvm_gen_update_masterclock(struct kvm *kvm)
1696 #ifdef CONFIG_X86_64
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1706 kvm_for_each_vcpu(i, vcpu, kvm)
1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1717 static int kvm_guest_time_update(struct kvm_vcpu *v)
1719 unsigned long flags, tgt_tsc_khz;
1720 struct kvm_vcpu_arch *vcpu = &v->arch;
1721 struct kvm_arch *ka = &v->kvm->arch;
1723 u64 tsc_timestamp, host_tsc;
1724 struct pvclock_vcpu_time_info guest_hv_clock;
1726 bool use_master_clock;
1732 * If the host uses TSC clock, then passthrough TSC as stable
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(tgt_tsc_khz == 0)) {
1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1751 if (!use_master_clock) {
1753 kernel_ns = get_kernel_ns();
1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1772 tsc_timestamp = tsc;
1776 local_irq_restore(flags);
1778 if (!vcpu->pv_time_enabled)
1781 if (kvm_has_tsc_control)
1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1786 &vcpu->hv_clock.tsc_shift,
1787 &vcpu->hv_clock.tsc_to_system_mul);
1788 vcpu->hw_tsc_khz = tgt_tsc_khz;
1791 /* With all the info we got, fill in the values */
1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1794 vcpu->last_guest_tsc = tsc_timestamp;
1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1819 sizeof(vcpu->hv_clock.version));
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1831 /* If the host uses TSC clocksource, then it is stable */
1832 if (use_master_clock)
1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1835 vcpu->hv_clock.flags = pvclock_flags;
1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1841 sizeof(vcpu->hv_clock));
1845 vcpu->hv_clock.version++;
1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 sizeof(vcpu->hv_clock.version));
1853 * kvmclock updates which are isolated to a given vcpu, such as
1854 * vcpu->cpu migration, should not allow system_timestamp from
1855 * the rest of the vcpus to remain static. Otherwise ntp frequency
1856 * correction applies to one vcpu's system_timestamp but not
1859 * So in those cases, request a kvmclock update for all vcpus.
1860 * We need to rate-limit these requests though, as they can
1861 * considerably slow guests that have a large number of vcpus.
1862 * The time for a remote vcpu to update its kvmclock is bound
1863 * by the delay we use to rate-limit the updates.
1866 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1868 static void kvmclock_update_fn(struct work_struct *work)
1871 struct delayed_work *dwork = to_delayed_work(work);
1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1873 kvmclock_update_work);
1874 struct kvm *kvm = container_of(ka, struct kvm, arch);
1875 struct kvm_vcpu *vcpu;
1877 kvm_for_each_vcpu(i, vcpu, kvm) {
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1879 kvm_vcpu_kick(vcpu);
1883 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1885 struct kvm *kvm = v->kvm;
1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1889 KVMCLOCK_UPDATE_DELAY);
1892 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1894 static void kvmclock_sync_fn(struct work_struct *work)
1896 struct delayed_work *dwork = to_delayed_work(work);
1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1898 kvmclock_sync_work);
1899 struct kvm *kvm = container_of(ka, struct kvm, arch);
1901 if (!kvmclock_periodic_sync)
1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1906 KVMCLOCK_SYNC_PERIOD);
1909 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1911 u64 mcg_cap = vcpu->arch.mcg_cap;
1912 unsigned bank_num = mcg_cap & 0xff;
1915 case MSR_IA32_MCG_STATUS:
1916 vcpu->arch.mcg_status = data;
1918 case MSR_IA32_MCG_CTL:
1919 if (!(mcg_cap & MCG_CTL_P))
1921 if (data != 0 && data != ~(u64)0)
1923 vcpu->arch.mcg_ctl = data;
1926 if (msr >= MSR_IA32_MC0_CTL &&
1927 msr < MSR_IA32_MCx_CTL(bank_num)) {
1928 u32 offset = msr - MSR_IA32_MC0_CTL;
1929 /* only 0 or all 1s can be written to IA32_MCi_CTL
1930 * some Linux kernels though clear bit 10 in bank 4 to
1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1932 * this to avoid an uncatched #GP in the guest
1934 if ((offset & 0x3) == 0 &&
1935 data != 0 && (data | (1 << 10)) != ~(u64)0)
1937 vcpu->arch.mce_banks[offset] = data;
1945 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1947 struct kvm *kvm = vcpu->kvm;
1948 int lm = is_long_mode(vcpu);
1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1952 : kvm->arch.xen_hvm_config.blob_size_32;
1953 u32 page_num = data & ~PAGE_MASK;
1954 u64 page_addr = data & PAGE_MASK;
1959 if (page_num >= blob_size)
1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1976 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1978 gpa_t gpa = data & ~0x3f;
1980 /* Bits 2:5 are reserved, Should be zero */
1984 vcpu->arch.apf.msr_val = data;
1986 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1987 kvm_clear_async_pf_completion_queue(vcpu);
1988 kvm_async_pf_hash_reset(vcpu);
1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1997 kvm_async_pf_wakeup_all(vcpu);
2001 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2003 vcpu->arch.pv_time_enabled = false;
2006 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2010 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2013 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2014 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2015 vcpu->arch.st.accum_steal = delta;
2018 static void record_steal_time(struct kvm_vcpu *vcpu)
2020 accumulate_steal_time(vcpu);
2022 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2025 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2026 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2029 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2030 vcpu->arch.st.steal.version += 2;
2031 vcpu->arch.st.accum_steal = 0;
2033 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2034 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2037 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2040 u32 msr = msr_info->index;
2041 u64 data = msr_info->data;
2044 case MSR_AMD64_NB_CFG:
2045 case MSR_IA32_UCODE_REV:
2046 case MSR_IA32_UCODE_WRITE:
2047 case MSR_VM_HSAVE_PA:
2048 case MSR_AMD64_PATCH_LOADER:
2049 case MSR_AMD64_BU_CFG2:
2053 return set_efer(vcpu, data);
2055 data &= ~(u64)0x40; /* ignore flush filter disable */
2056 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2057 data &= ~(u64)0x8; /* ignore TLB cache disable */
2058 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2060 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2065 case MSR_FAM10H_MMIO_CONF_BASE:
2067 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2072 case MSR_IA32_DEBUGCTLMSR:
2074 /* We support the non-activated case already */
2076 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2077 /* Values other than LBR and BTF are vendor-specific,
2078 thus reserved and should throw a #GP */
2081 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2084 case 0x200 ... 0x2ff:
2085 return kvm_mtrr_set_msr(vcpu, msr, data);
2086 case MSR_IA32_APICBASE:
2087 return kvm_set_apic_base(vcpu, msr_info);
2088 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2089 return kvm_x2apic_msr_write(vcpu, msr, data);
2090 case MSR_IA32_TSCDEADLINE:
2091 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2093 case MSR_IA32_TSC_ADJUST:
2094 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2095 if (!msr_info->host_initiated) {
2096 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2097 adjust_tsc_offset_guest(vcpu, adj);
2099 vcpu->arch.ia32_tsc_adjust_msr = data;
2102 case MSR_IA32_MISC_ENABLE:
2103 vcpu->arch.ia32_misc_enable_msr = data;
2105 case MSR_IA32_SMBASE:
2106 if (!msr_info->host_initiated)
2108 vcpu->arch.smbase = data;
2110 case MSR_KVM_WALL_CLOCK_NEW:
2111 case MSR_KVM_WALL_CLOCK:
2112 vcpu->kvm->arch.wall_clock = data;
2113 kvm_write_wall_clock(vcpu->kvm, data);
2115 case MSR_KVM_SYSTEM_TIME_NEW:
2116 case MSR_KVM_SYSTEM_TIME: {
2118 struct kvm_arch *ka = &vcpu->kvm->arch;
2120 kvmclock_reset(vcpu);
2122 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2123 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2125 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2126 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2129 ka->boot_vcpu_runs_old_kvmclock = tmp;
2132 vcpu->arch.time = data;
2133 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2135 /* we verify if the enable bit is set... */
2139 gpa_offset = data & ~(PAGE_MASK | 1);
2141 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2142 &vcpu->arch.pv_time, data & ~1ULL,
2143 sizeof(struct pvclock_vcpu_time_info)))
2144 vcpu->arch.pv_time_enabled = false;
2146 vcpu->arch.pv_time_enabled = true;
2150 case MSR_KVM_ASYNC_PF_EN:
2151 if (kvm_pv_enable_async_pf(vcpu, data))
2154 case MSR_KVM_STEAL_TIME:
2156 if (unlikely(!sched_info_on()))
2159 if (data & KVM_STEAL_RESERVED_MASK)
2162 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2163 data & KVM_STEAL_VALID_BITS,
2164 sizeof(struct kvm_steal_time)))
2167 vcpu->arch.st.msr_val = data;
2169 if (!(data & KVM_MSR_ENABLED))
2172 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2175 case MSR_KVM_PV_EOI_EN:
2176 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2180 case MSR_IA32_MCG_CTL:
2181 case MSR_IA32_MCG_STATUS:
2182 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2183 return set_msr_mce(vcpu, msr, data);
2185 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2186 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2187 pr = true; /* fall through */
2188 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2189 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2190 if (kvm_pmu_is_valid_msr(vcpu, msr))
2191 return kvm_pmu_set_msr(vcpu, msr_info);
2193 if (pr || data != 0)
2194 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2195 "0x%x data 0x%llx\n", msr, data);
2197 case MSR_K7_CLK_CTL:
2199 * Ignore all writes to this no longer documented MSR.
2200 * Writes are only relevant for old K7 processors,
2201 * all pre-dating SVM, but a recommended workaround from
2202 * AMD for these chips. It is possible to specify the
2203 * affected processor models on the command line, hence
2204 * the need to ignore the workaround.
2207 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2208 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2209 case HV_X64_MSR_CRASH_CTL:
2210 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2211 return kvm_hv_set_msr_common(vcpu, msr, data,
2212 msr_info->host_initiated);
2213 case MSR_IA32_BBL_CR_CTL3:
2214 /* Drop writes to this legacy MSR -- see rdmsr
2215 * counterpart for further detail.
2217 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2219 case MSR_AMD64_OSVW_ID_LENGTH:
2220 if (!guest_cpuid_has_osvw(vcpu))
2222 vcpu->arch.osvw.length = data;
2224 case MSR_AMD64_OSVW_STATUS:
2225 if (!guest_cpuid_has_osvw(vcpu))
2227 vcpu->arch.osvw.status = data;
2230 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2231 return xen_hvm_config(vcpu, data);
2232 if (kvm_pmu_is_valid_msr(vcpu, msr))
2233 return kvm_pmu_set_msr(vcpu, msr_info);
2235 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2239 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2246 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2250 * Reads an msr value (of 'msr_index') into 'pdata'.
2251 * Returns 0 on success, non-0 otherwise.
2252 * Assumes vcpu_load() was already called.
2254 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2256 return kvm_x86_ops->get_msr(vcpu, msr);
2258 EXPORT_SYMBOL_GPL(kvm_get_msr);
2260 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2263 u64 mcg_cap = vcpu->arch.mcg_cap;
2264 unsigned bank_num = mcg_cap & 0xff;
2267 case MSR_IA32_P5_MC_ADDR:
2268 case MSR_IA32_P5_MC_TYPE:
2271 case MSR_IA32_MCG_CAP:
2272 data = vcpu->arch.mcg_cap;
2274 case MSR_IA32_MCG_CTL:
2275 if (!(mcg_cap & MCG_CTL_P))
2277 data = vcpu->arch.mcg_ctl;
2279 case MSR_IA32_MCG_STATUS:
2280 data = vcpu->arch.mcg_status;
2283 if (msr >= MSR_IA32_MC0_CTL &&
2284 msr < MSR_IA32_MCx_CTL(bank_num)) {
2285 u32 offset = msr - MSR_IA32_MC0_CTL;
2286 data = vcpu->arch.mce_banks[offset];
2295 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2297 switch (msr_info->index) {
2298 case MSR_IA32_PLATFORM_ID:
2299 case MSR_IA32_EBL_CR_POWERON:
2300 case MSR_IA32_DEBUGCTLMSR:
2301 case MSR_IA32_LASTBRANCHFROMIP:
2302 case MSR_IA32_LASTBRANCHTOIP:
2303 case MSR_IA32_LASTINTFROMIP:
2304 case MSR_IA32_LASTINTTOIP:
2306 case MSR_K8_TSEG_ADDR:
2307 case MSR_K8_TSEG_MASK:
2309 case MSR_VM_HSAVE_PA:
2310 case MSR_K8_INT_PENDING_MSG:
2311 case MSR_AMD64_NB_CFG:
2312 case MSR_FAM10H_MMIO_CONF_BASE:
2313 case MSR_AMD64_BU_CFG2:
2316 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2317 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2318 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2319 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2320 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2321 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2324 case MSR_IA32_UCODE_REV:
2325 msr_info->data = 0x100000000ULL;
2328 case 0x200 ... 0x2ff:
2329 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2330 case 0xcd: /* fsb frequency */
2334 * MSR_EBC_FREQUENCY_ID
2335 * Conservative value valid for even the basic CPU models.
2336 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2337 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2338 * and 266MHz for model 3, or 4. Set Core Clock
2339 * Frequency to System Bus Frequency Ratio to 1 (bits
2340 * 31:24) even though these are only valid for CPU
2341 * models > 2, however guests may end up dividing or
2342 * multiplying by zero otherwise.
2344 case MSR_EBC_FREQUENCY_ID:
2345 msr_info->data = 1 << 24;
2347 case MSR_IA32_APICBASE:
2348 msr_info->data = kvm_get_apic_base(vcpu);
2350 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2351 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2353 case MSR_IA32_TSCDEADLINE:
2354 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2356 case MSR_IA32_TSC_ADJUST:
2357 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2359 case MSR_IA32_MISC_ENABLE:
2360 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2362 case MSR_IA32_SMBASE:
2363 if (!msr_info->host_initiated)
2365 msr_info->data = vcpu->arch.smbase;
2367 case MSR_IA32_PERF_STATUS:
2368 /* TSC increment by tick */
2369 msr_info->data = 1000ULL;
2370 /* CPU multiplier */
2371 msr_info->data |= (((uint64_t)4ULL) << 40);
2374 msr_info->data = vcpu->arch.efer;
2376 case MSR_KVM_WALL_CLOCK:
2377 case MSR_KVM_WALL_CLOCK_NEW:
2378 msr_info->data = vcpu->kvm->arch.wall_clock;
2380 case MSR_KVM_SYSTEM_TIME:
2381 case MSR_KVM_SYSTEM_TIME_NEW:
2382 msr_info->data = vcpu->arch.time;
2384 case MSR_KVM_ASYNC_PF_EN:
2385 msr_info->data = vcpu->arch.apf.msr_val;
2387 case MSR_KVM_STEAL_TIME:
2388 msr_info->data = vcpu->arch.st.msr_val;
2390 case MSR_KVM_PV_EOI_EN:
2391 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2393 case MSR_IA32_P5_MC_ADDR:
2394 case MSR_IA32_P5_MC_TYPE:
2395 case MSR_IA32_MCG_CAP:
2396 case MSR_IA32_MCG_CTL:
2397 case MSR_IA32_MCG_STATUS:
2398 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2399 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2400 case MSR_K7_CLK_CTL:
2402 * Provide expected ramp-up count for K7. All other
2403 * are set to zero, indicating minimum divisors for
2406 * This prevents guest kernels on AMD host with CPU
2407 * type 6, model 8 and higher from exploding due to
2408 * the rdmsr failing.
2410 msr_info->data = 0x20000000;
2412 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2413 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2414 case HV_X64_MSR_CRASH_CTL:
2415 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2416 return kvm_hv_get_msr_common(vcpu,
2417 msr_info->index, &msr_info->data);
2419 case MSR_IA32_BBL_CR_CTL3:
2420 /* This legacy MSR exists but isn't fully documented in current
2421 * silicon. It is however accessed by winxp in very narrow
2422 * scenarios where it sets bit #19, itself documented as
2423 * a "reserved" bit. Best effort attempt to source coherent
2424 * read data here should the balance of the register be
2425 * interpreted by the guest:
2427 * L2 cache control register 3: 64GB range, 256KB size,
2428 * enabled, latency 0x1, configured
2430 msr_info->data = 0xbe702111;
2432 case MSR_AMD64_OSVW_ID_LENGTH:
2433 if (!guest_cpuid_has_osvw(vcpu))
2435 msr_info->data = vcpu->arch.osvw.length;
2437 case MSR_AMD64_OSVW_STATUS:
2438 if (!guest_cpuid_has_osvw(vcpu))
2440 msr_info->data = vcpu->arch.osvw.status;
2443 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2444 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2446 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2449 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2456 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2459 * Read or write a bunch of msrs. All parameters are kernel addresses.
2461 * @return number of msrs set successfully.
2463 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2464 struct kvm_msr_entry *entries,
2465 int (*do_msr)(struct kvm_vcpu *vcpu,
2466 unsigned index, u64 *data))
2470 idx = srcu_read_lock(&vcpu->kvm->srcu);
2471 for (i = 0; i < msrs->nmsrs; ++i)
2472 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2474 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2480 * Read or write a bunch of msrs. Parameters are user addresses.
2482 * @return number of msrs set successfully.
2484 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2485 int (*do_msr)(struct kvm_vcpu *vcpu,
2486 unsigned index, u64 *data),
2489 struct kvm_msrs msrs;
2490 struct kvm_msr_entry *entries;
2495 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2499 if (msrs.nmsrs >= MAX_IO_MSRS)
2502 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2503 entries = memdup_user(user_msrs->entries, size);
2504 if (IS_ERR(entries)) {
2505 r = PTR_ERR(entries);
2509 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2514 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2525 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2530 case KVM_CAP_IRQCHIP:
2532 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2533 case KVM_CAP_SET_TSS_ADDR:
2534 case KVM_CAP_EXT_CPUID:
2535 case KVM_CAP_EXT_EMUL_CPUID:
2536 case KVM_CAP_CLOCKSOURCE:
2538 case KVM_CAP_NOP_IO_DELAY:
2539 case KVM_CAP_MP_STATE:
2540 case KVM_CAP_SYNC_MMU:
2541 case KVM_CAP_USER_NMI:
2542 case KVM_CAP_REINJECT_CONTROL:
2543 case KVM_CAP_IRQ_INJECT_STATUS:
2544 case KVM_CAP_IOEVENTFD:
2545 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2547 case KVM_CAP_PIT_STATE2:
2548 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2549 case KVM_CAP_XEN_HVM:
2550 case KVM_CAP_ADJUST_CLOCK:
2551 case KVM_CAP_VCPU_EVENTS:
2552 case KVM_CAP_HYPERV:
2553 case KVM_CAP_HYPERV_VAPIC:
2554 case KVM_CAP_HYPERV_SPIN:
2555 case KVM_CAP_HYPERV_SYNIC:
2556 case KVM_CAP_PCI_SEGMENT:
2557 case KVM_CAP_DEBUGREGS:
2558 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2560 case KVM_CAP_ASYNC_PF:
2561 case KVM_CAP_GET_TSC_KHZ:
2562 case KVM_CAP_KVMCLOCK_CTRL:
2563 case KVM_CAP_READONLY_MEM:
2564 case KVM_CAP_HYPERV_TIME:
2565 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2566 case KVM_CAP_TSC_DEADLINE_TIMER:
2567 case KVM_CAP_ENABLE_CAP_VM:
2568 case KVM_CAP_DISABLE_QUIRKS:
2569 case KVM_CAP_SET_BOOT_CPU_ID:
2570 case KVM_CAP_SPLIT_IRQCHIP:
2571 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2572 case KVM_CAP_ASSIGN_DEV_IRQ:
2573 case KVM_CAP_PCI_2_3:
2577 case KVM_CAP_X86_SMM:
2578 /* SMBASE is usually relocated above 1M on modern chipsets,
2579 * and SMM handlers might indeed rely on 4G segment limits,
2580 * so do not report SMM to be available if real mode is
2581 * emulated via vm86 mode. Still, do not go to great lengths
2582 * to avoid userspace's usage of the feature, because it is a
2583 * fringe case that is not enabled except via specific settings
2584 * of the module parameters.
2586 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2588 case KVM_CAP_COALESCED_MMIO:
2589 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2592 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2594 case KVM_CAP_NR_VCPUS:
2595 r = KVM_SOFT_MAX_VCPUS;
2597 case KVM_CAP_MAX_VCPUS:
2600 case KVM_CAP_NR_MEMSLOTS:
2601 r = KVM_USER_MEM_SLOTS;
2603 case KVM_CAP_PV_MMU: /* obsolete */
2606 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2608 r = iommu_present(&pci_bus_type);
2612 r = KVM_MAX_MCE_BANKS;
2617 case KVM_CAP_TSC_CONTROL:
2618 r = kvm_has_tsc_control;
2628 long kvm_arch_dev_ioctl(struct file *filp,
2629 unsigned int ioctl, unsigned long arg)
2631 void __user *argp = (void __user *)arg;
2635 case KVM_GET_MSR_INDEX_LIST: {
2636 struct kvm_msr_list __user *user_msr_list = argp;
2637 struct kvm_msr_list msr_list;
2641 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2644 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2645 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2648 if (n < msr_list.nmsrs)
2651 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2652 num_msrs_to_save * sizeof(u32)))
2654 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2656 num_emulated_msrs * sizeof(u32)))
2661 case KVM_GET_SUPPORTED_CPUID:
2662 case KVM_GET_EMULATED_CPUID: {
2663 struct kvm_cpuid2 __user *cpuid_arg = argp;
2664 struct kvm_cpuid2 cpuid;
2667 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2670 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2676 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2681 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2684 mce_cap = KVM_MCE_CAP_SUPPORTED;
2686 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2698 static void wbinvd_ipi(void *garbage)
2703 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2705 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2708 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2710 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2713 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2715 /* Address WBINVD may be executed by guest */
2716 if (need_emulate_wbinvd(vcpu)) {
2717 if (kvm_x86_ops->has_wbinvd_exit())
2718 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2719 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2720 smp_call_function_single(vcpu->cpu,
2721 wbinvd_ipi, NULL, 1);
2724 kvm_x86_ops->vcpu_load(vcpu, cpu);
2726 /* Apply any externally detected TSC adjustments (due to suspend) */
2727 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2728 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2729 vcpu->arch.tsc_offset_adjustment = 0;
2730 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2733 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2734 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2735 rdtsc() - vcpu->arch.last_host_tsc;
2737 mark_tsc_unstable("KVM discovered backwards TSC");
2738 if (check_tsc_unstable()) {
2739 u64 offset = kvm_compute_tsc_offset(vcpu,
2740 vcpu->arch.last_guest_tsc);
2741 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2742 vcpu->arch.tsc_catchup = 1;
2745 * On a host with synchronized TSC, there is no need to update
2746 * kvmclock on vcpu->cpu migration
2748 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2749 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2750 if (vcpu->cpu != cpu)
2751 kvm_migrate_timers(vcpu);
2755 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2758 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2760 kvm_x86_ops->vcpu_put(vcpu);
2761 kvm_put_guest_fpu(vcpu);
2762 vcpu->arch.last_host_tsc = rdtsc();
2765 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2766 struct kvm_lapic_state *s)
2768 if (vcpu->arch.apicv_active)
2769 kvm_x86_ops->sync_pir_to_irr(vcpu);
2771 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2776 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2779 kvm_apic_post_state_restore(vcpu, s);
2780 update_cr8_intercept(vcpu);
2785 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2787 return (!lapic_in_kernel(vcpu) ||
2788 kvm_apic_accept_pic_intr(vcpu));
2792 * if userspace requested an interrupt window, check that the
2793 * interrupt window is open.
2795 * No need to exit to userspace if we already have an interrupt queued.
2797 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2799 return kvm_arch_interrupt_allowed(vcpu) &&
2800 !kvm_cpu_has_interrupt(vcpu) &&
2801 !kvm_event_needs_reinjection(vcpu) &&
2802 kvm_cpu_accept_dm_intr(vcpu);
2805 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2806 struct kvm_interrupt *irq)
2808 if (irq->irq >= KVM_NR_INTERRUPTS)
2811 if (!irqchip_in_kernel(vcpu->kvm)) {
2812 kvm_queue_interrupt(vcpu, irq->irq, false);
2813 kvm_make_request(KVM_REQ_EVENT, vcpu);
2818 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2819 * fail for in-kernel 8259.
2821 if (pic_in_kernel(vcpu->kvm))
2824 if (vcpu->arch.pending_external_vector != -1)
2827 vcpu->arch.pending_external_vector = irq->irq;
2828 kvm_make_request(KVM_REQ_EVENT, vcpu);
2832 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2834 kvm_inject_nmi(vcpu);
2839 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2841 kvm_make_request(KVM_REQ_SMI, vcpu);
2846 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2847 struct kvm_tpr_access_ctl *tac)
2851 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2855 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2859 unsigned bank_num = mcg_cap & 0xff, bank;
2862 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2864 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2867 vcpu->arch.mcg_cap = mcg_cap;
2868 /* Init IA32_MCG_CTL to all 1s */
2869 if (mcg_cap & MCG_CTL_P)
2870 vcpu->arch.mcg_ctl = ~(u64)0;
2871 /* Init IA32_MCi_CTL to all 1s */
2872 for (bank = 0; bank < bank_num; bank++)
2873 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2878 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2879 struct kvm_x86_mce *mce)
2881 u64 mcg_cap = vcpu->arch.mcg_cap;
2882 unsigned bank_num = mcg_cap & 0xff;
2883 u64 *banks = vcpu->arch.mce_banks;
2885 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2888 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2889 * reporting is disabled
2891 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2892 vcpu->arch.mcg_ctl != ~(u64)0)
2894 banks += 4 * mce->bank;
2896 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2897 * reporting is disabled for the bank
2899 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2901 if (mce->status & MCI_STATUS_UC) {
2902 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2903 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2904 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2907 if (banks[1] & MCI_STATUS_VAL)
2908 mce->status |= MCI_STATUS_OVER;
2909 banks[2] = mce->addr;
2910 banks[3] = mce->misc;
2911 vcpu->arch.mcg_status = mce->mcg_status;
2912 banks[1] = mce->status;
2913 kvm_queue_exception(vcpu, MC_VECTOR);
2914 } else if (!(banks[1] & MCI_STATUS_VAL)
2915 || !(banks[1] & MCI_STATUS_UC)) {
2916 if (banks[1] & MCI_STATUS_VAL)
2917 mce->status |= MCI_STATUS_OVER;
2918 banks[2] = mce->addr;
2919 banks[3] = mce->misc;
2920 banks[1] = mce->status;
2922 banks[1] |= MCI_STATUS_OVER;
2926 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2927 struct kvm_vcpu_events *events)
2930 events->exception.injected =
2931 vcpu->arch.exception.pending &&
2932 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2933 events->exception.nr = vcpu->arch.exception.nr;
2934 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2935 events->exception.pad = 0;
2936 events->exception.error_code = vcpu->arch.exception.error_code;
2938 events->interrupt.injected =
2939 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2940 events->interrupt.nr = vcpu->arch.interrupt.nr;
2941 events->interrupt.soft = 0;
2942 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2944 events->nmi.injected = vcpu->arch.nmi_injected;
2945 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2946 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2947 events->nmi.pad = 0;
2949 events->sipi_vector = 0; /* never valid when reporting to user space */
2951 events->smi.smm = is_smm(vcpu);
2952 events->smi.pending = vcpu->arch.smi_pending;
2953 events->smi.smm_inside_nmi =
2954 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2955 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2957 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2958 | KVM_VCPUEVENT_VALID_SHADOW
2959 | KVM_VCPUEVENT_VALID_SMM);
2960 memset(&events->reserved, 0, sizeof(events->reserved));
2963 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2964 struct kvm_vcpu_events *events)
2966 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2967 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2968 | KVM_VCPUEVENT_VALID_SHADOW
2969 | KVM_VCPUEVENT_VALID_SMM))
2973 vcpu->arch.exception.pending = events->exception.injected;
2974 vcpu->arch.exception.nr = events->exception.nr;
2975 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2976 vcpu->arch.exception.error_code = events->exception.error_code;
2978 vcpu->arch.interrupt.pending = events->interrupt.injected;
2979 vcpu->arch.interrupt.nr = events->interrupt.nr;
2980 vcpu->arch.interrupt.soft = events->interrupt.soft;
2981 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2982 kvm_x86_ops->set_interrupt_shadow(vcpu,
2983 events->interrupt.shadow);
2985 vcpu->arch.nmi_injected = events->nmi.injected;
2986 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2987 vcpu->arch.nmi_pending = events->nmi.pending;
2988 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2990 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2991 lapic_in_kernel(vcpu))
2992 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2994 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2995 if (events->smi.smm)
2996 vcpu->arch.hflags |= HF_SMM_MASK;
2998 vcpu->arch.hflags &= ~HF_SMM_MASK;
2999 vcpu->arch.smi_pending = events->smi.pending;
3000 if (events->smi.smm_inside_nmi)
3001 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3003 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3004 if (lapic_in_kernel(vcpu)) {
3005 if (events->smi.latched_init)
3006 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3008 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3012 kvm_make_request(KVM_REQ_EVENT, vcpu);
3017 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3018 struct kvm_debugregs *dbgregs)
3022 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3023 kvm_get_dr(vcpu, 6, &val);
3025 dbgregs->dr7 = vcpu->arch.dr7;
3027 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3030 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3031 struct kvm_debugregs *dbgregs)
3036 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3037 kvm_update_dr0123(vcpu);
3038 vcpu->arch.dr6 = dbgregs->dr6;
3039 kvm_update_dr6(vcpu);
3040 vcpu->arch.dr7 = dbgregs->dr7;
3041 kvm_update_dr7(vcpu);
3046 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3048 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3050 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3051 u64 xstate_bv = xsave->header.xfeatures;
3055 * Copy legacy XSAVE area, to avoid complications with CPUID
3056 * leaves 0 and 1 in the loop below.
3058 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3061 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3064 * Copy each region from the possibly compacted offset to the
3065 * non-compacted offset.
3067 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3069 u64 feature = valid & -valid;
3070 int index = fls64(feature) - 1;
3071 void *src = get_xsave_addr(xsave, feature);
3074 u32 size, offset, ecx, edx;
3075 cpuid_count(XSTATE_CPUID, index,
3076 &size, &offset, &ecx, &edx);
3077 memcpy(dest + offset, src, size);
3084 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3086 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3087 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3091 * Copy legacy XSAVE area, to avoid complications with CPUID
3092 * leaves 0 and 1 in the loop below.
3094 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3096 /* Set XSTATE_BV and possibly XCOMP_BV. */
3097 xsave->header.xfeatures = xstate_bv;
3099 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3102 * Copy each region from the non-compacted offset to the
3103 * possibly compacted offset.
3105 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3107 u64 feature = valid & -valid;
3108 int index = fls64(feature) - 1;
3109 void *dest = get_xsave_addr(xsave, feature);
3112 u32 size, offset, ecx, edx;
3113 cpuid_count(XSTATE_CPUID, index,
3114 &size, &offset, &ecx, &edx);
3115 memcpy(dest, src + offset, size);
3122 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3123 struct kvm_xsave *guest_xsave)
3125 if (cpu_has_xsave) {
3126 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3127 fill_xsave((u8 *) guest_xsave->region, vcpu);
3129 memcpy(guest_xsave->region,
3130 &vcpu->arch.guest_fpu.state.fxsave,
3131 sizeof(struct fxregs_state));
3132 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3133 XFEATURE_MASK_FPSSE;
3137 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3138 struct kvm_xsave *guest_xsave)
3141 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3143 if (cpu_has_xsave) {
3145 * Here we allow setting states that are not present in
3146 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3147 * with old userspace.
3149 if (xstate_bv & ~kvm_supported_xcr0())
3151 load_xsave(vcpu, (u8 *)guest_xsave->region);
3153 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3155 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3156 guest_xsave->region, sizeof(struct fxregs_state));
3161 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3162 struct kvm_xcrs *guest_xcrs)
3164 if (!cpu_has_xsave) {
3165 guest_xcrs->nr_xcrs = 0;
3169 guest_xcrs->nr_xcrs = 1;
3170 guest_xcrs->flags = 0;
3171 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3172 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3175 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3176 struct kvm_xcrs *guest_xcrs)
3183 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3186 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3187 /* Only support XCR0 currently */
3188 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3189 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3190 guest_xcrs->xcrs[i].value);
3199 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3200 * stopped by the hypervisor. This function will be called from the host only.
3201 * EINVAL is returned when the host attempts to set the flag for a guest that
3202 * does not support pv clocks.
3204 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3206 if (!vcpu->arch.pv_time_enabled)
3208 vcpu->arch.pvclock_set_guest_stopped_request = true;
3209 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3213 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3214 struct kvm_enable_cap *cap)
3220 case KVM_CAP_HYPERV_SYNIC:
3221 return kvm_hv_activate_synic(vcpu);
3227 long kvm_arch_vcpu_ioctl(struct file *filp,
3228 unsigned int ioctl, unsigned long arg)
3230 struct kvm_vcpu *vcpu = filp->private_data;
3231 void __user *argp = (void __user *)arg;
3234 struct kvm_lapic_state *lapic;
3235 struct kvm_xsave *xsave;
3236 struct kvm_xcrs *xcrs;
3242 case KVM_GET_LAPIC: {
3244 if (!lapic_in_kernel(vcpu))
3246 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3251 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3255 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3260 case KVM_SET_LAPIC: {
3262 if (!lapic_in_kernel(vcpu))
3264 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3265 if (IS_ERR(u.lapic))
3266 return PTR_ERR(u.lapic);
3268 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3271 case KVM_INTERRUPT: {
3272 struct kvm_interrupt irq;
3275 if (copy_from_user(&irq, argp, sizeof irq))
3277 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3281 r = kvm_vcpu_ioctl_nmi(vcpu);
3285 r = kvm_vcpu_ioctl_smi(vcpu);
3288 case KVM_SET_CPUID: {
3289 struct kvm_cpuid __user *cpuid_arg = argp;
3290 struct kvm_cpuid cpuid;
3293 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3295 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3298 case KVM_SET_CPUID2: {
3299 struct kvm_cpuid2 __user *cpuid_arg = argp;
3300 struct kvm_cpuid2 cpuid;
3303 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3305 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3306 cpuid_arg->entries);
3309 case KVM_GET_CPUID2: {
3310 struct kvm_cpuid2 __user *cpuid_arg = argp;
3311 struct kvm_cpuid2 cpuid;
3314 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3316 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3317 cpuid_arg->entries);
3321 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3327 r = msr_io(vcpu, argp, do_get_msr, 1);
3330 r = msr_io(vcpu, argp, do_set_msr, 0);
3332 case KVM_TPR_ACCESS_REPORTING: {
3333 struct kvm_tpr_access_ctl tac;
3336 if (copy_from_user(&tac, argp, sizeof tac))
3338 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3342 if (copy_to_user(argp, &tac, sizeof tac))
3347 case KVM_SET_VAPIC_ADDR: {
3348 struct kvm_vapic_addr va;
3351 if (!lapic_in_kernel(vcpu))
3354 if (copy_from_user(&va, argp, sizeof va))
3356 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3359 case KVM_X86_SETUP_MCE: {
3363 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3365 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3368 case KVM_X86_SET_MCE: {
3369 struct kvm_x86_mce mce;
3372 if (copy_from_user(&mce, argp, sizeof mce))
3374 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3377 case KVM_GET_VCPU_EVENTS: {
3378 struct kvm_vcpu_events events;
3380 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3383 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3388 case KVM_SET_VCPU_EVENTS: {
3389 struct kvm_vcpu_events events;
3392 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3395 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3398 case KVM_GET_DEBUGREGS: {
3399 struct kvm_debugregs dbgregs;
3401 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3404 if (copy_to_user(argp, &dbgregs,
3405 sizeof(struct kvm_debugregs)))
3410 case KVM_SET_DEBUGREGS: {
3411 struct kvm_debugregs dbgregs;
3414 if (copy_from_user(&dbgregs, argp,
3415 sizeof(struct kvm_debugregs)))
3418 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3421 case KVM_GET_XSAVE: {
3422 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3427 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3430 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3435 case KVM_SET_XSAVE: {
3436 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3437 if (IS_ERR(u.xsave))
3438 return PTR_ERR(u.xsave);
3440 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3443 case KVM_GET_XCRS: {
3444 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3449 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3452 if (copy_to_user(argp, u.xcrs,
3453 sizeof(struct kvm_xcrs)))
3458 case KVM_SET_XCRS: {
3459 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3461 return PTR_ERR(u.xcrs);
3463 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3466 case KVM_SET_TSC_KHZ: {
3470 user_tsc_khz = (u32)arg;
3472 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3475 if (user_tsc_khz == 0)
3476 user_tsc_khz = tsc_khz;
3478 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3483 case KVM_GET_TSC_KHZ: {
3484 r = vcpu->arch.virtual_tsc_khz;
3487 case KVM_KVMCLOCK_CTRL: {
3488 r = kvm_set_guest_paused(vcpu);
3491 case KVM_ENABLE_CAP: {
3492 struct kvm_enable_cap cap;
3495 if (copy_from_user(&cap, argp, sizeof(cap)))
3497 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3508 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3510 return VM_FAULT_SIGBUS;
3513 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3517 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3519 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3523 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3526 kvm->arch.ept_identity_map_addr = ident_addr;
3530 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3531 u32 kvm_nr_mmu_pages)
3533 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3536 mutex_lock(&kvm->slots_lock);
3538 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3539 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3541 mutex_unlock(&kvm->slots_lock);
3545 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3547 return kvm->arch.n_max_mmu_pages;
3550 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3555 switch (chip->chip_id) {
3556 case KVM_IRQCHIP_PIC_MASTER:
3557 memcpy(&chip->chip.pic,
3558 &pic_irqchip(kvm)->pics[0],
3559 sizeof(struct kvm_pic_state));
3561 case KVM_IRQCHIP_PIC_SLAVE:
3562 memcpy(&chip->chip.pic,
3563 &pic_irqchip(kvm)->pics[1],
3564 sizeof(struct kvm_pic_state));
3566 case KVM_IRQCHIP_IOAPIC:
3567 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3576 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3581 switch (chip->chip_id) {
3582 case KVM_IRQCHIP_PIC_MASTER:
3583 spin_lock(&pic_irqchip(kvm)->lock);
3584 memcpy(&pic_irqchip(kvm)->pics[0],
3586 sizeof(struct kvm_pic_state));
3587 spin_unlock(&pic_irqchip(kvm)->lock);
3589 case KVM_IRQCHIP_PIC_SLAVE:
3590 spin_lock(&pic_irqchip(kvm)->lock);
3591 memcpy(&pic_irqchip(kvm)->pics[1],
3593 sizeof(struct kvm_pic_state));
3594 spin_unlock(&pic_irqchip(kvm)->lock);
3596 case KVM_IRQCHIP_IOAPIC:
3597 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3603 kvm_pic_update_irq(pic_irqchip(kvm));
3607 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3609 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3611 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3613 mutex_lock(&kps->lock);
3614 memcpy(ps, &kps->channels, sizeof(*ps));
3615 mutex_unlock(&kps->lock);
3619 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3622 struct kvm_pit *pit = kvm->arch.vpit;
3624 mutex_lock(&pit->pit_state.lock);
3625 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3626 for (i = 0; i < 3; i++)
3627 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3628 mutex_unlock(&pit->pit_state.lock);
3632 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3634 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3635 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3636 sizeof(ps->channels));
3637 ps->flags = kvm->arch.vpit->pit_state.flags;
3638 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3639 memset(&ps->reserved, 0, sizeof(ps->reserved));
3643 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3647 u32 prev_legacy, cur_legacy;
3648 struct kvm_pit *pit = kvm->arch.vpit;
3650 mutex_lock(&pit->pit_state.lock);
3651 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3652 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3653 if (!prev_legacy && cur_legacy)
3655 memcpy(&pit->pit_state.channels, &ps->channels,
3656 sizeof(pit->pit_state.channels));
3657 pit->pit_state.flags = ps->flags;
3658 for (i = 0; i < 3; i++)
3659 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3661 mutex_unlock(&pit->pit_state.lock);
3665 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3666 struct kvm_reinject_control *control)
3668 struct kvm_pit *pit = kvm->arch.vpit;
3673 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3674 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3675 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3677 mutex_lock(&pit->pit_state.lock);
3678 kvm_pit_set_reinject(pit, control->pit_reinject);
3679 mutex_unlock(&pit->pit_state.lock);
3685 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3686 * @kvm: kvm instance
3687 * @log: slot id and address to which we copy the log
3689 * Steps 1-4 below provide general overview of dirty page logging. See
3690 * kvm_get_dirty_log_protect() function description for additional details.
3692 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3693 * always flush the TLB (step 4) even if previous step failed and the dirty
3694 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3695 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3696 * writes will be marked dirty for next log read.
3698 * 1. Take a snapshot of the bit and clear it if needed.
3699 * 2. Write protect the corresponding page.
3700 * 3. Copy the snapshot to the userspace.
3701 * 4. Flush TLB's if needed.
3703 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3705 bool is_dirty = false;
3708 mutex_lock(&kvm->slots_lock);
3711 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3713 if (kvm_x86_ops->flush_log_dirty)
3714 kvm_x86_ops->flush_log_dirty(kvm);
3716 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3719 * All the TLBs can be flushed out of mmu lock, see the comments in
3720 * kvm_mmu_slot_remove_write_access().
3722 lockdep_assert_held(&kvm->slots_lock);
3724 kvm_flush_remote_tlbs(kvm);
3726 mutex_unlock(&kvm->slots_lock);
3730 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3733 if (!irqchip_in_kernel(kvm))
3736 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3737 irq_event->irq, irq_event->level,
3742 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3743 struct kvm_enable_cap *cap)
3751 case KVM_CAP_DISABLE_QUIRKS:
3752 kvm->arch.disabled_quirks = cap->args[0];
3755 case KVM_CAP_SPLIT_IRQCHIP: {
3756 mutex_lock(&kvm->lock);
3758 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3759 goto split_irqchip_unlock;
3761 if (irqchip_in_kernel(kvm))
3762 goto split_irqchip_unlock;
3763 if (atomic_read(&kvm->online_vcpus))
3764 goto split_irqchip_unlock;
3765 r = kvm_setup_empty_irq_routing(kvm);
3767 goto split_irqchip_unlock;
3768 /* Pairs with irqchip_in_kernel. */
3770 kvm->arch.irqchip_split = true;
3771 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3773 split_irqchip_unlock:
3774 mutex_unlock(&kvm->lock);
3784 long kvm_arch_vm_ioctl(struct file *filp,
3785 unsigned int ioctl, unsigned long arg)
3787 struct kvm *kvm = filp->private_data;
3788 void __user *argp = (void __user *)arg;
3791 * This union makes it completely explicit to gcc-3.x
3792 * that these two variables' stack usage should be
3793 * combined, not added together.
3796 struct kvm_pit_state ps;
3797 struct kvm_pit_state2 ps2;
3798 struct kvm_pit_config pit_config;
3802 case KVM_SET_TSS_ADDR:
3803 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3805 case KVM_SET_IDENTITY_MAP_ADDR: {
3809 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3811 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3814 case KVM_SET_NR_MMU_PAGES:
3815 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3817 case KVM_GET_NR_MMU_PAGES:
3818 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3820 case KVM_CREATE_IRQCHIP: {
3821 struct kvm_pic *vpic;
3823 mutex_lock(&kvm->lock);
3826 goto create_irqchip_unlock;
3828 if (atomic_read(&kvm->online_vcpus))
3829 goto create_irqchip_unlock;
3831 vpic = kvm_create_pic(kvm);
3833 r = kvm_ioapic_init(kvm);
3835 mutex_lock(&kvm->slots_lock);
3836 kvm_destroy_pic(vpic);
3837 mutex_unlock(&kvm->slots_lock);
3838 goto create_irqchip_unlock;
3841 goto create_irqchip_unlock;
3842 r = kvm_setup_default_irq_routing(kvm);
3844 mutex_lock(&kvm->slots_lock);
3845 mutex_lock(&kvm->irq_lock);
3846 kvm_ioapic_destroy(kvm);
3847 kvm_destroy_pic(vpic);
3848 mutex_unlock(&kvm->irq_lock);
3849 mutex_unlock(&kvm->slots_lock);
3850 goto create_irqchip_unlock;
3852 /* Write kvm->irq_routing before kvm->arch.vpic. */
3854 kvm->arch.vpic = vpic;
3855 create_irqchip_unlock:
3856 mutex_unlock(&kvm->lock);
3859 case KVM_CREATE_PIT:
3860 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3862 case KVM_CREATE_PIT2:
3864 if (copy_from_user(&u.pit_config, argp,
3865 sizeof(struct kvm_pit_config)))
3868 mutex_lock(&kvm->slots_lock);
3871 goto create_pit_unlock;
3873 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3877 mutex_unlock(&kvm->slots_lock);
3879 case KVM_GET_IRQCHIP: {
3880 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3881 struct kvm_irqchip *chip;
3883 chip = memdup_user(argp, sizeof(*chip));
3890 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3891 goto get_irqchip_out;
3892 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3894 goto get_irqchip_out;
3896 if (copy_to_user(argp, chip, sizeof *chip))
3897 goto get_irqchip_out;
3903 case KVM_SET_IRQCHIP: {
3904 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3905 struct kvm_irqchip *chip;
3907 chip = memdup_user(argp, sizeof(*chip));
3914 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3915 goto set_irqchip_out;
3916 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3918 goto set_irqchip_out;
3926 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3929 if (!kvm->arch.vpit)
3931 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3935 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3942 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3945 if (!kvm->arch.vpit)
3947 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3950 case KVM_GET_PIT2: {
3952 if (!kvm->arch.vpit)
3954 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3958 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3963 case KVM_SET_PIT2: {
3965 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3968 if (!kvm->arch.vpit)
3970 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3973 case KVM_REINJECT_CONTROL: {
3974 struct kvm_reinject_control control;
3976 if (copy_from_user(&control, argp, sizeof(control)))
3978 r = kvm_vm_ioctl_reinject(kvm, &control);
3981 case KVM_SET_BOOT_CPU_ID:
3983 mutex_lock(&kvm->lock);
3984 if (atomic_read(&kvm->online_vcpus) != 0)
3987 kvm->arch.bsp_vcpu_id = arg;
3988 mutex_unlock(&kvm->lock);
3990 case KVM_XEN_HVM_CONFIG: {
3992 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3993 sizeof(struct kvm_xen_hvm_config)))
3996 if (kvm->arch.xen_hvm_config.flags)
4001 case KVM_SET_CLOCK: {
4002 struct kvm_clock_data user_ns;
4007 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4015 local_irq_disable();
4016 now_ns = get_kernel_ns();
4017 delta = user_ns.clock - now_ns;
4019 kvm->arch.kvmclock_offset = delta;
4020 kvm_gen_update_masterclock(kvm);
4023 case KVM_GET_CLOCK: {
4024 struct kvm_clock_data user_ns;
4027 local_irq_disable();
4028 now_ns = get_kernel_ns();
4029 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4032 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4035 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4040 case KVM_ENABLE_CAP: {
4041 struct kvm_enable_cap cap;
4044 if (copy_from_user(&cap, argp, sizeof(cap)))
4046 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4050 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4056 static void kvm_init_msr_list(void)
4061 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4062 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4066 * Even MSRs that are valid in the host may not be exposed
4067 * to the guests in some cases.
4069 switch (msrs_to_save[i]) {
4070 case MSR_IA32_BNDCFGS:
4071 if (!kvm_x86_ops->mpx_supported())
4075 if (!kvm_x86_ops->rdtscp_supported())
4083 msrs_to_save[j] = msrs_to_save[i];
4086 num_msrs_to_save = j;
4088 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4089 switch (emulated_msrs[i]) {
4090 case MSR_IA32_SMBASE:
4091 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4099 emulated_msrs[j] = emulated_msrs[i];
4102 num_emulated_msrs = j;
4105 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4113 if (!(lapic_in_kernel(vcpu) &&
4114 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4115 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4126 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4133 if (!(lapic_in_kernel(vcpu) &&
4134 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4136 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4138 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4148 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4149 struct kvm_segment *var, int seg)
4151 kvm_x86_ops->set_segment(vcpu, var, seg);
4154 void kvm_get_segment(struct kvm_vcpu *vcpu,
4155 struct kvm_segment *var, int seg)
4157 kvm_x86_ops->get_segment(vcpu, var, seg);
4160 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4161 struct x86_exception *exception)
4165 BUG_ON(!mmu_is_nested(vcpu));
4167 /* NPT walks are always user-walks */
4168 access |= PFERR_USER_MASK;
4169 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4174 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4175 struct x86_exception *exception)
4177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4178 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4181 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4182 struct x86_exception *exception)
4184 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4185 access |= PFERR_FETCH_MASK;
4186 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4189 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4190 struct x86_exception *exception)
4192 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4193 access |= PFERR_WRITE_MASK;
4194 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4197 /* uses this to access any guest's mapped memory without checking CPL */
4198 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4199 struct x86_exception *exception)
4201 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4204 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4205 struct kvm_vcpu *vcpu, u32 access,
4206 struct x86_exception *exception)
4209 int r = X86EMUL_CONTINUE;
4212 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4214 unsigned offset = addr & (PAGE_SIZE-1);
4215 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4218 if (gpa == UNMAPPED_GVA)
4219 return X86EMUL_PROPAGATE_FAULT;
4220 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4223 r = X86EMUL_IO_NEEDED;
4235 /* used for instruction fetching */
4236 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4237 gva_t addr, void *val, unsigned int bytes,
4238 struct x86_exception *exception)
4240 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4241 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4245 /* Inline kvm_read_guest_virt_helper for speed. */
4246 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4248 if (unlikely(gpa == UNMAPPED_GVA))
4249 return X86EMUL_PROPAGATE_FAULT;
4251 offset = addr & (PAGE_SIZE-1);
4252 if (WARN_ON(offset + bytes > PAGE_SIZE))
4253 bytes = (unsigned)PAGE_SIZE - offset;
4254 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4256 if (unlikely(ret < 0))
4257 return X86EMUL_IO_NEEDED;
4259 return X86EMUL_CONTINUE;
4262 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4263 gva_t addr, void *val, unsigned int bytes,
4264 struct x86_exception *exception)
4266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4267 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4269 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4272 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4274 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4275 gva_t addr, void *val, unsigned int bytes,
4276 struct x86_exception *exception)
4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4279 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4282 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4283 unsigned long addr, void *val, unsigned int bytes)
4285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4286 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4288 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4291 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4292 gva_t addr, void *val,
4294 struct x86_exception *exception)
4296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4298 int r = X86EMUL_CONTINUE;
4301 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4304 unsigned offset = addr & (PAGE_SIZE-1);
4305 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4308 if (gpa == UNMAPPED_GVA)
4309 return X86EMUL_PROPAGATE_FAULT;
4310 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4312 r = X86EMUL_IO_NEEDED;
4323 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4325 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4326 gpa_t *gpa, struct x86_exception *exception,
4329 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4330 | (write ? PFERR_WRITE_MASK : 0);
4333 * currently PKRU is only applied to ept enabled guest so
4334 * there is no pkey in EPT page table for L1 guest or EPT
4335 * shadow page table for L2 guest.
4337 if (vcpu_match_mmio_gva(vcpu, gva)
4338 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4339 vcpu->arch.access, 0, access)) {
4340 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4341 (gva & (PAGE_SIZE - 1));
4342 trace_vcpu_match_mmio(gva, *gpa, write, false);
4346 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4348 if (*gpa == UNMAPPED_GVA)
4351 /* For APIC access vmexit */
4352 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4355 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4356 trace_vcpu_match_mmio(gva, *gpa, write, true);
4363 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4364 const void *val, int bytes)
4368 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4371 kvm_page_track_write(vcpu, gpa, val, bytes);
4375 struct read_write_emulator_ops {
4376 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4378 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4379 void *val, int bytes);
4380 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 int bytes, void *val);
4382 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 void *val, int bytes);
4387 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4389 if (vcpu->mmio_read_completed) {
4390 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4391 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4392 vcpu->mmio_read_completed = 0;
4399 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4400 void *val, int bytes)
4402 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4405 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4406 void *val, int bytes)
4408 return emulator_write_phys(vcpu, gpa, val, bytes);
4411 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4413 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4414 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4417 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4418 void *val, int bytes)
4420 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4421 return X86EMUL_IO_NEEDED;
4424 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4425 void *val, int bytes)
4427 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4429 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4430 return X86EMUL_CONTINUE;
4433 static const struct read_write_emulator_ops read_emultor = {
4434 .read_write_prepare = read_prepare,
4435 .read_write_emulate = read_emulate,
4436 .read_write_mmio = vcpu_mmio_read,
4437 .read_write_exit_mmio = read_exit_mmio,
4440 static const struct read_write_emulator_ops write_emultor = {
4441 .read_write_emulate = write_emulate,
4442 .read_write_mmio = write_mmio,
4443 .read_write_exit_mmio = write_exit_mmio,
4447 static int emulator_read_write_onepage(unsigned long addr, void *val,
4449 struct x86_exception *exception,
4450 struct kvm_vcpu *vcpu,
4451 const struct read_write_emulator_ops *ops)
4455 bool write = ops->write;
4456 struct kvm_mmio_fragment *frag;
4458 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4461 return X86EMUL_PROPAGATE_FAULT;
4463 /* For APIC access vmexit */
4467 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4468 return X86EMUL_CONTINUE;
4472 * Is this MMIO handled locally?
4474 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4475 if (handled == bytes)
4476 return X86EMUL_CONTINUE;
4482 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4483 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4487 return X86EMUL_CONTINUE;
4490 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4492 void *val, unsigned int bytes,
4493 struct x86_exception *exception,
4494 const struct read_write_emulator_ops *ops)
4496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4500 if (ops->read_write_prepare &&
4501 ops->read_write_prepare(vcpu, val, bytes))
4502 return X86EMUL_CONTINUE;
4504 vcpu->mmio_nr_fragments = 0;
4506 /* Crossing a page boundary? */
4507 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4510 now = -addr & ~PAGE_MASK;
4511 rc = emulator_read_write_onepage(addr, val, now, exception,
4514 if (rc != X86EMUL_CONTINUE)
4517 if (ctxt->mode != X86EMUL_MODE_PROT64)
4523 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4525 if (rc != X86EMUL_CONTINUE)
4528 if (!vcpu->mmio_nr_fragments)
4531 gpa = vcpu->mmio_fragments[0].gpa;
4533 vcpu->mmio_needed = 1;
4534 vcpu->mmio_cur_fragment = 0;
4536 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4537 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4538 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4539 vcpu->run->mmio.phys_addr = gpa;
4541 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4544 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4548 struct x86_exception *exception)
4550 return emulator_read_write(ctxt, addr, val, bytes,
4551 exception, &read_emultor);
4554 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4558 struct x86_exception *exception)
4560 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4561 exception, &write_emultor);
4564 #define CMPXCHG_TYPE(t, ptr, old, new) \
4565 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4567 #ifdef CONFIG_X86_64
4568 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4570 # define CMPXCHG64(ptr, old, new) \
4571 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4574 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4579 struct x86_exception *exception)
4581 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4587 /* guests cmpxchg8b have to be emulated atomically */
4588 if (bytes > 8 || (bytes & (bytes - 1)))
4591 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4593 if (gpa == UNMAPPED_GVA ||
4594 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4597 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4600 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4601 if (is_error_page(page))
4604 kaddr = kmap_atomic(page);
4605 kaddr += offset_in_page(gpa);
4608 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4611 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4614 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4617 exchanged = CMPXCHG64(kaddr, old, new);
4622 kunmap_atomic(kaddr);
4623 kvm_release_page_dirty(page);
4626 return X86EMUL_CMPXCHG_FAILED;
4628 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4629 kvm_page_track_write(vcpu, gpa, new, bytes);
4631 return X86EMUL_CONTINUE;
4634 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4636 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4639 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4641 /* TODO: String I/O for in kernel device */
4644 if (vcpu->arch.pio.in)
4645 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4646 vcpu->arch.pio.size, pd);
4648 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4649 vcpu->arch.pio.port, vcpu->arch.pio.size,
4654 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4655 unsigned short port, void *val,
4656 unsigned int count, bool in)
4658 vcpu->arch.pio.port = port;
4659 vcpu->arch.pio.in = in;
4660 vcpu->arch.pio.count = count;
4661 vcpu->arch.pio.size = size;
4663 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4664 vcpu->arch.pio.count = 0;
4668 vcpu->run->exit_reason = KVM_EXIT_IO;
4669 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4670 vcpu->run->io.size = size;
4671 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4672 vcpu->run->io.count = count;
4673 vcpu->run->io.port = port;
4678 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4679 int size, unsigned short port, void *val,
4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4685 if (vcpu->arch.pio.count)
4688 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4691 memcpy(val, vcpu->arch.pio_data, size * count);
4692 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4693 vcpu->arch.pio.count = 0;
4700 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4701 int size, unsigned short port,
4702 const void *val, unsigned int count)
4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4706 memcpy(vcpu->arch.pio_data, val, size * count);
4707 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4708 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4711 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4713 return kvm_x86_ops->get_segment_base(vcpu, seg);
4716 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4718 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4721 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4723 if (!need_emulate_wbinvd(vcpu))
4724 return X86EMUL_CONTINUE;
4726 if (kvm_x86_ops->has_wbinvd_exit()) {
4727 int cpu = get_cpu();
4729 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4730 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4731 wbinvd_ipi, NULL, 1);
4733 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4736 return X86EMUL_CONTINUE;
4739 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4741 kvm_x86_ops->skip_emulated_instruction(vcpu);
4742 return kvm_emulate_wbinvd_noskip(vcpu);
4744 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4748 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4750 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4753 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4754 unsigned long *dest)
4756 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4759 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4760 unsigned long value)
4763 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4766 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4768 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4771 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4773 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4774 unsigned long value;
4778 value = kvm_read_cr0(vcpu);
4781 value = vcpu->arch.cr2;
4784 value = kvm_read_cr3(vcpu);
4787 value = kvm_read_cr4(vcpu);
4790 value = kvm_get_cr8(vcpu);
4793 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4800 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4807 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4810 vcpu->arch.cr2 = val;
4813 res = kvm_set_cr3(vcpu, val);
4816 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4819 res = kvm_set_cr8(vcpu, val);
4822 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4829 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4831 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4834 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4836 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4839 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4841 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4844 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4846 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4849 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4851 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4854 static unsigned long emulator_get_cached_segment_base(
4855 struct x86_emulate_ctxt *ctxt, int seg)
4857 return get_segment_base(emul_to_vcpu(ctxt), seg);
4860 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4861 struct desc_struct *desc, u32 *base3,
4864 struct kvm_segment var;
4866 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4867 *selector = var.selector;
4870 memset(desc, 0, sizeof(*desc));
4876 set_desc_limit(desc, var.limit);
4877 set_desc_base(desc, (unsigned long)var.base);
4878 #ifdef CONFIG_X86_64
4880 *base3 = var.base >> 32;
4882 desc->type = var.type;
4884 desc->dpl = var.dpl;
4885 desc->p = var.present;
4886 desc->avl = var.avl;
4894 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4895 struct desc_struct *desc, u32 base3,
4898 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4899 struct kvm_segment var;
4901 var.selector = selector;
4902 var.base = get_desc_base(desc);
4903 #ifdef CONFIG_X86_64
4904 var.base |= ((u64)base3) << 32;
4906 var.limit = get_desc_limit(desc);
4908 var.limit = (var.limit << 12) | 0xfff;
4909 var.type = desc->type;
4910 var.dpl = desc->dpl;
4915 var.avl = desc->avl;
4916 var.present = desc->p;
4917 var.unusable = !var.present;
4920 kvm_set_segment(vcpu, &var, seg);
4924 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4925 u32 msr_index, u64 *pdata)
4927 struct msr_data msr;
4930 msr.index = msr_index;
4931 msr.host_initiated = false;
4932 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4940 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4941 u32 msr_index, u64 data)
4943 struct msr_data msr;
4946 msr.index = msr_index;
4947 msr.host_initiated = false;
4948 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4951 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4955 return vcpu->arch.smbase;
4958 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4962 vcpu->arch.smbase = smbase;
4965 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4968 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4971 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4972 u32 pmc, u64 *pdata)
4974 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4977 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4979 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4982 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4985 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4987 * CR0.TS may reference the host fpu state, not the guest fpu state,
4988 * so it may be clear at this point.
4993 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4998 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4999 struct x86_instruction_info *info,
5000 enum x86_intercept_stage stage)
5002 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5005 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5006 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5008 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5011 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5013 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5016 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5018 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5021 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5023 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5026 static const struct x86_emulate_ops emulate_ops = {
5027 .read_gpr = emulator_read_gpr,
5028 .write_gpr = emulator_write_gpr,
5029 .read_std = kvm_read_guest_virt_system,
5030 .write_std = kvm_write_guest_virt_system,
5031 .read_phys = kvm_read_guest_phys_system,
5032 .fetch = kvm_fetch_guest_virt,
5033 .read_emulated = emulator_read_emulated,
5034 .write_emulated = emulator_write_emulated,
5035 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5036 .invlpg = emulator_invlpg,
5037 .pio_in_emulated = emulator_pio_in_emulated,
5038 .pio_out_emulated = emulator_pio_out_emulated,
5039 .get_segment = emulator_get_segment,
5040 .set_segment = emulator_set_segment,
5041 .get_cached_segment_base = emulator_get_cached_segment_base,
5042 .get_gdt = emulator_get_gdt,
5043 .get_idt = emulator_get_idt,
5044 .set_gdt = emulator_set_gdt,
5045 .set_idt = emulator_set_idt,
5046 .get_cr = emulator_get_cr,
5047 .set_cr = emulator_set_cr,
5048 .cpl = emulator_get_cpl,
5049 .get_dr = emulator_get_dr,
5050 .set_dr = emulator_set_dr,
5051 .get_smbase = emulator_get_smbase,
5052 .set_smbase = emulator_set_smbase,
5053 .set_msr = emulator_set_msr,
5054 .get_msr = emulator_get_msr,
5055 .check_pmc = emulator_check_pmc,
5056 .read_pmc = emulator_read_pmc,
5057 .halt = emulator_halt,
5058 .wbinvd = emulator_wbinvd,
5059 .fix_hypercall = emulator_fix_hypercall,
5060 .get_fpu = emulator_get_fpu,
5061 .put_fpu = emulator_put_fpu,
5062 .intercept = emulator_intercept,
5063 .get_cpuid = emulator_get_cpuid,
5064 .set_nmi_mask = emulator_set_nmi_mask,
5067 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5069 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5071 * an sti; sti; sequence only disable interrupts for the first
5072 * instruction. So, if the last instruction, be it emulated or
5073 * not, left the system with the INT_STI flag enabled, it
5074 * means that the last instruction is an sti. We should not
5075 * leave the flag on in this case. The same goes for mov ss
5077 if (int_shadow & mask)
5079 if (unlikely(int_shadow || mask)) {
5080 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5082 kvm_make_request(KVM_REQ_EVENT, vcpu);
5086 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5088 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5089 if (ctxt->exception.vector == PF_VECTOR)
5090 return kvm_propagate_fault(vcpu, &ctxt->exception);
5092 if (ctxt->exception.error_code_valid)
5093 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5094 ctxt->exception.error_code);
5096 kvm_queue_exception(vcpu, ctxt->exception.vector);
5100 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5102 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5105 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5107 ctxt->eflags = kvm_get_rflags(vcpu);
5108 ctxt->eip = kvm_rip_read(vcpu);
5109 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5110 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5111 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5112 cs_db ? X86EMUL_MODE_PROT32 :
5113 X86EMUL_MODE_PROT16;
5114 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5115 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5116 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5117 ctxt->emul_flags = vcpu->arch.hflags;
5119 init_decode_cache(ctxt);
5120 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5123 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5125 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5128 init_emulate_ctxt(vcpu);
5132 ctxt->_eip = ctxt->eip + inc_eip;
5133 ret = emulate_int_real(ctxt, irq);
5135 if (ret != X86EMUL_CONTINUE)
5136 return EMULATE_FAIL;
5138 ctxt->eip = ctxt->_eip;
5139 kvm_rip_write(vcpu, ctxt->eip);
5140 kvm_set_rflags(vcpu, ctxt->eflags);
5142 if (irq == NMI_VECTOR)
5143 vcpu->arch.nmi_pending = 0;
5145 vcpu->arch.interrupt.pending = false;
5147 return EMULATE_DONE;
5149 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5151 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5153 int r = EMULATE_DONE;
5155 ++vcpu->stat.insn_emulation_fail;
5156 trace_kvm_emulate_insn_failed(vcpu);
5157 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5158 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5159 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5160 vcpu->run->internal.ndata = 0;
5163 kvm_queue_exception(vcpu, UD_VECTOR);
5168 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5169 bool write_fault_to_shadow_pgtable,
5175 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5178 if (!vcpu->arch.mmu.direct_map) {
5180 * Write permission should be allowed since only
5181 * write access need to be emulated.
5183 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5186 * If the mapping is invalid in guest, let cpu retry
5187 * it to generate fault.
5189 if (gpa == UNMAPPED_GVA)
5194 * Do not retry the unhandleable instruction if it faults on the
5195 * readonly host memory, otherwise it will goto a infinite loop:
5196 * retry instruction -> write #PF -> emulation fail -> retry
5197 * instruction -> ...
5199 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5202 * If the instruction failed on the error pfn, it can not be fixed,
5203 * report the error to userspace.
5205 if (is_error_noslot_pfn(pfn))
5208 kvm_release_pfn_clean(pfn);
5210 /* The instructions are well-emulated on direct mmu. */
5211 if (vcpu->arch.mmu.direct_map) {
5212 unsigned int indirect_shadow_pages;
5214 spin_lock(&vcpu->kvm->mmu_lock);
5215 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5216 spin_unlock(&vcpu->kvm->mmu_lock);
5218 if (indirect_shadow_pages)
5219 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5225 * if emulation was due to access to shadowed page table
5226 * and it failed try to unshadow page and re-enter the
5227 * guest to let CPU execute the instruction.
5229 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5232 * If the access faults on its page table, it can not
5233 * be fixed by unprotecting shadow page and it should
5234 * be reported to userspace.
5236 return !write_fault_to_shadow_pgtable;
5239 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5240 unsigned long cr2, int emulation_type)
5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5243 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5245 last_retry_eip = vcpu->arch.last_retry_eip;
5246 last_retry_addr = vcpu->arch.last_retry_addr;
5249 * If the emulation is caused by #PF and it is non-page_table
5250 * writing instruction, it means the VM-EXIT is caused by shadow
5251 * page protected, we can zap the shadow page and retry this
5252 * instruction directly.
5254 * Note: if the guest uses a non-page-table modifying instruction
5255 * on the PDE that points to the instruction, then we will unmap
5256 * the instruction and go to an infinite loop. So, we cache the
5257 * last retried eip and the last fault address, if we meet the eip
5258 * and the address again, we can break out of the potential infinite
5261 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5263 if (!(emulation_type & EMULTYPE_RETRY))
5266 if (x86_page_table_writing_insn(ctxt))
5269 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5272 vcpu->arch.last_retry_eip = ctxt->eip;
5273 vcpu->arch.last_retry_addr = cr2;
5275 if (!vcpu->arch.mmu.direct_map)
5276 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5278 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5283 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5284 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5286 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5288 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5289 /* This is a good place to trace that we are exiting SMM. */
5290 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5292 if (unlikely(vcpu->arch.smi_pending)) {
5293 kvm_make_request(KVM_REQ_SMI, vcpu);
5294 vcpu->arch.smi_pending = 0;
5296 /* Process a latched INIT, if any. */
5297 kvm_make_request(KVM_REQ_EVENT, vcpu);
5301 kvm_mmu_reset_context(vcpu);
5304 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5306 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5308 vcpu->arch.hflags = emul_flags;
5310 if (changed & HF_SMM_MASK)
5311 kvm_smm_changed(vcpu);
5314 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5323 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5324 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5329 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5331 struct kvm_run *kvm_run = vcpu->run;
5334 * rflags is the old, "raw" value of the flags. The new value has
5335 * not been saved yet.
5337 * This is correct even for TF set by the guest, because "the
5338 * processor will not generate this exception after the instruction
5339 * that sets the TF flag".
5341 if (unlikely(rflags & X86_EFLAGS_TF)) {
5342 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5343 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5345 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5346 kvm_run->debug.arch.exception = DB_VECTOR;
5347 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5348 *r = EMULATE_USER_EXIT;
5350 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5352 * "Certain debug exceptions may clear bit 0-3. The
5353 * remaining contents of the DR6 register are never
5354 * cleared by the processor".
5356 vcpu->arch.dr6 &= ~15;
5357 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5358 kvm_queue_exception(vcpu, DB_VECTOR);
5363 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5365 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5366 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5367 struct kvm_run *kvm_run = vcpu->run;
5368 unsigned long eip = kvm_get_linear_rip(vcpu);
5369 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5370 vcpu->arch.guest_debug_dr7,
5374 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5375 kvm_run->debug.arch.pc = eip;
5376 kvm_run->debug.arch.exception = DB_VECTOR;
5377 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5378 *r = EMULATE_USER_EXIT;
5383 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5384 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5385 unsigned long eip = kvm_get_linear_rip(vcpu);
5386 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5391 vcpu->arch.dr6 &= ~15;
5392 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5393 kvm_queue_exception(vcpu, DB_VECTOR);
5402 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5409 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5410 bool writeback = true;
5411 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5414 * Clear write_fault_to_shadow_pgtable here to ensure it is
5417 vcpu->arch.write_fault_to_shadow_pgtable = false;
5418 kvm_clear_exception_queue(vcpu);
5420 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5421 init_emulate_ctxt(vcpu);
5424 * We will reenter on the same instruction since
5425 * we do not set complete_userspace_io. This does not
5426 * handle watchpoints yet, those would be handled in
5429 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5432 ctxt->interruptibility = 0;
5433 ctxt->have_exception = false;
5434 ctxt->exception.vector = -1;
5435 ctxt->perm_ok = false;
5437 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5439 r = x86_decode_insn(ctxt, insn, insn_len);
5441 trace_kvm_emulate_insn_start(vcpu);
5442 ++vcpu->stat.insn_emulation;
5443 if (r != EMULATION_OK) {
5444 if (emulation_type & EMULTYPE_TRAP_UD)
5445 return EMULATE_FAIL;
5446 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5448 return EMULATE_DONE;
5449 if (emulation_type & EMULTYPE_SKIP)
5450 return EMULATE_FAIL;
5451 return handle_emulation_failure(vcpu);
5455 if (emulation_type & EMULTYPE_SKIP) {
5456 kvm_rip_write(vcpu, ctxt->_eip);
5457 if (ctxt->eflags & X86_EFLAGS_RF)
5458 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5459 return EMULATE_DONE;
5462 if (retry_instruction(ctxt, cr2, emulation_type))
5463 return EMULATE_DONE;
5465 /* this is needed for vmware backdoor interface to work since it
5466 changes registers values during IO operation */
5467 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5468 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5469 emulator_invalidate_register_cache(ctxt);
5473 r = x86_emulate_insn(ctxt);
5475 if (r == EMULATION_INTERCEPTED)
5476 return EMULATE_DONE;
5478 if (r == EMULATION_FAILED) {
5479 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5481 return EMULATE_DONE;
5483 return handle_emulation_failure(vcpu);
5486 if (ctxt->have_exception) {
5488 if (inject_emulated_exception(vcpu))
5490 } else if (vcpu->arch.pio.count) {
5491 if (!vcpu->arch.pio.in) {
5492 /* FIXME: return into emulator if single-stepping. */
5493 vcpu->arch.pio.count = 0;
5496 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5498 r = EMULATE_USER_EXIT;
5499 } else if (vcpu->mmio_needed) {
5500 if (!vcpu->mmio_is_write)
5502 r = EMULATE_USER_EXIT;
5503 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5504 } else if (r == EMULATION_RESTART)
5510 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5511 toggle_interruptibility(vcpu, ctxt->interruptibility);
5512 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5513 if (vcpu->arch.hflags != ctxt->emul_flags)
5514 kvm_set_hflags(vcpu, ctxt->emul_flags);
5515 kvm_rip_write(vcpu, ctxt->eip);
5516 if (r == EMULATE_DONE)
5517 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5518 if (!ctxt->have_exception ||
5519 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5520 __kvm_set_rflags(vcpu, ctxt->eflags);
5523 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5524 * do nothing, and it will be requested again as soon as
5525 * the shadow expires. But we still need to check here,
5526 * because POPF has no interrupt shadow.
5528 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5529 kvm_make_request(KVM_REQ_EVENT, vcpu);
5531 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5535 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5537 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5539 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5540 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5541 size, port, &val, 1);
5542 /* do not return to emulator after return from userspace */
5543 vcpu->arch.pio.count = 0;
5546 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5548 static void tsc_bad(void *info)
5550 __this_cpu_write(cpu_tsc_khz, 0);
5553 static void tsc_khz_changed(void *data)
5555 struct cpufreq_freqs *freq = data;
5556 unsigned long khz = 0;
5560 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5561 khz = cpufreq_quick_get(raw_smp_processor_id());
5564 __this_cpu_write(cpu_tsc_khz, khz);
5567 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5570 struct cpufreq_freqs *freq = data;
5572 struct kvm_vcpu *vcpu;
5573 int i, send_ipi = 0;
5576 * We allow guests to temporarily run on slowing clocks,
5577 * provided we notify them after, or to run on accelerating
5578 * clocks, provided we notify them before. Thus time never
5581 * However, we have a problem. We can't atomically update
5582 * the frequency of a given CPU from this function; it is
5583 * merely a notifier, which can be called from any CPU.
5584 * Changing the TSC frequency at arbitrary points in time
5585 * requires a recomputation of local variables related to
5586 * the TSC for each VCPU. We must flag these local variables
5587 * to be updated and be sure the update takes place with the
5588 * new frequency before any guests proceed.
5590 * Unfortunately, the combination of hotplug CPU and frequency
5591 * change creates an intractable locking scenario; the order
5592 * of when these callouts happen is undefined with respect to
5593 * CPU hotplug, and they can race with each other. As such,
5594 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5595 * undefined; you can actually have a CPU frequency change take
5596 * place in between the computation of X and the setting of the
5597 * variable. To protect against this problem, all updates of
5598 * the per_cpu tsc_khz variable are done in an interrupt
5599 * protected IPI, and all callers wishing to update the value
5600 * must wait for a synchronous IPI to complete (which is trivial
5601 * if the caller is on the CPU already). This establishes the
5602 * necessary total order on variable updates.
5604 * Note that because a guest time update may take place
5605 * anytime after the setting of the VCPU's request bit, the
5606 * correct TSC value must be set before the request. However,
5607 * to ensure the update actually makes it to any guest which
5608 * starts running in hardware virtualization between the set
5609 * and the acquisition of the spinlock, we must also ping the
5610 * CPU after setting the request bit.
5614 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5616 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5619 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5621 spin_lock(&kvm_lock);
5622 list_for_each_entry(kvm, &vm_list, vm_list) {
5623 kvm_for_each_vcpu(i, vcpu, kvm) {
5624 if (vcpu->cpu != freq->cpu)
5626 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5627 if (vcpu->cpu != smp_processor_id())
5631 spin_unlock(&kvm_lock);
5633 if (freq->old < freq->new && send_ipi) {
5635 * We upscale the frequency. Must make the guest
5636 * doesn't see old kvmclock values while running with
5637 * the new frequency, otherwise we risk the guest sees
5638 * time go backwards.
5640 * In case we update the frequency for another cpu
5641 * (which might be in guest context) send an interrupt
5642 * to kick the cpu out of guest context. Next time
5643 * guest context is entered kvmclock will be updated,
5644 * so the guest will not see stale values.
5646 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5651 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5652 .notifier_call = kvmclock_cpufreq_notifier
5655 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5656 unsigned long action, void *hcpu)
5658 unsigned int cpu = (unsigned long)hcpu;
5662 case CPU_DOWN_FAILED:
5663 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5665 case CPU_DOWN_PREPARE:
5666 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5672 static struct notifier_block kvmclock_cpu_notifier_block = {
5673 .notifier_call = kvmclock_cpu_notifier,
5674 .priority = -INT_MAX
5677 static void kvm_timer_init(void)
5681 max_tsc_khz = tsc_khz;
5683 cpu_notifier_register_begin();
5684 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5685 #ifdef CONFIG_CPU_FREQ
5686 struct cpufreq_policy policy;
5687 memset(&policy, 0, sizeof(policy));
5689 cpufreq_get_policy(&policy, cpu);
5690 if (policy.cpuinfo.max_freq)
5691 max_tsc_khz = policy.cpuinfo.max_freq;
5694 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5695 CPUFREQ_TRANSITION_NOTIFIER);
5697 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5698 for_each_online_cpu(cpu)
5699 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5701 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5702 cpu_notifier_register_done();
5706 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5708 int kvm_is_in_guest(void)
5710 return __this_cpu_read(current_vcpu) != NULL;
5713 static int kvm_is_user_mode(void)
5717 if (__this_cpu_read(current_vcpu))
5718 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5720 return user_mode != 0;
5723 static unsigned long kvm_get_guest_ip(void)
5725 unsigned long ip = 0;
5727 if (__this_cpu_read(current_vcpu))
5728 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5733 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5734 .is_in_guest = kvm_is_in_guest,
5735 .is_user_mode = kvm_is_user_mode,
5736 .get_guest_ip = kvm_get_guest_ip,
5739 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5741 __this_cpu_write(current_vcpu, vcpu);
5743 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5745 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5747 __this_cpu_write(current_vcpu, NULL);
5749 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5751 static void kvm_set_mmio_spte_mask(void)
5754 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5757 * Set the reserved bits and the present bit of an paging-structure
5758 * entry to generate page fault with PFER.RSV = 1.
5760 /* Mask the reserved physical address bits. */
5761 mask = rsvd_bits(maxphyaddr, 51);
5763 /* Bit 62 is always reserved for 32bit host. */
5764 mask |= 0x3ull << 62;
5766 /* Set the present bit. */
5769 #ifdef CONFIG_X86_64
5771 * If reserved bit is not supported, clear the present bit to disable
5774 if (maxphyaddr == 52)
5778 kvm_mmu_set_mmio_spte_mask(mask);
5781 #ifdef CONFIG_X86_64
5782 static void pvclock_gtod_update_fn(struct work_struct *work)
5786 struct kvm_vcpu *vcpu;
5789 spin_lock(&kvm_lock);
5790 list_for_each_entry(kvm, &vm_list, vm_list)
5791 kvm_for_each_vcpu(i, vcpu, kvm)
5792 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5793 atomic_set(&kvm_guest_has_master_clock, 0);
5794 spin_unlock(&kvm_lock);
5797 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5800 * Notification about pvclock gtod data update.
5802 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5805 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5806 struct timekeeper *tk = priv;
5808 update_pvclock_gtod(tk);
5810 /* disable master clock if host does not trust, or does not
5811 * use, TSC clocksource
5813 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5814 atomic_read(&kvm_guest_has_master_clock) != 0)
5815 queue_work(system_long_wq, &pvclock_gtod_work);
5820 static struct notifier_block pvclock_gtod_notifier = {
5821 .notifier_call = pvclock_gtod_notify,
5825 int kvm_arch_init(void *opaque)
5828 struct kvm_x86_ops *ops = opaque;
5831 printk(KERN_ERR "kvm: already loaded the other module\n");
5836 if (!ops->cpu_has_kvm_support()) {
5837 printk(KERN_ERR "kvm: no hardware support\n");
5841 if (ops->disabled_by_bios()) {
5842 printk(KERN_ERR "kvm: disabled by bios\n");
5848 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5850 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5854 r = kvm_mmu_module_init();
5856 goto out_free_percpu;
5858 kvm_set_mmio_spte_mask();
5862 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5863 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5867 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5870 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5873 #ifdef CONFIG_X86_64
5874 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5880 free_percpu(shared_msrs);
5885 void kvm_arch_exit(void)
5887 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5889 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5890 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5891 CPUFREQ_TRANSITION_NOTIFIER);
5892 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5893 #ifdef CONFIG_X86_64
5894 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5897 kvm_mmu_module_exit();
5898 free_percpu(shared_msrs);
5901 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5903 ++vcpu->stat.halt_exits;
5904 if (lapic_in_kernel(vcpu)) {
5905 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5908 vcpu->run->exit_reason = KVM_EXIT_HLT;
5912 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5914 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5916 kvm_x86_ops->skip_emulated_instruction(vcpu);
5917 return kvm_vcpu_halt(vcpu);
5919 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5922 * kvm_pv_kick_cpu_op: Kick a vcpu.
5924 * @apicid - apicid of vcpu to be kicked.
5926 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5928 struct kvm_lapic_irq lapic_irq;
5930 lapic_irq.shorthand = 0;
5931 lapic_irq.dest_mode = 0;
5932 lapic_irq.dest_id = apicid;
5933 lapic_irq.msi_redir_hint = false;
5935 lapic_irq.delivery_mode = APIC_DM_REMRD;
5936 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5939 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5941 vcpu->arch.apicv_active = false;
5942 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5945 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5947 unsigned long nr, a0, a1, a2, a3, ret;
5948 int op_64_bit, r = 1;
5950 kvm_x86_ops->skip_emulated_instruction(vcpu);
5952 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5953 return kvm_hv_hypercall(vcpu);
5955 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5956 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5957 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5958 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5959 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5961 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5963 op_64_bit = is_64_bit_mode(vcpu);
5972 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5978 case KVM_HC_VAPIC_POLL_IRQ:
5981 case KVM_HC_KICK_CPU:
5982 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5992 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5993 ++vcpu->stat.hypercalls;
5996 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5998 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6001 char instruction[3];
6002 unsigned long rip = kvm_rip_read(vcpu);
6004 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6006 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6009 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6011 return vcpu->run->request_interrupt_window &&
6012 likely(!pic_in_kernel(vcpu->kvm));
6015 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6017 struct kvm_run *kvm_run = vcpu->run;
6019 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6020 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6021 kvm_run->cr8 = kvm_get_cr8(vcpu);
6022 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6023 kvm_run->ready_for_interrupt_injection =
6024 pic_in_kernel(vcpu->kvm) ||
6025 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6028 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6032 if (!kvm_x86_ops->update_cr8_intercept)
6035 if (!lapic_in_kernel(vcpu))
6038 if (vcpu->arch.apicv_active)
6041 if (!vcpu->arch.apic->vapic_addr)
6042 max_irr = kvm_lapic_find_highest_irr(vcpu);
6049 tpr = kvm_lapic_get_cr8(vcpu);
6051 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6054 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6058 /* try to reinject previous events if any */
6059 if (vcpu->arch.exception.pending) {
6060 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6061 vcpu->arch.exception.has_error_code,
6062 vcpu->arch.exception.error_code);
6064 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6065 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6068 if (vcpu->arch.exception.nr == DB_VECTOR &&
6069 (vcpu->arch.dr7 & DR7_GD)) {
6070 vcpu->arch.dr7 &= ~DR7_GD;
6071 kvm_update_dr7(vcpu);
6074 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6075 vcpu->arch.exception.has_error_code,
6076 vcpu->arch.exception.error_code,
6077 vcpu->arch.exception.reinject);
6081 if (vcpu->arch.nmi_injected) {
6082 kvm_x86_ops->set_nmi(vcpu);
6086 if (vcpu->arch.interrupt.pending) {
6087 kvm_x86_ops->set_irq(vcpu);
6091 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6092 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6097 /* try to inject new event if pending */
6098 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6099 --vcpu->arch.nmi_pending;
6100 vcpu->arch.nmi_injected = true;
6101 kvm_x86_ops->set_nmi(vcpu);
6102 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6104 * Because interrupts can be injected asynchronously, we are
6105 * calling check_nested_events again here to avoid a race condition.
6106 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6107 * proposal and current concerns. Perhaps we should be setting
6108 * KVM_REQ_EVENT only on certain events and not unconditionally?
6110 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6111 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6115 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6116 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6118 kvm_x86_ops->set_irq(vcpu);
6124 static void process_nmi(struct kvm_vcpu *vcpu)
6129 * x86 is limited to one NMI running, and one NMI pending after it.
6130 * If an NMI is already in progress, limit further NMIs to just one.
6131 * Otherwise, allow two (and we'll inject the first one immediately).
6133 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6136 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6137 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6138 kvm_make_request(KVM_REQ_EVENT, vcpu);
6141 #define put_smstate(type, buf, offset, val) \
6142 *(type *)((buf) + (offset) - 0x7e00) = val
6144 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6147 flags |= seg->g << 23;
6148 flags |= seg->db << 22;
6149 flags |= seg->l << 21;
6150 flags |= seg->avl << 20;
6151 flags |= seg->present << 15;
6152 flags |= seg->dpl << 13;
6153 flags |= seg->s << 12;
6154 flags |= seg->type << 8;
6158 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6160 struct kvm_segment seg;
6163 kvm_get_segment(vcpu, &seg, n);
6164 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6167 offset = 0x7f84 + n * 12;
6169 offset = 0x7f2c + (n - 3) * 12;
6171 put_smstate(u32, buf, offset + 8, seg.base);
6172 put_smstate(u32, buf, offset + 4, seg.limit);
6173 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6176 #ifdef CONFIG_X86_64
6177 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6179 struct kvm_segment seg;
6183 kvm_get_segment(vcpu, &seg, n);
6184 offset = 0x7e00 + n * 16;
6186 flags = process_smi_get_segment_flags(&seg) >> 8;
6187 put_smstate(u16, buf, offset, seg.selector);
6188 put_smstate(u16, buf, offset + 2, flags);
6189 put_smstate(u32, buf, offset + 4, seg.limit);
6190 put_smstate(u64, buf, offset + 8, seg.base);
6194 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6197 struct kvm_segment seg;
6201 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6202 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6203 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6204 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6206 for (i = 0; i < 8; i++)
6207 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6209 kvm_get_dr(vcpu, 6, &val);
6210 put_smstate(u32, buf, 0x7fcc, (u32)val);
6211 kvm_get_dr(vcpu, 7, &val);
6212 put_smstate(u32, buf, 0x7fc8, (u32)val);
6214 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6215 put_smstate(u32, buf, 0x7fc4, seg.selector);
6216 put_smstate(u32, buf, 0x7f64, seg.base);
6217 put_smstate(u32, buf, 0x7f60, seg.limit);
6218 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6220 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6221 put_smstate(u32, buf, 0x7fc0, seg.selector);
6222 put_smstate(u32, buf, 0x7f80, seg.base);
6223 put_smstate(u32, buf, 0x7f7c, seg.limit);
6224 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6226 kvm_x86_ops->get_gdt(vcpu, &dt);
6227 put_smstate(u32, buf, 0x7f74, dt.address);
6228 put_smstate(u32, buf, 0x7f70, dt.size);
6230 kvm_x86_ops->get_idt(vcpu, &dt);
6231 put_smstate(u32, buf, 0x7f58, dt.address);
6232 put_smstate(u32, buf, 0x7f54, dt.size);
6234 for (i = 0; i < 6; i++)
6235 process_smi_save_seg_32(vcpu, buf, i);
6237 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6240 put_smstate(u32, buf, 0x7efc, 0x00020000);
6241 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6244 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6246 #ifdef CONFIG_X86_64
6248 struct kvm_segment seg;
6252 for (i = 0; i < 16; i++)
6253 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6255 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6256 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6258 kvm_get_dr(vcpu, 6, &val);
6259 put_smstate(u64, buf, 0x7f68, val);
6260 kvm_get_dr(vcpu, 7, &val);
6261 put_smstate(u64, buf, 0x7f60, val);
6263 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6264 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6265 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6267 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6270 put_smstate(u32, buf, 0x7efc, 0x00020064);
6272 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6274 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6275 put_smstate(u16, buf, 0x7e90, seg.selector);
6276 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6277 put_smstate(u32, buf, 0x7e94, seg.limit);
6278 put_smstate(u64, buf, 0x7e98, seg.base);
6280 kvm_x86_ops->get_idt(vcpu, &dt);
6281 put_smstate(u32, buf, 0x7e84, dt.size);
6282 put_smstate(u64, buf, 0x7e88, dt.address);
6284 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6285 put_smstate(u16, buf, 0x7e70, seg.selector);
6286 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6287 put_smstate(u32, buf, 0x7e74, seg.limit);
6288 put_smstate(u64, buf, 0x7e78, seg.base);
6290 kvm_x86_ops->get_gdt(vcpu, &dt);
6291 put_smstate(u32, buf, 0x7e64, dt.size);
6292 put_smstate(u64, buf, 0x7e68, dt.address);
6294 for (i = 0; i < 6; i++)
6295 process_smi_save_seg_64(vcpu, buf, i);
6301 static void process_smi(struct kvm_vcpu *vcpu)
6303 struct kvm_segment cs, ds;
6309 vcpu->arch.smi_pending = true;
6313 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6314 vcpu->arch.hflags |= HF_SMM_MASK;
6315 memset(buf, 0, 512);
6316 if (guest_cpuid_has_longmode(vcpu))
6317 process_smi_save_state_64(vcpu, buf);
6319 process_smi_save_state_32(vcpu, buf);
6321 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6323 if (kvm_x86_ops->get_nmi_mask(vcpu))
6324 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6326 kvm_x86_ops->set_nmi_mask(vcpu, true);
6328 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6329 kvm_rip_write(vcpu, 0x8000);
6331 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6332 kvm_x86_ops->set_cr0(vcpu, cr0);
6333 vcpu->arch.cr0 = cr0;
6335 kvm_x86_ops->set_cr4(vcpu, 0);
6337 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6338 dt.address = dt.size = 0;
6339 kvm_x86_ops->set_idt(vcpu, &dt);
6341 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6343 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6344 cs.base = vcpu->arch.smbase;
6349 cs.limit = ds.limit = 0xffffffff;
6350 cs.type = ds.type = 0x3;
6351 cs.dpl = ds.dpl = 0;
6356 cs.avl = ds.avl = 0;
6357 cs.present = ds.present = 1;
6358 cs.unusable = ds.unusable = 0;
6359 cs.padding = ds.padding = 0;
6361 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6362 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6363 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6364 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6368 if (guest_cpuid_has_longmode(vcpu))
6369 kvm_x86_ops->set_efer(vcpu, 0);
6371 kvm_update_cpuid(vcpu);
6372 kvm_mmu_reset_context(vcpu);
6375 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6377 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6380 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6382 u64 eoi_exit_bitmap[4];
6384 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6387 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6389 if (irqchip_split(vcpu->kvm))
6390 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6392 if (vcpu->arch.apicv_active)
6393 kvm_x86_ops->sync_pir_to_irr(vcpu);
6394 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6396 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6397 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6398 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6401 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6403 ++vcpu->stat.tlb_flush;
6404 kvm_x86_ops->tlb_flush(vcpu);
6407 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6409 struct page *page = NULL;
6411 if (!lapic_in_kernel(vcpu))
6414 if (!kvm_x86_ops->set_apic_access_page_addr)
6417 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6418 if (is_error_page(page))
6420 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6423 * Do not pin apic access page in memory, the MMU notifier
6424 * will call us again if it is migrated or swapped out.
6428 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6430 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6431 unsigned long address)
6434 * The physical address of apic access page is stored in the VMCS.
6435 * Update it when it becomes invalid.
6437 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6438 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6442 * Returns 1 to let vcpu_run() continue the guest execution loop without
6443 * exiting to the userspace. Otherwise, the value will be returned to the
6446 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6450 dm_request_for_irq_injection(vcpu) &&
6451 kvm_cpu_accept_dm_intr(vcpu);
6453 bool req_immediate_exit = false;
6455 if (vcpu->requests) {
6456 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6457 kvm_mmu_unload(vcpu);
6458 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6459 __kvm_migrate_timers(vcpu);
6460 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6461 kvm_gen_update_masterclock(vcpu->kvm);
6462 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6463 kvm_gen_kvmclock_update(vcpu);
6464 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6465 r = kvm_guest_time_update(vcpu);
6469 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6470 kvm_mmu_sync_roots(vcpu);
6471 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6472 kvm_vcpu_flush_tlb(vcpu);
6473 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6474 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6478 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6479 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6483 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6484 vcpu->fpu_active = 0;
6485 kvm_x86_ops->fpu_deactivate(vcpu);
6487 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6488 /* Page is swapped out. Do synthetic halt */
6489 vcpu->arch.apf.halted = true;
6493 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6494 record_steal_time(vcpu);
6495 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6497 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6499 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6500 kvm_pmu_handle_event(vcpu);
6501 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6502 kvm_pmu_deliver_pmi(vcpu);
6503 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6504 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6505 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6506 vcpu->arch.ioapic_handled_vectors)) {
6507 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6508 vcpu->run->eoi.vector =
6509 vcpu->arch.pending_ioapic_eoi;
6514 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6515 vcpu_scan_ioapic(vcpu);
6516 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6517 kvm_vcpu_reload_apic_access_page(vcpu);
6518 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6519 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6520 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6524 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6525 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6526 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6530 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6531 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6532 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6538 * KVM_REQ_HV_STIMER has to be processed after
6539 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6540 * depend on the guest clock being up-to-date
6542 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6543 kvm_hv_process_stimers(vcpu);
6547 * KVM_REQ_EVENT is not set when posted interrupts are set by
6548 * VT-d hardware, so we have to update RVI unconditionally.
6550 if (kvm_lapic_enabled(vcpu)) {
6552 * Update architecture specific hints for APIC
6553 * virtual interrupt delivery.
6555 if (vcpu->arch.apicv_active)
6556 kvm_x86_ops->hwapic_irr_update(vcpu,
6557 kvm_lapic_find_highest_irr(vcpu));
6560 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6561 kvm_apic_accept_events(vcpu);
6562 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6567 if (inject_pending_event(vcpu, req_int_win) != 0)
6568 req_immediate_exit = true;
6569 /* enable NMI/IRQ window open exits if needed */
6571 if (vcpu->arch.nmi_pending)
6572 kvm_x86_ops->enable_nmi_window(vcpu);
6573 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6574 kvm_x86_ops->enable_irq_window(vcpu);
6577 if (kvm_lapic_enabled(vcpu)) {
6578 update_cr8_intercept(vcpu);
6579 kvm_lapic_sync_to_vapic(vcpu);
6583 r = kvm_mmu_reload(vcpu);
6585 goto cancel_injection;
6590 kvm_x86_ops->prepare_guest_switch(vcpu);
6591 if (vcpu->fpu_active)
6592 kvm_load_guest_fpu(vcpu);
6593 kvm_load_guest_xcr0(vcpu);
6595 vcpu->mode = IN_GUEST_MODE;
6597 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6600 * We should set ->mode before check ->requests,
6601 * Please see the comment in kvm_make_all_cpus_request.
6602 * This also orders the write to mode from any reads
6603 * to the page tables done while the VCPU is running.
6604 * Please see the comment in kvm_flush_remote_tlbs.
6606 smp_mb__after_srcu_read_unlock();
6608 local_irq_disable();
6610 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6611 || need_resched() || signal_pending(current)) {
6612 vcpu->mode = OUTSIDE_GUEST_MODE;
6616 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6618 goto cancel_injection;
6621 if (req_immediate_exit)
6622 smp_send_reschedule(vcpu->cpu);
6624 trace_kvm_entry(vcpu->vcpu_id);
6625 wait_lapic_expire(vcpu);
6626 __kvm_guest_enter();
6628 if (unlikely(vcpu->arch.switch_db_regs)) {
6630 set_debugreg(vcpu->arch.eff_db[0], 0);
6631 set_debugreg(vcpu->arch.eff_db[1], 1);
6632 set_debugreg(vcpu->arch.eff_db[2], 2);
6633 set_debugreg(vcpu->arch.eff_db[3], 3);
6634 set_debugreg(vcpu->arch.dr6, 6);
6635 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6638 kvm_x86_ops->run(vcpu);
6641 * Do this here before restoring debug registers on the host. And
6642 * since we do this before handling the vmexit, a DR access vmexit
6643 * can (a) read the correct value of the debug registers, (b) set
6644 * KVM_DEBUGREG_WONT_EXIT again.
6646 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6647 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6648 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6649 kvm_update_dr0123(vcpu);
6650 kvm_update_dr6(vcpu);
6651 kvm_update_dr7(vcpu);
6652 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6656 * If the guest has used debug registers, at least dr7
6657 * will be disabled while returning to the host.
6658 * If we don't have active breakpoints in the host, we don't
6659 * care about the messed up debug address registers. But if
6660 * we have some of them active, restore the old state.
6662 if (hw_breakpoint_active())
6663 hw_breakpoint_restore();
6665 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6667 vcpu->mode = OUTSIDE_GUEST_MODE;
6670 /* Interrupt is enabled by handle_external_intr() */
6671 kvm_x86_ops->handle_external_intr(vcpu);
6676 * We must have an instruction between local_irq_enable() and
6677 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6678 * the interrupt shadow. The stat.exits increment will do nicely.
6679 * But we need to prevent reordering, hence this barrier():
6687 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6690 * Profile KVM exit RIPs:
6692 if (unlikely(prof_on == KVM_PROFILING)) {
6693 unsigned long rip = kvm_rip_read(vcpu);
6694 profile_hit(KVM_PROFILING, (void *)rip);
6697 if (unlikely(vcpu->arch.tsc_always_catchup))
6698 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6700 if (vcpu->arch.apic_attention)
6701 kvm_lapic_sync_from_vapic(vcpu);
6703 r = kvm_x86_ops->handle_exit(vcpu);
6707 kvm_x86_ops->cancel_injection(vcpu);
6708 if (unlikely(vcpu->arch.apic_attention))
6709 kvm_lapic_sync_from_vapic(vcpu);
6714 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6716 if (!kvm_arch_vcpu_runnable(vcpu) &&
6717 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6718 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6719 kvm_vcpu_block(vcpu);
6720 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6722 if (kvm_x86_ops->post_block)
6723 kvm_x86_ops->post_block(vcpu);
6725 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6729 kvm_apic_accept_events(vcpu);
6730 switch(vcpu->arch.mp_state) {
6731 case KVM_MP_STATE_HALTED:
6732 vcpu->arch.pv.pv_unhalted = false;
6733 vcpu->arch.mp_state =
6734 KVM_MP_STATE_RUNNABLE;
6735 case KVM_MP_STATE_RUNNABLE:
6736 vcpu->arch.apf.halted = false;
6738 case KVM_MP_STATE_INIT_RECEIVED:
6747 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6749 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6750 !vcpu->arch.apf.halted);
6753 static int vcpu_run(struct kvm_vcpu *vcpu)
6756 struct kvm *kvm = vcpu->kvm;
6758 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6761 if (kvm_vcpu_running(vcpu)) {
6762 r = vcpu_enter_guest(vcpu);
6764 r = vcpu_block(kvm, vcpu);
6770 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6771 if (kvm_cpu_has_pending_timer(vcpu))
6772 kvm_inject_pending_timer_irqs(vcpu);
6774 if (dm_request_for_irq_injection(vcpu) &&
6775 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6777 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6778 ++vcpu->stat.request_irq_exits;
6782 kvm_check_async_pf_completion(vcpu);
6784 if (signal_pending(current)) {
6786 vcpu->run->exit_reason = KVM_EXIT_INTR;
6787 ++vcpu->stat.signal_exits;
6790 if (need_resched()) {
6791 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6793 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6797 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6802 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6805 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6806 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6807 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6808 if (r != EMULATE_DONE)
6813 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6815 BUG_ON(!vcpu->arch.pio.count);
6817 return complete_emulated_io(vcpu);
6821 * Implements the following, as a state machine:
6825 * for each mmio piece in the fragment
6833 * for each mmio piece in the fragment
6838 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6840 struct kvm_run *run = vcpu->run;
6841 struct kvm_mmio_fragment *frag;
6844 BUG_ON(!vcpu->mmio_needed);
6846 /* Complete previous fragment */
6847 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6848 len = min(8u, frag->len);
6849 if (!vcpu->mmio_is_write)
6850 memcpy(frag->data, run->mmio.data, len);
6852 if (frag->len <= 8) {
6853 /* Switch to the next fragment. */
6855 vcpu->mmio_cur_fragment++;
6857 /* Go forward to the next mmio piece. */
6863 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6864 vcpu->mmio_needed = 0;
6866 /* FIXME: return into emulator if single-stepping. */
6867 if (vcpu->mmio_is_write)
6869 vcpu->mmio_read_completed = 1;
6870 return complete_emulated_io(vcpu);
6873 run->exit_reason = KVM_EXIT_MMIO;
6874 run->mmio.phys_addr = frag->gpa;
6875 if (vcpu->mmio_is_write)
6876 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6877 run->mmio.len = min(8u, frag->len);
6878 run->mmio.is_write = vcpu->mmio_is_write;
6879 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6884 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6886 struct fpu *fpu = ¤t->thread.fpu;
6890 fpu__activate_curr(fpu);
6892 if (vcpu->sigset_active)
6893 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6895 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6896 kvm_vcpu_block(vcpu);
6897 kvm_apic_accept_events(vcpu);
6898 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6903 /* re-sync apic's tpr */
6904 if (!lapic_in_kernel(vcpu)) {
6905 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6911 if (unlikely(vcpu->arch.complete_userspace_io)) {
6912 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6913 vcpu->arch.complete_userspace_io = NULL;
6918 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6923 post_kvm_run_save(vcpu);
6924 if (vcpu->sigset_active)
6925 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6930 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6932 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6934 * We are here if userspace calls get_regs() in the middle of
6935 * instruction emulation. Registers state needs to be copied
6936 * back from emulation context to vcpu. Userspace shouldn't do
6937 * that usually, but some bad designed PV devices (vmware
6938 * backdoor interface) need this to work
6940 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6941 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6943 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6944 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6945 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6946 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6947 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6948 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6949 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6950 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6951 #ifdef CONFIG_X86_64
6952 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6953 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6954 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6955 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6956 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6957 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6958 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6959 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6962 regs->rip = kvm_rip_read(vcpu);
6963 regs->rflags = kvm_get_rflags(vcpu);
6968 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6970 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6971 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6973 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6974 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6975 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6976 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6977 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6978 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6979 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6980 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6981 #ifdef CONFIG_X86_64
6982 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6983 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6984 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6985 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6986 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6987 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6988 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6989 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6992 kvm_rip_write(vcpu, regs->rip);
6993 kvm_set_rflags(vcpu, regs->rflags);
6995 vcpu->arch.exception.pending = false;
6997 kvm_make_request(KVM_REQ_EVENT, vcpu);
7002 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7004 struct kvm_segment cs;
7006 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7010 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7012 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7013 struct kvm_sregs *sregs)
7017 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7018 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7019 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7020 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7021 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7022 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7024 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7025 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7027 kvm_x86_ops->get_idt(vcpu, &dt);
7028 sregs->idt.limit = dt.size;
7029 sregs->idt.base = dt.address;
7030 kvm_x86_ops->get_gdt(vcpu, &dt);
7031 sregs->gdt.limit = dt.size;
7032 sregs->gdt.base = dt.address;
7034 sregs->cr0 = kvm_read_cr0(vcpu);
7035 sregs->cr2 = vcpu->arch.cr2;
7036 sregs->cr3 = kvm_read_cr3(vcpu);
7037 sregs->cr4 = kvm_read_cr4(vcpu);
7038 sregs->cr8 = kvm_get_cr8(vcpu);
7039 sregs->efer = vcpu->arch.efer;
7040 sregs->apic_base = kvm_get_apic_base(vcpu);
7042 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7044 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7045 set_bit(vcpu->arch.interrupt.nr,
7046 (unsigned long *)sregs->interrupt_bitmap);
7051 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7052 struct kvm_mp_state *mp_state)
7054 kvm_apic_accept_events(vcpu);
7055 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7056 vcpu->arch.pv.pv_unhalted)
7057 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7059 mp_state->mp_state = vcpu->arch.mp_state;
7064 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7065 struct kvm_mp_state *mp_state)
7067 if (!lapic_in_kernel(vcpu) &&
7068 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7071 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7072 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7073 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7075 vcpu->arch.mp_state = mp_state->mp_state;
7076 kvm_make_request(KVM_REQ_EVENT, vcpu);
7080 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7081 int reason, bool has_error_code, u32 error_code)
7083 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7086 init_emulate_ctxt(vcpu);
7088 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7089 has_error_code, error_code);
7092 return EMULATE_FAIL;
7094 kvm_rip_write(vcpu, ctxt->eip);
7095 kvm_set_rflags(vcpu, ctxt->eflags);
7096 kvm_make_request(KVM_REQ_EVENT, vcpu);
7097 return EMULATE_DONE;
7099 EXPORT_SYMBOL_GPL(kvm_task_switch);
7101 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7102 struct kvm_sregs *sregs)
7104 struct msr_data apic_base_msr;
7105 int mmu_reset_needed = 0;
7106 int pending_vec, max_bits, idx;
7109 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7112 dt.size = sregs->idt.limit;
7113 dt.address = sregs->idt.base;
7114 kvm_x86_ops->set_idt(vcpu, &dt);
7115 dt.size = sregs->gdt.limit;
7116 dt.address = sregs->gdt.base;
7117 kvm_x86_ops->set_gdt(vcpu, &dt);
7119 vcpu->arch.cr2 = sregs->cr2;
7120 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7121 vcpu->arch.cr3 = sregs->cr3;
7122 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7124 kvm_set_cr8(vcpu, sregs->cr8);
7126 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7127 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7128 apic_base_msr.data = sregs->apic_base;
7129 apic_base_msr.host_initiated = true;
7130 kvm_set_apic_base(vcpu, &apic_base_msr);
7132 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7133 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7134 vcpu->arch.cr0 = sregs->cr0;
7136 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7137 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7138 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7139 kvm_update_cpuid(vcpu);
7141 idx = srcu_read_lock(&vcpu->kvm->srcu);
7142 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7143 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7144 mmu_reset_needed = 1;
7146 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7148 if (mmu_reset_needed)
7149 kvm_mmu_reset_context(vcpu);
7151 max_bits = KVM_NR_INTERRUPTS;
7152 pending_vec = find_first_bit(
7153 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7154 if (pending_vec < max_bits) {
7155 kvm_queue_interrupt(vcpu, pending_vec, false);
7156 pr_debug("Set back pending irq %d\n", pending_vec);
7159 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7160 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7161 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7162 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7163 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7164 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7166 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7167 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7169 update_cr8_intercept(vcpu);
7171 /* Older userspace won't unhalt the vcpu on reset. */
7172 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7173 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7175 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7177 kvm_make_request(KVM_REQ_EVENT, vcpu);
7182 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7183 struct kvm_guest_debug *dbg)
7185 unsigned long rflags;
7188 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7190 if (vcpu->arch.exception.pending)
7192 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7193 kvm_queue_exception(vcpu, DB_VECTOR);
7195 kvm_queue_exception(vcpu, BP_VECTOR);
7199 * Read rflags as long as potentially injected trace flags are still
7202 rflags = kvm_get_rflags(vcpu);
7204 vcpu->guest_debug = dbg->control;
7205 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7206 vcpu->guest_debug = 0;
7208 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7209 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7210 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7211 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7213 for (i = 0; i < KVM_NR_DB_REGS; i++)
7214 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7216 kvm_update_dr7(vcpu);
7218 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7219 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7220 get_segment_base(vcpu, VCPU_SREG_CS);
7223 * Trigger an rflags update that will inject or remove the trace
7226 kvm_set_rflags(vcpu, rflags);
7228 kvm_x86_ops->update_bp_intercept(vcpu);
7238 * Translate a guest virtual address to a guest physical address.
7240 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7241 struct kvm_translation *tr)
7243 unsigned long vaddr = tr->linear_address;
7247 idx = srcu_read_lock(&vcpu->kvm->srcu);
7248 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7249 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7250 tr->physical_address = gpa;
7251 tr->valid = gpa != UNMAPPED_GVA;
7258 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7260 struct fxregs_state *fxsave =
7261 &vcpu->arch.guest_fpu.state.fxsave;
7263 memcpy(fpu->fpr, fxsave->st_space, 128);
7264 fpu->fcw = fxsave->cwd;
7265 fpu->fsw = fxsave->swd;
7266 fpu->ftwx = fxsave->twd;
7267 fpu->last_opcode = fxsave->fop;
7268 fpu->last_ip = fxsave->rip;
7269 fpu->last_dp = fxsave->rdp;
7270 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7275 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7277 struct fxregs_state *fxsave =
7278 &vcpu->arch.guest_fpu.state.fxsave;
7280 memcpy(fxsave->st_space, fpu->fpr, 128);
7281 fxsave->cwd = fpu->fcw;
7282 fxsave->swd = fpu->fsw;
7283 fxsave->twd = fpu->ftwx;
7284 fxsave->fop = fpu->last_opcode;
7285 fxsave->rip = fpu->last_ip;
7286 fxsave->rdp = fpu->last_dp;
7287 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7292 static void fx_init(struct kvm_vcpu *vcpu)
7294 fpstate_init(&vcpu->arch.guest_fpu.state);
7296 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7297 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7300 * Ensure guest xcr0 is valid for loading
7302 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7304 vcpu->arch.cr0 |= X86_CR0_ET;
7307 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7309 if (vcpu->guest_fpu_loaded)
7313 * Restore all possible states in the guest,
7314 * and assume host would use all available bits.
7315 * Guest xcr0 would be loaded later.
7317 kvm_put_guest_xcr0(vcpu);
7318 vcpu->guest_fpu_loaded = 1;
7319 __kernel_fpu_begin();
7320 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7324 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7326 kvm_put_guest_xcr0(vcpu);
7328 if (!vcpu->guest_fpu_loaded) {
7329 vcpu->fpu_counter = 0;
7333 vcpu->guest_fpu_loaded = 0;
7334 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7336 ++vcpu->stat.fpu_reload;
7338 * If using eager FPU mode, or if the guest is a frequent user
7339 * of the FPU, just leave the FPU active for next time.
7340 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7341 * the FPU in bursts will revert to loading it on demand.
7343 if (!use_eager_fpu()) {
7344 if (++vcpu->fpu_counter < 5)
7345 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7350 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7352 kvmclock_reset(vcpu);
7354 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7355 kvm_x86_ops->vcpu_free(vcpu);
7358 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7361 struct kvm_vcpu *vcpu;
7363 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7364 printk_once(KERN_WARNING
7365 "kvm: SMP vm created on host with unstable TSC; "
7366 "guest TSC will not be reliable\n");
7368 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7373 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7377 kvm_vcpu_mtrr_init(vcpu);
7378 r = vcpu_load(vcpu);
7381 kvm_vcpu_reset(vcpu, false);
7382 kvm_mmu_setup(vcpu);
7387 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7389 struct msr_data msr;
7390 struct kvm *kvm = vcpu->kvm;
7392 if (vcpu_load(vcpu))
7395 msr.index = MSR_IA32_TSC;
7396 msr.host_initiated = true;
7397 kvm_write_tsc(vcpu, &msr);
7400 if (!kvmclock_periodic_sync)
7403 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7404 KVMCLOCK_SYNC_PERIOD);
7407 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7410 vcpu->arch.apf.msr_val = 0;
7412 r = vcpu_load(vcpu);
7414 kvm_mmu_unload(vcpu);
7417 kvm_x86_ops->vcpu_free(vcpu);
7420 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7422 vcpu->arch.hflags = 0;
7424 atomic_set(&vcpu->arch.nmi_queued, 0);
7425 vcpu->arch.nmi_pending = 0;
7426 vcpu->arch.nmi_injected = false;
7427 kvm_clear_interrupt_queue(vcpu);
7428 kvm_clear_exception_queue(vcpu);
7430 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7431 kvm_update_dr0123(vcpu);
7432 vcpu->arch.dr6 = DR6_INIT;
7433 kvm_update_dr6(vcpu);
7434 vcpu->arch.dr7 = DR7_FIXED_1;
7435 kvm_update_dr7(vcpu);
7439 kvm_make_request(KVM_REQ_EVENT, vcpu);
7440 vcpu->arch.apf.msr_val = 0;
7441 vcpu->arch.st.msr_val = 0;
7443 kvmclock_reset(vcpu);
7445 kvm_clear_async_pf_completion_queue(vcpu);
7446 kvm_async_pf_hash_reset(vcpu);
7447 vcpu->arch.apf.halted = false;
7450 kvm_pmu_reset(vcpu);
7451 vcpu->arch.smbase = 0x30000;
7454 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7455 vcpu->arch.regs_avail = ~0;
7456 vcpu->arch.regs_dirty = ~0;
7458 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7461 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7463 struct kvm_segment cs;
7465 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7466 cs.selector = vector << 8;
7467 cs.base = vector << 12;
7468 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7469 kvm_rip_write(vcpu, 0);
7472 int kvm_arch_hardware_enable(void)
7475 struct kvm_vcpu *vcpu;
7480 bool stable, backwards_tsc = false;
7482 kvm_shared_msr_cpu_online();
7483 ret = kvm_x86_ops->hardware_enable();
7487 local_tsc = rdtsc();
7488 stable = !check_tsc_unstable();
7489 list_for_each_entry(kvm, &vm_list, vm_list) {
7490 kvm_for_each_vcpu(i, vcpu, kvm) {
7491 if (!stable && vcpu->cpu == smp_processor_id())
7492 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7493 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7494 backwards_tsc = true;
7495 if (vcpu->arch.last_host_tsc > max_tsc)
7496 max_tsc = vcpu->arch.last_host_tsc;
7502 * Sometimes, even reliable TSCs go backwards. This happens on
7503 * platforms that reset TSC during suspend or hibernate actions, but
7504 * maintain synchronization. We must compensate. Fortunately, we can
7505 * detect that condition here, which happens early in CPU bringup,
7506 * before any KVM threads can be running. Unfortunately, we can't
7507 * bring the TSCs fully up to date with real time, as we aren't yet far
7508 * enough into CPU bringup that we know how much real time has actually
7509 * elapsed; our helper function, get_kernel_ns() will be using boot
7510 * variables that haven't been updated yet.
7512 * So we simply find the maximum observed TSC above, then record the
7513 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7514 * the adjustment will be applied. Note that we accumulate
7515 * adjustments, in case multiple suspend cycles happen before some VCPU
7516 * gets a chance to run again. In the event that no KVM threads get a
7517 * chance to run, we will miss the entire elapsed period, as we'll have
7518 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7519 * loose cycle time. This isn't too big a deal, since the loss will be
7520 * uniform across all VCPUs (not to mention the scenario is extremely
7521 * unlikely). It is possible that a second hibernate recovery happens
7522 * much faster than a first, causing the observed TSC here to be
7523 * smaller; this would require additional padding adjustment, which is
7524 * why we set last_host_tsc to the local tsc observed here.
7526 * N.B. - this code below runs only on platforms with reliable TSC,
7527 * as that is the only way backwards_tsc is set above. Also note
7528 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7529 * have the same delta_cyc adjustment applied if backwards_tsc
7530 * is detected. Note further, this adjustment is only done once,
7531 * as we reset last_host_tsc on all VCPUs to stop this from being
7532 * called multiple times (one for each physical CPU bringup).
7534 * Platforms with unreliable TSCs don't have to deal with this, they
7535 * will be compensated by the logic in vcpu_load, which sets the TSC to
7536 * catchup mode. This will catchup all VCPUs to real time, but cannot
7537 * guarantee that they stay in perfect synchronization.
7539 if (backwards_tsc) {
7540 u64 delta_cyc = max_tsc - local_tsc;
7541 backwards_tsc_observed = true;
7542 list_for_each_entry(kvm, &vm_list, vm_list) {
7543 kvm_for_each_vcpu(i, vcpu, kvm) {
7544 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7545 vcpu->arch.last_host_tsc = local_tsc;
7546 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7550 * We have to disable TSC offset matching.. if you were
7551 * booting a VM while issuing an S4 host suspend....
7552 * you may have some problem. Solving this issue is
7553 * left as an exercise to the reader.
7555 kvm->arch.last_tsc_nsec = 0;
7556 kvm->arch.last_tsc_write = 0;
7563 void kvm_arch_hardware_disable(void)
7565 kvm_x86_ops->hardware_disable();
7566 drop_user_return_notifiers();
7569 int kvm_arch_hardware_setup(void)
7573 r = kvm_x86_ops->hardware_setup();
7577 if (kvm_has_tsc_control) {
7579 * Make sure the user can only configure tsc_khz values that
7580 * fit into a signed integer.
7581 * A min value is not calculated needed because it will always
7582 * be 1 on all machines.
7584 u64 max = min(0x7fffffffULL,
7585 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7586 kvm_max_guest_tsc_khz = max;
7588 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7591 kvm_init_msr_list();
7595 void kvm_arch_hardware_unsetup(void)
7597 kvm_x86_ops->hardware_unsetup();
7600 void kvm_arch_check_processor_compat(void *rtn)
7602 kvm_x86_ops->check_processor_compatibility(rtn);
7605 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7607 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7609 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7611 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7613 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7616 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7618 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7621 struct static_key kvm_no_apic_vcpu __read_mostly;
7622 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7624 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7630 BUG_ON(vcpu->kvm == NULL);
7633 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7634 vcpu->arch.pv.pv_unhalted = false;
7635 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7636 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7637 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7639 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7641 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7646 vcpu->arch.pio_data = page_address(page);
7648 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7650 r = kvm_mmu_create(vcpu);
7652 goto fail_free_pio_data;
7654 if (irqchip_in_kernel(kvm)) {
7655 r = kvm_create_lapic(vcpu);
7657 goto fail_mmu_destroy;
7659 static_key_slow_inc(&kvm_no_apic_vcpu);
7661 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7663 if (!vcpu->arch.mce_banks) {
7665 goto fail_free_lapic;
7667 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7669 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7671 goto fail_free_mce_banks;
7676 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7677 vcpu->arch.pv_time_enabled = false;
7679 vcpu->arch.guest_supported_xcr0 = 0;
7680 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7682 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7684 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7686 kvm_async_pf_hash_reset(vcpu);
7689 vcpu->arch.pending_external_vector = -1;
7691 kvm_hv_vcpu_init(vcpu);
7695 fail_free_mce_banks:
7696 kfree(vcpu->arch.mce_banks);
7698 kvm_free_lapic(vcpu);
7700 kvm_mmu_destroy(vcpu);
7702 free_page((unsigned long)vcpu->arch.pio_data);
7707 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7711 kvm_hv_vcpu_uninit(vcpu);
7712 kvm_pmu_destroy(vcpu);
7713 kfree(vcpu->arch.mce_banks);
7714 kvm_free_lapic(vcpu);
7715 idx = srcu_read_lock(&vcpu->kvm->srcu);
7716 kvm_mmu_destroy(vcpu);
7717 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7718 free_page((unsigned long)vcpu->arch.pio_data);
7719 if (!lapic_in_kernel(vcpu))
7720 static_key_slow_dec(&kvm_no_apic_vcpu);
7723 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7725 kvm_x86_ops->sched_in(vcpu, cpu);
7728 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7733 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7734 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7735 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7736 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7737 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7739 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7740 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7741 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7742 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7743 &kvm->arch.irq_sources_bitmap);
7745 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7746 mutex_init(&kvm->arch.apic_map_lock);
7747 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7749 pvclock_update_vm_gtod_copy(kvm);
7751 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7752 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7754 kvm_page_track_init(kvm);
7755 kvm_mmu_init_vm(kvm);
7760 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7763 r = vcpu_load(vcpu);
7765 kvm_mmu_unload(vcpu);
7769 static void kvm_free_vcpus(struct kvm *kvm)
7772 struct kvm_vcpu *vcpu;
7775 * Unpin any mmu pages first.
7777 kvm_for_each_vcpu(i, vcpu, kvm) {
7778 kvm_clear_async_pf_completion_queue(vcpu);
7779 kvm_unload_vcpu_mmu(vcpu);
7781 kvm_for_each_vcpu(i, vcpu, kvm)
7782 kvm_arch_vcpu_free(vcpu);
7784 mutex_lock(&kvm->lock);
7785 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7786 kvm->vcpus[i] = NULL;
7788 atomic_set(&kvm->online_vcpus, 0);
7789 mutex_unlock(&kvm->lock);
7792 void kvm_arch_sync_events(struct kvm *kvm)
7794 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7795 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7796 kvm_free_all_assigned_devices(kvm);
7800 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7804 struct kvm_memslots *slots = kvm_memslots(kvm);
7805 struct kvm_memory_slot *slot, old;
7807 /* Called with kvm->slots_lock held. */
7808 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7811 slot = id_to_memslot(slots, id);
7813 if (WARN_ON(slot->npages))
7817 * MAP_SHARED to prevent internal slot pages from being moved
7820 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7821 MAP_SHARED | MAP_ANONYMOUS, 0);
7822 if (IS_ERR((void *)hva))
7823 return PTR_ERR((void *)hva);
7832 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7833 struct kvm_userspace_memory_region m;
7835 m.slot = id | (i << 16);
7837 m.guest_phys_addr = gpa;
7838 m.userspace_addr = hva;
7839 m.memory_size = size;
7840 r = __kvm_set_memory_region(kvm, &m);
7846 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7852 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7854 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7858 mutex_lock(&kvm->slots_lock);
7859 r = __x86_set_memory_region(kvm, id, gpa, size);
7860 mutex_unlock(&kvm->slots_lock);
7864 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7866 void kvm_arch_destroy_vm(struct kvm *kvm)
7868 if (current->mm == kvm->mm) {
7870 * Free memory regions allocated on behalf of userspace,
7871 * unless the the memory map has changed due to process exit
7874 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7875 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7876 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7878 kvm_iommu_unmap_guest(kvm);
7879 kfree(kvm->arch.vpic);
7880 kfree(kvm->arch.vioapic);
7881 kvm_free_vcpus(kvm);
7882 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7883 kvm_mmu_uninit_vm(kvm);
7886 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7887 struct kvm_memory_slot *dont)
7891 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7892 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7893 kvfree(free->arch.rmap[i]);
7894 free->arch.rmap[i] = NULL;
7899 if (!dont || free->arch.lpage_info[i - 1] !=
7900 dont->arch.lpage_info[i - 1]) {
7901 kvfree(free->arch.lpage_info[i - 1]);
7902 free->arch.lpage_info[i - 1] = NULL;
7906 kvm_page_track_free_memslot(free, dont);
7909 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7910 unsigned long npages)
7914 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7915 struct kvm_lpage_info *linfo;
7920 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7921 slot->base_gfn, level) + 1;
7923 slot->arch.rmap[i] =
7924 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7925 if (!slot->arch.rmap[i])
7930 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7934 slot->arch.lpage_info[i - 1] = linfo;
7936 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7937 linfo[0].disallow_lpage = 1;
7938 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7939 linfo[lpages - 1].disallow_lpage = 1;
7940 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7942 * If the gfn and userspace address are not aligned wrt each
7943 * other, or if explicitly asked to, disable large page
7944 * support for this slot
7946 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7947 !kvm_largepages_enabled()) {
7950 for (j = 0; j < lpages; ++j)
7951 linfo[j].disallow_lpage = 1;
7955 if (kvm_page_track_create_memslot(slot, npages))
7961 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7962 kvfree(slot->arch.rmap[i]);
7963 slot->arch.rmap[i] = NULL;
7967 kvfree(slot->arch.lpage_info[i - 1]);
7968 slot->arch.lpage_info[i - 1] = NULL;
7973 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7976 * memslots->generation has been incremented.
7977 * mmio generation may have reached its maximum value.
7979 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7982 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7983 struct kvm_memory_slot *memslot,
7984 const struct kvm_userspace_memory_region *mem,
7985 enum kvm_mr_change change)
7990 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7991 struct kvm_memory_slot *new)
7993 /* Still write protect RO slot */
7994 if (new->flags & KVM_MEM_READONLY) {
7995 kvm_mmu_slot_remove_write_access(kvm, new);
8000 * Call kvm_x86_ops dirty logging hooks when they are valid.
8002 * kvm_x86_ops->slot_disable_log_dirty is called when:
8004 * - KVM_MR_CREATE with dirty logging is disabled
8005 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8007 * The reason is, in case of PML, we need to set D-bit for any slots
8008 * with dirty logging disabled in order to eliminate unnecessary GPA
8009 * logging in PML buffer (and potential PML buffer full VMEXT). This
8010 * guarantees leaving PML enabled during guest's lifetime won't have
8011 * any additonal overhead from PML when guest is running with dirty
8012 * logging disabled for memory slots.
8014 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8015 * to dirty logging mode.
8017 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8019 * In case of write protect:
8021 * Write protect all pages for dirty logging.
8023 * All the sptes including the large sptes which point to this
8024 * slot are set to readonly. We can not create any new large
8025 * spte on this slot until the end of the logging.
8027 * See the comments in fast_page_fault().
8029 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8030 if (kvm_x86_ops->slot_enable_log_dirty)
8031 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8033 kvm_mmu_slot_remove_write_access(kvm, new);
8035 if (kvm_x86_ops->slot_disable_log_dirty)
8036 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8040 void kvm_arch_commit_memory_region(struct kvm *kvm,
8041 const struct kvm_userspace_memory_region *mem,
8042 const struct kvm_memory_slot *old,
8043 const struct kvm_memory_slot *new,
8044 enum kvm_mr_change change)
8046 int nr_mmu_pages = 0;
8048 if (!kvm->arch.n_requested_mmu_pages)
8049 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8052 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8055 * Dirty logging tracks sptes in 4k granularity, meaning that large
8056 * sptes have to be split. If live migration is successful, the guest
8057 * in the source machine will be destroyed and large sptes will be
8058 * created in the destination. However, if the guest continues to run
8059 * in the source machine (for example if live migration fails), small
8060 * sptes will remain around and cause bad performance.
8062 * Scan sptes if dirty logging has been stopped, dropping those
8063 * which can be collapsed into a single large-page spte. Later
8064 * page faults will create the large-page sptes.
8066 if ((change != KVM_MR_DELETE) &&
8067 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8068 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8069 kvm_mmu_zap_collapsible_sptes(kvm, new);
8072 * Set up write protection and/or dirty logging for the new slot.
8074 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8075 * been zapped so no dirty logging staff is needed for old slot. For
8076 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8077 * new and it's also covered when dealing with the new slot.
8079 * FIXME: const-ify all uses of struct kvm_memory_slot.
8081 if (change != KVM_MR_DELETE)
8082 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8085 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8087 kvm_mmu_invalidate_zap_all_pages(kvm);
8090 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8091 struct kvm_memory_slot *slot)
8093 kvm_mmu_invalidate_zap_all_pages(kvm);
8096 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8098 if (!list_empty_careful(&vcpu->async_pf.done))
8101 if (kvm_apic_has_events(vcpu))
8104 if (vcpu->arch.pv.pv_unhalted)
8107 if (atomic_read(&vcpu->arch.nmi_queued))
8110 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8113 if (kvm_arch_interrupt_allowed(vcpu) &&
8114 kvm_cpu_has_interrupt(vcpu))
8117 if (kvm_hv_has_stimer_pending(vcpu))
8123 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8125 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8126 kvm_x86_ops->check_nested_events(vcpu, false);
8128 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8131 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8133 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8136 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8138 return kvm_x86_ops->interrupt_allowed(vcpu);
8141 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8143 if (is_64_bit_mode(vcpu))
8144 return kvm_rip_read(vcpu);
8145 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8146 kvm_rip_read(vcpu));
8148 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8150 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8152 return kvm_get_linear_rip(vcpu) == linear_rip;
8154 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8156 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8158 unsigned long rflags;
8160 rflags = kvm_x86_ops->get_rflags(vcpu);
8161 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8162 rflags &= ~X86_EFLAGS_TF;
8165 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8167 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8169 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8170 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8171 rflags |= X86_EFLAGS_TF;
8172 kvm_x86_ops->set_rflags(vcpu, rflags);
8175 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8177 __kvm_set_rflags(vcpu, rflags);
8178 kvm_make_request(KVM_REQ_EVENT, vcpu);
8180 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8182 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8186 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8190 r = kvm_mmu_reload(vcpu);
8194 if (!vcpu->arch.mmu.direct_map &&
8195 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8198 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8201 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8203 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8206 static inline u32 kvm_async_pf_next_probe(u32 key)
8208 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8211 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8213 u32 key = kvm_async_pf_hash_fn(gfn);
8215 while (vcpu->arch.apf.gfns[key] != ~0)
8216 key = kvm_async_pf_next_probe(key);
8218 vcpu->arch.apf.gfns[key] = gfn;
8221 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8224 u32 key = kvm_async_pf_hash_fn(gfn);
8226 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8227 (vcpu->arch.apf.gfns[key] != gfn &&
8228 vcpu->arch.apf.gfns[key] != ~0); i++)
8229 key = kvm_async_pf_next_probe(key);
8234 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8236 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8239 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8243 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8245 vcpu->arch.apf.gfns[i] = ~0;
8247 j = kvm_async_pf_next_probe(j);
8248 if (vcpu->arch.apf.gfns[j] == ~0)
8250 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8252 * k lies cyclically in ]i,j]
8254 * |....j i.k.| or |.k..j i...|
8256 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8257 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8262 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8265 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8269 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8270 struct kvm_async_pf *work)
8272 struct x86_exception fault;
8274 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8275 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8277 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8278 (vcpu->arch.apf.send_user_only &&
8279 kvm_x86_ops->get_cpl(vcpu) == 0))
8280 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8281 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8282 fault.vector = PF_VECTOR;
8283 fault.error_code_valid = true;
8284 fault.error_code = 0;
8285 fault.nested_page_fault = false;
8286 fault.address = work->arch.token;
8287 kvm_inject_page_fault(vcpu, &fault);
8291 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8292 struct kvm_async_pf *work)
8294 struct x86_exception fault;
8296 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8297 if (work->wakeup_all)
8298 work->arch.token = ~0; /* broadcast wakeup */
8300 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8302 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8303 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8304 fault.vector = PF_VECTOR;
8305 fault.error_code_valid = true;
8306 fault.error_code = 0;
8307 fault.nested_page_fault = false;
8308 fault.address = work->arch.token;
8309 kvm_inject_page_fault(vcpu, &fault);
8311 vcpu->arch.apf.halted = false;
8312 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8315 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8317 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8320 return !kvm_event_needs_reinjection(vcpu) &&
8321 kvm_x86_ops->interrupt_allowed(vcpu);
8324 void kvm_arch_start_assignment(struct kvm *kvm)
8326 atomic_inc(&kvm->arch.assigned_device_count);
8328 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8330 void kvm_arch_end_assignment(struct kvm *kvm)
8332 atomic_dec(&kvm->arch.assigned_device_count);
8334 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8336 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8338 return atomic_read(&kvm->arch.assigned_device_count);
8340 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8342 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8344 atomic_inc(&kvm->arch.noncoherent_dma_count);
8346 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8348 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8350 atomic_dec(&kvm->arch.noncoherent_dma_count);
8352 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8354 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8356 return atomic_read(&kvm->arch.noncoherent_dma_count);
8358 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8360 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8361 struct irq_bypass_producer *prod)
8363 struct kvm_kernel_irqfd *irqfd =
8364 container_of(cons, struct kvm_kernel_irqfd, consumer);
8366 if (kvm_x86_ops->update_pi_irte) {
8367 irqfd->producer = prod;
8368 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8369 prod->irq, irqfd->gsi, 1);
8375 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8376 struct irq_bypass_producer *prod)
8379 struct kvm_kernel_irqfd *irqfd =
8380 container_of(cons, struct kvm_kernel_irqfd, consumer);
8382 if (!kvm_x86_ops->update_pi_irte) {
8383 WARN_ON(irqfd->producer != NULL);
8387 WARN_ON(irqfd->producer != prod);
8388 irqfd->producer = NULL;
8391 * When producer of consumer is unregistered, we change back to
8392 * remapped mode, so we can re-use the current implementation
8393 * when the irq is masked/disabed or the consumer side (KVM
8394 * int this case doesn't want to receive the interrupts.
8396 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8398 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8399 " fails: %d\n", irqfd->consumer.token, ret);
8402 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8403 uint32_t guest_irq, bool set)
8405 if (!kvm_x86_ops->update_pi_irte)
8408 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8411 bool kvm_vector_hashing_enabled(void)
8413 return vector_hashing;
8415 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8417 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8419 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8420 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8430 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8432 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8433 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);