2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109 #define KVM_NR_SHARED_MSRS 16
111 struct kvm_shared_msrs_global {
113 u32 msrs[KVM_NR_SHARED_MSRS];
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
119 struct kvm_shared_msr_values {
122 } values[KVM_NR_SHARED_MSRS];
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
164 u64 __read_mostly host_xcr0;
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
175 static void kvm_on_user_return(struct user_return_notifier *urn)
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
193 static void shared_msr_update(unsigned slot, u32 msr)
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
220 static void kvm_shared_msr_cpu_online(void)
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
245 static void drop_user_return_notifiers(void *ignore)
247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
256 return vcpu->arch.apic_base;
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
260 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
278 kvm_lapic_set_base(vcpu, msr_info->data);
281 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
283 asmlinkage void kvm_spurious_fault(void)
285 /* Fault while not rebooting. We want the trace. */
288 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
290 #define EXCPT_BENIGN 0
291 #define EXCPT_CONTRIBUTORY 1
294 static int exception_class(int vector)
304 return EXCPT_CONTRIBUTORY;
311 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
312 unsigned nr, bool has_error, u32 error_code,
318 kvm_make_request(KVM_REQ_EVENT, vcpu);
320 if (!vcpu->arch.exception.pending) {
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
326 vcpu->arch.exception.reinject = reinject;
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
353 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
355 kvm_multiple_exception(vcpu, nr, false, 0, false);
357 EXPORT_SYMBOL_GPL(kvm_queue_exception);
359 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
363 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
365 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
368 kvm_inject_gp(vcpu, 0);
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
372 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
374 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
376 ++vcpu->stat.pf_guest;
377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
380 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
382 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
390 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
395 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
397 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
401 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
403 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
413 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
420 EXPORT_SYMBOL_GPL(kvm_require_cpl);
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
427 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
439 real_gfn = gpa_to_gfn(real_gfn);
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
443 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
445 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
453 * Load the pae pdptrs. Return true is they are all valid.
455 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
471 if (is_present_gpte(pdpte[i]) &&
472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
488 EXPORT_SYMBOL_GPL(load_pdptrs);
490 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
517 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
526 if (cr0 & 0xffffffff00000000UL)
530 cr0 &= ~CR0_RESERVED_BITS;
532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
540 if ((vcpu->arch.efer & EFER_LME)) {
545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
558 kvm_x86_ops->set_cr0(vcpu, cr0);
560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
561 kvm_clear_async_pf_completion_queue(vcpu);
562 kvm_async_pf_hash_reset(vcpu);
565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
569 EXPORT_SYMBOL_GPL(kvm_set_cr0);
571 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
575 EXPORT_SYMBOL_GPL(kvm_lmsw);
577 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
587 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
596 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
599 u64 old_xcr0 = vcpu->arch.xcr0;
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
605 if (!(xcr0 & XSTATE_FP))
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
622 kvm_put_guest_xcr0(vcpu);
623 vcpu->arch.xcr0 = xcr0;
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
630 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
634 kvm_inject_gp(vcpu, 0);
639 EXPORT_SYMBOL_GPL(kvm_set_xcr);
641 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
646 if (cr4 & CR4_RESERVED_BITS)
649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
655 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
658 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
661 if (is_long_mode(vcpu)) {
662 if (!(cr4 & X86_CR4_PAE))
664 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
665 && ((cr4 ^ old_cr4) & pdptr_bits)
666 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
670 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
671 if (!guest_cpuid_has_pcid(vcpu))
674 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
675 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
679 if (kvm_x86_ops->set_cr4(vcpu, cr4))
682 if (((cr4 ^ old_cr4) & pdptr_bits) ||
683 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
684 kvm_mmu_reset_context(vcpu);
686 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
687 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
689 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
690 kvm_update_cpuid(vcpu);
694 EXPORT_SYMBOL_GPL(kvm_set_cr4);
696 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
698 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
699 kvm_mmu_sync_roots(vcpu);
700 kvm_mmu_flush_tlb(vcpu);
704 if (is_long_mode(vcpu) && (cr3 & CR3_L_MODE_RESERVED_BITS))
706 if (is_pae(vcpu) && is_paging(vcpu) &&
707 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
710 vcpu->arch.cr3 = cr3;
711 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
712 kvm_mmu_new_cr3(vcpu);
715 EXPORT_SYMBOL_GPL(kvm_set_cr3);
717 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
719 if (cr8 & CR8_RESERVED_BITS)
721 if (irqchip_in_kernel(vcpu->kvm))
722 kvm_lapic_set_tpr(vcpu, cr8);
724 vcpu->arch.cr8 = cr8;
727 EXPORT_SYMBOL_GPL(kvm_set_cr8);
729 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
731 if (irqchip_in_kernel(vcpu->kvm))
732 return kvm_lapic_get_cr8(vcpu);
734 return vcpu->arch.cr8;
736 EXPORT_SYMBOL_GPL(kvm_get_cr8);
738 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
740 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
741 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
744 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
748 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
749 dr7 = vcpu->arch.guest_debug_dr7;
751 dr7 = vcpu->arch.dr7;
752 kvm_x86_ops->set_dr7(vcpu, dr7);
753 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
754 if (dr7 & DR7_BP_EN_MASK)
755 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
758 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
762 vcpu->arch.db[dr] = val;
763 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
764 vcpu->arch.eff_db[dr] = val;
767 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
771 if (val & 0xffffffff00000000ULL)
773 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
774 kvm_update_dr6(vcpu);
777 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
781 if (val & 0xffffffff00000000ULL)
783 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
784 kvm_update_dr7(vcpu);
791 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
795 res = __kvm_set_dr(vcpu, dr, val);
797 kvm_queue_exception(vcpu, UD_VECTOR);
799 kvm_inject_gp(vcpu, 0);
803 EXPORT_SYMBOL_GPL(kvm_set_dr);
805 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809 *val = vcpu->arch.db[dr];
812 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
816 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
817 *val = vcpu->arch.dr6;
819 *val = kvm_x86_ops->get_dr6(vcpu);
822 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
826 *val = vcpu->arch.dr7;
833 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
835 if (_kvm_get_dr(vcpu, dr, val)) {
836 kvm_queue_exception(vcpu, UD_VECTOR);
841 EXPORT_SYMBOL_GPL(kvm_get_dr);
843 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
845 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
849 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
852 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
853 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
856 EXPORT_SYMBOL_GPL(kvm_rdpmc);
859 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
860 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
862 * This list is modified at module load time to reflect the
863 * capabilities of the host cpu. This capabilities test skips MSRs that are
864 * kvm-specific. Those are put in the beginning of the list.
867 #define KVM_SAVE_MSRS_BEGIN 12
868 static u32 msrs_to_save[] = {
869 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
870 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
871 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
872 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
873 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
875 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
878 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
880 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
881 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
884 static unsigned num_msrs_to_save;
886 static const u32 emulated_msrs[] = {
888 MSR_IA32_TSCDEADLINE,
889 MSR_IA32_MISC_ENABLE,
894 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
896 if (efer & efer_reserved_bits)
899 if (efer & EFER_FFXSR) {
900 struct kvm_cpuid_entry2 *feat;
902 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
903 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
907 if (efer & EFER_SVME) {
908 struct kvm_cpuid_entry2 *feat;
910 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
911 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
917 EXPORT_SYMBOL_GPL(kvm_valid_efer);
919 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
921 u64 old_efer = vcpu->arch.efer;
923 if (!kvm_valid_efer(vcpu, efer))
927 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
931 efer |= vcpu->arch.efer & EFER_LMA;
933 kvm_x86_ops->set_efer(vcpu, efer);
935 /* Update reserved bits */
936 if ((efer ^ old_efer) & EFER_NX)
937 kvm_mmu_reset_context(vcpu);
942 void kvm_enable_efer_bits(u64 mask)
944 efer_reserved_bits &= ~mask;
946 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
950 * Writes msr value into into the appropriate "register".
951 * Returns 0 on success, non-0 otherwise.
952 * Assumes vcpu_load() was already called.
954 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
956 return kvm_x86_ops->set_msr(vcpu, msr);
960 * Adapt set_msr() to msr_io()'s calling convention
962 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
968 msr.host_initiated = true;
969 return kvm_set_msr(vcpu, &msr);
973 struct pvclock_gtod_data {
976 struct { /* extract of a clocksource struct */
984 /* open coded 'struct timespec' */
985 u64 monotonic_time_snsec;
986 time_t monotonic_time_sec;
989 static struct pvclock_gtod_data pvclock_gtod_data;
991 static void update_pvclock_gtod(struct timekeeper *tk)
993 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
995 write_seqcount_begin(&vdata->seq);
997 /* copy pvclock gtod data */
998 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
999 vdata->clock.cycle_last = tk->clock->cycle_last;
1000 vdata->clock.mask = tk->clock->mask;
1001 vdata->clock.mult = tk->mult;
1002 vdata->clock.shift = tk->shift;
1004 vdata->monotonic_time_sec = tk->xtime_sec
1005 + tk->wall_to_monotonic.tv_sec;
1006 vdata->monotonic_time_snsec = tk->xtime_nsec
1007 + (tk->wall_to_monotonic.tv_nsec
1009 while (vdata->monotonic_time_snsec >=
1010 (((u64)NSEC_PER_SEC) << tk->shift)) {
1011 vdata->monotonic_time_snsec -=
1012 ((u64)NSEC_PER_SEC) << tk->shift;
1013 vdata->monotonic_time_sec++;
1016 write_seqcount_end(&vdata->seq);
1021 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1025 struct pvclock_wall_clock wc;
1026 struct timespec boot;
1031 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1036 ++version; /* first time write, random junk */
1040 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1043 * The guest calculates current wall clock time by adding
1044 * system time (updated by kvm_guest_time_update below) to the
1045 * wall clock specified here. guest system time equals host
1046 * system time for us, thus we must fill in host boot time here.
1050 if (kvm->arch.kvmclock_offset) {
1051 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1052 boot = timespec_sub(boot, ts);
1054 wc.sec = boot.tv_sec;
1055 wc.nsec = boot.tv_nsec;
1056 wc.version = version;
1058 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1061 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1064 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1066 uint32_t quotient, remainder;
1068 /* Don't try to replace with do_div(), this one calculates
1069 * "(dividend << 32) / divisor" */
1071 : "=a" (quotient), "=d" (remainder)
1072 : "0" (0), "1" (dividend), "r" (divisor) );
1076 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1077 s8 *pshift, u32 *pmultiplier)
1084 tps64 = base_khz * 1000LL;
1085 scaled64 = scaled_khz * 1000LL;
1086 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1091 tps32 = (uint32_t)tps64;
1092 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1093 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1101 *pmultiplier = div_frac(scaled64, tps32);
1103 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1104 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1107 static inline u64 get_kernel_ns(void)
1112 monotonic_to_bootbased(&ts);
1113 return timespec_to_ns(&ts);
1116 #ifdef CONFIG_X86_64
1117 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1120 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1121 unsigned long max_tsc_khz;
1123 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1125 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1126 vcpu->arch.virtual_tsc_shift);
1129 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1131 u64 v = (u64)khz * (1000000 + ppm);
1136 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1138 u32 thresh_lo, thresh_hi;
1139 int use_scaling = 0;
1141 /* tsc_khz can be zero if TSC calibration fails */
1142 if (this_tsc_khz == 0)
1145 /* Compute a scale to convert nanoseconds in TSC cycles */
1146 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1147 &vcpu->arch.virtual_tsc_shift,
1148 &vcpu->arch.virtual_tsc_mult);
1149 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1152 * Compute the variation in TSC rate which is acceptable
1153 * within the range of tolerance and decide if the
1154 * rate being applied is within that bounds of the hardware
1155 * rate. If so, no scaling or compensation need be done.
1157 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1158 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1159 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1160 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1163 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1166 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1168 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1169 vcpu->arch.virtual_tsc_mult,
1170 vcpu->arch.virtual_tsc_shift);
1171 tsc += vcpu->arch.this_tsc_write;
1175 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1177 #ifdef CONFIG_X86_64
1179 bool do_request = false;
1180 struct kvm_arch *ka = &vcpu->kvm->arch;
1181 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1183 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1184 atomic_read(&vcpu->kvm->online_vcpus));
1186 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1187 if (!ka->use_master_clock)
1190 if (!vcpus_matched && ka->use_master_clock)
1194 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1196 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1197 atomic_read(&vcpu->kvm->online_vcpus),
1198 ka->use_master_clock, gtod->clock.vclock_mode);
1202 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1204 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1205 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1208 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1210 struct kvm *kvm = vcpu->kvm;
1211 u64 offset, ns, elapsed;
1212 unsigned long flags;
1215 u64 data = msr->data;
1217 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1218 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1219 ns = get_kernel_ns();
1220 elapsed = ns - kvm->arch.last_tsc_nsec;
1222 if (vcpu->arch.virtual_tsc_khz) {
1225 /* n.b - signed multiplication and division required */
1226 usdiff = data - kvm->arch.last_tsc_write;
1227 #ifdef CONFIG_X86_64
1228 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1230 /* do_div() only does unsigned */
1231 asm("1: idivl %[divisor]\n"
1232 "2: xor %%edx, %%edx\n"
1233 " movl $0, %[faulted]\n"
1235 ".section .fixup,\"ax\"\n"
1236 "4: movl $1, %[faulted]\n"
1240 _ASM_EXTABLE(1b, 4b)
1242 : "=A"(usdiff), [faulted] "=r" (faulted)
1243 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1246 do_div(elapsed, 1000);
1251 /* idivl overflow => difference is larger than USEC_PER_SEC */
1253 usdiff = USEC_PER_SEC;
1255 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1258 * Special case: TSC write with a small delta (1 second) of virtual
1259 * cycle time against real time is interpreted as an attempt to
1260 * synchronize the CPU.
1262 * For a reliable TSC, we can match TSC offsets, and for an unstable
1263 * TSC, we add elapsed time in this computation. We could let the
1264 * compensation code attempt to catch up if we fall behind, but
1265 * it's better to try to match offsets from the beginning.
1267 if (usdiff < USEC_PER_SEC &&
1268 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1269 if (!check_tsc_unstable()) {
1270 offset = kvm->arch.cur_tsc_offset;
1271 pr_debug("kvm: matched tsc offset for %llu\n", data);
1273 u64 delta = nsec_to_cycles(vcpu, elapsed);
1275 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1276 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1281 * We split periods of matched TSC writes into generations.
1282 * For each generation, we track the original measured
1283 * nanosecond time, offset, and write, so if TSCs are in
1284 * sync, we can match exact offset, and if not, we can match
1285 * exact software computation in compute_guest_tsc()
1287 * These values are tracked in kvm->arch.cur_xxx variables.
1289 kvm->arch.cur_tsc_generation++;
1290 kvm->arch.cur_tsc_nsec = ns;
1291 kvm->arch.cur_tsc_write = data;
1292 kvm->arch.cur_tsc_offset = offset;
1294 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1295 kvm->arch.cur_tsc_generation, data);
1299 * We also track th most recent recorded KHZ, write and time to
1300 * allow the matching interval to be extended at each write.
1302 kvm->arch.last_tsc_nsec = ns;
1303 kvm->arch.last_tsc_write = data;
1304 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1306 vcpu->arch.last_guest_tsc = data;
1308 /* Keep track of which generation this VCPU has synchronized to */
1309 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1310 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1311 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1313 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1314 update_ia32_tsc_adjust_msr(vcpu, offset);
1315 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1316 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1318 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1320 kvm->arch.nr_vcpus_matched_tsc++;
1322 kvm->arch.nr_vcpus_matched_tsc = 0;
1324 kvm_track_tsc_matching(vcpu);
1325 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1328 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1330 #ifdef CONFIG_X86_64
1332 static cycle_t read_tsc(void)
1338 * Empirically, a fence (of type that depends on the CPU)
1339 * before rdtsc is enough to ensure that rdtsc is ordered
1340 * with respect to loads. The various CPU manuals are unclear
1341 * as to whether rdtsc can be reordered with later loads,
1342 * but no one has ever seen it happen.
1345 ret = (cycle_t)vget_cycles();
1347 last = pvclock_gtod_data.clock.cycle_last;
1349 if (likely(ret >= last))
1353 * GCC likes to generate cmov here, but this branch is extremely
1354 * predictable (it's just a funciton of time and the likely is
1355 * very likely) and there's a data dependence, so force GCC
1356 * to generate a branch instead. I don't barrier() because
1357 * we don't actually need a barrier, and if this function
1358 * ever gets inlined it will generate worse code.
1364 static inline u64 vgettsc(cycle_t *cycle_now)
1367 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1369 *cycle_now = read_tsc();
1371 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1372 return v * gtod->clock.mult;
1375 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1380 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1384 seq = read_seqcount_begin(>od->seq);
1385 mode = gtod->clock.vclock_mode;
1386 ts->tv_sec = gtod->monotonic_time_sec;
1387 ns = gtod->monotonic_time_snsec;
1388 ns += vgettsc(cycle_now);
1389 ns >>= gtod->clock.shift;
1390 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1391 timespec_add_ns(ts, ns);
1396 /* returns true if host is using tsc clocksource */
1397 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1401 /* checked again under seqlock below */
1402 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1405 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1408 monotonic_to_bootbased(&ts);
1409 *kernel_ns = timespec_to_ns(&ts);
1417 * Assuming a stable TSC across physical CPUS, and a stable TSC
1418 * across virtual CPUs, the following condition is possible.
1419 * Each numbered line represents an event visible to both
1420 * CPUs at the next numbered event.
1422 * "timespecX" represents host monotonic time. "tscX" represents
1425 * VCPU0 on CPU0 | VCPU1 on CPU1
1427 * 1. read timespec0,tsc0
1428 * 2. | timespec1 = timespec0 + N
1430 * 3. transition to guest | transition to guest
1431 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1432 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1433 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1435 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1438 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1440 * - 0 < N - M => M < N
1442 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1443 * always the case (the difference between two distinct xtime instances
1444 * might be smaller then the difference between corresponding TSC reads,
1445 * when updating guest vcpus pvclock areas).
1447 * To avoid that problem, do not allow visibility of distinct
1448 * system_timestamp/tsc_timestamp values simultaneously: use a master
1449 * copy of host monotonic time values. Update that master copy
1452 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1456 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1458 #ifdef CONFIG_X86_64
1459 struct kvm_arch *ka = &kvm->arch;
1461 bool host_tsc_clocksource, vcpus_matched;
1463 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1464 atomic_read(&kvm->online_vcpus));
1467 * If the host uses TSC clock, then passthrough TSC as stable
1470 host_tsc_clocksource = kvm_get_time_and_clockread(
1471 &ka->master_kernel_ns,
1472 &ka->master_cycle_now);
1474 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1476 if (ka->use_master_clock)
1477 atomic_set(&kvm_guest_has_master_clock, 1);
1479 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1480 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1485 static void kvm_gen_update_masterclock(struct kvm *kvm)
1487 #ifdef CONFIG_X86_64
1489 struct kvm_vcpu *vcpu;
1490 struct kvm_arch *ka = &kvm->arch;
1492 spin_lock(&ka->pvclock_gtod_sync_lock);
1493 kvm_make_mclock_inprogress_request(kvm);
1494 /* no guest entries from this point */
1495 pvclock_update_vm_gtod_copy(kvm);
1497 kvm_for_each_vcpu(i, vcpu, kvm)
1498 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1500 /* guest entries allowed */
1501 kvm_for_each_vcpu(i, vcpu, kvm)
1502 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1504 spin_unlock(&ka->pvclock_gtod_sync_lock);
1508 static int kvm_guest_time_update(struct kvm_vcpu *v)
1510 unsigned long flags, this_tsc_khz;
1511 struct kvm_vcpu_arch *vcpu = &v->arch;
1512 struct kvm_arch *ka = &v->kvm->arch;
1514 u64 tsc_timestamp, host_tsc;
1515 struct pvclock_vcpu_time_info guest_hv_clock;
1517 bool use_master_clock;
1523 * If the host uses TSC clock, then passthrough TSC as stable
1526 spin_lock(&ka->pvclock_gtod_sync_lock);
1527 use_master_clock = ka->use_master_clock;
1528 if (use_master_clock) {
1529 host_tsc = ka->master_cycle_now;
1530 kernel_ns = ka->master_kernel_ns;
1532 spin_unlock(&ka->pvclock_gtod_sync_lock);
1534 /* Keep irq disabled to prevent changes to the clock */
1535 local_irq_save(flags);
1536 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1537 if (unlikely(this_tsc_khz == 0)) {
1538 local_irq_restore(flags);
1539 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1542 if (!use_master_clock) {
1543 host_tsc = native_read_tsc();
1544 kernel_ns = get_kernel_ns();
1547 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1550 * We may have to catch up the TSC to match elapsed wall clock
1551 * time for two reasons, even if kvmclock is used.
1552 * 1) CPU could have been running below the maximum TSC rate
1553 * 2) Broken TSC compensation resets the base at each VCPU
1554 * entry to avoid unknown leaps of TSC even when running
1555 * again on the same CPU. This may cause apparent elapsed
1556 * time to disappear, and the guest to stand still or run
1559 if (vcpu->tsc_catchup) {
1560 u64 tsc = compute_guest_tsc(v, kernel_ns);
1561 if (tsc > tsc_timestamp) {
1562 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1563 tsc_timestamp = tsc;
1567 local_irq_restore(flags);
1569 if (!vcpu->pv_time_enabled)
1572 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1573 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1574 &vcpu->hv_clock.tsc_shift,
1575 &vcpu->hv_clock.tsc_to_system_mul);
1576 vcpu->hw_tsc_khz = this_tsc_khz;
1579 /* With all the info we got, fill in the values */
1580 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1581 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1582 vcpu->last_guest_tsc = tsc_timestamp;
1585 * The interface expects us to write an even number signaling that the
1586 * update is finished. Since the guest won't see the intermediate
1587 * state, we just increase by 2 at the end.
1589 vcpu->hv_clock.version += 2;
1591 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1592 &guest_hv_clock, sizeof(guest_hv_clock))))
1595 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1596 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1598 if (vcpu->pvclock_set_guest_stopped_request) {
1599 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1600 vcpu->pvclock_set_guest_stopped_request = false;
1603 /* If the host uses TSC clocksource, then it is stable */
1604 if (use_master_clock)
1605 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1607 vcpu->hv_clock.flags = pvclock_flags;
1609 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1611 sizeof(vcpu->hv_clock));
1616 * kvmclock updates which are isolated to a given vcpu, such as
1617 * vcpu->cpu migration, should not allow system_timestamp from
1618 * the rest of the vcpus to remain static. Otherwise ntp frequency
1619 * correction applies to one vcpu's system_timestamp but not
1622 * So in those cases, request a kvmclock update for all vcpus.
1623 * We need to rate-limit these requests though, as they can
1624 * considerably slow guests that have a large number of vcpus.
1625 * The time for a remote vcpu to update its kvmclock is bound
1626 * by the delay we use to rate-limit the updates.
1629 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1631 static void kvmclock_update_fn(struct work_struct *work)
1634 struct delayed_work *dwork = to_delayed_work(work);
1635 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1636 kvmclock_update_work);
1637 struct kvm *kvm = container_of(ka, struct kvm, arch);
1638 struct kvm_vcpu *vcpu;
1640 kvm_for_each_vcpu(i, vcpu, kvm) {
1641 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1642 kvm_vcpu_kick(vcpu);
1646 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1648 struct kvm *kvm = v->kvm;
1650 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1651 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1652 KVMCLOCK_UPDATE_DELAY);
1655 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1657 static void kvmclock_sync_fn(struct work_struct *work)
1659 struct delayed_work *dwork = to_delayed_work(work);
1660 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1661 kvmclock_sync_work);
1662 struct kvm *kvm = container_of(ka, struct kvm, arch);
1664 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1665 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1666 KVMCLOCK_SYNC_PERIOD);
1669 static bool msr_mtrr_valid(unsigned msr)
1672 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1673 case MSR_MTRRfix64K_00000:
1674 case MSR_MTRRfix16K_80000:
1675 case MSR_MTRRfix16K_A0000:
1676 case MSR_MTRRfix4K_C0000:
1677 case MSR_MTRRfix4K_C8000:
1678 case MSR_MTRRfix4K_D0000:
1679 case MSR_MTRRfix4K_D8000:
1680 case MSR_MTRRfix4K_E0000:
1681 case MSR_MTRRfix4K_E8000:
1682 case MSR_MTRRfix4K_F0000:
1683 case MSR_MTRRfix4K_F8000:
1684 case MSR_MTRRdefType:
1685 case MSR_IA32_CR_PAT:
1693 static bool valid_pat_type(unsigned t)
1695 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1698 static bool valid_mtrr_type(unsigned t)
1700 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1703 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1707 if (!msr_mtrr_valid(msr))
1710 if (msr == MSR_IA32_CR_PAT) {
1711 for (i = 0; i < 8; i++)
1712 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1715 } else if (msr == MSR_MTRRdefType) {
1718 return valid_mtrr_type(data & 0xff);
1719 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1720 for (i = 0; i < 8 ; i++)
1721 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1726 /* variable MTRRs */
1727 return valid_mtrr_type(data & 0xff);
1730 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1732 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1734 if (!mtrr_valid(vcpu, msr, data))
1737 if (msr == MSR_MTRRdefType) {
1738 vcpu->arch.mtrr_state.def_type = data;
1739 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1740 } else if (msr == MSR_MTRRfix64K_00000)
1742 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1743 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1744 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1745 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1746 else if (msr == MSR_IA32_CR_PAT)
1747 vcpu->arch.pat = data;
1748 else { /* Variable MTRRs */
1749 int idx, is_mtrr_mask;
1752 idx = (msr - 0x200) / 2;
1753 is_mtrr_mask = msr - 0x200 - 2 * idx;
1756 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1759 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1763 kvm_mmu_reset_context(vcpu);
1767 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1769 u64 mcg_cap = vcpu->arch.mcg_cap;
1770 unsigned bank_num = mcg_cap & 0xff;
1773 case MSR_IA32_MCG_STATUS:
1774 vcpu->arch.mcg_status = data;
1776 case MSR_IA32_MCG_CTL:
1777 if (!(mcg_cap & MCG_CTL_P))
1779 if (data != 0 && data != ~(u64)0)
1781 vcpu->arch.mcg_ctl = data;
1784 if (msr >= MSR_IA32_MC0_CTL &&
1785 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1786 u32 offset = msr - MSR_IA32_MC0_CTL;
1787 /* only 0 or all 1s can be written to IA32_MCi_CTL
1788 * some Linux kernels though clear bit 10 in bank 4 to
1789 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1790 * this to avoid an uncatched #GP in the guest
1792 if ((offset & 0x3) == 0 &&
1793 data != 0 && (data | (1 << 10)) != ~(u64)0)
1795 vcpu->arch.mce_banks[offset] = data;
1803 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1805 struct kvm *kvm = vcpu->kvm;
1806 int lm = is_long_mode(vcpu);
1807 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1808 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1809 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1810 : kvm->arch.xen_hvm_config.blob_size_32;
1811 u32 page_num = data & ~PAGE_MASK;
1812 u64 page_addr = data & PAGE_MASK;
1817 if (page_num >= blob_size)
1820 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1825 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1834 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1836 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1839 static bool kvm_hv_msr_partition_wide(u32 msr)
1843 case HV_X64_MSR_GUEST_OS_ID:
1844 case HV_X64_MSR_HYPERCALL:
1845 case HV_X64_MSR_REFERENCE_TSC:
1846 case HV_X64_MSR_TIME_REF_COUNT:
1854 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1856 struct kvm *kvm = vcpu->kvm;
1859 case HV_X64_MSR_GUEST_OS_ID:
1860 kvm->arch.hv_guest_os_id = data;
1861 /* setting guest os id to zero disables hypercall page */
1862 if (!kvm->arch.hv_guest_os_id)
1863 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1865 case HV_X64_MSR_HYPERCALL: {
1870 /* if guest os id is not set hypercall should remain disabled */
1871 if (!kvm->arch.hv_guest_os_id)
1873 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1874 kvm->arch.hv_hypercall = data;
1877 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1878 addr = gfn_to_hva(kvm, gfn);
1879 if (kvm_is_error_hva(addr))
1881 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1882 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1883 if (__copy_to_user((void __user *)addr, instructions, 4))
1885 kvm->arch.hv_hypercall = data;
1886 mark_page_dirty(kvm, gfn);
1889 case HV_X64_MSR_REFERENCE_TSC: {
1891 HV_REFERENCE_TSC_PAGE tsc_ref;
1892 memset(&tsc_ref, 0, sizeof(tsc_ref));
1893 kvm->arch.hv_tsc_page = data;
1894 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1896 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1897 if (kvm_write_guest(kvm, data,
1898 &tsc_ref, sizeof(tsc_ref)))
1900 mark_page_dirty(kvm, gfn);
1904 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1905 "data 0x%llx\n", msr, data);
1911 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1914 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1918 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1919 vcpu->arch.hv_vapic = data;
1922 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1923 addr = gfn_to_hva(vcpu->kvm, gfn);
1924 if (kvm_is_error_hva(addr))
1926 if (__clear_user((void __user *)addr, PAGE_SIZE))
1928 vcpu->arch.hv_vapic = data;
1929 mark_page_dirty(vcpu->kvm, gfn);
1932 case HV_X64_MSR_EOI:
1933 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1934 case HV_X64_MSR_ICR:
1935 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1936 case HV_X64_MSR_TPR:
1937 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1939 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1940 "data 0x%llx\n", msr, data);
1947 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1949 gpa_t gpa = data & ~0x3f;
1951 /* Bits 2:5 are reserved, Should be zero */
1955 vcpu->arch.apf.msr_val = data;
1957 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1958 kvm_clear_async_pf_completion_queue(vcpu);
1959 kvm_async_pf_hash_reset(vcpu);
1963 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1967 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1968 kvm_async_pf_wakeup_all(vcpu);
1972 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1974 vcpu->arch.pv_time_enabled = false;
1977 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1981 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1984 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1985 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1986 vcpu->arch.st.accum_steal = delta;
1989 static void record_steal_time(struct kvm_vcpu *vcpu)
1991 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1994 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1995 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1998 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1999 vcpu->arch.st.steal.version += 2;
2000 vcpu->arch.st.accum_steal = 0;
2002 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2003 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2006 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2009 u32 msr = msr_info->index;
2010 u64 data = msr_info->data;
2013 case MSR_AMD64_NB_CFG:
2014 case MSR_IA32_UCODE_REV:
2015 case MSR_IA32_UCODE_WRITE:
2016 case MSR_VM_HSAVE_PA:
2017 case MSR_AMD64_PATCH_LOADER:
2018 case MSR_AMD64_BU_CFG2:
2022 return set_efer(vcpu, data);
2024 data &= ~(u64)0x40; /* ignore flush filter disable */
2025 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2026 data &= ~(u64)0x8; /* ignore TLB cache disable */
2028 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2033 case MSR_FAM10H_MMIO_CONF_BASE:
2035 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2040 case MSR_IA32_DEBUGCTLMSR:
2042 /* We support the non-activated case already */
2044 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2045 /* Values other than LBR and BTF are vendor-specific,
2046 thus reserved and should throw a #GP */
2049 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2052 case 0x200 ... 0x2ff:
2053 return set_msr_mtrr(vcpu, msr, data);
2054 case MSR_IA32_APICBASE:
2055 return kvm_set_apic_base(vcpu, msr_info);
2056 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2057 return kvm_x2apic_msr_write(vcpu, msr, data);
2058 case MSR_IA32_TSCDEADLINE:
2059 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2061 case MSR_IA32_TSC_ADJUST:
2062 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2063 if (!msr_info->host_initiated) {
2064 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2065 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2067 vcpu->arch.ia32_tsc_adjust_msr = data;
2070 case MSR_IA32_MISC_ENABLE:
2071 vcpu->arch.ia32_misc_enable_msr = data;
2073 case MSR_KVM_WALL_CLOCK_NEW:
2074 case MSR_KVM_WALL_CLOCK:
2075 vcpu->kvm->arch.wall_clock = data;
2076 kvm_write_wall_clock(vcpu->kvm, data);
2078 case MSR_KVM_SYSTEM_TIME_NEW:
2079 case MSR_KVM_SYSTEM_TIME: {
2081 kvmclock_reset(vcpu);
2083 vcpu->arch.time = data;
2084 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2086 /* we verify if the enable bit is set... */
2090 gpa_offset = data & ~(PAGE_MASK | 1);
2092 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2093 &vcpu->arch.pv_time, data & ~1ULL,
2094 sizeof(struct pvclock_vcpu_time_info)))
2095 vcpu->arch.pv_time_enabled = false;
2097 vcpu->arch.pv_time_enabled = true;
2101 case MSR_KVM_ASYNC_PF_EN:
2102 if (kvm_pv_enable_async_pf(vcpu, data))
2105 case MSR_KVM_STEAL_TIME:
2107 if (unlikely(!sched_info_on()))
2110 if (data & KVM_STEAL_RESERVED_MASK)
2113 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2114 data & KVM_STEAL_VALID_BITS,
2115 sizeof(struct kvm_steal_time)))
2118 vcpu->arch.st.msr_val = data;
2120 if (!(data & KVM_MSR_ENABLED))
2123 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2126 accumulate_steal_time(vcpu);
2129 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2132 case MSR_KVM_PV_EOI_EN:
2133 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2137 case MSR_IA32_MCG_CTL:
2138 case MSR_IA32_MCG_STATUS:
2139 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2140 return set_msr_mce(vcpu, msr, data);
2142 /* Performance counters are not protected by a CPUID bit,
2143 * so we should check all of them in the generic path for the sake of
2144 * cross vendor migration.
2145 * Writing a zero into the event select MSRs disables them,
2146 * which we perfectly emulate ;-). Any other value should be at least
2147 * reported, some guests depend on them.
2149 case MSR_K7_EVNTSEL0:
2150 case MSR_K7_EVNTSEL1:
2151 case MSR_K7_EVNTSEL2:
2152 case MSR_K7_EVNTSEL3:
2154 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2155 "0x%x data 0x%llx\n", msr, data);
2157 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2158 * so we ignore writes to make it happy.
2160 case MSR_K7_PERFCTR0:
2161 case MSR_K7_PERFCTR1:
2162 case MSR_K7_PERFCTR2:
2163 case MSR_K7_PERFCTR3:
2164 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2165 "0x%x data 0x%llx\n", msr, data);
2167 case MSR_P6_PERFCTR0:
2168 case MSR_P6_PERFCTR1:
2170 case MSR_P6_EVNTSEL0:
2171 case MSR_P6_EVNTSEL1:
2172 if (kvm_pmu_msr(vcpu, msr))
2173 return kvm_pmu_set_msr(vcpu, msr_info);
2175 if (pr || data != 0)
2176 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2177 "0x%x data 0x%llx\n", msr, data);
2179 case MSR_K7_CLK_CTL:
2181 * Ignore all writes to this no longer documented MSR.
2182 * Writes are only relevant for old K7 processors,
2183 * all pre-dating SVM, but a recommended workaround from
2184 * AMD for these chips. It is possible to specify the
2185 * affected processor models on the command line, hence
2186 * the need to ignore the workaround.
2189 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2190 if (kvm_hv_msr_partition_wide(msr)) {
2192 mutex_lock(&vcpu->kvm->lock);
2193 r = set_msr_hyperv_pw(vcpu, msr, data);
2194 mutex_unlock(&vcpu->kvm->lock);
2197 return set_msr_hyperv(vcpu, msr, data);
2199 case MSR_IA32_BBL_CR_CTL3:
2200 /* Drop writes to this legacy MSR -- see rdmsr
2201 * counterpart for further detail.
2203 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2205 case MSR_AMD64_OSVW_ID_LENGTH:
2206 if (!guest_cpuid_has_osvw(vcpu))
2208 vcpu->arch.osvw.length = data;
2210 case MSR_AMD64_OSVW_STATUS:
2211 if (!guest_cpuid_has_osvw(vcpu))
2213 vcpu->arch.osvw.status = data;
2216 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2217 return xen_hvm_config(vcpu, data);
2218 if (kvm_pmu_msr(vcpu, msr))
2219 return kvm_pmu_set_msr(vcpu, msr_info);
2221 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2225 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2232 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2236 * Reads an msr value (of 'msr_index') into 'pdata'.
2237 * Returns 0 on success, non-0 otherwise.
2238 * Assumes vcpu_load() was already called.
2240 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2242 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2245 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2247 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2249 if (!msr_mtrr_valid(msr))
2252 if (msr == MSR_MTRRdefType)
2253 *pdata = vcpu->arch.mtrr_state.def_type +
2254 (vcpu->arch.mtrr_state.enabled << 10);
2255 else if (msr == MSR_MTRRfix64K_00000)
2257 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2258 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2259 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2260 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2261 else if (msr == MSR_IA32_CR_PAT)
2262 *pdata = vcpu->arch.pat;
2263 else { /* Variable MTRRs */
2264 int idx, is_mtrr_mask;
2267 idx = (msr - 0x200) / 2;
2268 is_mtrr_mask = msr - 0x200 - 2 * idx;
2271 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2274 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2281 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2284 u64 mcg_cap = vcpu->arch.mcg_cap;
2285 unsigned bank_num = mcg_cap & 0xff;
2288 case MSR_IA32_P5_MC_ADDR:
2289 case MSR_IA32_P5_MC_TYPE:
2292 case MSR_IA32_MCG_CAP:
2293 data = vcpu->arch.mcg_cap;
2295 case MSR_IA32_MCG_CTL:
2296 if (!(mcg_cap & MCG_CTL_P))
2298 data = vcpu->arch.mcg_ctl;
2300 case MSR_IA32_MCG_STATUS:
2301 data = vcpu->arch.mcg_status;
2304 if (msr >= MSR_IA32_MC0_CTL &&
2305 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2306 u32 offset = msr - MSR_IA32_MC0_CTL;
2307 data = vcpu->arch.mce_banks[offset];
2316 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2319 struct kvm *kvm = vcpu->kvm;
2322 case HV_X64_MSR_GUEST_OS_ID:
2323 data = kvm->arch.hv_guest_os_id;
2325 case HV_X64_MSR_HYPERCALL:
2326 data = kvm->arch.hv_hypercall;
2328 case HV_X64_MSR_TIME_REF_COUNT: {
2330 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2333 case HV_X64_MSR_REFERENCE_TSC:
2334 data = kvm->arch.hv_tsc_page;
2337 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2345 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2350 case HV_X64_MSR_VP_INDEX: {
2353 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2361 case HV_X64_MSR_EOI:
2362 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2363 case HV_X64_MSR_ICR:
2364 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2365 case HV_X64_MSR_TPR:
2366 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2367 case HV_X64_MSR_APIC_ASSIST_PAGE:
2368 data = vcpu->arch.hv_vapic;
2371 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2378 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2383 case MSR_IA32_PLATFORM_ID:
2384 case MSR_IA32_EBL_CR_POWERON:
2385 case MSR_IA32_DEBUGCTLMSR:
2386 case MSR_IA32_LASTBRANCHFROMIP:
2387 case MSR_IA32_LASTBRANCHTOIP:
2388 case MSR_IA32_LASTINTFROMIP:
2389 case MSR_IA32_LASTINTTOIP:
2392 case MSR_VM_HSAVE_PA:
2393 case MSR_K7_EVNTSEL0:
2394 case MSR_K7_PERFCTR0:
2395 case MSR_K8_INT_PENDING_MSG:
2396 case MSR_AMD64_NB_CFG:
2397 case MSR_FAM10H_MMIO_CONF_BASE:
2398 case MSR_AMD64_BU_CFG2:
2401 case MSR_P6_PERFCTR0:
2402 case MSR_P6_PERFCTR1:
2403 case MSR_P6_EVNTSEL0:
2404 case MSR_P6_EVNTSEL1:
2405 if (kvm_pmu_msr(vcpu, msr))
2406 return kvm_pmu_get_msr(vcpu, msr, pdata);
2409 case MSR_IA32_UCODE_REV:
2410 data = 0x100000000ULL;
2413 data = 0x500 | KVM_NR_VAR_MTRR;
2415 case 0x200 ... 0x2ff:
2416 return get_msr_mtrr(vcpu, msr, pdata);
2417 case 0xcd: /* fsb frequency */
2421 * MSR_EBC_FREQUENCY_ID
2422 * Conservative value valid for even the basic CPU models.
2423 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2424 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2425 * and 266MHz for model 3, or 4. Set Core Clock
2426 * Frequency to System Bus Frequency Ratio to 1 (bits
2427 * 31:24) even though these are only valid for CPU
2428 * models > 2, however guests may end up dividing or
2429 * multiplying by zero otherwise.
2431 case MSR_EBC_FREQUENCY_ID:
2434 case MSR_IA32_APICBASE:
2435 data = kvm_get_apic_base(vcpu);
2437 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2438 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2440 case MSR_IA32_TSCDEADLINE:
2441 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2443 case MSR_IA32_TSC_ADJUST:
2444 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2446 case MSR_IA32_MISC_ENABLE:
2447 data = vcpu->arch.ia32_misc_enable_msr;
2449 case MSR_IA32_PERF_STATUS:
2450 /* TSC increment by tick */
2452 /* CPU multiplier */
2453 data |= (((uint64_t)4ULL) << 40);
2456 data = vcpu->arch.efer;
2458 case MSR_KVM_WALL_CLOCK:
2459 case MSR_KVM_WALL_CLOCK_NEW:
2460 data = vcpu->kvm->arch.wall_clock;
2462 case MSR_KVM_SYSTEM_TIME:
2463 case MSR_KVM_SYSTEM_TIME_NEW:
2464 data = vcpu->arch.time;
2466 case MSR_KVM_ASYNC_PF_EN:
2467 data = vcpu->arch.apf.msr_val;
2469 case MSR_KVM_STEAL_TIME:
2470 data = vcpu->arch.st.msr_val;
2472 case MSR_KVM_PV_EOI_EN:
2473 data = vcpu->arch.pv_eoi.msr_val;
2475 case MSR_IA32_P5_MC_ADDR:
2476 case MSR_IA32_P5_MC_TYPE:
2477 case MSR_IA32_MCG_CAP:
2478 case MSR_IA32_MCG_CTL:
2479 case MSR_IA32_MCG_STATUS:
2480 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2481 return get_msr_mce(vcpu, msr, pdata);
2482 case MSR_K7_CLK_CTL:
2484 * Provide expected ramp-up count for K7. All other
2485 * are set to zero, indicating minimum divisors for
2488 * This prevents guest kernels on AMD host with CPU
2489 * type 6, model 8 and higher from exploding due to
2490 * the rdmsr failing.
2494 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2495 if (kvm_hv_msr_partition_wide(msr)) {
2497 mutex_lock(&vcpu->kvm->lock);
2498 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2499 mutex_unlock(&vcpu->kvm->lock);
2502 return get_msr_hyperv(vcpu, msr, pdata);
2504 case MSR_IA32_BBL_CR_CTL3:
2505 /* This legacy MSR exists but isn't fully documented in current
2506 * silicon. It is however accessed by winxp in very narrow
2507 * scenarios where it sets bit #19, itself documented as
2508 * a "reserved" bit. Best effort attempt to source coherent
2509 * read data here should the balance of the register be
2510 * interpreted by the guest:
2512 * L2 cache control register 3: 64GB range, 256KB size,
2513 * enabled, latency 0x1, configured
2517 case MSR_AMD64_OSVW_ID_LENGTH:
2518 if (!guest_cpuid_has_osvw(vcpu))
2520 data = vcpu->arch.osvw.length;
2522 case MSR_AMD64_OSVW_STATUS:
2523 if (!guest_cpuid_has_osvw(vcpu))
2525 data = vcpu->arch.osvw.status;
2528 if (kvm_pmu_msr(vcpu, msr))
2529 return kvm_pmu_get_msr(vcpu, msr, pdata);
2531 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2534 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2542 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2545 * Read or write a bunch of msrs. All parameters are kernel addresses.
2547 * @return number of msrs set successfully.
2549 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2550 struct kvm_msr_entry *entries,
2551 int (*do_msr)(struct kvm_vcpu *vcpu,
2552 unsigned index, u64 *data))
2556 idx = srcu_read_lock(&vcpu->kvm->srcu);
2557 for (i = 0; i < msrs->nmsrs; ++i)
2558 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2566 * Read or write a bunch of msrs. Parameters are user addresses.
2568 * @return number of msrs set successfully.
2570 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2571 int (*do_msr)(struct kvm_vcpu *vcpu,
2572 unsigned index, u64 *data),
2575 struct kvm_msrs msrs;
2576 struct kvm_msr_entry *entries;
2581 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2585 if (msrs.nmsrs >= MAX_IO_MSRS)
2588 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2589 entries = memdup_user(user_msrs->entries, size);
2590 if (IS_ERR(entries)) {
2591 r = PTR_ERR(entries);
2595 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2600 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2611 int kvm_dev_ioctl_check_extension(long ext)
2616 case KVM_CAP_IRQCHIP:
2618 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2619 case KVM_CAP_SET_TSS_ADDR:
2620 case KVM_CAP_EXT_CPUID:
2621 case KVM_CAP_EXT_EMUL_CPUID:
2622 case KVM_CAP_CLOCKSOURCE:
2624 case KVM_CAP_NOP_IO_DELAY:
2625 case KVM_CAP_MP_STATE:
2626 case KVM_CAP_SYNC_MMU:
2627 case KVM_CAP_USER_NMI:
2628 case KVM_CAP_REINJECT_CONTROL:
2629 case KVM_CAP_IRQ_INJECT_STATUS:
2631 case KVM_CAP_IOEVENTFD:
2632 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2634 case KVM_CAP_PIT_STATE2:
2635 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2636 case KVM_CAP_XEN_HVM:
2637 case KVM_CAP_ADJUST_CLOCK:
2638 case KVM_CAP_VCPU_EVENTS:
2639 case KVM_CAP_HYPERV:
2640 case KVM_CAP_HYPERV_VAPIC:
2641 case KVM_CAP_HYPERV_SPIN:
2642 case KVM_CAP_PCI_SEGMENT:
2643 case KVM_CAP_DEBUGREGS:
2644 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2646 case KVM_CAP_ASYNC_PF:
2647 case KVM_CAP_GET_TSC_KHZ:
2648 case KVM_CAP_KVMCLOCK_CTRL:
2649 case KVM_CAP_READONLY_MEM:
2650 case KVM_CAP_HYPERV_TIME:
2651 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2652 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2653 case KVM_CAP_ASSIGN_DEV_IRQ:
2654 case KVM_CAP_PCI_2_3:
2658 case KVM_CAP_COALESCED_MMIO:
2659 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2662 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2664 case KVM_CAP_NR_VCPUS:
2665 r = KVM_SOFT_MAX_VCPUS;
2667 case KVM_CAP_MAX_VCPUS:
2670 case KVM_CAP_NR_MEMSLOTS:
2671 r = KVM_USER_MEM_SLOTS;
2673 case KVM_CAP_PV_MMU: /* obsolete */
2676 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2678 r = iommu_present(&pci_bus_type);
2682 r = KVM_MAX_MCE_BANKS;
2687 case KVM_CAP_TSC_CONTROL:
2688 r = kvm_has_tsc_control;
2690 case KVM_CAP_TSC_DEADLINE_TIMER:
2691 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2701 long kvm_arch_dev_ioctl(struct file *filp,
2702 unsigned int ioctl, unsigned long arg)
2704 void __user *argp = (void __user *)arg;
2708 case KVM_GET_MSR_INDEX_LIST: {
2709 struct kvm_msr_list __user *user_msr_list = argp;
2710 struct kvm_msr_list msr_list;
2714 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2717 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2718 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2721 if (n < msr_list.nmsrs)
2724 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2725 num_msrs_to_save * sizeof(u32)))
2727 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2729 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2734 case KVM_GET_SUPPORTED_CPUID:
2735 case KVM_GET_EMULATED_CPUID: {
2736 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737 struct kvm_cpuid2 cpuid;
2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2743 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2749 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2754 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2757 mce_cap = KVM_MCE_CAP_SUPPORTED;
2759 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2771 static void wbinvd_ipi(void *garbage)
2776 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2778 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2781 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2783 /* Address WBINVD may be executed by guest */
2784 if (need_emulate_wbinvd(vcpu)) {
2785 if (kvm_x86_ops->has_wbinvd_exit())
2786 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2787 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2788 smp_call_function_single(vcpu->cpu,
2789 wbinvd_ipi, NULL, 1);
2792 kvm_x86_ops->vcpu_load(vcpu, cpu);
2794 /* Apply any externally detected TSC adjustments (due to suspend) */
2795 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2796 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2797 vcpu->arch.tsc_offset_adjustment = 0;
2798 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2801 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2802 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2803 native_read_tsc() - vcpu->arch.last_host_tsc;
2805 mark_tsc_unstable("KVM discovered backwards TSC");
2806 if (check_tsc_unstable()) {
2807 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2808 vcpu->arch.last_guest_tsc);
2809 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2810 vcpu->arch.tsc_catchup = 1;
2813 * On a host with synchronized TSC, there is no need to update
2814 * kvmclock on vcpu->cpu migration
2816 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2817 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2818 if (vcpu->cpu != cpu)
2819 kvm_migrate_timers(vcpu);
2823 accumulate_steal_time(vcpu);
2824 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2827 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2829 kvm_x86_ops->vcpu_put(vcpu);
2830 kvm_put_guest_fpu(vcpu);
2831 vcpu->arch.last_host_tsc = native_read_tsc();
2834 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2835 struct kvm_lapic_state *s)
2837 kvm_x86_ops->sync_pir_to_irr(vcpu);
2838 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2843 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2844 struct kvm_lapic_state *s)
2846 kvm_apic_post_state_restore(vcpu, s);
2847 update_cr8_intercept(vcpu);
2852 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2853 struct kvm_interrupt *irq)
2855 if (irq->irq >= KVM_NR_INTERRUPTS)
2857 if (irqchip_in_kernel(vcpu->kvm))
2860 kvm_queue_interrupt(vcpu, irq->irq, false);
2861 kvm_make_request(KVM_REQ_EVENT, vcpu);
2866 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2868 kvm_inject_nmi(vcpu);
2873 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2874 struct kvm_tpr_access_ctl *tac)
2878 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2882 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2886 unsigned bank_num = mcg_cap & 0xff, bank;
2889 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2891 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2894 vcpu->arch.mcg_cap = mcg_cap;
2895 /* Init IA32_MCG_CTL to all 1s */
2896 if (mcg_cap & MCG_CTL_P)
2897 vcpu->arch.mcg_ctl = ~(u64)0;
2898 /* Init IA32_MCi_CTL to all 1s */
2899 for (bank = 0; bank < bank_num; bank++)
2900 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2905 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2906 struct kvm_x86_mce *mce)
2908 u64 mcg_cap = vcpu->arch.mcg_cap;
2909 unsigned bank_num = mcg_cap & 0xff;
2910 u64 *banks = vcpu->arch.mce_banks;
2912 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2915 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2916 * reporting is disabled
2918 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2919 vcpu->arch.mcg_ctl != ~(u64)0)
2921 banks += 4 * mce->bank;
2923 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2924 * reporting is disabled for the bank
2926 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2928 if (mce->status & MCI_STATUS_UC) {
2929 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2930 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2931 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2934 if (banks[1] & MCI_STATUS_VAL)
2935 mce->status |= MCI_STATUS_OVER;
2936 banks[2] = mce->addr;
2937 banks[3] = mce->misc;
2938 vcpu->arch.mcg_status = mce->mcg_status;
2939 banks[1] = mce->status;
2940 kvm_queue_exception(vcpu, MC_VECTOR);
2941 } else if (!(banks[1] & MCI_STATUS_VAL)
2942 || !(banks[1] & MCI_STATUS_UC)) {
2943 if (banks[1] & MCI_STATUS_VAL)
2944 mce->status |= MCI_STATUS_OVER;
2945 banks[2] = mce->addr;
2946 banks[3] = mce->misc;
2947 banks[1] = mce->status;
2949 banks[1] |= MCI_STATUS_OVER;
2953 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2954 struct kvm_vcpu_events *events)
2957 events->exception.injected =
2958 vcpu->arch.exception.pending &&
2959 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2960 events->exception.nr = vcpu->arch.exception.nr;
2961 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2962 events->exception.pad = 0;
2963 events->exception.error_code = vcpu->arch.exception.error_code;
2965 events->interrupt.injected =
2966 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2967 events->interrupt.nr = vcpu->arch.interrupt.nr;
2968 events->interrupt.soft = 0;
2969 events->interrupt.shadow =
2970 kvm_x86_ops->get_interrupt_shadow(vcpu,
2971 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2973 events->nmi.injected = vcpu->arch.nmi_injected;
2974 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2975 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2976 events->nmi.pad = 0;
2978 events->sipi_vector = 0; /* never valid when reporting to user space */
2980 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2981 | KVM_VCPUEVENT_VALID_SHADOW);
2982 memset(&events->reserved, 0, sizeof(events->reserved));
2985 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2986 struct kvm_vcpu_events *events)
2988 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2989 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2990 | KVM_VCPUEVENT_VALID_SHADOW))
2994 vcpu->arch.exception.pending = events->exception.injected;
2995 vcpu->arch.exception.nr = events->exception.nr;
2996 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2997 vcpu->arch.exception.error_code = events->exception.error_code;
2999 vcpu->arch.interrupt.pending = events->interrupt.injected;
3000 vcpu->arch.interrupt.nr = events->interrupt.nr;
3001 vcpu->arch.interrupt.soft = events->interrupt.soft;
3002 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3003 kvm_x86_ops->set_interrupt_shadow(vcpu,
3004 events->interrupt.shadow);
3006 vcpu->arch.nmi_injected = events->nmi.injected;
3007 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3008 vcpu->arch.nmi_pending = events->nmi.pending;
3009 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3011 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3012 kvm_vcpu_has_lapic(vcpu))
3013 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3015 kvm_make_request(KVM_REQ_EVENT, vcpu);
3020 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3021 struct kvm_debugregs *dbgregs)
3025 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3026 _kvm_get_dr(vcpu, 6, &val);
3028 dbgregs->dr7 = vcpu->arch.dr7;
3030 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3033 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3034 struct kvm_debugregs *dbgregs)
3039 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3040 vcpu->arch.dr6 = dbgregs->dr6;
3041 kvm_update_dr6(vcpu);
3042 vcpu->arch.dr7 = dbgregs->dr7;
3043 kvm_update_dr7(vcpu);
3048 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3049 struct kvm_xsave *guest_xsave)
3051 if (cpu_has_xsave) {
3052 memcpy(guest_xsave->region,
3053 &vcpu->arch.guest_fpu.state->xsave,
3054 vcpu->arch.guest_xstate_size);
3055 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3056 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3058 memcpy(guest_xsave->region,
3059 &vcpu->arch.guest_fpu.state->fxsave,
3060 sizeof(struct i387_fxsave_struct));
3061 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3066 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3067 struct kvm_xsave *guest_xsave)
3070 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3072 if (cpu_has_xsave) {
3074 * Here we allow setting states that are not present in
3075 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3076 * with old userspace.
3078 if (xstate_bv & ~kvm_supported_xcr0())
3080 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3081 guest_xsave->region, vcpu->arch.guest_xstate_size);
3083 if (xstate_bv & ~XSTATE_FPSSE)
3085 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3086 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3091 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3092 struct kvm_xcrs *guest_xcrs)
3094 if (!cpu_has_xsave) {
3095 guest_xcrs->nr_xcrs = 0;
3099 guest_xcrs->nr_xcrs = 1;
3100 guest_xcrs->flags = 0;
3101 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3102 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3105 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3106 struct kvm_xcrs *guest_xcrs)
3113 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3116 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3117 /* Only support XCR0 currently */
3118 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3119 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3120 guest_xcrs->xcrs[i].value);
3129 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3130 * stopped by the hypervisor. This function will be called from the host only.
3131 * EINVAL is returned when the host attempts to set the flag for a guest that
3132 * does not support pv clocks.
3134 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3136 if (!vcpu->arch.pv_time_enabled)
3138 vcpu->arch.pvclock_set_guest_stopped_request = true;
3139 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3143 long kvm_arch_vcpu_ioctl(struct file *filp,
3144 unsigned int ioctl, unsigned long arg)
3146 struct kvm_vcpu *vcpu = filp->private_data;
3147 void __user *argp = (void __user *)arg;
3150 struct kvm_lapic_state *lapic;
3151 struct kvm_xsave *xsave;
3152 struct kvm_xcrs *xcrs;
3158 case KVM_GET_LAPIC: {
3160 if (!vcpu->arch.apic)
3162 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3167 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3171 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3176 case KVM_SET_LAPIC: {
3178 if (!vcpu->arch.apic)
3180 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3181 if (IS_ERR(u.lapic))
3182 return PTR_ERR(u.lapic);
3184 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3187 case KVM_INTERRUPT: {
3188 struct kvm_interrupt irq;
3191 if (copy_from_user(&irq, argp, sizeof irq))
3193 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3197 r = kvm_vcpu_ioctl_nmi(vcpu);
3200 case KVM_SET_CPUID: {
3201 struct kvm_cpuid __user *cpuid_arg = argp;
3202 struct kvm_cpuid cpuid;
3205 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3207 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3210 case KVM_SET_CPUID2: {
3211 struct kvm_cpuid2 __user *cpuid_arg = argp;
3212 struct kvm_cpuid2 cpuid;
3215 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3217 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3218 cpuid_arg->entries);
3221 case KVM_GET_CPUID2: {
3222 struct kvm_cpuid2 __user *cpuid_arg = argp;
3223 struct kvm_cpuid2 cpuid;
3226 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3228 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3229 cpuid_arg->entries);
3233 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3239 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3242 r = msr_io(vcpu, argp, do_set_msr, 0);
3244 case KVM_TPR_ACCESS_REPORTING: {
3245 struct kvm_tpr_access_ctl tac;
3248 if (copy_from_user(&tac, argp, sizeof tac))
3250 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3254 if (copy_to_user(argp, &tac, sizeof tac))
3259 case KVM_SET_VAPIC_ADDR: {
3260 struct kvm_vapic_addr va;
3263 if (!irqchip_in_kernel(vcpu->kvm))
3266 if (copy_from_user(&va, argp, sizeof va))
3268 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3271 case KVM_X86_SETUP_MCE: {
3275 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3277 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3280 case KVM_X86_SET_MCE: {
3281 struct kvm_x86_mce mce;
3284 if (copy_from_user(&mce, argp, sizeof mce))
3286 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3289 case KVM_GET_VCPU_EVENTS: {
3290 struct kvm_vcpu_events events;
3292 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3295 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3300 case KVM_SET_VCPU_EVENTS: {
3301 struct kvm_vcpu_events events;
3304 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3307 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3310 case KVM_GET_DEBUGREGS: {
3311 struct kvm_debugregs dbgregs;
3313 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3316 if (copy_to_user(argp, &dbgregs,
3317 sizeof(struct kvm_debugregs)))
3322 case KVM_SET_DEBUGREGS: {
3323 struct kvm_debugregs dbgregs;
3326 if (copy_from_user(&dbgregs, argp,
3327 sizeof(struct kvm_debugregs)))
3330 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3333 case KVM_GET_XSAVE: {
3334 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3339 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3342 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3347 case KVM_SET_XSAVE: {
3348 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3349 if (IS_ERR(u.xsave))
3350 return PTR_ERR(u.xsave);
3352 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3355 case KVM_GET_XCRS: {
3356 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3361 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3364 if (copy_to_user(argp, u.xcrs,
3365 sizeof(struct kvm_xcrs)))
3370 case KVM_SET_XCRS: {
3371 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3373 return PTR_ERR(u.xcrs);
3375 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3378 case KVM_SET_TSC_KHZ: {
3382 user_tsc_khz = (u32)arg;
3384 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3387 if (user_tsc_khz == 0)
3388 user_tsc_khz = tsc_khz;
3390 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3395 case KVM_GET_TSC_KHZ: {
3396 r = vcpu->arch.virtual_tsc_khz;
3399 case KVM_KVMCLOCK_CTRL: {
3400 r = kvm_set_guest_paused(vcpu);
3411 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3413 return VM_FAULT_SIGBUS;
3416 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3420 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3422 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3426 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3429 kvm->arch.ept_identity_map_addr = ident_addr;
3433 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3434 u32 kvm_nr_mmu_pages)
3436 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3439 mutex_lock(&kvm->slots_lock);
3441 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3442 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3444 mutex_unlock(&kvm->slots_lock);
3448 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3450 return kvm->arch.n_max_mmu_pages;
3453 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3458 switch (chip->chip_id) {
3459 case KVM_IRQCHIP_PIC_MASTER:
3460 memcpy(&chip->chip.pic,
3461 &pic_irqchip(kvm)->pics[0],
3462 sizeof(struct kvm_pic_state));
3464 case KVM_IRQCHIP_PIC_SLAVE:
3465 memcpy(&chip->chip.pic,
3466 &pic_irqchip(kvm)->pics[1],
3467 sizeof(struct kvm_pic_state));
3469 case KVM_IRQCHIP_IOAPIC:
3470 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3479 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3484 switch (chip->chip_id) {
3485 case KVM_IRQCHIP_PIC_MASTER:
3486 spin_lock(&pic_irqchip(kvm)->lock);
3487 memcpy(&pic_irqchip(kvm)->pics[0],
3489 sizeof(struct kvm_pic_state));
3490 spin_unlock(&pic_irqchip(kvm)->lock);
3492 case KVM_IRQCHIP_PIC_SLAVE:
3493 spin_lock(&pic_irqchip(kvm)->lock);
3494 memcpy(&pic_irqchip(kvm)->pics[1],
3496 sizeof(struct kvm_pic_state));
3497 spin_unlock(&pic_irqchip(kvm)->lock);
3499 case KVM_IRQCHIP_IOAPIC:
3500 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3506 kvm_pic_update_irq(pic_irqchip(kvm));
3510 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3514 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3515 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3516 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3520 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3524 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3525 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3526 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3527 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3531 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3535 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3536 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3537 sizeof(ps->channels));
3538 ps->flags = kvm->arch.vpit->pit_state.flags;
3539 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3540 memset(&ps->reserved, 0, sizeof(ps->reserved));
3544 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3546 int r = 0, start = 0;
3547 u32 prev_legacy, cur_legacy;
3548 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3549 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3550 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3551 if (!prev_legacy && cur_legacy)
3553 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3554 sizeof(kvm->arch.vpit->pit_state.channels));
3555 kvm->arch.vpit->pit_state.flags = ps->flags;
3556 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3557 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3561 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3562 struct kvm_reinject_control *control)
3564 if (!kvm->arch.vpit)
3566 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3567 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3568 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3573 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3574 * @kvm: kvm instance
3575 * @log: slot id and address to which we copy the log
3577 * We need to keep it in mind that VCPU threads can write to the bitmap
3578 * concurrently. So, to avoid losing data, we keep the following order for
3581 * 1. Take a snapshot of the bit and clear it if needed.
3582 * 2. Write protect the corresponding page.
3583 * 3. Flush TLB's if needed.
3584 * 4. Copy the snapshot to the userspace.
3586 * Between 2 and 3, the guest may write to the page using the remaining TLB
3587 * entry. This is not a problem because the page will be reported dirty at
3588 * step 4 using the snapshot taken before and step 3 ensures that successive
3589 * writes will be logged for the next call.
3591 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3594 struct kvm_memory_slot *memslot;
3596 unsigned long *dirty_bitmap;
3597 unsigned long *dirty_bitmap_buffer;
3598 bool is_dirty = false;
3600 mutex_lock(&kvm->slots_lock);
3603 if (log->slot >= KVM_USER_MEM_SLOTS)
3606 memslot = id_to_memslot(kvm->memslots, log->slot);
3608 dirty_bitmap = memslot->dirty_bitmap;
3613 n = kvm_dirty_bitmap_bytes(memslot);
3615 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3616 memset(dirty_bitmap_buffer, 0, n);
3618 spin_lock(&kvm->mmu_lock);
3620 for (i = 0; i < n / sizeof(long); i++) {
3624 if (!dirty_bitmap[i])
3629 mask = xchg(&dirty_bitmap[i], 0);
3630 dirty_bitmap_buffer[i] = mask;
3632 offset = i * BITS_PER_LONG;
3633 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3636 kvm_flush_remote_tlbs(kvm);
3638 spin_unlock(&kvm->mmu_lock);
3641 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3646 mutex_unlock(&kvm->slots_lock);
3650 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3653 if (!irqchip_in_kernel(kvm))
3656 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3657 irq_event->irq, irq_event->level,
3662 long kvm_arch_vm_ioctl(struct file *filp,
3663 unsigned int ioctl, unsigned long arg)
3665 struct kvm *kvm = filp->private_data;
3666 void __user *argp = (void __user *)arg;
3669 * This union makes it completely explicit to gcc-3.x
3670 * that these two variables' stack usage should be
3671 * combined, not added together.
3674 struct kvm_pit_state ps;
3675 struct kvm_pit_state2 ps2;
3676 struct kvm_pit_config pit_config;
3680 case KVM_SET_TSS_ADDR:
3681 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3683 case KVM_SET_IDENTITY_MAP_ADDR: {
3687 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3689 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3692 case KVM_SET_NR_MMU_PAGES:
3693 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3695 case KVM_GET_NR_MMU_PAGES:
3696 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3698 case KVM_CREATE_IRQCHIP: {
3699 struct kvm_pic *vpic;
3701 mutex_lock(&kvm->lock);
3704 goto create_irqchip_unlock;
3706 if (atomic_read(&kvm->online_vcpus))
3707 goto create_irqchip_unlock;
3709 vpic = kvm_create_pic(kvm);
3711 r = kvm_ioapic_init(kvm);
3713 mutex_lock(&kvm->slots_lock);
3714 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3716 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3718 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3720 mutex_unlock(&kvm->slots_lock);
3722 goto create_irqchip_unlock;
3725 goto create_irqchip_unlock;
3727 kvm->arch.vpic = vpic;
3729 r = kvm_setup_default_irq_routing(kvm);
3731 mutex_lock(&kvm->slots_lock);
3732 mutex_lock(&kvm->irq_lock);
3733 kvm_ioapic_destroy(kvm);
3734 kvm_destroy_pic(kvm);
3735 mutex_unlock(&kvm->irq_lock);
3736 mutex_unlock(&kvm->slots_lock);
3738 create_irqchip_unlock:
3739 mutex_unlock(&kvm->lock);
3742 case KVM_CREATE_PIT:
3743 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3745 case KVM_CREATE_PIT2:
3747 if (copy_from_user(&u.pit_config, argp,
3748 sizeof(struct kvm_pit_config)))
3751 mutex_lock(&kvm->slots_lock);
3754 goto create_pit_unlock;
3756 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3760 mutex_unlock(&kvm->slots_lock);
3762 case KVM_GET_IRQCHIP: {
3763 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3764 struct kvm_irqchip *chip;
3766 chip = memdup_user(argp, sizeof(*chip));
3773 if (!irqchip_in_kernel(kvm))
3774 goto get_irqchip_out;
3775 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3777 goto get_irqchip_out;
3779 if (copy_to_user(argp, chip, sizeof *chip))
3780 goto get_irqchip_out;
3786 case KVM_SET_IRQCHIP: {
3787 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3788 struct kvm_irqchip *chip;
3790 chip = memdup_user(argp, sizeof(*chip));
3797 if (!irqchip_in_kernel(kvm))
3798 goto set_irqchip_out;
3799 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3801 goto set_irqchip_out;
3809 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3812 if (!kvm->arch.vpit)
3814 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3818 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3825 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3828 if (!kvm->arch.vpit)
3830 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3833 case KVM_GET_PIT2: {
3835 if (!kvm->arch.vpit)
3837 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3841 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3846 case KVM_SET_PIT2: {
3848 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3851 if (!kvm->arch.vpit)
3853 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3856 case KVM_REINJECT_CONTROL: {
3857 struct kvm_reinject_control control;
3859 if (copy_from_user(&control, argp, sizeof(control)))
3861 r = kvm_vm_ioctl_reinject(kvm, &control);
3864 case KVM_XEN_HVM_CONFIG: {
3866 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3867 sizeof(struct kvm_xen_hvm_config)))
3870 if (kvm->arch.xen_hvm_config.flags)
3875 case KVM_SET_CLOCK: {
3876 struct kvm_clock_data user_ns;
3881 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3889 local_irq_disable();
3890 now_ns = get_kernel_ns();
3891 delta = user_ns.clock - now_ns;
3893 kvm->arch.kvmclock_offset = delta;
3894 kvm_gen_update_masterclock(kvm);
3897 case KVM_GET_CLOCK: {
3898 struct kvm_clock_data user_ns;
3901 local_irq_disable();
3902 now_ns = get_kernel_ns();
3903 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3906 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3909 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3922 static void kvm_init_msr_list(void)
3927 /* skip the first msrs in the list. KVM-specific */
3928 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3929 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3933 * Even MSRs that are valid in the host may not be exposed
3934 * to the guests in some cases. We could work around this
3935 * in VMX with the generic MSR save/load machinery, but it
3936 * is not really worthwhile since it will really only
3937 * happen with nested virtualization.
3939 switch (msrs_to_save[i]) {
3940 case MSR_IA32_BNDCFGS:
3941 if (!kvm_x86_ops->mpx_supported())
3949 msrs_to_save[j] = msrs_to_save[i];
3952 num_msrs_to_save = j;
3955 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3963 if (!(vcpu->arch.apic &&
3964 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3965 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3976 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3983 if (!(vcpu->arch.apic &&
3984 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3985 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3987 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3997 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3998 struct kvm_segment *var, int seg)
4000 kvm_x86_ops->set_segment(vcpu, var, seg);
4003 void kvm_get_segment(struct kvm_vcpu *vcpu,
4004 struct kvm_segment *var, int seg)
4006 kvm_x86_ops->get_segment(vcpu, var, seg);
4009 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
4012 struct x86_exception exception;
4014 BUG_ON(!mmu_is_nested(vcpu));
4016 /* NPT walks are always user-walks */
4017 access |= PFERR_USER_MASK;
4018 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
4023 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4024 struct x86_exception *exception)
4026 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4027 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4030 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4031 struct x86_exception *exception)
4033 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4034 access |= PFERR_FETCH_MASK;
4035 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4038 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4039 struct x86_exception *exception)
4041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4042 access |= PFERR_WRITE_MASK;
4043 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4046 /* uses this to access any guest's mapped memory without checking CPL */
4047 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4048 struct x86_exception *exception)
4050 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4053 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4054 struct kvm_vcpu *vcpu, u32 access,
4055 struct x86_exception *exception)
4058 int r = X86EMUL_CONTINUE;
4061 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4063 unsigned offset = addr & (PAGE_SIZE-1);
4064 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4067 if (gpa == UNMAPPED_GVA)
4068 return X86EMUL_PROPAGATE_FAULT;
4069 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4071 r = X86EMUL_IO_NEEDED;
4083 /* used for instruction fetching */
4084 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4085 gva_t addr, void *val, unsigned int bytes,
4086 struct x86_exception *exception)
4088 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4089 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4091 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4092 access | PFERR_FETCH_MASK,
4096 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4097 gva_t addr, void *val, unsigned int bytes,
4098 struct x86_exception *exception)
4100 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4101 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4103 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4106 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4108 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4109 gva_t addr, void *val, unsigned int bytes,
4110 struct x86_exception *exception)
4112 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4113 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4116 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4117 gva_t addr, void *val,
4119 struct x86_exception *exception)
4121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4123 int r = X86EMUL_CONTINUE;
4126 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4129 unsigned offset = addr & (PAGE_SIZE-1);
4130 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4133 if (gpa == UNMAPPED_GVA)
4134 return X86EMUL_PROPAGATE_FAULT;
4135 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4137 r = X86EMUL_IO_NEEDED;
4148 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4150 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4151 gpa_t *gpa, struct x86_exception *exception,
4154 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4155 | (write ? PFERR_WRITE_MASK : 0);
4157 if (vcpu_match_mmio_gva(vcpu, gva)
4158 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4159 vcpu->arch.access, access)) {
4160 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4161 (gva & (PAGE_SIZE - 1));
4162 trace_vcpu_match_mmio(gva, *gpa, write, false);
4166 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4168 if (*gpa == UNMAPPED_GVA)
4171 /* For APIC access vmexit */
4172 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4175 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4176 trace_vcpu_match_mmio(gva, *gpa, write, true);
4183 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4184 const void *val, int bytes)
4188 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4191 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4195 struct read_write_emulator_ops {
4196 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4198 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4199 void *val, int bytes);
4200 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4201 int bytes, void *val);
4202 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4203 void *val, int bytes);
4207 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4209 if (vcpu->mmio_read_completed) {
4210 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4211 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4212 vcpu->mmio_read_completed = 0;
4219 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4220 void *val, int bytes)
4222 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4225 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4226 void *val, int bytes)
4228 return emulator_write_phys(vcpu, gpa, val, bytes);
4231 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4233 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4234 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4237 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4238 void *val, int bytes)
4240 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4241 return X86EMUL_IO_NEEDED;
4244 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4245 void *val, int bytes)
4247 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4249 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4250 return X86EMUL_CONTINUE;
4253 static const struct read_write_emulator_ops read_emultor = {
4254 .read_write_prepare = read_prepare,
4255 .read_write_emulate = read_emulate,
4256 .read_write_mmio = vcpu_mmio_read,
4257 .read_write_exit_mmio = read_exit_mmio,
4260 static const struct read_write_emulator_ops write_emultor = {
4261 .read_write_emulate = write_emulate,
4262 .read_write_mmio = write_mmio,
4263 .read_write_exit_mmio = write_exit_mmio,
4267 static int emulator_read_write_onepage(unsigned long addr, void *val,
4269 struct x86_exception *exception,
4270 struct kvm_vcpu *vcpu,
4271 const struct read_write_emulator_ops *ops)
4275 bool write = ops->write;
4276 struct kvm_mmio_fragment *frag;
4278 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4281 return X86EMUL_PROPAGATE_FAULT;
4283 /* For APIC access vmexit */
4287 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4288 return X86EMUL_CONTINUE;
4292 * Is this MMIO handled locally?
4294 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4295 if (handled == bytes)
4296 return X86EMUL_CONTINUE;
4302 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4303 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4307 return X86EMUL_CONTINUE;
4310 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4311 void *val, unsigned int bytes,
4312 struct x86_exception *exception,
4313 const struct read_write_emulator_ops *ops)
4315 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4319 if (ops->read_write_prepare &&
4320 ops->read_write_prepare(vcpu, val, bytes))
4321 return X86EMUL_CONTINUE;
4323 vcpu->mmio_nr_fragments = 0;
4325 /* Crossing a page boundary? */
4326 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4329 now = -addr & ~PAGE_MASK;
4330 rc = emulator_read_write_onepage(addr, val, now, exception,
4333 if (rc != X86EMUL_CONTINUE)
4340 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4342 if (rc != X86EMUL_CONTINUE)
4345 if (!vcpu->mmio_nr_fragments)
4348 gpa = vcpu->mmio_fragments[0].gpa;
4350 vcpu->mmio_needed = 1;
4351 vcpu->mmio_cur_fragment = 0;
4353 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4354 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4355 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4356 vcpu->run->mmio.phys_addr = gpa;
4358 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4361 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4365 struct x86_exception *exception)
4367 return emulator_read_write(ctxt, addr, val, bytes,
4368 exception, &read_emultor);
4371 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4375 struct x86_exception *exception)
4377 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4378 exception, &write_emultor);
4381 #define CMPXCHG_TYPE(t, ptr, old, new) \
4382 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4384 #ifdef CONFIG_X86_64
4385 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4387 # define CMPXCHG64(ptr, old, new) \
4388 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4391 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4396 struct x86_exception *exception)
4398 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4404 /* guests cmpxchg8b have to be emulated atomically */
4405 if (bytes > 8 || (bytes & (bytes - 1)))
4408 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4410 if (gpa == UNMAPPED_GVA ||
4411 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4414 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4417 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4418 if (is_error_page(page))
4421 kaddr = kmap_atomic(page);
4422 kaddr += offset_in_page(gpa);
4425 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4428 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4431 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4434 exchanged = CMPXCHG64(kaddr, old, new);
4439 kunmap_atomic(kaddr);
4440 kvm_release_page_dirty(page);
4443 return X86EMUL_CMPXCHG_FAILED;
4445 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4446 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4448 return X86EMUL_CONTINUE;
4451 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4453 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4456 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4458 /* TODO: String I/O for in kernel device */
4461 if (vcpu->arch.pio.in)
4462 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4463 vcpu->arch.pio.size, pd);
4465 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4466 vcpu->arch.pio.port, vcpu->arch.pio.size,
4471 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4472 unsigned short port, void *val,
4473 unsigned int count, bool in)
4475 trace_kvm_pio(!in, port, size, count);
4477 vcpu->arch.pio.port = port;
4478 vcpu->arch.pio.in = in;
4479 vcpu->arch.pio.count = count;
4480 vcpu->arch.pio.size = size;
4482 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4483 vcpu->arch.pio.count = 0;
4487 vcpu->run->exit_reason = KVM_EXIT_IO;
4488 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4489 vcpu->run->io.size = size;
4490 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4491 vcpu->run->io.count = count;
4492 vcpu->run->io.port = port;
4497 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4498 int size, unsigned short port, void *val,
4501 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4504 if (vcpu->arch.pio.count)
4507 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4510 memcpy(val, vcpu->arch.pio_data, size * count);
4511 vcpu->arch.pio.count = 0;
4518 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4519 int size, unsigned short port,
4520 const void *val, unsigned int count)
4522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4524 memcpy(vcpu->arch.pio_data, val, size * count);
4525 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4528 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4530 return kvm_x86_ops->get_segment_base(vcpu, seg);
4533 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4535 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4538 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4540 if (!need_emulate_wbinvd(vcpu))
4541 return X86EMUL_CONTINUE;
4543 if (kvm_x86_ops->has_wbinvd_exit()) {
4544 int cpu = get_cpu();
4546 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4547 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4548 wbinvd_ipi, NULL, 1);
4550 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4553 return X86EMUL_CONTINUE;
4555 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4557 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4559 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4562 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4564 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4567 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4570 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4573 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4575 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4578 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4580 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4581 unsigned long value;
4585 value = kvm_read_cr0(vcpu);
4588 value = vcpu->arch.cr2;
4591 value = kvm_read_cr3(vcpu);
4594 value = kvm_read_cr4(vcpu);
4597 value = kvm_get_cr8(vcpu);
4600 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4607 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4614 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4617 vcpu->arch.cr2 = val;
4620 res = kvm_set_cr3(vcpu, val);
4623 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4626 res = kvm_set_cr8(vcpu, val);
4629 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4636 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4638 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4641 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4643 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4646 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4648 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4651 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4653 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4656 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4658 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4661 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4663 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4666 static unsigned long emulator_get_cached_segment_base(
4667 struct x86_emulate_ctxt *ctxt, int seg)
4669 return get_segment_base(emul_to_vcpu(ctxt), seg);
4672 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4673 struct desc_struct *desc, u32 *base3,
4676 struct kvm_segment var;
4678 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4679 *selector = var.selector;
4682 memset(desc, 0, sizeof(*desc));
4688 set_desc_limit(desc, var.limit);
4689 set_desc_base(desc, (unsigned long)var.base);
4690 #ifdef CONFIG_X86_64
4692 *base3 = var.base >> 32;
4694 desc->type = var.type;
4696 desc->dpl = var.dpl;
4697 desc->p = var.present;
4698 desc->avl = var.avl;
4706 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4707 struct desc_struct *desc, u32 base3,
4710 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4711 struct kvm_segment var;
4713 var.selector = selector;
4714 var.base = get_desc_base(desc);
4715 #ifdef CONFIG_X86_64
4716 var.base |= ((u64)base3) << 32;
4718 var.limit = get_desc_limit(desc);
4720 var.limit = (var.limit << 12) | 0xfff;
4721 var.type = desc->type;
4722 var.present = desc->p;
4723 var.dpl = desc->dpl;
4728 var.avl = desc->avl;
4729 var.present = desc->p;
4730 var.unusable = !var.present;
4733 kvm_set_segment(vcpu, &var, seg);
4737 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4738 u32 msr_index, u64 *pdata)
4740 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4743 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4744 u32 msr_index, u64 data)
4746 struct msr_data msr;
4749 msr.index = msr_index;
4750 msr.host_initiated = false;
4751 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4754 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4755 u32 pmc, u64 *pdata)
4757 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4760 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4762 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4765 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4768 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4770 * CR0.TS may reference the host fpu state, not the guest fpu state,
4771 * so it may be clear at this point.
4776 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4781 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4782 struct x86_instruction_info *info,
4783 enum x86_intercept_stage stage)
4785 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4788 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4789 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4791 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4794 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4796 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4799 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4801 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4804 static const struct x86_emulate_ops emulate_ops = {
4805 .read_gpr = emulator_read_gpr,
4806 .write_gpr = emulator_write_gpr,
4807 .read_std = kvm_read_guest_virt_system,
4808 .write_std = kvm_write_guest_virt_system,
4809 .fetch = kvm_fetch_guest_virt,
4810 .read_emulated = emulator_read_emulated,
4811 .write_emulated = emulator_write_emulated,
4812 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4813 .invlpg = emulator_invlpg,
4814 .pio_in_emulated = emulator_pio_in_emulated,
4815 .pio_out_emulated = emulator_pio_out_emulated,
4816 .get_segment = emulator_get_segment,
4817 .set_segment = emulator_set_segment,
4818 .get_cached_segment_base = emulator_get_cached_segment_base,
4819 .get_gdt = emulator_get_gdt,
4820 .get_idt = emulator_get_idt,
4821 .set_gdt = emulator_set_gdt,
4822 .set_idt = emulator_set_idt,
4823 .get_cr = emulator_get_cr,
4824 .set_cr = emulator_set_cr,
4825 .set_rflags = emulator_set_rflags,
4826 .cpl = emulator_get_cpl,
4827 .get_dr = emulator_get_dr,
4828 .set_dr = emulator_set_dr,
4829 .set_msr = emulator_set_msr,
4830 .get_msr = emulator_get_msr,
4831 .read_pmc = emulator_read_pmc,
4832 .halt = emulator_halt,
4833 .wbinvd = emulator_wbinvd,
4834 .fix_hypercall = emulator_fix_hypercall,
4835 .get_fpu = emulator_get_fpu,
4836 .put_fpu = emulator_put_fpu,
4837 .intercept = emulator_intercept,
4838 .get_cpuid = emulator_get_cpuid,
4841 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4843 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4845 * an sti; sti; sequence only disable interrupts for the first
4846 * instruction. So, if the last instruction, be it emulated or
4847 * not, left the system with the INT_STI flag enabled, it
4848 * means that the last instruction is an sti. We should not
4849 * leave the flag on in this case. The same goes for mov ss
4851 if (!(int_shadow & mask))
4852 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4855 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4857 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4858 if (ctxt->exception.vector == PF_VECTOR)
4859 kvm_propagate_fault(vcpu, &ctxt->exception);
4860 else if (ctxt->exception.error_code_valid)
4861 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4862 ctxt->exception.error_code);
4864 kvm_queue_exception(vcpu, ctxt->exception.vector);
4867 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4869 memset(&ctxt->opcode_len, 0,
4870 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4872 ctxt->fetch.start = 0;
4873 ctxt->fetch.end = 0;
4874 ctxt->io_read.pos = 0;
4875 ctxt->io_read.end = 0;
4876 ctxt->mem_read.pos = 0;
4877 ctxt->mem_read.end = 0;
4880 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4882 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4885 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4887 ctxt->eflags = kvm_get_rflags(vcpu);
4888 ctxt->eip = kvm_rip_read(vcpu);
4889 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4890 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4891 cs_l ? X86EMUL_MODE_PROT64 :
4892 cs_db ? X86EMUL_MODE_PROT32 :
4893 X86EMUL_MODE_PROT16;
4894 ctxt->guest_mode = is_guest_mode(vcpu);
4896 init_decode_cache(ctxt);
4897 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4900 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4902 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4905 init_emulate_ctxt(vcpu);
4909 ctxt->_eip = ctxt->eip + inc_eip;
4910 ret = emulate_int_real(ctxt, irq);
4912 if (ret != X86EMUL_CONTINUE)
4913 return EMULATE_FAIL;
4915 ctxt->eip = ctxt->_eip;
4916 kvm_rip_write(vcpu, ctxt->eip);
4917 kvm_set_rflags(vcpu, ctxt->eflags);
4919 if (irq == NMI_VECTOR)
4920 vcpu->arch.nmi_pending = 0;
4922 vcpu->arch.interrupt.pending = false;
4924 return EMULATE_DONE;
4926 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4928 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4930 int r = EMULATE_DONE;
4932 ++vcpu->stat.insn_emulation_fail;
4933 trace_kvm_emulate_insn_failed(vcpu);
4934 if (!is_guest_mode(vcpu)) {
4935 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4936 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4937 vcpu->run->internal.ndata = 0;
4940 kvm_queue_exception(vcpu, UD_VECTOR);
4945 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4946 bool write_fault_to_shadow_pgtable,
4952 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4955 if (!vcpu->arch.mmu.direct_map) {
4957 * Write permission should be allowed since only
4958 * write access need to be emulated.
4960 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4963 * If the mapping is invalid in guest, let cpu retry
4964 * it to generate fault.
4966 if (gpa == UNMAPPED_GVA)
4971 * Do not retry the unhandleable instruction if it faults on the
4972 * readonly host memory, otherwise it will goto a infinite loop:
4973 * retry instruction -> write #PF -> emulation fail -> retry
4974 * instruction -> ...
4976 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4979 * If the instruction failed on the error pfn, it can not be fixed,
4980 * report the error to userspace.
4982 if (is_error_noslot_pfn(pfn))
4985 kvm_release_pfn_clean(pfn);
4987 /* The instructions are well-emulated on direct mmu. */
4988 if (vcpu->arch.mmu.direct_map) {
4989 unsigned int indirect_shadow_pages;
4991 spin_lock(&vcpu->kvm->mmu_lock);
4992 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4993 spin_unlock(&vcpu->kvm->mmu_lock);
4995 if (indirect_shadow_pages)
4996 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5002 * if emulation was due to access to shadowed page table
5003 * and it failed try to unshadow page and re-enter the
5004 * guest to let CPU execute the instruction.
5006 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5009 * If the access faults on its page table, it can not
5010 * be fixed by unprotecting shadow page and it should
5011 * be reported to userspace.
5013 return !write_fault_to_shadow_pgtable;
5016 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5017 unsigned long cr2, int emulation_type)
5019 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5020 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5022 last_retry_eip = vcpu->arch.last_retry_eip;
5023 last_retry_addr = vcpu->arch.last_retry_addr;
5026 * If the emulation is caused by #PF and it is non-page_table
5027 * writing instruction, it means the VM-EXIT is caused by shadow
5028 * page protected, we can zap the shadow page and retry this
5029 * instruction directly.
5031 * Note: if the guest uses a non-page-table modifying instruction
5032 * on the PDE that points to the instruction, then we will unmap
5033 * the instruction and go to an infinite loop. So, we cache the
5034 * last retried eip and the last fault address, if we meet the eip
5035 * and the address again, we can break out of the potential infinite
5038 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5040 if (!(emulation_type & EMULTYPE_RETRY))
5043 if (x86_page_table_writing_insn(ctxt))
5046 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5049 vcpu->arch.last_retry_eip = ctxt->eip;
5050 vcpu->arch.last_retry_addr = cr2;
5052 if (!vcpu->arch.mmu.direct_map)
5053 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5055 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5060 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5061 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5063 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5072 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5073 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5078 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5080 struct kvm_run *kvm_run = vcpu->run;
5083 * Use the "raw" value to see if TF was passed to the processor.
5084 * Note that the new value of the flags has not been saved yet.
5086 * This is correct even for TF set by the guest, because "the
5087 * processor will not generate this exception after the instruction
5088 * that sets the TF flag".
5090 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5092 if (unlikely(rflags & X86_EFLAGS_TF)) {
5093 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5094 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5095 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5096 kvm_run->debug.arch.exception = DB_VECTOR;
5097 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5098 *r = EMULATE_USER_EXIT;
5100 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5102 * "Certain debug exceptions may clear bit 0-3. The
5103 * remaining contents of the DR6 register are never
5104 * cleared by the processor".
5106 vcpu->arch.dr6 &= ~15;
5107 vcpu->arch.dr6 |= DR6_BS;
5108 kvm_queue_exception(vcpu, DB_VECTOR);
5113 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5115 struct kvm_run *kvm_run = vcpu->run;
5116 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5119 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5120 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5121 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5122 vcpu->arch.guest_debug_dr7,
5126 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5127 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5128 get_segment_base(vcpu, VCPU_SREG_CS);
5130 kvm_run->debug.arch.exception = DB_VECTOR;
5131 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5132 *r = EMULATE_USER_EXIT;
5137 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5138 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5143 vcpu->arch.dr6 &= ~15;
5144 vcpu->arch.dr6 |= dr6;
5145 kvm_queue_exception(vcpu, DB_VECTOR);
5154 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5161 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5162 bool writeback = true;
5163 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5166 * Clear write_fault_to_shadow_pgtable here to ensure it is
5169 vcpu->arch.write_fault_to_shadow_pgtable = false;
5170 kvm_clear_exception_queue(vcpu);
5172 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5173 init_emulate_ctxt(vcpu);
5176 * We will reenter on the same instruction since
5177 * we do not set complete_userspace_io. This does not
5178 * handle watchpoints yet, those would be handled in
5181 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5184 ctxt->interruptibility = 0;
5185 ctxt->have_exception = false;
5186 ctxt->perm_ok = false;
5188 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5190 r = x86_decode_insn(ctxt, insn, insn_len);
5192 trace_kvm_emulate_insn_start(vcpu);
5193 ++vcpu->stat.insn_emulation;
5194 if (r != EMULATION_OK) {
5195 if (emulation_type & EMULTYPE_TRAP_UD)
5196 return EMULATE_FAIL;
5197 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5199 return EMULATE_DONE;
5200 if (emulation_type & EMULTYPE_SKIP)
5201 return EMULATE_FAIL;
5202 return handle_emulation_failure(vcpu);
5206 if (emulation_type & EMULTYPE_SKIP) {
5207 kvm_rip_write(vcpu, ctxt->_eip);
5208 return EMULATE_DONE;
5211 if (retry_instruction(ctxt, cr2, emulation_type))
5212 return EMULATE_DONE;
5214 /* this is needed for vmware backdoor interface to work since it
5215 changes registers values during IO operation */
5216 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5217 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5218 emulator_invalidate_register_cache(ctxt);
5222 r = x86_emulate_insn(ctxt);
5224 if (r == EMULATION_INTERCEPTED)
5225 return EMULATE_DONE;
5227 if (r == EMULATION_FAILED) {
5228 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5230 return EMULATE_DONE;
5232 return handle_emulation_failure(vcpu);
5235 if (ctxt->have_exception) {
5236 inject_emulated_exception(vcpu);
5238 } else if (vcpu->arch.pio.count) {
5239 if (!vcpu->arch.pio.in) {
5240 /* FIXME: return into emulator if single-stepping. */
5241 vcpu->arch.pio.count = 0;
5244 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5246 r = EMULATE_USER_EXIT;
5247 } else if (vcpu->mmio_needed) {
5248 if (!vcpu->mmio_is_write)
5250 r = EMULATE_USER_EXIT;
5251 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5252 } else if (r == EMULATION_RESTART)
5258 toggle_interruptibility(vcpu, ctxt->interruptibility);
5259 kvm_make_request(KVM_REQ_EVENT, vcpu);
5260 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5261 kvm_rip_write(vcpu, ctxt->eip);
5262 if (r == EMULATE_DONE)
5263 kvm_vcpu_check_singlestep(vcpu, &r);
5264 kvm_set_rflags(vcpu, ctxt->eflags);
5266 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5270 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5272 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5274 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5275 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5276 size, port, &val, 1);
5277 /* do not return to emulator after return from userspace */
5278 vcpu->arch.pio.count = 0;
5281 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5283 static void tsc_bad(void *info)
5285 __this_cpu_write(cpu_tsc_khz, 0);
5288 static void tsc_khz_changed(void *data)
5290 struct cpufreq_freqs *freq = data;
5291 unsigned long khz = 0;
5295 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5296 khz = cpufreq_quick_get(raw_smp_processor_id());
5299 __this_cpu_write(cpu_tsc_khz, khz);
5302 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5305 struct cpufreq_freqs *freq = data;
5307 struct kvm_vcpu *vcpu;
5308 int i, send_ipi = 0;
5311 * We allow guests to temporarily run on slowing clocks,
5312 * provided we notify them after, or to run on accelerating
5313 * clocks, provided we notify them before. Thus time never
5316 * However, we have a problem. We can't atomically update
5317 * the frequency of a given CPU from this function; it is
5318 * merely a notifier, which can be called from any CPU.
5319 * Changing the TSC frequency at arbitrary points in time
5320 * requires a recomputation of local variables related to
5321 * the TSC for each VCPU. We must flag these local variables
5322 * to be updated and be sure the update takes place with the
5323 * new frequency before any guests proceed.
5325 * Unfortunately, the combination of hotplug CPU and frequency
5326 * change creates an intractable locking scenario; the order
5327 * of when these callouts happen is undefined with respect to
5328 * CPU hotplug, and they can race with each other. As such,
5329 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5330 * undefined; you can actually have a CPU frequency change take
5331 * place in between the computation of X and the setting of the
5332 * variable. To protect against this problem, all updates of
5333 * the per_cpu tsc_khz variable are done in an interrupt
5334 * protected IPI, and all callers wishing to update the value
5335 * must wait for a synchronous IPI to complete (which is trivial
5336 * if the caller is on the CPU already). This establishes the
5337 * necessary total order on variable updates.
5339 * Note that because a guest time update may take place
5340 * anytime after the setting of the VCPU's request bit, the
5341 * correct TSC value must be set before the request. However,
5342 * to ensure the update actually makes it to any guest which
5343 * starts running in hardware virtualization between the set
5344 * and the acquisition of the spinlock, we must also ping the
5345 * CPU after setting the request bit.
5349 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5351 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5354 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5356 spin_lock(&kvm_lock);
5357 list_for_each_entry(kvm, &vm_list, vm_list) {
5358 kvm_for_each_vcpu(i, vcpu, kvm) {
5359 if (vcpu->cpu != freq->cpu)
5361 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5362 if (vcpu->cpu != smp_processor_id())
5366 spin_unlock(&kvm_lock);
5368 if (freq->old < freq->new && send_ipi) {
5370 * We upscale the frequency. Must make the guest
5371 * doesn't see old kvmclock values while running with
5372 * the new frequency, otherwise we risk the guest sees
5373 * time go backwards.
5375 * In case we update the frequency for another cpu
5376 * (which might be in guest context) send an interrupt
5377 * to kick the cpu out of guest context. Next time
5378 * guest context is entered kvmclock will be updated,
5379 * so the guest will not see stale values.
5381 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5386 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5387 .notifier_call = kvmclock_cpufreq_notifier
5390 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5391 unsigned long action, void *hcpu)
5393 unsigned int cpu = (unsigned long)hcpu;
5397 case CPU_DOWN_FAILED:
5398 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5400 case CPU_DOWN_PREPARE:
5401 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5407 static struct notifier_block kvmclock_cpu_notifier_block = {
5408 .notifier_call = kvmclock_cpu_notifier,
5409 .priority = -INT_MAX
5412 static void kvm_timer_init(void)
5416 max_tsc_khz = tsc_khz;
5418 cpu_notifier_register_begin();
5419 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5420 #ifdef CONFIG_CPU_FREQ
5421 struct cpufreq_policy policy;
5422 memset(&policy, 0, sizeof(policy));
5424 cpufreq_get_policy(&policy, cpu);
5425 if (policy.cpuinfo.max_freq)
5426 max_tsc_khz = policy.cpuinfo.max_freq;
5429 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5430 CPUFREQ_TRANSITION_NOTIFIER);
5432 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5433 for_each_online_cpu(cpu)
5434 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5436 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5437 cpu_notifier_register_done();
5441 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5443 int kvm_is_in_guest(void)
5445 return __this_cpu_read(current_vcpu) != NULL;
5448 static int kvm_is_user_mode(void)
5452 if (__this_cpu_read(current_vcpu))
5453 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5455 return user_mode != 0;
5458 static unsigned long kvm_get_guest_ip(void)
5460 unsigned long ip = 0;
5462 if (__this_cpu_read(current_vcpu))
5463 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5468 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5469 .is_in_guest = kvm_is_in_guest,
5470 .is_user_mode = kvm_is_user_mode,
5471 .get_guest_ip = kvm_get_guest_ip,
5474 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5476 __this_cpu_write(current_vcpu, vcpu);
5478 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5480 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5482 __this_cpu_write(current_vcpu, NULL);
5484 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5486 static void kvm_set_mmio_spte_mask(void)
5489 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5492 * Set the reserved bits and the present bit of an paging-structure
5493 * entry to generate page fault with PFER.RSV = 1.
5495 /* Mask the reserved physical address bits. */
5496 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5498 /* Bit 62 is always reserved for 32bit host. */
5499 mask |= 0x3ull << 62;
5501 /* Set the present bit. */
5504 #ifdef CONFIG_X86_64
5506 * If reserved bit is not supported, clear the present bit to disable
5509 if (maxphyaddr == 52)
5513 kvm_mmu_set_mmio_spte_mask(mask);
5516 #ifdef CONFIG_X86_64
5517 static void pvclock_gtod_update_fn(struct work_struct *work)
5521 struct kvm_vcpu *vcpu;
5524 spin_lock(&kvm_lock);
5525 list_for_each_entry(kvm, &vm_list, vm_list)
5526 kvm_for_each_vcpu(i, vcpu, kvm)
5527 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5528 atomic_set(&kvm_guest_has_master_clock, 0);
5529 spin_unlock(&kvm_lock);
5532 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5535 * Notification about pvclock gtod data update.
5537 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5540 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5541 struct timekeeper *tk = priv;
5543 update_pvclock_gtod(tk);
5545 /* disable master clock if host does not trust, or does not
5546 * use, TSC clocksource
5548 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5549 atomic_read(&kvm_guest_has_master_clock) != 0)
5550 queue_work(system_long_wq, &pvclock_gtod_work);
5555 static struct notifier_block pvclock_gtod_notifier = {
5556 .notifier_call = pvclock_gtod_notify,
5560 int kvm_arch_init(void *opaque)
5563 struct kvm_x86_ops *ops = opaque;
5566 printk(KERN_ERR "kvm: already loaded the other module\n");
5571 if (!ops->cpu_has_kvm_support()) {
5572 printk(KERN_ERR "kvm: no hardware support\n");
5576 if (ops->disabled_by_bios()) {
5577 printk(KERN_ERR "kvm: disabled by bios\n");
5583 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5585 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5589 r = kvm_mmu_module_init();
5591 goto out_free_percpu;
5593 kvm_set_mmio_spte_mask();
5596 kvm_init_msr_list();
5598 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5599 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5603 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5606 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5609 #ifdef CONFIG_X86_64
5610 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5616 free_percpu(shared_msrs);
5621 void kvm_arch_exit(void)
5623 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5625 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5626 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5627 CPUFREQ_TRANSITION_NOTIFIER);
5628 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5629 #ifdef CONFIG_X86_64
5630 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5633 kvm_mmu_module_exit();
5634 free_percpu(shared_msrs);
5637 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5639 ++vcpu->stat.halt_exits;
5640 if (irqchip_in_kernel(vcpu->kvm)) {
5641 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5644 vcpu->run->exit_reason = KVM_EXIT_HLT;
5648 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5650 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5652 u64 param, ingpa, outgpa, ret;
5653 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5654 bool fast, longmode;
5658 * hypercall generates UD from non zero cpl and real mode
5661 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5662 kvm_queue_exception(vcpu, UD_VECTOR);
5666 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5667 longmode = is_long_mode(vcpu) && cs_l == 1;
5670 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5671 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5672 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5673 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5674 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5675 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5677 #ifdef CONFIG_X86_64
5679 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5680 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5681 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5685 code = param & 0xffff;
5686 fast = (param >> 16) & 0x1;
5687 rep_cnt = (param >> 32) & 0xfff;
5688 rep_idx = (param >> 48) & 0xfff;
5690 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5693 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5694 kvm_vcpu_on_spin(vcpu);
5697 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5701 ret = res | (((u64)rep_done & 0xfff) << 32);
5703 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5705 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5706 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5713 * kvm_pv_kick_cpu_op: Kick a vcpu.
5715 * @apicid - apicid of vcpu to be kicked.
5717 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5719 struct kvm_lapic_irq lapic_irq;
5721 lapic_irq.shorthand = 0;
5722 lapic_irq.dest_mode = 0;
5723 lapic_irq.dest_id = apicid;
5725 lapic_irq.delivery_mode = APIC_DM_REMRD;
5726 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5729 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5731 unsigned long nr, a0, a1, a2, a3, ret;
5734 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5735 return kvm_hv_hypercall(vcpu);
5737 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5738 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5739 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5740 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5741 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5743 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5745 if (!is_long_mode(vcpu)) {
5753 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5759 case KVM_HC_VAPIC_POLL_IRQ:
5762 case KVM_HC_KICK_CPU:
5763 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5771 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5772 ++vcpu->stat.hypercalls;
5775 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5777 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5780 char instruction[3];
5781 unsigned long rip = kvm_rip_read(vcpu);
5783 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5785 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5789 * Check if userspace requested an interrupt window, and that the
5790 * interrupt window is open.
5792 * No need to exit to userspace if we already have an interrupt queued.
5794 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5796 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5797 vcpu->run->request_interrupt_window &&
5798 kvm_arch_interrupt_allowed(vcpu));
5801 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5803 struct kvm_run *kvm_run = vcpu->run;
5805 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5806 kvm_run->cr8 = kvm_get_cr8(vcpu);
5807 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5808 if (irqchip_in_kernel(vcpu->kvm))
5809 kvm_run->ready_for_interrupt_injection = 1;
5811 kvm_run->ready_for_interrupt_injection =
5812 kvm_arch_interrupt_allowed(vcpu) &&
5813 !kvm_cpu_has_interrupt(vcpu) &&
5814 !kvm_event_needs_reinjection(vcpu);
5817 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5821 if (!kvm_x86_ops->update_cr8_intercept)
5824 if (!vcpu->arch.apic)
5827 if (!vcpu->arch.apic->vapic_addr)
5828 max_irr = kvm_lapic_find_highest_irr(vcpu);
5835 tpr = kvm_lapic_get_cr8(vcpu);
5837 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5840 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5844 /* try to reinject previous events if any */
5845 if (vcpu->arch.exception.pending) {
5846 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5847 vcpu->arch.exception.has_error_code,
5848 vcpu->arch.exception.error_code);
5849 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5850 vcpu->arch.exception.has_error_code,
5851 vcpu->arch.exception.error_code,
5852 vcpu->arch.exception.reinject);
5856 if (vcpu->arch.nmi_injected) {
5857 kvm_x86_ops->set_nmi(vcpu);
5861 if (vcpu->arch.interrupt.pending) {
5862 kvm_x86_ops->set_irq(vcpu);
5866 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5867 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5872 /* try to inject new event if pending */
5873 if (vcpu->arch.nmi_pending) {
5874 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5875 --vcpu->arch.nmi_pending;
5876 vcpu->arch.nmi_injected = true;
5877 kvm_x86_ops->set_nmi(vcpu);
5879 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5880 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5881 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5883 kvm_x86_ops->set_irq(vcpu);
5889 static void process_nmi(struct kvm_vcpu *vcpu)
5894 * x86 is limited to one NMI running, and one NMI pending after it.
5895 * If an NMI is already in progress, limit further NMIs to just one.
5896 * Otherwise, allow two (and we'll inject the first one immediately).
5898 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5901 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5902 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5903 kvm_make_request(KVM_REQ_EVENT, vcpu);
5906 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5908 u64 eoi_exit_bitmap[4];
5911 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5914 memset(eoi_exit_bitmap, 0, 32);
5917 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5918 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5919 kvm_apic_update_tmr(vcpu, tmr);
5923 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5924 * exiting to the userspace. Otherwise, the value will be returned to the
5927 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5930 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5931 vcpu->run->request_interrupt_window;
5932 bool req_immediate_exit = false;
5934 if (vcpu->requests) {
5935 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5936 kvm_mmu_unload(vcpu);
5937 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5938 __kvm_migrate_timers(vcpu);
5939 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5940 kvm_gen_update_masterclock(vcpu->kvm);
5941 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5942 kvm_gen_kvmclock_update(vcpu);
5943 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5944 r = kvm_guest_time_update(vcpu);
5948 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5949 kvm_mmu_sync_roots(vcpu);
5950 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5951 kvm_x86_ops->tlb_flush(vcpu);
5952 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5953 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5957 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5958 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5962 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5963 vcpu->fpu_active = 0;
5964 kvm_x86_ops->fpu_deactivate(vcpu);
5966 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5967 /* Page is swapped out. Do synthetic halt */
5968 vcpu->arch.apf.halted = true;
5972 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5973 record_steal_time(vcpu);
5974 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5976 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5977 kvm_handle_pmu_event(vcpu);
5978 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5979 kvm_deliver_pmi(vcpu);
5980 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5981 vcpu_scan_ioapic(vcpu);
5984 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5985 kvm_apic_accept_events(vcpu);
5986 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5991 if (inject_pending_event(vcpu, req_int_win) != 0)
5992 req_immediate_exit = true;
5993 /* enable NMI/IRQ window open exits if needed */
5994 else if (vcpu->arch.nmi_pending)
5995 kvm_x86_ops->enable_nmi_window(vcpu);
5996 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5997 kvm_x86_ops->enable_irq_window(vcpu);
5999 if (kvm_lapic_enabled(vcpu)) {
6001 * Update architecture specific hints for APIC
6002 * virtual interrupt delivery.
6004 if (kvm_x86_ops->hwapic_irr_update)
6005 kvm_x86_ops->hwapic_irr_update(vcpu,
6006 kvm_lapic_find_highest_irr(vcpu));
6007 update_cr8_intercept(vcpu);
6008 kvm_lapic_sync_to_vapic(vcpu);
6012 r = kvm_mmu_reload(vcpu);
6014 goto cancel_injection;
6019 kvm_x86_ops->prepare_guest_switch(vcpu);
6020 if (vcpu->fpu_active)
6021 kvm_load_guest_fpu(vcpu);
6022 kvm_load_guest_xcr0(vcpu);
6024 vcpu->mode = IN_GUEST_MODE;
6026 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6028 /* We should set ->mode before check ->requests,
6029 * see the comment in make_all_cpus_request.
6031 smp_mb__after_srcu_read_unlock();
6033 local_irq_disable();
6035 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6036 || need_resched() || signal_pending(current)) {
6037 vcpu->mode = OUTSIDE_GUEST_MODE;
6041 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6043 goto cancel_injection;
6046 if (req_immediate_exit)
6047 smp_send_reschedule(vcpu->cpu);
6051 if (unlikely(vcpu->arch.switch_db_regs)) {
6053 set_debugreg(vcpu->arch.eff_db[0], 0);
6054 set_debugreg(vcpu->arch.eff_db[1], 1);
6055 set_debugreg(vcpu->arch.eff_db[2], 2);
6056 set_debugreg(vcpu->arch.eff_db[3], 3);
6057 set_debugreg(vcpu->arch.dr6, 6);
6060 trace_kvm_entry(vcpu->vcpu_id);
6061 kvm_x86_ops->run(vcpu);
6064 * Do this here before restoring debug registers on the host. And
6065 * since we do this before handling the vmexit, a DR access vmexit
6066 * can (a) read the correct value of the debug registers, (b) set
6067 * KVM_DEBUGREG_WONT_EXIT again.
6069 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6072 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6073 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6074 for (i = 0; i < KVM_NR_DB_REGS; i++)
6075 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6079 * If the guest has used debug registers, at least dr7
6080 * will be disabled while returning to the host.
6081 * If we don't have active breakpoints in the host, we don't
6082 * care about the messed up debug address registers. But if
6083 * we have some of them active, restore the old state.
6085 if (hw_breakpoint_active())
6086 hw_breakpoint_restore();
6088 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6091 vcpu->mode = OUTSIDE_GUEST_MODE;
6094 /* Interrupt is enabled by handle_external_intr() */
6095 kvm_x86_ops->handle_external_intr(vcpu);
6100 * We must have an instruction between local_irq_enable() and
6101 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6102 * the interrupt shadow. The stat.exits increment will do nicely.
6103 * But we need to prevent reordering, hence this barrier():
6111 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6114 * Profile KVM exit RIPs:
6116 if (unlikely(prof_on == KVM_PROFILING)) {
6117 unsigned long rip = kvm_rip_read(vcpu);
6118 profile_hit(KVM_PROFILING, (void *)rip);
6121 if (unlikely(vcpu->arch.tsc_always_catchup))
6122 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6124 if (vcpu->arch.apic_attention)
6125 kvm_lapic_sync_from_vapic(vcpu);
6127 r = kvm_x86_ops->handle_exit(vcpu);
6131 kvm_x86_ops->cancel_injection(vcpu);
6132 if (unlikely(vcpu->arch.apic_attention))
6133 kvm_lapic_sync_from_vapic(vcpu);
6139 static int __vcpu_run(struct kvm_vcpu *vcpu)
6142 struct kvm *kvm = vcpu->kvm;
6144 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6148 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6149 !vcpu->arch.apf.halted)
6150 r = vcpu_enter_guest(vcpu);
6152 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6153 kvm_vcpu_block(vcpu);
6154 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6155 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6156 kvm_apic_accept_events(vcpu);
6157 switch(vcpu->arch.mp_state) {
6158 case KVM_MP_STATE_HALTED:
6159 vcpu->arch.pv.pv_unhalted = false;
6160 vcpu->arch.mp_state =
6161 KVM_MP_STATE_RUNNABLE;
6162 case KVM_MP_STATE_RUNNABLE:
6163 vcpu->arch.apf.halted = false;
6165 case KVM_MP_STATE_INIT_RECEIVED:
6177 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6178 if (kvm_cpu_has_pending_timer(vcpu))
6179 kvm_inject_pending_timer_irqs(vcpu);
6181 if (dm_request_for_irq_injection(vcpu)) {
6183 vcpu->run->exit_reason = KVM_EXIT_INTR;
6184 ++vcpu->stat.request_irq_exits;
6187 kvm_check_async_pf_completion(vcpu);
6189 if (signal_pending(current)) {
6191 vcpu->run->exit_reason = KVM_EXIT_INTR;
6192 ++vcpu->stat.signal_exits;
6194 if (need_resched()) {
6195 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6197 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6201 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6206 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6209 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6210 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6211 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6212 if (r != EMULATE_DONE)
6217 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6219 BUG_ON(!vcpu->arch.pio.count);
6221 return complete_emulated_io(vcpu);
6225 * Implements the following, as a state machine:
6229 * for each mmio piece in the fragment
6237 * for each mmio piece in the fragment
6242 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6244 struct kvm_run *run = vcpu->run;
6245 struct kvm_mmio_fragment *frag;
6248 BUG_ON(!vcpu->mmio_needed);
6250 /* Complete previous fragment */
6251 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6252 len = min(8u, frag->len);
6253 if (!vcpu->mmio_is_write)
6254 memcpy(frag->data, run->mmio.data, len);
6256 if (frag->len <= 8) {
6257 /* Switch to the next fragment. */
6259 vcpu->mmio_cur_fragment++;
6261 /* Go forward to the next mmio piece. */
6267 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6268 vcpu->mmio_needed = 0;
6270 /* FIXME: return into emulator if single-stepping. */
6271 if (vcpu->mmio_is_write)
6273 vcpu->mmio_read_completed = 1;
6274 return complete_emulated_io(vcpu);
6277 run->exit_reason = KVM_EXIT_MMIO;
6278 run->mmio.phys_addr = frag->gpa;
6279 if (vcpu->mmio_is_write)
6280 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6281 run->mmio.len = min(8u, frag->len);
6282 run->mmio.is_write = vcpu->mmio_is_write;
6283 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6288 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6293 if (!tsk_used_math(current) && init_fpu(current))
6296 if (vcpu->sigset_active)
6297 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6299 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6300 kvm_vcpu_block(vcpu);
6301 kvm_apic_accept_events(vcpu);
6302 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6307 /* re-sync apic's tpr */
6308 if (!irqchip_in_kernel(vcpu->kvm)) {
6309 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6315 if (unlikely(vcpu->arch.complete_userspace_io)) {
6316 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6317 vcpu->arch.complete_userspace_io = NULL;
6322 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6324 r = __vcpu_run(vcpu);
6327 post_kvm_run_save(vcpu);
6328 if (vcpu->sigset_active)
6329 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6334 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6336 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6338 * We are here if userspace calls get_regs() in the middle of
6339 * instruction emulation. Registers state needs to be copied
6340 * back from emulation context to vcpu. Userspace shouldn't do
6341 * that usually, but some bad designed PV devices (vmware
6342 * backdoor interface) need this to work
6344 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6345 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6347 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6348 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6349 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6350 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6351 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6352 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6353 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6354 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6355 #ifdef CONFIG_X86_64
6356 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6357 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6358 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6359 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6360 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6361 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6362 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6363 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6366 regs->rip = kvm_rip_read(vcpu);
6367 regs->rflags = kvm_get_rflags(vcpu);
6372 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6374 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6375 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6377 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6378 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6379 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6380 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6381 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6382 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6383 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6384 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6385 #ifdef CONFIG_X86_64
6386 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6387 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6388 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6389 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6390 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6391 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6392 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6393 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6396 kvm_rip_write(vcpu, regs->rip);
6397 kvm_set_rflags(vcpu, regs->rflags);
6399 vcpu->arch.exception.pending = false;
6401 kvm_make_request(KVM_REQ_EVENT, vcpu);
6406 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6408 struct kvm_segment cs;
6410 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6414 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6416 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6417 struct kvm_sregs *sregs)
6421 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6422 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6423 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6424 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6425 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6426 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6428 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6429 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6431 kvm_x86_ops->get_idt(vcpu, &dt);
6432 sregs->idt.limit = dt.size;
6433 sregs->idt.base = dt.address;
6434 kvm_x86_ops->get_gdt(vcpu, &dt);
6435 sregs->gdt.limit = dt.size;
6436 sregs->gdt.base = dt.address;
6438 sregs->cr0 = kvm_read_cr0(vcpu);
6439 sregs->cr2 = vcpu->arch.cr2;
6440 sregs->cr3 = kvm_read_cr3(vcpu);
6441 sregs->cr4 = kvm_read_cr4(vcpu);
6442 sregs->cr8 = kvm_get_cr8(vcpu);
6443 sregs->efer = vcpu->arch.efer;
6444 sregs->apic_base = kvm_get_apic_base(vcpu);
6446 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6448 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6449 set_bit(vcpu->arch.interrupt.nr,
6450 (unsigned long *)sregs->interrupt_bitmap);
6455 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6456 struct kvm_mp_state *mp_state)
6458 kvm_apic_accept_events(vcpu);
6459 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6460 vcpu->arch.pv.pv_unhalted)
6461 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6463 mp_state->mp_state = vcpu->arch.mp_state;
6468 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6469 struct kvm_mp_state *mp_state)
6471 if (!kvm_vcpu_has_lapic(vcpu) &&
6472 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6475 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6476 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6477 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6479 vcpu->arch.mp_state = mp_state->mp_state;
6480 kvm_make_request(KVM_REQ_EVENT, vcpu);
6484 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6485 int reason, bool has_error_code, u32 error_code)
6487 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6490 init_emulate_ctxt(vcpu);
6492 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6493 has_error_code, error_code);
6496 return EMULATE_FAIL;
6498 kvm_rip_write(vcpu, ctxt->eip);
6499 kvm_set_rflags(vcpu, ctxt->eflags);
6500 kvm_make_request(KVM_REQ_EVENT, vcpu);
6501 return EMULATE_DONE;
6503 EXPORT_SYMBOL_GPL(kvm_task_switch);
6505 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6506 struct kvm_sregs *sregs)
6508 struct msr_data apic_base_msr;
6509 int mmu_reset_needed = 0;
6510 int pending_vec, max_bits, idx;
6513 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6516 dt.size = sregs->idt.limit;
6517 dt.address = sregs->idt.base;
6518 kvm_x86_ops->set_idt(vcpu, &dt);
6519 dt.size = sregs->gdt.limit;
6520 dt.address = sregs->gdt.base;
6521 kvm_x86_ops->set_gdt(vcpu, &dt);
6523 vcpu->arch.cr2 = sregs->cr2;
6524 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6525 vcpu->arch.cr3 = sregs->cr3;
6526 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6528 kvm_set_cr8(vcpu, sregs->cr8);
6530 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6531 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6532 apic_base_msr.data = sregs->apic_base;
6533 apic_base_msr.host_initiated = true;
6534 kvm_set_apic_base(vcpu, &apic_base_msr);
6536 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6537 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6538 vcpu->arch.cr0 = sregs->cr0;
6540 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6541 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6542 if (sregs->cr4 & X86_CR4_OSXSAVE)
6543 kvm_update_cpuid(vcpu);
6545 idx = srcu_read_lock(&vcpu->kvm->srcu);
6546 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6547 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6548 mmu_reset_needed = 1;
6550 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6552 if (mmu_reset_needed)
6553 kvm_mmu_reset_context(vcpu);
6555 max_bits = KVM_NR_INTERRUPTS;
6556 pending_vec = find_first_bit(
6557 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6558 if (pending_vec < max_bits) {
6559 kvm_queue_interrupt(vcpu, pending_vec, false);
6560 pr_debug("Set back pending irq %d\n", pending_vec);
6563 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6564 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6565 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6566 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6567 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6568 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6570 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6571 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6573 update_cr8_intercept(vcpu);
6575 /* Older userspace won't unhalt the vcpu on reset. */
6576 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6577 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6579 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6581 kvm_make_request(KVM_REQ_EVENT, vcpu);
6586 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6587 struct kvm_guest_debug *dbg)
6589 unsigned long rflags;
6592 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6594 if (vcpu->arch.exception.pending)
6596 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6597 kvm_queue_exception(vcpu, DB_VECTOR);
6599 kvm_queue_exception(vcpu, BP_VECTOR);
6603 * Read rflags as long as potentially injected trace flags are still
6606 rflags = kvm_get_rflags(vcpu);
6608 vcpu->guest_debug = dbg->control;
6609 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6610 vcpu->guest_debug = 0;
6612 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6613 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6614 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6615 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6617 for (i = 0; i < KVM_NR_DB_REGS; i++)
6618 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6620 kvm_update_dr7(vcpu);
6622 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6623 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6624 get_segment_base(vcpu, VCPU_SREG_CS);
6627 * Trigger an rflags update that will inject or remove the trace
6630 kvm_set_rflags(vcpu, rflags);
6632 kvm_x86_ops->update_db_bp_intercept(vcpu);
6642 * Translate a guest virtual address to a guest physical address.
6644 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6645 struct kvm_translation *tr)
6647 unsigned long vaddr = tr->linear_address;
6651 idx = srcu_read_lock(&vcpu->kvm->srcu);
6652 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6653 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6654 tr->physical_address = gpa;
6655 tr->valid = gpa != UNMAPPED_GVA;
6662 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6664 struct i387_fxsave_struct *fxsave =
6665 &vcpu->arch.guest_fpu.state->fxsave;
6667 memcpy(fpu->fpr, fxsave->st_space, 128);
6668 fpu->fcw = fxsave->cwd;
6669 fpu->fsw = fxsave->swd;
6670 fpu->ftwx = fxsave->twd;
6671 fpu->last_opcode = fxsave->fop;
6672 fpu->last_ip = fxsave->rip;
6673 fpu->last_dp = fxsave->rdp;
6674 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6679 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6681 struct i387_fxsave_struct *fxsave =
6682 &vcpu->arch.guest_fpu.state->fxsave;
6684 memcpy(fxsave->st_space, fpu->fpr, 128);
6685 fxsave->cwd = fpu->fcw;
6686 fxsave->swd = fpu->fsw;
6687 fxsave->twd = fpu->ftwx;
6688 fxsave->fop = fpu->last_opcode;
6689 fxsave->rip = fpu->last_ip;
6690 fxsave->rdp = fpu->last_dp;
6691 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6696 int fx_init(struct kvm_vcpu *vcpu)
6700 err = fpu_alloc(&vcpu->arch.guest_fpu);
6704 fpu_finit(&vcpu->arch.guest_fpu);
6707 * Ensure guest xcr0 is valid for loading
6709 vcpu->arch.xcr0 = XSTATE_FP;
6711 vcpu->arch.cr0 |= X86_CR0_ET;
6715 EXPORT_SYMBOL_GPL(fx_init);
6717 static void fx_free(struct kvm_vcpu *vcpu)
6719 fpu_free(&vcpu->arch.guest_fpu);
6722 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6724 if (vcpu->guest_fpu_loaded)
6728 * Restore all possible states in the guest,
6729 * and assume host would use all available bits.
6730 * Guest xcr0 would be loaded later.
6732 kvm_put_guest_xcr0(vcpu);
6733 vcpu->guest_fpu_loaded = 1;
6734 __kernel_fpu_begin();
6735 fpu_restore_checking(&vcpu->arch.guest_fpu);
6739 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6741 kvm_put_guest_xcr0(vcpu);
6743 if (!vcpu->guest_fpu_loaded)
6746 vcpu->guest_fpu_loaded = 0;
6747 fpu_save_init(&vcpu->arch.guest_fpu);
6749 ++vcpu->stat.fpu_reload;
6750 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6754 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6756 kvmclock_reset(vcpu);
6758 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6760 kvm_x86_ops->vcpu_free(vcpu);
6763 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6766 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6767 printk_once(KERN_WARNING
6768 "kvm: SMP vm created on host with unstable TSC; "
6769 "guest TSC will not be reliable\n");
6770 return kvm_x86_ops->vcpu_create(kvm, id);
6773 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6777 vcpu->arch.mtrr_state.have_fixed = 1;
6778 r = vcpu_load(vcpu);
6781 kvm_vcpu_reset(vcpu);
6782 kvm_mmu_setup(vcpu);
6788 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6791 struct msr_data msr;
6792 struct kvm *kvm = vcpu->kvm;
6794 r = vcpu_load(vcpu);
6798 msr.index = MSR_IA32_TSC;
6799 msr.host_initiated = true;
6800 kvm_write_tsc(vcpu, &msr);
6803 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6804 KVMCLOCK_SYNC_PERIOD);
6809 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6812 vcpu->arch.apf.msr_val = 0;
6814 r = vcpu_load(vcpu);
6816 kvm_mmu_unload(vcpu);
6820 kvm_x86_ops->vcpu_free(vcpu);
6823 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6825 atomic_set(&vcpu->arch.nmi_queued, 0);
6826 vcpu->arch.nmi_pending = 0;
6827 vcpu->arch.nmi_injected = false;
6829 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6830 vcpu->arch.dr6 = DR6_FIXED_1;
6831 kvm_update_dr6(vcpu);
6832 vcpu->arch.dr7 = DR7_FIXED_1;
6833 kvm_update_dr7(vcpu);
6835 kvm_make_request(KVM_REQ_EVENT, vcpu);
6836 vcpu->arch.apf.msr_val = 0;
6837 vcpu->arch.st.msr_val = 0;
6839 kvmclock_reset(vcpu);
6841 kvm_clear_async_pf_completion_queue(vcpu);
6842 kvm_async_pf_hash_reset(vcpu);
6843 vcpu->arch.apf.halted = false;
6845 kvm_pmu_reset(vcpu);
6847 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6848 vcpu->arch.regs_avail = ~0;
6849 vcpu->arch.regs_dirty = ~0;
6851 kvm_x86_ops->vcpu_reset(vcpu);
6854 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6856 struct kvm_segment cs;
6858 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6859 cs.selector = vector << 8;
6860 cs.base = vector << 12;
6861 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6862 kvm_rip_write(vcpu, 0);
6865 int kvm_arch_hardware_enable(void *garbage)
6868 struct kvm_vcpu *vcpu;
6873 bool stable, backwards_tsc = false;
6875 kvm_shared_msr_cpu_online();
6876 ret = kvm_x86_ops->hardware_enable(garbage);
6880 local_tsc = native_read_tsc();
6881 stable = !check_tsc_unstable();
6882 list_for_each_entry(kvm, &vm_list, vm_list) {
6883 kvm_for_each_vcpu(i, vcpu, kvm) {
6884 if (!stable && vcpu->cpu == smp_processor_id())
6885 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6886 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6887 backwards_tsc = true;
6888 if (vcpu->arch.last_host_tsc > max_tsc)
6889 max_tsc = vcpu->arch.last_host_tsc;
6895 * Sometimes, even reliable TSCs go backwards. This happens on
6896 * platforms that reset TSC during suspend or hibernate actions, but
6897 * maintain synchronization. We must compensate. Fortunately, we can
6898 * detect that condition here, which happens early in CPU bringup,
6899 * before any KVM threads can be running. Unfortunately, we can't
6900 * bring the TSCs fully up to date with real time, as we aren't yet far
6901 * enough into CPU bringup that we know how much real time has actually
6902 * elapsed; our helper function, get_kernel_ns() will be using boot
6903 * variables that haven't been updated yet.
6905 * So we simply find the maximum observed TSC above, then record the
6906 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6907 * the adjustment will be applied. Note that we accumulate
6908 * adjustments, in case multiple suspend cycles happen before some VCPU
6909 * gets a chance to run again. In the event that no KVM threads get a
6910 * chance to run, we will miss the entire elapsed period, as we'll have
6911 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6912 * loose cycle time. This isn't too big a deal, since the loss will be
6913 * uniform across all VCPUs (not to mention the scenario is extremely
6914 * unlikely). It is possible that a second hibernate recovery happens
6915 * much faster than a first, causing the observed TSC here to be
6916 * smaller; this would require additional padding adjustment, which is
6917 * why we set last_host_tsc to the local tsc observed here.
6919 * N.B. - this code below runs only on platforms with reliable TSC,
6920 * as that is the only way backwards_tsc is set above. Also note
6921 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6922 * have the same delta_cyc adjustment applied if backwards_tsc
6923 * is detected. Note further, this adjustment is only done once,
6924 * as we reset last_host_tsc on all VCPUs to stop this from being
6925 * called multiple times (one for each physical CPU bringup).
6927 * Platforms with unreliable TSCs don't have to deal with this, they
6928 * will be compensated by the logic in vcpu_load, which sets the TSC to
6929 * catchup mode. This will catchup all VCPUs to real time, but cannot
6930 * guarantee that they stay in perfect synchronization.
6932 if (backwards_tsc) {
6933 u64 delta_cyc = max_tsc - local_tsc;
6934 list_for_each_entry(kvm, &vm_list, vm_list) {
6935 kvm_for_each_vcpu(i, vcpu, kvm) {
6936 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6937 vcpu->arch.last_host_tsc = local_tsc;
6938 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6943 * We have to disable TSC offset matching.. if you were
6944 * booting a VM while issuing an S4 host suspend....
6945 * you may have some problem. Solving this issue is
6946 * left as an exercise to the reader.
6948 kvm->arch.last_tsc_nsec = 0;
6949 kvm->arch.last_tsc_write = 0;
6956 void kvm_arch_hardware_disable(void *garbage)
6958 kvm_x86_ops->hardware_disable(garbage);
6959 drop_user_return_notifiers(garbage);
6962 int kvm_arch_hardware_setup(void)
6964 return kvm_x86_ops->hardware_setup();
6967 void kvm_arch_hardware_unsetup(void)
6969 kvm_x86_ops->hardware_unsetup();
6972 void kvm_arch_check_processor_compat(void *rtn)
6974 kvm_x86_ops->check_processor_compatibility(rtn);
6977 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6979 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6982 struct static_key kvm_no_apic_vcpu __read_mostly;
6984 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6990 BUG_ON(vcpu->kvm == NULL);
6993 vcpu->arch.pv.pv_unhalted = false;
6994 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6995 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6998 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7000 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7005 vcpu->arch.pio_data = page_address(page);
7007 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7009 r = kvm_mmu_create(vcpu);
7011 goto fail_free_pio_data;
7013 if (irqchip_in_kernel(kvm)) {
7014 r = kvm_create_lapic(vcpu);
7016 goto fail_mmu_destroy;
7018 static_key_slow_inc(&kvm_no_apic_vcpu);
7020 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7022 if (!vcpu->arch.mce_banks) {
7024 goto fail_free_lapic;
7026 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7028 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7030 goto fail_free_mce_banks;
7035 goto fail_free_wbinvd_dirty_mask;
7037 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7038 vcpu->arch.pv_time_enabled = false;
7040 vcpu->arch.guest_supported_xcr0 = 0;
7041 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7043 kvm_async_pf_hash_reset(vcpu);
7047 fail_free_wbinvd_dirty_mask:
7048 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7049 fail_free_mce_banks:
7050 kfree(vcpu->arch.mce_banks);
7052 kvm_free_lapic(vcpu);
7054 kvm_mmu_destroy(vcpu);
7056 free_page((unsigned long)vcpu->arch.pio_data);
7061 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7065 kvm_pmu_destroy(vcpu);
7066 kfree(vcpu->arch.mce_banks);
7067 kvm_free_lapic(vcpu);
7068 idx = srcu_read_lock(&vcpu->kvm->srcu);
7069 kvm_mmu_destroy(vcpu);
7070 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7071 free_page((unsigned long)vcpu->arch.pio_data);
7072 if (!irqchip_in_kernel(vcpu->kvm))
7073 static_key_slow_dec(&kvm_no_apic_vcpu);
7076 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7081 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7082 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7083 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7084 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7086 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7087 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7088 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7089 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7090 &kvm->arch.irq_sources_bitmap);
7092 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7093 mutex_init(&kvm->arch.apic_map_lock);
7094 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7096 pvclock_update_vm_gtod_copy(kvm);
7098 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7099 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7104 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7107 r = vcpu_load(vcpu);
7109 kvm_mmu_unload(vcpu);
7113 static void kvm_free_vcpus(struct kvm *kvm)
7116 struct kvm_vcpu *vcpu;
7119 * Unpin any mmu pages first.
7121 kvm_for_each_vcpu(i, vcpu, kvm) {
7122 kvm_clear_async_pf_completion_queue(vcpu);
7123 kvm_unload_vcpu_mmu(vcpu);
7125 kvm_for_each_vcpu(i, vcpu, kvm)
7126 kvm_arch_vcpu_free(vcpu);
7128 mutex_lock(&kvm->lock);
7129 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7130 kvm->vcpus[i] = NULL;
7132 atomic_set(&kvm->online_vcpus, 0);
7133 mutex_unlock(&kvm->lock);
7136 void kvm_arch_sync_events(struct kvm *kvm)
7138 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7139 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7140 kvm_free_all_assigned_devices(kvm);
7144 void kvm_arch_destroy_vm(struct kvm *kvm)
7146 if (current->mm == kvm->mm) {
7148 * Free memory regions allocated on behalf of userspace,
7149 * unless the the memory map has changed due to process exit
7152 struct kvm_userspace_memory_region mem;
7153 memset(&mem, 0, sizeof(mem));
7154 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7155 kvm_set_memory_region(kvm, &mem);
7157 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7158 kvm_set_memory_region(kvm, &mem);
7160 mem.slot = TSS_PRIVATE_MEMSLOT;
7161 kvm_set_memory_region(kvm, &mem);
7163 kvm_iommu_unmap_guest(kvm);
7164 kfree(kvm->arch.vpic);
7165 kfree(kvm->arch.vioapic);
7166 kvm_free_vcpus(kvm);
7167 if (kvm->arch.apic_access_page)
7168 put_page(kvm->arch.apic_access_page);
7169 if (kvm->arch.ept_identity_pagetable)
7170 put_page(kvm->arch.ept_identity_pagetable);
7171 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7174 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7175 struct kvm_memory_slot *dont)
7179 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7180 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7181 kvm_kvfree(free->arch.rmap[i]);
7182 free->arch.rmap[i] = NULL;
7187 if (!dont || free->arch.lpage_info[i - 1] !=
7188 dont->arch.lpage_info[i - 1]) {
7189 kvm_kvfree(free->arch.lpage_info[i - 1]);
7190 free->arch.lpage_info[i - 1] = NULL;
7195 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7196 unsigned long npages)
7200 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7205 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7206 slot->base_gfn, level) + 1;
7208 slot->arch.rmap[i] =
7209 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7210 if (!slot->arch.rmap[i])
7215 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7216 sizeof(*slot->arch.lpage_info[i - 1]));
7217 if (!slot->arch.lpage_info[i - 1])
7220 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7221 slot->arch.lpage_info[i - 1][0].write_count = 1;
7222 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7223 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7224 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7226 * If the gfn and userspace address are not aligned wrt each
7227 * other, or if explicitly asked to, disable large page
7228 * support for this slot
7230 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7231 !kvm_largepages_enabled()) {
7234 for (j = 0; j < lpages; ++j)
7235 slot->arch.lpage_info[i - 1][j].write_count = 1;
7242 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7243 kvm_kvfree(slot->arch.rmap[i]);
7244 slot->arch.rmap[i] = NULL;
7248 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7249 slot->arch.lpage_info[i - 1] = NULL;
7254 void kvm_arch_memslots_updated(struct kvm *kvm)
7257 * memslots->generation has been incremented.
7258 * mmio generation may have reached its maximum value.
7260 kvm_mmu_invalidate_mmio_sptes(kvm);
7263 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7264 struct kvm_memory_slot *memslot,
7265 struct kvm_userspace_memory_region *mem,
7266 enum kvm_mr_change change)
7269 * Only private memory slots need to be mapped here since
7270 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7272 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7273 unsigned long userspace_addr;
7276 * MAP_SHARED to prevent internal slot pages from being moved
7279 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7280 PROT_READ | PROT_WRITE,
7281 MAP_SHARED | MAP_ANONYMOUS, 0);
7283 if (IS_ERR((void *)userspace_addr))
7284 return PTR_ERR((void *)userspace_addr);
7286 memslot->userspace_addr = userspace_addr;
7292 void kvm_arch_commit_memory_region(struct kvm *kvm,
7293 struct kvm_userspace_memory_region *mem,
7294 const struct kvm_memory_slot *old,
7295 enum kvm_mr_change change)
7298 int nr_mmu_pages = 0;
7300 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7303 ret = vm_munmap(old->userspace_addr,
7304 old->npages * PAGE_SIZE);
7307 "kvm_vm_ioctl_set_memory_region: "
7308 "failed to munmap memory\n");
7311 if (!kvm->arch.n_requested_mmu_pages)
7312 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7315 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7317 * Write protect all pages for dirty logging.
7318 * Existing largepage mappings are destroyed here and new ones will
7319 * not be created until the end of the logging.
7321 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7322 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7325 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7327 kvm_mmu_invalidate_zap_all_pages(kvm);
7330 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7331 struct kvm_memory_slot *slot)
7333 kvm_mmu_invalidate_zap_all_pages(kvm);
7336 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7338 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7339 kvm_x86_ops->check_nested_events(vcpu, false);
7341 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7342 !vcpu->arch.apf.halted)
7343 || !list_empty_careful(&vcpu->async_pf.done)
7344 || kvm_apic_has_events(vcpu)
7345 || vcpu->arch.pv.pv_unhalted
7346 || atomic_read(&vcpu->arch.nmi_queued) ||
7347 (kvm_arch_interrupt_allowed(vcpu) &&
7348 kvm_cpu_has_interrupt(vcpu));
7351 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7353 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7356 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7358 return kvm_x86_ops->interrupt_allowed(vcpu);
7361 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7363 unsigned long current_rip = kvm_rip_read(vcpu) +
7364 get_segment_base(vcpu, VCPU_SREG_CS);
7366 return current_rip == linear_rip;
7368 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7370 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7372 unsigned long rflags;
7374 rflags = kvm_x86_ops->get_rflags(vcpu);
7375 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7376 rflags &= ~X86_EFLAGS_TF;
7379 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7381 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7383 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7384 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7385 rflags |= X86_EFLAGS_TF;
7386 kvm_x86_ops->set_rflags(vcpu, rflags);
7387 kvm_make_request(KVM_REQ_EVENT, vcpu);
7389 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7391 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7395 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7399 r = kvm_mmu_reload(vcpu);
7403 if (!vcpu->arch.mmu.direct_map &&
7404 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7407 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7410 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7412 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7415 static inline u32 kvm_async_pf_next_probe(u32 key)
7417 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7420 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7422 u32 key = kvm_async_pf_hash_fn(gfn);
7424 while (vcpu->arch.apf.gfns[key] != ~0)
7425 key = kvm_async_pf_next_probe(key);
7427 vcpu->arch.apf.gfns[key] = gfn;
7430 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7433 u32 key = kvm_async_pf_hash_fn(gfn);
7435 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7436 (vcpu->arch.apf.gfns[key] != gfn &&
7437 vcpu->arch.apf.gfns[key] != ~0); i++)
7438 key = kvm_async_pf_next_probe(key);
7443 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7445 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7448 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7452 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7454 vcpu->arch.apf.gfns[i] = ~0;
7456 j = kvm_async_pf_next_probe(j);
7457 if (vcpu->arch.apf.gfns[j] == ~0)
7459 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7461 * k lies cyclically in ]i,j]
7463 * |....j i.k.| or |.k..j i...|
7465 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7466 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7471 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7474 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7478 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7479 struct kvm_async_pf *work)
7481 struct x86_exception fault;
7483 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7484 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7486 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7487 (vcpu->arch.apf.send_user_only &&
7488 kvm_x86_ops->get_cpl(vcpu) == 0))
7489 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7490 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7491 fault.vector = PF_VECTOR;
7492 fault.error_code_valid = true;
7493 fault.error_code = 0;
7494 fault.nested_page_fault = false;
7495 fault.address = work->arch.token;
7496 kvm_inject_page_fault(vcpu, &fault);
7500 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7501 struct kvm_async_pf *work)
7503 struct x86_exception fault;
7505 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7506 if (work->wakeup_all)
7507 work->arch.token = ~0; /* broadcast wakeup */
7509 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7511 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7512 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7513 fault.vector = PF_VECTOR;
7514 fault.error_code_valid = true;
7515 fault.error_code = 0;
7516 fault.nested_page_fault = false;
7517 fault.address = work->arch.token;
7518 kvm_inject_page_fault(vcpu, &fault);
7520 vcpu->arch.apf.halted = false;
7521 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7524 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7526 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7529 return !kvm_event_needs_reinjection(vcpu) &&
7530 kvm_x86_ops->interrupt_allowed(vcpu);
7533 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7535 atomic_inc(&kvm->arch.noncoherent_dma_count);
7537 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7539 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7541 atomic_dec(&kvm->arch.noncoherent_dma_count);
7543 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7545 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7547 return atomic_read(&kvm->arch.noncoherent_dma_count);
7549 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7551 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7552 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7553 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7554 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7555 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7556 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7557 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7558 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7560 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);