2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
51 #define CREATE_TRACE_POINTS
54 #include <asm/debugreg.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
69 #define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32 kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
104 #define KVM_NR_SHARED_MSRS 16
106 struct kvm_shared_msrs_global {
108 u32 msrs[KVM_NR_SHARED_MSRS];
111 struct kvm_shared_msrs {
112 struct user_return_notifier urn;
114 struct kvm_shared_msr_values {
117 } values[KVM_NR_SHARED_MSRS];
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136 { "hypercalls", VCPU_STAT(hypercalls) },
137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144 { "irq_injections", VCPU_STAT(irq_injections) },
145 { "nmi_injections", VCPU_STAT(nmi_injections) },
146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153 { "mmu_unsync", VM_STAT(mmu_unsync) },
154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155 { "largepages", VM_STAT(lpages) },
159 u64 __read_mostly host_xcr0;
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
170 static void kvm_on_user_return(struct user_return_notifier *urn)
173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
175 struct kvm_shared_msr_values *values;
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
188 static void shared_msr_update(unsigned slot, u32 msr)
190 struct kvm_shared_msrs *smsr;
193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
215 static void kvm_shared_msr_cpu_online(void)
219 for (i = 0; i < shared_msrs_global.nr; ++i)
220 shared_msr_update(i, shared_msrs_global.msrs[i]);
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
239 static void drop_user_return_notifiers(void *ignore)
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
249 if (irqchip_in_kernel(vcpu->kvm))
250 return vcpu->arch.apic_base;
252 return vcpu->arch.apic_base;
254 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 /* TODO: reserve bits check */
259 if (irqchip_in_kernel(vcpu->kvm))
260 kvm_lapic_set_base(vcpu, data);
262 vcpu->arch.apic_base = data;
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266 #define EXCPT_BENIGN 0
267 #define EXCPT_CONTRIBUTORY 1
270 static int exception_class(int vector)
280 return EXCPT_CONTRIBUTORY;
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288 unsigned nr, bool has_error, u32 error_code,
294 kvm_make_request(KVM_REQ_EVENT, vcpu);
296 if (!vcpu->arch.exception.pending) {
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
302 vcpu->arch.exception.reinject = reinject;
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331 kvm_multiple_exception(vcpu, nr, false, 0, false);
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
344 kvm_inject_gp(vcpu, 0);
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
352 ++vcpu->stat.pf_guest;
353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
415 real_gfn = gpa_to_gfn(real_gfn);
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
429 * Load the pae pdptrs. Return true is they are all valid.
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447 if (is_present_gpte(pdpte[i]) &&
448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
464 EXPORT_SYMBOL_GPL(load_pdptrs);
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
502 if (cr0 & 0xffffffff00000000UL)
506 cr0 &= ~CR0_RESERVED_BITS;
508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
516 if ((vcpu->arch.efer & EFER_LME)) {
521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
534 kvm_x86_ops->set_cr0(vcpu, cr0);
536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
537 kvm_clear_async_pf_completion_queue(vcpu);
538 kvm_async_pf_hash_reset(vcpu);
541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
545 EXPORT_SYMBOL_GPL(kvm_set_cr0);
547 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
551 EXPORT_SYMBOL_GPL(kvm_lmsw);
553 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
563 if (!(xcr0 & XSTATE_FP))
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
567 if (xcr0 & ~host_xcr0)
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
574 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
582 EXPORT_SYMBOL_GPL(kvm_set_xcr);
584 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
589 if (cr4 & CR4_RESERVED_BITS)
592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
601 if (is_long_mode(vcpu)) {
602 if (!(cr4 & X86_CR4_PAE))
604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
624 kvm_mmu_reset_context(vcpu);
626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627 kvm_update_cpuid(vcpu);
631 EXPORT_SYMBOL_GPL(kvm_set_cr4);
633 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
636 kvm_mmu_sync_roots(vcpu);
637 kvm_mmu_flush_tlb(vcpu);
641 if (is_long_mode(vcpu)) {
642 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
650 if (cr3 & CR3_PAE_RESERVED_BITS)
652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
673 vcpu->arch.cr3 = cr3;
674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
675 vcpu->arch.mmu.new_cr3(vcpu);
678 EXPORT_SYMBOL_GPL(kvm_set_cr3);
680 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
682 if (cr8 & CR8_RESERVED_BITS)
684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
687 vcpu->arch.cr8 = cr8;
690 EXPORT_SYMBOL_GPL(kvm_set_cr8);
692 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
697 return vcpu->arch.cr8;
699 EXPORT_SYMBOL_GPL(kvm_get_cr8);
701 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
705 vcpu->arch.db[dr] = val;
706 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
707 vcpu->arch.eff_db[dr] = val;
710 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 if (val & 0xffffffff00000000ULL)
716 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
719 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
723 if (val & 0xffffffff00000000ULL)
725 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
726 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
727 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
728 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
736 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
740 res = __kvm_set_dr(vcpu, dr, val);
742 kvm_queue_exception(vcpu, UD_VECTOR);
744 kvm_inject_gp(vcpu, 0);
748 EXPORT_SYMBOL_GPL(kvm_set_dr);
750 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
754 *val = vcpu->arch.db[dr];
757 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
761 *val = vcpu->arch.dr6;
764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
768 *val = vcpu->arch.dr7;
775 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
777 if (_kvm_get_dr(vcpu, dr, val)) {
778 kvm_queue_exception(vcpu, UD_VECTOR);
783 EXPORT_SYMBOL_GPL(kvm_get_dr);
785 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
787 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
791 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
794 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
795 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
798 EXPORT_SYMBOL_GPL(kvm_rdpmc);
801 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
802 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
804 * This list is modified at module load time to reflect the
805 * capabilities of the host cpu. This capabilities test skips MSRs that are
806 * kvm-specific. Those are put in the beginning of the list.
809 #define KVM_SAVE_MSRS_BEGIN 9
810 static u32 msrs_to_save[] = {
811 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
812 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
813 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
814 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
816 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
819 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
821 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
824 static unsigned num_msrs_to_save;
826 static u32 emulated_msrs[] = {
827 MSR_IA32_TSCDEADLINE,
828 MSR_IA32_MISC_ENABLE,
833 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
835 u64 old_efer = vcpu->arch.efer;
837 if (efer & efer_reserved_bits)
841 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
844 if (efer & EFER_FFXSR) {
845 struct kvm_cpuid_entry2 *feat;
847 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
848 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
852 if (efer & EFER_SVME) {
853 struct kvm_cpuid_entry2 *feat;
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
856 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
861 efer |= vcpu->arch.efer & EFER_LMA;
863 kvm_x86_ops->set_efer(vcpu, efer);
865 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
867 /* Update reserved bits */
868 if ((efer ^ old_efer) & EFER_NX)
869 kvm_mmu_reset_context(vcpu);
874 void kvm_enable_efer_bits(u64 mask)
876 efer_reserved_bits &= ~mask;
878 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
882 * Writes msr value into into the appropriate "register".
883 * Returns 0 on success, non-0 otherwise.
884 * Assumes vcpu_load() was already called.
886 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
888 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
892 * Adapt set_msr() to msr_io()'s calling convention
894 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
896 return kvm_set_msr(vcpu, index, *data);
899 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
903 struct pvclock_wall_clock wc;
904 struct timespec boot;
909 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
914 ++version; /* first time write, random junk */
918 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
921 * The guest calculates current wall clock time by adding
922 * system time (updated by kvm_guest_time_update below) to the
923 * wall clock specified here. guest system time equals host
924 * system time for us, thus we must fill in host boot time here.
928 if (kvm->arch.kvmclock_offset) {
929 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
930 boot = timespec_sub(boot, ts);
932 wc.sec = boot.tv_sec;
933 wc.nsec = boot.tv_nsec;
934 wc.version = version;
936 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
939 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
942 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
944 uint32_t quotient, remainder;
946 /* Don't try to replace with do_div(), this one calculates
947 * "(dividend << 32) / divisor" */
949 : "=a" (quotient), "=d" (remainder)
950 : "0" (0), "1" (dividend), "r" (divisor) );
954 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
955 s8 *pshift, u32 *pmultiplier)
962 tps64 = base_khz * 1000LL;
963 scaled64 = scaled_khz * 1000LL;
964 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
969 tps32 = (uint32_t)tps64;
970 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
971 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
979 *pmultiplier = div_frac(scaled64, tps32);
981 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
982 __func__, base_khz, scaled_khz, shift, *pmultiplier);
985 static inline u64 get_kernel_ns(void)
989 WARN_ON(preemptible());
991 monotonic_to_bootbased(&ts);
992 return timespec_to_ns(&ts);
995 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
996 unsigned long max_tsc_khz;
998 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1000 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1001 vcpu->arch.virtual_tsc_shift);
1004 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1006 u64 v = (u64)khz * (1000000 + ppm);
1011 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1013 u32 thresh_lo, thresh_hi;
1014 int use_scaling = 0;
1016 /* Compute a scale to convert nanoseconds in TSC cycles */
1017 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1018 &vcpu->arch.virtual_tsc_shift,
1019 &vcpu->arch.virtual_tsc_mult);
1020 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1023 * Compute the variation in TSC rate which is acceptable
1024 * within the range of tolerance and decide if the
1025 * rate being applied is within that bounds of the hardware
1026 * rate. If so, no scaling or compensation need be done.
1028 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1029 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1030 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1031 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1034 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1037 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1039 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1040 vcpu->arch.virtual_tsc_mult,
1041 vcpu->arch.virtual_tsc_shift);
1042 tsc += vcpu->arch.this_tsc_write;
1046 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1048 struct kvm *kvm = vcpu->kvm;
1049 u64 offset, ns, elapsed;
1050 unsigned long flags;
1053 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1054 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1055 ns = get_kernel_ns();
1056 elapsed = ns - kvm->arch.last_tsc_nsec;
1058 /* n.b - signed multiplication and division required */
1059 usdiff = data - kvm->arch.last_tsc_write;
1060 #ifdef CONFIG_X86_64
1061 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1063 /* do_div() only does unsigned */
1064 asm("idivl %2; xor %%edx, %%edx"
1066 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1068 do_div(elapsed, 1000);
1074 * Special case: TSC write with a small delta (1 second) of virtual
1075 * cycle time against real time is interpreted as an attempt to
1076 * synchronize the CPU.
1078 * For a reliable TSC, we can match TSC offsets, and for an unstable
1079 * TSC, we add elapsed time in this computation. We could let the
1080 * compensation code attempt to catch up if we fall behind, but
1081 * it's better to try to match offsets from the beginning.
1083 if (usdiff < USEC_PER_SEC &&
1084 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1085 if (!check_tsc_unstable()) {
1086 offset = kvm->arch.cur_tsc_offset;
1087 pr_debug("kvm: matched tsc offset for %llu\n", data);
1089 u64 delta = nsec_to_cycles(vcpu, elapsed);
1091 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1092 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1096 * We split periods of matched TSC writes into generations.
1097 * For each generation, we track the original measured
1098 * nanosecond time, offset, and write, so if TSCs are in
1099 * sync, we can match exact offset, and if not, we can match
1100 * exact software computaion in compute_guest_tsc()
1102 * These values are tracked in kvm->arch.cur_xxx variables.
1104 kvm->arch.cur_tsc_generation++;
1105 kvm->arch.cur_tsc_nsec = ns;
1106 kvm->arch.cur_tsc_write = data;
1107 kvm->arch.cur_tsc_offset = offset;
1108 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1109 kvm->arch.cur_tsc_generation, data);
1113 * We also track th most recent recorded KHZ, write and time to
1114 * allow the matching interval to be extended at each write.
1116 kvm->arch.last_tsc_nsec = ns;
1117 kvm->arch.last_tsc_write = data;
1118 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1120 /* Reset of TSC must disable overshoot protection below */
1121 vcpu->arch.hv_clock.tsc_timestamp = 0;
1122 vcpu->arch.last_guest_tsc = data;
1124 /* Keep track of which generation this VCPU has synchronized to */
1125 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1126 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1127 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1129 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1130 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1133 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1135 static int kvm_guest_time_update(struct kvm_vcpu *v)
1137 unsigned long flags;
1138 struct kvm_vcpu_arch *vcpu = &v->arch;
1140 unsigned long this_tsc_khz;
1141 s64 kernel_ns, max_kernel_ns;
1144 /* Keep irq disabled to prevent changes to the clock */
1145 local_irq_save(flags);
1146 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1147 kernel_ns = get_kernel_ns();
1148 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1149 if (unlikely(this_tsc_khz == 0)) {
1150 local_irq_restore(flags);
1151 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1156 * We may have to catch up the TSC to match elapsed wall clock
1157 * time for two reasons, even if kvmclock is used.
1158 * 1) CPU could have been running below the maximum TSC rate
1159 * 2) Broken TSC compensation resets the base at each VCPU
1160 * entry to avoid unknown leaps of TSC even when running
1161 * again on the same CPU. This may cause apparent elapsed
1162 * time to disappear, and the guest to stand still or run
1165 if (vcpu->tsc_catchup) {
1166 u64 tsc = compute_guest_tsc(v, kernel_ns);
1167 if (tsc > tsc_timestamp) {
1168 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1169 tsc_timestamp = tsc;
1173 local_irq_restore(flags);
1175 if (!vcpu->time_page)
1179 * Time as measured by the TSC may go backwards when resetting the base
1180 * tsc_timestamp. The reason for this is that the TSC resolution is
1181 * higher than the resolution of the other clock scales. Thus, many
1182 * possible measurments of the TSC correspond to one measurement of any
1183 * other clock, and so a spread of values is possible. This is not a
1184 * problem for the computation of the nanosecond clock; with TSC rates
1185 * around 1GHZ, there can only be a few cycles which correspond to one
1186 * nanosecond value, and any path through this code will inevitably
1187 * take longer than that. However, with the kernel_ns value itself,
1188 * the precision may be much lower, down to HZ granularity. If the
1189 * first sampling of TSC against kernel_ns ends in the low part of the
1190 * range, and the second in the high end of the range, we can get:
1192 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1194 * As the sampling errors potentially range in the thousands of cycles,
1195 * it is possible such a time value has already been observed by the
1196 * guest. To protect against this, we must compute the system time as
1197 * observed by the guest and ensure the new system time is greater.
1200 if (vcpu->hv_clock.tsc_timestamp) {
1201 max_kernel_ns = vcpu->last_guest_tsc -
1202 vcpu->hv_clock.tsc_timestamp;
1203 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1204 vcpu->hv_clock.tsc_to_system_mul,
1205 vcpu->hv_clock.tsc_shift);
1206 max_kernel_ns += vcpu->last_kernel_ns;
1209 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1210 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1211 &vcpu->hv_clock.tsc_shift,
1212 &vcpu->hv_clock.tsc_to_system_mul);
1213 vcpu->hw_tsc_khz = this_tsc_khz;
1216 if (max_kernel_ns > kernel_ns)
1217 kernel_ns = max_kernel_ns;
1219 /* With all the info we got, fill in the values */
1220 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1221 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1222 vcpu->last_kernel_ns = kernel_ns;
1223 vcpu->last_guest_tsc = tsc_timestamp;
1224 vcpu->hv_clock.flags = 0;
1227 * The interface expects us to write an even number signaling that the
1228 * update is finished. Since the guest won't see the intermediate
1229 * state, we just increase by 2 at the end.
1231 vcpu->hv_clock.version += 2;
1233 shared_kaddr = kmap_atomic(vcpu->time_page);
1235 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1236 sizeof(vcpu->hv_clock));
1238 kunmap_atomic(shared_kaddr);
1240 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1244 static bool msr_mtrr_valid(unsigned msr)
1247 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1248 case MSR_MTRRfix64K_00000:
1249 case MSR_MTRRfix16K_80000:
1250 case MSR_MTRRfix16K_A0000:
1251 case MSR_MTRRfix4K_C0000:
1252 case MSR_MTRRfix4K_C8000:
1253 case MSR_MTRRfix4K_D0000:
1254 case MSR_MTRRfix4K_D8000:
1255 case MSR_MTRRfix4K_E0000:
1256 case MSR_MTRRfix4K_E8000:
1257 case MSR_MTRRfix4K_F0000:
1258 case MSR_MTRRfix4K_F8000:
1259 case MSR_MTRRdefType:
1260 case MSR_IA32_CR_PAT:
1268 static bool valid_pat_type(unsigned t)
1270 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1273 static bool valid_mtrr_type(unsigned t)
1275 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1278 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1282 if (!msr_mtrr_valid(msr))
1285 if (msr == MSR_IA32_CR_PAT) {
1286 for (i = 0; i < 8; i++)
1287 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1290 } else if (msr == MSR_MTRRdefType) {
1293 return valid_mtrr_type(data & 0xff);
1294 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1295 for (i = 0; i < 8 ; i++)
1296 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1301 /* variable MTRRs */
1302 return valid_mtrr_type(data & 0xff);
1305 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1307 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1309 if (!mtrr_valid(vcpu, msr, data))
1312 if (msr == MSR_MTRRdefType) {
1313 vcpu->arch.mtrr_state.def_type = data;
1314 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1315 } else if (msr == MSR_MTRRfix64K_00000)
1317 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1318 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1319 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1320 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1321 else if (msr == MSR_IA32_CR_PAT)
1322 vcpu->arch.pat = data;
1323 else { /* Variable MTRRs */
1324 int idx, is_mtrr_mask;
1327 idx = (msr - 0x200) / 2;
1328 is_mtrr_mask = msr - 0x200 - 2 * idx;
1331 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1334 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1338 kvm_mmu_reset_context(vcpu);
1342 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1344 u64 mcg_cap = vcpu->arch.mcg_cap;
1345 unsigned bank_num = mcg_cap & 0xff;
1348 case MSR_IA32_MCG_STATUS:
1349 vcpu->arch.mcg_status = data;
1351 case MSR_IA32_MCG_CTL:
1352 if (!(mcg_cap & MCG_CTL_P))
1354 if (data != 0 && data != ~(u64)0)
1356 vcpu->arch.mcg_ctl = data;
1359 if (msr >= MSR_IA32_MC0_CTL &&
1360 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1361 u32 offset = msr - MSR_IA32_MC0_CTL;
1362 /* only 0 or all 1s can be written to IA32_MCi_CTL
1363 * some Linux kernels though clear bit 10 in bank 4 to
1364 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1365 * this to avoid an uncatched #GP in the guest
1367 if ((offset & 0x3) == 0 &&
1368 data != 0 && (data | (1 << 10)) != ~(u64)0)
1370 vcpu->arch.mce_banks[offset] = data;
1378 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1380 struct kvm *kvm = vcpu->kvm;
1381 int lm = is_long_mode(vcpu);
1382 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1383 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1384 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1385 : kvm->arch.xen_hvm_config.blob_size_32;
1386 u32 page_num = data & ~PAGE_MASK;
1387 u64 page_addr = data & PAGE_MASK;
1392 if (page_num >= blob_size)
1395 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1400 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1409 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1411 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1414 static bool kvm_hv_msr_partition_wide(u32 msr)
1418 case HV_X64_MSR_GUEST_OS_ID:
1419 case HV_X64_MSR_HYPERCALL:
1427 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1429 struct kvm *kvm = vcpu->kvm;
1432 case HV_X64_MSR_GUEST_OS_ID:
1433 kvm->arch.hv_guest_os_id = data;
1434 /* setting guest os id to zero disables hypercall page */
1435 if (!kvm->arch.hv_guest_os_id)
1436 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1438 case HV_X64_MSR_HYPERCALL: {
1443 /* if guest os id is not set hypercall should remain disabled */
1444 if (!kvm->arch.hv_guest_os_id)
1446 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1447 kvm->arch.hv_hypercall = data;
1450 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1451 addr = gfn_to_hva(kvm, gfn);
1452 if (kvm_is_error_hva(addr))
1454 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1455 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1456 if (__copy_to_user((void __user *)addr, instructions, 4))
1458 kvm->arch.hv_hypercall = data;
1462 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1463 "data 0x%llx\n", msr, data);
1469 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1472 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1475 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1476 vcpu->arch.hv_vapic = data;
1479 addr = gfn_to_hva(vcpu->kvm, data >>
1480 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1481 if (kvm_is_error_hva(addr))
1483 if (__clear_user((void __user *)addr, PAGE_SIZE))
1485 vcpu->arch.hv_vapic = data;
1488 case HV_X64_MSR_EOI:
1489 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1490 case HV_X64_MSR_ICR:
1491 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1492 case HV_X64_MSR_TPR:
1493 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1495 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1496 "data 0x%llx\n", msr, data);
1503 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1505 gpa_t gpa = data & ~0x3f;
1507 /* Bits 2:5 are resrved, Should be zero */
1511 vcpu->arch.apf.msr_val = data;
1513 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1514 kvm_clear_async_pf_completion_queue(vcpu);
1515 kvm_async_pf_hash_reset(vcpu);
1519 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1522 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1523 kvm_async_pf_wakeup_all(vcpu);
1527 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1529 if (vcpu->arch.time_page) {
1530 kvm_release_page_dirty(vcpu->arch.time_page);
1531 vcpu->arch.time_page = NULL;
1535 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1539 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1542 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1543 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1544 vcpu->arch.st.accum_steal = delta;
1547 static void record_steal_time(struct kvm_vcpu *vcpu)
1549 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1552 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1553 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1556 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1557 vcpu->arch.st.steal.version += 2;
1558 vcpu->arch.st.accum_steal = 0;
1560 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1561 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1564 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1570 return set_efer(vcpu, data);
1572 data &= ~(u64)0x40; /* ignore flush filter disable */
1573 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1574 data &= ~(u64)0x8; /* ignore TLB cache disable */
1576 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1581 case MSR_FAM10H_MMIO_CONF_BASE:
1583 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1588 case MSR_AMD64_NB_CFG:
1590 case MSR_IA32_DEBUGCTLMSR:
1592 /* We support the non-activated case already */
1594 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1595 /* Values other than LBR and BTF are vendor-specific,
1596 thus reserved and should throw a #GP */
1599 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1602 case MSR_IA32_UCODE_REV:
1603 case MSR_IA32_UCODE_WRITE:
1604 case MSR_VM_HSAVE_PA:
1605 case MSR_AMD64_PATCH_LOADER:
1607 case 0x200 ... 0x2ff:
1608 return set_msr_mtrr(vcpu, msr, data);
1609 case MSR_IA32_APICBASE:
1610 kvm_set_apic_base(vcpu, data);
1612 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1613 return kvm_x2apic_msr_write(vcpu, msr, data);
1614 case MSR_IA32_TSCDEADLINE:
1615 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1617 case MSR_IA32_MISC_ENABLE:
1618 vcpu->arch.ia32_misc_enable_msr = data;
1620 case MSR_KVM_WALL_CLOCK_NEW:
1621 case MSR_KVM_WALL_CLOCK:
1622 vcpu->kvm->arch.wall_clock = data;
1623 kvm_write_wall_clock(vcpu->kvm, data);
1625 case MSR_KVM_SYSTEM_TIME_NEW:
1626 case MSR_KVM_SYSTEM_TIME: {
1627 kvmclock_reset(vcpu);
1629 vcpu->arch.time = data;
1630 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1632 /* we verify if the enable bit is set... */
1636 /* ...but clean it before doing the actual write */
1637 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1639 vcpu->arch.time_page =
1640 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1642 if (is_error_page(vcpu->arch.time_page)) {
1643 kvm_release_page_clean(vcpu->arch.time_page);
1644 vcpu->arch.time_page = NULL;
1648 case MSR_KVM_ASYNC_PF_EN:
1649 if (kvm_pv_enable_async_pf(vcpu, data))
1652 case MSR_KVM_STEAL_TIME:
1654 if (unlikely(!sched_info_on()))
1657 if (data & KVM_STEAL_RESERVED_MASK)
1660 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1661 data & KVM_STEAL_VALID_BITS))
1664 vcpu->arch.st.msr_val = data;
1666 if (!(data & KVM_MSR_ENABLED))
1669 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1672 accumulate_steal_time(vcpu);
1675 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1678 case MSR_KVM_PV_EOI_EN:
1679 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1683 case MSR_IA32_MCG_CTL:
1684 case MSR_IA32_MCG_STATUS:
1685 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1686 return set_msr_mce(vcpu, msr, data);
1688 /* Performance counters are not protected by a CPUID bit,
1689 * so we should check all of them in the generic path for the sake of
1690 * cross vendor migration.
1691 * Writing a zero into the event select MSRs disables them,
1692 * which we perfectly emulate ;-). Any other value should be at least
1693 * reported, some guests depend on them.
1695 case MSR_K7_EVNTSEL0:
1696 case MSR_K7_EVNTSEL1:
1697 case MSR_K7_EVNTSEL2:
1698 case MSR_K7_EVNTSEL3:
1700 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1701 "0x%x data 0x%llx\n", msr, data);
1703 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1704 * so we ignore writes to make it happy.
1706 case MSR_K7_PERFCTR0:
1707 case MSR_K7_PERFCTR1:
1708 case MSR_K7_PERFCTR2:
1709 case MSR_K7_PERFCTR3:
1710 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1711 "0x%x data 0x%llx\n", msr, data);
1713 case MSR_P6_PERFCTR0:
1714 case MSR_P6_PERFCTR1:
1716 case MSR_P6_EVNTSEL0:
1717 case MSR_P6_EVNTSEL1:
1718 if (kvm_pmu_msr(vcpu, msr))
1719 return kvm_pmu_set_msr(vcpu, msr, data);
1721 if (pr || data != 0)
1722 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1723 "0x%x data 0x%llx\n", msr, data);
1725 case MSR_K7_CLK_CTL:
1727 * Ignore all writes to this no longer documented MSR.
1728 * Writes are only relevant for old K7 processors,
1729 * all pre-dating SVM, but a recommended workaround from
1730 * AMD for these chips. It is possible to speicify the
1731 * affected processor models on the command line, hence
1732 * the need to ignore the workaround.
1735 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1736 if (kvm_hv_msr_partition_wide(msr)) {
1738 mutex_lock(&vcpu->kvm->lock);
1739 r = set_msr_hyperv_pw(vcpu, msr, data);
1740 mutex_unlock(&vcpu->kvm->lock);
1743 return set_msr_hyperv(vcpu, msr, data);
1745 case MSR_IA32_BBL_CR_CTL3:
1746 /* Drop writes to this legacy MSR -- see rdmsr
1747 * counterpart for further detail.
1749 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1751 case MSR_AMD64_OSVW_ID_LENGTH:
1752 if (!guest_cpuid_has_osvw(vcpu))
1754 vcpu->arch.osvw.length = data;
1756 case MSR_AMD64_OSVW_STATUS:
1757 if (!guest_cpuid_has_osvw(vcpu))
1759 vcpu->arch.osvw.status = data;
1762 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1763 return xen_hvm_config(vcpu, data);
1764 if (kvm_pmu_msr(vcpu, msr))
1765 return kvm_pmu_set_msr(vcpu, msr, data);
1767 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1771 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1778 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1782 * Reads an msr value (of 'msr_index') into 'pdata'.
1783 * Returns 0 on success, non-0 otherwise.
1784 * Assumes vcpu_load() was already called.
1786 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1788 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1791 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1793 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1795 if (!msr_mtrr_valid(msr))
1798 if (msr == MSR_MTRRdefType)
1799 *pdata = vcpu->arch.mtrr_state.def_type +
1800 (vcpu->arch.mtrr_state.enabled << 10);
1801 else if (msr == MSR_MTRRfix64K_00000)
1803 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1804 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1805 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1806 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1807 else if (msr == MSR_IA32_CR_PAT)
1808 *pdata = vcpu->arch.pat;
1809 else { /* Variable MTRRs */
1810 int idx, is_mtrr_mask;
1813 idx = (msr - 0x200) / 2;
1814 is_mtrr_mask = msr - 0x200 - 2 * idx;
1817 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1820 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1827 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1830 u64 mcg_cap = vcpu->arch.mcg_cap;
1831 unsigned bank_num = mcg_cap & 0xff;
1834 case MSR_IA32_P5_MC_ADDR:
1835 case MSR_IA32_P5_MC_TYPE:
1838 case MSR_IA32_MCG_CAP:
1839 data = vcpu->arch.mcg_cap;
1841 case MSR_IA32_MCG_CTL:
1842 if (!(mcg_cap & MCG_CTL_P))
1844 data = vcpu->arch.mcg_ctl;
1846 case MSR_IA32_MCG_STATUS:
1847 data = vcpu->arch.mcg_status;
1850 if (msr >= MSR_IA32_MC0_CTL &&
1851 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1852 u32 offset = msr - MSR_IA32_MC0_CTL;
1853 data = vcpu->arch.mce_banks[offset];
1862 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1865 struct kvm *kvm = vcpu->kvm;
1868 case HV_X64_MSR_GUEST_OS_ID:
1869 data = kvm->arch.hv_guest_os_id;
1871 case HV_X64_MSR_HYPERCALL:
1872 data = kvm->arch.hv_hypercall;
1875 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1883 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1888 case HV_X64_MSR_VP_INDEX: {
1891 kvm_for_each_vcpu(r, v, vcpu->kvm)
1896 case HV_X64_MSR_EOI:
1897 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1898 case HV_X64_MSR_ICR:
1899 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1900 case HV_X64_MSR_TPR:
1901 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1902 case HV_X64_MSR_APIC_ASSIST_PAGE:
1903 data = vcpu->arch.hv_vapic;
1906 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1913 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1918 case MSR_IA32_PLATFORM_ID:
1919 case MSR_IA32_EBL_CR_POWERON:
1920 case MSR_IA32_DEBUGCTLMSR:
1921 case MSR_IA32_LASTBRANCHFROMIP:
1922 case MSR_IA32_LASTBRANCHTOIP:
1923 case MSR_IA32_LASTINTFROMIP:
1924 case MSR_IA32_LASTINTTOIP:
1927 case MSR_VM_HSAVE_PA:
1928 case MSR_K7_EVNTSEL0:
1929 case MSR_K7_PERFCTR0:
1930 case MSR_K8_INT_PENDING_MSG:
1931 case MSR_AMD64_NB_CFG:
1932 case MSR_FAM10H_MMIO_CONF_BASE:
1935 case MSR_P6_PERFCTR0:
1936 case MSR_P6_PERFCTR1:
1937 case MSR_P6_EVNTSEL0:
1938 case MSR_P6_EVNTSEL1:
1939 if (kvm_pmu_msr(vcpu, msr))
1940 return kvm_pmu_get_msr(vcpu, msr, pdata);
1943 case MSR_IA32_UCODE_REV:
1944 data = 0x100000000ULL;
1947 data = 0x500 | KVM_NR_VAR_MTRR;
1949 case 0x200 ... 0x2ff:
1950 return get_msr_mtrr(vcpu, msr, pdata);
1951 case 0xcd: /* fsb frequency */
1955 * MSR_EBC_FREQUENCY_ID
1956 * Conservative value valid for even the basic CPU models.
1957 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1958 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1959 * and 266MHz for model 3, or 4. Set Core Clock
1960 * Frequency to System Bus Frequency Ratio to 1 (bits
1961 * 31:24) even though these are only valid for CPU
1962 * models > 2, however guests may end up dividing or
1963 * multiplying by zero otherwise.
1965 case MSR_EBC_FREQUENCY_ID:
1968 case MSR_IA32_APICBASE:
1969 data = kvm_get_apic_base(vcpu);
1971 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1972 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1974 case MSR_IA32_TSCDEADLINE:
1975 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1977 case MSR_IA32_MISC_ENABLE:
1978 data = vcpu->arch.ia32_misc_enable_msr;
1980 case MSR_IA32_PERF_STATUS:
1981 /* TSC increment by tick */
1983 /* CPU multiplier */
1984 data |= (((uint64_t)4ULL) << 40);
1987 data = vcpu->arch.efer;
1989 case MSR_KVM_WALL_CLOCK:
1990 case MSR_KVM_WALL_CLOCK_NEW:
1991 data = vcpu->kvm->arch.wall_clock;
1993 case MSR_KVM_SYSTEM_TIME:
1994 case MSR_KVM_SYSTEM_TIME_NEW:
1995 data = vcpu->arch.time;
1997 case MSR_KVM_ASYNC_PF_EN:
1998 data = vcpu->arch.apf.msr_val;
2000 case MSR_KVM_STEAL_TIME:
2001 data = vcpu->arch.st.msr_val;
2003 case MSR_IA32_P5_MC_ADDR:
2004 case MSR_IA32_P5_MC_TYPE:
2005 case MSR_IA32_MCG_CAP:
2006 case MSR_IA32_MCG_CTL:
2007 case MSR_IA32_MCG_STATUS:
2008 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2009 return get_msr_mce(vcpu, msr, pdata);
2010 case MSR_K7_CLK_CTL:
2012 * Provide expected ramp-up count for K7. All other
2013 * are set to zero, indicating minimum divisors for
2016 * This prevents guest kernels on AMD host with CPU
2017 * type 6, model 8 and higher from exploding due to
2018 * the rdmsr failing.
2022 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2023 if (kvm_hv_msr_partition_wide(msr)) {
2025 mutex_lock(&vcpu->kvm->lock);
2026 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2027 mutex_unlock(&vcpu->kvm->lock);
2030 return get_msr_hyperv(vcpu, msr, pdata);
2032 case MSR_IA32_BBL_CR_CTL3:
2033 /* This legacy MSR exists but isn't fully documented in current
2034 * silicon. It is however accessed by winxp in very narrow
2035 * scenarios where it sets bit #19, itself documented as
2036 * a "reserved" bit. Best effort attempt to source coherent
2037 * read data here should the balance of the register be
2038 * interpreted by the guest:
2040 * L2 cache control register 3: 64GB range, 256KB size,
2041 * enabled, latency 0x1, configured
2045 case MSR_AMD64_OSVW_ID_LENGTH:
2046 if (!guest_cpuid_has_osvw(vcpu))
2048 data = vcpu->arch.osvw.length;
2050 case MSR_AMD64_OSVW_STATUS:
2051 if (!guest_cpuid_has_osvw(vcpu))
2053 data = vcpu->arch.osvw.status;
2056 if (kvm_pmu_msr(vcpu, msr))
2057 return kvm_pmu_get_msr(vcpu, msr, pdata);
2059 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2062 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2070 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2073 * Read or write a bunch of msrs. All parameters are kernel addresses.
2075 * @return number of msrs set successfully.
2077 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2078 struct kvm_msr_entry *entries,
2079 int (*do_msr)(struct kvm_vcpu *vcpu,
2080 unsigned index, u64 *data))
2084 idx = srcu_read_lock(&vcpu->kvm->srcu);
2085 for (i = 0; i < msrs->nmsrs; ++i)
2086 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2088 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2094 * Read or write a bunch of msrs. Parameters are user addresses.
2096 * @return number of msrs set successfully.
2098 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2099 int (*do_msr)(struct kvm_vcpu *vcpu,
2100 unsigned index, u64 *data),
2103 struct kvm_msrs msrs;
2104 struct kvm_msr_entry *entries;
2109 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2113 if (msrs.nmsrs >= MAX_IO_MSRS)
2116 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2117 entries = memdup_user(user_msrs->entries, size);
2118 if (IS_ERR(entries)) {
2119 r = PTR_ERR(entries);
2123 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2128 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2139 int kvm_dev_ioctl_check_extension(long ext)
2144 case KVM_CAP_IRQCHIP:
2146 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2147 case KVM_CAP_SET_TSS_ADDR:
2148 case KVM_CAP_EXT_CPUID:
2149 case KVM_CAP_CLOCKSOURCE:
2151 case KVM_CAP_NOP_IO_DELAY:
2152 case KVM_CAP_MP_STATE:
2153 case KVM_CAP_SYNC_MMU:
2154 case KVM_CAP_USER_NMI:
2155 case KVM_CAP_REINJECT_CONTROL:
2156 case KVM_CAP_IRQ_INJECT_STATUS:
2157 case KVM_CAP_ASSIGN_DEV_IRQ:
2159 case KVM_CAP_IOEVENTFD:
2161 case KVM_CAP_PIT_STATE2:
2162 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2163 case KVM_CAP_XEN_HVM:
2164 case KVM_CAP_ADJUST_CLOCK:
2165 case KVM_CAP_VCPU_EVENTS:
2166 case KVM_CAP_HYPERV:
2167 case KVM_CAP_HYPERV_VAPIC:
2168 case KVM_CAP_HYPERV_SPIN:
2169 case KVM_CAP_PCI_SEGMENT:
2170 case KVM_CAP_DEBUGREGS:
2171 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2173 case KVM_CAP_ASYNC_PF:
2174 case KVM_CAP_GET_TSC_KHZ:
2175 case KVM_CAP_PCI_2_3:
2176 case KVM_CAP_KVMCLOCK_CTRL:
2179 case KVM_CAP_COALESCED_MMIO:
2180 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2183 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2185 case KVM_CAP_NR_VCPUS:
2186 r = KVM_SOFT_MAX_VCPUS;
2188 case KVM_CAP_MAX_VCPUS:
2191 case KVM_CAP_NR_MEMSLOTS:
2192 r = KVM_MEMORY_SLOTS;
2194 case KVM_CAP_PV_MMU: /* obsolete */
2198 r = iommu_present(&pci_bus_type);
2201 r = KVM_MAX_MCE_BANKS;
2206 case KVM_CAP_TSC_CONTROL:
2207 r = kvm_has_tsc_control;
2209 case KVM_CAP_TSC_DEADLINE_TIMER:
2210 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2220 long kvm_arch_dev_ioctl(struct file *filp,
2221 unsigned int ioctl, unsigned long arg)
2223 void __user *argp = (void __user *)arg;
2227 case KVM_GET_MSR_INDEX_LIST: {
2228 struct kvm_msr_list __user *user_msr_list = argp;
2229 struct kvm_msr_list msr_list;
2233 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2236 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2237 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2240 if (n < msr_list.nmsrs)
2243 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2244 num_msrs_to_save * sizeof(u32)))
2246 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2248 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2253 case KVM_GET_SUPPORTED_CPUID: {
2254 struct kvm_cpuid2 __user *cpuid_arg = argp;
2255 struct kvm_cpuid2 cpuid;
2258 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2260 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2261 cpuid_arg->entries);
2266 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2271 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2274 mce_cap = KVM_MCE_CAP_SUPPORTED;
2276 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2288 static void wbinvd_ipi(void *garbage)
2293 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2295 return vcpu->kvm->arch.iommu_domain &&
2296 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2299 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2301 /* Address WBINVD may be executed by guest */
2302 if (need_emulate_wbinvd(vcpu)) {
2303 if (kvm_x86_ops->has_wbinvd_exit())
2304 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2305 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2306 smp_call_function_single(vcpu->cpu,
2307 wbinvd_ipi, NULL, 1);
2310 kvm_x86_ops->vcpu_load(vcpu, cpu);
2312 /* Apply any externally detected TSC adjustments (due to suspend) */
2313 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2314 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2315 vcpu->arch.tsc_offset_adjustment = 0;
2316 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2319 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2320 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2321 native_read_tsc() - vcpu->arch.last_host_tsc;
2323 mark_tsc_unstable("KVM discovered backwards TSC");
2324 if (check_tsc_unstable()) {
2325 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2326 vcpu->arch.last_guest_tsc);
2327 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2328 vcpu->arch.tsc_catchup = 1;
2330 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2331 if (vcpu->cpu != cpu)
2332 kvm_migrate_timers(vcpu);
2336 accumulate_steal_time(vcpu);
2337 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2340 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2342 kvm_x86_ops->vcpu_put(vcpu);
2343 kvm_put_guest_fpu(vcpu);
2344 vcpu->arch.last_host_tsc = native_read_tsc();
2347 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2348 struct kvm_lapic_state *s)
2350 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2355 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2356 struct kvm_lapic_state *s)
2358 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2359 kvm_apic_post_state_restore(vcpu);
2360 update_cr8_intercept(vcpu);
2365 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2366 struct kvm_interrupt *irq)
2368 if (irq->irq < 0 || irq->irq >= 256)
2370 if (irqchip_in_kernel(vcpu->kvm))
2373 kvm_queue_interrupt(vcpu, irq->irq, false);
2374 kvm_make_request(KVM_REQ_EVENT, vcpu);
2379 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2381 kvm_inject_nmi(vcpu);
2386 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2387 struct kvm_tpr_access_ctl *tac)
2391 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2395 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2399 unsigned bank_num = mcg_cap & 0xff, bank;
2402 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2404 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2407 vcpu->arch.mcg_cap = mcg_cap;
2408 /* Init IA32_MCG_CTL to all 1s */
2409 if (mcg_cap & MCG_CTL_P)
2410 vcpu->arch.mcg_ctl = ~(u64)0;
2411 /* Init IA32_MCi_CTL to all 1s */
2412 for (bank = 0; bank < bank_num; bank++)
2413 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2418 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2419 struct kvm_x86_mce *mce)
2421 u64 mcg_cap = vcpu->arch.mcg_cap;
2422 unsigned bank_num = mcg_cap & 0xff;
2423 u64 *banks = vcpu->arch.mce_banks;
2425 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2428 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2429 * reporting is disabled
2431 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2432 vcpu->arch.mcg_ctl != ~(u64)0)
2434 banks += 4 * mce->bank;
2436 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2437 * reporting is disabled for the bank
2439 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2441 if (mce->status & MCI_STATUS_UC) {
2442 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2443 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2444 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2447 if (banks[1] & MCI_STATUS_VAL)
2448 mce->status |= MCI_STATUS_OVER;
2449 banks[2] = mce->addr;
2450 banks[3] = mce->misc;
2451 vcpu->arch.mcg_status = mce->mcg_status;
2452 banks[1] = mce->status;
2453 kvm_queue_exception(vcpu, MC_VECTOR);
2454 } else if (!(banks[1] & MCI_STATUS_VAL)
2455 || !(banks[1] & MCI_STATUS_UC)) {
2456 if (banks[1] & MCI_STATUS_VAL)
2457 mce->status |= MCI_STATUS_OVER;
2458 banks[2] = mce->addr;
2459 banks[3] = mce->misc;
2460 banks[1] = mce->status;
2462 banks[1] |= MCI_STATUS_OVER;
2466 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2467 struct kvm_vcpu_events *events)
2470 events->exception.injected =
2471 vcpu->arch.exception.pending &&
2472 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2473 events->exception.nr = vcpu->arch.exception.nr;
2474 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2475 events->exception.pad = 0;
2476 events->exception.error_code = vcpu->arch.exception.error_code;
2478 events->interrupt.injected =
2479 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2480 events->interrupt.nr = vcpu->arch.interrupt.nr;
2481 events->interrupt.soft = 0;
2482 events->interrupt.shadow =
2483 kvm_x86_ops->get_interrupt_shadow(vcpu,
2484 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2486 events->nmi.injected = vcpu->arch.nmi_injected;
2487 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2488 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2489 events->nmi.pad = 0;
2491 events->sipi_vector = vcpu->arch.sipi_vector;
2493 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2494 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2495 | KVM_VCPUEVENT_VALID_SHADOW);
2496 memset(&events->reserved, 0, sizeof(events->reserved));
2499 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2500 struct kvm_vcpu_events *events)
2502 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2503 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2504 | KVM_VCPUEVENT_VALID_SHADOW))
2508 vcpu->arch.exception.pending = events->exception.injected;
2509 vcpu->arch.exception.nr = events->exception.nr;
2510 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2511 vcpu->arch.exception.error_code = events->exception.error_code;
2513 vcpu->arch.interrupt.pending = events->interrupt.injected;
2514 vcpu->arch.interrupt.nr = events->interrupt.nr;
2515 vcpu->arch.interrupt.soft = events->interrupt.soft;
2516 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2517 kvm_x86_ops->set_interrupt_shadow(vcpu,
2518 events->interrupt.shadow);
2520 vcpu->arch.nmi_injected = events->nmi.injected;
2521 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2522 vcpu->arch.nmi_pending = events->nmi.pending;
2523 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2525 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2526 vcpu->arch.sipi_vector = events->sipi_vector;
2528 kvm_make_request(KVM_REQ_EVENT, vcpu);
2533 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2534 struct kvm_debugregs *dbgregs)
2536 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2537 dbgregs->dr6 = vcpu->arch.dr6;
2538 dbgregs->dr7 = vcpu->arch.dr7;
2540 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2543 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2544 struct kvm_debugregs *dbgregs)
2549 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2550 vcpu->arch.dr6 = dbgregs->dr6;
2551 vcpu->arch.dr7 = dbgregs->dr7;
2556 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2557 struct kvm_xsave *guest_xsave)
2560 memcpy(guest_xsave->region,
2561 &vcpu->arch.guest_fpu.state->xsave,
2564 memcpy(guest_xsave->region,
2565 &vcpu->arch.guest_fpu.state->fxsave,
2566 sizeof(struct i387_fxsave_struct));
2567 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2572 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2573 struct kvm_xsave *guest_xsave)
2576 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2579 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2580 guest_xsave->region, xstate_size);
2582 if (xstate_bv & ~XSTATE_FPSSE)
2584 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2585 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2590 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2591 struct kvm_xcrs *guest_xcrs)
2593 if (!cpu_has_xsave) {
2594 guest_xcrs->nr_xcrs = 0;
2598 guest_xcrs->nr_xcrs = 1;
2599 guest_xcrs->flags = 0;
2600 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2601 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2604 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2605 struct kvm_xcrs *guest_xcrs)
2612 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2615 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2616 /* Only support XCR0 currently */
2617 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2618 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2619 guest_xcrs->xcrs[0].value);
2628 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2629 * stopped by the hypervisor. This function will be called from the host only.
2630 * EINVAL is returned when the host attempts to set the flag for a guest that
2631 * does not support pv clocks.
2633 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2635 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2636 if (!vcpu->arch.time_page)
2638 src->flags |= PVCLOCK_GUEST_STOPPED;
2639 mark_page_dirty(vcpu->kvm, vcpu->arch.time >> PAGE_SHIFT);
2640 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2644 long kvm_arch_vcpu_ioctl(struct file *filp,
2645 unsigned int ioctl, unsigned long arg)
2647 struct kvm_vcpu *vcpu = filp->private_data;
2648 void __user *argp = (void __user *)arg;
2651 struct kvm_lapic_state *lapic;
2652 struct kvm_xsave *xsave;
2653 struct kvm_xcrs *xcrs;
2659 case KVM_GET_LAPIC: {
2661 if (!vcpu->arch.apic)
2663 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2668 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2672 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2677 case KVM_SET_LAPIC: {
2679 if (!vcpu->arch.apic)
2681 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2682 if (IS_ERR(u.lapic)) {
2683 r = PTR_ERR(u.lapic);
2687 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2693 case KVM_INTERRUPT: {
2694 struct kvm_interrupt irq;
2697 if (copy_from_user(&irq, argp, sizeof irq))
2699 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2706 r = kvm_vcpu_ioctl_nmi(vcpu);
2712 case KVM_SET_CPUID: {
2713 struct kvm_cpuid __user *cpuid_arg = argp;
2714 struct kvm_cpuid cpuid;
2717 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2719 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2724 case KVM_SET_CPUID2: {
2725 struct kvm_cpuid2 __user *cpuid_arg = argp;
2726 struct kvm_cpuid2 cpuid;
2729 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2731 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2732 cpuid_arg->entries);
2737 case KVM_GET_CPUID2: {
2738 struct kvm_cpuid2 __user *cpuid_arg = argp;
2739 struct kvm_cpuid2 cpuid;
2742 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2744 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2745 cpuid_arg->entries);
2749 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2755 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2758 r = msr_io(vcpu, argp, do_set_msr, 0);
2760 case KVM_TPR_ACCESS_REPORTING: {
2761 struct kvm_tpr_access_ctl tac;
2764 if (copy_from_user(&tac, argp, sizeof tac))
2766 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2770 if (copy_to_user(argp, &tac, sizeof tac))
2775 case KVM_SET_VAPIC_ADDR: {
2776 struct kvm_vapic_addr va;
2779 if (!irqchip_in_kernel(vcpu->kvm))
2782 if (copy_from_user(&va, argp, sizeof va))
2785 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2788 case KVM_X86_SETUP_MCE: {
2792 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2794 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2797 case KVM_X86_SET_MCE: {
2798 struct kvm_x86_mce mce;
2801 if (copy_from_user(&mce, argp, sizeof mce))
2803 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2806 case KVM_GET_VCPU_EVENTS: {
2807 struct kvm_vcpu_events events;
2809 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2812 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2817 case KVM_SET_VCPU_EVENTS: {
2818 struct kvm_vcpu_events events;
2821 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2824 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2827 case KVM_GET_DEBUGREGS: {
2828 struct kvm_debugregs dbgregs;
2830 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2833 if (copy_to_user(argp, &dbgregs,
2834 sizeof(struct kvm_debugregs)))
2839 case KVM_SET_DEBUGREGS: {
2840 struct kvm_debugregs dbgregs;
2843 if (copy_from_user(&dbgregs, argp,
2844 sizeof(struct kvm_debugregs)))
2847 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2850 case KVM_GET_XSAVE: {
2851 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2856 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2859 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2864 case KVM_SET_XSAVE: {
2865 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2866 if (IS_ERR(u.xsave)) {
2867 r = PTR_ERR(u.xsave);
2871 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2874 case KVM_GET_XCRS: {
2875 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2880 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2883 if (copy_to_user(argp, u.xcrs,
2884 sizeof(struct kvm_xcrs)))
2889 case KVM_SET_XCRS: {
2890 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2891 if (IS_ERR(u.xcrs)) {
2892 r = PTR_ERR(u.xcrs);
2896 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2899 case KVM_SET_TSC_KHZ: {
2903 user_tsc_khz = (u32)arg;
2905 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2908 if (user_tsc_khz == 0)
2909 user_tsc_khz = tsc_khz;
2911 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2916 case KVM_GET_TSC_KHZ: {
2917 r = vcpu->arch.virtual_tsc_khz;
2920 case KVM_KVMCLOCK_CTRL: {
2921 r = kvm_set_guest_paused(vcpu);
2932 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2934 return VM_FAULT_SIGBUS;
2937 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2941 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2943 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2947 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2950 kvm->arch.ept_identity_map_addr = ident_addr;
2954 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2955 u32 kvm_nr_mmu_pages)
2957 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2960 mutex_lock(&kvm->slots_lock);
2961 spin_lock(&kvm->mmu_lock);
2963 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2964 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2966 spin_unlock(&kvm->mmu_lock);
2967 mutex_unlock(&kvm->slots_lock);
2971 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2973 return kvm->arch.n_max_mmu_pages;
2976 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2981 switch (chip->chip_id) {
2982 case KVM_IRQCHIP_PIC_MASTER:
2983 memcpy(&chip->chip.pic,
2984 &pic_irqchip(kvm)->pics[0],
2985 sizeof(struct kvm_pic_state));
2987 case KVM_IRQCHIP_PIC_SLAVE:
2988 memcpy(&chip->chip.pic,
2989 &pic_irqchip(kvm)->pics[1],
2990 sizeof(struct kvm_pic_state));
2992 case KVM_IRQCHIP_IOAPIC:
2993 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3002 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3007 switch (chip->chip_id) {
3008 case KVM_IRQCHIP_PIC_MASTER:
3009 spin_lock(&pic_irqchip(kvm)->lock);
3010 memcpy(&pic_irqchip(kvm)->pics[0],
3012 sizeof(struct kvm_pic_state));
3013 spin_unlock(&pic_irqchip(kvm)->lock);
3015 case KVM_IRQCHIP_PIC_SLAVE:
3016 spin_lock(&pic_irqchip(kvm)->lock);
3017 memcpy(&pic_irqchip(kvm)->pics[1],
3019 sizeof(struct kvm_pic_state));
3020 spin_unlock(&pic_irqchip(kvm)->lock);
3022 case KVM_IRQCHIP_IOAPIC:
3023 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3029 kvm_pic_update_irq(pic_irqchip(kvm));
3033 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3037 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3038 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3039 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3043 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3047 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3048 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3049 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3050 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3054 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3058 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3059 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3060 sizeof(ps->channels));
3061 ps->flags = kvm->arch.vpit->pit_state.flags;
3062 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3063 memset(&ps->reserved, 0, sizeof(ps->reserved));
3067 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3069 int r = 0, start = 0;
3070 u32 prev_legacy, cur_legacy;
3071 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3072 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3073 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3074 if (!prev_legacy && cur_legacy)
3076 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3077 sizeof(kvm->arch.vpit->pit_state.channels));
3078 kvm->arch.vpit->pit_state.flags = ps->flags;
3079 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3080 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3084 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3085 struct kvm_reinject_control *control)
3087 if (!kvm->arch.vpit)
3089 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3090 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3091 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3096 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3097 * @kvm: kvm instance
3098 * @log: slot id and address to which we copy the log
3100 * We need to keep it in mind that VCPU threads can write to the bitmap
3101 * concurrently. So, to avoid losing data, we keep the following order for
3104 * 1. Take a snapshot of the bit and clear it if needed.
3105 * 2. Write protect the corresponding page.
3106 * 3. Flush TLB's if needed.
3107 * 4. Copy the snapshot to the userspace.
3109 * Between 2 and 3, the guest may write to the page using the remaining TLB
3110 * entry. This is not a problem because the page will be reported dirty at
3111 * step 4 using the snapshot taken before and step 3 ensures that successive
3112 * writes will be logged for the next call.
3114 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3117 struct kvm_memory_slot *memslot;
3119 unsigned long *dirty_bitmap;
3120 unsigned long *dirty_bitmap_buffer;
3121 bool is_dirty = false;
3123 mutex_lock(&kvm->slots_lock);
3126 if (log->slot >= KVM_MEMORY_SLOTS)
3129 memslot = id_to_memslot(kvm->memslots, log->slot);
3131 dirty_bitmap = memslot->dirty_bitmap;
3136 n = kvm_dirty_bitmap_bytes(memslot);
3138 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3139 memset(dirty_bitmap_buffer, 0, n);
3141 spin_lock(&kvm->mmu_lock);
3143 for (i = 0; i < n / sizeof(long); i++) {
3147 if (!dirty_bitmap[i])
3152 mask = xchg(&dirty_bitmap[i], 0);
3153 dirty_bitmap_buffer[i] = mask;
3155 offset = i * BITS_PER_LONG;
3156 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3159 kvm_flush_remote_tlbs(kvm);
3161 spin_unlock(&kvm->mmu_lock);
3164 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3169 mutex_unlock(&kvm->slots_lock);
3173 long kvm_arch_vm_ioctl(struct file *filp,
3174 unsigned int ioctl, unsigned long arg)
3176 struct kvm *kvm = filp->private_data;
3177 void __user *argp = (void __user *)arg;
3180 * This union makes it completely explicit to gcc-3.x
3181 * that these two variables' stack usage should be
3182 * combined, not added together.
3185 struct kvm_pit_state ps;
3186 struct kvm_pit_state2 ps2;
3187 struct kvm_pit_config pit_config;
3191 case KVM_SET_TSS_ADDR:
3192 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3196 case KVM_SET_IDENTITY_MAP_ADDR: {
3200 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3202 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3207 case KVM_SET_NR_MMU_PAGES:
3208 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3212 case KVM_GET_NR_MMU_PAGES:
3213 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3215 case KVM_CREATE_IRQCHIP: {
3216 struct kvm_pic *vpic;
3218 mutex_lock(&kvm->lock);
3221 goto create_irqchip_unlock;
3223 if (atomic_read(&kvm->online_vcpus))
3224 goto create_irqchip_unlock;
3226 vpic = kvm_create_pic(kvm);
3228 r = kvm_ioapic_init(kvm);
3230 mutex_lock(&kvm->slots_lock);
3231 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3233 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3235 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3237 mutex_unlock(&kvm->slots_lock);
3239 goto create_irqchip_unlock;
3242 goto create_irqchip_unlock;
3244 kvm->arch.vpic = vpic;
3246 r = kvm_setup_default_irq_routing(kvm);
3248 mutex_lock(&kvm->slots_lock);
3249 mutex_lock(&kvm->irq_lock);
3250 kvm_ioapic_destroy(kvm);
3251 kvm_destroy_pic(kvm);
3252 mutex_unlock(&kvm->irq_lock);
3253 mutex_unlock(&kvm->slots_lock);
3255 create_irqchip_unlock:
3256 mutex_unlock(&kvm->lock);
3259 case KVM_CREATE_PIT:
3260 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3262 case KVM_CREATE_PIT2:
3264 if (copy_from_user(&u.pit_config, argp,
3265 sizeof(struct kvm_pit_config)))
3268 mutex_lock(&kvm->slots_lock);
3271 goto create_pit_unlock;
3273 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3277 mutex_unlock(&kvm->slots_lock);
3279 case KVM_IRQ_LINE_STATUS:
3280 case KVM_IRQ_LINE: {
3281 struct kvm_irq_level irq_event;
3284 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3287 if (irqchip_in_kernel(kvm)) {
3289 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3290 irq_event.irq, irq_event.level);
3291 if (ioctl == KVM_IRQ_LINE_STATUS) {
3293 irq_event.status = status;
3294 if (copy_to_user(argp, &irq_event,
3302 case KVM_GET_IRQCHIP: {
3303 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3304 struct kvm_irqchip *chip;
3306 chip = memdup_user(argp, sizeof(*chip));
3313 if (!irqchip_in_kernel(kvm))
3314 goto get_irqchip_out;
3315 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3317 goto get_irqchip_out;
3319 if (copy_to_user(argp, chip, sizeof *chip))
3320 goto get_irqchip_out;
3328 case KVM_SET_IRQCHIP: {
3329 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3330 struct kvm_irqchip *chip;
3332 chip = memdup_user(argp, sizeof(*chip));
3339 if (!irqchip_in_kernel(kvm))
3340 goto set_irqchip_out;
3341 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3343 goto set_irqchip_out;
3353 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3356 if (!kvm->arch.vpit)
3358 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3362 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3369 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3372 if (!kvm->arch.vpit)
3374 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3380 case KVM_GET_PIT2: {
3382 if (!kvm->arch.vpit)
3384 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3388 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3393 case KVM_SET_PIT2: {
3395 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3398 if (!kvm->arch.vpit)
3400 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3406 case KVM_REINJECT_CONTROL: {
3407 struct kvm_reinject_control control;
3409 if (copy_from_user(&control, argp, sizeof(control)))
3411 r = kvm_vm_ioctl_reinject(kvm, &control);
3417 case KVM_XEN_HVM_CONFIG: {
3419 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3420 sizeof(struct kvm_xen_hvm_config)))
3423 if (kvm->arch.xen_hvm_config.flags)
3428 case KVM_SET_CLOCK: {
3429 struct kvm_clock_data user_ns;
3434 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3442 local_irq_disable();
3443 now_ns = get_kernel_ns();
3444 delta = user_ns.clock - now_ns;
3446 kvm->arch.kvmclock_offset = delta;
3449 case KVM_GET_CLOCK: {
3450 struct kvm_clock_data user_ns;
3453 local_irq_disable();
3454 now_ns = get_kernel_ns();
3455 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3458 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3461 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3474 static void kvm_init_msr_list(void)
3479 /* skip the first msrs in the list. KVM-specific */
3480 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3481 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3484 msrs_to_save[j] = msrs_to_save[i];
3487 num_msrs_to_save = j;
3490 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3498 if (!(vcpu->arch.apic &&
3499 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3500 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3511 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3518 if (!(vcpu->arch.apic &&
3519 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3520 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3522 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3532 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3533 struct kvm_segment *var, int seg)
3535 kvm_x86_ops->set_segment(vcpu, var, seg);
3538 void kvm_get_segment(struct kvm_vcpu *vcpu,
3539 struct kvm_segment *var, int seg)
3541 kvm_x86_ops->get_segment(vcpu, var, seg);
3544 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3547 struct x86_exception exception;
3549 BUG_ON(!mmu_is_nested(vcpu));
3551 /* NPT walks are always user-walks */
3552 access |= PFERR_USER_MASK;
3553 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3558 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3559 struct x86_exception *exception)
3561 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3562 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3565 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3566 struct x86_exception *exception)
3568 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3569 access |= PFERR_FETCH_MASK;
3570 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3573 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3574 struct x86_exception *exception)
3576 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3577 access |= PFERR_WRITE_MASK;
3578 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3581 /* uses this to access any guest's mapped memory without checking CPL */
3582 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3583 struct x86_exception *exception)
3585 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3588 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3589 struct kvm_vcpu *vcpu, u32 access,
3590 struct x86_exception *exception)
3593 int r = X86EMUL_CONTINUE;
3596 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3598 unsigned offset = addr & (PAGE_SIZE-1);
3599 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3602 if (gpa == UNMAPPED_GVA)
3603 return X86EMUL_PROPAGATE_FAULT;
3604 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3606 r = X86EMUL_IO_NEEDED;
3618 /* used for instruction fetching */
3619 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3620 gva_t addr, void *val, unsigned int bytes,
3621 struct x86_exception *exception)
3623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3624 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3626 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3627 access | PFERR_FETCH_MASK,
3631 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3632 gva_t addr, void *val, unsigned int bytes,
3633 struct x86_exception *exception)
3635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3636 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3638 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3641 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3643 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3644 gva_t addr, void *val, unsigned int bytes,
3645 struct x86_exception *exception)
3647 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3648 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3651 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3652 gva_t addr, void *val,
3654 struct x86_exception *exception)
3656 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3658 int r = X86EMUL_CONTINUE;
3661 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3664 unsigned offset = addr & (PAGE_SIZE-1);
3665 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3668 if (gpa == UNMAPPED_GVA)
3669 return X86EMUL_PROPAGATE_FAULT;
3670 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3672 r = X86EMUL_IO_NEEDED;
3683 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3685 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3686 gpa_t *gpa, struct x86_exception *exception,
3689 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3691 if (vcpu_match_mmio_gva(vcpu, gva) &&
3692 check_write_user_access(vcpu, write, access,
3693 vcpu->arch.access)) {
3694 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3695 (gva & (PAGE_SIZE - 1));
3696 trace_vcpu_match_mmio(gva, *gpa, write, false);
3701 access |= PFERR_WRITE_MASK;
3703 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3705 if (*gpa == UNMAPPED_GVA)
3708 /* For APIC access vmexit */
3709 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3712 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3713 trace_vcpu_match_mmio(gva, *gpa, write, true);
3720 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3721 const void *val, int bytes)
3725 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3728 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3732 struct read_write_emulator_ops {
3733 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3735 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3736 void *val, int bytes);
3737 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3738 int bytes, void *val);
3739 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3740 void *val, int bytes);
3744 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3746 if (vcpu->mmio_read_completed) {
3747 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3748 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3749 vcpu->mmio_read_completed = 0;
3756 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3757 void *val, int bytes)
3759 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3762 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3763 void *val, int bytes)
3765 return emulator_write_phys(vcpu, gpa, val, bytes);
3768 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3770 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3771 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3774 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3775 void *val, int bytes)
3777 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3778 return X86EMUL_IO_NEEDED;
3781 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3782 void *val, int bytes)
3784 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3786 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3787 return X86EMUL_CONTINUE;
3790 static struct read_write_emulator_ops read_emultor = {
3791 .read_write_prepare = read_prepare,
3792 .read_write_emulate = read_emulate,
3793 .read_write_mmio = vcpu_mmio_read,
3794 .read_write_exit_mmio = read_exit_mmio,
3797 static struct read_write_emulator_ops write_emultor = {
3798 .read_write_emulate = write_emulate,
3799 .read_write_mmio = write_mmio,
3800 .read_write_exit_mmio = write_exit_mmio,
3804 static int emulator_read_write_onepage(unsigned long addr, void *val,
3806 struct x86_exception *exception,
3807 struct kvm_vcpu *vcpu,
3808 struct read_write_emulator_ops *ops)
3812 bool write = ops->write;
3813 struct kvm_mmio_fragment *frag;
3815 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3818 return X86EMUL_PROPAGATE_FAULT;
3820 /* For APIC access vmexit */
3824 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3825 return X86EMUL_CONTINUE;
3829 * Is this MMIO handled locally?
3831 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3832 if (handled == bytes)
3833 return X86EMUL_CONTINUE;
3840 unsigned now = min(bytes, 8U);
3842 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3851 return X86EMUL_CONTINUE;
3854 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3855 void *val, unsigned int bytes,
3856 struct x86_exception *exception,
3857 struct read_write_emulator_ops *ops)
3859 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3863 if (ops->read_write_prepare &&
3864 ops->read_write_prepare(vcpu, val, bytes))
3865 return X86EMUL_CONTINUE;
3867 vcpu->mmio_nr_fragments = 0;
3869 /* Crossing a page boundary? */
3870 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3873 now = -addr & ~PAGE_MASK;
3874 rc = emulator_read_write_onepage(addr, val, now, exception,
3877 if (rc != X86EMUL_CONTINUE)
3884 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3886 if (rc != X86EMUL_CONTINUE)
3889 if (!vcpu->mmio_nr_fragments)
3892 gpa = vcpu->mmio_fragments[0].gpa;
3894 vcpu->mmio_needed = 1;
3895 vcpu->mmio_cur_fragment = 0;
3897 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3898 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3899 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3900 vcpu->run->mmio.phys_addr = gpa;
3902 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3905 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3909 struct x86_exception *exception)
3911 return emulator_read_write(ctxt, addr, val, bytes,
3912 exception, &read_emultor);
3915 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3919 struct x86_exception *exception)
3921 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3922 exception, &write_emultor);
3925 #define CMPXCHG_TYPE(t, ptr, old, new) \
3926 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3928 #ifdef CONFIG_X86_64
3929 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3931 # define CMPXCHG64(ptr, old, new) \
3932 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3935 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3940 struct x86_exception *exception)
3942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3948 /* guests cmpxchg8b have to be emulated atomically */
3949 if (bytes > 8 || (bytes & (bytes - 1)))
3952 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3954 if (gpa == UNMAPPED_GVA ||
3955 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3958 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3961 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3962 if (is_error_page(page)) {
3963 kvm_release_page_clean(page);
3967 kaddr = kmap_atomic(page);
3968 kaddr += offset_in_page(gpa);
3971 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3974 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3977 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3980 exchanged = CMPXCHG64(kaddr, old, new);
3985 kunmap_atomic(kaddr);
3986 kvm_release_page_dirty(page);
3989 return X86EMUL_CMPXCHG_FAILED;
3991 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3993 return X86EMUL_CONTINUE;
3996 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3998 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4001 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4003 /* TODO: String I/O for in kernel device */
4006 if (vcpu->arch.pio.in)
4007 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4008 vcpu->arch.pio.size, pd);
4010 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4011 vcpu->arch.pio.port, vcpu->arch.pio.size,
4016 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4017 unsigned short port, void *val,
4018 unsigned int count, bool in)
4020 trace_kvm_pio(!in, port, size, count);
4022 vcpu->arch.pio.port = port;
4023 vcpu->arch.pio.in = in;
4024 vcpu->arch.pio.count = count;
4025 vcpu->arch.pio.size = size;
4027 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4028 vcpu->arch.pio.count = 0;
4032 vcpu->run->exit_reason = KVM_EXIT_IO;
4033 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4034 vcpu->run->io.size = size;
4035 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4036 vcpu->run->io.count = count;
4037 vcpu->run->io.port = port;
4042 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4043 int size, unsigned short port, void *val,
4046 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4049 if (vcpu->arch.pio.count)
4052 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4055 memcpy(val, vcpu->arch.pio_data, size * count);
4056 vcpu->arch.pio.count = 0;
4063 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4064 int size, unsigned short port,
4065 const void *val, unsigned int count)
4067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4069 memcpy(vcpu->arch.pio_data, val, size * count);
4070 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4073 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4075 return kvm_x86_ops->get_segment_base(vcpu, seg);
4078 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4080 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4083 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4085 if (!need_emulate_wbinvd(vcpu))
4086 return X86EMUL_CONTINUE;
4088 if (kvm_x86_ops->has_wbinvd_exit()) {
4089 int cpu = get_cpu();
4091 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4092 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4093 wbinvd_ipi, NULL, 1);
4095 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4098 return X86EMUL_CONTINUE;
4100 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4102 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4104 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4107 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4109 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4112 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4115 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4118 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4120 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4123 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4125 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4126 unsigned long value;
4130 value = kvm_read_cr0(vcpu);
4133 value = vcpu->arch.cr2;
4136 value = kvm_read_cr3(vcpu);
4139 value = kvm_read_cr4(vcpu);
4142 value = kvm_get_cr8(vcpu);
4145 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4152 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4154 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4159 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4162 vcpu->arch.cr2 = val;
4165 res = kvm_set_cr3(vcpu, val);
4168 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4171 res = kvm_set_cr8(vcpu, val);
4174 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4181 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4183 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4186 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4188 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4191 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4193 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4196 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4198 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4201 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4203 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4206 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4208 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4211 static unsigned long emulator_get_cached_segment_base(
4212 struct x86_emulate_ctxt *ctxt, int seg)
4214 return get_segment_base(emul_to_vcpu(ctxt), seg);
4217 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4218 struct desc_struct *desc, u32 *base3,
4221 struct kvm_segment var;
4223 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4224 *selector = var.selector;
4231 set_desc_limit(desc, var.limit);
4232 set_desc_base(desc, (unsigned long)var.base);
4233 #ifdef CONFIG_X86_64
4235 *base3 = var.base >> 32;
4237 desc->type = var.type;
4239 desc->dpl = var.dpl;
4240 desc->p = var.present;
4241 desc->avl = var.avl;
4249 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4250 struct desc_struct *desc, u32 base3,
4253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4254 struct kvm_segment var;
4256 var.selector = selector;
4257 var.base = get_desc_base(desc);
4258 #ifdef CONFIG_X86_64
4259 var.base |= ((u64)base3) << 32;
4261 var.limit = get_desc_limit(desc);
4263 var.limit = (var.limit << 12) | 0xfff;
4264 var.type = desc->type;
4265 var.present = desc->p;
4266 var.dpl = desc->dpl;
4271 var.avl = desc->avl;
4272 var.present = desc->p;
4273 var.unusable = !var.present;
4276 kvm_set_segment(vcpu, &var, seg);
4280 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4281 u32 msr_index, u64 *pdata)
4283 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4286 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4287 u32 msr_index, u64 data)
4289 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4292 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4293 u32 pmc, u64 *pdata)
4295 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4298 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4300 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4303 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4306 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4308 * CR0.TS may reference the host fpu state, not the guest fpu state,
4309 * so it may be clear at this point.
4314 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4319 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4320 struct x86_instruction_info *info,
4321 enum x86_intercept_stage stage)
4323 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4326 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4327 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4329 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4332 static struct x86_emulate_ops emulate_ops = {
4333 .read_std = kvm_read_guest_virt_system,
4334 .write_std = kvm_write_guest_virt_system,
4335 .fetch = kvm_fetch_guest_virt,
4336 .read_emulated = emulator_read_emulated,
4337 .write_emulated = emulator_write_emulated,
4338 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4339 .invlpg = emulator_invlpg,
4340 .pio_in_emulated = emulator_pio_in_emulated,
4341 .pio_out_emulated = emulator_pio_out_emulated,
4342 .get_segment = emulator_get_segment,
4343 .set_segment = emulator_set_segment,
4344 .get_cached_segment_base = emulator_get_cached_segment_base,
4345 .get_gdt = emulator_get_gdt,
4346 .get_idt = emulator_get_idt,
4347 .set_gdt = emulator_set_gdt,
4348 .set_idt = emulator_set_idt,
4349 .get_cr = emulator_get_cr,
4350 .set_cr = emulator_set_cr,
4351 .set_rflags = emulator_set_rflags,
4352 .cpl = emulator_get_cpl,
4353 .get_dr = emulator_get_dr,
4354 .set_dr = emulator_set_dr,
4355 .set_msr = emulator_set_msr,
4356 .get_msr = emulator_get_msr,
4357 .read_pmc = emulator_read_pmc,
4358 .halt = emulator_halt,
4359 .wbinvd = emulator_wbinvd,
4360 .fix_hypercall = emulator_fix_hypercall,
4361 .get_fpu = emulator_get_fpu,
4362 .put_fpu = emulator_put_fpu,
4363 .intercept = emulator_intercept,
4364 .get_cpuid = emulator_get_cpuid,
4367 static void cache_all_regs(struct kvm_vcpu *vcpu)
4369 kvm_register_read(vcpu, VCPU_REGS_RAX);
4370 kvm_register_read(vcpu, VCPU_REGS_RSP);
4371 kvm_register_read(vcpu, VCPU_REGS_RIP);
4372 vcpu->arch.regs_dirty = ~0;
4375 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4377 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4379 * an sti; sti; sequence only disable interrupts for the first
4380 * instruction. So, if the last instruction, be it emulated or
4381 * not, left the system with the INT_STI flag enabled, it
4382 * means that the last instruction is an sti. We should not
4383 * leave the flag on in this case. The same goes for mov ss
4385 if (!(int_shadow & mask))
4386 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4389 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4391 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4392 if (ctxt->exception.vector == PF_VECTOR)
4393 kvm_propagate_fault(vcpu, &ctxt->exception);
4394 else if (ctxt->exception.error_code_valid)
4395 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4396 ctxt->exception.error_code);
4398 kvm_queue_exception(vcpu, ctxt->exception.vector);
4401 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4402 const unsigned long *regs)
4404 memset(&ctxt->twobyte, 0,
4405 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4406 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4408 ctxt->fetch.start = 0;
4409 ctxt->fetch.end = 0;
4410 ctxt->io_read.pos = 0;
4411 ctxt->io_read.end = 0;
4412 ctxt->mem_read.pos = 0;
4413 ctxt->mem_read.end = 0;
4416 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4418 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4422 * TODO: fix emulate.c to use guest_read/write_register
4423 * instead of direct ->regs accesses, can save hundred cycles
4424 * on Intel for instructions that don't read/change RSP, for
4427 cache_all_regs(vcpu);
4429 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4431 ctxt->eflags = kvm_get_rflags(vcpu);
4432 ctxt->eip = kvm_rip_read(vcpu);
4433 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4434 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4435 cs_l ? X86EMUL_MODE_PROT64 :
4436 cs_db ? X86EMUL_MODE_PROT32 :
4437 X86EMUL_MODE_PROT16;
4438 ctxt->guest_mode = is_guest_mode(vcpu);
4440 init_decode_cache(ctxt, vcpu->arch.regs);
4441 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4444 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4446 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4449 init_emulate_ctxt(vcpu);
4453 ctxt->_eip = ctxt->eip + inc_eip;
4454 ret = emulate_int_real(ctxt, irq);
4456 if (ret != X86EMUL_CONTINUE)
4457 return EMULATE_FAIL;
4459 ctxt->eip = ctxt->_eip;
4460 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4461 kvm_rip_write(vcpu, ctxt->eip);
4462 kvm_set_rflags(vcpu, ctxt->eflags);
4464 if (irq == NMI_VECTOR)
4465 vcpu->arch.nmi_pending = 0;
4467 vcpu->arch.interrupt.pending = false;
4469 return EMULATE_DONE;
4471 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4473 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4475 int r = EMULATE_DONE;
4477 ++vcpu->stat.insn_emulation_fail;
4478 trace_kvm_emulate_insn_failed(vcpu);
4479 if (!is_guest_mode(vcpu)) {
4480 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4481 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4482 vcpu->run->internal.ndata = 0;
4485 kvm_queue_exception(vcpu, UD_VECTOR);
4490 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4498 * if emulation was due to access to shadowed page table
4499 * and it failed try to unshadow page and re-entetr the
4500 * guest to let CPU execute the instruction.
4502 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4505 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4507 if (gpa == UNMAPPED_GVA)
4508 return true; /* let cpu generate fault */
4510 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4516 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4517 unsigned long cr2, int emulation_type)
4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4520 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4522 last_retry_eip = vcpu->arch.last_retry_eip;
4523 last_retry_addr = vcpu->arch.last_retry_addr;
4526 * If the emulation is caused by #PF and it is non-page_table
4527 * writing instruction, it means the VM-EXIT is caused by shadow
4528 * page protected, we can zap the shadow page and retry this
4529 * instruction directly.
4531 * Note: if the guest uses a non-page-table modifying instruction
4532 * on the PDE that points to the instruction, then we will unmap
4533 * the instruction and go to an infinite loop. So, we cache the
4534 * last retried eip and the last fault address, if we meet the eip
4535 * and the address again, we can break out of the potential infinite
4538 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4540 if (!(emulation_type & EMULTYPE_RETRY))
4543 if (x86_page_table_writing_insn(ctxt))
4546 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4549 vcpu->arch.last_retry_eip = ctxt->eip;
4550 vcpu->arch.last_retry_addr = cr2;
4552 if (!vcpu->arch.mmu.direct_map)
4553 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4555 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4560 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4567 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4568 bool writeback = true;
4570 kvm_clear_exception_queue(vcpu);
4572 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4573 init_emulate_ctxt(vcpu);
4574 ctxt->interruptibility = 0;
4575 ctxt->have_exception = false;
4576 ctxt->perm_ok = false;
4578 ctxt->only_vendor_specific_insn
4579 = emulation_type & EMULTYPE_TRAP_UD;
4581 r = x86_decode_insn(ctxt, insn, insn_len);
4583 trace_kvm_emulate_insn_start(vcpu);
4584 ++vcpu->stat.insn_emulation;
4585 if (r != EMULATION_OK) {
4586 if (emulation_type & EMULTYPE_TRAP_UD)
4587 return EMULATE_FAIL;
4588 if (reexecute_instruction(vcpu, cr2))
4589 return EMULATE_DONE;
4590 if (emulation_type & EMULTYPE_SKIP)
4591 return EMULATE_FAIL;
4592 return handle_emulation_failure(vcpu);
4596 if (emulation_type & EMULTYPE_SKIP) {
4597 kvm_rip_write(vcpu, ctxt->_eip);
4598 return EMULATE_DONE;
4601 if (retry_instruction(ctxt, cr2, emulation_type))
4602 return EMULATE_DONE;
4604 /* this is needed for vmware backdoor interface to work since it
4605 changes registers values during IO operation */
4606 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4607 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4608 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4612 r = x86_emulate_insn(ctxt);
4614 if (r == EMULATION_INTERCEPTED)
4615 return EMULATE_DONE;
4617 if (r == EMULATION_FAILED) {
4618 if (reexecute_instruction(vcpu, cr2))
4619 return EMULATE_DONE;
4621 return handle_emulation_failure(vcpu);
4624 if (ctxt->have_exception) {
4625 inject_emulated_exception(vcpu);
4627 } else if (vcpu->arch.pio.count) {
4628 if (!vcpu->arch.pio.in)
4629 vcpu->arch.pio.count = 0;
4632 r = EMULATE_DO_MMIO;
4633 } else if (vcpu->mmio_needed) {
4634 if (!vcpu->mmio_is_write)
4636 r = EMULATE_DO_MMIO;
4637 } else if (r == EMULATION_RESTART)
4643 toggle_interruptibility(vcpu, ctxt->interruptibility);
4644 kvm_set_rflags(vcpu, ctxt->eflags);
4645 kvm_make_request(KVM_REQ_EVENT, vcpu);
4646 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4647 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4648 kvm_rip_write(vcpu, ctxt->eip);
4650 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4654 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4656 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4658 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4659 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4660 size, port, &val, 1);
4661 /* do not return to emulator after return from userspace */
4662 vcpu->arch.pio.count = 0;
4665 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4667 static void tsc_bad(void *info)
4669 __this_cpu_write(cpu_tsc_khz, 0);
4672 static void tsc_khz_changed(void *data)
4674 struct cpufreq_freqs *freq = data;
4675 unsigned long khz = 0;
4679 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4680 khz = cpufreq_quick_get(raw_smp_processor_id());
4683 __this_cpu_write(cpu_tsc_khz, khz);
4686 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4689 struct cpufreq_freqs *freq = data;
4691 struct kvm_vcpu *vcpu;
4692 int i, send_ipi = 0;
4695 * We allow guests to temporarily run on slowing clocks,
4696 * provided we notify them after, or to run on accelerating
4697 * clocks, provided we notify them before. Thus time never
4700 * However, we have a problem. We can't atomically update
4701 * the frequency of a given CPU from this function; it is
4702 * merely a notifier, which can be called from any CPU.
4703 * Changing the TSC frequency at arbitrary points in time
4704 * requires a recomputation of local variables related to
4705 * the TSC for each VCPU. We must flag these local variables
4706 * to be updated and be sure the update takes place with the
4707 * new frequency before any guests proceed.
4709 * Unfortunately, the combination of hotplug CPU and frequency
4710 * change creates an intractable locking scenario; the order
4711 * of when these callouts happen is undefined with respect to
4712 * CPU hotplug, and they can race with each other. As such,
4713 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4714 * undefined; you can actually have a CPU frequency change take
4715 * place in between the computation of X and the setting of the
4716 * variable. To protect against this problem, all updates of
4717 * the per_cpu tsc_khz variable are done in an interrupt
4718 * protected IPI, and all callers wishing to update the value
4719 * must wait for a synchronous IPI to complete (which is trivial
4720 * if the caller is on the CPU already). This establishes the
4721 * necessary total order on variable updates.
4723 * Note that because a guest time update may take place
4724 * anytime after the setting of the VCPU's request bit, the
4725 * correct TSC value must be set before the request. However,
4726 * to ensure the update actually makes it to any guest which
4727 * starts running in hardware virtualization between the set
4728 * and the acquisition of the spinlock, we must also ping the
4729 * CPU after setting the request bit.
4733 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4735 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4738 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4740 raw_spin_lock(&kvm_lock);
4741 list_for_each_entry(kvm, &vm_list, vm_list) {
4742 kvm_for_each_vcpu(i, vcpu, kvm) {
4743 if (vcpu->cpu != freq->cpu)
4745 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4746 if (vcpu->cpu != smp_processor_id())
4750 raw_spin_unlock(&kvm_lock);
4752 if (freq->old < freq->new && send_ipi) {
4754 * We upscale the frequency. Must make the guest
4755 * doesn't see old kvmclock values while running with
4756 * the new frequency, otherwise we risk the guest sees
4757 * time go backwards.
4759 * In case we update the frequency for another cpu
4760 * (which might be in guest context) send an interrupt
4761 * to kick the cpu out of guest context. Next time
4762 * guest context is entered kvmclock will be updated,
4763 * so the guest will not see stale values.
4765 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4770 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4771 .notifier_call = kvmclock_cpufreq_notifier
4774 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4775 unsigned long action, void *hcpu)
4777 unsigned int cpu = (unsigned long)hcpu;
4781 case CPU_DOWN_FAILED:
4782 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4784 case CPU_DOWN_PREPARE:
4785 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4791 static struct notifier_block kvmclock_cpu_notifier_block = {
4792 .notifier_call = kvmclock_cpu_notifier,
4793 .priority = -INT_MAX
4796 static void kvm_timer_init(void)
4800 max_tsc_khz = tsc_khz;
4801 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4802 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4803 #ifdef CONFIG_CPU_FREQ
4804 struct cpufreq_policy policy;
4805 memset(&policy, 0, sizeof(policy));
4807 cpufreq_get_policy(&policy, cpu);
4808 if (policy.cpuinfo.max_freq)
4809 max_tsc_khz = policy.cpuinfo.max_freq;
4812 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4813 CPUFREQ_TRANSITION_NOTIFIER);
4815 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4816 for_each_online_cpu(cpu)
4817 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4820 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4822 int kvm_is_in_guest(void)
4824 return __this_cpu_read(current_vcpu) != NULL;
4827 static int kvm_is_user_mode(void)
4831 if (__this_cpu_read(current_vcpu))
4832 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4834 return user_mode != 0;
4837 static unsigned long kvm_get_guest_ip(void)
4839 unsigned long ip = 0;
4841 if (__this_cpu_read(current_vcpu))
4842 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4847 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4848 .is_in_guest = kvm_is_in_guest,
4849 .is_user_mode = kvm_is_user_mode,
4850 .get_guest_ip = kvm_get_guest_ip,
4853 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4855 __this_cpu_write(current_vcpu, vcpu);
4857 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4859 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4861 __this_cpu_write(current_vcpu, NULL);
4863 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4865 static void kvm_set_mmio_spte_mask(void)
4868 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4871 * Set the reserved bits and the present bit of an paging-structure
4872 * entry to generate page fault with PFER.RSV = 1.
4874 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4877 #ifdef CONFIG_X86_64
4879 * If reserved bit is not supported, clear the present bit to disable
4882 if (maxphyaddr == 52)
4886 kvm_mmu_set_mmio_spte_mask(mask);
4889 int kvm_arch_init(void *opaque)
4892 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4895 printk(KERN_ERR "kvm: already loaded the other module\n");
4900 if (!ops->cpu_has_kvm_support()) {
4901 printk(KERN_ERR "kvm: no hardware support\n");
4905 if (ops->disabled_by_bios()) {
4906 printk(KERN_ERR "kvm: disabled by bios\n");
4911 r = kvm_mmu_module_init();
4915 kvm_set_mmio_spte_mask();
4916 kvm_init_msr_list();
4919 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4920 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4924 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4927 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4935 void kvm_arch_exit(void)
4937 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4939 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4940 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4941 CPUFREQ_TRANSITION_NOTIFIER);
4942 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4944 kvm_mmu_module_exit();
4947 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4949 ++vcpu->stat.halt_exits;
4950 if (irqchip_in_kernel(vcpu->kvm)) {
4951 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4954 vcpu->run->exit_reason = KVM_EXIT_HLT;
4958 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4960 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4962 u64 param, ingpa, outgpa, ret;
4963 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4964 bool fast, longmode;
4968 * hypercall generates UD from non zero cpl and real mode
4971 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4972 kvm_queue_exception(vcpu, UD_VECTOR);
4976 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4977 longmode = is_long_mode(vcpu) && cs_l == 1;
4980 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4981 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4982 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4983 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4984 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4985 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4987 #ifdef CONFIG_X86_64
4989 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4990 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4991 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4995 code = param & 0xffff;
4996 fast = (param >> 16) & 0x1;
4997 rep_cnt = (param >> 32) & 0xfff;
4998 rep_idx = (param >> 48) & 0xfff;
5000 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5003 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5004 kvm_vcpu_on_spin(vcpu);
5007 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5011 ret = res | (((u64)rep_done & 0xfff) << 32);
5013 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5015 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5016 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5022 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5024 unsigned long nr, a0, a1, a2, a3, ret;
5027 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5028 return kvm_hv_hypercall(vcpu);
5030 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5031 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5032 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5033 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5034 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5036 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5038 if (!is_long_mode(vcpu)) {
5046 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5052 case KVM_HC_VAPIC_POLL_IRQ:
5060 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5061 ++vcpu->stat.hypercalls;
5064 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5066 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5068 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5069 char instruction[3];
5070 unsigned long rip = kvm_rip_read(vcpu);
5073 * Blow out the MMU to ensure that no other VCPU has an active mapping
5074 * to ensure that the updated hypercall appears atomically across all
5077 kvm_mmu_zap_all(vcpu->kvm);
5079 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5081 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5085 * Check if userspace requested an interrupt window, and that the
5086 * interrupt window is open.
5088 * No need to exit to userspace if we already have an interrupt queued.
5090 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5092 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5093 vcpu->run->request_interrupt_window &&
5094 kvm_arch_interrupt_allowed(vcpu));
5097 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5099 struct kvm_run *kvm_run = vcpu->run;
5101 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5102 kvm_run->cr8 = kvm_get_cr8(vcpu);
5103 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5104 if (irqchip_in_kernel(vcpu->kvm))
5105 kvm_run->ready_for_interrupt_injection = 1;
5107 kvm_run->ready_for_interrupt_injection =
5108 kvm_arch_interrupt_allowed(vcpu) &&
5109 !kvm_cpu_has_interrupt(vcpu) &&
5110 !kvm_event_needs_reinjection(vcpu);
5113 static void vapic_enter(struct kvm_vcpu *vcpu)
5115 struct kvm_lapic *apic = vcpu->arch.apic;
5118 if (!apic || !apic->vapic_addr)
5121 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5123 vcpu->arch.apic->vapic_page = page;
5126 static void vapic_exit(struct kvm_vcpu *vcpu)
5128 struct kvm_lapic *apic = vcpu->arch.apic;
5131 if (!apic || !apic->vapic_addr)
5134 idx = srcu_read_lock(&vcpu->kvm->srcu);
5135 kvm_release_page_dirty(apic->vapic_page);
5136 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5137 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5140 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5144 if (!kvm_x86_ops->update_cr8_intercept)
5147 if (!vcpu->arch.apic)
5150 if (!vcpu->arch.apic->vapic_addr)
5151 max_irr = kvm_lapic_find_highest_irr(vcpu);
5158 tpr = kvm_lapic_get_cr8(vcpu);
5160 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5163 static void inject_pending_event(struct kvm_vcpu *vcpu)
5165 /* try to reinject previous events if any */
5166 if (vcpu->arch.exception.pending) {
5167 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5168 vcpu->arch.exception.has_error_code,
5169 vcpu->arch.exception.error_code);
5170 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5171 vcpu->arch.exception.has_error_code,
5172 vcpu->arch.exception.error_code,
5173 vcpu->arch.exception.reinject);
5177 if (vcpu->arch.nmi_injected) {
5178 kvm_x86_ops->set_nmi(vcpu);
5182 if (vcpu->arch.interrupt.pending) {
5183 kvm_x86_ops->set_irq(vcpu);
5187 /* try to inject new event if pending */
5188 if (vcpu->arch.nmi_pending) {
5189 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5190 --vcpu->arch.nmi_pending;
5191 vcpu->arch.nmi_injected = true;
5192 kvm_x86_ops->set_nmi(vcpu);
5194 } else if (kvm_cpu_has_interrupt(vcpu)) {
5195 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5196 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5198 kvm_x86_ops->set_irq(vcpu);
5203 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5205 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5206 !vcpu->guest_xcr0_loaded) {
5207 /* kvm_set_xcr() also depends on this */
5208 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5209 vcpu->guest_xcr0_loaded = 1;
5213 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5215 if (vcpu->guest_xcr0_loaded) {
5216 if (vcpu->arch.xcr0 != host_xcr0)
5217 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5218 vcpu->guest_xcr0_loaded = 0;
5222 static void process_nmi(struct kvm_vcpu *vcpu)
5227 * x86 is limited to one NMI running, and one NMI pending after it.
5228 * If an NMI is already in progress, limit further NMIs to just one.
5229 * Otherwise, allow two (and we'll inject the first one immediately).
5231 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5234 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5235 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5236 kvm_make_request(KVM_REQ_EVENT, vcpu);
5239 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5242 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5243 vcpu->run->request_interrupt_window;
5244 bool req_immediate_exit = 0;
5246 if (vcpu->requests) {
5247 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5248 kvm_mmu_unload(vcpu);
5249 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5250 __kvm_migrate_timers(vcpu);
5251 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5252 r = kvm_guest_time_update(vcpu);
5256 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5257 kvm_mmu_sync_roots(vcpu);
5258 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5259 kvm_x86_ops->tlb_flush(vcpu);
5260 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5261 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5265 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5266 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5270 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5271 vcpu->fpu_active = 0;
5272 kvm_x86_ops->fpu_deactivate(vcpu);
5274 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5275 /* Page is swapped out. Do synthetic halt */
5276 vcpu->arch.apf.halted = true;
5280 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5281 record_steal_time(vcpu);
5282 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5284 req_immediate_exit =
5285 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5286 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5287 kvm_handle_pmu_event(vcpu);
5288 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5289 kvm_deliver_pmi(vcpu);
5292 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5293 inject_pending_event(vcpu);
5295 /* enable NMI/IRQ window open exits if needed */
5296 if (vcpu->arch.nmi_pending)
5297 kvm_x86_ops->enable_nmi_window(vcpu);
5298 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5299 kvm_x86_ops->enable_irq_window(vcpu);
5301 if (kvm_lapic_enabled(vcpu)) {
5302 update_cr8_intercept(vcpu);
5303 kvm_lapic_sync_to_vapic(vcpu);
5307 r = kvm_mmu_reload(vcpu);
5309 goto cancel_injection;
5314 kvm_x86_ops->prepare_guest_switch(vcpu);
5315 if (vcpu->fpu_active)
5316 kvm_load_guest_fpu(vcpu);
5317 kvm_load_guest_xcr0(vcpu);
5319 vcpu->mode = IN_GUEST_MODE;
5321 /* We should set ->mode before check ->requests,
5322 * see the comment in make_all_cpus_request.
5326 local_irq_disable();
5328 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5329 || need_resched() || signal_pending(current)) {
5330 vcpu->mode = OUTSIDE_GUEST_MODE;
5335 goto cancel_injection;
5338 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5340 if (req_immediate_exit)
5341 smp_send_reschedule(vcpu->cpu);
5345 if (unlikely(vcpu->arch.switch_db_regs)) {
5347 set_debugreg(vcpu->arch.eff_db[0], 0);
5348 set_debugreg(vcpu->arch.eff_db[1], 1);
5349 set_debugreg(vcpu->arch.eff_db[2], 2);
5350 set_debugreg(vcpu->arch.eff_db[3], 3);
5353 trace_kvm_entry(vcpu->vcpu_id);
5354 kvm_x86_ops->run(vcpu);
5357 * If the guest has used debug registers, at least dr7
5358 * will be disabled while returning to the host.
5359 * If we don't have active breakpoints in the host, we don't
5360 * care about the messed up debug address registers. But if
5361 * we have some of them active, restore the old state.
5363 if (hw_breakpoint_active())
5364 hw_breakpoint_restore();
5366 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5368 vcpu->mode = OUTSIDE_GUEST_MODE;
5375 * We must have an instruction between local_irq_enable() and
5376 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5377 * the interrupt shadow. The stat.exits increment will do nicely.
5378 * But we need to prevent reordering, hence this barrier():
5386 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5389 * Profile KVM exit RIPs:
5391 if (unlikely(prof_on == KVM_PROFILING)) {
5392 unsigned long rip = kvm_rip_read(vcpu);
5393 profile_hit(KVM_PROFILING, (void *)rip);
5396 if (unlikely(vcpu->arch.tsc_always_catchup))
5397 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5399 if (vcpu->arch.apic_attention)
5400 kvm_lapic_sync_from_vapic(vcpu);
5402 r = kvm_x86_ops->handle_exit(vcpu);
5406 kvm_x86_ops->cancel_injection(vcpu);
5407 if (unlikely(vcpu->arch.apic_attention))
5408 kvm_lapic_sync_from_vapic(vcpu);
5414 static int __vcpu_run(struct kvm_vcpu *vcpu)
5417 struct kvm *kvm = vcpu->kvm;
5419 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5420 pr_debug("vcpu %d received sipi with vector # %x\n",
5421 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5422 kvm_lapic_reset(vcpu);
5423 r = kvm_arch_vcpu_reset(vcpu);
5426 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5429 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5434 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5435 !vcpu->arch.apf.halted)
5436 r = vcpu_enter_guest(vcpu);
5438 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5439 kvm_vcpu_block(vcpu);
5440 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5441 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5443 switch(vcpu->arch.mp_state) {
5444 case KVM_MP_STATE_HALTED:
5445 vcpu->arch.mp_state =
5446 KVM_MP_STATE_RUNNABLE;
5447 case KVM_MP_STATE_RUNNABLE:
5448 vcpu->arch.apf.halted = false;
5450 case KVM_MP_STATE_SIPI_RECEIVED:
5461 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5462 if (kvm_cpu_has_pending_timer(vcpu))
5463 kvm_inject_pending_timer_irqs(vcpu);
5465 if (dm_request_for_irq_injection(vcpu)) {
5467 vcpu->run->exit_reason = KVM_EXIT_INTR;
5468 ++vcpu->stat.request_irq_exits;
5471 kvm_check_async_pf_completion(vcpu);
5473 if (signal_pending(current)) {
5475 vcpu->run->exit_reason = KVM_EXIT_INTR;
5476 ++vcpu->stat.signal_exits;
5478 if (need_resched()) {
5479 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5481 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5485 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5493 * Implements the following, as a state machine:
5508 static int complete_mmio(struct kvm_vcpu *vcpu)
5510 struct kvm_run *run = vcpu->run;
5511 struct kvm_mmio_fragment *frag;
5514 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5517 if (vcpu->mmio_needed) {
5518 /* Complete previous fragment */
5519 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5520 if (!vcpu->mmio_is_write)
5521 memcpy(frag->data, run->mmio.data, frag->len);
5522 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5523 vcpu->mmio_needed = 0;
5524 if (vcpu->mmio_is_write)
5526 vcpu->mmio_read_completed = 1;
5529 /* Initiate next fragment */
5531 run->exit_reason = KVM_EXIT_MMIO;
5532 run->mmio.phys_addr = frag->gpa;
5533 if (vcpu->mmio_is_write)
5534 memcpy(run->mmio.data, frag->data, frag->len);
5535 run->mmio.len = frag->len;
5536 run->mmio.is_write = vcpu->mmio_is_write;
5541 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5542 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5543 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5544 if (r != EMULATE_DONE)
5549 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5554 if (!tsk_used_math(current) && init_fpu(current))
5557 if (vcpu->sigset_active)
5558 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5560 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5561 kvm_vcpu_block(vcpu);
5562 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5567 /* re-sync apic's tpr */
5568 if (!irqchip_in_kernel(vcpu->kvm)) {
5569 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5575 r = complete_mmio(vcpu);
5579 r = __vcpu_run(vcpu);
5582 post_kvm_run_save(vcpu);
5583 if (vcpu->sigset_active)
5584 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5589 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5591 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5593 * We are here if userspace calls get_regs() in the middle of
5594 * instruction emulation. Registers state needs to be copied
5595 * back from emulation context to vcpu. Usrapace shouldn't do
5596 * that usually, but some bad designed PV devices (vmware
5597 * backdoor interface) need this to work
5599 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5600 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5601 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5603 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5604 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5605 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5606 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5607 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5608 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5609 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5610 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5611 #ifdef CONFIG_X86_64
5612 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5613 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5614 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5615 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5616 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5617 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5618 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5619 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5622 regs->rip = kvm_rip_read(vcpu);
5623 regs->rflags = kvm_get_rflags(vcpu);
5628 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5630 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5631 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5633 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5634 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5635 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5636 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5637 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5638 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5639 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5640 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5641 #ifdef CONFIG_X86_64
5642 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5643 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5644 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5645 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5646 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5647 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5648 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5649 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5652 kvm_rip_write(vcpu, regs->rip);
5653 kvm_set_rflags(vcpu, regs->rflags);
5655 vcpu->arch.exception.pending = false;
5657 kvm_make_request(KVM_REQ_EVENT, vcpu);
5662 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5664 struct kvm_segment cs;
5666 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5670 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5672 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5673 struct kvm_sregs *sregs)
5677 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5678 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5679 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5680 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5681 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5682 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5684 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5685 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5687 kvm_x86_ops->get_idt(vcpu, &dt);
5688 sregs->idt.limit = dt.size;
5689 sregs->idt.base = dt.address;
5690 kvm_x86_ops->get_gdt(vcpu, &dt);
5691 sregs->gdt.limit = dt.size;
5692 sregs->gdt.base = dt.address;
5694 sregs->cr0 = kvm_read_cr0(vcpu);
5695 sregs->cr2 = vcpu->arch.cr2;
5696 sregs->cr3 = kvm_read_cr3(vcpu);
5697 sregs->cr4 = kvm_read_cr4(vcpu);
5698 sregs->cr8 = kvm_get_cr8(vcpu);
5699 sregs->efer = vcpu->arch.efer;
5700 sregs->apic_base = kvm_get_apic_base(vcpu);
5702 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5704 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5705 set_bit(vcpu->arch.interrupt.nr,
5706 (unsigned long *)sregs->interrupt_bitmap);
5711 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5712 struct kvm_mp_state *mp_state)
5714 mp_state->mp_state = vcpu->arch.mp_state;
5718 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5719 struct kvm_mp_state *mp_state)
5721 vcpu->arch.mp_state = mp_state->mp_state;
5722 kvm_make_request(KVM_REQ_EVENT, vcpu);
5726 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5727 int reason, bool has_error_code, u32 error_code)
5729 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5732 init_emulate_ctxt(vcpu);
5734 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5735 has_error_code, error_code);
5738 return EMULATE_FAIL;
5740 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5741 kvm_rip_write(vcpu, ctxt->eip);
5742 kvm_set_rflags(vcpu, ctxt->eflags);
5743 kvm_make_request(KVM_REQ_EVENT, vcpu);
5744 return EMULATE_DONE;
5746 EXPORT_SYMBOL_GPL(kvm_task_switch);
5748 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5749 struct kvm_sregs *sregs)
5751 int mmu_reset_needed = 0;
5752 int pending_vec, max_bits, idx;
5755 dt.size = sregs->idt.limit;
5756 dt.address = sregs->idt.base;
5757 kvm_x86_ops->set_idt(vcpu, &dt);
5758 dt.size = sregs->gdt.limit;
5759 dt.address = sregs->gdt.base;
5760 kvm_x86_ops->set_gdt(vcpu, &dt);
5762 vcpu->arch.cr2 = sregs->cr2;
5763 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5764 vcpu->arch.cr3 = sregs->cr3;
5765 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5767 kvm_set_cr8(vcpu, sregs->cr8);
5769 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5770 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5771 kvm_set_apic_base(vcpu, sregs->apic_base);
5773 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5774 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5775 vcpu->arch.cr0 = sregs->cr0;
5777 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5778 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5779 if (sregs->cr4 & X86_CR4_OSXSAVE)
5780 kvm_update_cpuid(vcpu);
5782 idx = srcu_read_lock(&vcpu->kvm->srcu);
5783 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5784 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5785 mmu_reset_needed = 1;
5787 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5789 if (mmu_reset_needed)
5790 kvm_mmu_reset_context(vcpu);
5792 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5793 pending_vec = find_first_bit(
5794 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5795 if (pending_vec < max_bits) {
5796 kvm_queue_interrupt(vcpu, pending_vec, false);
5797 pr_debug("Set back pending irq %d\n", pending_vec);
5800 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5801 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5802 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5803 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5804 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5805 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5807 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5808 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5810 update_cr8_intercept(vcpu);
5812 /* Older userspace won't unhalt the vcpu on reset. */
5813 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5814 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5818 kvm_make_request(KVM_REQ_EVENT, vcpu);
5823 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5824 struct kvm_guest_debug *dbg)
5826 unsigned long rflags;
5829 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5831 if (vcpu->arch.exception.pending)
5833 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5834 kvm_queue_exception(vcpu, DB_VECTOR);
5836 kvm_queue_exception(vcpu, BP_VECTOR);
5840 * Read rflags as long as potentially injected trace flags are still
5843 rflags = kvm_get_rflags(vcpu);
5845 vcpu->guest_debug = dbg->control;
5846 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5847 vcpu->guest_debug = 0;
5849 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5850 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5851 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5852 vcpu->arch.switch_db_regs =
5853 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5855 for (i = 0; i < KVM_NR_DB_REGS; i++)
5856 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5857 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5860 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5861 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5862 get_segment_base(vcpu, VCPU_SREG_CS);
5865 * Trigger an rflags update that will inject or remove the trace
5868 kvm_set_rflags(vcpu, rflags);
5870 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5880 * Translate a guest virtual address to a guest physical address.
5882 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5883 struct kvm_translation *tr)
5885 unsigned long vaddr = tr->linear_address;
5889 idx = srcu_read_lock(&vcpu->kvm->srcu);
5890 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5891 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5892 tr->physical_address = gpa;
5893 tr->valid = gpa != UNMAPPED_GVA;
5900 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5902 struct i387_fxsave_struct *fxsave =
5903 &vcpu->arch.guest_fpu.state->fxsave;
5905 memcpy(fpu->fpr, fxsave->st_space, 128);
5906 fpu->fcw = fxsave->cwd;
5907 fpu->fsw = fxsave->swd;
5908 fpu->ftwx = fxsave->twd;
5909 fpu->last_opcode = fxsave->fop;
5910 fpu->last_ip = fxsave->rip;
5911 fpu->last_dp = fxsave->rdp;
5912 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5917 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5919 struct i387_fxsave_struct *fxsave =
5920 &vcpu->arch.guest_fpu.state->fxsave;
5922 memcpy(fxsave->st_space, fpu->fpr, 128);
5923 fxsave->cwd = fpu->fcw;
5924 fxsave->swd = fpu->fsw;
5925 fxsave->twd = fpu->ftwx;
5926 fxsave->fop = fpu->last_opcode;
5927 fxsave->rip = fpu->last_ip;
5928 fxsave->rdp = fpu->last_dp;
5929 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5934 int fx_init(struct kvm_vcpu *vcpu)
5938 err = fpu_alloc(&vcpu->arch.guest_fpu);
5942 fpu_finit(&vcpu->arch.guest_fpu);
5945 * Ensure guest xcr0 is valid for loading
5947 vcpu->arch.xcr0 = XSTATE_FP;
5949 vcpu->arch.cr0 |= X86_CR0_ET;
5953 EXPORT_SYMBOL_GPL(fx_init);
5955 static void fx_free(struct kvm_vcpu *vcpu)
5957 fpu_free(&vcpu->arch.guest_fpu);
5960 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5962 if (vcpu->guest_fpu_loaded)
5966 * Restore all possible states in the guest,
5967 * and assume host would use all available bits.
5968 * Guest xcr0 would be loaded later.
5970 kvm_put_guest_xcr0(vcpu);
5971 vcpu->guest_fpu_loaded = 1;
5972 unlazy_fpu(current);
5973 fpu_restore_checking(&vcpu->arch.guest_fpu);
5977 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5979 kvm_put_guest_xcr0(vcpu);
5981 if (!vcpu->guest_fpu_loaded)
5984 vcpu->guest_fpu_loaded = 0;
5985 fpu_save_init(&vcpu->arch.guest_fpu);
5986 ++vcpu->stat.fpu_reload;
5987 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5991 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5993 kvmclock_reset(vcpu);
5995 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5997 kvm_x86_ops->vcpu_free(vcpu);
6000 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6003 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6004 printk_once(KERN_WARNING
6005 "kvm: SMP vm created on host with unstable TSC; "
6006 "guest TSC will not be reliable\n");
6007 return kvm_x86_ops->vcpu_create(kvm, id);
6010 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6014 vcpu->arch.mtrr_state.have_fixed = 1;
6016 r = kvm_arch_vcpu_reset(vcpu);
6018 r = kvm_mmu_setup(vcpu);
6024 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6026 vcpu->arch.apf.msr_val = 0;
6029 kvm_mmu_unload(vcpu);
6033 kvm_x86_ops->vcpu_free(vcpu);
6036 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6038 atomic_set(&vcpu->arch.nmi_queued, 0);
6039 vcpu->arch.nmi_pending = 0;
6040 vcpu->arch.nmi_injected = false;
6042 vcpu->arch.switch_db_regs = 0;
6043 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6044 vcpu->arch.dr6 = DR6_FIXED_1;
6045 vcpu->arch.dr7 = DR7_FIXED_1;
6047 kvm_make_request(KVM_REQ_EVENT, vcpu);
6048 vcpu->arch.apf.msr_val = 0;
6049 vcpu->arch.st.msr_val = 0;
6051 kvmclock_reset(vcpu);
6053 kvm_clear_async_pf_completion_queue(vcpu);
6054 kvm_async_pf_hash_reset(vcpu);
6055 vcpu->arch.apf.halted = false;
6057 kvm_pmu_reset(vcpu);
6059 return kvm_x86_ops->vcpu_reset(vcpu);
6062 int kvm_arch_hardware_enable(void *garbage)
6065 struct kvm_vcpu *vcpu;
6070 bool stable, backwards_tsc = false;
6072 kvm_shared_msr_cpu_online();
6073 ret = kvm_x86_ops->hardware_enable(garbage);
6077 local_tsc = native_read_tsc();
6078 stable = !check_tsc_unstable();
6079 list_for_each_entry(kvm, &vm_list, vm_list) {
6080 kvm_for_each_vcpu(i, vcpu, kvm) {
6081 if (!stable && vcpu->cpu == smp_processor_id())
6082 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6083 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6084 backwards_tsc = true;
6085 if (vcpu->arch.last_host_tsc > max_tsc)
6086 max_tsc = vcpu->arch.last_host_tsc;
6092 * Sometimes, even reliable TSCs go backwards. This happens on
6093 * platforms that reset TSC during suspend or hibernate actions, but
6094 * maintain synchronization. We must compensate. Fortunately, we can
6095 * detect that condition here, which happens early in CPU bringup,
6096 * before any KVM threads can be running. Unfortunately, we can't
6097 * bring the TSCs fully up to date with real time, as we aren't yet far
6098 * enough into CPU bringup that we know how much real time has actually
6099 * elapsed; our helper function, get_kernel_ns() will be using boot
6100 * variables that haven't been updated yet.
6102 * So we simply find the maximum observed TSC above, then record the
6103 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6104 * the adjustment will be applied. Note that we accumulate
6105 * adjustments, in case multiple suspend cycles happen before some VCPU
6106 * gets a chance to run again. In the event that no KVM threads get a
6107 * chance to run, we will miss the entire elapsed period, as we'll have
6108 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6109 * loose cycle time. This isn't too big a deal, since the loss will be
6110 * uniform across all VCPUs (not to mention the scenario is extremely
6111 * unlikely). It is possible that a second hibernate recovery happens
6112 * much faster than a first, causing the observed TSC here to be
6113 * smaller; this would require additional padding adjustment, which is
6114 * why we set last_host_tsc to the local tsc observed here.
6116 * N.B. - this code below runs only on platforms with reliable TSC,
6117 * as that is the only way backwards_tsc is set above. Also note
6118 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6119 * have the same delta_cyc adjustment applied if backwards_tsc
6120 * is detected. Note further, this adjustment is only done once,
6121 * as we reset last_host_tsc on all VCPUs to stop this from being
6122 * called multiple times (one for each physical CPU bringup).
6124 * Platforms with unnreliable TSCs don't have to deal with this, they
6125 * will be compensated by the logic in vcpu_load, which sets the TSC to
6126 * catchup mode. This will catchup all VCPUs to real time, but cannot
6127 * guarantee that they stay in perfect synchronization.
6129 if (backwards_tsc) {
6130 u64 delta_cyc = max_tsc - local_tsc;
6131 list_for_each_entry(kvm, &vm_list, vm_list) {
6132 kvm_for_each_vcpu(i, vcpu, kvm) {
6133 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6134 vcpu->arch.last_host_tsc = local_tsc;
6138 * We have to disable TSC offset matching.. if you were
6139 * booting a VM while issuing an S4 host suspend....
6140 * you may have some problem. Solving this issue is
6141 * left as an exercise to the reader.
6143 kvm->arch.last_tsc_nsec = 0;
6144 kvm->arch.last_tsc_write = 0;
6151 void kvm_arch_hardware_disable(void *garbage)
6153 kvm_x86_ops->hardware_disable(garbage);
6154 drop_user_return_notifiers(garbage);
6157 int kvm_arch_hardware_setup(void)
6159 return kvm_x86_ops->hardware_setup();
6162 void kvm_arch_hardware_unsetup(void)
6164 kvm_x86_ops->hardware_unsetup();
6167 void kvm_arch_check_processor_compat(void *rtn)
6169 kvm_x86_ops->check_processor_compatibility(rtn);
6172 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6174 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6177 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6183 BUG_ON(vcpu->kvm == NULL);
6186 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6187 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6188 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6190 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6192 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6197 vcpu->arch.pio_data = page_address(page);
6199 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6201 r = kvm_mmu_create(vcpu);
6203 goto fail_free_pio_data;
6205 if (irqchip_in_kernel(kvm)) {
6206 r = kvm_create_lapic(vcpu);
6208 goto fail_mmu_destroy;
6211 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6213 if (!vcpu->arch.mce_banks) {
6215 goto fail_free_lapic;
6217 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6219 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6220 goto fail_free_mce_banks;
6222 kvm_async_pf_hash_reset(vcpu);
6226 fail_free_mce_banks:
6227 kfree(vcpu->arch.mce_banks);
6229 kvm_free_lapic(vcpu);
6231 kvm_mmu_destroy(vcpu);
6233 free_page((unsigned long)vcpu->arch.pio_data);
6238 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6242 kvm_pmu_destroy(vcpu);
6243 kfree(vcpu->arch.mce_banks);
6244 kvm_free_lapic(vcpu);
6245 idx = srcu_read_lock(&vcpu->kvm->srcu);
6246 kvm_mmu_destroy(vcpu);
6247 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6248 free_page((unsigned long)vcpu->arch.pio_data);
6251 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6256 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6257 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6259 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6260 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6262 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6267 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6270 kvm_mmu_unload(vcpu);
6274 static void kvm_free_vcpus(struct kvm *kvm)
6277 struct kvm_vcpu *vcpu;
6280 * Unpin any mmu pages first.
6282 kvm_for_each_vcpu(i, vcpu, kvm) {
6283 kvm_clear_async_pf_completion_queue(vcpu);
6284 kvm_unload_vcpu_mmu(vcpu);
6286 kvm_for_each_vcpu(i, vcpu, kvm)
6287 kvm_arch_vcpu_free(vcpu);
6289 mutex_lock(&kvm->lock);
6290 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6291 kvm->vcpus[i] = NULL;
6293 atomic_set(&kvm->online_vcpus, 0);
6294 mutex_unlock(&kvm->lock);
6297 void kvm_arch_sync_events(struct kvm *kvm)
6299 kvm_free_all_assigned_devices(kvm);
6303 void kvm_arch_destroy_vm(struct kvm *kvm)
6305 kvm_iommu_unmap_guest(kvm);
6306 kfree(kvm->arch.vpic);
6307 kfree(kvm->arch.vioapic);
6308 kvm_free_vcpus(kvm);
6309 if (kvm->arch.apic_access_page)
6310 put_page(kvm->arch.apic_access_page);
6311 if (kvm->arch.ept_identity_pagetable)
6312 put_page(kvm->arch.ept_identity_pagetable);
6315 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6316 struct kvm_memory_slot *dont)
6320 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6321 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
6322 kvm_kvfree(free->arch.lpage_info[i]);
6323 free->arch.lpage_info[i] = NULL;
6328 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6332 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6337 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6338 slot->base_gfn, level) + 1;
6340 slot->arch.lpage_info[i] =
6341 kvm_kvzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
6342 if (!slot->arch.lpage_info[i])
6345 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6346 slot->arch.lpage_info[i][0].write_count = 1;
6347 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6348 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6349 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6351 * If the gfn and userspace address are not aligned wrt each
6352 * other, or if explicitly asked to, disable large page
6353 * support for this slot
6355 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6356 !kvm_largepages_enabled()) {
6359 for (j = 0; j < lpages; ++j)
6360 slot->arch.lpage_info[i][j].write_count = 1;
6367 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6368 kvm_kvfree(slot->arch.lpage_info[i]);
6369 slot->arch.lpage_info[i] = NULL;
6374 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6375 struct kvm_memory_slot *memslot,
6376 struct kvm_memory_slot old,
6377 struct kvm_userspace_memory_region *mem,
6380 int npages = memslot->npages;
6381 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6383 /* Prevent internal slot pages from being moved by fork()/COW. */
6384 if (memslot->id >= KVM_MEMORY_SLOTS)
6385 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6387 /*To keep backward compatibility with older userspace,
6388 *x86 needs to hanlde !user_alloc case.
6391 if (npages && !old.rmap) {
6392 unsigned long userspace_addr;
6394 userspace_addr = vm_mmap(NULL, 0,
6396 PROT_READ | PROT_WRITE,
6400 if (IS_ERR((void *)userspace_addr))
6401 return PTR_ERR((void *)userspace_addr);
6403 memslot->userspace_addr = userspace_addr;
6411 void kvm_arch_commit_memory_region(struct kvm *kvm,
6412 struct kvm_userspace_memory_region *mem,
6413 struct kvm_memory_slot old,
6417 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6419 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6422 ret = vm_munmap(old.userspace_addr,
6423 old.npages * PAGE_SIZE);
6426 "kvm_vm_ioctl_set_memory_region: "
6427 "failed to munmap memory\n");
6430 if (!kvm->arch.n_requested_mmu_pages)
6431 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6433 spin_lock(&kvm->mmu_lock);
6435 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6436 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6437 spin_unlock(&kvm->mmu_lock);
6440 void kvm_arch_flush_shadow(struct kvm *kvm)
6442 kvm_mmu_zap_all(kvm);
6443 kvm_reload_remote_mmus(kvm);
6446 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6448 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6449 !vcpu->arch.apf.halted)
6450 || !list_empty_careful(&vcpu->async_pf.done)
6451 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6452 || atomic_read(&vcpu->arch.nmi_queued) ||
6453 (kvm_arch_interrupt_allowed(vcpu) &&
6454 kvm_cpu_has_interrupt(vcpu));
6457 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
6459 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
6462 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6464 return kvm_x86_ops->interrupt_allowed(vcpu);
6467 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6469 unsigned long current_rip = kvm_rip_read(vcpu) +
6470 get_segment_base(vcpu, VCPU_SREG_CS);
6472 return current_rip == linear_rip;
6474 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6476 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6478 unsigned long rflags;
6480 rflags = kvm_x86_ops->get_rflags(vcpu);
6481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6482 rflags &= ~X86_EFLAGS_TF;
6485 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6487 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6489 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6490 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6491 rflags |= X86_EFLAGS_TF;
6492 kvm_x86_ops->set_rflags(vcpu, rflags);
6493 kvm_make_request(KVM_REQ_EVENT, vcpu);
6495 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6497 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6501 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6502 is_error_page(work->page))
6505 r = kvm_mmu_reload(vcpu);
6509 if (!vcpu->arch.mmu.direct_map &&
6510 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6513 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6516 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6518 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6521 static inline u32 kvm_async_pf_next_probe(u32 key)
6523 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6526 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6528 u32 key = kvm_async_pf_hash_fn(gfn);
6530 while (vcpu->arch.apf.gfns[key] != ~0)
6531 key = kvm_async_pf_next_probe(key);
6533 vcpu->arch.apf.gfns[key] = gfn;
6536 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6539 u32 key = kvm_async_pf_hash_fn(gfn);
6541 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6542 (vcpu->arch.apf.gfns[key] != gfn &&
6543 vcpu->arch.apf.gfns[key] != ~0); i++)
6544 key = kvm_async_pf_next_probe(key);
6549 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6551 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6554 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6558 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6560 vcpu->arch.apf.gfns[i] = ~0;
6562 j = kvm_async_pf_next_probe(j);
6563 if (vcpu->arch.apf.gfns[j] == ~0)
6565 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6567 * k lies cyclically in ]i,j]
6569 * |....j i.k.| or |.k..j i...|
6571 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6572 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6577 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6580 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6584 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6585 struct kvm_async_pf *work)
6587 struct x86_exception fault;
6589 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6590 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6592 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6593 (vcpu->arch.apf.send_user_only &&
6594 kvm_x86_ops->get_cpl(vcpu) == 0))
6595 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6596 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6597 fault.vector = PF_VECTOR;
6598 fault.error_code_valid = true;
6599 fault.error_code = 0;
6600 fault.nested_page_fault = false;
6601 fault.address = work->arch.token;
6602 kvm_inject_page_fault(vcpu, &fault);
6606 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6607 struct kvm_async_pf *work)
6609 struct x86_exception fault;
6611 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6612 if (is_error_page(work->page))
6613 work->arch.token = ~0; /* broadcast wakeup */
6615 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6617 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6618 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6619 fault.vector = PF_VECTOR;
6620 fault.error_code_valid = true;
6621 fault.error_code = 0;
6622 fault.nested_page_fault = false;
6623 fault.address = work->arch.token;
6624 kvm_inject_page_fault(vcpu, &fault);
6626 vcpu->arch.apf.halted = false;
6627 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6630 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6632 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6635 return !kvm_event_needs_reinjection(vcpu) &&
6636 kvm_x86_ops->interrupt_allowed(vcpu);
6639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6640 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6641 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6642 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6643 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6644 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6645 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6646 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6647 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6648 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6649 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6650 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);