2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32 kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
106 #define KVM_NR_SHARED_MSRS 16
108 struct kvm_shared_msrs_global {
110 u32 msrs[KVM_NR_SHARED_MSRS];
113 struct kvm_shared_msrs {
114 struct user_return_notifier urn;
116 struct kvm_shared_msr_values {
119 } values[KVM_NR_SHARED_MSRS];
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static struct kvm_shared_msrs __percpu *shared_msrs;
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138 { "hypercalls", VCPU_STAT(hypercalls) },
139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146 { "irq_injections", VCPU_STAT(irq_injections) },
147 { "nmi_injections", VCPU_STAT(nmi_injections) },
148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155 { "mmu_unsync", VM_STAT(mmu_unsync) },
156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157 { "largepages", VM_STAT(lpages) },
161 u64 __read_mostly host_xcr0;
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
165 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
167 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
174 static void kvm_on_user_return(struct user_return_notifier *urn)
177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
179 struct kvm_shared_msr_values *values;
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
192 static void shared_msr_update(unsigned slot, u32 msr)
195 unsigned int cpu = smp_processor_id();
196 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
209 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
217 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219 static void kvm_shared_msr_cpu_online(void)
223 for (i = 0; i < shared_msrs_global.nr; ++i)
224 shared_msr_update(i, shared_msrs_global.msrs[i]);
227 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 unsigned int cpu = smp_processor_id();
230 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232 if (((value ^ smsr->values[slot].curr) & mask) == 0)
234 smsr->values[slot].curr = value;
235 wrmsrl(shared_msrs_global.msrs[slot], value);
236 if (!smsr->registered) {
237 smsr->urn.on_user_return = kvm_on_user_return;
238 user_return_notifier_register(&smsr->urn);
239 smsr->registered = true;
242 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244 static void drop_user_return_notifiers(void *ignore)
246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249 if (smsr->registered)
250 kvm_on_user_return(&smsr->urn);
253 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 return vcpu->arch.apic_base;
257 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261 /* TODO: reserve bits check */
262 kvm_lapic_set_base(vcpu, data);
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266 #define EXCPT_BENIGN 0
267 #define EXCPT_CONTRIBUTORY 1
270 static int exception_class(int vector)
280 return EXCPT_CONTRIBUTORY;
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288 unsigned nr, bool has_error, u32 error_code,
294 kvm_make_request(KVM_REQ_EVENT, vcpu);
296 if (!vcpu->arch.exception.pending) {
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
302 vcpu->arch.exception.reinject = reinject;
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331 kvm_multiple_exception(vcpu, nr, false, 0, false);
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
344 kvm_inject_gp(vcpu, 0);
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
352 ++vcpu->stat.pf_guest;
353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
415 real_gfn = gpa_to_gfn(real_gfn);
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
429 * Load the pae pdptrs. Return true is they are all valid.
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447 if (is_present_gpte(pdpte[i]) &&
448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
464 EXPORT_SYMBOL_GPL(load_pdptrs);
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
502 if (cr0 & 0xffffffff00000000UL)
506 cr0 &= ~CR0_RESERVED_BITS;
508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
516 if ((vcpu->arch.efer & EFER_LME)) {
521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
534 kvm_x86_ops->set_cr0(vcpu, cr0);
536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
537 kvm_clear_async_pf_completion_queue(vcpu);
538 kvm_async_pf_hash_reset(vcpu);
541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
545 EXPORT_SYMBOL_GPL(kvm_set_cr0);
547 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
551 EXPORT_SYMBOL_GPL(kvm_lmsw);
553 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
563 if (!(xcr0 & XSTATE_FP))
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
567 if (xcr0 & ~host_xcr0)
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
574 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
582 EXPORT_SYMBOL_GPL(kvm_set_xcr);
584 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
589 if (cr4 & CR4_RESERVED_BITS)
592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
601 if (is_long_mode(vcpu)) {
602 if (!(cr4 & X86_CR4_PAE))
604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
624 kvm_mmu_reset_context(vcpu);
626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627 kvm_update_cpuid(vcpu);
631 EXPORT_SYMBOL_GPL(kvm_set_cr4);
633 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
636 kvm_mmu_sync_roots(vcpu);
637 kvm_mmu_flush_tlb(vcpu);
641 if (is_long_mode(vcpu)) {
642 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
650 if (cr3 & CR3_PAE_RESERVED_BITS)
652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
673 vcpu->arch.cr3 = cr3;
674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
675 vcpu->arch.mmu.new_cr3(vcpu);
678 EXPORT_SYMBOL_GPL(kvm_set_cr3);
680 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
682 if (cr8 & CR8_RESERVED_BITS)
684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
687 vcpu->arch.cr8 = cr8;
690 EXPORT_SYMBOL_GPL(kvm_set_cr8);
692 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
697 return vcpu->arch.cr8;
699 EXPORT_SYMBOL_GPL(kvm_get_cr8);
701 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
705 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
706 dr7 = vcpu->arch.guest_debug_dr7;
708 dr7 = vcpu->arch.dr7;
709 kvm_x86_ops->set_dr7(vcpu, dr7);
710 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
713 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
717 vcpu->arch.db[dr] = val;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
719 vcpu->arch.eff_db[dr] = val;
722 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
726 if (val & 0xffffffff00000000ULL)
728 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
731 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
735 if (val & 0xffffffff00000000ULL)
737 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
738 kvm_update_dr7(vcpu);
745 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
749 res = __kvm_set_dr(vcpu, dr, val);
751 kvm_queue_exception(vcpu, UD_VECTOR);
753 kvm_inject_gp(vcpu, 0);
757 EXPORT_SYMBOL_GPL(kvm_set_dr);
759 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
763 *val = vcpu->arch.db[dr];
766 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
770 *val = vcpu->arch.dr6;
773 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
777 *val = vcpu->arch.dr7;
784 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
786 if (_kvm_get_dr(vcpu, dr, val)) {
787 kvm_queue_exception(vcpu, UD_VECTOR);
792 EXPORT_SYMBOL_GPL(kvm_get_dr);
794 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
796 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
800 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
803 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
804 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
807 EXPORT_SYMBOL_GPL(kvm_rdpmc);
810 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
811 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
813 * This list is modified at module load time to reflect the
814 * capabilities of the host cpu. This capabilities test skips MSRs that are
815 * kvm-specific. Those are put in the beginning of the list.
818 #define KVM_SAVE_MSRS_BEGIN 10
819 static u32 msrs_to_save[] = {
820 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
821 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
822 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
823 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
825 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
828 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
830 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
833 static unsigned num_msrs_to_save;
835 static const u32 emulated_msrs[] = {
837 MSR_IA32_TSCDEADLINE,
838 MSR_IA32_MISC_ENABLE,
843 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
845 u64 old_efer = vcpu->arch.efer;
847 if (efer & efer_reserved_bits)
851 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
854 if (efer & EFER_FFXSR) {
855 struct kvm_cpuid_entry2 *feat;
857 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
858 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
862 if (efer & EFER_SVME) {
863 struct kvm_cpuid_entry2 *feat;
865 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
866 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
871 efer |= vcpu->arch.efer & EFER_LMA;
873 kvm_x86_ops->set_efer(vcpu, efer);
875 /* Update reserved bits */
876 if ((efer ^ old_efer) & EFER_NX)
877 kvm_mmu_reset_context(vcpu);
882 void kvm_enable_efer_bits(u64 mask)
884 efer_reserved_bits &= ~mask;
886 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
890 * Writes msr value into into the appropriate "register".
891 * Returns 0 on success, non-0 otherwise.
892 * Assumes vcpu_load() was already called.
894 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
896 return kvm_x86_ops->set_msr(vcpu, msr);
900 * Adapt set_msr() to msr_io()'s calling convention
902 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
908 msr.host_initiated = true;
909 return kvm_set_msr(vcpu, &msr);
913 struct pvclock_gtod_data {
916 struct { /* extract of a clocksource struct */
924 /* open coded 'struct timespec' */
925 u64 monotonic_time_snsec;
926 time_t monotonic_time_sec;
929 static struct pvclock_gtod_data pvclock_gtod_data;
931 static void update_pvclock_gtod(struct timekeeper *tk)
933 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
935 write_seqcount_begin(&vdata->seq);
937 /* copy pvclock gtod data */
938 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
939 vdata->clock.cycle_last = tk->clock->cycle_last;
940 vdata->clock.mask = tk->clock->mask;
941 vdata->clock.mult = tk->mult;
942 vdata->clock.shift = tk->shift;
944 vdata->monotonic_time_sec = tk->xtime_sec
945 + tk->wall_to_monotonic.tv_sec;
946 vdata->monotonic_time_snsec = tk->xtime_nsec
947 + (tk->wall_to_monotonic.tv_nsec
949 while (vdata->monotonic_time_snsec >=
950 (((u64)NSEC_PER_SEC) << tk->shift)) {
951 vdata->monotonic_time_snsec -=
952 ((u64)NSEC_PER_SEC) << tk->shift;
953 vdata->monotonic_time_sec++;
956 write_seqcount_end(&vdata->seq);
961 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
965 struct pvclock_wall_clock wc;
966 struct timespec boot;
971 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
976 ++version; /* first time write, random junk */
980 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
983 * The guest calculates current wall clock time by adding
984 * system time (updated by kvm_guest_time_update below) to the
985 * wall clock specified here. guest system time equals host
986 * system time for us, thus we must fill in host boot time here.
990 if (kvm->arch.kvmclock_offset) {
991 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
992 boot = timespec_sub(boot, ts);
994 wc.sec = boot.tv_sec;
995 wc.nsec = boot.tv_nsec;
996 wc.version = version;
998 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1001 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1004 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1006 uint32_t quotient, remainder;
1008 /* Don't try to replace with do_div(), this one calculates
1009 * "(dividend << 32) / divisor" */
1011 : "=a" (quotient), "=d" (remainder)
1012 : "0" (0), "1" (dividend), "r" (divisor) );
1016 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1017 s8 *pshift, u32 *pmultiplier)
1024 tps64 = base_khz * 1000LL;
1025 scaled64 = scaled_khz * 1000LL;
1026 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1031 tps32 = (uint32_t)tps64;
1032 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1033 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1041 *pmultiplier = div_frac(scaled64, tps32);
1043 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1044 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1047 static inline u64 get_kernel_ns(void)
1051 WARN_ON(preemptible());
1053 monotonic_to_bootbased(&ts);
1054 return timespec_to_ns(&ts);
1057 #ifdef CONFIG_X86_64
1058 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1061 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1062 unsigned long max_tsc_khz;
1064 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1066 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1067 vcpu->arch.virtual_tsc_shift);
1070 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1072 u64 v = (u64)khz * (1000000 + ppm);
1077 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1079 u32 thresh_lo, thresh_hi;
1080 int use_scaling = 0;
1082 /* Compute a scale to convert nanoseconds in TSC cycles */
1083 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1084 &vcpu->arch.virtual_tsc_shift,
1085 &vcpu->arch.virtual_tsc_mult);
1086 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1089 * Compute the variation in TSC rate which is acceptable
1090 * within the range of tolerance and decide if the
1091 * rate being applied is within that bounds of the hardware
1092 * rate. If so, no scaling or compensation need be done.
1094 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1095 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1096 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1097 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1100 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1103 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1105 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1106 vcpu->arch.virtual_tsc_mult,
1107 vcpu->arch.virtual_tsc_shift);
1108 tsc += vcpu->arch.this_tsc_write;
1112 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1114 #ifdef CONFIG_X86_64
1116 bool do_request = false;
1117 struct kvm_arch *ka = &vcpu->kvm->arch;
1118 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1120 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1121 atomic_read(&vcpu->kvm->online_vcpus));
1123 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1124 if (!ka->use_master_clock)
1127 if (!vcpus_matched && ka->use_master_clock)
1131 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1133 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1134 atomic_read(&vcpu->kvm->online_vcpus),
1135 ka->use_master_clock, gtod->clock.vclock_mode);
1139 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1141 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1142 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1145 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1147 struct kvm *kvm = vcpu->kvm;
1148 u64 offset, ns, elapsed;
1149 unsigned long flags;
1152 u64 data = msr->data;
1154 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1155 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1156 ns = get_kernel_ns();
1157 elapsed = ns - kvm->arch.last_tsc_nsec;
1159 /* n.b - signed multiplication and division required */
1160 usdiff = data - kvm->arch.last_tsc_write;
1161 #ifdef CONFIG_X86_64
1162 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1164 /* do_div() only does unsigned */
1165 asm("idivl %2; xor %%edx, %%edx"
1167 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1169 do_div(elapsed, 1000);
1175 * Special case: TSC write with a small delta (1 second) of virtual
1176 * cycle time against real time is interpreted as an attempt to
1177 * synchronize the CPU.
1179 * For a reliable TSC, we can match TSC offsets, and for an unstable
1180 * TSC, we add elapsed time in this computation. We could let the
1181 * compensation code attempt to catch up if we fall behind, but
1182 * it's better to try to match offsets from the beginning.
1184 if (usdiff < USEC_PER_SEC &&
1185 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1186 if (!check_tsc_unstable()) {
1187 offset = kvm->arch.cur_tsc_offset;
1188 pr_debug("kvm: matched tsc offset for %llu\n", data);
1190 u64 delta = nsec_to_cycles(vcpu, elapsed);
1192 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1193 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1198 * We split periods of matched TSC writes into generations.
1199 * For each generation, we track the original measured
1200 * nanosecond time, offset, and write, so if TSCs are in
1201 * sync, we can match exact offset, and if not, we can match
1202 * exact software computation in compute_guest_tsc()
1204 * These values are tracked in kvm->arch.cur_xxx variables.
1206 kvm->arch.cur_tsc_generation++;
1207 kvm->arch.cur_tsc_nsec = ns;
1208 kvm->arch.cur_tsc_write = data;
1209 kvm->arch.cur_tsc_offset = offset;
1211 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1212 kvm->arch.cur_tsc_generation, data);
1216 * We also track th most recent recorded KHZ, write and time to
1217 * allow the matching interval to be extended at each write.
1219 kvm->arch.last_tsc_nsec = ns;
1220 kvm->arch.last_tsc_write = data;
1221 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1223 /* Reset of TSC must disable overshoot protection below */
1224 vcpu->arch.hv_clock.tsc_timestamp = 0;
1225 vcpu->arch.last_guest_tsc = data;
1227 /* Keep track of which generation this VCPU has synchronized to */
1228 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1229 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1230 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1232 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1233 update_ia32_tsc_adjust_msr(vcpu, offset);
1234 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1235 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1237 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1239 kvm->arch.nr_vcpus_matched_tsc++;
1241 kvm->arch.nr_vcpus_matched_tsc = 0;
1243 kvm_track_tsc_matching(vcpu);
1244 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1247 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1249 #ifdef CONFIG_X86_64
1251 static cycle_t read_tsc(void)
1257 * Empirically, a fence (of type that depends on the CPU)
1258 * before rdtsc is enough to ensure that rdtsc is ordered
1259 * with respect to loads. The various CPU manuals are unclear
1260 * as to whether rdtsc can be reordered with later loads,
1261 * but no one has ever seen it happen.
1264 ret = (cycle_t)vget_cycles();
1266 last = pvclock_gtod_data.clock.cycle_last;
1268 if (likely(ret >= last))
1272 * GCC likes to generate cmov here, but this branch is extremely
1273 * predictable (it's just a funciton of time and the likely is
1274 * very likely) and there's a data dependence, so force GCC
1275 * to generate a branch instead. I don't barrier() because
1276 * we don't actually need a barrier, and if this function
1277 * ever gets inlined it will generate worse code.
1283 static inline u64 vgettsc(cycle_t *cycle_now)
1286 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1288 *cycle_now = read_tsc();
1290 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1291 return v * gtod->clock.mult;
1294 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1299 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1303 seq = read_seqcount_begin(>od->seq);
1304 mode = gtod->clock.vclock_mode;
1305 ts->tv_sec = gtod->monotonic_time_sec;
1306 ns = gtod->monotonic_time_snsec;
1307 ns += vgettsc(cycle_now);
1308 ns >>= gtod->clock.shift;
1309 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1310 timespec_add_ns(ts, ns);
1315 /* returns true if host is using tsc clocksource */
1316 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1320 /* checked again under seqlock below */
1321 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1324 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1327 monotonic_to_bootbased(&ts);
1328 *kernel_ns = timespec_to_ns(&ts);
1336 * Assuming a stable TSC across physical CPUS, and a stable TSC
1337 * across virtual CPUs, the following condition is possible.
1338 * Each numbered line represents an event visible to both
1339 * CPUs at the next numbered event.
1341 * "timespecX" represents host monotonic time. "tscX" represents
1344 * VCPU0 on CPU0 | VCPU1 on CPU1
1346 * 1. read timespec0,tsc0
1347 * 2. | timespec1 = timespec0 + N
1349 * 3. transition to guest | transition to guest
1350 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1351 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1352 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1354 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1357 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1359 * - 0 < N - M => M < N
1361 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1362 * always the case (the difference between two distinct xtime instances
1363 * might be smaller then the difference between corresponding TSC reads,
1364 * when updating guest vcpus pvclock areas).
1366 * To avoid that problem, do not allow visibility of distinct
1367 * system_timestamp/tsc_timestamp values simultaneously: use a master
1368 * copy of host monotonic time values. Update that master copy
1371 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1375 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1377 #ifdef CONFIG_X86_64
1378 struct kvm_arch *ka = &kvm->arch;
1380 bool host_tsc_clocksource, vcpus_matched;
1382 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1383 atomic_read(&kvm->online_vcpus));
1386 * If the host uses TSC clock, then passthrough TSC as stable
1389 host_tsc_clocksource = kvm_get_time_and_clockread(
1390 &ka->master_kernel_ns,
1391 &ka->master_cycle_now);
1393 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1395 if (ka->use_master_clock)
1396 atomic_set(&kvm_guest_has_master_clock, 1);
1398 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1399 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1404 static int kvm_guest_time_update(struct kvm_vcpu *v)
1406 unsigned long flags, this_tsc_khz;
1407 struct kvm_vcpu_arch *vcpu = &v->arch;
1408 struct kvm_arch *ka = &v->kvm->arch;
1409 s64 kernel_ns, max_kernel_ns;
1410 u64 tsc_timestamp, host_tsc;
1411 struct pvclock_vcpu_time_info guest_hv_clock;
1413 bool use_master_clock;
1419 * If the host uses TSC clock, then passthrough TSC as stable
1422 spin_lock(&ka->pvclock_gtod_sync_lock);
1423 use_master_clock = ka->use_master_clock;
1424 if (use_master_clock) {
1425 host_tsc = ka->master_cycle_now;
1426 kernel_ns = ka->master_kernel_ns;
1428 spin_unlock(&ka->pvclock_gtod_sync_lock);
1430 /* Keep irq disabled to prevent changes to the clock */
1431 local_irq_save(flags);
1432 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1433 if (unlikely(this_tsc_khz == 0)) {
1434 local_irq_restore(flags);
1435 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1438 if (!use_master_clock) {
1439 host_tsc = native_read_tsc();
1440 kernel_ns = get_kernel_ns();
1443 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1446 * We may have to catch up the TSC to match elapsed wall clock
1447 * time for two reasons, even if kvmclock is used.
1448 * 1) CPU could have been running below the maximum TSC rate
1449 * 2) Broken TSC compensation resets the base at each VCPU
1450 * entry to avoid unknown leaps of TSC even when running
1451 * again on the same CPU. This may cause apparent elapsed
1452 * time to disappear, and the guest to stand still or run
1455 if (vcpu->tsc_catchup) {
1456 u64 tsc = compute_guest_tsc(v, kernel_ns);
1457 if (tsc > tsc_timestamp) {
1458 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1459 tsc_timestamp = tsc;
1463 local_irq_restore(flags);
1465 if (!vcpu->pv_time_enabled)
1469 * Time as measured by the TSC may go backwards when resetting the base
1470 * tsc_timestamp. The reason for this is that the TSC resolution is
1471 * higher than the resolution of the other clock scales. Thus, many
1472 * possible measurments of the TSC correspond to one measurement of any
1473 * other clock, and so a spread of values is possible. This is not a
1474 * problem for the computation of the nanosecond clock; with TSC rates
1475 * around 1GHZ, there can only be a few cycles which correspond to one
1476 * nanosecond value, and any path through this code will inevitably
1477 * take longer than that. However, with the kernel_ns value itself,
1478 * the precision may be much lower, down to HZ granularity. If the
1479 * first sampling of TSC against kernel_ns ends in the low part of the
1480 * range, and the second in the high end of the range, we can get:
1482 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1484 * As the sampling errors potentially range in the thousands of cycles,
1485 * it is possible such a time value has already been observed by the
1486 * guest. To protect against this, we must compute the system time as
1487 * observed by the guest and ensure the new system time is greater.
1490 if (vcpu->hv_clock.tsc_timestamp) {
1491 max_kernel_ns = vcpu->last_guest_tsc -
1492 vcpu->hv_clock.tsc_timestamp;
1493 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1494 vcpu->hv_clock.tsc_to_system_mul,
1495 vcpu->hv_clock.tsc_shift);
1496 max_kernel_ns += vcpu->last_kernel_ns;
1499 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1500 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1501 &vcpu->hv_clock.tsc_shift,
1502 &vcpu->hv_clock.tsc_to_system_mul);
1503 vcpu->hw_tsc_khz = this_tsc_khz;
1506 /* with a master <monotonic time, tsc value> tuple,
1507 * pvclock clock reads always increase at the (scaled) rate
1508 * of guest TSC - no need to deal with sampling errors.
1510 if (!use_master_clock) {
1511 if (max_kernel_ns > kernel_ns)
1512 kernel_ns = max_kernel_ns;
1514 /* With all the info we got, fill in the values */
1515 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1516 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1517 vcpu->last_kernel_ns = kernel_ns;
1518 vcpu->last_guest_tsc = tsc_timestamp;
1521 * The interface expects us to write an even number signaling that the
1522 * update is finished. Since the guest won't see the intermediate
1523 * state, we just increase by 2 at the end.
1525 vcpu->hv_clock.version += 2;
1527 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1528 &guest_hv_clock, sizeof(guest_hv_clock))))
1531 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1532 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1534 if (vcpu->pvclock_set_guest_stopped_request) {
1535 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1536 vcpu->pvclock_set_guest_stopped_request = false;
1539 /* If the host uses TSC clocksource, then it is stable */
1540 if (use_master_clock)
1541 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1543 vcpu->hv_clock.flags = pvclock_flags;
1545 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1547 sizeof(vcpu->hv_clock));
1551 static bool msr_mtrr_valid(unsigned msr)
1554 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1555 case MSR_MTRRfix64K_00000:
1556 case MSR_MTRRfix16K_80000:
1557 case MSR_MTRRfix16K_A0000:
1558 case MSR_MTRRfix4K_C0000:
1559 case MSR_MTRRfix4K_C8000:
1560 case MSR_MTRRfix4K_D0000:
1561 case MSR_MTRRfix4K_D8000:
1562 case MSR_MTRRfix4K_E0000:
1563 case MSR_MTRRfix4K_E8000:
1564 case MSR_MTRRfix4K_F0000:
1565 case MSR_MTRRfix4K_F8000:
1566 case MSR_MTRRdefType:
1567 case MSR_IA32_CR_PAT:
1575 static bool valid_pat_type(unsigned t)
1577 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1580 static bool valid_mtrr_type(unsigned t)
1582 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1585 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1589 if (!msr_mtrr_valid(msr))
1592 if (msr == MSR_IA32_CR_PAT) {
1593 for (i = 0; i < 8; i++)
1594 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1597 } else if (msr == MSR_MTRRdefType) {
1600 return valid_mtrr_type(data & 0xff);
1601 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1602 for (i = 0; i < 8 ; i++)
1603 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1608 /* variable MTRRs */
1609 return valid_mtrr_type(data & 0xff);
1612 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1614 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1616 if (!mtrr_valid(vcpu, msr, data))
1619 if (msr == MSR_MTRRdefType) {
1620 vcpu->arch.mtrr_state.def_type = data;
1621 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1622 } else if (msr == MSR_MTRRfix64K_00000)
1624 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1625 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1626 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1627 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1628 else if (msr == MSR_IA32_CR_PAT)
1629 vcpu->arch.pat = data;
1630 else { /* Variable MTRRs */
1631 int idx, is_mtrr_mask;
1634 idx = (msr - 0x200) / 2;
1635 is_mtrr_mask = msr - 0x200 - 2 * idx;
1638 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1641 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1645 kvm_mmu_reset_context(vcpu);
1649 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1651 u64 mcg_cap = vcpu->arch.mcg_cap;
1652 unsigned bank_num = mcg_cap & 0xff;
1655 case MSR_IA32_MCG_STATUS:
1656 vcpu->arch.mcg_status = data;
1658 case MSR_IA32_MCG_CTL:
1659 if (!(mcg_cap & MCG_CTL_P))
1661 if (data != 0 && data != ~(u64)0)
1663 vcpu->arch.mcg_ctl = data;
1666 if (msr >= MSR_IA32_MC0_CTL &&
1667 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1668 u32 offset = msr - MSR_IA32_MC0_CTL;
1669 /* only 0 or all 1s can be written to IA32_MCi_CTL
1670 * some Linux kernels though clear bit 10 in bank 4 to
1671 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1672 * this to avoid an uncatched #GP in the guest
1674 if ((offset & 0x3) == 0 &&
1675 data != 0 && (data | (1 << 10)) != ~(u64)0)
1677 vcpu->arch.mce_banks[offset] = data;
1685 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1687 struct kvm *kvm = vcpu->kvm;
1688 int lm = is_long_mode(vcpu);
1689 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1690 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1691 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1692 : kvm->arch.xen_hvm_config.blob_size_32;
1693 u32 page_num = data & ~PAGE_MASK;
1694 u64 page_addr = data & PAGE_MASK;
1699 if (page_num >= blob_size)
1702 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1707 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1716 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1718 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1721 static bool kvm_hv_msr_partition_wide(u32 msr)
1725 case HV_X64_MSR_GUEST_OS_ID:
1726 case HV_X64_MSR_HYPERCALL:
1734 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1736 struct kvm *kvm = vcpu->kvm;
1739 case HV_X64_MSR_GUEST_OS_ID:
1740 kvm->arch.hv_guest_os_id = data;
1741 /* setting guest os id to zero disables hypercall page */
1742 if (!kvm->arch.hv_guest_os_id)
1743 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1745 case HV_X64_MSR_HYPERCALL: {
1750 /* if guest os id is not set hypercall should remain disabled */
1751 if (!kvm->arch.hv_guest_os_id)
1753 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1754 kvm->arch.hv_hypercall = data;
1757 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1758 addr = gfn_to_hva(kvm, gfn);
1759 if (kvm_is_error_hva(addr))
1761 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1762 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1763 if (__copy_to_user((void __user *)addr, instructions, 4))
1765 kvm->arch.hv_hypercall = data;
1769 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1770 "data 0x%llx\n", msr, data);
1776 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1779 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1782 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1783 vcpu->arch.hv_vapic = data;
1786 addr = gfn_to_hva(vcpu->kvm, data >>
1787 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1788 if (kvm_is_error_hva(addr))
1790 if (__clear_user((void __user *)addr, PAGE_SIZE))
1792 vcpu->arch.hv_vapic = data;
1795 case HV_X64_MSR_EOI:
1796 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1797 case HV_X64_MSR_ICR:
1798 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1799 case HV_X64_MSR_TPR:
1800 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1802 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1803 "data 0x%llx\n", msr, data);
1810 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1812 gpa_t gpa = data & ~0x3f;
1814 /* Bits 2:5 are reserved, Should be zero */
1818 vcpu->arch.apf.msr_val = data;
1820 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1821 kvm_clear_async_pf_completion_queue(vcpu);
1822 kvm_async_pf_hash_reset(vcpu);
1826 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1829 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1830 kvm_async_pf_wakeup_all(vcpu);
1834 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1836 vcpu->arch.pv_time_enabled = false;
1839 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1843 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1846 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1847 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1848 vcpu->arch.st.accum_steal = delta;
1851 static void record_steal_time(struct kvm_vcpu *vcpu)
1853 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1856 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1857 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1860 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1861 vcpu->arch.st.steal.version += 2;
1862 vcpu->arch.st.accum_steal = 0;
1864 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1865 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1868 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1871 u32 msr = msr_info->index;
1872 u64 data = msr_info->data;
1875 case MSR_AMD64_NB_CFG:
1876 case MSR_IA32_UCODE_REV:
1877 case MSR_IA32_UCODE_WRITE:
1878 case MSR_VM_HSAVE_PA:
1879 case MSR_AMD64_PATCH_LOADER:
1880 case MSR_AMD64_BU_CFG2:
1884 return set_efer(vcpu, data);
1886 data &= ~(u64)0x40; /* ignore flush filter disable */
1887 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1888 data &= ~(u64)0x8; /* ignore TLB cache disable */
1890 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1895 case MSR_FAM10H_MMIO_CONF_BASE:
1897 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1902 case MSR_IA32_DEBUGCTLMSR:
1904 /* We support the non-activated case already */
1906 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1907 /* Values other than LBR and BTF are vendor-specific,
1908 thus reserved and should throw a #GP */
1911 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1914 case 0x200 ... 0x2ff:
1915 return set_msr_mtrr(vcpu, msr, data);
1916 case MSR_IA32_APICBASE:
1917 kvm_set_apic_base(vcpu, data);
1919 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1920 return kvm_x2apic_msr_write(vcpu, msr, data);
1921 case MSR_IA32_TSCDEADLINE:
1922 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1924 case MSR_IA32_TSC_ADJUST:
1925 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1926 if (!msr_info->host_initiated) {
1927 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1928 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1930 vcpu->arch.ia32_tsc_adjust_msr = data;
1933 case MSR_IA32_MISC_ENABLE:
1934 vcpu->arch.ia32_misc_enable_msr = data;
1936 case MSR_KVM_WALL_CLOCK_NEW:
1937 case MSR_KVM_WALL_CLOCK:
1938 vcpu->kvm->arch.wall_clock = data;
1939 kvm_write_wall_clock(vcpu->kvm, data);
1941 case MSR_KVM_SYSTEM_TIME_NEW:
1942 case MSR_KVM_SYSTEM_TIME: {
1944 kvmclock_reset(vcpu);
1946 vcpu->arch.time = data;
1947 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1949 /* we verify if the enable bit is set... */
1953 gpa_offset = data & ~(PAGE_MASK | 1);
1955 /* Check that the address is 32-byte aligned. */
1956 if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
1959 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1960 &vcpu->arch.pv_time, data & ~1ULL))
1961 vcpu->arch.pv_time_enabled = false;
1963 vcpu->arch.pv_time_enabled = true;
1967 case MSR_KVM_ASYNC_PF_EN:
1968 if (kvm_pv_enable_async_pf(vcpu, data))
1971 case MSR_KVM_STEAL_TIME:
1973 if (unlikely(!sched_info_on()))
1976 if (data & KVM_STEAL_RESERVED_MASK)
1979 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1980 data & KVM_STEAL_VALID_BITS))
1983 vcpu->arch.st.msr_val = data;
1985 if (!(data & KVM_MSR_ENABLED))
1988 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1991 accumulate_steal_time(vcpu);
1994 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1997 case MSR_KVM_PV_EOI_EN:
1998 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2002 case MSR_IA32_MCG_CTL:
2003 case MSR_IA32_MCG_STATUS:
2004 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2005 return set_msr_mce(vcpu, msr, data);
2007 /* Performance counters are not protected by a CPUID bit,
2008 * so we should check all of them in the generic path for the sake of
2009 * cross vendor migration.
2010 * Writing a zero into the event select MSRs disables them,
2011 * which we perfectly emulate ;-). Any other value should be at least
2012 * reported, some guests depend on them.
2014 case MSR_K7_EVNTSEL0:
2015 case MSR_K7_EVNTSEL1:
2016 case MSR_K7_EVNTSEL2:
2017 case MSR_K7_EVNTSEL3:
2019 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2020 "0x%x data 0x%llx\n", msr, data);
2022 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2023 * so we ignore writes to make it happy.
2025 case MSR_K7_PERFCTR0:
2026 case MSR_K7_PERFCTR1:
2027 case MSR_K7_PERFCTR2:
2028 case MSR_K7_PERFCTR3:
2029 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2030 "0x%x data 0x%llx\n", msr, data);
2032 case MSR_P6_PERFCTR0:
2033 case MSR_P6_PERFCTR1:
2035 case MSR_P6_EVNTSEL0:
2036 case MSR_P6_EVNTSEL1:
2037 if (kvm_pmu_msr(vcpu, msr))
2038 return kvm_pmu_set_msr(vcpu, msr, data);
2040 if (pr || data != 0)
2041 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2042 "0x%x data 0x%llx\n", msr, data);
2044 case MSR_K7_CLK_CTL:
2046 * Ignore all writes to this no longer documented MSR.
2047 * Writes are only relevant for old K7 processors,
2048 * all pre-dating SVM, but a recommended workaround from
2049 * AMD for these chips. It is possible to specify the
2050 * affected processor models on the command line, hence
2051 * the need to ignore the workaround.
2054 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2055 if (kvm_hv_msr_partition_wide(msr)) {
2057 mutex_lock(&vcpu->kvm->lock);
2058 r = set_msr_hyperv_pw(vcpu, msr, data);
2059 mutex_unlock(&vcpu->kvm->lock);
2062 return set_msr_hyperv(vcpu, msr, data);
2064 case MSR_IA32_BBL_CR_CTL3:
2065 /* Drop writes to this legacy MSR -- see rdmsr
2066 * counterpart for further detail.
2068 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2070 case MSR_AMD64_OSVW_ID_LENGTH:
2071 if (!guest_cpuid_has_osvw(vcpu))
2073 vcpu->arch.osvw.length = data;
2075 case MSR_AMD64_OSVW_STATUS:
2076 if (!guest_cpuid_has_osvw(vcpu))
2078 vcpu->arch.osvw.status = data;
2081 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2082 return xen_hvm_config(vcpu, data);
2083 if (kvm_pmu_msr(vcpu, msr))
2084 return kvm_pmu_set_msr(vcpu, msr, data);
2086 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2090 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2097 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2101 * Reads an msr value (of 'msr_index') into 'pdata'.
2102 * Returns 0 on success, non-0 otherwise.
2103 * Assumes vcpu_load() was already called.
2105 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2107 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2110 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2112 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2114 if (!msr_mtrr_valid(msr))
2117 if (msr == MSR_MTRRdefType)
2118 *pdata = vcpu->arch.mtrr_state.def_type +
2119 (vcpu->arch.mtrr_state.enabled << 10);
2120 else if (msr == MSR_MTRRfix64K_00000)
2122 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2123 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2124 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2125 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2126 else if (msr == MSR_IA32_CR_PAT)
2127 *pdata = vcpu->arch.pat;
2128 else { /* Variable MTRRs */
2129 int idx, is_mtrr_mask;
2132 idx = (msr - 0x200) / 2;
2133 is_mtrr_mask = msr - 0x200 - 2 * idx;
2136 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2139 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2146 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
2153 case MSR_IA32_P5_MC_ADDR:
2154 case MSR_IA32_P5_MC_TYPE:
2157 case MSR_IA32_MCG_CAP:
2158 data = vcpu->arch.mcg_cap;
2160 case MSR_IA32_MCG_CTL:
2161 if (!(mcg_cap & MCG_CTL_P))
2163 data = vcpu->arch.mcg_ctl;
2165 case MSR_IA32_MCG_STATUS:
2166 data = vcpu->arch.mcg_status;
2169 if (msr >= MSR_IA32_MC0_CTL &&
2170 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2171 u32 offset = msr - MSR_IA32_MC0_CTL;
2172 data = vcpu->arch.mce_banks[offset];
2181 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2184 struct kvm *kvm = vcpu->kvm;
2187 case HV_X64_MSR_GUEST_OS_ID:
2188 data = kvm->arch.hv_guest_os_id;
2190 case HV_X64_MSR_HYPERCALL:
2191 data = kvm->arch.hv_hypercall;
2194 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2202 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2207 case HV_X64_MSR_VP_INDEX: {
2210 kvm_for_each_vcpu(r, v, vcpu->kvm)
2215 case HV_X64_MSR_EOI:
2216 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2217 case HV_X64_MSR_ICR:
2218 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2219 case HV_X64_MSR_TPR:
2220 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2221 case HV_X64_MSR_APIC_ASSIST_PAGE:
2222 data = vcpu->arch.hv_vapic;
2225 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2232 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2237 case MSR_IA32_PLATFORM_ID:
2238 case MSR_IA32_EBL_CR_POWERON:
2239 case MSR_IA32_DEBUGCTLMSR:
2240 case MSR_IA32_LASTBRANCHFROMIP:
2241 case MSR_IA32_LASTBRANCHTOIP:
2242 case MSR_IA32_LASTINTFROMIP:
2243 case MSR_IA32_LASTINTTOIP:
2246 case MSR_VM_HSAVE_PA:
2247 case MSR_K7_EVNTSEL0:
2248 case MSR_K7_PERFCTR0:
2249 case MSR_K8_INT_PENDING_MSG:
2250 case MSR_AMD64_NB_CFG:
2251 case MSR_FAM10H_MMIO_CONF_BASE:
2252 case MSR_AMD64_BU_CFG2:
2255 case MSR_P6_PERFCTR0:
2256 case MSR_P6_PERFCTR1:
2257 case MSR_P6_EVNTSEL0:
2258 case MSR_P6_EVNTSEL1:
2259 if (kvm_pmu_msr(vcpu, msr))
2260 return kvm_pmu_get_msr(vcpu, msr, pdata);
2263 case MSR_IA32_UCODE_REV:
2264 data = 0x100000000ULL;
2267 data = 0x500 | KVM_NR_VAR_MTRR;
2269 case 0x200 ... 0x2ff:
2270 return get_msr_mtrr(vcpu, msr, pdata);
2271 case 0xcd: /* fsb frequency */
2275 * MSR_EBC_FREQUENCY_ID
2276 * Conservative value valid for even the basic CPU models.
2277 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2278 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2279 * and 266MHz for model 3, or 4. Set Core Clock
2280 * Frequency to System Bus Frequency Ratio to 1 (bits
2281 * 31:24) even though these are only valid for CPU
2282 * models > 2, however guests may end up dividing or
2283 * multiplying by zero otherwise.
2285 case MSR_EBC_FREQUENCY_ID:
2288 case MSR_IA32_APICBASE:
2289 data = kvm_get_apic_base(vcpu);
2291 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2292 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2294 case MSR_IA32_TSCDEADLINE:
2295 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2297 case MSR_IA32_TSC_ADJUST:
2298 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2300 case MSR_IA32_MISC_ENABLE:
2301 data = vcpu->arch.ia32_misc_enable_msr;
2303 case MSR_IA32_PERF_STATUS:
2304 /* TSC increment by tick */
2306 /* CPU multiplier */
2307 data |= (((uint64_t)4ULL) << 40);
2310 data = vcpu->arch.efer;
2312 case MSR_KVM_WALL_CLOCK:
2313 case MSR_KVM_WALL_CLOCK_NEW:
2314 data = vcpu->kvm->arch.wall_clock;
2316 case MSR_KVM_SYSTEM_TIME:
2317 case MSR_KVM_SYSTEM_TIME_NEW:
2318 data = vcpu->arch.time;
2320 case MSR_KVM_ASYNC_PF_EN:
2321 data = vcpu->arch.apf.msr_val;
2323 case MSR_KVM_STEAL_TIME:
2324 data = vcpu->arch.st.msr_val;
2326 case MSR_KVM_PV_EOI_EN:
2327 data = vcpu->arch.pv_eoi.msr_val;
2329 case MSR_IA32_P5_MC_ADDR:
2330 case MSR_IA32_P5_MC_TYPE:
2331 case MSR_IA32_MCG_CAP:
2332 case MSR_IA32_MCG_CTL:
2333 case MSR_IA32_MCG_STATUS:
2334 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2335 return get_msr_mce(vcpu, msr, pdata);
2336 case MSR_K7_CLK_CTL:
2338 * Provide expected ramp-up count for K7. All other
2339 * are set to zero, indicating minimum divisors for
2342 * This prevents guest kernels on AMD host with CPU
2343 * type 6, model 8 and higher from exploding due to
2344 * the rdmsr failing.
2348 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2349 if (kvm_hv_msr_partition_wide(msr)) {
2351 mutex_lock(&vcpu->kvm->lock);
2352 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2353 mutex_unlock(&vcpu->kvm->lock);
2356 return get_msr_hyperv(vcpu, msr, pdata);
2358 case MSR_IA32_BBL_CR_CTL3:
2359 /* This legacy MSR exists but isn't fully documented in current
2360 * silicon. It is however accessed by winxp in very narrow
2361 * scenarios where it sets bit #19, itself documented as
2362 * a "reserved" bit. Best effort attempt to source coherent
2363 * read data here should the balance of the register be
2364 * interpreted by the guest:
2366 * L2 cache control register 3: 64GB range, 256KB size,
2367 * enabled, latency 0x1, configured
2371 case MSR_AMD64_OSVW_ID_LENGTH:
2372 if (!guest_cpuid_has_osvw(vcpu))
2374 data = vcpu->arch.osvw.length;
2376 case MSR_AMD64_OSVW_STATUS:
2377 if (!guest_cpuid_has_osvw(vcpu))
2379 data = vcpu->arch.osvw.status;
2382 if (kvm_pmu_msr(vcpu, msr))
2383 return kvm_pmu_get_msr(vcpu, msr, pdata);
2385 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2388 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2396 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2399 * Read or write a bunch of msrs. All parameters are kernel addresses.
2401 * @return number of msrs set successfully.
2403 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2404 struct kvm_msr_entry *entries,
2405 int (*do_msr)(struct kvm_vcpu *vcpu,
2406 unsigned index, u64 *data))
2410 idx = srcu_read_lock(&vcpu->kvm->srcu);
2411 for (i = 0; i < msrs->nmsrs; ++i)
2412 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2414 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2420 * Read or write a bunch of msrs. Parameters are user addresses.
2422 * @return number of msrs set successfully.
2424 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2425 int (*do_msr)(struct kvm_vcpu *vcpu,
2426 unsigned index, u64 *data),
2429 struct kvm_msrs msrs;
2430 struct kvm_msr_entry *entries;
2435 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2439 if (msrs.nmsrs >= MAX_IO_MSRS)
2442 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2443 entries = memdup_user(user_msrs->entries, size);
2444 if (IS_ERR(entries)) {
2445 r = PTR_ERR(entries);
2449 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2454 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2465 int kvm_dev_ioctl_check_extension(long ext)
2470 case KVM_CAP_IRQCHIP:
2472 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2473 case KVM_CAP_SET_TSS_ADDR:
2474 case KVM_CAP_EXT_CPUID:
2475 case KVM_CAP_CLOCKSOURCE:
2477 case KVM_CAP_NOP_IO_DELAY:
2478 case KVM_CAP_MP_STATE:
2479 case KVM_CAP_SYNC_MMU:
2480 case KVM_CAP_USER_NMI:
2481 case KVM_CAP_REINJECT_CONTROL:
2482 case KVM_CAP_IRQ_INJECT_STATUS:
2483 case KVM_CAP_ASSIGN_DEV_IRQ:
2485 case KVM_CAP_IOEVENTFD:
2487 case KVM_CAP_PIT_STATE2:
2488 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2489 case KVM_CAP_XEN_HVM:
2490 case KVM_CAP_ADJUST_CLOCK:
2491 case KVM_CAP_VCPU_EVENTS:
2492 case KVM_CAP_HYPERV:
2493 case KVM_CAP_HYPERV_VAPIC:
2494 case KVM_CAP_HYPERV_SPIN:
2495 case KVM_CAP_PCI_SEGMENT:
2496 case KVM_CAP_DEBUGREGS:
2497 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2499 case KVM_CAP_ASYNC_PF:
2500 case KVM_CAP_GET_TSC_KHZ:
2501 case KVM_CAP_PCI_2_3:
2502 case KVM_CAP_KVMCLOCK_CTRL:
2503 case KVM_CAP_READONLY_MEM:
2504 case KVM_CAP_IRQFD_RESAMPLE:
2507 case KVM_CAP_COALESCED_MMIO:
2508 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2511 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2513 case KVM_CAP_NR_VCPUS:
2514 r = KVM_SOFT_MAX_VCPUS;
2516 case KVM_CAP_MAX_VCPUS:
2519 case KVM_CAP_NR_MEMSLOTS:
2520 r = KVM_USER_MEM_SLOTS;
2522 case KVM_CAP_PV_MMU: /* obsolete */
2526 r = iommu_present(&pci_bus_type);
2529 r = KVM_MAX_MCE_BANKS;
2534 case KVM_CAP_TSC_CONTROL:
2535 r = kvm_has_tsc_control;
2537 case KVM_CAP_TSC_DEADLINE_TIMER:
2538 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2548 long kvm_arch_dev_ioctl(struct file *filp,
2549 unsigned int ioctl, unsigned long arg)
2551 void __user *argp = (void __user *)arg;
2555 case KVM_GET_MSR_INDEX_LIST: {
2556 struct kvm_msr_list __user *user_msr_list = argp;
2557 struct kvm_msr_list msr_list;
2561 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2564 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2565 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2568 if (n < msr_list.nmsrs)
2571 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2572 num_msrs_to_save * sizeof(u32)))
2574 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2576 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2581 case KVM_GET_SUPPORTED_CPUID: {
2582 struct kvm_cpuid2 __user *cpuid_arg = argp;
2583 struct kvm_cpuid2 cpuid;
2586 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2588 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2589 cpuid_arg->entries);
2594 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2599 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2602 mce_cap = KVM_MCE_CAP_SUPPORTED;
2604 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2616 static void wbinvd_ipi(void *garbage)
2621 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2623 return vcpu->kvm->arch.iommu_domain &&
2624 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2627 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2629 /* Address WBINVD may be executed by guest */
2630 if (need_emulate_wbinvd(vcpu)) {
2631 if (kvm_x86_ops->has_wbinvd_exit())
2632 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2633 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2634 smp_call_function_single(vcpu->cpu,
2635 wbinvd_ipi, NULL, 1);
2638 kvm_x86_ops->vcpu_load(vcpu, cpu);
2640 /* Apply any externally detected TSC adjustments (due to suspend) */
2641 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2642 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2643 vcpu->arch.tsc_offset_adjustment = 0;
2644 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2647 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2648 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2649 native_read_tsc() - vcpu->arch.last_host_tsc;
2651 mark_tsc_unstable("KVM discovered backwards TSC");
2652 if (check_tsc_unstable()) {
2653 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2654 vcpu->arch.last_guest_tsc);
2655 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2656 vcpu->arch.tsc_catchup = 1;
2659 * On a host with synchronized TSC, there is no need to update
2660 * kvmclock on vcpu->cpu migration
2662 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2663 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2664 if (vcpu->cpu != cpu)
2665 kvm_migrate_timers(vcpu);
2669 accumulate_steal_time(vcpu);
2670 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2673 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2675 kvm_x86_ops->vcpu_put(vcpu);
2676 kvm_put_guest_fpu(vcpu);
2677 vcpu->arch.last_host_tsc = native_read_tsc();
2680 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2681 struct kvm_lapic_state *s)
2683 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2688 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2689 struct kvm_lapic_state *s)
2691 kvm_apic_post_state_restore(vcpu, s);
2692 update_cr8_intercept(vcpu);
2697 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2698 struct kvm_interrupt *irq)
2700 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
2702 if (irqchip_in_kernel(vcpu->kvm))
2705 kvm_queue_interrupt(vcpu, irq->irq, false);
2706 kvm_make_request(KVM_REQ_EVENT, vcpu);
2711 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2713 kvm_inject_nmi(vcpu);
2718 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2719 struct kvm_tpr_access_ctl *tac)
2723 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2727 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2731 unsigned bank_num = mcg_cap & 0xff, bank;
2734 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2736 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2739 vcpu->arch.mcg_cap = mcg_cap;
2740 /* Init IA32_MCG_CTL to all 1s */
2741 if (mcg_cap & MCG_CTL_P)
2742 vcpu->arch.mcg_ctl = ~(u64)0;
2743 /* Init IA32_MCi_CTL to all 1s */
2744 for (bank = 0; bank < bank_num; bank++)
2745 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2750 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2751 struct kvm_x86_mce *mce)
2753 u64 mcg_cap = vcpu->arch.mcg_cap;
2754 unsigned bank_num = mcg_cap & 0xff;
2755 u64 *banks = vcpu->arch.mce_banks;
2757 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2760 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2761 * reporting is disabled
2763 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2764 vcpu->arch.mcg_ctl != ~(u64)0)
2766 banks += 4 * mce->bank;
2768 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2769 * reporting is disabled for the bank
2771 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2773 if (mce->status & MCI_STATUS_UC) {
2774 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2775 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2776 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2779 if (banks[1] & MCI_STATUS_VAL)
2780 mce->status |= MCI_STATUS_OVER;
2781 banks[2] = mce->addr;
2782 banks[3] = mce->misc;
2783 vcpu->arch.mcg_status = mce->mcg_status;
2784 banks[1] = mce->status;
2785 kvm_queue_exception(vcpu, MC_VECTOR);
2786 } else if (!(banks[1] & MCI_STATUS_VAL)
2787 || !(banks[1] & MCI_STATUS_UC)) {
2788 if (banks[1] & MCI_STATUS_VAL)
2789 mce->status |= MCI_STATUS_OVER;
2790 banks[2] = mce->addr;
2791 banks[3] = mce->misc;
2792 banks[1] = mce->status;
2794 banks[1] |= MCI_STATUS_OVER;
2798 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2799 struct kvm_vcpu_events *events)
2802 events->exception.injected =
2803 vcpu->arch.exception.pending &&
2804 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2805 events->exception.nr = vcpu->arch.exception.nr;
2806 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2807 events->exception.pad = 0;
2808 events->exception.error_code = vcpu->arch.exception.error_code;
2810 events->interrupt.injected =
2811 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2812 events->interrupt.nr = vcpu->arch.interrupt.nr;
2813 events->interrupt.soft = 0;
2814 events->interrupt.shadow =
2815 kvm_x86_ops->get_interrupt_shadow(vcpu,
2816 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2818 events->nmi.injected = vcpu->arch.nmi_injected;
2819 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2820 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2821 events->nmi.pad = 0;
2823 events->sipi_vector = vcpu->arch.sipi_vector;
2825 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2826 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2827 | KVM_VCPUEVENT_VALID_SHADOW);
2828 memset(&events->reserved, 0, sizeof(events->reserved));
2831 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2832 struct kvm_vcpu_events *events)
2834 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2835 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2836 | KVM_VCPUEVENT_VALID_SHADOW))
2840 vcpu->arch.exception.pending = events->exception.injected;
2841 vcpu->arch.exception.nr = events->exception.nr;
2842 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2843 vcpu->arch.exception.error_code = events->exception.error_code;
2845 vcpu->arch.interrupt.pending = events->interrupt.injected;
2846 vcpu->arch.interrupt.nr = events->interrupt.nr;
2847 vcpu->arch.interrupt.soft = events->interrupt.soft;
2848 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2849 kvm_x86_ops->set_interrupt_shadow(vcpu,
2850 events->interrupt.shadow);
2852 vcpu->arch.nmi_injected = events->nmi.injected;
2853 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2854 vcpu->arch.nmi_pending = events->nmi.pending;
2855 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2857 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2858 vcpu->arch.sipi_vector = events->sipi_vector;
2860 kvm_make_request(KVM_REQ_EVENT, vcpu);
2865 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2866 struct kvm_debugregs *dbgregs)
2868 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2869 dbgregs->dr6 = vcpu->arch.dr6;
2870 dbgregs->dr7 = vcpu->arch.dr7;
2872 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2875 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2876 struct kvm_debugregs *dbgregs)
2881 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2882 vcpu->arch.dr6 = dbgregs->dr6;
2883 vcpu->arch.dr7 = dbgregs->dr7;
2888 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2889 struct kvm_xsave *guest_xsave)
2892 memcpy(guest_xsave->region,
2893 &vcpu->arch.guest_fpu.state->xsave,
2896 memcpy(guest_xsave->region,
2897 &vcpu->arch.guest_fpu.state->fxsave,
2898 sizeof(struct i387_fxsave_struct));
2899 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2904 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2905 struct kvm_xsave *guest_xsave)
2908 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2911 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2912 guest_xsave->region, xstate_size);
2914 if (xstate_bv & ~XSTATE_FPSSE)
2916 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2917 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2922 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2923 struct kvm_xcrs *guest_xcrs)
2925 if (!cpu_has_xsave) {
2926 guest_xcrs->nr_xcrs = 0;
2930 guest_xcrs->nr_xcrs = 1;
2931 guest_xcrs->flags = 0;
2932 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2933 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2936 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2937 struct kvm_xcrs *guest_xcrs)
2944 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2947 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2948 /* Only support XCR0 currently */
2949 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2950 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2951 guest_xcrs->xcrs[0].value);
2960 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2961 * stopped by the hypervisor. This function will be called from the host only.
2962 * EINVAL is returned when the host attempts to set the flag for a guest that
2963 * does not support pv clocks.
2965 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2967 if (!vcpu->arch.pv_time_enabled)
2969 vcpu->arch.pvclock_set_guest_stopped_request = true;
2970 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2974 long kvm_arch_vcpu_ioctl(struct file *filp,
2975 unsigned int ioctl, unsigned long arg)
2977 struct kvm_vcpu *vcpu = filp->private_data;
2978 void __user *argp = (void __user *)arg;
2981 struct kvm_lapic_state *lapic;
2982 struct kvm_xsave *xsave;
2983 struct kvm_xcrs *xcrs;
2989 case KVM_GET_LAPIC: {
2991 if (!vcpu->arch.apic)
2993 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2998 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3002 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3007 case KVM_SET_LAPIC: {
3009 if (!vcpu->arch.apic)
3011 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3012 if (IS_ERR(u.lapic))
3013 return PTR_ERR(u.lapic);
3015 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3018 case KVM_INTERRUPT: {
3019 struct kvm_interrupt irq;
3022 if (copy_from_user(&irq, argp, sizeof irq))
3024 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3028 r = kvm_vcpu_ioctl_nmi(vcpu);
3031 case KVM_SET_CPUID: {
3032 struct kvm_cpuid __user *cpuid_arg = argp;
3033 struct kvm_cpuid cpuid;
3036 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3038 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3041 case KVM_SET_CPUID2: {
3042 struct kvm_cpuid2 __user *cpuid_arg = argp;
3043 struct kvm_cpuid2 cpuid;
3046 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3048 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3049 cpuid_arg->entries);
3052 case KVM_GET_CPUID2: {
3053 struct kvm_cpuid2 __user *cpuid_arg = argp;
3054 struct kvm_cpuid2 cpuid;
3057 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3059 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3060 cpuid_arg->entries);
3064 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3070 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3073 r = msr_io(vcpu, argp, do_set_msr, 0);
3075 case KVM_TPR_ACCESS_REPORTING: {
3076 struct kvm_tpr_access_ctl tac;
3079 if (copy_from_user(&tac, argp, sizeof tac))
3081 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3085 if (copy_to_user(argp, &tac, sizeof tac))
3090 case KVM_SET_VAPIC_ADDR: {
3091 struct kvm_vapic_addr va;
3094 if (!irqchip_in_kernel(vcpu->kvm))
3097 if (copy_from_user(&va, argp, sizeof va))
3100 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3103 case KVM_X86_SETUP_MCE: {
3107 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3109 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3112 case KVM_X86_SET_MCE: {
3113 struct kvm_x86_mce mce;
3116 if (copy_from_user(&mce, argp, sizeof mce))
3118 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3121 case KVM_GET_VCPU_EVENTS: {
3122 struct kvm_vcpu_events events;
3124 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3127 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3132 case KVM_SET_VCPU_EVENTS: {
3133 struct kvm_vcpu_events events;
3136 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3139 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3142 case KVM_GET_DEBUGREGS: {
3143 struct kvm_debugregs dbgregs;
3145 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3148 if (copy_to_user(argp, &dbgregs,
3149 sizeof(struct kvm_debugregs)))
3154 case KVM_SET_DEBUGREGS: {
3155 struct kvm_debugregs dbgregs;
3158 if (copy_from_user(&dbgregs, argp,
3159 sizeof(struct kvm_debugregs)))
3162 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3165 case KVM_GET_XSAVE: {
3166 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3171 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3174 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3179 case KVM_SET_XSAVE: {
3180 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3181 if (IS_ERR(u.xsave))
3182 return PTR_ERR(u.xsave);
3184 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3187 case KVM_GET_XCRS: {
3188 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3193 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3196 if (copy_to_user(argp, u.xcrs,
3197 sizeof(struct kvm_xcrs)))
3202 case KVM_SET_XCRS: {
3203 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3205 return PTR_ERR(u.xcrs);
3207 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3210 case KVM_SET_TSC_KHZ: {
3214 user_tsc_khz = (u32)arg;
3216 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3219 if (user_tsc_khz == 0)
3220 user_tsc_khz = tsc_khz;
3222 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3227 case KVM_GET_TSC_KHZ: {
3228 r = vcpu->arch.virtual_tsc_khz;
3231 case KVM_KVMCLOCK_CTRL: {
3232 r = kvm_set_guest_paused(vcpu);
3243 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3245 return VM_FAULT_SIGBUS;
3248 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3252 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3254 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3258 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3261 kvm->arch.ept_identity_map_addr = ident_addr;
3265 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3266 u32 kvm_nr_mmu_pages)
3268 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3271 mutex_lock(&kvm->slots_lock);
3273 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3274 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3276 mutex_unlock(&kvm->slots_lock);
3280 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3282 return kvm->arch.n_max_mmu_pages;
3285 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3290 switch (chip->chip_id) {
3291 case KVM_IRQCHIP_PIC_MASTER:
3292 memcpy(&chip->chip.pic,
3293 &pic_irqchip(kvm)->pics[0],
3294 sizeof(struct kvm_pic_state));
3296 case KVM_IRQCHIP_PIC_SLAVE:
3297 memcpy(&chip->chip.pic,
3298 &pic_irqchip(kvm)->pics[1],
3299 sizeof(struct kvm_pic_state));
3301 case KVM_IRQCHIP_IOAPIC:
3302 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3311 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3316 switch (chip->chip_id) {
3317 case KVM_IRQCHIP_PIC_MASTER:
3318 spin_lock(&pic_irqchip(kvm)->lock);
3319 memcpy(&pic_irqchip(kvm)->pics[0],
3321 sizeof(struct kvm_pic_state));
3322 spin_unlock(&pic_irqchip(kvm)->lock);
3324 case KVM_IRQCHIP_PIC_SLAVE:
3325 spin_lock(&pic_irqchip(kvm)->lock);
3326 memcpy(&pic_irqchip(kvm)->pics[1],
3328 sizeof(struct kvm_pic_state));
3329 spin_unlock(&pic_irqchip(kvm)->lock);
3331 case KVM_IRQCHIP_IOAPIC:
3332 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3338 kvm_pic_update_irq(pic_irqchip(kvm));
3342 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3346 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3347 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3348 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3352 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3356 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3357 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3358 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3359 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3363 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3367 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3368 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3369 sizeof(ps->channels));
3370 ps->flags = kvm->arch.vpit->pit_state.flags;
3371 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3372 memset(&ps->reserved, 0, sizeof(ps->reserved));
3376 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3378 int r = 0, start = 0;
3379 u32 prev_legacy, cur_legacy;
3380 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3381 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3382 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3383 if (!prev_legacy && cur_legacy)
3385 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3386 sizeof(kvm->arch.vpit->pit_state.channels));
3387 kvm->arch.vpit->pit_state.flags = ps->flags;
3388 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3389 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3393 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3394 struct kvm_reinject_control *control)
3396 if (!kvm->arch.vpit)
3398 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3399 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3400 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3405 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3406 * @kvm: kvm instance
3407 * @log: slot id and address to which we copy the log
3409 * We need to keep it in mind that VCPU threads can write to the bitmap
3410 * concurrently. So, to avoid losing data, we keep the following order for
3413 * 1. Take a snapshot of the bit and clear it if needed.
3414 * 2. Write protect the corresponding page.
3415 * 3. Flush TLB's if needed.
3416 * 4. Copy the snapshot to the userspace.
3418 * Between 2 and 3, the guest may write to the page using the remaining TLB
3419 * entry. This is not a problem because the page will be reported dirty at
3420 * step 4 using the snapshot taken before and step 3 ensures that successive
3421 * writes will be logged for the next call.
3423 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3426 struct kvm_memory_slot *memslot;
3428 unsigned long *dirty_bitmap;
3429 unsigned long *dirty_bitmap_buffer;
3430 bool is_dirty = false;
3432 mutex_lock(&kvm->slots_lock);
3435 if (log->slot >= KVM_USER_MEM_SLOTS)
3438 memslot = id_to_memslot(kvm->memslots, log->slot);
3440 dirty_bitmap = memslot->dirty_bitmap;
3445 n = kvm_dirty_bitmap_bytes(memslot);
3447 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3448 memset(dirty_bitmap_buffer, 0, n);
3450 spin_lock(&kvm->mmu_lock);
3452 for (i = 0; i < n / sizeof(long); i++) {
3456 if (!dirty_bitmap[i])
3461 mask = xchg(&dirty_bitmap[i], 0);
3462 dirty_bitmap_buffer[i] = mask;
3464 offset = i * BITS_PER_LONG;
3465 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3468 kvm_flush_remote_tlbs(kvm);
3470 spin_unlock(&kvm->mmu_lock);
3473 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3478 mutex_unlock(&kvm->slots_lock);
3482 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3484 if (!irqchip_in_kernel(kvm))
3487 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3488 irq_event->irq, irq_event->level);
3492 long kvm_arch_vm_ioctl(struct file *filp,
3493 unsigned int ioctl, unsigned long arg)
3495 struct kvm *kvm = filp->private_data;
3496 void __user *argp = (void __user *)arg;
3499 * This union makes it completely explicit to gcc-3.x
3500 * that these two variables' stack usage should be
3501 * combined, not added together.
3504 struct kvm_pit_state ps;
3505 struct kvm_pit_state2 ps2;
3506 struct kvm_pit_config pit_config;
3510 case KVM_SET_TSS_ADDR:
3511 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3513 case KVM_SET_IDENTITY_MAP_ADDR: {
3517 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3519 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3522 case KVM_SET_NR_MMU_PAGES:
3523 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3525 case KVM_GET_NR_MMU_PAGES:
3526 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3528 case KVM_CREATE_IRQCHIP: {
3529 struct kvm_pic *vpic;
3531 mutex_lock(&kvm->lock);
3534 goto create_irqchip_unlock;
3536 if (atomic_read(&kvm->online_vcpus))
3537 goto create_irqchip_unlock;
3539 vpic = kvm_create_pic(kvm);
3541 r = kvm_ioapic_init(kvm);
3543 mutex_lock(&kvm->slots_lock);
3544 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3546 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3548 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3550 mutex_unlock(&kvm->slots_lock);
3552 goto create_irqchip_unlock;
3555 goto create_irqchip_unlock;
3557 kvm->arch.vpic = vpic;
3559 r = kvm_setup_default_irq_routing(kvm);
3561 mutex_lock(&kvm->slots_lock);
3562 mutex_lock(&kvm->irq_lock);
3563 kvm_ioapic_destroy(kvm);
3564 kvm_destroy_pic(kvm);
3565 mutex_unlock(&kvm->irq_lock);
3566 mutex_unlock(&kvm->slots_lock);
3568 create_irqchip_unlock:
3569 mutex_unlock(&kvm->lock);
3572 case KVM_CREATE_PIT:
3573 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3575 case KVM_CREATE_PIT2:
3577 if (copy_from_user(&u.pit_config, argp,
3578 sizeof(struct kvm_pit_config)))
3581 mutex_lock(&kvm->slots_lock);
3584 goto create_pit_unlock;
3586 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3590 mutex_unlock(&kvm->slots_lock);
3592 case KVM_GET_IRQCHIP: {
3593 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3594 struct kvm_irqchip *chip;
3596 chip = memdup_user(argp, sizeof(*chip));
3603 if (!irqchip_in_kernel(kvm))
3604 goto get_irqchip_out;
3605 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3607 goto get_irqchip_out;
3609 if (copy_to_user(argp, chip, sizeof *chip))
3610 goto get_irqchip_out;
3616 case KVM_SET_IRQCHIP: {
3617 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3618 struct kvm_irqchip *chip;
3620 chip = memdup_user(argp, sizeof(*chip));
3627 if (!irqchip_in_kernel(kvm))
3628 goto set_irqchip_out;
3629 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3631 goto set_irqchip_out;
3639 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3642 if (!kvm->arch.vpit)
3644 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3648 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3655 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3658 if (!kvm->arch.vpit)
3660 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3663 case KVM_GET_PIT2: {
3665 if (!kvm->arch.vpit)
3667 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3671 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3676 case KVM_SET_PIT2: {
3678 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3681 if (!kvm->arch.vpit)
3683 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3686 case KVM_REINJECT_CONTROL: {
3687 struct kvm_reinject_control control;
3689 if (copy_from_user(&control, argp, sizeof(control)))
3691 r = kvm_vm_ioctl_reinject(kvm, &control);
3694 case KVM_XEN_HVM_CONFIG: {
3696 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3697 sizeof(struct kvm_xen_hvm_config)))
3700 if (kvm->arch.xen_hvm_config.flags)
3705 case KVM_SET_CLOCK: {
3706 struct kvm_clock_data user_ns;
3711 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3719 local_irq_disable();
3720 now_ns = get_kernel_ns();
3721 delta = user_ns.clock - now_ns;
3723 kvm->arch.kvmclock_offset = delta;
3726 case KVM_GET_CLOCK: {
3727 struct kvm_clock_data user_ns;
3730 local_irq_disable();
3731 now_ns = get_kernel_ns();
3732 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3735 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3738 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3751 static void kvm_init_msr_list(void)
3756 /* skip the first msrs in the list. KVM-specific */
3757 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3758 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3761 msrs_to_save[j] = msrs_to_save[i];
3764 num_msrs_to_save = j;
3767 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3775 if (!(vcpu->arch.apic &&
3776 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3777 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3788 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3795 if (!(vcpu->arch.apic &&
3796 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3797 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3799 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3809 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3810 struct kvm_segment *var, int seg)
3812 kvm_x86_ops->set_segment(vcpu, var, seg);
3815 void kvm_get_segment(struct kvm_vcpu *vcpu,
3816 struct kvm_segment *var, int seg)
3818 kvm_x86_ops->get_segment(vcpu, var, seg);
3821 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3824 struct x86_exception exception;
3826 BUG_ON(!mmu_is_nested(vcpu));
3828 /* NPT walks are always user-walks */
3829 access |= PFERR_USER_MASK;
3830 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3835 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3836 struct x86_exception *exception)
3838 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3839 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3842 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3843 struct x86_exception *exception)
3845 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3846 access |= PFERR_FETCH_MASK;
3847 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3850 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3851 struct x86_exception *exception)
3853 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3854 access |= PFERR_WRITE_MASK;
3855 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3858 /* uses this to access any guest's mapped memory without checking CPL */
3859 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3860 struct x86_exception *exception)
3862 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3865 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3866 struct kvm_vcpu *vcpu, u32 access,
3867 struct x86_exception *exception)
3870 int r = X86EMUL_CONTINUE;
3873 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3875 unsigned offset = addr & (PAGE_SIZE-1);
3876 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3879 if (gpa == UNMAPPED_GVA)
3880 return X86EMUL_PROPAGATE_FAULT;
3881 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3883 r = X86EMUL_IO_NEEDED;
3895 /* used for instruction fetching */
3896 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3897 gva_t addr, void *val, unsigned int bytes,
3898 struct x86_exception *exception)
3900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3901 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3903 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3904 access | PFERR_FETCH_MASK,
3908 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3909 gva_t addr, void *val, unsigned int bytes,
3910 struct x86_exception *exception)
3912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3913 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3915 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3918 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3920 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3921 gva_t addr, void *val, unsigned int bytes,
3922 struct x86_exception *exception)
3924 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3925 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3928 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3929 gva_t addr, void *val,
3931 struct x86_exception *exception)
3933 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3935 int r = X86EMUL_CONTINUE;
3938 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3941 unsigned offset = addr & (PAGE_SIZE-1);
3942 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3945 if (gpa == UNMAPPED_GVA)
3946 return X86EMUL_PROPAGATE_FAULT;
3947 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3949 r = X86EMUL_IO_NEEDED;
3960 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3962 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3963 gpa_t *gpa, struct x86_exception *exception,
3966 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3967 | (write ? PFERR_WRITE_MASK : 0);
3969 if (vcpu_match_mmio_gva(vcpu, gva)
3970 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
3971 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3972 (gva & (PAGE_SIZE - 1));
3973 trace_vcpu_match_mmio(gva, *gpa, write, false);
3977 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3979 if (*gpa == UNMAPPED_GVA)
3982 /* For APIC access vmexit */
3983 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3986 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3987 trace_vcpu_match_mmio(gva, *gpa, write, true);
3994 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3995 const void *val, int bytes)
3999 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4002 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4006 struct read_write_emulator_ops {
4007 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4009 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4010 void *val, int bytes);
4011 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4012 int bytes, void *val);
4013 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4014 void *val, int bytes);
4018 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4020 if (vcpu->mmio_read_completed) {
4021 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4022 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4023 vcpu->mmio_read_completed = 0;
4030 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4031 void *val, int bytes)
4033 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4036 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4037 void *val, int bytes)
4039 return emulator_write_phys(vcpu, gpa, val, bytes);
4042 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4044 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4045 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4048 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4049 void *val, int bytes)
4051 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4052 return X86EMUL_IO_NEEDED;
4055 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4056 void *val, int bytes)
4058 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4060 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4061 return X86EMUL_CONTINUE;
4064 static const struct read_write_emulator_ops read_emultor = {
4065 .read_write_prepare = read_prepare,
4066 .read_write_emulate = read_emulate,
4067 .read_write_mmio = vcpu_mmio_read,
4068 .read_write_exit_mmio = read_exit_mmio,
4071 static const struct read_write_emulator_ops write_emultor = {
4072 .read_write_emulate = write_emulate,
4073 .read_write_mmio = write_mmio,
4074 .read_write_exit_mmio = write_exit_mmio,
4078 static int emulator_read_write_onepage(unsigned long addr, void *val,
4080 struct x86_exception *exception,
4081 struct kvm_vcpu *vcpu,
4082 const struct read_write_emulator_ops *ops)
4086 bool write = ops->write;
4087 struct kvm_mmio_fragment *frag;
4089 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4092 return X86EMUL_PROPAGATE_FAULT;
4094 /* For APIC access vmexit */
4098 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4099 return X86EMUL_CONTINUE;
4103 * Is this MMIO handled locally?
4105 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4106 if (handled == bytes)
4107 return X86EMUL_CONTINUE;
4113 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4114 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4118 return X86EMUL_CONTINUE;
4121 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4122 void *val, unsigned int bytes,
4123 struct x86_exception *exception,
4124 const struct read_write_emulator_ops *ops)
4126 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4130 if (ops->read_write_prepare &&
4131 ops->read_write_prepare(vcpu, val, bytes))
4132 return X86EMUL_CONTINUE;
4134 vcpu->mmio_nr_fragments = 0;
4136 /* Crossing a page boundary? */
4137 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4140 now = -addr & ~PAGE_MASK;
4141 rc = emulator_read_write_onepage(addr, val, now, exception,
4144 if (rc != X86EMUL_CONTINUE)
4151 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4153 if (rc != X86EMUL_CONTINUE)
4156 if (!vcpu->mmio_nr_fragments)
4159 gpa = vcpu->mmio_fragments[0].gpa;
4161 vcpu->mmio_needed = 1;
4162 vcpu->mmio_cur_fragment = 0;
4164 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4165 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4166 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4167 vcpu->run->mmio.phys_addr = gpa;
4169 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4172 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4176 struct x86_exception *exception)
4178 return emulator_read_write(ctxt, addr, val, bytes,
4179 exception, &read_emultor);
4182 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4186 struct x86_exception *exception)
4188 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4189 exception, &write_emultor);
4192 #define CMPXCHG_TYPE(t, ptr, old, new) \
4193 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4195 #ifdef CONFIG_X86_64
4196 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4198 # define CMPXCHG64(ptr, old, new) \
4199 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4202 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4207 struct x86_exception *exception)
4209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4215 /* guests cmpxchg8b have to be emulated atomically */
4216 if (bytes > 8 || (bytes & (bytes - 1)))
4219 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4221 if (gpa == UNMAPPED_GVA ||
4222 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4225 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4228 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4229 if (is_error_page(page))
4232 kaddr = kmap_atomic(page);
4233 kaddr += offset_in_page(gpa);
4236 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4239 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4242 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4245 exchanged = CMPXCHG64(kaddr, old, new);
4250 kunmap_atomic(kaddr);
4251 kvm_release_page_dirty(page);
4254 return X86EMUL_CMPXCHG_FAILED;
4256 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4258 return X86EMUL_CONTINUE;
4261 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4263 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4266 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4268 /* TODO: String I/O for in kernel device */
4271 if (vcpu->arch.pio.in)
4272 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4273 vcpu->arch.pio.size, pd);
4275 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4276 vcpu->arch.pio.port, vcpu->arch.pio.size,
4281 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4282 unsigned short port, void *val,
4283 unsigned int count, bool in)
4285 trace_kvm_pio(!in, port, size, count);
4287 vcpu->arch.pio.port = port;
4288 vcpu->arch.pio.in = in;
4289 vcpu->arch.pio.count = count;
4290 vcpu->arch.pio.size = size;
4292 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4293 vcpu->arch.pio.count = 0;
4297 vcpu->run->exit_reason = KVM_EXIT_IO;
4298 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4299 vcpu->run->io.size = size;
4300 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4301 vcpu->run->io.count = count;
4302 vcpu->run->io.port = port;
4307 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4308 int size, unsigned short port, void *val,
4311 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4314 if (vcpu->arch.pio.count)
4317 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4320 memcpy(val, vcpu->arch.pio_data, size * count);
4321 vcpu->arch.pio.count = 0;
4328 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4329 int size, unsigned short port,
4330 const void *val, unsigned int count)
4332 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4334 memcpy(vcpu->arch.pio_data, val, size * count);
4335 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4338 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4340 return kvm_x86_ops->get_segment_base(vcpu, seg);
4343 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4345 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4348 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4350 if (!need_emulate_wbinvd(vcpu))
4351 return X86EMUL_CONTINUE;
4353 if (kvm_x86_ops->has_wbinvd_exit()) {
4354 int cpu = get_cpu();
4356 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4357 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4358 wbinvd_ipi, NULL, 1);
4360 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4363 return X86EMUL_CONTINUE;
4365 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4367 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4369 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4372 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4374 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4377 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4380 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4383 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4385 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4388 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4390 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4391 unsigned long value;
4395 value = kvm_read_cr0(vcpu);
4398 value = vcpu->arch.cr2;
4401 value = kvm_read_cr3(vcpu);
4404 value = kvm_read_cr4(vcpu);
4407 value = kvm_get_cr8(vcpu);
4410 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4417 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4419 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4424 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4427 vcpu->arch.cr2 = val;
4430 res = kvm_set_cr3(vcpu, val);
4433 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4436 res = kvm_set_cr8(vcpu, val);
4439 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4446 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4448 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4451 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4453 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4456 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4458 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4461 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4463 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4466 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4468 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4471 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4473 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4476 static unsigned long emulator_get_cached_segment_base(
4477 struct x86_emulate_ctxt *ctxt, int seg)
4479 return get_segment_base(emul_to_vcpu(ctxt), seg);
4482 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4483 struct desc_struct *desc, u32 *base3,
4486 struct kvm_segment var;
4488 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4489 *selector = var.selector;
4492 memset(desc, 0, sizeof(*desc));
4498 set_desc_limit(desc, var.limit);
4499 set_desc_base(desc, (unsigned long)var.base);
4500 #ifdef CONFIG_X86_64
4502 *base3 = var.base >> 32;
4504 desc->type = var.type;
4506 desc->dpl = var.dpl;
4507 desc->p = var.present;
4508 desc->avl = var.avl;
4516 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4517 struct desc_struct *desc, u32 base3,
4520 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4521 struct kvm_segment var;
4523 var.selector = selector;
4524 var.base = get_desc_base(desc);
4525 #ifdef CONFIG_X86_64
4526 var.base |= ((u64)base3) << 32;
4528 var.limit = get_desc_limit(desc);
4530 var.limit = (var.limit << 12) | 0xfff;
4531 var.type = desc->type;
4532 var.present = desc->p;
4533 var.dpl = desc->dpl;
4538 var.avl = desc->avl;
4539 var.present = desc->p;
4540 var.unusable = !var.present;
4543 kvm_set_segment(vcpu, &var, seg);
4547 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4548 u32 msr_index, u64 *pdata)
4550 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4553 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4554 u32 msr_index, u64 data)
4556 struct msr_data msr;
4559 msr.index = msr_index;
4560 msr.host_initiated = false;
4561 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4564 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4565 u32 pmc, u64 *pdata)
4567 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4570 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4572 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4575 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4578 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4580 * CR0.TS may reference the host fpu state, not the guest fpu state,
4581 * so it may be clear at this point.
4586 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4591 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4592 struct x86_instruction_info *info,
4593 enum x86_intercept_stage stage)
4595 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4598 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4599 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4601 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4604 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4606 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4609 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4611 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4614 static const struct x86_emulate_ops emulate_ops = {
4615 .read_gpr = emulator_read_gpr,
4616 .write_gpr = emulator_write_gpr,
4617 .read_std = kvm_read_guest_virt_system,
4618 .write_std = kvm_write_guest_virt_system,
4619 .fetch = kvm_fetch_guest_virt,
4620 .read_emulated = emulator_read_emulated,
4621 .write_emulated = emulator_write_emulated,
4622 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4623 .invlpg = emulator_invlpg,
4624 .pio_in_emulated = emulator_pio_in_emulated,
4625 .pio_out_emulated = emulator_pio_out_emulated,
4626 .get_segment = emulator_get_segment,
4627 .set_segment = emulator_set_segment,
4628 .get_cached_segment_base = emulator_get_cached_segment_base,
4629 .get_gdt = emulator_get_gdt,
4630 .get_idt = emulator_get_idt,
4631 .set_gdt = emulator_set_gdt,
4632 .set_idt = emulator_set_idt,
4633 .get_cr = emulator_get_cr,
4634 .set_cr = emulator_set_cr,
4635 .set_rflags = emulator_set_rflags,
4636 .cpl = emulator_get_cpl,
4637 .get_dr = emulator_get_dr,
4638 .set_dr = emulator_set_dr,
4639 .set_msr = emulator_set_msr,
4640 .get_msr = emulator_get_msr,
4641 .read_pmc = emulator_read_pmc,
4642 .halt = emulator_halt,
4643 .wbinvd = emulator_wbinvd,
4644 .fix_hypercall = emulator_fix_hypercall,
4645 .get_fpu = emulator_get_fpu,
4646 .put_fpu = emulator_put_fpu,
4647 .intercept = emulator_intercept,
4648 .get_cpuid = emulator_get_cpuid,
4651 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4653 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4655 * an sti; sti; sequence only disable interrupts for the first
4656 * instruction. So, if the last instruction, be it emulated or
4657 * not, left the system with the INT_STI flag enabled, it
4658 * means that the last instruction is an sti. We should not
4659 * leave the flag on in this case. The same goes for mov ss
4661 if (!(int_shadow & mask))
4662 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4665 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4667 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4668 if (ctxt->exception.vector == PF_VECTOR)
4669 kvm_propagate_fault(vcpu, &ctxt->exception);
4670 else if (ctxt->exception.error_code_valid)
4671 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4672 ctxt->exception.error_code);
4674 kvm_queue_exception(vcpu, ctxt->exception.vector);
4677 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4679 memset(&ctxt->twobyte, 0,
4680 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4682 ctxt->fetch.start = 0;
4683 ctxt->fetch.end = 0;
4684 ctxt->io_read.pos = 0;
4685 ctxt->io_read.end = 0;
4686 ctxt->mem_read.pos = 0;
4687 ctxt->mem_read.end = 0;
4690 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4692 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4695 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4697 ctxt->eflags = kvm_get_rflags(vcpu);
4698 ctxt->eip = kvm_rip_read(vcpu);
4699 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4700 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4701 cs_l ? X86EMUL_MODE_PROT64 :
4702 cs_db ? X86EMUL_MODE_PROT32 :
4703 X86EMUL_MODE_PROT16;
4704 ctxt->guest_mode = is_guest_mode(vcpu);
4706 init_decode_cache(ctxt);
4707 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4710 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4712 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4715 init_emulate_ctxt(vcpu);
4719 ctxt->_eip = ctxt->eip + inc_eip;
4720 ret = emulate_int_real(ctxt, irq);
4722 if (ret != X86EMUL_CONTINUE)
4723 return EMULATE_FAIL;
4725 ctxt->eip = ctxt->_eip;
4726 kvm_rip_write(vcpu, ctxt->eip);
4727 kvm_set_rflags(vcpu, ctxt->eflags);
4729 if (irq == NMI_VECTOR)
4730 vcpu->arch.nmi_pending = 0;
4732 vcpu->arch.interrupt.pending = false;
4734 return EMULATE_DONE;
4736 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4738 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4740 int r = EMULATE_DONE;
4742 ++vcpu->stat.insn_emulation_fail;
4743 trace_kvm_emulate_insn_failed(vcpu);
4744 if (!is_guest_mode(vcpu)) {
4745 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4746 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4747 vcpu->run->internal.ndata = 0;
4750 kvm_queue_exception(vcpu, UD_VECTOR);
4755 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4756 bool write_fault_to_shadow_pgtable)
4761 if (!vcpu->arch.mmu.direct_map) {
4763 * Write permission should be allowed since only
4764 * write access need to be emulated.
4766 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4769 * If the mapping is invalid in guest, let cpu retry
4770 * it to generate fault.
4772 if (gpa == UNMAPPED_GVA)
4777 * Do not retry the unhandleable instruction if it faults on the
4778 * readonly host memory, otherwise it will goto a infinite loop:
4779 * retry instruction -> write #PF -> emulation fail -> retry
4780 * instruction -> ...
4782 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4785 * If the instruction failed on the error pfn, it can not be fixed,
4786 * report the error to userspace.
4788 if (is_error_noslot_pfn(pfn))
4791 kvm_release_pfn_clean(pfn);
4793 /* The instructions are well-emulated on direct mmu. */
4794 if (vcpu->arch.mmu.direct_map) {
4795 unsigned int indirect_shadow_pages;
4797 spin_lock(&vcpu->kvm->mmu_lock);
4798 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4799 spin_unlock(&vcpu->kvm->mmu_lock);
4801 if (indirect_shadow_pages)
4802 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4808 * if emulation was due to access to shadowed page table
4809 * and it failed try to unshadow page and re-enter the
4810 * guest to let CPU execute the instruction.
4812 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4815 * If the access faults on its page table, it can not
4816 * be fixed by unprotecting shadow page and it should
4817 * be reported to userspace.
4819 return !write_fault_to_shadow_pgtable;
4822 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4823 unsigned long cr2, int emulation_type)
4825 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4826 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4828 last_retry_eip = vcpu->arch.last_retry_eip;
4829 last_retry_addr = vcpu->arch.last_retry_addr;
4832 * If the emulation is caused by #PF and it is non-page_table
4833 * writing instruction, it means the VM-EXIT is caused by shadow
4834 * page protected, we can zap the shadow page and retry this
4835 * instruction directly.
4837 * Note: if the guest uses a non-page-table modifying instruction
4838 * on the PDE that points to the instruction, then we will unmap
4839 * the instruction and go to an infinite loop. So, we cache the
4840 * last retried eip and the last fault address, if we meet the eip
4841 * and the address again, we can break out of the potential infinite
4844 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4846 if (!(emulation_type & EMULTYPE_RETRY))
4849 if (x86_page_table_writing_insn(ctxt))
4852 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4855 vcpu->arch.last_retry_eip = ctxt->eip;
4856 vcpu->arch.last_retry_addr = cr2;
4858 if (!vcpu->arch.mmu.direct_map)
4859 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4861 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4866 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4867 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4869 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4876 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4877 bool writeback = true;
4878 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4881 * Clear write_fault_to_shadow_pgtable here to ensure it is
4884 vcpu->arch.write_fault_to_shadow_pgtable = false;
4885 kvm_clear_exception_queue(vcpu);
4887 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4888 init_emulate_ctxt(vcpu);
4889 ctxt->interruptibility = 0;
4890 ctxt->have_exception = false;
4891 ctxt->perm_ok = false;
4893 ctxt->only_vendor_specific_insn
4894 = emulation_type & EMULTYPE_TRAP_UD;
4896 r = x86_decode_insn(ctxt, insn, insn_len);
4898 trace_kvm_emulate_insn_start(vcpu);
4899 ++vcpu->stat.insn_emulation;
4900 if (r != EMULATION_OK) {
4901 if (emulation_type & EMULTYPE_TRAP_UD)
4902 return EMULATE_FAIL;
4903 if (reexecute_instruction(vcpu, cr2,
4904 write_fault_to_spt))
4905 return EMULATE_DONE;
4906 if (emulation_type & EMULTYPE_SKIP)
4907 return EMULATE_FAIL;
4908 return handle_emulation_failure(vcpu);
4912 if (emulation_type & EMULTYPE_SKIP) {
4913 kvm_rip_write(vcpu, ctxt->_eip);
4914 return EMULATE_DONE;
4917 if (retry_instruction(ctxt, cr2, emulation_type))
4918 return EMULATE_DONE;
4920 /* this is needed for vmware backdoor interface to work since it
4921 changes registers values during IO operation */
4922 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4923 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4924 emulator_invalidate_register_cache(ctxt);
4928 r = x86_emulate_insn(ctxt);
4930 if (r == EMULATION_INTERCEPTED)
4931 return EMULATE_DONE;
4933 if (r == EMULATION_FAILED) {
4934 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt))
4935 return EMULATE_DONE;
4937 return handle_emulation_failure(vcpu);
4940 if (ctxt->have_exception) {
4941 inject_emulated_exception(vcpu);
4943 } else if (vcpu->arch.pio.count) {
4944 if (!vcpu->arch.pio.in)
4945 vcpu->arch.pio.count = 0;
4948 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4950 r = EMULATE_DO_MMIO;
4951 } else if (vcpu->mmio_needed) {
4952 if (!vcpu->mmio_is_write)
4954 r = EMULATE_DO_MMIO;
4955 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
4956 } else if (r == EMULATION_RESTART)
4962 toggle_interruptibility(vcpu, ctxt->interruptibility);
4963 kvm_set_rflags(vcpu, ctxt->eflags);
4964 kvm_make_request(KVM_REQ_EVENT, vcpu);
4965 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4966 kvm_rip_write(vcpu, ctxt->eip);
4968 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4972 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4974 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4976 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4977 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4978 size, port, &val, 1);
4979 /* do not return to emulator after return from userspace */
4980 vcpu->arch.pio.count = 0;
4983 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4985 static void tsc_bad(void *info)
4987 __this_cpu_write(cpu_tsc_khz, 0);
4990 static void tsc_khz_changed(void *data)
4992 struct cpufreq_freqs *freq = data;
4993 unsigned long khz = 0;
4997 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4998 khz = cpufreq_quick_get(raw_smp_processor_id());
5001 __this_cpu_write(cpu_tsc_khz, khz);
5004 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5007 struct cpufreq_freqs *freq = data;
5009 struct kvm_vcpu *vcpu;
5010 int i, send_ipi = 0;
5013 * We allow guests to temporarily run on slowing clocks,
5014 * provided we notify them after, or to run on accelerating
5015 * clocks, provided we notify them before. Thus time never
5018 * However, we have a problem. We can't atomically update
5019 * the frequency of a given CPU from this function; it is
5020 * merely a notifier, which can be called from any CPU.
5021 * Changing the TSC frequency at arbitrary points in time
5022 * requires a recomputation of local variables related to
5023 * the TSC for each VCPU. We must flag these local variables
5024 * to be updated and be sure the update takes place with the
5025 * new frequency before any guests proceed.
5027 * Unfortunately, the combination of hotplug CPU and frequency
5028 * change creates an intractable locking scenario; the order
5029 * of when these callouts happen is undefined with respect to
5030 * CPU hotplug, and they can race with each other. As such,
5031 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5032 * undefined; you can actually have a CPU frequency change take
5033 * place in between the computation of X and the setting of the
5034 * variable. To protect against this problem, all updates of
5035 * the per_cpu tsc_khz variable are done in an interrupt
5036 * protected IPI, and all callers wishing to update the value
5037 * must wait for a synchronous IPI to complete (which is trivial
5038 * if the caller is on the CPU already). This establishes the
5039 * necessary total order on variable updates.
5041 * Note that because a guest time update may take place
5042 * anytime after the setting of the VCPU's request bit, the
5043 * correct TSC value must be set before the request. However,
5044 * to ensure the update actually makes it to any guest which
5045 * starts running in hardware virtualization between the set
5046 * and the acquisition of the spinlock, we must also ping the
5047 * CPU after setting the request bit.
5051 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5053 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5056 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5058 raw_spin_lock(&kvm_lock);
5059 list_for_each_entry(kvm, &vm_list, vm_list) {
5060 kvm_for_each_vcpu(i, vcpu, kvm) {
5061 if (vcpu->cpu != freq->cpu)
5063 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5064 if (vcpu->cpu != smp_processor_id())
5068 raw_spin_unlock(&kvm_lock);
5070 if (freq->old < freq->new && send_ipi) {
5072 * We upscale the frequency. Must make the guest
5073 * doesn't see old kvmclock values while running with
5074 * the new frequency, otherwise we risk the guest sees
5075 * time go backwards.
5077 * In case we update the frequency for another cpu
5078 * (which might be in guest context) send an interrupt
5079 * to kick the cpu out of guest context. Next time
5080 * guest context is entered kvmclock will be updated,
5081 * so the guest will not see stale values.
5083 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5088 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5089 .notifier_call = kvmclock_cpufreq_notifier
5092 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5093 unsigned long action, void *hcpu)
5095 unsigned int cpu = (unsigned long)hcpu;
5099 case CPU_DOWN_FAILED:
5100 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5102 case CPU_DOWN_PREPARE:
5103 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5109 static struct notifier_block kvmclock_cpu_notifier_block = {
5110 .notifier_call = kvmclock_cpu_notifier,
5111 .priority = -INT_MAX
5114 static void kvm_timer_init(void)
5118 max_tsc_khz = tsc_khz;
5119 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5120 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5121 #ifdef CONFIG_CPU_FREQ
5122 struct cpufreq_policy policy;
5123 memset(&policy, 0, sizeof(policy));
5125 cpufreq_get_policy(&policy, cpu);
5126 if (policy.cpuinfo.max_freq)
5127 max_tsc_khz = policy.cpuinfo.max_freq;
5130 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5131 CPUFREQ_TRANSITION_NOTIFIER);
5133 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5134 for_each_online_cpu(cpu)
5135 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5138 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5140 int kvm_is_in_guest(void)
5142 return __this_cpu_read(current_vcpu) != NULL;
5145 static int kvm_is_user_mode(void)
5149 if (__this_cpu_read(current_vcpu))
5150 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5152 return user_mode != 0;
5155 static unsigned long kvm_get_guest_ip(void)
5157 unsigned long ip = 0;
5159 if (__this_cpu_read(current_vcpu))
5160 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5165 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5166 .is_in_guest = kvm_is_in_guest,
5167 .is_user_mode = kvm_is_user_mode,
5168 .get_guest_ip = kvm_get_guest_ip,
5171 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5173 __this_cpu_write(current_vcpu, vcpu);
5175 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5177 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5179 __this_cpu_write(current_vcpu, NULL);
5181 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5183 static void kvm_set_mmio_spte_mask(void)
5186 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5189 * Set the reserved bits and the present bit of an paging-structure
5190 * entry to generate page fault with PFER.RSV = 1.
5192 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5195 #ifdef CONFIG_X86_64
5197 * If reserved bit is not supported, clear the present bit to disable
5200 if (maxphyaddr == 52)
5204 kvm_mmu_set_mmio_spte_mask(mask);
5207 #ifdef CONFIG_X86_64
5208 static void pvclock_gtod_update_fn(struct work_struct *work)
5212 struct kvm_vcpu *vcpu;
5215 raw_spin_lock(&kvm_lock);
5216 list_for_each_entry(kvm, &vm_list, vm_list)
5217 kvm_for_each_vcpu(i, vcpu, kvm)
5218 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5219 atomic_set(&kvm_guest_has_master_clock, 0);
5220 raw_spin_unlock(&kvm_lock);
5223 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5226 * Notification about pvclock gtod data update.
5228 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5231 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5232 struct timekeeper *tk = priv;
5234 update_pvclock_gtod(tk);
5236 /* disable master clock if host does not trust, or does not
5237 * use, TSC clocksource
5239 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5240 atomic_read(&kvm_guest_has_master_clock) != 0)
5241 queue_work(system_long_wq, &pvclock_gtod_work);
5246 static struct notifier_block pvclock_gtod_notifier = {
5247 .notifier_call = pvclock_gtod_notify,
5251 int kvm_arch_init(void *opaque)
5254 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5257 printk(KERN_ERR "kvm: already loaded the other module\n");
5262 if (!ops->cpu_has_kvm_support()) {
5263 printk(KERN_ERR "kvm: no hardware support\n");
5267 if (ops->disabled_by_bios()) {
5268 printk(KERN_ERR "kvm: disabled by bios\n");
5274 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5276 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5280 r = kvm_mmu_module_init();
5282 goto out_free_percpu;
5284 kvm_set_mmio_spte_mask();
5285 kvm_init_msr_list();
5288 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5289 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5293 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5296 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5299 #ifdef CONFIG_X86_64
5300 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5306 free_percpu(shared_msrs);
5311 void kvm_arch_exit(void)
5313 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5315 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5316 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5317 CPUFREQ_TRANSITION_NOTIFIER);
5318 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5319 #ifdef CONFIG_X86_64
5320 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5323 kvm_mmu_module_exit();
5324 free_percpu(shared_msrs);
5327 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5329 ++vcpu->stat.halt_exits;
5330 if (irqchip_in_kernel(vcpu->kvm)) {
5331 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5334 vcpu->run->exit_reason = KVM_EXIT_HLT;
5338 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5340 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5342 u64 param, ingpa, outgpa, ret;
5343 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5344 bool fast, longmode;
5348 * hypercall generates UD from non zero cpl and real mode
5351 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5352 kvm_queue_exception(vcpu, UD_VECTOR);
5356 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5357 longmode = is_long_mode(vcpu) && cs_l == 1;
5360 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5361 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5362 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5363 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5364 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5365 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5367 #ifdef CONFIG_X86_64
5369 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5370 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5371 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5375 code = param & 0xffff;
5376 fast = (param >> 16) & 0x1;
5377 rep_cnt = (param >> 32) & 0xfff;
5378 rep_idx = (param >> 48) & 0xfff;
5380 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5383 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5384 kvm_vcpu_on_spin(vcpu);
5387 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5391 ret = res | (((u64)rep_done & 0xfff) << 32);
5393 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5395 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5396 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5402 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5404 unsigned long nr, a0, a1, a2, a3, ret;
5407 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5408 return kvm_hv_hypercall(vcpu);
5410 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5411 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5412 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5413 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5414 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5416 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5418 if (!is_long_mode(vcpu)) {
5426 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5432 case KVM_HC_VAPIC_POLL_IRQ:
5440 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5441 ++vcpu->stat.hypercalls;
5444 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5446 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5448 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5449 char instruction[3];
5450 unsigned long rip = kvm_rip_read(vcpu);
5453 * Blow out the MMU to ensure that no other VCPU has an active mapping
5454 * to ensure that the updated hypercall appears atomically across all
5457 kvm_mmu_zap_all(vcpu->kvm);
5459 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5461 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5465 * Check if userspace requested an interrupt window, and that the
5466 * interrupt window is open.
5468 * No need to exit to userspace if we already have an interrupt queued.
5470 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5472 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5473 vcpu->run->request_interrupt_window &&
5474 kvm_arch_interrupt_allowed(vcpu));
5477 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5479 struct kvm_run *kvm_run = vcpu->run;
5481 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5482 kvm_run->cr8 = kvm_get_cr8(vcpu);
5483 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5484 if (irqchip_in_kernel(vcpu->kvm))
5485 kvm_run->ready_for_interrupt_injection = 1;
5487 kvm_run->ready_for_interrupt_injection =
5488 kvm_arch_interrupt_allowed(vcpu) &&
5489 !kvm_cpu_has_interrupt(vcpu) &&
5490 !kvm_event_needs_reinjection(vcpu);
5493 static int vapic_enter(struct kvm_vcpu *vcpu)
5495 struct kvm_lapic *apic = vcpu->arch.apic;
5498 if (!apic || !apic->vapic_addr)
5501 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5502 if (is_error_page(page))
5505 vcpu->arch.apic->vapic_page = page;
5509 static void vapic_exit(struct kvm_vcpu *vcpu)
5511 struct kvm_lapic *apic = vcpu->arch.apic;
5514 if (!apic || !apic->vapic_addr)
5517 idx = srcu_read_lock(&vcpu->kvm->srcu);
5518 kvm_release_page_dirty(apic->vapic_page);
5519 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5520 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5523 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5527 if (!kvm_x86_ops->update_cr8_intercept)
5530 if (!vcpu->arch.apic)
5533 if (!vcpu->arch.apic->vapic_addr)
5534 max_irr = kvm_lapic_find_highest_irr(vcpu);
5541 tpr = kvm_lapic_get_cr8(vcpu);
5543 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5546 static void inject_pending_event(struct kvm_vcpu *vcpu)
5548 /* try to reinject previous events if any */
5549 if (vcpu->arch.exception.pending) {
5550 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5551 vcpu->arch.exception.has_error_code,
5552 vcpu->arch.exception.error_code);
5553 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5554 vcpu->arch.exception.has_error_code,
5555 vcpu->arch.exception.error_code,
5556 vcpu->arch.exception.reinject);
5560 if (vcpu->arch.nmi_injected) {
5561 kvm_x86_ops->set_nmi(vcpu);
5565 if (vcpu->arch.interrupt.pending) {
5566 kvm_x86_ops->set_irq(vcpu);
5570 /* try to inject new event if pending */
5571 if (vcpu->arch.nmi_pending) {
5572 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5573 --vcpu->arch.nmi_pending;
5574 vcpu->arch.nmi_injected = true;
5575 kvm_x86_ops->set_nmi(vcpu);
5577 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5578 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5579 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5581 kvm_x86_ops->set_irq(vcpu);
5586 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5588 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5589 !vcpu->guest_xcr0_loaded) {
5590 /* kvm_set_xcr() also depends on this */
5591 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5592 vcpu->guest_xcr0_loaded = 1;
5596 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5598 if (vcpu->guest_xcr0_loaded) {
5599 if (vcpu->arch.xcr0 != host_xcr0)
5600 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5601 vcpu->guest_xcr0_loaded = 0;
5605 static void process_nmi(struct kvm_vcpu *vcpu)
5610 * x86 is limited to one NMI running, and one NMI pending after it.
5611 * If an NMI is already in progress, limit further NMIs to just one.
5612 * Otherwise, allow two (and we'll inject the first one immediately).
5614 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5617 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5618 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5619 kvm_make_request(KVM_REQ_EVENT, vcpu);
5622 static void kvm_gen_update_masterclock(struct kvm *kvm)
5624 #ifdef CONFIG_X86_64
5626 struct kvm_vcpu *vcpu;
5627 struct kvm_arch *ka = &kvm->arch;
5629 spin_lock(&ka->pvclock_gtod_sync_lock);
5630 kvm_make_mclock_inprogress_request(kvm);
5631 /* no guest entries from this point */
5632 pvclock_update_vm_gtod_copy(kvm);
5634 kvm_for_each_vcpu(i, vcpu, kvm)
5635 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5637 /* guest entries allowed */
5638 kvm_for_each_vcpu(i, vcpu, kvm)
5639 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5641 spin_unlock(&ka->pvclock_gtod_sync_lock);
5645 static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
5647 u64 eoi_exit_bitmap[4];
5649 memset(eoi_exit_bitmap, 0, 32);
5651 kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
5652 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5655 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5658 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5659 vcpu->run->request_interrupt_window;
5660 bool req_immediate_exit = 0;
5662 if (vcpu->requests) {
5663 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5664 kvm_mmu_unload(vcpu);
5665 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5666 __kvm_migrate_timers(vcpu);
5667 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5668 kvm_gen_update_masterclock(vcpu->kvm);
5669 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5670 r = kvm_guest_time_update(vcpu);
5674 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5675 kvm_mmu_sync_roots(vcpu);
5676 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5677 kvm_x86_ops->tlb_flush(vcpu);
5678 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5679 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5683 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5684 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5688 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5689 vcpu->fpu_active = 0;
5690 kvm_x86_ops->fpu_deactivate(vcpu);
5692 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5693 /* Page is swapped out. Do synthetic halt */
5694 vcpu->arch.apf.halted = true;
5698 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5699 record_steal_time(vcpu);
5700 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5702 req_immediate_exit =
5703 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5704 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5705 kvm_handle_pmu_event(vcpu);
5706 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5707 kvm_deliver_pmi(vcpu);
5708 if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
5709 update_eoi_exitmap(vcpu);
5712 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5713 inject_pending_event(vcpu);
5715 /* enable NMI/IRQ window open exits if needed */
5716 if (vcpu->arch.nmi_pending)
5717 kvm_x86_ops->enable_nmi_window(vcpu);
5718 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5719 kvm_x86_ops->enable_irq_window(vcpu);
5721 if (kvm_lapic_enabled(vcpu)) {
5723 * Update architecture specific hints for APIC
5724 * virtual interrupt delivery.
5726 if (kvm_x86_ops->hwapic_irr_update)
5727 kvm_x86_ops->hwapic_irr_update(vcpu,
5728 kvm_lapic_find_highest_irr(vcpu));
5729 update_cr8_intercept(vcpu);
5730 kvm_lapic_sync_to_vapic(vcpu);
5734 r = kvm_mmu_reload(vcpu);
5736 goto cancel_injection;
5741 kvm_x86_ops->prepare_guest_switch(vcpu);
5742 if (vcpu->fpu_active)
5743 kvm_load_guest_fpu(vcpu);
5744 kvm_load_guest_xcr0(vcpu);
5746 vcpu->mode = IN_GUEST_MODE;
5748 /* We should set ->mode before check ->requests,
5749 * see the comment in make_all_cpus_request.
5753 local_irq_disable();
5755 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5756 || need_resched() || signal_pending(current)) {
5757 vcpu->mode = OUTSIDE_GUEST_MODE;
5762 goto cancel_injection;
5765 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5767 if (req_immediate_exit)
5768 smp_send_reschedule(vcpu->cpu);
5772 if (unlikely(vcpu->arch.switch_db_regs)) {
5774 set_debugreg(vcpu->arch.eff_db[0], 0);
5775 set_debugreg(vcpu->arch.eff_db[1], 1);
5776 set_debugreg(vcpu->arch.eff_db[2], 2);
5777 set_debugreg(vcpu->arch.eff_db[3], 3);
5780 trace_kvm_entry(vcpu->vcpu_id);
5781 kvm_x86_ops->run(vcpu);
5784 * If the guest has used debug registers, at least dr7
5785 * will be disabled while returning to the host.
5786 * If we don't have active breakpoints in the host, we don't
5787 * care about the messed up debug address registers. But if
5788 * we have some of them active, restore the old state.
5790 if (hw_breakpoint_active())
5791 hw_breakpoint_restore();
5793 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5796 vcpu->mode = OUTSIDE_GUEST_MODE;
5803 * We must have an instruction between local_irq_enable() and
5804 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5805 * the interrupt shadow. The stat.exits increment will do nicely.
5806 * But we need to prevent reordering, hence this barrier():
5814 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5817 * Profile KVM exit RIPs:
5819 if (unlikely(prof_on == KVM_PROFILING)) {
5820 unsigned long rip = kvm_rip_read(vcpu);
5821 profile_hit(KVM_PROFILING, (void *)rip);
5824 if (unlikely(vcpu->arch.tsc_always_catchup))
5825 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5827 if (vcpu->arch.apic_attention)
5828 kvm_lapic_sync_from_vapic(vcpu);
5830 r = kvm_x86_ops->handle_exit(vcpu);
5834 kvm_x86_ops->cancel_injection(vcpu);
5835 if (unlikely(vcpu->arch.apic_attention))
5836 kvm_lapic_sync_from_vapic(vcpu);
5842 static int __vcpu_run(struct kvm_vcpu *vcpu)
5845 struct kvm *kvm = vcpu->kvm;
5847 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5848 pr_debug("vcpu %d received sipi with vector # %x\n",
5849 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5850 kvm_lapic_reset(vcpu);
5851 r = kvm_vcpu_reset(vcpu);
5854 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5857 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5858 r = vapic_enter(vcpu);
5860 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5866 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5867 !vcpu->arch.apf.halted)
5868 r = vcpu_enter_guest(vcpu);
5870 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5871 kvm_vcpu_block(vcpu);
5872 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5873 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5875 switch(vcpu->arch.mp_state) {
5876 case KVM_MP_STATE_HALTED:
5877 vcpu->arch.mp_state =
5878 KVM_MP_STATE_RUNNABLE;
5879 case KVM_MP_STATE_RUNNABLE:
5880 vcpu->arch.apf.halted = false;
5882 case KVM_MP_STATE_SIPI_RECEIVED:
5893 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5894 if (kvm_cpu_has_pending_timer(vcpu))
5895 kvm_inject_pending_timer_irqs(vcpu);
5897 if (dm_request_for_irq_injection(vcpu)) {
5899 vcpu->run->exit_reason = KVM_EXIT_INTR;
5900 ++vcpu->stat.request_irq_exits;
5903 kvm_check_async_pf_completion(vcpu);
5905 if (signal_pending(current)) {
5907 vcpu->run->exit_reason = KVM_EXIT_INTR;
5908 ++vcpu->stat.signal_exits;
5910 if (need_resched()) {
5911 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5913 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5917 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5924 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5927 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5928 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5929 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5930 if (r != EMULATE_DONE)
5935 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5937 BUG_ON(!vcpu->arch.pio.count);
5939 return complete_emulated_io(vcpu);
5943 * Implements the following, as a state machine:
5947 * for each mmio piece in the fragment
5955 * for each mmio piece in the fragment
5960 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5962 struct kvm_run *run = vcpu->run;
5963 struct kvm_mmio_fragment *frag;
5966 BUG_ON(!vcpu->mmio_needed);
5968 /* Complete previous fragment */
5969 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5970 len = min(8u, frag->len);
5971 if (!vcpu->mmio_is_write)
5972 memcpy(frag->data, run->mmio.data, len);
5974 if (frag->len <= 8) {
5975 /* Switch to the next fragment. */
5977 vcpu->mmio_cur_fragment++;
5979 /* Go forward to the next mmio piece. */
5985 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5986 vcpu->mmio_needed = 0;
5987 if (vcpu->mmio_is_write)
5989 vcpu->mmio_read_completed = 1;
5990 return complete_emulated_io(vcpu);
5993 run->exit_reason = KVM_EXIT_MMIO;
5994 run->mmio.phys_addr = frag->gpa;
5995 if (vcpu->mmio_is_write)
5996 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
5997 run->mmio.len = min(8u, frag->len);
5998 run->mmio.is_write = vcpu->mmio_is_write;
5999 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6004 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6009 if (!tsk_used_math(current) && init_fpu(current))
6012 if (vcpu->sigset_active)
6013 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6015 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6016 kvm_vcpu_block(vcpu);
6017 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6022 /* re-sync apic's tpr */
6023 if (!irqchip_in_kernel(vcpu->kvm)) {
6024 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6030 if (unlikely(vcpu->arch.complete_userspace_io)) {
6031 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6032 vcpu->arch.complete_userspace_io = NULL;
6037 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6039 r = __vcpu_run(vcpu);
6042 post_kvm_run_save(vcpu);
6043 if (vcpu->sigset_active)
6044 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6049 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6051 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6053 * We are here if userspace calls get_regs() in the middle of
6054 * instruction emulation. Registers state needs to be copied
6055 * back from emulation context to vcpu. Userspace shouldn't do
6056 * that usually, but some bad designed PV devices (vmware
6057 * backdoor interface) need this to work
6059 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6060 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6062 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6063 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6064 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6065 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6066 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6067 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6068 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6069 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6070 #ifdef CONFIG_X86_64
6071 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6072 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6073 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6074 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6075 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6076 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6077 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6078 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6081 regs->rip = kvm_rip_read(vcpu);
6082 regs->rflags = kvm_get_rflags(vcpu);
6087 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6089 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6090 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6092 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6093 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6094 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6095 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6096 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6097 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6098 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6099 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6100 #ifdef CONFIG_X86_64
6101 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6102 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6103 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6104 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6105 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6106 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6107 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6108 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6111 kvm_rip_write(vcpu, regs->rip);
6112 kvm_set_rflags(vcpu, regs->rflags);
6114 vcpu->arch.exception.pending = false;
6116 kvm_make_request(KVM_REQ_EVENT, vcpu);
6121 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6123 struct kvm_segment cs;
6125 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6129 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6131 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6132 struct kvm_sregs *sregs)
6136 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6137 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6138 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6139 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6140 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6141 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6143 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6144 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6146 kvm_x86_ops->get_idt(vcpu, &dt);
6147 sregs->idt.limit = dt.size;
6148 sregs->idt.base = dt.address;
6149 kvm_x86_ops->get_gdt(vcpu, &dt);
6150 sregs->gdt.limit = dt.size;
6151 sregs->gdt.base = dt.address;
6153 sregs->cr0 = kvm_read_cr0(vcpu);
6154 sregs->cr2 = vcpu->arch.cr2;
6155 sregs->cr3 = kvm_read_cr3(vcpu);
6156 sregs->cr4 = kvm_read_cr4(vcpu);
6157 sregs->cr8 = kvm_get_cr8(vcpu);
6158 sregs->efer = vcpu->arch.efer;
6159 sregs->apic_base = kvm_get_apic_base(vcpu);
6161 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6163 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6164 set_bit(vcpu->arch.interrupt.nr,
6165 (unsigned long *)sregs->interrupt_bitmap);
6170 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6171 struct kvm_mp_state *mp_state)
6173 mp_state->mp_state = vcpu->arch.mp_state;
6177 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6178 struct kvm_mp_state *mp_state)
6180 vcpu->arch.mp_state = mp_state->mp_state;
6181 kvm_make_request(KVM_REQ_EVENT, vcpu);
6185 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6186 int reason, bool has_error_code, u32 error_code)
6188 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6191 init_emulate_ctxt(vcpu);
6193 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6194 has_error_code, error_code);
6197 return EMULATE_FAIL;
6199 kvm_rip_write(vcpu, ctxt->eip);
6200 kvm_set_rflags(vcpu, ctxt->eflags);
6201 kvm_make_request(KVM_REQ_EVENT, vcpu);
6202 return EMULATE_DONE;
6204 EXPORT_SYMBOL_GPL(kvm_task_switch);
6206 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6207 struct kvm_sregs *sregs)
6209 int mmu_reset_needed = 0;
6210 int pending_vec, max_bits, idx;
6213 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6216 dt.size = sregs->idt.limit;
6217 dt.address = sregs->idt.base;
6218 kvm_x86_ops->set_idt(vcpu, &dt);
6219 dt.size = sregs->gdt.limit;
6220 dt.address = sregs->gdt.base;
6221 kvm_x86_ops->set_gdt(vcpu, &dt);
6223 vcpu->arch.cr2 = sregs->cr2;
6224 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6225 vcpu->arch.cr3 = sregs->cr3;
6226 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6228 kvm_set_cr8(vcpu, sregs->cr8);
6230 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6231 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6232 kvm_set_apic_base(vcpu, sregs->apic_base);
6234 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6235 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6236 vcpu->arch.cr0 = sregs->cr0;
6238 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6239 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6240 if (sregs->cr4 & X86_CR4_OSXSAVE)
6241 kvm_update_cpuid(vcpu);
6243 idx = srcu_read_lock(&vcpu->kvm->srcu);
6244 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6245 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6246 mmu_reset_needed = 1;
6248 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6250 if (mmu_reset_needed)
6251 kvm_mmu_reset_context(vcpu);
6253 max_bits = KVM_NR_INTERRUPTS;
6254 pending_vec = find_first_bit(
6255 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6256 if (pending_vec < max_bits) {
6257 kvm_queue_interrupt(vcpu, pending_vec, false);
6258 pr_debug("Set back pending irq %d\n", pending_vec);
6261 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6262 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6263 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6264 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6265 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6266 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6268 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6269 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6271 update_cr8_intercept(vcpu);
6273 /* Older userspace won't unhalt the vcpu on reset. */
6274 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6275 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6277 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6279 kvm_make_request(KVM_REQ_EVENT, vcpu);
6284 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6285 struct kvm_guest_debug *dbg)
6287 unsigned long rflags;
6290 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6292 if (vcpu->arch.exception.pending)
6294 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6295 kvm_queue_exception(vcpu, DB_VECTOR);
6297 kvm_queue_exception(vcpu, BP_VECTOR);
6301 * Read rflags as long as potentially injected trace flags are still
6304 rflags = kvm_get_rflags(vcpu);
6306 vcpu->guest_debug = dbg->control;
6307 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6308 vcpu->guest_debug = 0;
6310 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6311 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6312 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6313 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6315 for (i = 0; i < KVM_NR_DB_REGS; i++)
6316 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6318 kvm_update_dr7(vcpu);
6320 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6321 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6322 get_segment_base(vcpu, VCPU_SREG_CS);
6325 * Trigger an rflags update that will inject or remove the trace
6328 kvm_set_rflags(vcpu, rflags);
6330 kvm_x86_ops->update_db_bp_intercept(vcpu);
6340 * Translate a guest virtual address to a guest physical address.
6342 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6343 struct kvm_translation *tr)
6345 unsigned long vaddr = tr->linear_address;
6349 idx = srcu_read_lock(&vcpu->kvm->srcu);
6350 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6351 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6352 tr->physical_address = gpa;
6353 tr->valid = gpa != UNMAPPED_GVA;
6360 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6362 struct i387_fxsave_struct *fxsave =
6363 &vcpu->arch.guest_fpu.state->fxsave;
6365 memcpy(fpu->fpr, fxsave->st_space, 128);
6366 fpu->fcw = fxsave->cwd;
6367 fpu->fsw = fxsave->swd;
6368 fpu->ftwx = fxsave->twd;
6369 fpu->last_opcode = fxsave->fop;
6370 fpu->last_ip = fxsave->rip;
6371 fpu->last_dp = fxsave->rdp;
6372 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6377 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6379 struct i387_fxsave_struct *fxsave =
6380 &vcpu->arch.guest_fpu.state->fxsave;
6382 memcpy(fxsave->st_space, fpu->fpr, 128);
6383 fxsave->cwd = fpu->fcw;
6384 fxsave->swd = fpu->fsw;
6385 fxsave->twd = fpu->ftwx;
6386 fxsave->fop = fpu->last_opcode;
6387 fxsave->rip = fpu->last_ip;
6388 fxsave->rdp = fpu->last_dp;
6389 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6394 int fx_init(struct kvm_vcpu *vcpu)
6398 err = fpu_alloc(&vcpu->arch.guest_fpu);
6402 fpu_finit(&vcpu->arch.guest_fpu);
6405 * Ensure guest xcr0 is valid for loading
6407 vcpu->arch.xcr0 = XSTATE_FP;
6409 vcpu->arch.cr0 |= X86_CR0_ET;
6413 EXPORT_SYMBOL_GPL(fx_init);
6415 static void fx_free(struct kvm_vcpu *vcpu)
6417 fpu_free(&vcpu->arch.guest_fpu);
6420 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6422 if (vcpu->guest_fpu_loaded)
6426 * Restore all possible states in the guest,
6427 * and assume host would use all available bits.
6428 * Guest xcr0 would be loaded later.
6430 kvm_put_guest_xcr0(vcpu);
6431 vcpu->guest_fpu_loaded = 1;
6432 __kernel_fpu_begin();
6433 fpu_restore_checking(&vcpu->arch.guest_fpu);
6437 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6439 kvm_put_guest_xcr0(vcpu);
6441 if (!vcpu->guest_fpu_loaded)
6444 vcpu->guest_fpu_loaded = 0;
6445 fpu_save_init(&vcpu->arch.guest_fpu);
6447 ++vcpu->stat.fpu_reload;
6448 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6452 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6454 kvmclock_reset(vcpu);
6456 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6458 kvm_x86_ops->vcpu_free(vcpu);
6461 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6464 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6465 printk_once(KERN_WARNING
6466 "kvm: SMP vm created on host with unstable TSC; "
6467 "guest TSC will not be reliable\n");
6468 return kvm_x86_ops->vcpu_create(kvm, id);
6471 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6475 vcpu->arch.mtrr_state.have_fixed = 1;
6476 r = vcpu_load(vcpu);
6479 r = kvm_vcpu_reset(vcpu);
6481 r = kvm_mmu_setup(vcpu);
6487 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6490 struct msr_data msr;
6492 r = vcpu_load(vcpu);
6496 msr.index = MSR_IA32_TSC;
6497 msr.host_initiated = true;
6498 kvm_write_tsc(vcpu, &msr);
6504 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6507 vcpu->arch.apf.msr_val = 0;
6509 r = vcpu_load(vcpu);
6511 kvm_mmu_unload(vcpu);
6515 kvm_x86_ops->vcpu_free(vcpu);
6518 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6520 atomic_set(&vcpu->arch.nmi_queued, 0);
6521 vcpu->arch.nmi_pending = 0;
6522 vcpu->arch.nmi_injected = false;
6524 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6525 vcpu->arch.dr6 = DR6_FIXED_1;
6526 vcpu->arch.dr7 = DR7_FIXED_1;
6527 kvm_update_dr7(vcpu);
6529 kvm_make_request(KVM_REQ_EVENT, vcpu);
6530 vcpu->arch.apf.msr_val = 0;
6531 vcpu->arch.st.msr_val = 0;
6533 kvmclock_reset(vcpu);
6535 kvm_clear_async_pf_completion_queue(vcpu);
6536 kvm_async_pf_hash_reset(vcpu);
6537 vcpu->arch.apf.halted = false;
6539 kvm_pmu_reset(vcpu);
6541 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6542 vcpu->arch.regs_avail = ~0;
6543 vcpu->arch.regs_dirty = ~0;
6545 return kvm_x86_ops->vcpu_reset(vcpu);
6548 int kvm_arch_hardware_enable(void *garbage)
6551 struct kvm_vcpu *vcpu;
6556 bool stable, backwards_tsc = false;
6558 kvm_shared_msr_cpu_online();
6559 ret = kvm_x86_ops->hardware_enable(garbage);
6563 local_tsc = native_read_tsc();
6564 stable = !check_tsc_unstable();
6565 list_for_each_entry(kvm, &vm_list, vm_list) {
6566 kvm_for_each_vcpu(i, vcpu, kvm) {
6567 if (!stable && vcpu->cpu == smp_processor_id())
6568 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6569 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6570 backwards_tsc = true;
6571 if (vcpu->arch.last_host_tsc > max_tsc)
6572 max_tsc = vcpu->arch.last_host_tsc;
6578 * Sometimes, even reliable TSCs go backwards. This happens on
6579 * platforms that reset TSC during suspend or hibernate actions, but
6580 * maintain synchronization. We must compensate. Fortunately, we can
6581 * detect that condition here, which happens early in CPU bringup,
6582 * before any KVM threads can be running. Unfortunately, we can't
6583 * bring the TSCs fully up to date with real time, as we aren't yet far
6584 * enough into CPU bringup that we know how much real time has actually
6585 * elapsed; our helper function, get_kernel_ns() will be using boot
6586 * variables that haven't been updated yet.
6588 * So we simply find the maximum observed TSC above, then record the
6589 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6590 * the adjustment will be applied. Note that we accumulate
6591 * adjustments, in case multiple suspend cycles happen before some VCPU
6592 * gets a chance to run again. In the event that no KVM threads get a
6593 * chance to run, we will miss the entire elapsed period, as we'll have
6594 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6595 * loose cycle time. This isn't too big a deal, since the loss will be
6596 * uniform across all VCPUs (not to mention the scenario is extremely
6597 * unlikely). It is possible that a second hibernate recovery happens
6598 * much faster than a first, causing the observed TSC here to be
6599 * smaller; this would require additional padding adjustment, which is
6600 * why we set last_host_tsc to the local tsc observed here.
6602 * N.B. - this code below runs only on platforms with reliable TSC,
6603 * as that is the only way backwards_tsc is set above. Also note
6604 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6605 * have the same delta_cyc adjustment applied if backwards_tsc
6606 * is detected. Note further, this adjustment is only done once,
6607 * as we reset last_host_tsc on all VCPUs to stop this from being
6608 * called multiple times (one for each physical CPU bringup).
6610 * Platforms with unreliable TSCs don't have to deal with this, they
6611 * will be compensated by the logic in vcpu_load, which sets the TSC to
6612 * catchup mode. This will catchup all VCPUs to real time, but cannot
6613 * guarantee that they stay in perfect synchronization.
6615 if (backwards_tsc) {
6616 u64 delta_cyc = max_tsc - local_tsc;
6617 list_for_each_entry(kvm, &vm_list, vm_list) {
6618 kvm_for_each_vcpu(i, vcpu, kvm) {
6619 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6620 vcpu->arch.last_host_tsc = local_tsc;
6621 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6626 * We have to disable TSC offset matching.. if you were
6627 * booting a VM while issuing an S4 host suspend....
6628 * you may have some problem. Solving this issue is
6629 * left as an exercise to the reader.
6631 kvm->arch.last_tsc_nsec = 0;
6632 kvm->arch.last_tsc_write = 0;
6639 void kvm_arch_hardware_disable(void *garbage)
6641 kvm_x86_ops->hardware_disable(garbage);
6642 drop_user_return_notifiers(garbage);
6645 int kvm_arch_hardware_setup(void)
6647 return kvm_x86_ops->hardware_setup();
6650 void kvm_arch_hardware_unsetup(void)
6652 kvm_x86_ops->hardware_unsetup();
6655 void kvm_arch_check_processor_compat(void *rtn)
6657 kvm_x86_ops->check_processor_compatibility(rtn);
6660 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6662 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6665 struct static_key kvm_no_apic_vcpu __read_mostly;
6667 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6673 BUG_ON(vcpu->kvm == NULL);
6676 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6677 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6678 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6680 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6682 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6687 vcpu->arch.pio_data = page_address(page);
6689 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6691 r = kvm_mmu_create(vcpu);
6693 goto fail_free_pio_data;
6695 if (irqchip_in_kernel(kvm)) {
6696 r = kvm_create_lapic(vcpu);
6698 goto fail_mmu_destroy;
6700 static_key_slow_inc(&kvm_no_apic_vcpu);
6702 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6704 if (!vcpu->arch.mce_banks) {
6706 goto fail_free_lapic;
6708 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6710 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6711 goto fail_free_mce_banks;
6715 goto fail_free_wbinvd_dirty_mask;
6717 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6718 vcpu->arch.pv_time_enabled = false;
6719 kvm_async_pf_hash_reset(vcpu);
6723 fail_free_wbinvd_dirty_mask:
6724 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6725 fail_free_mce_banks:
6726 kfree(vcpu->arch.mce_banks);
6728 kvm_free_lapic(vcpu);
6730 kvm_mmu_destroy(vcpu);
6732 free_page((unsigned long)vcpu->arch.pio_data);
6737 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6741 kvm_pmu_destroy(vcpu);
6742 kfree(vcpu->arch.mce_banks);
6743 kvm_free_lapic(vcpu);
6744 idx = srcu_read_lock(&vcpu->kvm->srcu);
6745 kvm_mmu_destroy(vcpu);
6746 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6747 free_page((unsigned long)vcpu->arch.pio_data);
6748 if (!irqchip_in_kernel(vcpu->kvm))
6749 static_key_slow_dec(&kvm_no_apic_vcpu);
6752 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6757 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6758 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6760 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6761 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6762 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6763 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6764 &kvm->arch.irq_sources_bitmap);
6766 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6767 mutex_init(&kvm->arch.apic_map_lock);
6768 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6770 pvclock_update_vm_gtod_copy(kvm);
6775 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6778 r = vcpu_load(vcpu);
6780 kvm_mmu_unload(vcpu);
6784 static void kvm_free_vcpus(struct kvm *kvm)
6787 struct kvm_vcpu *vcpu;
6790 * Unpin any mmu pages first.
6792 kvm_for_each_vcpu(i, vcpu, kvm) {
6793 kvm_clear_async_pf_completion_queue(vcpu);
6794 kvm_unload_vcpu_mmu(vcpu);
6796 kvm_for_each_vcpu(i, vcpu, kvm)
6797 kvm_arch_vcpu_free(vcpu);
6799 mutex_lock(&kvm->lock);
6800 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6801 kvm->vcpus[i] = NULL;
6803 atomic_set(&kvm->online_vcpus, 0);
6804 mutex_unlock(&kvm->lock);
6807 void kvm_arch_sync_events(struct kvm *kvm)
6809 kvm_free_all_assigned_devices(kvm);
6813 void kvm_arch_destroy_vm(struct kvm *kvm)
6815 kvm_iommu_unmap_guest(kvm);
6816 kfree(kvm->arch.vpic);
6817 kfree(kvm->arch.vioapic);
6818 kvm_free_vcpus(kvm);
6819 if (kvm->arch.apic_access_page)
6820 put_page(kvm->arch.apic_access_page);
6821 if (kvm->arch.ept_identity_pagetable)
6822 put_page(kvm->arch.ept_identity_pagetable);
6823 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6826 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6827 struct kvm_memory_slot *dont)
6831 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6832 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6833 kvm_kvfree(free->arch.rmap[i]);
6834 free->arch.rmap[i] = NULL;
6839 if (!dont || free->arch.lpage_info[i - 1] !=
6840 dont->arch.lpage_info[i - 1]) {
6841 kvm_kvfree(free->arch.lpage_info[i - 1]);
6842 free->arch.lpage_info[i - 1] = NULL;
6847 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6851 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6856 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6857 slot->base_gfn, level) + 1;
6859 slot->arch.rmap[i] =
6860 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6861 if (!slot->arch.rmap[i])
6866 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6867 sizeof(*slot->arch.lpage_info[i - 1]));
6868 if (!slot->arch.lpage_info[i - 1])
6871 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6872 slot->arch.lpage_info[i - 1][0].write_count = 1;
6873 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6874 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6875 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6877 * If the gfn and userspace address are not aligned wrt each
6878 * other, or if explicitly asked to, disable large page
6879 * support for this slot
6881 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6882 !kvm_largepages_enabled()) {
6885 for (j = 0; j < lpages; ++j)
6886 slot->arch.lpage_info[i - 1][j].write_count = 1;
6893 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6894 kvm_kvfree(slot->arch.rmap[i]);
6895 slot->arch.rmap[i] = NULL;
6899 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6900 slot->arch.lpage_info[i - 1] = NULL;
6905 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6906 struct kvm_memory_slot *memslot,
6907 struct kvm_memory_slot old,
6908 struct kvm_userspace_memory_region *mem,
6911 int npages = memslot->npages;
6914 * Only private memory slots need to be mapped here since
6915 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
6917 if ((memslot->id >= KVM_USER_MEM_SLOTS) && npages && !old.npages) {
6918 unsigned long userspace_addr;
6921 * MAP_SHARED to prevent internal slot pages from being moved
6924 userspace_addr = vm_mmap(NULL, 0, npages * PAGE_SIZE,
6925 PROT_READ | PROT_WRITE,
6926 MAP_SHARED | MAP_ANONYMOUS, 0);
6928 if (IS_ERR((void *)userspace_addr))
6929 return PTR_ERR((void *)userspace_addr);
6931 memslot->userspace_addr = userspace_addr;
6937 void kvm_arch_commit_memory_region(struct kvm *kvm,
6938 struct kvm_userspace_memory_region *mem,
6939 struct kvm_memory_slot old,
6943 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6945 if ((mem->slot >= KVM_USER_MEM_SLOTS) && old.npages && !npages) {
6948 ret = vm_munmap(old.userspace_addr,
6949 old.npages * PAGE_SIZE);
6952 "kvm_vm_ioctl_set_memory_region: "
6953 "failed to munmap memory\n");
6956 if (!kvm->arch.n_requested_mmu_pages)
6957 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6960 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6962 * Write protect all pages for dirty logging.
6963 * Existing largepage mappings are destroyed here and new ones will
6964 * not be created until the end of the logging.
6966 if (npages && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
6967 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6969 * If memory slot is created, or moved, we need to clear all
6972 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6973 kvm_mmu_zap_all(kvm);
6974 kvm_reload_remote_mmus(kvm);
6978 void kvm_arch_flush_shadow_all(struct kvm *kvm)
6980 kvm_mmu_zap_all(kvm);
6981 kvm_reload_remote_mmus(kvm);
6984 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6985 struct kvm_memory_slot *slot)
6987 kvm_arch_flush_shadow_all(kvm);
6990 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6992 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6993 !vcpu->arch.apf.halted)
6994 || !list_empty_careful(&vcpu->async_pf.done)
6995 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6996 || atomic_read(&vcpu->arch.nmi_queued) ||
6997 (kvm_arch_interrupt_allowed(vcpu) &&
6998 kvm_cpu_has_interrupt(vcpu));
7001 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7003 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7006 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7008 return kvm_x86_ops->interrupt_allowed(vcpu);
7011 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7013 unsigned long current_rip = kvm_rip_read(vcpu) +
7014 get_segment_base(vcpu, VCPU_SREG_CS);
7016 return current_rip == linear_rip;
7018 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7020 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7022 unsigned long rflags;
7024 rflags = kvm_x86_ops->get_rflags(vcpu);
7025 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7026 rflags &= ~X86_EFLAGS_TF;
7029 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7031 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7033 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7034 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7035 rflags |= X86_EFLAGS_TF;
7036 kvm_x86_ops->set_rflags(vcpu, rflags);
7037 kvm_make_request(KVM_REQ_EVENT, vcpu);
7039 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7041 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7045 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7046 is_error_page(work->page))
7049 r = kvm_mmu_reload(vcpu);
7053 if (!vcpu->arch.mmu.direct_map &&
7054 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7057 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7060 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7062 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7065 static inline u32 kvm_async_pf_next_probe(u32 key)
7067 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7070 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7072 u32 key = kvm_async_pf_hash_fn(gfn);
7074 while (vcpu->arch.apf.gfns[key] != ~0)
7075 key = kvm_async_pf_next_probe(key);
7077 vcpu->arch.apf.gfns[key] = gfn;
7080 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7083 u32 key = kvm_async_pf_hash_fn(gfn);
7085 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7086 (vcpu->arch.apf.gfns[key] != gfn &&
7087 vcpu->arch.apf.gfns[key] != ~0); i++)
7088 key = kvm_async_pf_next_probe(key);
7093 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7095 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7098 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7102 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7104 vcpu->arch.apf.gfns[i] = ~0;
7106 j = kvm_async_pf_next_probe(j);
7107 if (vcpu->arch.apf.gfns[j] == ~0)
7109 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7111 * k lies cyclically in ]i,j]
7113 * |....j i.k.| or |.k..j i...|
7115 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7116 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7121 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7124 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7128 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7129 struct kvm_async_pf *work)
7131 struct x86_exception fault;
7133 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7134 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7136 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7137 (vcpu->arch.apf.send_user_only &&
7138 kvm_x86_ops->get_cpl(vcpu) == 0))
7139 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7140 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7141 fault.vector = PF_VECTOR;
7142 fault.error_code_valid = true;
7143 fault.error_code = 0;
7144 fault.nested_page_fault = false;
7145 fault.address = work->arch.token;
7146 kvm_inject_page_fault(vcpu, &fault);
7150 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7151 struct kvm_async_pf *work)
7153 struct x86_exception fault;
7155 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7156 if (is_error_page(work->page))
7157 work->arch.token = ~0; /* broadcast wakeup */
7159 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7161 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7162 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7163 fault.vector = PF_VECTOR;
7164 fault.error_code_valid = true;
7165 fault.error_code = 0;
7166 fault.nested_page_fault = false;
7167 fault.address = work->arch.token;
7168 kvm_inject_page_fault(vcpu, &fault);
7170 vcpu->arch.apf.halted = false;
7171 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7174 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7176 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7179 return !kvm_event_needs_reinjection(vcpu) &&
7180 kvm_x86_ops->interrupt_allowed(vcpu);
7183 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7184 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7185 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7186 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7187 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7188 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7189 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7190 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7191 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7192 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7193 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7194 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);