2 * x86 instruction analysis
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (C) IBM Corporation, 2002, 2004, 2009
22 #include <linux/string.h>
29 /* Verify next sizeof(t) bytes can be on the same instruction */
30 #define validate_next(t, insn, n) \
31 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
33 #define __get_next(t, insn) \
34 ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; })
36 #define __peek_nbyte_next(t, insn, n) \
37 ({ t r = *(t*)((insn)->next_byte + n); r; })
39 #define get_next(t, insn) \
40 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
42 #define peek_nbyte_next(t, insn, n) \
43 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
45 #define peek_next(t, insn) peek_nbyte_next(t, insn, 0)
48 * insn_init() - initialize struct insn
49 * @insn: &struct insn to be initialized
50 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
51 * @x86_64: !0 for 64-bit kernel or 64-bit app
53 void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64)
55 memset(insn, 0, sizeof(*insn));
57 insn->end_kaddr = kaddr + buf_len;
58 insn->next_byte = kaddr;
59 insn->x86_64 = x86_64 ? 1 : 0;
68 * insn_get_prefixes - scan x86 instruction prefix bytes
69 * @insn: &struct insn containing instruction
71 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
72 * to point to the (first) opcode. No effect if @insn->prefixes.got
75 void insn_get_prefixes(struct insn *insn)
77 struct insn_field *prefixes = &insn->prefixes;
87 b = peek_next(insn_byte_t, insn);
88 attr = inat_get_opcode_attribute(b);
89 while (inat_is_legacy_prefix(attr)) {
90 /* Skip if same prefix */
91 for (i = 0; i < nb; i++)
92 if (prefixes->bytes[i] == b)
95 /* Invalid instruction */
97 prefixes->bytes[nb++] = b;
98 if (inat_is_address_size_prefix(attr)) {
99 /* address size switches 2/4 or 4/8 */
101 insn->addr_bytes ^= 12;
103 insn->addr_bytes ^= 6;
104 } else if (inat_is_operand_size_prefix(attr)) {
105 /* oprand size switches 2/4 */
106 insn->opnd_bytes ^= 6;
112 b = peek_next(insn_byte_t, insn);
113 attr = inat_get_opcode_attribute(b);
115 /* Set the last prefix */
116 if (lb && lb != insn->prefixes.bytes[3]) {
117 if (unlikely(insn->prefixes.bytes[3])) {
118 /* Swap the last prefix */
119 b = insn->prefixes.bytes[3];
120 for (i = 0; i < nb; i++)
121 if (prefixes->bytes[i] == lb)
122 prefixes->bytes[i] = b;
124 insn->prefixes.bytes[3] = lb;
127 /* Decode REX prefix */
129 b = peek_next(insn_byte_t, insn);
130 attr = inat_get_opcode_attribute(b);
131 if (inat_is_rex_prefix(attr)) {
132 insn->rex_prefix.value = b;
133 insn->rex_prefix.nbytes = 1;
136 /* REX.W overrides opnd_size */
137 insn->opnd_bytes = 8;
140 insn->rex_prefix.got = 1;
142 /* Decode VEX prefix */
143 b = peek_next(insn_byte_t, insn);
144 attr = inat_get_opcode_attribute(b);
145 if (inat_is_vex_prefix(attr)) {
146 insn_byte_t b2 = peek_nbyte_next(insn_byte_t, insn, 1);
149 * In 32-bits mode, if the [7:6] bits (mod bits of
150 * ModRM) on the second byte are not 11b, it is
153 if (X86_MODRM_MOD(b2) != 3)
156 insn->vex_prefix.bytes[0] = b;
157 insn->vex_prefix.bytes[1] = b2;
158 if (inat_is_vex3_prefix(attr)) {
159 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
160 insn->vex_prefix.bytes[2] = b2;
161 insn->vex_prefix.nbytes = 3;
162 insn->next_byte += 3;
163 if (insn->x86_64 && X86_VEX_W(b2))
164 /* VEX.W overrides opnd_size */
165 insn->opnd_bytes = 8;
168 * For VEX2, fake VEX3-like byte#2.
169 * Makes it easier to decode vex.W, vex.vvvv,
170 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
172 insn->vex_prefix.bytes[2] = b2 & 0x7f;
173 insn->vex_prefix.nbytes = 2;
174 insn->next_byte += 2;
178 insn->vex_prefix.got = 1;
187 * insn_get_opcode - collect opcode(s)
188 * @insn: &struct insn containing instruction
190 * Populates @insn->opcode, updates @insn->next_byte to point past the
191 * opcode byte(s), and set @insn->attr (except for groups).
192 * If necessary, first collects any preceding (prefix) bytes.
193 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
196 void insn_get_opcode(struct insn *insn)
198 struct insn_field *opcode = &insn->opcode;
203 if (!insn->prefixes.got)
204 insn_get_prefixes(insn);
206 /* Get first opcode */
207 op = get_next(insn_byte_t, insn);
208 opcode->bytes[0] = op;
211 /* Check if there is VEX prefix or not */
212 if (insn_is_avx(insn)) {
214 m = insn_vex_m_bits(insn);
215 p = insn_vex_p_bits(insn);
216 insn->attr = inat_get_avx_attribute(op, m, p);
217 if (!inat_accept_vex(insn->attr) && !inat_is_group(insn->attr))
218 insn->attr = 0; /* This instruction is bad */
219 goto end; /* VEX has only 1 byte for opcode */
222 insn->attr = inat_get_opcode_attribute(op);
223 while (inat_is_escape(insn->attr)) {
224 /* Get escaped opcode */
225 op = get_next(insn_byte_t, insn);
226 opcode->bytes[opcode->nbytes++] = op;
227 pfx_id = insn_last_prefix_id(insn);
228 insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr);
230 if (inat_must_vex(insn->attr))
231 insn->attr = 0; /* This instruction is bad */
240 * insn_get_modrm - collect ModRM byte, if any
241 * @insn: &struct insn containing instruction
243 * Populates @insn->modrm and updates @insn->next_byte to point past the
244 * ModRM byte, if any. If necessary, first collects the preceding bytes
245 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
247 void insn_get_modrm(struct insn *insn)
249 struct insn_field *modrm = &insn->modrm;
250 insn_byte_t pfx_id, mod;
253 if (!insn->opcode.got)
254 insn_get_opcode(insn);
256 if (inat_has_modrm(insn->attr)) {
257 mod = get_next(insn_byte_t, insn);
260 if (inat_is_group(insn->attr)) {
261 pfx_id = insn_last_prefix_id(insn);
262 insn->attr = inat_get_group_attribute(mod, pfx_id,
264 if (insn_is_avx(insn) && !inat_accept_vex(insn->attr))
265 insn->attr = 0; /* This is bad */
269 if (insn->x86_64 && inat_is_force64(insn->attr))
270 insn->opnd_bytes = 8;
279 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
280 * @insn: &struct insn containing instruction
282 * If necessary, first collects the instruction up to and including the
283 * ModRM byte. No effect if @insn->x86_64 is 0.
285 int insn_rip_relative(struct insn *insn)
287 struct insn_field *modrm = &insn->modrm;
292 insn_get_modrm(insn);
294 * For rip-relative instructions, the mod field (top 2 bits)
295 * is zero and the r/m field (bottom 3 bits) is 0x5.
297 return (modrm->nbytes && (modrm->value & 0xc7) == 0x5);
301 * insn_get_sib() - Get the SIB byte of instruction
302 * @insn: &struct insn containing instruction
304 * If necessary, first collects the instruction up to and including the
307 void insn_get_sib(struct insn *insn)
313 if (!insn->modrm.got)
314 insn_get_modrm(insn);
315 if (insn->modrm.nbytes) {
316 modrm = (insn_byte_t)insn->modrm.value;
317 if (insn->addr_bytes != 2 &&
318 X86_MODRM_MOD(modrm) != 3 && X86_MODRM_RM(modrm) == 4) {
319 insn->sib.value = get_next(insn_byte_t, insn);
320 insn->sib.nbytes = 1;
331 * insn_get_displacement() - Get the displacement of instruction
332 * @insn: &struct insn containing instruction
334 * If necessary, first collects the instruction up to and including the
336 * Displacement value is sign-expanded.
338 void insn_get_displacement(struct insn *insn)
340 insn_byte_t mod, rm, base;
342 if (insn->displacement.got)
346 if (insn->modrm.nbytes) {
348 * Interpreting the modrm byte:
349 * mod = 00 - no displacement fields (exceptions below)
350 * mod = 01 - 1-byte displacement field
351 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
352 * address size = 2 (0x67 prefix in 32-bit mode)
353 * mod = 11 - no memory operand
355 * If address size = 2...
356 * mod = 00, r/m = 110 - displacement field is 2 bytes
358 * If address size != 2...
359 * mod != 11, r/m = 100 - SIB byte exists
360 * mod = 00, SIB base = 101 - displacement field is 4 bytes
361 * mod = 00, r/m = 101 - rip-relative addressing, displacement
364 mod = X86_MODRM_MOD(insn->modrm.value);
365 rm = X86_MODRM_RM(insn->modrm.value);
366 base = X86_SIB_BASE(insn->sib.value);
370 insn->displacement.value = get_next(char, insn);
371 insn->displacement.nbytes = 1;
372 } else if (insn->addr_bytes == 2) {
373 if ((mod == 0 && rm == 6) || mod == 2) {
374 insn->displacement.value =
375 get_next(short, insn);
376 insn->displacement.nbytes = 2;
379 if ((mod == 0 && rm == 5) || mod == 2 ||
380 (mod == 0 && base == 5)) {
381 insn->displacement.value = get_next(int, insn);
382 insn->displacement.nbytes = 4;
387 insn->displacement.got = 1;
393 /* Decode moffset16/32/64. Return 0 if failed */
394 static int __get_moffset(struct insn *insn)
396 switch (insn->addr_bytes) {
398 insn->moffset1.value = get_next(short, insn);
399 insn->moffset1.nbytes = 2;
402 insn->moffset1.value = get_next(int, insn);
403 insn->moffset1.nbytes = 4;
406 insn->moffset1.value = get_next(int, insn);
407 insn->moffset1.nbytes = 4;
408 insn->moffset2.value = get_next(int, insn);
409 insn->moffset2.nbytes = 4;
411 default: /* opnd_bytes must be modified manually */
414 insn->moffset1.got = insn->moffset2.got = 1;
422 /* Decode imm v32(Iz). Return 0 if failed */
423 static int __get_immv32(struct insn *insn)
425 switch (insn->opnd_bytes) {
427 insn->immediate.value = get_next(short, insn);
428 insn->immediate.nbytes = 2;
432 insn->immediate.value = get_next(int, insn);
433 insn->immediate.nbytes = 4;
435 default: /* opnd_bytes must be modified manually */
445 /* Decode imm v64(Iv/Ov), Return 0 if failed */
446 static int __get_immv(struct insn *insn)
448 switch (insn->opnd_bytes) {
450 insn->immediate1.value = get_next(short, insn);
451 insn->immediate1.nbytes = 2;
454 insn->immediate1.value = get_next(int, insn);
455 insn->immediate1.nbytes = 4;
458 insn->immediate1.value = get_next(int, insn);
459 insn->immediate1.nbytes = 4;
460 insn->immediate2.value = get_next(int, insn);
461 insn->immediate2.nbytes = 4;
463 default: /* opnd_bytes must be modified manually */
466 insn->immediate1.got = insn->immediate2.got = 1;
473 /* Decode ptr16:16/32(Ap) */
474 static int __get_immptr(struct insn *insn)
476 switch (insn->opnd_bytes) {
478 insn->immediate1.value = get_next(short, insn);
479 insn->immediate1.nbytes = 2;
482 insn->immediate1.value = get_next(int, insn);
483 insn->immediate1.nbytes = 4;
486 /* ptr16:64 is not exist (no segment) */
488 default: /* opnd_bytes must be modified manually */
491 insn->immediate2.value = get_next(unsigned short, insn);
492 insn->immediate2.nbytes = 2;
493 insn->immediate1.got = insn->immediate2.got = 1;
501 * insn_get_immediate() - Get the immediates of instruction
502 * @insn: &struct insn containing instruction
504 * If necessary, first collects the instruction up to and including the
505 * displacement bytes.
506 * Basically, most of immediates are sign-expanded. Unsigned-value can be
507 * get by bit masking with ((1 << (nbytes * 8)) - 1)
509 void insn_get_immediate(struct insn *insn)
511 if (insn->immediate.got)
513 if (!insn->displacement.got)
514 insn_get_displacement(insn);
516 if (inat_has_moffset(insn->attr)) {
517 if (!__get_moffset(insn))
522 if (!inat_has_immediate(insn->attr))
526 switch (inat_immediate_size(insn->attr)) {
528 insn->immediate.value = get_next(char, insn);
529 insn->immediate.nbytes = 1;
532 insn->immediate.value = get_next(short, insn);
533 insn->immediate.nbytes = 2;
536 insn->immediate.value = get_next(int, insn);
537 insn->immediate.nbytes = 4;
540 insn->immediate1.value = get_next(int, insn);
541 insn->immediate1.nbytes = 4;
542 insn->immediate2.value = get_next(int, insn);
543 insn->immediate2.nbytes = 4;
546 if (!__get_immptr(insn))
549 case INAT_IMM_VWORD32:
550 if (!__get_immv32(insn))
554 if (!__get_immv(insn))
558 /* Here, insn must have an immediate, but failed */
561 if (inat_has_second_immediate(insn->attr)) {
562 insn->immediate2.value = get_next(char, insn);
563 insn->immediate2.nbytes = 1;
566 insn->immediate.got = 1;
573 * insn_get_length() - Get the length of instruction
574 * @insn: &struct insn containing instruction
576 * If necessary, first collects the instruction up to and including the
579 void insn_get_length(struct insn *insn)
583 if (!insn->immediate.got)
584 insn_get_immediate(insn);
585 insn->length = (unsigned char)((unsigned long)insn->next_byte
586 - (unsigned long)insn->kaddr);