3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8 * SPDX-License-Identifier: GPL-2.0+
12 * This file provides the interrupt handling functionality for systems
13 * based on the standard PC/AT architecture using two cascaded i8259
14 * Programmable Interrupt Controllers.
19 #include <asm/i8259.h>
20 #include <asm/ibmpc.h>
21 #include <asm/interrupt.h>
23 #if CONFIG_SYS_NUM_IRQS != 16
24 #error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
27 int interrupt_init(void)
33 /* Mask all interrupts */
34 outb(0xff, MASTER_PIC + IMR);
35 outb(0xff, SLAVE_PIC + IMR);
38 /* Place master PIC interrupts at INT20 */
39 /* ICW3, One slave PIC is present */
40 outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
41 outb(0x20, MASTER_PIC + ICW2);
42 outb(IR2, MASTER_PIC + ICW3);
43 outb(ICW4_PM, MASTER_PIC + ICW4);
45 for (i = 0; i < 8; i++)
46 outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
49 /* Place slave PIC interrupts at INT28 */
51 outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
52 outb(0x28, SLAVE_PIC + ICW2);
53 outb(0x02, SLAVE_PIC + ICW3);
54 outb(ICW4_PM, SLAVE_PIC + ICW4);
56 for (i = 0; i < 8; i++)
57 outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
60 * Enable cascaded interrupts by unmasking the cascade IRQ pin of
70 void mask_irq(int irq)
74 if (irq >= CONFIG_SYS_NUM_IRQS)
78 imr_port = SLAVE_PIC + IMR;
80 imr_port = MASTER_PIC + IMR;
82 outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
85 void unmask_irq(int irq)
89 if (irq >= CONFIG_SYS_NUM_IRQS)
93 imr_port = SLAVE_PIC + IMR;
95 imr_port = MASTER_PIC + IMR;
97 outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
100 void specific_eoi(int irq)
102 if (irq >= CONFIG_SYS_NUM_IRQS)
107 * IRQ is on the slave - Issue a corresponding EOI to the
108 * slave PIC and an EOI for IRQ2 (the cascade interrupt)
111 outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
115 outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);