2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
14 #include <linux/pfn.h>
15 #include <linux/percpu.h>
18 #include <asm/processor.h>
19 #include <asm/tlbflush.h>
20 #include <asm/sections.h>
21 #include <asm/setup.h>
22 #include <asm/uaccess.h>
23 #include <asm/pgalloc.h>
24 #include <asm/proto.h>
28 * The current flushing context - we pass it instead of 5 arguments:
37 unsigned force_split : 1;
43 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
44 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
45 * entries change the page attribute in parallel to some other cpu
46 * splitting a large page entry along with changing the attribute.
48 static DEFINE_SPINLOCK(cpa_lock);
50 #define CPA_FLUSHTLB 1
52 #define CPA_PAGES_ARRAY 4
55 static unsigned long direct_pages_count[PG_LEVEL_NUM];
57 void update_page_count(int level, unsigned long pages)
61 /* Protect against CPA */
62 spin_lock_irqsave(&pgd_lock, flags);
63 direct_pages_count[level] += pages;
64 spin_unlock_irqrestore(&pgd_lock, flags);
67 static void split_page_count(int level)
69 direct_pages_count[level]--;
70 direct_pages_count[level - 1] += PTRS_PER_PTE;
73 void arch_report_meminfo(struct seq_file *m)
75 seq_printf(m, "DirectMap4k: %8lu kB\n",
76 direct_pages_count[PG_LEVEL_4K] << 2);
77 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
78 seq_printf(m, "DirectMap2M: %8lu kB\n",
79 direct_pages_count[PG_LEVEL_2M] << 11);
81 seq_printf(m, "DirectMap4M: %8lu kB\n",
82 direct_pages_count[PG_LEVEL_2M] << 12);
86 seq_printf(m, "DirectMap1G: %8lu kB\n",
87 direct_pages_count[PG_LEVEL_1G] << 20);
91 static inline void split_page_count(int level) { }
96 static inline unsigned long highmap_start_pfn(void)
98 return __pa(_text) >> PAGE_SHIFT;
101 static inline unsigned long highmap_end_pfn(void)
103 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
108 #ifdef CONFIG_DEBUG_PAGEALLOC
109 # define debug_pagealloc 1
111 # define debug_pagealloc 0
115 within(unsigned long addr, unsigned long start, unsigned long end)
117 return addr >= start && addr < end;
125 * clflush_cache_range - flush a cache range with clflush
126 * @addr: virtual start address
127 * @size: number of bytes to flush
129 * clflush is an unordered instruction which needs fencing with mfence
130 * to avoid ordering issues.
132 void clflush_cache_range(void *vaddr, unsigned int size)
134 void *vend = vaddr + size - 1;
138 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
141 * Flush any possible final partial cacheline:
147 EXPORT_SYMBOL_GPL(clflush_cache_range);
149 static void __cpa_flush_all(void *arg)
151 unsigned long cache = (unsigned long)arg;
154 * Flush all to work around Errata in early athlons regarding
155 * large page flushing.
159 if (cache && boot_cpu_data.x86 >= 4)
163 static void cpa_flush_all(unsigned long cache)
165 BUG_ON(irqs_disabled());
167 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
170 static void __cpa_flush_range(void *arg)
173 * We could optimize that further and do individual per page
174 * tlb invalidates for a low number of pages. Caveat: we must
175 * flush the high aliases on 64bit as well.
180 static void cpa_flush_range(unsigned long start, int numpages, int cache)
182 unsigned int i, level;
185 BUG_ON(irqs_disabled());
186 WARN_ON(PAGE_ALIGN(start) != start);
188 on_each_cpu(__cpa_flush_range, NULL, 1);
194 * We only need to flush on one CPU,
195 * clflush is a MESI-coherent instruction that
196 * will cause all other CPUs to flush the same
199 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
200 pte_t *pte = lookup_address(addr, &level);
203 * Only flush present addresses:
205 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
206 clflush_cache_range((void *) addr, PAGE_SIZE);
210 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
211 int in_flags, struct page **pages)
213 unsigned int i, level;
214 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
216 BUG_ON(irqs_disabled());
218 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
220 if (!cache || do_wbinvd)
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
229 for (i = 0; i < numpages; i++) {
233 if (in_flags & CPA_PAGES_ARRAY)
234 addr = (unsigned long)page_address(pages[i]);
238 pte = lookup_address(addr, &level);
241 * Only flush present addresses:
243 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
244 clflush_cache_range((void *)addr, PAGE_SIZE);
249 * Certain areas of memory on x86 require very specific protection flags,
250 * for example the BIOS area or kernel text. Callers don't always get this
251 * right (again, ioremap() on BIOS memory is not uncommon) so this function
252 * checks and fixes these known static required protection bits.
254 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
257 pgprot_t forbidden = __pgprot(0);
260 * The BIOS area between 640k and 1Mb needs to be executable for
261 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
263 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
267 * The kernel text needs to be executable for obvious reasons
268 * Does not cover __inittext since that is gone later on. On
269 * 64bit we do not enforce !NX on the low mapping
271 if (within(address, (unsigned long)_text, (unsigned long)_etext))
272 pgprot_val(forbidden) |= _PAGE_NX;
275 * The .rodata section needs to be read-only. Using the pfn
276 * catches all aliases.
278 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
279 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
280 pgprot_val(forbidden) |= _PAGE_RW;
282 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
284 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
285 * kernel text mappings for the large page aligned text, rodata sections
286 * will be always read-only. For the kernel identity mappings covering
287 * the holes caused by this alignment can be anything that user asks.
289 * This will preserve the large page mappings for kernel text/data
292 if (kernel_set_to_readonly &&
293 within(address, (unsigned long)_text,
294 (unsigned long)__end_rodata_hpage_align))
295 pgprot_val(forbidden) |= _PAGE_RW;
298 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
304 * Lookup the page table entry for a virtual address. Return a pointer
305 * to the entry and the level of the mapping.
307 * Note: We return pud and pmd either when the entry is marked large
308 * or when the present bit is not set. Otherwise we would return a
309 * pointer to a nonexisting mapping.
311 pte_t *lookup_address(unsigned long address, unsigned int *level)
313 pgd_t *pgd = pgd_offset_k(address);
317 *level = PG_LEVEL_NONE;
322 pud = pud_offset(pgd, address);
326 *level = PG_LEVEL_1G;
327 if (pud_large(*pud) || !pud_present(*pud))
330 pmd = pmd_offset(pud, address);
334 *level = PG_LEVEL_2M;
335 if (pmd_large(*pmd) || !pmd_present(*pmd))
338 *level = PG_LEVEL_4K;
340 return pte_offset_kernel(pmd, address);
342 EXPORT_SYMBOL_GPL(lookup_address);
345 * Set the new pmd in all the pgds we know about:
347 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
350 set_pte_atomic(kpte, pte);
352 if (!SHARED_KERNEL_PMD) {
355 list_for_each_entry(page, &pgd_list, lru) {
360 pgd = (pgd_t *)page_address(page) + pgd_index(address);
361 pud = pud_offset(pgd, address);
362 pmd = pmd_offset(pud, address);
363 set_pte_atomic((pte_t *)pmd, pte);
370 try_preserve_large_page(pte_t *kpte, unsigned long address,
371 struct cpa_data *cpa)
373 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
374 pte_t new_pte, old_pte, *tmp;
375 pgprot_t old_prot, new_prot;
379 if (cpa->force_split)
382 spin_lock_irqsave(&pgd_lock, flags);
384 * Check for races, another CPU might have split this page
387 tmp = lookup_address(address, &level);
393 psize = PMD_PAGE_SIZE;
394 pmask = PMD_PAGE_MASK;
398 psize = PUD_PAGE_SIZE;
399 pmask = PUD_PAGE_MASK;
408 * Calculate the number of pages, which fit into this large
409 * page starting at address:
411 nextpage_addr = (address + psize) & pmask;
412 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
413 if (numpages < cpa->numpages)
414 cpa->numpages = numpages;
417 * We are safe now. Check whether the new pgprot is the same:
420 old_prot = new_prot = pte_pgprot(old_pte);
422 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
423 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
426 * old_pte points to the large page base address. So we need
427 * to add the offset of the virtual address:
429 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
432 new_prot = static_protections(new_prot, address, pfn);
435 * We need to check the full range, whether
436 * static_protection() requires a different pgprot for one of
437 * the pages in the range we try to preserve:
439 addr = address + PAGE_SIZE;
441 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
442 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
444 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
449 * If there are no changes, return. maxpages has been updated
452 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
458 * We need to change the attributes. Check, whether we can
459 * change the large page in one go. We request a split, when
460 * the address is not aligned and the number of pages is
461 * smaller than the number of pages in the large page. Note
462 * that we limited the number of possible pages already to
463 * the number of pages in the large page.
465 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
467 * The address is aligned and the number of pages
468 * covers the full page.
470 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
471 __set_pmd_pte(kpte, address, new_pte);
472 cpa->flags |= CPA_FLUSHTLB;
477 spin_unlock_irqrestore(&pgd_lock, flags);
482 static int split_large_page(pte_t *kpte, unsigned long address)
484 unsigned long flags, pfn, pfninc = 1;
485 unsigned int i, level;
490 if (!debug_pagealloc)
491 spin_unlock(&cpa_lock);
492 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
493 if (!debug_pagealloc)
494 spin_lock(&cpa_lock);
498 spin_lock_irqsave(&pgd_lock, flags);
500 * Check for races, another CPU might have split this page
503 tmp = lookup_address(address, &level);
507 pbase = (pte_t *)page_address(base);
508 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
509 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
511 * If we ever want to utilize the PAT bit, we need to
512 * update this function to make sure it's converted from
513 * bit 12 to bit 7 when we cross from the 2MB level to
516 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
519 if (level == PG_LEVEL_1G) {
520 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
521 pgprot_val(ref_prot) |= _PAGE_PSE;
526 * Get the target pfn from the original entry:
528 pfn = pte_pfn(*kpte);
529 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
530 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
532 if (address >= (unsigned long)__va(0) &&
533 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
534 split_page_count(level);
537 if (address >= (unsigned long)__va(1UL<<32) &&
538 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
539 split_page_count(level);
543 * Install the new, split up pagetable.
545 * We use the standard kernel pagetable protections for the new
546 * pagetable protections, the actual ptes set above control the
547 * primary protection behavior:
549 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
552 * Intel Atom errata AAH41 workaround.
554 * The real fix should be in hw or in a microcode update, but
555 * we also probabilistically try to reduce the window of having
556 * a large TLB mixed with 4K TLBs while instruction fetches are
565 * If we dropped out via the lookup_address check under
566 * pgd_lock then stick the page back into the pool:
570 spin_unlock_irqrestore(&pgd_lock, flags);
575 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
579 * Ignore all non primary paths.
585 * Ignore the NULL PTE for kernel identity mapping, as it is expected
587 * Also set numpages to '1' indicating that we processed cpa req for
588 * one virtual address page and its pfn. TBD: numpages can be set based
589 * on the initial value and the level returned by lookup_address().
591 if (within(vaddr, PAGE_OFFSET,
592 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
594 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
597 WARN(1, KERN_WARNING "CPA: called for zero pte. "
598 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
605 static int __change_page_attr(struct cpa_data *cpa, int primary)
607 unsigned long address;
610 pte_t *kpte, old_pte;
612 if (cpa->flags & CPA_PAGES_ARRAY) {
613 struct page *page = cpa->pages[cpa->curpage];
614 if (unlikely(PageHighMem(page)))
616 address = (unsigned long)page_address(page);
617 } else if (cpa->flags & CPA_ARRAY)
618 address = cpa->vaddr[cpa->curpage];
620 address = *cpa->vaddr;
622 kpte = lookup_address(address, &level);
624 return __cpa_process_fault(cpa, address, primary);
627 if (!pte_val(old_pte))
628 return __cpa_process_fault(cpa, address, primary);
630 if (level == PG_LEVEL_4K) {
632 pgprot_t new_prot = pte_pgprot(old_pte);
633 unsigned long pfn = pte_pfn(old_pte);
635 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
636 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
638 new_prot = static_protections(new_prot, address, pfn);
641 * We need to keep the pfn from the existing PTE,
642 * after all we're only going to change it's attributes
643 * not the memory it points to
645 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
648 * Do we really change anything ?
650 if (pte_val(old_pte) != pte_val(new_pte)) {
651 set_pte_atomic(kpte, new_pte);
652 cpa->flags |= CPA_FLUSHTLB;
659 * Check, whether we can keep the large page intact
660 * and just change the pte:
662 do_split = try_preserve_large_page(kpte, address, cpa);
664 * When the range fits into the existing large page,
665 * return. cp->numpages and cpa->tlbflush have been updated in
672 * We have to split the large page:
674 err = split_large_page(kpte, address);
677 * Do a global flush tlb after splitting the large page
678 * and before we do the actual change page attribute in the PTE.
680 * With out this, we violate the TLB application note, that says
681 * "The TLBs may contain both ordinary and large-page
682 * translations for a 4-KByte range of linear addresses. This
683 * may occur if software modifies the paging structures so that
684 * the page size used for the address range changes. If the two
685 * translations differ with respect to page frame or attributes
686 * (e.g., permissions), processor behavior is undefined and may
687 * be implementation-specific."
689 * We do this global tlb flush inside the cpa_lock, so that we
690 * don't allow any other cpu, with stale tlb entries change the
691 * page attribute in parallel, that also falls into the
692 * just split large page entry.
701 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
703 static int cpa_process_alias(struct cpa_data *cpa)
705 struct cpa_data alias_cpa;
706 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
710 if (cpa->pfn >= max_pfn_mapped)
714 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
718 * No need to redo, when the primary call touched the direct
721 if (cpa->flags & CPA_PAGES_ARRAY) {
722 struct page *page = cpa->pages[cpa->curpage];
723 if (unlikely(PageHighMem(page)))
725 vaddr = (unsigned long)page_address(page);
726 } else if (cpa->flags & CPA_ARRAY)
727 vaddr = cpa->vaddr[cpa->curpage];
731 if (!(within(vaddr, PAGE_OFFSET,
732 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
735 alias_cpa.vaddr = &laddr;
736 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
738 ret = __change_page_attr_set_clr(&alias_cpa, 0);
745 * If the primary call didn't touch the high mapping already
746 * and the physical address is inside the kernel map, we need
747 * to touch the high mapped kernel as well:
749 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
750 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
751 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
752 __START_KERNEL_map - phys_base;
754 alias_cpa.vaddr = &temp_cpa_vaddr;
755 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
758 * The high mapping range is imprecise, so ignore the
761 __change_page_attr_set_clr(&alias_cpa, 0);
768 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
770 int ret, numpages = cpa->numpages;
774 * Store the remaining nr of pages for the large page
775 * preservation check.
777 cpa->numpages = numpages;
778 /* for array changes, we can't use large page */
779 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
782 if (!debug_pagealloc)
783 spin_lock(&cpa_lock);
784 ret = __change_page_attr(cpa, checkalias);
785 if (!debug_pagealloc)
786 spin_unlock(&cpa_lock);
791 ret = cpa_process_alias(cpa);
797 * Adjust the number of pages with the result of the
798 * CPA operation. Either a large page has been
799 * preserved or a single page update happened.
801 BUG_ON(cpa->numpages > numpages);
802 numpages -= cpa->numpages;
803 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
806 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
812 static inline int cache_attr(pgprot_t attr)
814 return pgprot_val(attr) &
815 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
818 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
819 pgprot_t mask_set, pgprot_t mask_clr,
820 int force_split, int in_flag,
824 int ret, cache, checkalias;
825 unsigned long baddr = 0;
828 * Check, if we are requested to change a not supported
831 mask_set = canon_pgprot(mask_set);
832 mask_clr = canon_pgprot(mask_clr);
833 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
836 /* Ensure we are PAGE_SIZE aligned */
837 if (in_flag & CPA_ARRAY) {
839 for (i = 0; i < numpages; i++) {
840 if (addr[i] & ~PAGE_MASK) {
841 addr[i] &= PAGE_MASK;
845 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
847 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
848 * No need to cehck in that case
850 if (*addr & ~PAGE_MASK) {
853 * People should not be passing in unaligned addresses:
858 * Save address for cache flush. *addr is modified in the call
859 * to __change_page_attr_set_clr() below.
864 /* Must avoid aliasing mappings in the highmem code */
871 cpa.numpages = numpages;
872 cpa.mask_set = mask_set;
873 cpa.mask_clr = mask_clr;
876 cpa.force_split = force_split;
878 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
879 cpa.flags |= in_flag;
881 /* No alias checking for _NX bit modifications */
882 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
884 ret = __change_page_attr_set_clr(&cpa, checkalias);
887 * Check whether we really changed something:
889 if (!(cpa.flags & CPA_FLUSHTLB))
893 * No need to flush, when we did not set any of the caching
896 cache = cache_attr(mask_set);
899 * On success we use clflush, when the CPU supports it to
900 * avoid the wbindv. If the CPU does not support it and in the
901 * error case we fall back to cpa_flush_all (which uses
904 if (!ret && cpu_has_clflush) {
905 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
906 cpa_flush_array(addr, numpages, cache,
909 cpa_flush_range(baddr, numpages, cache);
911 cpa_flush_all(cache);
917 static inline int change_page_attr_set(unsigned long *addr, int numpages,
918 pgprot_t mask, int array)
920 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
921 (array ? CPA_ARRAY : 0), NULL);
924 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
925 pgprot_t mask, int array)
927 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
928 (array ? CPA_ARRAY : 0), NULL);
931 static inline int cpa_set_pages_array(struct page **pages, int numpages,
934 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
935 CPA_PAGES_ARRAY, pages);
938 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
941 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
942 CPA_PAGES_ARRAY, pages);
945 int _set_memory_uc(unsigned long addr, int numpages)
948 * for now UC MINUS. see comments in ioremap_nocache()
950 return change_page_attr_set(&addr, numpages,
951 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
954 int set_memory_uc(unsigned long addr, int numpages)
959 * for now UC MINUS. see comments in ioremap_nocache()
961 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
962 _PAGE_CACHE_UC_MINUS, NULL);
966 ret = _set_memory_uc(addr, numpages);
973 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
977 EXPORT_SYMBOL(set_memory_uc);
979 int set_memory_array_uc(unsigned long *addr, int addrinarray)
985 * for now UC MINUS. see comments in ioremap_nocache()
987 for (i = 0; i < addrinarray; i++) {
988 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
989 _PAGE_CACHE_UC_MINUS, NULL);
994 ret = change_page_attr_set(addr, addrinarray,
995 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1002 for (j = 0; j < i; j++)
1003 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1007 EXPORT_SYMBOL(set_memory_array_uc);
1009 int _set_memory_wc(unsigned long addr, int numpages)
1012 unsigned long addr_copy = addr;
1014 ret = change_page_attr_set(&addr, numpages,
1015 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1017 ret = change_page_attr_set_clr(&addr_copy, numpages,
1018 __pgprot(_PAGE_CACHE_WC),
1019 __pgprot(_PAGE_CACHE_MASK),
1025 int set_memory_wc(unsigned long addr, int numpages)
1030 return set_memory_uc(addr, numpages);
1032 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1033 _PAGE_CACHE_WC, NULL);
1037 ret = _set_memory_wc(addr, numpages);
1044 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1048 EXPORT_SYMBOL(set_memory_wc);
1050 int _set_memory_wb(unsigned long addr, int numpages)
1052 return change_page_attr_clear(&addr, numpages,
1053 __pgprot(_PAGE_CACHE_MASK), 0);
1056 int set_memory_wb(unsigned long addr, int numpages)
1060 ret = _set_memory_wb(addr, numpages);
1064 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1067 EXPORT_SYMBOL(set_memory_wb);
1069 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1074 ret = change_page_attr_clear(addr, addrinarray,
1075 __pgprot(_PAGE_CACHE_MASK), 1);
1079 for (i = 0; i < addrinarray; i++)
1080 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1084 EXPORT_SYMBOL(set_memory_array_wb);
1086 int set_memory_x(unsigned long addr, int numpages)
1088 if (!(__supported_pte_mask & _PAGE_NX))
1091 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1093 EXPORT_SYMBOL(set_memory_x);
1095 int set_memory_nx(unsigned long addr, int numpages)
1097 if (!(__supported_pte_mask & _PAGE_NX))
1100 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1102 EXPORT_SYMBOL(set_memory_nx);
1104 int set_memory_ro(unsigned long addr, int numpages)
1106 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1108 EXPORT_SYMBOL_GPL(set_memory_ro);
1110 int set_memory_rw(unsigned long addr, int numpages)
1112 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1114 EXPORT_SYMBOL_GPL(set_memory_rw);
1116 int set_memory_np(unsigned long addr, int numpages)
1118 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1121 int set_memory_4k(unsigned long addr, int numpages)
1123 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1124 __pgprot(0), 1, 0, NULL);
1127 int set_pages_uc(struct page *page, int numpages)
1129 unsigned long addr = (unsigned long)page_address(page);
1131 return set_memory_uc(addr, numpages);
1133 EXPORT_SYMBOL(set_pages_uc);
1135 int set_pages_array_uc(struct page **pages, int addrinarray)
1137 unsigned long start;
1142 for (i = 0; i < addrinarray; i++) {
1143 if (PageHighMem(pages[i]))
1145 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1146 end = start + PAGE_SIZE;
1147 if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))
1151 if (cpa_set_pages_array(pages, addrinarray,
1152 __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) {
1153 return 0; /* Success */
1157 for (i = 0; i < free_idx; i++) {
1158 if (PageHighMem(pages[i]))
1160 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1161 end = start + PAGE_SIZE;
1162 free_memtype(start, end);
1166 EXPORT_SYMBOL(set_pages_array_uc);
1168 int set_pages_wb(struct page *page, int numpages)
1170 unsigned long addr = (unsigned long)page_address(page);
1172 return set_memory_wb(addr, numpages);
1174 EXPORT_SYMBOL(set_pages_wb);
1176 int set_pages_array_wb(struct page **pages, int addrinarray)
1179 unsigned long start;
1183 retval = cpa_clear_pages_array(pages, addrinarray,
1184 __pgprot(_PAGE_CACHE_MASK));
1188 for (i = 0; i < addrinarray; i++) {
1189 if (PageHighMem(pages[i]))
1191 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1192 end = start + PAGE_SIZE;
1193 free_memtype(start, end);
1198 EXPORT_SYMBOL(set_pages_array_wb);
1200 int set_pages_x(struct page *page, int numpages)
1202 unsigned long addr = (unsigned long)page_address(page);
1204 return set_memory_x(addr, numpages);
1206 EXPORT_SYMBOL(set_pages_x);
1208 int set_pages_nx(struct page *page, int numpages)
1210 unsigned long addr = (unsigned long)page_address(page);
1212 return set_memory_nx(addr, numpages);
1214 EXPORT_SYMBOL(set_pages_nx);
1216 int set_pages_ro(struct page *page, int numpages)
1218 unsigned long addr = (unsigned long)page_address(page);
1220 return set_memory_ro(addr, numpages);
1223 int set_pages_rw(struct page *page, int numpages)
1225 unsigned long addr = (unsigned long)page_address(page);
1227 return set_memory_rw(addr, numpages);
1230 #ifdef CONFIG_DEBUG_PAGEALLOC
1232 static int __set_pages_p(struct page *page, int numpages)
1234 unsigned long tempaddr = (unsigned long) page_address(page);
1235 struct cpa_data cpa = { .vaddr = &tempaddr,
1236 .numpages = numpages,
1237 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1238 .mask_clr = __pgprot(0),
1242 * No alias checking needed for setting present flag. otherwise,
1243 * we may need to break large pages for 64-bit kernel text
1244 * mappings (this adds to complexity if we want to do this from
1245 * atomic context especially). Let's keep it simple!
1247 return __change_page_attr_set_clr(&cpa, 0);
1250 static int __set_pages_np(struct page *page, int numpages)
1252 unsigned long tempaddr = (unsigned long) page_address(page);
1253 struct cpa_data cpa = { .vaddr = &tempaddr,
1254 .numpages = numpages,
1255 .mask_set = __pgprot(0),
1256 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1260 * No alias checking needed for setting not present flag. otherwise,
1261 * we may need to break large pages for 64-bit kernel text
1262 * mappings (this adds to complexity if we want to do this from
1263 * atomic context especially). Let's keep it simple!
1265 return __change_page_attr_set_clr(&cpa, 0);
1268 void kernel_map_pages(struct page *page, int numpages, int enable)
1270 if (PageHighMem(page))
1273 debug_check_no_locks_freed(page_address(page),
1274 numpages * PAGE_SIZE);
1278 * If page allocator is not up yet then do not call c_p_a():
1280 if (!debug_pagealloc_enabled)
1284 * The return value is ignored as the calls cannot fail.
1285 * Large pages for identity mappings are not used at boot time
1286 * and hence no memory allocations during large page split.
1289 __set_pages_p(page, numpages);
1291 __set_pages_np(page, numpages);
1294 * We should perform an IPI and flush all tlbs,
1295 * but that can deadlock->flush only current cpu:
1300 #ifdef CONFIG_HIBERNATION
1302 bool kernel_page_present(struct page *page)
1307 if (PageHighMem(page))
1310 pte = lookup_address((unsigned long)page_address(page), &level);
1311 return (pte_val(*pte) & _PAGE_PRESENT);
1314 #endif /* CONFIG_HIBERNATION */
1316 #endif /* CONFIG_DEBUG_PAGEALLOC */
1319 * The testcases use internal knowledge of the implementation that shouldn't
1320 * be exposed to the rest of the kernel. Include these directly here.
1322 #ifdef CONFIG_CPA_DEBUG
1323 #include "pageattr-test.c"