2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
16 #include <linux/pci.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
38 unsigned force_split : 1;
44 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
45 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
46 * entries change the page attribute in parallel to some other cpu
47 * splitting a large page entry along with changing the attribute.
49 static DEFINE_SPINLOCK(cpa_lock);
51 #define CPA_FLUSHTLB 1
53 #define CPA_PAGES_ARRAY 4
56 static unsigned long direct_pages_count[PG_LEVEL_NUM];
58 void update_page_count(int level, unsigned long pages)
60 /* Protect against CPA */
62 direct_pages_count[level] += pages;
63 spin_unlock(&pgd_lock);
66 static void split_page_count(int level)
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
72 void arch_report_meminfo(struct seq_file *m)
74 seq_printf(m, "DirectMap4k: %8lu kB\n",
75 direct_pages_count[PG_LEVEL_4K] << 2);
76 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
77 seq_printf(m, "DirectMap2M: %8lu kB\n",
78 direct_pages_count[PG_LEVEL_2M] << 11);
80 seq_printf(m, "DirectMap4M: %8lu kB\n",
81 direct_pages_count[PG_LEVEL_2M] << 12);
85 seq_printf(m, "DirectMap1G: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_1G] << 20);
90 static inline void split_page_count(int level) { }
95 static inline unsigned long highmap_start_pfn(void)
97 return __pa_symbol(_text) >> PAGE_SHIFT;
100 static inline unsigned long highmap_end_pfn(void)
102 return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
107 #ifdef CONFIG_DEBUG_PAGEALLOC
108 # define debug_pagealloc 1
110 # define debug_pagealloc 0
114 within(unsigned long addr, unsigned long start, unsigned long end)
116 return addr >= start && addr < end;
124 * clflush_cache_range - flush a cache range with clflush
125 * @vaddr: virtual start address
126 * @size: number of bytes to flush
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
131 void clflush_cache_range(void *vaddr, unsigned int size)
133 void *vend = vaddr + size - 1;
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
140 * Flush any possible final partial cacheline:
146 EXPORT_SYMBOL_GPL(clflush_cache_range);
148 static void __cpa_flush_all(void *arg)
150 unsigned long cache = (unsigned long)arg;
153 * Flush all to work around Errata in early athlons regarding
154 * large page flushing.
158 if (cache && boot_cpu_data.x86 >= 4)
162 static void cpa_flush_all(unsigned long cache)
164 BUG_ON(irqs_disabled());
166 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
169 static void __cpa_flush_range(void *arg)
172 * We could optimize that further and do individual per page
173 * tlb invalidates for a low number of pages. Caveat: we must
174 * flush the high aliases on 64bit as well.
179 static void cpa_flush_range(unsigned long start, int numpages, int cache)
181 unsigned int i, level;
184 BUG_ON(irqs_disabled());
185 WARN_ON(PAGE_ALIGN(start) != start);
187 on_each_cpu(__cpa_flush_range, NULL, 1);
193 * We only need to flush on one CPU,
194 * clflush is a MESI-coherent instruction that
195 * will cause all other CPUs to flush the same
198 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
199 pte_t *pte = lookup_address(addr, &level);
202 * Only flush present addresses:
204 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
205 clflush_cache_range((void *) addr, PAGE_SIZE);
209 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
210 int in_flags, struct page **pages)
212 unsigned int i, level;
213 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
215 BUG_ON(irqs_disabled());
217 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
219 if (!cache || do_wbinvd)
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
228 for (i = 0; i < numpages; i++) {
232 if (in_flags & CPA_PAGES_ARRAY)
233 addr = (unsigned long)page_address(pages[i]);
237 pte = lookup_address(addr, &level);
240 * Only flush present addresses:
242 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
243 clflush_cache_range((void *)addr, PAGE_SIZE);
248 * Certain areas of memory on x86 require very specific protection flags,
249 * for example the BIOS area or kernel text. Callers don't always get this
250 * right (again, ioremap() on BIOS memory is not uncommon) so this function
251 * checks and fixes these known static required protection bits.
253 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
256 pgprot_t forbidden = __pgprot(0);
259 * The BIOS area between 640k and 1Mb needs to be executable for
260 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
262 #ifdef CONFIG_PCI_BIOS
263 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
268 * The kernel text needs to be executable for obvious reasons
269 * Does not cover __inittext since that is gone later on. On
270 * 64bit we do not enforce !NX on the low mapping
272 if (within(address, (unsigned long)_text, (unsigned long)_etext))
273 pgprot_val(forbidden) |= _PAGE_NX;
276 * The .rodata section needs to be read-only. Using the pfn
277 * catches all aliases.
279 if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
280 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
281 pgprot_val(forbidden) |= _PAGE_RW;
283 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
285 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
286 * kernel text mappings for the large page aligned text, rodata sections
287 * will be always read-only. For the kernel identity mappings covering
288 * the holes caused by this alignment can be anything that user asks.
290 * This will preserve the large page mappings for kernel text/data
293 if (kernel_set_to_readonly &&
294 within(address, (unsigned long)_text,
295 (unsigned long)__end_rodata_hpage_align)) {
299 * Don't enforce the !RW mapping for the kernel text mapping,
300 * if the current mapping is already using small page mapping.
301 * No need to work hard to preserve large page mappings in this
304 * This also fixes the Linux Xen paravirt guest boot failure
305 * (because of unexpected read-only mappings for kernel identity
306 * mappings). In this paravirt guest case, the kernel text
307 * mapping and the kernel identity mapping share the same
308 * page-table pages. Thus we can't really use different
309 * protections for the kernel text and identity mappings. Also,
310 * these shared mappings are made of small page mappings.
311 * Thus this don't enforce !RW mapping for small page kernel
312 * text mapping logic will help Linux Xen parvirt guest boot
315 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
316 pgprot_val(forbidden) |= _PAGE_RW;
320 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
326 * Lookup the page table entry for a virtual address. Return a pointer
327 * to the entry and the level of the mapping.
329 * Note: We return pud and pmd either when the entry is marked large
330 * or when the present bit is not set. Otherwise we would return a
331 * pointer to a nonexisting mapping.
333 pte_t *lookup_address(unsigned long address, unsigned int *level)
335 pgd_t *pgd = pgd_offset_k(address);
339 *level = PG_LEVEL_NONE;
344 pud = pud_offset(pgd, address);
348 *level = PG_LEVEL_1G;
349 if (pud_large(*pud) || !pud_present(*pud))
352 pmd = pmd_offset(pud, address);
356 *level = PG_LEVEL_2M;
357 if (pmd_large(*pmd) || !pmd_present(*pmd))
360 *level = PG_LEVEL_4K;
362 return pte_offset_kernel(pmd, address);
364 EXPORT_SYMBOL_GPL(lookup_address);
367 * This is necessary because __pa() does not work on some
368 * kinds of memory, like vmalloc() or the alloc_remap()
369 * areas on 32-bit NUMA systems. The percpu areas can
370 * end up in this kind of memory, for instance.
372 * This could be optimized, but it is only intended to be
373 * used at inititalization time, and keeping it
374 * unoptimized should increase the testing coverage for
375 * the more obscure platforms.
377 phys_addr_t slow_virt_to_phys(void *__virt_addr)
379 unsigned long virt_addr = (unsigned long)__virt_addr;
380 phys_addr_t phys_addr;
381 unsigned long offset;
387 pte = lookup_address(virt_addr, &level);
389 psize = page_level_size(level);
390 pmask = page_level_mask(level);
391 offset = virt_addr & ~pmask;
392 phys_addr = pte_pfn(*pte) << PAGE_SHIFT;
393 return (phys_addr | offset);
395 EXPORT_SYMBOL_GPL(slow_virt_to_phys);
398 * Set the new pmd in all the pgds we know about:
400 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
403 set_pte_atomic(kpte, pte);
405 if (!SHARED_KERNEL_PMD) {
408 list_for_each_entry(page, &pgd_list, lru) {
413 pgd = (pgd_t *)page_address(page) + pgd_index(address);
414 pud = pud_offset(pgd, address);
415 pmd = pmd_offset(pud, address);
416 set_pte_atomic((pte_t *)pmd, pte);
423 try_preserve_large_page(pte_t *kpte, unsigned long address,
424 struct cpa_data *cpa)
426 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
427 pte_t new_pte, old_pte, *tmp;
428 pgprot_t old_prot, new_prot, req_prot;
432 if (cpa->force_split)
435 spin_lock(&pgd_lock);
437 * Check for races, another CPU might have split this page
440 tmp = lookup_address(address, &level);
449 psize = page_level_size(level);
450 pmask = page_level_mask(level);
458 * Calculate the number of pages, which fit into this large
459 * page starting at address:
461 nextpage_addr = (address + psize) & pmask;
462 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
463 if (numpages < cpa->numpages)
464 cpa->numpages = numpages;
467 * We are safe now. Check whether the new pgprot is the same:
470 old_prot = req_prot = pte_pgprot(old_pte);
472 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
473 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
476 * Set the PSE and GLOBAL flags only if the PRESENT flag is
477 * set otherwise pmd_present/pmd_huge will return true even on
478 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
479 * for the ancient hardware that doesn't support it.
481 if (pgprot_val(req_prot) & _PAGE_PRESENT)
482 pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL;
484 pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL);
486 req_prot = canon_pgprot(req_prot);
489 * old_pte points to the large page base address. So we need
490 * to add the offset of the virtual address:
492 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
495 new_prot = static_protections(req_prot, address, pfn);
498 * We need to check the full range, whether
499 * static_protection() requires a different pgprot for one of
500 * the pages in the range we try to preserve:
502 addr = address & pmask;
503 pfn = pte_pfn(old_pte);
504 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
505 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
507 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
512 * If there are no changes, return. maxpages has been updated
515 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
521 * We need to change the attributes. Check, whether we can
522 * change the large page in one go. We request a split, when
523 * the address is not aligned and the number of pages is
524 * smaller than the number of pages in the large page. Note
525 * that we limited the number of possible pages already to
526 * the number of pages in the large page.
528 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
530 * The address is aligned and the number of pages
531 * covers the full page.
533 new_pte = pfn_pte(pte_pfn(old_pte), new_prot);
534 __set_pmd_pte(kpte, address, new_pte);
535 cpa->flags |= CPA_FLUSHTLB;
540 spin_unlock(&pgd_lock);
546 __split_large_page(pte_t *kpte, unsigned long address, struct page *base)
548 pte_t *pbase = (pte_t *)page_address(base);
549 unsigned long pfn, pfninc = 1;
550 unsigned int i, level;
554 spin_lock(&pgd_lock);
556 * Check for races, another CPU might have split this page
559 tmp = lookup_address(address, &level);
561 spin_unlock(&pgd_lock);
565 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
566 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
568 * If we ever want to utilize the PAT bit, we need to
569 * update this function to make sure it's converted from
570 * bit 12 to bit 7 when we cross from the 2MB level to
573 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
576 if (level == PG_LEVEL_1G) {
577 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
579 * Set the PSE flags only if the PRESENT flag is set
580 * otherwise pmd_present/pmd_huge will return true
581 * even on a non present pmd.
583 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
584 pgprot_val(ref_prot) |= _PAGE_PSE;
586 pgprot_val(ref_prot) &= ~_PAGE_PSE;
591 * Set the GLOBAL flags only if the PRESENT flag is set
592 * otherwise pmd/pte_present will return true even on a non
593 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
594 * for the ancient hardware that doesn't support it.
596 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
597 pgprot_val(ref_prot) |= _PAGE_GLOBAL;
599 pgprot_val(ref_prot) &= ~_PAGE_GLOBAL;
602 * Get the target pfn from the original entry:
604 pfn = pte_pfn(*kpte);
605 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
606 set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot)));
608 if (pfn_range_is_mapped(PFN_DOWN(__pa(address)),
609 PFN_DOWN(__pa(address)) + 1))
610 split_page_count(level);
613 * Install the new, split up pagetable.
615 * We use the standard kernel pagetable protections for the new
616 * pagetable protections, the actual ptes set above control the
617 * primary protection behavior:
619 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
622 * Intel Atom errata AAH41 workaround.
624 * The real fix should be in hw or in a microcode update, but
625 * we also probabilistically try to reduce the window of having
626 * a large TLB mixed with 4K TLBs while instruction fetches are
630 spin_unlock(&pgd_lock);
635 static int split_large_page(pte_t *kpte, unsigned long address)
639 if (!debug_pagealloc)
640 spin_unlock(&cpa_lock);
641 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
642 if (!debug_pagealloc)
643 spin_lock(&cpa_lock);
647 if (__split_large_page(kpte, address, base))
653 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
657 * Ignore all non primary paths.
663 * Ignore the NULL PTE for kernel identity mapping, as it is expected
665 * Also set numpages to '1' indicating that we processed cpa req for
666 * one virtual address page and its pfn. TBD: numpages can be set based
667 * on the initial value and the level returned by lookup_address().
669 if (within(vaddr, PAGE_OFFSET,
670 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
672 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
675 WARN(1, KERN_WARNING "CPA: called for zero pte. "
676 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
683 static int __change_page_attr(struct cpa_data *cpa, int primary)
685 unsigned long address;
688 pte_t *kpte, old_pte;
690 if (cpa->flags & CPA_PAGES_ARRAY) {
691 struct page *page = cpa->pages[cpa->curpage];
692 if (unlikely(PageHighMem(page)))
694 address = (unsigned long)page_address(page);
695 } else if (cpa->flags & CPA_ARRAY)
696 address = cpa->vaddr[cpa->curpage];
698 address = *cpa->vaddr;
700 kpte = lookup_address(address, &level);
702 return __cpa_process_fault(cpa, address, primary);
705 if (!pte_val(old_pte))
706 return __cpa_process_fault(cpa, address, primary);
708 if (level == PG_LEVEL_4K) {
710 pgprot_t new_prot = pte_pgprot(old_pte);
711 unsigned long pfn = pte_pfn(old_pte);
713 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
714 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
716 new_prot = static_protections(new_prot, address, pfn);
719 * Set the GLOBAL flags only if the PRESENT flag is
720 * set otherwise pte_present will return true even on
721 * a non present pte. The canon_pgprot will clear
722 * _PAGE_GLOBAL for the ancient hardware that doesn't
725 if (pgprot_val(new_prot) & _PAGE_PRESENT)
726 pgprot_val(new_prot) |= _PAGE_GLOBAL;
728 pgprot_val(new_prot) &= ~_PAGE_GLOBAL;
731 * We need to keep the pfn from the existing PTE,
732 * after all we're only going to change it's attributes
733 * not the memory it points to
735 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
738 * Do we really change anything ?
740 if (pte_val(old_pte) != pte_val(new_pte)) {
741 set_pte_atomic(kpte, new_pte);
742 cpa->flags |= CPA_FLUSHTLB;
749 * Check, whether we can keep the large page intact
750 * and just change the pte:
752 do_split = try_preserve_large_page(kpte, address, cpa);
754 * When the range fits into the existing large page,
755 * return. cp->numpages and cpa->tlbflush have been updated in
762 * We have to split the large page:
764 err = split_large_page(kpte, address);
767 * Do a global flush tlb after splitting the large page
768 * and before we do the actual change page attribute in the PTE.
770 * With out this, we violate the TLB application note, that says
771 * "The TLBs may contain both ordinary and large-page
772 * translations for a 4-KByte range of linear addresses. This
773 * may occur if software modifies the paging structures so that
774 * the page size used for the address range changes. If the two
775 * translations differ with respect to page frame or attributes
776 * (e.g., permissions), processor behavior is undefined and may
777 * be implementation-specific."
779 * We do this global tlb flush inside the cpa_lock, so that we
780 * don't allow any other cpu, with stale tlb entries change the
781 * page attribute in parallel, that also falls into the
782 * just split large page entry.
791 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
793 static int cpa_process_alias(struct cpa_data *cpa)
795 struct cpa_data alias_cpa;
796 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
800 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
804 * No need to redo, when the primary call touched the direct
807 if (cpa->flags & CPA_PAGES_ARRAY) {
808 struct page *page = cpa->pages[cpa->curpage];
809 if (unlikely(PageHighMem(page)))
811 vaddr = (unsigned long)page_address(page);
812 } else if (cpa->flags & CPA_ARRAY)
813 vaddr = cpa->vaddr[cpa->curpage];
817 if (!(within(vaddr, PAGE_OFFSET,
818 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
821 alias_cpa.vaddr = &laddr;
822 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
824 ret = __change_page_attr_set_clr(&alias_cpa, 0);
831 * If the primary call didn't touch the high mapping already
832 * and the physical address is inside the kernel map, we need
833 * to touch the high mapped kernel as well:
835 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
836 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
837 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
838 __START_KERNEL_map - phys_base;
840 alias_cpa.vaddr = &temp_cpa_vaddr;
841 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
844 * The high mapping range is imprecise, so ignore the
847 __change_page_attr_set_clr(&alias_cpa, 0);
854 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
856 int ret, numpages = cpa->numpages;
860 * Store the remaining nr of pages for the large page
861 * preservation check.
863 cpa->numpages = numpages;
864 /* for array changes, we can't use large page */
865 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
868 if (!debug_pagealloc)
869 spin_lock(&cpa_lock);
870 ret = __change_page_attr(cpa, checkalias);
871 if (!debug_pagealloc)
872 spin_unlock(&cpa_lock);
877 ret = cpa_process_alias(cpa);
883 * Adjust the number of pages with the result of the
884 * CPA operation. Either a large page has been
885 * preserved or a single page update happened.
887 BUG_ON(cpa->numpages > numpages);
888 numpages -= cpa->numpages;
889 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
892 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
898 static inline int cache_attr(pgprot_t attr)
900 return pgprot_val(attr) &
901 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
904 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
905 pgprot_t mask_set, pgprot_t mask_clr,
906 int force_split, int in_flag,
910 int ret, cache, checkalias;
911 unsigned long baddr = 0;
914 * Check, if we are requested to change a not supported
917 mask_set = canon_pgprot(mask_set);
918 mask_clr = canon_pgprot(mask_clr);
919 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
922 /* Ensure we are PAGE_SIZE aligned */
923 if (in_flag & CPA_ARRAY) {
925 for (i = 0; i < numpages; i++) {
926 if (addr[i] & ~PAGE_MASK) {
927 addr[i] &= PAGE_MASK;
931 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
933 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
934 * No need to cehck in that case
936 if (*addr & ~PAGE_MASK) {
939 * People should not be passing in unaligned addresses:
944 * Save address for cache flush. *addr is modified in the call
945 * to __change_page_attr_set_clr() below.
950 /* Must avoid aliasing mappings in the highmem code */
957 cpa.numpages = numpages;
958 cpa.mask_set = mask_set;
959 cpa.mask_clr = mask_clr;
962 cpa.force_split = force_split;
964 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
965 cpa.flags |= in_flag;
967 /* No alias checking for _NX bit modifications */
968 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
970 ret = __change_page_attr_set_clr(&cpa, checkalias);
973 * Check whether we really changed something:
975 if (!(cpa.flags & CPA_FLUSHTLB))
979 * No need to flush, when we did not set any of the caching
982 cache = cache_attr(mask_set);
985 * On success we use clflush, when the CPU supports it to
986 * avoid the wbindv. If the CPU does not support it and in the
987 * error case we fall back to cpa_flush_all (which uses
990 if (!ret && cpu_has_clflush) {
991 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
992 cpa_flush_array(addr, numpages, cache,
995 cpa_flush_range(baddr, numpages, cache);
997 cpa_flush_all(cache);
1003 static inline int change_page_attr_set(unsigned long *addr, int numpages,
1004 pgprot_t mask, int array)
1006 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
1007 (array ? CPA_ARRAY : 0), NULL);
1010 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1011 pgprot_t mask, int array)
1013 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
1014 (array ? CPA_ARRAY : 0), NULL);
1017 static inline int cpa_set_pages_array(struct page **pages, int numpages,
1020 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1021 CPA_PAGES_ARRAY, pages);
1024 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1027 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1028 CPA_PAGES_ARRAY, pages);
1031 int _set_memory_uc(unsigned long addr, int numpages)
1034 * for now UC MINUS. see comments in ioremap_nocache()
1036 return change_page_attr_set(&addr, numpages,
1037 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1040 int set_memory_uc(unsigned long addr, int numpages)
1045 * for now UC MINUS. see comments in ioremap_nocache()
1047 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1048 _PAGE_CACHE_UC_MINUS, NULL);
1052 ret = _set_memory_uc(addr, numpages);
1059 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1063 EXPORT_SYMBOL(set_memory_uc);
1065 static int _set_memory_array(unsigned long *addr, int addrinarray,
1066 unsigned long new_type)
1072 * for now UC MINUS. see comments in ioremap_nocache()
1074 for (i = 0; i < addrinarray; i++) {
1075 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1081 ret = change_page_attr_set(addr, addrinarray,
1082 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1084 if (!ret && new_type == _PAGE_CACHE_WC)
1085 ret = change_page_attr_set_clr(addr, addrinarray,
1086 __pgprot(_PAGE_CACHE_WC),
1087 __pgprot(_PAGE_CACHE_MASK),
1088 0, CPA_ARRAY, NULL);
1095 for (j = 0; j < i; j++)
1096 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1101 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1103 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1105 EXPORT_SYMBOL(set_memory_array_uc);
1107 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1109 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1111 EXPORT_SYMBOL(set_memory_array_wc);
1113 int _set_memory_wc(unsigned long addr, int numpages)
1116 unsigned long addr_copy = addr;
1118 ret = change_page_attr_set(&addr, numpages,
1119 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1121 ret = change_page_attr_set_clr(&addr_copy, numpages,
1122 __pgprot(_PAGE_CACHE_WC),
1123 __pgprot(_PAGE_CACHE_MASK),
1129 int set_memory_wc(unsigned long addr, int numpages)
1134 return set_memory_uc(addr, numpages);
1136 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1137 _PAGE_CACHE_WC, NULL);
1141 ret = _set_memory_wc(addr, numpages);
1148 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1152 EXPORT_SYMBOL(set_memory_wc);
1154 int _set_memory_wb(unsigned long addr, int numpages)
1156 return change_page_attr_clear(&addr, numpages,
1157 __pgprot(_PAGE_CACHE_MASK), 0);
1160 int set_memory_wb(unsigned long addr, int numpages)
1164 ret = _set_memory_wb(addr, numpages);
1168 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1171 EXPORT_SYMBOL(set_memory_wb);
1173 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1178 ret = change_page_attr_clear(addr, addrinarray,
1179 __pgprot(_PAGE_CACHE_MASK), 1);
1183 for (i = 0; i < addrinarray; i++)
1184 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1188 EXPORT_SYMBOL(set_memory_array_wb);
1190 int set_memory_x(unsigned long addr, int numpages)
1192 if (!(__supported_pte_mask & _PAGE_NX))
1195 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1197 EXPORT_SYMBOL(set_memory_x);
1199 int set_memory_nx(unsigned long addr, int numpages)
1201 if (!(__supported_pte_mask & _PAGE_NX))
1204 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1206 EXPORT_SYMBOL(set_memory_nx);
1208 int set_memory_ro(unsigned long addr, int numpages)
1210 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1212 EXPORT_SYMBOL_GPL(set_memory_ro);
1214 int set_memory_rw(unsigned long addr, int numpages)
1216 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1218 EXPORT_SYMBOL_GPL(set_memory_rw);
1220 int set_memory_np(unsigned long addr, int numpages)
1222 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1225 int set_memory_4k(unsigned long addr, int numpages)
1227 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1228 __pgprot(0), 1, 0, NULL);
1231 int set_pages_uc(struct page *page, int numpages)
1233 unsigned long addr = (unsigned long)page_address(page);
1235 return set_memory_uc(addr, numpages);
1237 EXPORT_SYMBOL(set_pages_uc);
1239 static int _set_pages_array(struct page **pages, int addrinarray,
1240 unsigned long new_type)
1242 unsigned long start;
1248 for (i = 0; i < addrinarray; i++) {
1249 if (PageHighMem(pages[i]))
1251 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1252 end = start + PAGE_SIZE;
1253 if (reserve_memtype(start, end, new_type, NULL))
1257 ret = cpa_set_pages_array(pages, addrinarray,
1258 __pgprot(_PAGE_CACHE_UC_MINUS));
1259 if (!ret && new_type == _PAGE_CACHE_WC)
1260 ret = change_page_attr_set_clr(NULL, addrinarray,
1261 __pgprot(_PAGE_CACHE_WC),
1262 __pgprot(_PAGE_CACHE_MASK),
1263 0, CPA_PAGES_ARRAY, pages);
1266 return 0; /* Success */
1269 for (i = 0; i < free_idx; i++) {
1270 if (PageHighMem(pages[i]))
1272 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1273 end = start + PAGE_SIZE;
1274 free_memtype(start, end);
1279 int set_pages_array_uc(struct page **pages, int addrinarray)
1281 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1283 EXPORT_SYMBOL(set_pages_array_uc);
1285 int set_pages_array_wc(struct page **pages, int addrinarray)
1287 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1289 EXPORT_SYMBOL(set_pages_array_wc);
1291 int set_pages_wb(struct page *page, int numpages)
1293 unsigned long addr = (unsigned long)page_address(page);
1295 return set_memory_wb(addr, numpages);
1297 EXPORT_SYMBOL(set_pages_wb);
1299 int set_pages_array_wb(struct page **pages, int addrinarray)
1302 unsigned long start;
1306 retval = cpa_clear_pages_array(pages, addrinarray,
1307 __pgprot(_PAGE_CACHE_MASK));
1311 for (i = 0; i < addrinarray; i++) {
1312 if (PageHighMem(pages[i]))
1314 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1315 end = start + PAGE_SIZE;
1316 free_memtype(start, end);
1321 EXPORT_SYMBOL(set_pages_array_wb);
1323 int set_pages_x(struct page *page, int numpages)
1325 unsigned long addr = (unsigned long)page_address(page);
1327 return set_memory_x(addr, numpages);
1329 EXPORT_SYMBOL(set_pages_x);
1331 int set_pages_nx(struct page *page, int numpages)
1333 unsigned long addr = (unsigned long)page_address(page);
1335 return set_memory_nx(addr, numpages);
1337 EXPORT_SYMBOL(set_pages_nx);
1339 int set_pages_ro(struct page *page, int numpages)
1341 unsigned long addr = (unsigned long)page_address(page);
1343 return set_memory_ro(addr, numpages);
1346 int set_pages_rw(struct page *page, int numpages)
1348 unsigned long addr = (unsigned long)page_address(page);
1350 return set_memory_rw(addr, numpages);
1353 #ifdef CONFIG_DEBUG_PAGEALLOC
1355 static int __set_pages_p(struct page *page, int numpages)
1357 unsigned long tempaddr = (unsigned long) page_address(page);
1358 struct cpa_data cpa = { .vaddr = &tempaddr,
1359 .numpages = numpages,
1360 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1361 .mask_clr = __pgprot(0),
1365 * No alias checking needed for setting present flag. otherwise,
1366 * we may need to break large pages for 64-bit kernel text
1367 * mappings (this adds to complexity if we want to do this from
1368 * atomic context especially). Let's keep it simple!
1370 return __change_page_attr_set_clr(&cpa, 0);
1373 static int __set_pages_np(struct page *page, int numpages)
1375 unsigned long tempaddr = (unsigned long) page_address(page);
1376 struct cpa_data cpa = { .vaddr = &tempaddr,
1377 .numpages = numpages,
1378 .mask_set = __pgprot(0),
1379 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1383 * No alias checking needed for setting not present flag. otherwise,
1384 * we may need to break large pages for 64-bit kernel text
1385 * mappings (this adds to complexity if we want to do this from
1386 * atomic context especially). Let's keep it simple!
1388 return __change_page_attr_set_clr(&cpa, 0);
1391 void kernel_map_pages(struct page *page, int numpages, int enable)
1393 if (PageHighMem(page))
1396 debug_check_no_locks_freed(page_address(page),
1397 numpages * PAGE_SIZE);
1401 * The return value is ignored as the calls cannot fail.
1402 * Large pages for identity mappings are not used at boot time
1403 * and hence no memory allocations during large page split.
1406 __set_pages_p(page, numpages);
1408 __set_pages_np(page, numpages);
1411 * We should perform an IPI and flush all tlbs,
1412 * but that can deadlock->flush only current cpu:
1416 arch_flush_lazy_mmu_mode();
1419 #ifdef CONFIG_HIBERNATION
1421 bool kernel_page_present(struct page *page)
1426 if (PageHighMem(page))
1429 pte = lookup_address((unsigned long)page_address(page), &level);
1430 return (pte_val(*pte) & _PAGE_PRESENT);
1433 #endif /* CONFIG_HIBERNATION */
1435 #endif /* CONFIG_DEBUG_PAGEALLOC */
1438 * The testcases use internal knowledge of the implementation that shouldn't
1439 * be exposed to the rest of the kernel. Include these directly here.
1441 #ifdef CONFIG_CPA_DEBUG
1442 #include "pageattr-test.c"