4 * @remark Copyright 2002-2008 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
8 * @author Robert Richter <robert.richter@amd.com>
11 #include <linux/init.h>
12 #include <linux/notifier.h>
13 #include <linux/smp.h>
14 #include <linux/oprofile.h>
15 #include <linux/sysdev.h>
16 #include <linux/slab.h>
17 #include <linux/moduleparam.h>
18 #include <linux/kdebug.h>
23 #include "op_counter.h"
24 #include "op_x86_model.h"
26 static struct op_x86_model_spec const *model;
27 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
28 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
30 static int nmi_start(void);
31 static void nmi_stop(void);
33 /* 0 == registered but off, 1 == registered and on */
34 static int nmi_enabled = 0;
38 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
45 static int nmi_resume(struct sys_device *dev)
52 static struct sysdev_class oprofile_sysclass = {
55 .suspend = nmi_suspend,
58 static struct sys_device device_oprofile = {
60 .cls = &oprofile_sysclass,
63 static int __init init_sysfs(void)
67 error = sysdev_class_register(&oprofile_sysclass);
69 error = sysdev_register(&device_oprofile);
73 static void exit_sysfs(void)
75 sysdev_unregister(&device_oprofile);
76 sysdev_class_unregister(&oprofile_sysclass);
80 #define init_sysfs() do { } while (0)
81 #define exit_sysfs() do { } while (0)
82 #endif /* CONFIG_PM */
84 static int profile_exceptions_notify(struct notifier_block *self,
85 unsigned long val, void *data)
87 struct die_args *args = (struct die_args *)data;
88 int ret = NOTIFY_DONE;
89 int cpu = smp_processor_id();
93 if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
102 static void nmi_cpu_save_registers(struct op_msrs *msrs)
104 unsigned int const nr_ctrs = model->num_counters;
105 unsigned int const nr_ctrls = model->num_controls;
106 struct op_msr *counters = msrs->counters;
107 struct op_msr *controls = msrs->controls;
110 for (i = 0; i < nr_ctrs; ++i) {
111 if (counters[i].addr) {
112 rdmsr(counters[i].addr,
113 counters[i].saved.low,
114 counters[i].saved.high);
118 for (i = 0; i < nr_ctrls; ++i) {
119 if (controls[i].addr) {
120 rdmsr(controls[i].addr,
121 controls[i].saved.low,
122 controls[i].saved.high);
127 static void nmi_save_registers(void *dummy)
129 int cpu = smp_processor_id();
130 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
131 nmi_cpu_save_registers(msrs);
134 static void free_msrs(void)
137 for_each_possible_cpu(i) {
138 kfree(per_cpu(cpu_msrs, i).counters);
139 per_cpu(cpu_msrs, i).counters = NULL;
140 kfree(per_cpu(cpu_msrs, i).controls);
141 per_cpu(cpu_msrs, i).controls = NULL;
145 static int allocate_msrs(void)
148 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
149 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
152 for_each_possible_cpu(i) {
153 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
155 if (!per_cpu(cpu_msrs, i).counters) {
159 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
161 if (!per_cpu(cpu_msrs, i).controls) {
173 static void nmi_cpu_setup(void *dummy)
175 int cpu = smp_processor_id();
176 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
177 spin_lock(&oprofilefs_lock);
178 model->setup_ctrs(msrs);
179 spin_unlock(&oprofilefs_lock);
180 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
181 apic_write(APIC_LVTPC, APIC_DM_NMI);
184 static struct notifier_block profile_exceptions_nb = {
185 .notifier_call = profile_exceptions_notify,
190 static int nmi_setup(void)
195 if (!allocate_msrs())
198 err = register_die_notifier(&profile_exceptions_nb);
204 /* We need to serialize save and setup for HT because the subset
205 * of msrs are distinct for save and setup operations
208 /* Assume saved/restored counters are the same on all CPUs */
209 model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
210 for_each_possible_cpu(cpu) {
212 memcpy(per_cpu(cpu_msrs, cpu).counters,
213 per_cpu(cpu_msrs, 0).counters,
214 sizeof(struct op_msr) * model->num_counters);
216 memcpy(per_cpu(cpu_msrs, cpu).controls,
217 per_cpu(cpu_msrs, 0).controls,
218 sizeof(struct op_msr) * model->num_controls);
222 on_each_cpu(nmi_save_registers, NULL, 1);
223 on_each_cpu(nmi_cpu_setup, NULL, 1);
228 static void nmi_restore_registers(struct op_msrs *msrs)
230 unsigned int const nr_ctrs = model->num_counters;
231 unsigned int const nr_ctrls = model->num_controls;
232 struct op_msr *counters = msrs->counters;
233 struct op_msr *controls = msrs->controls;
236 for (i = 0; i < nr_ctrls; ++i) {
237 if (controls[i].addr) {
238 wrmsr(controls[i].addr,
239 controls[i].saved.low,
240 controls[i].saved.high);
244 for (i = 0; i < nr_ctrs; ++i) {
245 if (counters[i].addr) {
246 wrmsr(counters[i].addr,
247 counters[i].saved.low,
248 counters[i].saved.high);
253 static void nmi_cpu_shutdown(void *dummy)
256 int cpu = smp_processor_id();
257 struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
259 /* restoring APIC_LVTPC can trigger an apic error because the delivery
260 * mode and vector nr combination can be illegal. That's by design: on
261 * power on apic lvt contain a zero vector nr which are legal only for
262 * NMI delivery mode. So inhibit apic err before restoring lvtpc
264 v = apic_read(APIC_LVTERR);
265 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
266 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
267 apic_write(APIC_LVTERR, v);
268 nmi_restore_registers(msrs);
271 static void nmi_shutdown(void)
273 struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
275 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
276 unregister_die_notifier(&profile_exceptions_nb);
277 model->shutdown(msrs);
279 put_cpu_var(cpu_msrs);
282 static void nmi_cpu_start(void *dummy)
284 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
288 static int nmi_start(void)
290 on_each_cpu(nmi_cpu_start, NULL, 1);
294 static void nmi_cpu_stop(void *dummy)
296 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
300 static void nmi_stop(void)
302 on_each_cpu(nmi_cpu_stop, NULL, 1);
305 struct op_counter_config counter_config[OP_MAX_COUNTER];
307 static int nmi_create_files(struct super_block *sb, struct dentry *root)
311 for (i = 0; i < model->num_counters; ++i) {
315 /* quick little hack to _not_ expose a counter if it is not
316 * available for use. This should protect userspace app.
317 * NOTE: assumes 1:1 mapping here (that counters are organized
318 * sequentially in their struct assignment).
320 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
323 snprintf(buf, sizeof(buf), "%d", i);
324 dir = oprofilefs_mkdir(sb, root, buf);
325 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
326 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
327 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
328 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
329 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
330 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
337 module_param(p4force, int, 0);
339 static int __init p4_init(char **cpu_type)
341 __u8 cpu_model = boot_cpu_data.x86_model;
343 if (!p4force && (cpu_model > 6 || cpu_model == 5))
347 *cpu_type = "i386/p4";
351 switch (smp_num_siblings) {
353 *cpu_type = "i386/p4";
358 *cpu_type = "i386/p4-ht";
359 model = &op_p4_ht2_spec;
364 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
365 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
369 static int __init ppro_init(char **cpu_type)
371 __u8 cpu_model = boot_cpu_data.x86_model;
375 *cpu_type = "i386/ppro";
378 *cpu_type = "i386/pii";
381 *cpu_type = "i386/piii";
384 *cpu_type = "i386/p6_mobile";
387 *cpu_type = "i386/p6";
390 *cpu_type = "i386/core";
393 *cpu_type = "i386/core_2";
396 *cpu_type = "i386/core_2";
403 model = &op_ppro_spec;
407 /* in order to get sysfs right */
408 static int using_nmi;
410 int __init op_nmi_init(struct oprofile_operations *ops)
412 __u8 vendor = boot_cpu_data.x86_vendor;
413 __u8 family = boot_cpu_data.x86;
422 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
428 model = &op_amd_spec;
429 cpu_type = "i386/athlon";
432 model = &op_amd_spec;
433 /* Actually it could be i386/hammer too, but give
434 user space an consistent name. */
435 cpu_type = "x86-64/hammer";
438 model = &op_amd_spec;
439 cpu_type = "x86-64/family10";
442 model = &op_amd_spec;
443 cpu_type = "x86-64/family11h";
448 case X86_VENDOR_INTEL:
452 if (!p4_init(&cpu_type))
456 /* A P6-class processor */
458 if (!ppro_init(&cpu_type))
471 /* default values, can be overwritten by model */
472 ops->create_files = nmi_create_files;
473 ops->setup = nmi_setup;
474 ops->shutdown = nmi_shutdown;
475 ops->start = nmi_start;
476 ops->stop = nmi_stop;
477 ops->cpu_type = cpu_type;
480 ret = model->init(ops);
486 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
490 void op_nmi_exit(void)