4 * @remark Copyright 2002-2009 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
8 * @author Robert Richter <robert.richter@amd.com>
9 * @author Barry Kasindorf <barry.kasindorf@amd.com>
10 * @author Jason Yeh <jason.yeh@amd.com>
11 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
14 #include <linux/init.h>
15 #include <linux/notifier.h>
16 #include <linux/smp.h>
17 #include <linux/oprofile.h>
18 #include <linux/sysdev.h>
19 #include <linux/slab.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kdebug.h>
22 #include <linux/cpu.h>
27 #include "op_counter.h"
28 #include "op_x86_model.h"
30 static struct op_x86_model_spec *model;
31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
34 /* must be protected with get_online_cpus()/put_online_cpus(): */
35 static int nmi_enabled;
36 static int ctr_running;
38 struct op_counter_config counter_config[OP_MAX_COUNTER];
40 /* common functions */
42 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
43 struct op_counter_config *counter_config)
46 u16 event = (u16)counter_config->event;
48 val |= ARCH_PERFMON_EVENTSEL_INT;
49 val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
50 val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
51 val |= (counter_config->unit_mask & 0xFF) << 8;
52 event &= model->event_mask ? model->event_mask : 0xFF;
54 val |= (event & 0x0F00) << 24;
60 static int profile_exceptions_notify(struct notifier_block *self,
61 unsigned long val, void *data)
63 struct die_args *args = (struct die_args *)data;
64 int ret = NOTIFY_DONE;
69 model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs));
70 else if (!nmi_enabled)
73 model->stop(&__get_cpu_var(cpu_msrs));
82 static void nmi_cpu_save_registers(struct op_msrs *msrs)
84 struct op_msr *counters = msrs->counters;
85 struct op_msr *controls = msrs->controls;
88 for (i = 0; i < model->num_counters; ++i) {
90 rdmsrl(counters[i].addr, counters[i].saved);
93 for (i = 0; i < model->num_controls; ++i) {
95 rdmsrl(controls[i].addr, controls[i].saved);
99 static void nmi_cpu_start(void *dummy)
101 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
108 static int nmi_start(void)
111 on_each_cpu(nmi_cpu_start, NULL, 1);
117 static void nmi_cpu_stop(void *dummy)
119 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
126 static void nmi_stop(void)
129 on_each_cpu(nmi_cpu_stop, NULL, 1);
134 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
136 static DEFINE_PER_CPU(int, switch_index);
138 static inline int has_mux(void)
140 return !!model->switch_ctrl;
143 inline int op_x86_phys_to_virt(int phys)
145 return __this_cpu_read(switch_index) + phys;
148 inline int op_x86_virt_to_phys(int virt)
150 return virt % model->num_counters;
153 static void nmi_shutdown_mux(void)
160 for_each_possible_cpu(i) {
161 kfree(per_cpu(cpu_msrs, i).multiplex);
162 per_cpu(cpu_msrs, i).multiplex = NULL;
163 per_cpu(switch_index, i) = 0;
167 static int nmi_setup_mux(void)
169 size_t multiplex_size =
170 sizeof(struct op_msr) * model->num_virt_counters;
176 for_each_possible_cpu(i) {
177 per_cpu(cpu_msrs, i).multiplex =
178 kzalloc(multiplex_size, GFP_KERNEL);
179 if (!per_cpu(cpu_msrs, i).multiplex)
186 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
189 struct op_msr *multiplex = msrs->multiplex;
194 for (i = 0; i < model->num_virt_counters; ++i) {
195 if (counter_config[i].enabled) {
196 multiplex[i].saved = -(u64)counter_config[i].count;
198 multiplex[i].saved = 0;
202 per_cpu(switch_index, cpu) = 0;
205 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
207 struct op_msr *counters = msrs->counters;
208 struct op_msr *multiplex = msrs->multiplex;
211 for (i = 0; i < model->num_counters; ++i) {
212 int virt = op_x86_phys_to_virt(i);
213 if (counters[i].addr)
214 rdmsrl(counters[i].addr, multiplex[virt].saved);
218 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
220 struct op_msr *counters = msrs->counters;
221 struct op_msr *multiplex = msrs->multiplex;
224 for (i = 0; i < model->num_counters; ++i) {
225 int virt = op_x86_phys_to_virt(i);
226 if (counters[i].addr)
227 wrmsrl(counters[i].addr, multiplex[virt].saved);
231 static void nmi_cpu_switch(void *dummy)
233 int cpu = smp_processor_id();
234 int si = per_cpu(switch_index, cpu);
235 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
238 nmi_cpu_save_mpx_registers(msrs);
240 /* move to next set */
241 si += model->num_counters;
242 if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
243 per_cpu(switch_index, cpu) = 0;
245 per_cpu(switch_index, cpu) = si;
247 model->switch_ctrl(model, msrs);
248 nmi_cpu_restore_mpx_registers(msrs);
255 * Quick check to see if multiplexing is necessary.
256 * The check should be sufficient since counters are used
259 static int nmi_multiplex_on(void)
261 return counter_config[model->num_counters].count ? 0 : -EINVAL;
264 static int nmi_switch_event(void)
267 return -ENOSYS; /* not implemented */
268 if (nmi_multiplex_on() < 0)
269 return -EINVAL; /* not necessary */
273 on_each_cpu(nmi_cpu_switch, NULL, 1);
279 static inline void mux_init(struct oprofile_operations *ops)
282 ops->switch_events = nmi_switch_event;
285 static void mux_clone(int cpu)
290 memcpy(per_cpu(cpu_msrs, cpu).multiplex,
291 per_cpu(cpu_msrs, 0).multiplex,
292 sizeof(struct op_msr) * model->num_virt_counters);
297 inline int op_x86_phys_to_virt(int phys) { return phys; }
298 inline int op_x86_virt_to_phys(int virt) { return virt; }
299 static inline void nmi_shutdown_mux(void) { }
300 static inline int nmi_setup_mux(void) { return 1; }
302 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
303 static inline void mux_init(struct oprofile_operations *ops) { }
304 static void mux_clone(int cpu) { }
308 static void free_msrs(void)
311 for_each_possible_cpu(i) {
312 kfree(per_cpu(cpu_msrs, i).counters);
313 per_cpu(cpu_msrs, i).counters = NULL;
314 kfree(per_cpu(cpu_msrs, i).controls);
315 per_cpu(cpu_msrs, i).controls = NULL;
320 static int allocate_msrs(void)
322 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
323 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
326 for_each_possible_cpu(i) {
327 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
329 if (!per_cpu(cpu_msrs, i).counters)
331 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
333 if (!per_cpu(cpu_msrs, i).controls)
337 if (!nmi_setup_mux())
347 static void nmi_cpu_setup(void *dummy)
349 int cpu = smp_processor_id();
350 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
351 nmi_cpu_save_registers(msrs);
352 spin_lock(&oprofilefs_lock);
353 model->setup_ctrs(model, msrs);
354 nmi_cpu_setup_mux(cpu, msrs);
355 spin_unlock(&oprofilefs_lock);
356 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
357 apic_write(APIC_LVTPC, APIC_DM_NMI);
360 static struct notifier_block profile_exceptions_nb = {
361 .notifier_call = profile_exceptions_notify,
363 .priority = NMI_LOCAL_LOW_PRIOR,
366 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
368 struct op_msr *counters = msrs->counters;
369 struct op_msr *controls = msrs->controls;
372 for (i = 0; i < model->num_controls; ++i) {
373 if (controls[i].addr)
374 wrmsrl(controls[i].addr, controls[i].saved);
377 for (i = 0; i < model->num_counters; ++i) {
378 if (counters[i].addr)
379 wrmsrl(counters[i].addr, counters[i].saved);
383 static void nmi_cpu_shutdown(void *dummy)
386 int cpu = smp_processor_id();
387 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
389 /* restoring APIC_LVTPC can trigger an apic error because the delivery
390 * mode and vector nr combination can be illegal. That's by design: on
391 * power on apic lvt contain a zero vector nr which are legal only for
392 * NMI delivery mode. So inhibit apic err before restoring lvtpc
394 v = apic_read(APIC_LVTERR);
395 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
396 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
397 apic_write(APIC_LVTERR, v);
398 nmi_cpu_restore_registers(msrs);
403 static void nmi_cpu_up(void *dummy)
406 nmi_cpu_setup(dummy);
408 nmi_cpu_start(dummy);
411 static void nmi_cpu_down(void *dummy)
416 nmi_cpu_shutdown(dummy);
419 static int nmi_create_files(struct super_block *sb, struct dentry *root)
423 for (i = 0; i < model->num_virt_counters; ++i) {
427 /* quick little hack to _not_ expose a counter if it is not
428 * available for use. This should protect userspace app.
429 * NOTE: assumes 1:1 mapping here (that counters are organized
430 * sequentially in their struct assignment).
432 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
435 snprintf(buf, sizeof(buf), "%d", i);
436 dir = oprofilefs_mkdir(sb, root, buf);
437 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
438 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
439 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
440 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
441 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
442 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
448 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
451 int cpu = (unsigned long)data;
453 case CPU_DOWN_FAILED:
455 smp_call_function_single(cpu, nmi_cpu_up, NULL, 0);
457 case CPU_DOWN_PREPARE:
458 smp_call_function_single(cpu, nmi_cpu_down, NULL, 1);
464 static struct notifier_block oprofile_cpu_nb = {
465 .notifier_call = oprofile_cpu_notifier
468 static int nmi_setup(void)
473 if (!allocate_msrs())
476 /* We need to serialize save and setup for HT because the subset
477 * of msrs are distinct for save and setup operations
480 /* Assume saved/restored counters are the same on all CPUs */
481 err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
485 for_each_possible_cpu(cpu) {
489 memcpy(per_cpu(cpu_msrs, cpu).counters,
490 per_cpu(cpu_msrs, 0).counters,
491 sizeof(struct op_msr) * model->num_counters);
493 memcpy(per_cpu(cpu_msrs, cpu).controls,
494 per_cpu(cpu_msrs, 0).controls,
495 sizeof(struct op_msr) * model->num_controls);
503 err = register_die_notifier(&profile_exceptions_nb);
508 register_cpu_notifier(&oprofile_cpu_nb);
509 on_each_cpu(nmi_cpu_setup, NULL, 1);
519 static void nmi_shutdown(void)
521 struct op_msrs *msrs;
524 unregister_cpu_notifier(&oprofile_cpu_nb);
525 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
530 unregister_die_notifier(&profile_exceptions_nb);
531 msrs = &get_cpu_var(cpu_msrs);
532 model->shutdown(msrs);
534 put_cpu_var(cpu_msrs);
539 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
541 /* Only one CPU left, just stop that one */
542 if (nmi_enabled == 1)
547 static int nmi_resume(struct sys_device *dev)
549 if (nmi_enabled == 1)
554 static struct sysdev_class oprofile_sysclass = {
556 .resume = nmi_resume,
557 .suspend = nmi_suspend,
560 static struct sys_device device_oprofile = {
562 .cls = &oprofile_sysclass,
565 static int __init init_sysfs(void)
569 error = sysdev_class_register(&oprofile_sysclass);
573 error = sysdev_register(&device_oprofile);
575 sysdev_class_unregister(&oprofile_sysclass);
580 static void exit_sysfs(void)
582 sysdev_unregister(&device_oprofile);
583 sysdev_class_unregister(&oprofile_sysclass);
588 static inline int init_sysfs(void) { return 0; }
589 static inline void exit_sysfs(void) { }
591 #endif /* CONFIG_PM */
593 static int __init p4_init(char **cpu_type)
595 __u8 cpu_model = boot_cpu_data.x86_model;
597 if (cpu_model > 6 || cpu_model == 5)
601 *cpu_type = "i386/p4";
605 switch (smp_num_siblings) {
607 *cpu_type = "i386/p4";
612 *cpu_type = "i386/p4-ht";
613 model = &op_p4_ht2_spec;
618 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
619 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
623 static int force_arch_perfmon;
624 static int force_cpu_type(const char *str, struct kernel_param *kp)
626 if (!strcmp(str, "arch_perfmon")) {
627 force_arch_perfmon = 1;
628 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
633 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
635 static int __init ppro_init(char **cpu_type)
637 __u8 cpu_model = boot_cpu_data.x86_model;
638 struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
640 if (force_arch_perfmon && cpu_has_arch_perfmon)
644 * Documentation on identifying Intel processors by CPU family
645 * and model can be found in the Intel Software Developer's
648 * http://www.intel.com/products/processor/manuals/
650 * As of May 2010 the documentation for this was in the:
651 * "Intel 64 and IA-32 Architectures Software Developer's
652 * Manual Volume 3B: System Programming Guide", "Table B-1
653 * CPUID Signature Values of DisplayFamily_DisplayModel".
657 *cpu_type = "i386/ppro";
660 *cpu_type = "i386/pii";
664 *cpu_type = "i386/piii";
668 *cpu_type = "i386/p6_mobile";
671 *cpu_type = "i386/core";
677 *cpu_type = "i386/core_2";
682 spec = &op_arch_perfmon_spec;
683 *cpu_type = "i386/core_i7";
686 *cpu_type = "i386/atom";
697 int __init op_nmi_init(struct oprofile_operations *ops)
699 __u8 vendor = boot_cpu_data.x86_vendor;
700 __u8 family = boot_cpu_data.x86;
701 char *cpu_type = NULL;
709 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
713 cpu_type = "i386/athlon";
717 * Actually it could be i386/hammer too, but
718 * give user space an consistent name.
720 cpu_type = "x86-64/hammer";
723 cpu_type = "x86-64/family10";
726 cpu_type = "x86-64/family11h";
729 cpu_type = "x86-64/family12h";
732 cpu_type = "x86-64/family14h";
735 cpu_type = "x86-64/family15h";
740 model = &op_amd_spec;
743 case X86_VENDOR_INTEL:
750 /* A P6-class processor */
752 ppro_init(&cpu_type);
762 if (!cpu_has_arch_perfmon)
765 /* use arch perfmon as fallback */
766 cpu_type = "i386/arch_perfmon";
767 model = &op_arch_perfmon_spec;
774 /* default values, can be overwritten by model */
775 ops->create_files = nmi_create_files;
776 ops->setup = nmi_setup;
777 ops->shutdown = nmi_shutdown;
778 ops->start = nmi_start;
779 ops->stop = nmi_stop;
780 ops->cpu_type = cpu_type;
783 ret = model->init(ops);
787 if (!model->num_virt_counters)
788 model->num_virt_counters = model->num_counters;
796 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
800 void op_nmi_exit(void)