arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* 0 == registered but off, 1 == registered and on */
  35 static int nmi_enabled = 0;
  36
  37
  38 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  39 extern atomic_t multiplex_counter;
  40 #endif
  41
  42 struct op_counter_config counter_config[OP_MAX_COUNTER];
  43
  44 /* common functions */
  45
  46 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  47                     struct op_counter_config *counter_config)
  48 {
  49         u64 val = 0;
  50         u16 event = (u16)counter_config->event;
  51
  52         val |= ARCH_PERFMON_EVENTSEL_INT;
  53         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  54         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  55         val |= (counter_config->unit_mask & 0xFF) << 8;
  56         event &= model->event_mask ? model->event_mask : 0xFF;
  57         val |= event & 0xFF;
  58         val |= (event & 0x0F00) << 24;
  59
  60         return val;
  61 }
  62
  63
  64 static int profile_exceptions_notify(struct notifier_block *self,
  65                                      unsigned long val, void *data)
  66 {
  67         struct die_args *args = (struct die_args *)data;
  68         int ret = NOTIFY_DONE;
  69         int cpu = smp_processor_id();
  70
  71         switch (val) {
  72         case DIE_NMI:
  73         case DIE_NMI_IPI:
  74                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  75                 ret = NOTIFY_STOP;
  76                 break;
  77         default:
  78                 break;
  79         }
  80         return ret;
  81 }
  82
  83 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  84 {
  85         struct op_msr *counters = msrs->counters;
  86         struct op_msr *controls = msrs->controls;
  87         unsigned int i;
  88
  89         for (i = 0; i < model->num_counters; ++i) {
  90                 if (counters[i].addr)
  91                         rdmsrl(counters[i].addr, counters[i].saved);
  92         }
  93
  94         for (i = 0; i < model->num_controls; ++i) {
  95                 if (controls[i].addr)
  96                         rdmsrl(controls[i].addr, controls[i].saved);
  97         }
  98 }
  99
 100 static void nmi_cpu_start(void *dummy)
 101 {
 102         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 103         model->start(msrs);
 104 }
 105
 106 static int nmi_start(void)
 107 {
 108         on_each_cpu(nmi_cpu_start, NULL, 1);
 109         return 0;
 110 }
 111
 112 static void nmi_cpu_stop(void *dummy)
 113 {
 114         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 115         model->stop(msrs);
 116 }
 117
 118 static void nmi_stop(void)
 119 {
 120         on_each_cpu(nmi_cpu_stop, NULL, 1);
 121 }
 122
 123 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 124
 125 static DEFINE_PER_CPU(int, switch_index);
 126
 127 static inline int has_mux(void)
 128 {
 129         return !!model->switch_ctrl;
 130 }
 131
 132 inline int op_x86_phys_to_virt(int phys)
 133 {
 134         return __get_cpu_var(switch_index) + phys;
 135 }
 136
 137 static void nmi_shutdown_mux(void)
 138 {
 139         int i;
 140
 141         if (!has_mux())
 142                 return;
 143
 144         for_each_possible_cpu(i) {
 145                 kfree(per_cpu(cpu_msrs, i).multiplex);
 146                 per_cpu(cpu_msrs, i).multiplex = NULL;
 147                 per_cpu(switch_index, i) = 0;
 148         }
 149 }
 150
 151 static int nmi_setup_mux(void)
 152 {
 153         size_t multiplex_size =
 154                 sizeof(struct op_msr) * model->num_virt_counters;
 155         int i;
 156
 157         if (!has_mux())
 158                 return 1;
 159
 160         for_each_possible_cpu(i) {
 161                 per_cpu(cpu_msrs, i).multiplex =
 162                         kmalloc(multiplex_size, GFP_KERNEL);
 163                 if (!per_cpu(cpu_msrs, i).multiplex)
 164                         return 0;
 165         }
 166
 167         return 1;
 168 }
 169
 170 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 171 {
 172         int i;
 173         struct op_msr *multiplex = msrs->multiplex;
 174
 175         if (!has_mux())
 176                 return;
 177
 178         for (i = 0; i < model->num_virt_counters; ++i) {
 179                 if (counter_config[i].enabled) {
 180                         multiplex[i].saved = -(u64)counter_config[i].count;
 181                 } else {
 182                         multiplex[i].addr  = 0;
 183                         multiplex[i].saved = 0;
 184                 }
 185         }
 186
 187         per_cpu(switch_index, cpu) = 0;
 188 }
 189
 190 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 191 {
 192         struct op_msr *multiplex = msrs->multiplex;
 193         int i;
 194
 195         for (i = 0; i < model->num_counters; ++i) {
 196                 int virt = op_x86_phys_to_virt(i);
 197                 if (multiplex[virt].addr)
 198                         rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
 199         }
 200 }
 201
 202 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 203 {
 204         struct op_msr *multiplex = msrs->multiplex;
 205         int i;
 206
 207         for (i = 0; i < model->num_counters; ++i) {
 208                 int virt = op_x86_phys_to_virt(i);
 209                 if (multiplex[virt].addr)
 210                         wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
 211         }
 212 }
 213
 214 static void nmi_cpu_switch(void *dummy)
 215 {
 216         int cpu = smp_processor_id();
 217         int si = per_cpu(switch_index, cpu);
 218         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 219
 220         nmi_cpu_stop(NULL);
 221         nmi_cpu_save_mpx_registers(msrs);
 222
 223         /* move to next set */
 224         si += model->num_counters;
 225         if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
 226                 per_cpu(switch_index, cpu) = 0;
 227         else
 228                 per_cpu(switch_index, cpu) = si;
 229
 230         model->switch_ctrl(model, msrs);
 231         nmi_cpu_restore_mpx_registers(msrs);
 232
 233         nmi_cpu_start(NULL);
 234 }
 235
 236
 237 /*
 238  * Quick check to see if multiplexing is necessary.
 239  * The check should be sufficient since counters are used
 240  * in ordre.
 241  */
 242 static int nmi_multiplex_on(void)
 243 {
 244         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 245 }
 246
 247 static int nmi_switch_event(void)
 248 {
 249         if (!has_mux())
 250                 return -ENOSYS;         /* not implemented */
 251         if (nmi_multiplex_on() < 0)
 252                 return -EINVAL;         /* not necessary */
 253
 254         on_each_cpu(nmi_cpu_switch, NULL, 1);
 255
 256         atomic_inc(&multiplex_counter);
 257
 258         return 0;
 259 }
 260
 261 static inline void mux_init(struct oprofile_operations *ops)
 262 {
 263         if (has_mux())
 264                 ops->switch_events = nmi_switch_event;
 265 }
 266
 267 #else
 268
 269 inline int op_x86_phys_to_virt(int phys) { return phys; }
 270 static inline void nmi_shutdown_mux(void) { }
 271 static inline int nmi_setup_mux(void) { return 1; }
 272 static inline void
 273 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 274 static inline void mux_init(struct oprofile_operations *ops) { }
 275
 276 #endif
 277
 278 static void free_msrs(void)
 279 {
 280         int i;
 281         for_each_possible_cpu(i) {
 282                 kfree(per_cpu(cpu_msrs, i).counters);
 283                 per_cpu(cpu_msrs, i).counters = NULL;
 284                 kfree(per_cpu(cpu_msrs, i).controls);
 285                 per_cpu(cpu_msrs, i).controls = NULL;
 286         }
 287 }
 288
 289 static int allocate_msrs(void)
 290 {
 291         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 292         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 293
 294         int i;
 295         for_each_possible_cpu(i) {
 296                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 297                                                         GFP_KERNEL);
 298                 if (!per_cpu(cpu_msrs, i).counters)
 299                         return 0;
 300                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 301                                                         GFP_KERNEL);
 302                 if (!per_cpu(cpu_msrs, i).controls)
 303                         return 0;
 304         }
 305
 306         return 1;
 307 }
 308
 309 static void nmi_cpu_setup(void *dummy)
 310 {
 311         int cpu = smp_processor_id();
 312         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 313         nmi_cpu_save_registers(msrs);
 314         spin_lock(&oprofilefs_lock);
 315         model->setup_ctrs(model, msrs);
 316         nmi_cpu_setup_mux(cpu, msrs);
 317         spin_unlock(&oprofilefs_lock);
 318         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 319         apic_write(APIC_LVTPC, APIC_DM_NMI);
 320 }
 321
 322 static struct notifier_block profile_exceptions_nb = {
 323         .notifier_call = profile_exceptions_notify,
 324         .next = NULL,
 325         .priority = 2
 326 };
 327
 328 static int nmi_setup(void)
 329 {
 330         int err = 0;
 331         int cpu;
 332
 333         if (!allocate_msrs())
 334                 err = -ENOMEM;
 335         else if (!nmi_setup_mux())
 336                 err = -ENOMEM;
 337         else
 338                 err = register_die_notifier(&profile_exceptions_nb);
 339
 340         if (err) {
 341                 free_msrs();
 342                 nmi_shutdown_mux();
 343                 return err;
 344         }
 345
 346         /* We need to serialize save and setup for HT because the subset
 347          * of msrs are distinct for save and setup operations
 348          */
 349
 350         /* Assume saved/restored counters are the same on all CPUs */
 351         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 352         for_each_possible_cpu(cpu) {
 353                 if (cpu != 0) {
 354                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 355                                 per_cpu(cpu_msrs, 0).counters,
 356                                 sizeof(struct op_msr) * model->num_counters);
 357
 358                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 359                                 per_cpu(cpu_msrs, 0).controls,
 360                                 sizeof(struct op_msr) * model->num_controls);
 361 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 362                         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 363                                 per_cpu(cpu_msrs, 0).multiplex,
 364                                 sizeof(struct op_msr) * model->num_virt_counters);
 365 #endif
 366                 }
 367         }
 368         on_each_cpu(nmi_cpu_setup, NULL, 1);
 369         nmi_enabled = 1;
 370         return 0;
 371 }
 372
 373 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 374 {
 375         struct op_msr *counters = msrs->counters;
 376         struct op_msr *controls = msrs->controls;
 377         unsigned int i;
 378
 379         for (i = 0; i < model->num_controls; ++i) {
 380                 if (controls[i].addr)
 381                         wrmsrl(controls[i].addr, controls[i].saved);
 382         }
 383
 384         for (i = 0; i < model->num_counters; ++i) {
 385                 if (counters[i].addr)
 386                         wrmsrl(counters[i].addr, counters[i].saved);
 387         }
 388 }
 389
 390 static void nmi_cpu_shutdown(void *dummy)
 391 {
 392         unsigned int v;
 393         int cpu = smp_processor_id();
 394         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 395
 396         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 397          * mode and vector nr combination can be illegal. That's by design: on
 398          * power on apic lvt contain a zero vector nr which are legal only for
 399          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 400          */
 401         v = apic_read(APIC_LVTERR);
 402         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 403         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 404         apic_write(APIC_LVTERR, v);
 405         nmi_cpu_restore_registers(msrs);
 406 }
 407
 408 static void nmi_shutdown(void)
 409 {
 410         struct op_msrs *msrs;
 411
 412         nmi_enabled = 0;
 413         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 414         unregister_die_notifier(&profile_exceptions_nb);
 415         nmi_shutdown_mux();
 416         msrs = &get_cpu_var(cpu_msrs);
 417         model->shutdown(msrs);
 418         free_msrs();
 419         put_cpu_var(cpu_msrs);
 420 }
 421
 422 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 423 {
 424         unsigned int i;
 425
 426         for (i = 0; i < model->num_virt_counters; ++i) {
 427                 struct dentry *dir;
 428                 char buf[4];
 429
 430 #ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
 431                 /* quick little hack to _not_ expose a counter if it is not
 432                  * available for use.  This should protect userspace app.
 433                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 434                  *        sequentially in their struct assignment).
 435                  */
 436                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 437                         continue;
 438 #endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
 439
 440                 snprintf(buf,  sizeof(buf), "%d", i);
 441                 dir = oprofilefs_mkdir(sb, root, buf);
 442                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 443                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 444                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 445                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 446                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 447                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 448         }
 449
 450         return 0;
 451 }
 452
 453 #ifdef CONFIG_SMP
 454 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 455                                  void *data)
 456 {
 457         int cpu = (unsigned long)data;
 458         switch (action) {
 459         case CPU_DOWN_FAILED:
 460         case CPU_ONLINE:
 461                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 462                 break;
 463         case CPU_DOWN_PREPARE:
 464                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 465                 break;
 466         }
 467         return NOTIFY_DONE;
 468 }
 469
 470 static struct notifier_block oprofile_cpu_nb = {
 471         .notifier_call = oprofile_cpu_notifier
 472 };
 473 #endif
 474
 475 #ifdef CONFIG_PM
 476
 477 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 478 {
 479         /* Only one CPU left, just stop that one */
 480         if (nmi_enabled == 1)
 481                 nmi_cpu_stop(NULL);
 482         return 0;
 483 }
 484
 485 static int nmi_resume(struct sys_device *dev)
 486 {
 487         if (nmi_enabled == 1)
 488                 nmi_cpu_start(NULL);
 489         return 0;
 490 }
 491
 492 static struct sysdev_class oprofile_sysclass = {
 493         .name           = "oprofile",
 494         .resume         = nmi_resume,
 495         .suspend        = nmi_suspend,
 496 };
 497
 498 static struct sys_device device_oprofile = {
 499         .id     = 0,
 500         .cls    = &oprofile_sysclass,
 501 };
 502
 503 static int __init init_sysfs(void)
 504 {
 505         int error;
 506
 507         error = sysdev_class_register(&oprofile_sysclass);
 508         if (!error)
 509                 error = sysdev_register(&device_oprofile);
 510         return error;
 511 }
 512
 513 static void exit_sysfs(void)
 514 {
 515         sysdev_unregister(&device_oprofile);
 516         sysdev_class_unregister(&oprofile_sysclass);
 517 }
 518
 519 #else
 520 #define init_sysfs() do { } while (0)
 521 #define exit_sysfs() do { } while (0)
 522 #endif /* CONFIG_PM */
 523
 524 static int __init p4_init(char **cpu_type)
 525 {
 526         __u8 cpu_model = boot_cpu_data.x86_model;
 527
 528         if (cpu_model > 6 || cpu_model == 5)
 529                 return 0;
 530
 531 #ifndef CONFIG_SMP
 532         *cpu_type = "i386/p4";
 533         model = &op_p4_spec;
 534         return 1;
 535 #else
 536         switch (smp_num_siblings) {
 537         case 1:
 538                 *cpu_type = "i386/p4";
 539                 model = &op_p4_spec;
 540                 return 1;
 541
 542         case 2:
 543                 *cpu_type = "i386/p4-ht";
 544                 model = &op_p4_ht2_spec;
 545                 return 1;
 546         }
 547 #endif
 548
 549         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 550         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 551         return 0;
 552 }
 553
 554 static int force_arch_perfmon;
 555 static int force_cpu_type(const char *str, struct kernel_param *kp)
 556 {
 557         if (!strcmp(str, "arch_perfmon")) {
 558                 force_arch_perfmon = 1;
 559                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 560         }
 561
 562         return 0;
 563 }
 564 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 565
 566 static int __init ppro_init(char **cpu_type)
 567 {
 568         __u8 cpu_model = boot_cpu_data.x86_model;
 569         struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
 570
 571         if (force_arch_perfmon && cpu_has_arch_perfmon)
 572                 return 0;
 573
 574         switch (cpu_model) {
 575         case 0 ... 2:
 576                 *cpu_type = "i386/ppro";
 577                 break;
 578         case 3 ... 5:
 579                 *cpu_type = "i386/pii";
 580                 break;
 581         case 6 ... 8:
 582         case 10 ... 11:
 583                 *cpu_type = "i386/piii";
 584                 break;
 585         case 9:
 586         case 13:
 587                 *cpu_type = "i386/p6_mobile";
 588                 break;
 589         case 14:
 590                 *cpu_type = "i386/core";
 591                 break;
 592         case 15: case 23:
 593                 *cpu_type = "i386/core_2";
 594                 break;
 595         case 26:
 596                 spec = &op_arch_perfmon_spec;
 597                 *cpu_type = "i386/core_i7";
 598                 break;
 599         case 28:
 600                 *cpu_type = "i386/atom";
 601                 break;
 602         default:
 603                 /* Unknown */
 604                 return 0;
 605         }
 606
 607         model = spec;
 608         return 1;
 609 }
 610
 611 /* in order to get sysfs right */
 612 static int using_nmi;
 613
 614 int __init op_nmi_init(struct oprofile_operations *ops)
 615 {
 616         __u8 vendor = boot_cpu_data.x86_vendor;
 617         __u8 family = boot_cpu_data.x86;
 618         char *cpu_type = NULL;
 619         int ret = 0;
 620
 621         if (!cpu_has_apic)
 622                 return -ENODEV;
 623
 624         switch (vendor) {
 625         case X86_VENDOR_AMD:
 626                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 627
 628                 switch (family) {
 629                 case 6:
 630                         cpu_type = "i386/athlon";
 631                         break;
 632                 case 0xf:
 633                         /*
 634                          * Actually it could be i386/hammer too, but
 635                          * give user space an consistent name.
 636                          */
 637                         cpu_type = "x86-64/hammer";
 638                         break;
 639                 case 0x10:
 640                         cpu_type = "x86-64/family10";
 641                         break;
 642                 case 0x11:
 643                         cpu_type = "x86-64/family11h";
 644                         break;
 645                 default:
 646                         return -ENODEV;
 647                 }
 648                 model = &op_amd_spec;
 649                 break;
 650
 651         case X86_VENDOR_INTEL:
 652                 switch (family) {
 653                         /* Pentium IV */
 654                 case 0xf:
 655                         p4_init(&cpu_type);
 656                         break;
 657
 658                         /* A P6-class processor */
 659                 case 6:
 660                         ppro_init(&cpu_type);
 661                         break;
 662
 663                 default:
 664                         break;
 665                 }
 666
 667                 if (cpu_type)
 668                         break;
 669
 670                 if (!cpu_has_arch_perfmon)
 671                         return -ENODEV;
 672
 673                 /* use arch perfmon as fallback */
 674                 cpu_type = "i386/arch_perfmon";
 675                 model = &op_arch_perfmon_spec;
 676                 break;
 677
 678         default:
 679                 return -ENODEV;
 680         }
 681
 682 #ifdef CONFIG_SMP
 683         register_cpu_notifier(&oprofile_cpu_nb);
 684 #endif
 685         /* default values, can be overwritten by model */
 686         ops->create_files       = nmi_create_files;
 687         ops->setup              = nmi_setup;
 688         ops->shutdown           = nmi_shutdown;
 689         ops->start              = nmi_start;
 690         ops->stop               = nmi_stop;
 691         ops->cpu_type           = cpu_type;
 692
 693         if (model->init)
 694                 ret = model->init(ops);
 695         if (ret)
 696                 return ret;
 697
 698         if (!model->num_virt_counters)
 699                 model->num_virt_counters = model->num_counters;
 700
 701         mux_init(ops);
 702
 703         init_sysfs();
 704         using_nmi = 1;
 705         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 706         return 0;
 707 }
 708
 709 void op_nmi_exit(void)
 710 {
 711         if (using_nmi) {
 712                 exit_sysfs();
 713 #ifdef CONFIG_SMP
 714                 unregister_cpu_notifier(&oprofile_cpu_nb);
 715 #endif
 716         }
 717         if (model->exit)
 718                 model->exit();
 719 }