4 * @remark Copyright 2002 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
10 #include <linux/init.h>
11 #include <linux/notifier.h>
12 #include <linux/smp.h>
13 #include <linux/oprofile.h>
14 #include <linux/sysdev.h>
15 #include <linux/slab.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kdebug.h>
22 #include "op_counter.h"
23 #include "op_x86_model.h"
25 static struct op_x86_model_spec const *model;
26 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
27 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
29 static int nmi_start(void);
30 static void nmi_stop(void);
32 /* 0 == registered but off, 1 == registered and on */
33 static int nmi_enabled = 0;
37 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
44 static int nmi_resume(struct sys_device *dev)
51 static struct sysdev_class oprofile_sysclass = {
54 .suspend = nmi_suspend,
57 static struct sys_device device_oprofile = {
59 .cls = &oprofile_sysclass,
62 static int __init init_sysfs(void)
66 error = sysdev_class_register(&oprofile_sysclass);
68 error = sysdev_register(&device_oprofile);
72 static void exit_sysfs(void)
74 sysdev_unregister(&device_oprofile);
75 sysdev_class_unregister(&oprofile_sysclass);
79 #define init_sysfs() do { } while (0)
80 #define exit_sysfs() do { } while (0)
81 #endif /* CONFIG_PM */
83 static int profile_exceptions_notify(struct notifier_block *self,
84 unsigned long val, void *data)
86 struct die_args *args = (struct die_args *)data;
87 int ret = NOTIFY_DONE;
88 int cpu = smp_processor_id();
92 if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
101 static void nmi_cpu_save_registers(struct op_msrs *msrs)
103 unsigned int const nr_ctrs = model->num_counters;
104 unsigned int const nr_ctrls = model->num_controls;
105 struct op_msr *counters = msrs->counters;
106 struct op_msr *controls = msrs->controls;
109 for (i = 0; i < nr_ctrs; ++i) {
110 if (counters[i].addr) {
111 rdmsr(counters[i].addr,
112 counters[i].saved.low,
113 counters[i].saved.high);
117 for (i = 0; i < nr_ctrls; ++i) {
118 if (controls[i].addr) {
119 rdmsr(controls[i].addr,
120 controls[i].saved.low,
121 controls[i].saved.high);
126 static void nmi_save_registers(void *dummy)
128 int cpu = smp_processor_id();
129 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
130 nmi_cpu_save_registers(msrs);
133 static void free_msrs(void)
136 for_each_possible_cpu(i) {
137 kfree(per_cpu(cpu_msrs, i).counters);
138 per_cpu(cpu_msrs, i).counters = NULL;
139 kfree(per_cpu(cpu_msrs, i).controls);
140 per_cpu(cpu_msrs, i).controls = NULL;
144 static int allocate_msrs(void)
147 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
148 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
151 for_each_possible_cpu(i) {
152 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
154 if (!per_cpu(cpu_msrs, i).counters) {
158 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
160 if (!per_cpu(cpu_msrs, i).controls) {
172 static void nmi_cpu_setup(void *dummy)
174 int cpu = smp_processor_id();
175 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
176 spin_lock(&oprofilefs_lock);
177 model->setup_ctrs(msrs);
178 spin_unlock(&oprofilefs_lock);
179 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
180 apic_write(APIC_LVTPC, APIC_DM_NMI);
183 static struct notifier_block profile_exceptions_nb = {
184 .notifier_call = profile_exceptions_notify,
189 static int nmi_setup(void)
194 if (!allocate_msrs())
197 err = register_die_notifier(&profile_exceptions_nb);
203 /* We need to serialize save and setup for HT because the subset
204 * of msrs are distinct for save and setup operations
207 /* Assume saved/restored counters are the same on all CPUs */
208 model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
209 for_each_possible_cpu(cpu) {
211 memcpy(per_cpu(cpu_msrs, cpu).counters,
212 per_cpu(cpu_msrs, 0).counters,
213 sizeof(struct op_msr) * model->num_counters);
215 memcpy(per_cpu(cpu_msrs, cpu).controls,
216 per_cpu(cpu_msrs, 0).controls,
217 sizeof(struct op_msr) * model->num_controls);
221 on_each_cpu(nmi_save_registers, NULL, 1);
222 on_each_cpu(nmi_cpu_setup, NULL, 1);
227 static void nmi_restore_registers(struct op_msrs *msrs)
229 unsigned int const nr_ctrs = model->num_counters;
230 unsigned int const nr_ctrls = model->num_controls;
231 struct op_msr *counters = msrs->counters;
232 struct op_msr *controls = msrs->controls;
235 for (i = 0; i < nr_ctrls; ++i) {
236 if (controls[i].addr) {
237 wrmsr(controls[i].addr,
238 controls[i].saved.low,
239 controls[i].saved.high);
243 for (i = 0; i < nr_ctrs; ++i) {
244 if (counters[i].addr) {
245 wrmsr(counters[i].addr,
246 counters[i].saved.low,
247 counters[i].saved.high);
252 static void nmi_cpu_shutdown(void *dummy)
255 int cpu = smp_processor_id();
256 struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
258 /* restoring APIC_LVTPC can trigger an apic error because the delivery
259 * mode and vector nr combination can be illegal. That's by design: on
260 * power on apic lvt contain a zero vector nr which are legal only for
261 * NMI delivery mode. So inhibit apic err before restoring lvtpc
263 v = apic_read(APIC_LVTERR);
264 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
265 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
266 apic_write(APIC_LVTERR, v);
267 nmi_restore_registers(msrs);
270 static void nmi_shutdown(void)
272 struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
274 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
275 unregister_die_notifier(&profile_exceptions_nb);
276 model->shutdown(msrs);
278 put_cpu_var(cpu_msrs);
281 static void nmi_cpu_start(void *dummy)
283 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
287 static int nmi_start(void)
289 on_each_cpu(nmi_cpu_start, NULL, 1);
293 static void nmi_cpu_stop(void *dummy)
295 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
299 static void nmi_stop(void)
301 on_each_cpu(nmi_cpu_stop, NULL, 1);
304 struct op_counter_config counter_config[OP_MAX_COUNTER];
306 static int nmi_create_files(struct super_block *sb, struct dentry *root)
310 for (i = 0; i < model->num_counters; ++i) {
314 /* quick little hack to _not_ expose a counter if it is not
315 * available for use. This should protect userspace app.
316 * NOTE: assumes 1:1 mapping here (that counters are organized
317 * sequentially in their struct assignment).
319 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
322 snprintf(buf, sizeof(buf), "%d", i);
323 dir = oprofilefs_mkdir(sb, root, buf);
324 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
325 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
326 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
327 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
328 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
329 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
336 module_param(p4force, int, 0);
338 static int __init p4_init(char **cpu_type)
340 __u8 cpu_model = boot_cpu_data.x86_model;
342 if (!p4force && (cpu_model > 6 || cpu_model == 5))
346 *cpu_type = "i386/p4";
350 switch (smp_num_siblings) {
352 *cpu_type = "i386/p4";
357 *cpu_type = "i386/p4-ht";
358 model = &op_p4_ht2_spec;
363 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
364 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
368 static int __init ppro_init(char **cpu_type)
370 __u8 cpu_model = boot_cpu_data.x86_model;
374 *cpu_type = "i386/ppro";
377 *cpu_type = "i386/pii";
380 *cpu_type = "i386/piii";
383 *cpu_type = "i386/p6_mobile";
386 *cpu_type = "i386/p6";
389 *cpu_type = "i386/core";
392 *cpu_type = "i386/core_2";
395 *cpu_type = "i386/core_2";
402 model = &op_ppro_spec;
406 /* in order to get sysfs right */
407 static int using_nmi;
409 int __init op_nmi_init(struct oprofile_operations *ops)
411 __u8 vendor = boot_cpu_data.x86_vendor;
412 __u8 family = boot_cpu_data.x86;
420 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
426 model = &op_athlon_spec;
427 cpu_type = "i386/athlon";
430 model = &op_athlon_spec;
431 /* Actually it could be i386/hammer too, but give
432 user space an consistent name. */
433 cpu_type = "x86-64/hammer";
436 model = &op_athlon_spec;
437 cpu_type = "x86-64/family10";
442 case X86_VENDOR_INTEL:
446 if (!p4_init(&cpu_type))
450 /* A P6-class processor */
452 if (!ppro_init(&cpu_type))
467 ops->create_files = nmi_create_files;
468 ops->setup = nmi_setup;
469 ops->shutdown = nmi_shutdown;
470 ops->start = nmi_start;
471 ops->stop = nmi_stop;
472 ops->cpu_type = cpu_type;
473 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
477 void op_nmi_exit(void)