arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25 #include <asm/apic.h>
  26 #include <asm/processor.h>
  27 #include <asm/cpufeature.h>
  28
  29 #include "op_x86_model.h"
  30 #include "op_counter.h"
  31
  32 #define NUM_COUNTERS 4
  33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  34 #define NUM_VIRT_COUNTERS 32
  35 #else
  36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  37 #endif
  38
  39 #define OP_EVENT_MASK                   0x0FFF
  40 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  41
  42 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  43
  44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  45
  46 #define IBS_FETCH_SIZE                  6
  47 #define IBS_OP_SIZE                     12
  48
  49 static u32 ibs_caps;
  50
  51 struct ibs_config {
  52         unsigned long op_enabled;
  53         unsigned long fetch_enabled;
  54         unsigned long max_cnt_fetch;
  55         unsigned long max_cnt_op;
  56         unsigned long rand_en;
  57         unsigned long dispatched_ops;
  58         unsigned long branch_target;
  59 };
  60
  61 struct ibs_state {
  62         u64             ibs_op_ctl;
  63         int             branch_target;
  64         unsigned long   sample_size;
  65 };
  66
  67 static struct ibs_config ibs_config;
  68 static struct ibs_state ibs_state;
  69
  70 /*
  71  * IBS cpuid feature detection
  72  */
  73
  74 #define IBS_CPUID_FEATURES      0x8000001b
  75
  76 /*
  77  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
  78  * bit 0 is used to indicate the existence of IBS.
  79  */
  80 #define IBS_CAPS_AVAIL                  (1U<<0)
  81 #define IBS_CAPS_FETCHSAM               (1U<<1)
  82 #define IBS_CAPS_OPSAM                  (1U<<2)
  83 #define IBS_CAPS_RDWROPCNT              (1U<<3)
  84 #define IBS_CAPS_OPCNT                  (1U<<4)
  85 #define IBS_CAPS_BRNTRGT                (1U<<5)
  86 #define IBS_CAPS_OPCNTEXT               (1U<<6)
  87
  88 #define IBS_CAPS_DEFAULT                (IBS_CAPS_AVAIL         \
  89                                          | IBS_CAPS_FETCHSAM    \
  90                                          | IBS_CAPS_OPSAM)
  91
  92 /*
  93  * IBS APIC setup
  94  */
  95 #define IBSCTL                          0x1cc
  96 #define IBSCTL_LVT_OFFSET_VALID         (1ULL<<8)
  97 #define IBSCTL_LVT_OFFSET_MASK          0x0F
  98
  99 /*
 100  * IBS randomization macros
 101  */
 102 #define IBS_RANDOM_BITS                 12
 103 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
 104 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
 105
 106 static u32 get_ibs_caps(void)
 107 {
 108         u32 ibs_caps;
 109         unsigned int max_level;
 110
 111         if (!boot_cpu_has(X86_FEATURE_IBS))
 112                 return 0;
 113
 114         /* check IBS cpuid feature flags */
 115         max_level = cpuid_eax(0x80000000);
 116         if (max_level < IBS_CPUID_FEATURES)
 117                 return IBS_CAPS_DEFAULT;
 118
 119         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
 120         if (!(ibs_caps & IBS_CAPS_AVAIL))
 121                 /* cpuid flags not valid */
 122                 return IBS_CAPS_DEFAULT;
 123
 124         return ibs_caps;
 125 }
 126
 127 /*
 128  * 16-bit Linear Feedback Shift Register (LFSR)
 129  *
 130  *                       16   14   13    11
 131  * Feedback polynomial = X  + X  + X  +  X  + 1
 132  */
 133 static unsigned int lfsr_random(void)
 134 {
 135         static unsigned int lfsr_value = 0xF00D;
 136         unsigned int bit;
 137
 138         /* Compute next bit to shift in */
 139         bit = ((lfsr_value >> 0) ^
 140                (lfsr_value >> 2) ^
 141                (lfsr_value >> 3) ^
 142                (lfsr_value >> 5)) & 0x0001;
 143
 144         /* Advance to next register value */
 145         lfsr_value = (lfsr_value >> 1) | (bit << 15);
 146
 147         return lfsr_value;
 148 }
 149
 150 /*
 151  * IBS software randomization
 152  *
 153  * The IBS periodic op counter is randomized in software. The lower 12
 154  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
 155  * initialized with a 12 bit random value.
 156  */
 157 static inline u64 op_amd_randomize_ibs_op(u64 val)
 158 {
 159         unsigned int random = lfsr_random();
 160
 161         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
 162                 /*
 163                  * Work around if the hw can not write to IbsOpCurCnt
 164                  *
 165                  * Randomize the lower 8 bits of the 16 bit
 166                  * IbsOpMaxCnt [15:0] value in the range of -128 to
 167                  * +127 by adding/subtracting an offset to the
 168                  * maximum count (IbsOpMaxCnt).
 169                  *
 170                  * To avoid over or underflows and protect upper bits
 171                  * starting at bit 16, the initial value for
 172                  * IbsOpMaxCnt must fit in the range from 0x0081 to
 173                  * 0xff80.
 174                  */
 175                 val += (s8)(random >> 4);
 176         else
 177                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
 178
 179         return val;
 180 }
 181
 182 static inline void
 183 op_amd_handle_ibs(struct pt_regs * const regs,
 184                   struct op_msrs const * const msrs)
 185 {
 186         u64 val, ctl;
 187         struct op_entry entry;
 188
 189         if (!ibs_caps)
 190                 return;
 191
 192         if (ibs_config.fetch_enabled) {
 193                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 194                 if (ctl & IBS_FETCH_VAL) {
 195                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 196                         oprofile_write_reserve(&entry, regs, val,
 197                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 198                         oprofile_add_data64(&entry, val);
 199                         oprofile_add_data64(&entry, ctl);
 200                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 201                         oprofile_add_data64(&entry, val);
 202                         oprofile_write_commit(&entry);
 203
 204                         /* reenable the IRQ */
 205                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
 206                         ctl |= IBS_FETCH_ENABLE;
 207                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 208                 }
 209         }
 210
 211         if (ibs_config.op_enabled) {
 212                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 213                 if (ctl & IBS_OP_VAL) {
 214                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 215                         oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,
 216                                                ibs_state.sample_size);
 217                         oprofile_add_data64(&entry, val);
 218                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 219                         oprofile_add_data64(&entry, val);
 220                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 221                         oprofile_add_data64(&entry, val);
 222                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 223                         oprofile_add_data64(&entry, val);
 224                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 225                         oprofile_add_data64(&entry, val);
 226                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 227                         oprofile_add_data64(&entry, val);
 228                         if (ibs_state.branch_target) {
 229                                 rdmsrl(MSR_AMD64_IBSBRTARGET, val);
 230                                 oprofile_add_data(&entry, (unsigned long)val);
 231                         }
 232                         oprofile_write_commit(&entry);
 233
 234                         /* reenable the IRQ */
 235                         ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
 236                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 237                 }
 238         }
 239 }
 240
 241 static inline void op_amd_start_ibs(void)
 242 {
 243         u64 val;
 244
 245         if (!ibs_caps)
 246                 return;
 247
 248         memset(&ibs_state, 0, sizeof(ibs_state));
 249
 250         /*
 251          * Note: Since the max count settings may out of range we
 252          * write back the actual used values so that userland can read
 253          * it.
 254          */
 255
 256         if (ibs_config.fetch_enabled) {
 257                 val = ibs_config.max_cnt_fetch >> 4;
 258                 val = min(val, IBS_FETCH_MAX_CNT);
 259                 ibs_config.max_cnt_fetch = val << 4;
 260                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 261                 val |= IBS_FETCH_ENABLE;
 262                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 263         }
 264
 265         if (ibs_config.op_enabled) {
 266                 val = ibs_config.max_cnt_op >> 4;
 267                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
 268                         /*
 269                          * IbsOpCurCnt not supported.  See
 270                          * op_amd_randomize_ibs_op() for details.
 271                          */
 272                         val = clamp(val, 0x0081ULL, 0xFF80ULL);
 273                         ibs_config.max_cnt_op = val << 4;
 274                 } else {
 275                         /*
 276                          * The start value is randomized with a
 277                          * positive offset, we need to compensate it
 278                          * with the half of the randomized range. Also
 279                          * avoid underflows.
 280                          */
 281                         val += IBS_RANDOM_MAXCNT_OFFSET;
 282                         if (ibs_caps & IBS_CAPS_OPCNTEXT)
 283                                 val = min(val, IBS_OP_MAX_CNT_EXT);
 284                         else
 285                                 val = min(val, IBS_OP_MAX_CNT);
 286                         ibs_config.max_cnt_op =
 287                                 (val - IBS_RANDOM_MAXCNT_OFFSET) << 4;
 288                 }
 289                 val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);
 290                 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
 291                 val |= IBS_OP_ENABLE;
 292                 ibs_state.ibs_op_ctl = val;
 293                 ibs_state.sample_size = IBS_OP_SIZE;
 294                 if (ibs_config.branch_target) {
 295                         ibs_state.branch_target = 1;
 296                         ibs_state.sample_size++;
 297                 }
 298                 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
 299                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 300         }
 301 }
 302
 303 static void op_amd_stop_ibs(void)
 304 {
 305         if (!ibs_caps)
 306                 return;
 307
 308         if (ibs_config.fetch_enabled)
 309                 /* clear max count and enable */
 310                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 311
 312         if (ibs_config.op_enabled)
 313                 /* clear max count and enable */
 314                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 315 }
 316
 317 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 318
 319 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
 320                                struct op_msrs const * const msrs)
 321 {
 322         u64 val;
 323         int i;
 324
 325         /* enable active counters */
 326         for (i = 0; i < NUM_COUNTERS; ++i) {
 327                 int virt = op_x86_phys_to_virt(i);
 328                 if (!reset_value[virt])
 329                         continue;
 330                 rdmsrl(msrs->controls[i].addr, val);
 331                 val &= model->reserved;
 332                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 333                 wrmsrl(msrs->controls[i].addr, val);
 334         }
 335 }
 336
 337 #endif
 338
 339 /* functions for op_amd_spec */
 340
 341 static void op_amd_shutdown(struct op_msrs const * const msrs)
 342 {
 343         int i;
 344
 345         for (i = 0; i < NUM_COUNTERS; ++i) {
 346                 if (!msrs->counters[i].addr)
 347                         continue;
 348                 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 349                 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 350         }
 351 }
 352
 353 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
 354 {
 355         int i;
 356
 357         for (i = 0; i < NUM_COUNTERS; i++) {
 358                 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 359                         goto fail;
 360                 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
 361                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 362                         goto fail;
 363                 }
 364                 /* both registers must be reserved */
 365                 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 366                 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 367                 continue;
 368         fail:
 369                 if (!counter_config[i].enabled)
 370                         continue;
 371                 op_x86_warn_reserved(i);
 372                 op_amd_shutdown(msrs);
 373                 return -EBUSY;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 380                               struct op_msrs const * const msrs)
 381 {
 382         u64 val;
 383         int i;
 384
 385         /* setup reset_value */
 386         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 387                 if (counter_config[i].enabled
 388                     && msrs->counters[op_x86_virt_to_phys(i)].addr)
 389                         reset_value[i] = counter_config[i].count;
 390                 else
 391                         reset_value[i] = 0;
 392         }
 393
 394         /* clear all counters */
 395         for (i = 0; i < NUM_COUNTERS; ++i) {
 396                 if (!msrs->controls[i].addr)
 397                         continue;
 398                 rdmsrl(msrs->controls[i].addr, val);
 399                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 400                         op_x86_warn_in_use(i);
 401                 val &= model->reserved;
 402                 wrmsrl(msrs->controls[i].addr, val);
 403                 /*
 404                  * avoid a false detection of ctr overflows in NMI
 405                  * handler
 406                  */
 407                 wrmsrl(msrs->counters[i].addr, -1LL);
 408         }
 409
 410         /* enable active counters */
 411         for (i = 0; i < NUM_COUNTERS; ++i) {
 412                 int virt = op_x86_phys_to_virt(i);
 413                 if (!reset_value[virt])
 414                         continue;
 415
 416                 /* setup counter registers */
 417                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 418
 419                 /* setup control registers */
 420                 rdmsrl(msrs->controls[i].addr, val);
 421                 val &= model->reserved;
 422                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 423                 wrmsrl(msrs->controls[i].addr, val);
 424         }
 425
 426         if (ibs_caps)
 427                 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 428 }
 429
 430 static void op_amd_cpu_shutdown(void)
 431 {
 432         if (ibs_caps)
 433                 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 434 }
 435
 436 static int op_amd_check_ctrs(struct pt_regs * const regs,
 437                              struct op_msrs const * const msrs)
 438 {
 439         u64 val;
 440         int i;
 441
 442         for (i = 0; i < NUM_COUNTERS; ++i) {
 443                 int virt = op_x86_phys_to_virt(i);
 444                 if (!reset_value[virt])
 445                         continue;
 446                 rdmsrl(msrs->counters[i].addr, val);
 447                 /* bit is clear if overflowed: */
 448                 if (val & OP_CTR_OVERFLOW)
 449                         continue;
 450                 oprofile_add_sample(regs, virt);
 451                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 452         }
 453
 454         op_amd_handle_ibs(regs, msrs);
 455
 456         /* See op_model_ppro.c */
 457         return 1;
 458 }
 459
 460 static void op_amd_start(struct op_msrs const * const msrs)
 461 {
 462         u64 val;
 463         int i;
 464
 465         for (i = 0; i < NUM_COUNTERS; ++i) {
 466                 if (!reset_value[op_x86_phys_to_virt(i)])
 467                         continue;
 468                 rdmsrl(msrs->controls[i].addr, val);
 469                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 470                 wrmsrl(msrs->controls[i].addr, val);
 471         }
 472
 473         op_amd_start_ibs();
 474 }
 475
 476 static void op_amd_stop(struct op_msrs const * const msrs)
 477 {
 478         u64 val;
 479         int i;
 480
 481         /*
 482          * Subtle: stop on all counters to avoid race with setting our
 483          * pm callback
 484          */
 485         for (i = 0; i < NUM_COUNTERS; ++i) {
 486                 if (!reset_value[op_x86_phys_to_virt(i)])
 487                         continue;
 488                 rdmsrl(msrs->controls[i].addr, val);
 489                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 490                 wrmsrl(msrs->controls[i].addr, val);
 491         }
 492
 493         op_amd_stop_ibs();
 494 }
 495
 496 static int __init_ibs_nmi(void)
 497 {
 498 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 499 #define IBSCTL                          0x1cc
 500         struct pci_dev *cpu_cfg;
 501         int nodes;
 502         u32 value = 0;
 503         u8 ibs_eilvt_off;
 504
 505         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 506
 507         nodes = 0;
 508         cpu_cfg = NULL;
 509         do {
 510                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 511                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 512                                          cpu_cfg);
 513                 if (!cpu_cfg)
 514                         break;
 515                 ++nodes;
 516                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 517                                        | IBSCTL_LVTOFFSETVAL);
 518                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 519                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 520                         pci_dev_put(cpu_cfg);
 521                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 522                                 "IBSCTL = 0x%08x", value);
 523                         return 1;
 524                 }
 525         } while (1);
 526
 527         if (!nodes) {
 528                 printk(KERN_DEBUG "No CPU node configured for IBS");
 529                 return 1;
 530         }
 531
 532         return 0;
 533 }
 534
 535 /* initialize the APIC for the IBS interrupts if available */
 536 static void init_ibs(void)
 537 {
 538         ibs_caps = get_ibs_caps();
 539
 540         if (!ibs_caps)
 541                 return;
 542
 543         if (__init_ibs_nmi()) {
 544                 ibs_caps = 0;
 545                 return;
 546         }
 547
 548         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
 549                (unsigned)ibs_caps);
 550 }
 551
 552 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 553
 554 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 555 {
 556         struct dentry *dir;
 557         int ret = 0;
 558
 559         /* architecture specific files */
 560         if (create_arch_files)
 561                 ret = create_arch_files(sb, root);
 562
 563         if (ret)
 564                 return ret;
 565
 566         if (!ibs_caps)
 567                 return ret;
 568
 569         /* model specific files */
 570
 571         /* setup some reasonable defaults */
 572         memset(&ibs_config, 0, sizeof(ibs_config));
 573         ibs_config.max_cnt_fetch = 250000;
 574         ibs_config.max_cnt_op = 250000;
 575
 576         if (ibs_caps & IBS_CAPS_FETCHSAM) {
 577                 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 578                 oprofilefs_create_ulong(sb, dir, "enable",
 579                                         &ibs_config.fetch_enabled);
 580                 oprofilefs_create_ulong(sb, dir, "max_count",
 581                                         &ibs_config.max_cnt_fetch);
 582                 oprofilefs_create_ulong(sb, dir, "rand_enable",
 583                                         &ibs_config.rand_en);
 584         }
 585
 586         if (ibs_caps & IBS_CAPS_OPSAM) {
 587                 dir = oprofilefs_mkdir(sb, root, "ibs_op");
 588                 oprofilefs_create_ulong(sb, dir, "enable",
 589                                         &ibs_config.op_enabled);
 590                 oprofilefs_create_ulong(sb, dir, "max_count",
 591                                         &ibs_config.max_cnt_op);
 592                 if (ibs_caps & IBS_CAPS_OPCNT)
 593                         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 594                                                 &ibs_config.dispatched_ops);
 595                 if (ibs_caps & IBS_CAPS_BRNTRGT)
 596                         oprofilefs_create_ulong(sb, dir, "branch_target",
 597                                                 &ibs_config.branch_target);
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int op_amd_init(struct oprofile_operations *ops)
 604 {
 605         init_ibs();
 606         create_arch_files = ops->create_files;
 607         ops->create_files = setup_ibs_files;
 608         return 0;
 609 }
 610
 611 struct op_x86_model_spec op_amd_spec = {
 612         .num_counters           = NUM_COUNTERS,
 613         .num_controls           = NUM_COUNTERS,
 614         .num_virt_counters      = NUM_VIRT_COUNTERS,
 615         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 616         .event_mask             = OP_EVENT_MASK,
 617         .init                   = op_amd_init,
 618         .fill_in_addresses      = &op_amd_fill_in_addresses,
 619         .setup_ctrs             = &op_amd_setup_ctrs,
 620         .cpu_down               = &op_amd_cpu_shutdown,
 621         .check_ctrs             = &op_amd_check_ctrs,
 622         .start                  = &op_amd_start,
 623         .stop                   = &op_amd_stop,
 624         .shutdown               = &op_amd_shutdown,
 625 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 626         .switch_ctrl            = &op_mux_switch_ctrl,
 627 #endif
 628 };