3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf <barry.kasindorf@amd.com>
13 * @author Jason Yeh <jason.yeh@amd.com>
14 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
22 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
29 #include "op_x86_model.h"
30 #include "op_counter.h"
32 #define NUM_COUNTERS 4
33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
34 #define NUM_VIRT_COUNTERS 32
36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
39 #define OP_EVENT_MASK 0x0FFF
40 #define OP_CTR_OVERFLOW (1ULL<<31)
42 #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
46 #define IBS_FETCH_SIZE 6
47 #define IBS_OP_SIZE 12
52 unsigned long op_enabled;
53 unsigned long fetch_enabled;
54 unsigned long max_cnt_fetch;
55 unsigned long max_cnt_op;
56 unsigned long rand_en;
57 unsigned long dispatched_ops;
64 static struct ibs_config ibs_config;
65 static struct ibs_state ibs_state;
68 * IBS cpuid feature detection
71 #define IBS_CPUID_FEATURES 0x8000001b
74 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
75 * bit 0 is used to indicate the existence of IBS.
77 #define IBS_CAPS_AVAIL (1U<<0)
78 #define IBS_CAPS_FETCHSAM (1U<<1)
79 #define IBS_CAPS_OPSAM (1U<<2)
80 #define IBS_CAPS_RDWROPCNT (1U<<3)
81 #define IBS_CAPS_OPCNT (1U<<4)
83 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
91 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
92 #define IBSCTL_LVT_OFFSET_MASK 0x0F
95 * IBS randomization macros
97 #define IBS_RANDOM_BITS 12
98 #define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
99 #define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
101 static u32 get_ibs_caps(void)
104 unsigned int max_level;
106 if (!boot_cpu_has(X86_FEATURE_IBS))
109 /* check IBS cpuid feature flags */
110 max_level = cpuid_eax(0x80000000);
111 if (max_level < IBS_CPUID_FEATURES)
112 return IBS_CAPS_DEFAULT;
114 ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
115 if (!(ibs_caps & IBS_CAPS_AVAIL))
116 /* cpuid flags not valid */
117 return IBS_CAPS_DEFAULT;
123 * 16-bit Linear Feedback Shift Register (LFSR)
126 * Feedback polynomial = X + X + X + X + 1
128 static unsigned int lfsr_random(void)
130 static unsigned int lfsr_value = 0xF00D;
133 /* Compute next bit to shift in */
134 bit = ((lfsr_value >> 0) ^
137 (lfsr_value >> 5)) & 0x0001;
139 /* Advance to next register value */
140 lfsr_value = (lfsr_value >> 1) | (bit << 15);
146 * IBS software randomization
148 * The IBS periodic op counter is randomized in software. The lower 12
149 * bits of the 20 bit counter are randomized. IbsOpCurCnt is
150 * initialized with a 12 bit random value.
152 static inline u64 op_amd_randomize_ibs_op(u64 val)
154 unsigned int random = lfsr_random();
156 if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
158 * Work around if the hw can not write to IbsOpCurCnt
160 * Randomize the lower 8 bits of the 16 bit
161 * IbsOpMaxCnt [15:0] value in the range of -128 to
162 * +127 by adding/subtracting an offset to the
163 * maximum count (IbsOpMaxCnt).
165 * To avoid over or underflows and protect upper bits
166 * starting at bit 16, the initial value for
167 * IbsOpMaxCnt must fit in the range from 0x0081 to
170 val += (s8)(random >> 4);
172 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
178 op_amd_handle_ibs(struct pt_regs * const regs,
179 struct op_msrs const * const msrs)
182 struct op_entry entry;
187 if (ibs_config.fetch_enabled) {
188 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
189 if (ctl & IBS_FETCH_VAL) {
190 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
191 oprofile_write_reserve(&entry, regs, val,
192 IBS_FETCH_CODE, IBS_FETCH_SIZE);
193 oprofile_add_data64(&entry, val);
194 oprofile_add_data64(&entry, ctl);
195 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
196 oprofile_add_data64(&entry, val);
197 oprofile_write_commit(&entry);
199 /* reenable the IRQ */
200 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
201 ctl |= IBS_FETCH_ENABLE;
202 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
206 if (ibs_config.op_enabled) {
207 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
208 if (ctl & IBS_OP_VAL) {
209 rdmsrl(MSR_AMD64_IBSOPRIP, val);
210 oprofile_write_reserve(&entry, regs, val,
211 IBS_OP_CODE, IBS_OP_SIZE);
212 oprofile_add_data64(&entry, val);
213 rdmsrl(MSR_AMD64_IBSOPDATA, val);
214 oprofile_add_data64(&entry, val);
215 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
216 oprofile_add_data64(&entry, val);
217 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
218 oprofile_add_data64(&entry, val);
219 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
220 oprofile_add_data64(&entry, val);
221 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
222 oprofile_add_data64(&entry, val);
223 oprofile_write_commit(&entry);
225 /* reenable the IRQ */
226 ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
227 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
232 static inline void op_amd_start_ibs(void)
239 memset(&ibs_state, 0, sizeof(ibs_state));
241 if (ibs_config.fetch_enabled) {
242 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
243 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
244 val |= IBS_FETCH_ENABLE;
245 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
248 if (ibs_config.op_enabled) {
249 val = ibs_config.max_cnt_op >> 4;
250 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
252 * IbsOpCurCnt not supported. See
253 * op_amd_randomize_ibs_op() for details.
255 val = clamp(val, 0x0081ULL, 0xFF80ULL);
258 * The start value is randomized with a
259 * positive offset, we need to compensate it
260 * with the half of the randomized range. Also
263 val = min(val + IBS_RANDOM_MAXCNT_OFFSET,
266 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
267 val |= IBS_OP_ENABLE;
268 ibs_state.ibs_op_ctl = val;
269 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
270 wrmsrl(MSR_AMD64_IBSOPCTL, val);
274 static void op_amd_stop_ibs(void)
279 if (ibs_config.fetch_enabled)
280 /* clear max count and enable */
281 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
283 if (ibs_config.op_enabled)
284 /* clear max count and enable */
285 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
288 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
290 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
291 struct op_msrs const * const msrs)
296 /* enable active counters */
297 for (i = 0; i < NUM_COUNTERS; ++i) {
298 int virt = op_x86_phys_to_virt(i);
299 if (!reset_value[virt])
301 rdmsrl(msrs->controls[i].addr, val);
302 val &= model->reserved;
303 val |= op_x86_get_ctrl(model, &counter_config[virt]);
304 wrmsrl(msrs->controls[i].addr, val);
310 /* functions for op_amd_spec */
312 static void op_amd_shutdown(struct op_msrs const * const msrs)
316 for (i = 0; i < NUM_COUNTERS; ++i) {
317 if (!msrs->counters[i].addr)
319 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
320 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
324 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
328 for (i = 0; i < NUM_COUNTERS; i++) {
329 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
331 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
332 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
335 /* both registers must be reserved */
336 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
337 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
340 if (!counter_config[i].enabled)
342 op_x86_warn_reserved(i);
343 op_amd_shutdown(msrs);
350 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
351 struct op_msrs const * const msrs)
356 /* setup reset_value */
357 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
358 if (counter_config[i].enabled
359 && msrs->counters[op_x86_virt_to_phys(i)].addr)
360 reset_value[i] = counter_config[i].count;
365 /* clear all counters */
366 for (i = 0; i < NUM_COUNTERS; ++i) {
367 if (!msrs->controls[i].addr)
369 rdmsrl(msrs->controls[i].addr, val);
370 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
371 op_x86_warn_in_use(i);
372 val &= model->reserved;
373 wrmsrl(msrs->controls[i].addr, val);
375 * avoid a false detection of ctr overflows in NMI
378 wrmsrl(msrs->counters[i].addr, -1LL);
381 /* enable active counters */
382 for (i = 0; i < NUM_COUNTERS; ++i) {
383 int virt = op_x86_phys_to_virt(i);
384 if (!reset_value[virt])
387 /* setup counter registers */
388 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
390 /* setup control registers */
391 rdmsrl(msrs->controls[i].addr, val);
392 val &= model->reserved;
393 val |= op_x86_get_ctrl(model, &counter_config[virt]);
394 wrmsrl(msrs->controls[i].addr, val);
398 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
401 static void op_amd_cpu_shutdown(void)
404 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
407 static int op_amd_check_ctrs(struct pt_regs * const regs,
408 struct op_msrs const * const msrs)
413 for (i = 0; i < NUM_COUNTERS; ++i) {
414 int virt = op_x86_phys_to_virt(i);
415 if (!reset_value[virt])
417 rdmsrl(msrs->counters[i].addr, val);
418 /* bit is clear if overflowed: */
419 if (val & OP_CTR_OVERFLOW)
421 oprofile_add_sample(regs, virt);
422 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
425 op_amd_handle_ibs(regs, msrs);
427 /* See op_model_ppro.c */
431 static void op_amd_start(struct op_msrs const * const msrs)
436 for (i = 0; i < NUM_COUNTERS; ++i) {
437 if (!reset_value[op_x86_phys_to_virt(i)])
439 rdmsrl(msrs->controls[i].addr, val);
440 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
441 wrmsrl(msrs->controls[i].addr, val);
447 static void op_amd_stop(struct op_msrs const * const msrs)
453 * Subtle: stop on all counters to avoid race with setting our
456 for (i = 0; i < NUM_COUNTERS; ++i) {
457 if (!reset_value[op_x86_phys_to_virt(i)])
459 rdmsrl(msrs->controls[i].addr, val);
460 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
461 wrmsrl(msrs->controls[i].addr, val);
467 static int __init_ibs_nmi(void)
469 #define IBSCTL_LVTOFFSETVAL (1 << 8)
471 struct pci_dev *cpu_cfg;
476 ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
481 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
482 PCI_DEVICE_ID_AMD_10H_NB_MISC,
487 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
488 | IBSCTL_LVTOFFSETVAL);
489 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
490 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
491 pci_dev_put(cpu_cfg);
492 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
493 "IBSCTL = 0x%08x", value);
499 printk(KERN_DEBUG "No CPU node configured for IBS");
506 /* initialize the APIC for the IBS interrupts if available */
507 static void init_ibs(void)
509 ibs_caps = get_ibs_caps();
514 if (__init_ibs_nmi()) {
519 printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
523 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
525 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
530 /* architecture specific files */
531 if (create_arch_files)
532 ret = create_arch_files(sb, root);
540 /* model specific files */
542 /* setup some reasonable defaults */
543 ibs_config.max_cnt_fetch = 250000;
544 ibs_config.fetch_enabled = 0;
545 ibs_config.max_cnt_op = 250000;
546 ibs_config.op_enabled = 0;
547 ibs_config.dispatched_ops = 0;
549 if (ibs_caps & IBS_CAPS_FETCHSAM) {
550 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
551 oprofilefs_create_ulong(sb, dir, "enable",
552 &ibs_config.fetch_enabled);
553 oprofilefs_create_ulong(sb, dir, "max_count",
554 &ibs_config.max_cnt_fetch);
555 oprofilefs_create_ulong(sb, dir, "rand_enable",
556 &ibs_config.rand_en);
559 if (ibs_caps & IBS_CAPS_OPSAM) {
560 dir = oprofilefs_mkdir(sb, root, "ibs_op");
561 oprofilefs_create_ulong(sb, dir, "enable",
562 &ibs_config.op_enabled);
563 oprofilefs_create_ulong(sb, dir, "max_count",
564 &ibs_config.max_cnt_op);
565 if (ibs_caps & IBS_CAPS_OPCNT)
566 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
567 &ibs_config.dispatched_ops);
573 static int op_amd_init(struct oprofile_operations *ops)
576 create_arch_files = ops->create_files;
577 ops->create_files = setup_ibs_files;
581 struct op_x86_model_spec op_amd_spec = {
582 .num_counters = NUM_COUNTERS,
583 .num_controls = NUM_COUNTERS,
584 .num_virt_counters = NUM_VIRT_COUNTERS,
585 .reserved = MSR_AMD_EVENTSEL_RESERVED,
586 .event_mask = OP_EVENT_MASK,
588 .fill_in_addresses = &op_amd_fill_in_addresses,
589 .setup_ctrs = &op_amd_setup_ctrs,
590 .cpu_down = &op_amd_cpu_shutdown,
591 .check_ctrs = &op_amd_check_ctrs,
592 .start = &op_amd_start,
593 .stop = &op_amd_stop,
594 .shutdown = &op_amd_shutdown,
595 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
596 .switch_ctrl = &op_mux_switch_ctrl,