arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25 #include <asm/apic.h>
  26 #include <asm/processor.h>
  27 #include <asm/cpufeature.h>
  28
  29 #include "op_x86_model.h"
  30 #include "op_counter.h"
  31
  32 #define NUM_COUNTERS 4
  33 #define NUM_CONTROLS 4
  34 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  35 #define NUM_VIRT_COUNTERS 32
  36 #define NUM_VIRT_CONTROLS 32
  37 #else
  38 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  39 #define NUM_VIRT_CONTROLS NUM_CONTROLS
  40 #endif
  41
  42 #define OP_EVENT_MASK                   0x0FFF
  43 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  44
  45 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  46
  47 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  48
  49 /* IbsFetchCtl bits/masks */
  50 #define IBS_FETCH_RAND_EN               (1ULL<<57)
  51 #define IBS_FETCH_VAL                   (1ULL<<49)
  52 #define IBS_FETCH_ENABLE                (1ULL<<48)
  53 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
  54
  55 /* IbsOpCtl bits */
  56 #define IBS_OP_CNT_CTL                  (1ULL<<19)
  57 #define IBS_OP_VAL                      (1ULL<<18)
  58 #define IBS_OP_ENABLE                   (1ULL<<17)
  59
  60 #define IBS_FETCH_SIZE                  6
  61 #define IBS_OP_SIZE                     12
  62
  63 static u32 ibs_caps;
  64
  65 struct op_ibs_config {
  66         unsigned long op_enabled;
  67         unsigned long fetch_enabled;
  68         unsigned long max_cnt_fetch;
  69         unsigned long max_cnt_op;
  70         unsigned long rand_en;
  71         unsigned long dispatched_ops;
  72 };
  73
  74 static struct op_ibs_config ibs_config;
  75 static u64 ibs_op_ctl;
  76
  77 /*
  78  * IBS cpuid feature detection
  79  */
  80
  81 #define IBS_CPUID_FEATURES      0x8000001b
  82
  83 /*
  84  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
  85  * bit 0 is used to indicate the existence of IBS.
  86  */
  87 #define IBS_CAPS_AVAIL                  (1LL<<0)
  88 #define IBS_CAPS_RDWROPCNT              (1LL<<3)
  89 #define IBS_CAPS_OPCNT                  (1LL<<4)
  90
  91 /*
  92  * IBS randomization macros
  93  */
  94 #define IBS_RANDOM_BITS                 12
  95 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
  96 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
  97
  98 static u32 get_ibs_caps(void)
  99 {
 100         u32 ibs_caps;
 101         unsigned int max_level;
 102
 103         if (!boot_cpu_has(X86_FEATURE_IBS))
 104                 return 0;
 105
 106         /* check IBS cpuid feature flags */
 107         max_level = cpuid_eax(0x80000000);
 108         if (max_level < IBS_CPUID_FEATURES)
 109                 return IBS_CAPS_AVAIL;
 110
 111         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
 112         if (!(ibs_caps & IBS_CAPS_AVAIL))
 113                 /* cpuid flags not valid */
 114                 return IBS_CAPS_AVAIL;
 115
 116         return ibs_caps;
 117 }
 118
 119 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 120
 121 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
 122                                struct op_msrs const * const msrs)
 123 {
 124         u64 val;
 125         int i;
 126
 127         /* enable active counters */
 128         for (i = 0; i < NUM_COUNTERS; ++i) {
 129                 int virt = op_x86_phys_to_virt(i);
 130                 if (!reset_value[virt])
 131                         continue;
 132                 rdmsrl(msrs->controls[i].addr, val);
 133                 val &= model->reserved;
 134                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 135                 wrmsrl(msrs->controls[i].addr, val);
 136         }
 137 }
 138
 139 #endif
 140
 141 /* functions for op_amd_spec */
 142
 143 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
 144 {
 145         int i;
 146
 147         for (i = 0; i < NUM_COUNTERS; i++) {
 148                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 149                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 150         }
 151
 152         for (i = 0; i < NUM_CONTROLS; i++) {
 153                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
 154                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 155         }
 156 }
 157
 158 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 159                               struct op_msrs const * const msrs)
 160 {
 161         u64 val;
 162         int i;
 163
 164         /* setup reset_value */
 165         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 166                 if (counter_config[i].enabled
 167                     && msrs->counters[op_x86_virt_to_phys(i)].addr)
 168                         reset_value[i] = counter_config[i].count;
 169                 else
 170                         reset_value[i] = 0;
 171         }
 172
 173         /* clear all counters */
 174         for (i = 0; i < NUM_CONTROLS; ++i) {
 175                 if (unlikely(!msrs->controls[i].addr)) {
 176                         if (counter_config[i].enabled && !smp_processor_id())
 177                                 /*
 178                                  * counter is reserved, this is on all
 179                                  * cpus, so report only for cpu #0
 180                                  */
 181                                 op_x86_warn_reserved(i);
 182                         continue;
 183                 }
 184                 rdmsrl(msrs->controls[i].addr, val);
 185                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
 186                         op_x86_warn_in_use(i);
 187                 val &= model->reserved;
 188                 wrmsrl(msrs->controls[i].addr, val);
 189         }
 190
 191         /* avoid a false detection of ctr overflows in NMI handler */
 192         for (i = 0; i < NUM_COUNTERS; ++i) {
 193                 if (unlikely(!msrs->counters[i].addr))
 194                         continue;
 195                 wrmsrl(msrs->counters[i].addr, -1LL);
 196         }
 197
 198         /* enable active counters */
 199         for (i = 0; i < NUM_COUNTERS; ++i) {
 200                 int virt = op_x86_phys_to_virt(i);
 201                 if (!reset_value[virt])
 202                         continue;
 203
 204                 /* setup counter registers */
 205                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 206
 207                 /* setup control registers */
 208                 rdmsrl(msrs->controls[i].addr, val);
 209                 val &= model->reserved;
 210                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 211                 wrmsrl(msrs->controls[i].addr, val);
 212         }
 213 }
 214
 215 /*
 216  * 16-bit Linear Feedback Shift Register (LFSR)
 217  *
 218  *                       16   14   13    11
 219  * Feedback polynomial = X  + X  + X  +  X  + 1
 220  */
 221 static unsigned int lfsr_random(void)
 222 {
 223         static unsigned int lfsr_value = 0xF00D;
 224         unsigned int bit;
 225
 226         /* Compute next bit to shift in */
 227         bit = ((lfsr_value >> 0) ^
 228                (lfsr_value >> 2) ^
 229                (lfsr_value >> 3) ^
 230                (lfsr_value >> 5)) & 0x0001;
 231
 232         /* Advance to next register value */
 233         lfsr_value = (lfsr_value >> 1) | (bit << 15);
 234
 235         return lfsr_value;
 236 }
 237
 238 /*
 239  * IBS software randomization
 240  *
 241  * The IBS periodic op counter is randomized in software. The lower 12
 242  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
 243  * initialized with a 12 bit random value.
 244  */
 245 static inline u64 op_amd_randomize_ibs_op(u64 val)
 246 {
 247         unsigned int random = lfsr_random();
 248
 249         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
 250                 /*
 251                  * Work around if the hw can not write to IbsOpCurCnt
 252                  *
 253                  * Randomize the lower 8 bits of the 16 bit
 254                  * IbsOpMaxCnt [15:0] value in the range of -128 to
 255                  * +127 by adding/subtracting an offset to the
 256                  * maximum count (IbsOpMaxCnt).
 257                  *
 258                  * To avoid over or underflows and protect upper bits
 259                  * starting at bit 16, the initial value for
 260                  * IbsOpMaxCnt must fit in the range from 0x0081 to
 261                  * 0xff80.
 262                  */
 263                 val += (s8)(random >> 4);
 264         else
 265                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
 266
 267         return val;
 268 }
 269
 270 static inline void
 271 op_amd_handle_ibs(struct pt_regs * const regs,
 272                   struct op_msrs const * const msrs)
 273 {
 274         u64 val, ctl;
 275         struct op_entry entry;
 276
 277         if (!ibs_caps)
 278                 return;
 279
 280         if (ibs_config.fetch_enabled) {
 281                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 282                 if (ctl & IBS_FETCH_VAL) {
 283                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 284                         oprofile_write_reserve(&entry, regs, val,
 285                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 286                         oprofile_add_data64(&entry, val);
 287                         oprofile_add_data64(&entry, ctl);
 288                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 289                         oprofile_add_data64(&entry, val);
 290                         oprofile_write_commit(&entry);
 291
 292                         /* reenable the IRQ */
 293                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
 294                         ctl |= IBS_FETCH_ENABLE;
 295                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 296                 }
 297         }
 298
 299         if (ibs_config.op_enabled) {
 300                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 301                 if (ctl & IBS_OP_VAL) {
 302                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 303                         oprofile_write_reserve(&entry, regs, val,
 304                                                IBS_OP_CODE, IBS_OP_SIZE);
 305                         oprofile_add_data64(&entry, val);
 306                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 307                         oprofile_add_data64(&entry, val);
 308                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 309                         oprofile_add_data64(&entry, val);
 310                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 311                         oprofile_add_data64(&entry, val);
 312                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 313                         oprofile_add_data64(&entry, val);
 314                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 315                         oprofile_add_data64(&entry, val);
 316                         oprofile_write_commit(&entry);
 317
 318                         /* reenable the IRQ */
 319                         ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
 320                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 321                 }
 322         }
 323 }
 324
 325 static inline void op_amd_start_ibs(void)
 326 {
 327         u64 val;
 328
 329         if (!ibs_caps)
 330                 return;
 331
 332         if (ibs_config.fetch_enabled) {
 333                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 334                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 335                 val |= IBS_FETCH_ENABLE;
 336                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 337         }
 338
 339         if (ibs_config.op_enabled) {
 340                 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
 341                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
 342                         /*
 343                          * IbsOpCurCnt not supported.  See
 344                          * op_amd_randomize_ibs_op() for details.
 345                          */
 346                         ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
 347                 } else {
 348                         /*
 349                          * The start value is randomized with a
 350                          * positive offset, we need to compensate it
 351                          * with the half of the randomized range. Also
 352                          * avoid underflows.
 353                          */
 354                         ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
 355                                          0xFFFFULL);
 356                 }
 357                 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
 358                         ibs_op_ctl |= IBS_OP_CNT_CTL;
 359                 ibs_op_ctl |= IBS_OP_ENABLE;
 360                 val = op_amd_randomize_ibs_op(ibs_op_ctl);
 361                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 362         }
 363 }
 364
 365 static void op_amd_stop_ibs(void)
 366 {
 367         if (!ibs_caps)
 368                 return;
 369
 370         if (ibs_config.fetch_enabled)
 371                 /* clear max count and enable */
 372                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 373
 374         if (ibs_config.op_enabled)
 375                 /* clear max count and enable */
 376                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 377 }
 378
 379 static int op_amd_check_ctrs(struct pt_regs * const regs,
 380                              struct op_msrs const * const msrs)
 381 {
 382         u64 val;
 383         int i;
 384
 385         for (i = 0; i < NUM_COUNTERS; ++i) {
 386                 int virt = op_x86_phys_to_virt(i);
 387                 if (!reset_value[virt])
 388                         continue;
 389                 rdmsrl(msrs->counters[i].addr, val);
 390                 /* bit is clear if overflowed: */
 391                 if (val & OP_CTR_OVERFLOW)
 392                         continue;
 393                 oprofile_add_sample(regs, virt);
 394                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 395         }
 396
 397         op_amd_handle_ibs(regs, msrs);
 398
 399         /* See op_model_ppro.c */
 400         return 1;
 401 }
 402
 403 static void op_amd_start(struct op_msrs const * const msrs)
 404 {
 405         u64 val;
 406         int i;
 407
 408         for (i = 0; i < NUM_COUNTERS; ++i) {
 409                 if (!reset_value[op_x86_phys_to_virt(i)])
 410                         continue;
 411                 rdmsrl(msrs->controls[i].addr, val);
 412                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 413                 wrmsrl(msrs->controls[i].addr, val);
 414         }
 415
 416         op_amd_start_ibs();
 417 }
 418
 419 static void op_amd_stop(struct op_msrs const * const msrs)
 420 {
 421         u64 val;
 422         int i;
 423
 424         /*
 425          * Subtle: stop on all counters to avoid race with setting our
 426          * pm callback
 427          */
 428         for (i = 0; i < NUM_COUNTERS; ++i) {
 429                 if (!reset_value[op_x86_phys_to_virt(i)])
 430                         continue;
 431                 rdmsrl(msrs->controls[i].addr, val);
 432                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 433                 wrmsrl(msrs->controls[i].addr, val);
 434         }
 435
 436         op_amd_stop_ibs();
 437 }
 438
 439 static void op_amd_shutdown(struct op_msrs const * const msrs)
 440 {
 441         int i;
 442
 443         for (i = 0; i < NUM_COUNTERS; ++i) {
 444                 if (msrs->counters[i].addr)
 445                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 446         }
 447         for (i = 0; i < NUM_CONTROLS; ++i) {
 448                 if (msrs->controls[i].addr)
 449                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 450         }
 451 }
 452
 453 static u8 ibs_eilvt_off;
 454
 455 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 456 {
 457         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 458 }
 459
 460 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 461 {
 462         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 463 }
 464
 465 static int init_ibs_nmi(void)
 466 {
 467 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 468 #define IBSCTL                          0x1cc
 469         struct pci_dev *cpu_cfg;
 470         int nodes;
 471         u32 value = 0;
 472
 473         /* per CPU setup */
 474         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 475
 476         nodes = 0;
 477         cpu_cfg = NULL;
 478         do {
 479                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 480                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 481                                          cpu_cfg);
 482                 if (!cpu_cfg)
 483                         break;
 484                 ++nodes;
 485                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 486                                        | IBSCTL_LVTOFFSETVAL);
 487                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 488                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 489                         pci_dev_put(cpu_cfg);
 490                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 491                                 "IBSCTL = 0x%08x", value);
 492                         return 1;
 493                 }
 494         } while (1);
 495
 496         if (!nodes) {
 497                 printk(KERN_DEBUG "No CPU node configured for IBS");
 498                 return 1;
 499         }
 500
 501         return 0;
 502 }
 503
 504 /* uninitialize the APIC for the IBS interrupts if needed */
 505 static void clear_ibs_nmi(void)
 506 {
 507         if (ibs_caps)
 508                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 509 }
 510
 511 /* initialize the APIC for the IBS interrupts if available */
 512 static void ibs_init(void)
 513 {
 514         ibs_caps = get_ibs_caps();
 515
 516         if (!ibs_caps)
 517                 return;
 518
 519         if (init_ibs_nmi()) {
 520                 ibs_caps = 0;
 521                 return;
 522         }
 523
 524         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
 525                (unsigned)ibs_caps);
 526 }
 527
 528 static void ibs_exit(void)
 529 {
 530         if (!ibs_caps)
 531                 return;
 532
 533         clear_ibs_nmi();
 534 }
 535
 536 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 537
 538 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 539 {
 540         struct dentry *dir;
 541         int ret = 0;
 542
 543         /* architecture specific files */
 544         if (create_arch_files)
 545                 ret = create_arch_files(sb, root);
 546
 547         if (ret)
 548                 return ret;
 549
 550         if (!ibs_caps)
 551                 return ret;
 552
 553         /* model specific files */
 554
 555         /* setup some reasonable defaults */
 556         ibs_config.max_cnt_fetch = 250000;
 557         ibs_config.fetch_enabled = 0;
 558         ibs_config.max_cnt_op = 250000;
 559         ibs_config.op_enabled = 0;
 560         ibs_config.dispatched_ops = 0;
 561
 562         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 563         oprofilefs_create_ulong(sb, dir, "enable",
 564                                 &ibs_config.fetch_enabled);
 565         oprofilefs_create_ulong(sb, dir, "max_count",
 566                                 &ibs_config.max_cnt_fetch);
 567         oprofilefs_create_ulong(sb, dir, "rand_enable",
 568                                 &ibs_config.rand_en);
 569
 570         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 571         oprofilefs_create_ulong(sb, dir, "enable",
 572                                 &ibs_config.op_enabled);
 573         oprofilefs_create_ulong(sb, dir, "max_count",
 574                                 &ibs_config.max_cnt_op);
 575         if (ibs_caps & IBS_CAPS_OPCNT)
 576                 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 577                                         &ibs_config.dispatched_ops);
 578
 579         return 0;
 580 }
 581
 582 static int op_amd_init(struct oprofile_operations *ops)
 583 {
 584         ibs_init();
 585         create_arch_files = ops->create_files;
 586         ops->create_files = setup_ibs_files;
 587         return 0;
 588 }
 589
 590 static void op_amd_exit(void)
 591 {
 592         ibs_exit();
 593 }
 594
 595 struct op_x86_model_spec op_amd_spec = {
 596         .num_counters           = NUM_COUNTERS,
 597         .num_controls           = NUM_CONTROLS,
 598         .num_virt_counters      = NUM_VIRT_COUNTERS,
 599         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 600         .event_mask             = OP_EVENT_MASK,
 601         .init                   = op_amd_init,
 602         .exit                   = op_amd_exit,
 603         .fill_in_addresses      = &op_amd_fill_in_addresses,
 604         .setup_ctrs             = &op_amd_setup_ctrs,
 605         .check_ctrs             = &op_amd_check_ctrs,
 606         .start                  = &op_amd_start,
 607         .stop                   = &op_amd_stop,
 608         .shutdown               = &op_amd_shutdown,
 609 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 610         .switch_ctrl            = &op_mux_switch_ctrl,
 611 #endif
 612 };