3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf <barry.kasindorf@amd.com>
13 * @author Jason Yeh <jason.yeh@amd.com>
14 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
22 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
29 #include "op_x86_model.h"
30 #include "op_counter.h"
32 #define NUM_COUNTERS 4
33 #define NUM_CONTROLS 4
34 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
35 #define NUM_VIRT_COUNTERS 32
36 #define NUM_VIRT_CONTROLS 32
38 #define NUM_VIRT_COUNTERS NUM_COUNTERS
39 #define NUM_VIRT_CONTROLS NUM_CONTROLS
42 #define OP_EVENT_MASK 0x0FFF
43 #define OP_CTR_OVERFLOW (1ULL<<31)
45 #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
47 static unsigned long reset_value[NUM_VIRT_COUNTERS];
49 /* IbsFetchCtl bits/masks */
50 #define IBS_FETCH_RAND_EN (1ULL<<57)
51 #define IBS_FETCH_VAL (1ULL<<49)
52 #define IBS_FETCH_ENABLE (1ULL<<48)
53 #define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
56 #define IBS_OP_CNT_CTL (1ULL<<19)
57 #define IBS_OP_VAL (1ULL<<18)
58 #define IBS_OP_ENABLE (1ULL<<17)
60 #define IBS_FETCH_SIZE 6
61 #define IBS_OP_SIZE 12
65 struct op_ibs_config {
66 unsigned long op_enabled;
67 unsigned long fetch_enabled;
68 unsigned long max_cnt_fetch;
69 unsigned long max_cnt_op;
70 unsigned long rand_en;
71 unsigned long dispatched_ops;
74 static struct op_ibs_config ibs_config;
77 * IBS cpuid feature detection
80 #define IBS_CPUID_FEATURES 0x8000001b
83 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
84 * bit 0 is used to indicate the existence of IBS.
86 #define IBS_CAPS_AVAIL (1LL<<0)
87 #define IBS_CAPS_OPCNT (1LL<<4)
89 static u32 get_ibs_caps(void)
92 unsigned int max_level;
94 if (!boot_cpu_has(X86_FEATURE_IBS))
97 /* check IBS cpuid feature flags */
98 max_level = cpuid_eax(0x80000000);
99 if (max_level < IBS_CPUID_FEATURES)
100 return IBS_CAPS_AVAIL;
102 ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
103 if (!(ibs_caps & IBS_CAPS_AVAIL))
104 /* cpuid flags not valid */
105 return IBS_CAPS_AVAIL;
110 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
112 static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
116 for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
117 int hw_counter = op_x86_virt_to_phys(i);
118 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
119 msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
121 msrs->multiplex[i].addr = 0;
125 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
126 struct op_msrs const * const msrs)
131 /* enable active counters */
132 for (i = 0; i < NUM_COUNTERS; ++i) {
133 int virt = op_x86_phys_to_virt(i);
134 if (!counter_config[virt].enabled)
136 rdmsrl(msrs->controls[i].addr, val);
137 val &= model->reserved;
138 val |= op_x86_get_ctrl(model, &counter_config[virt]);
139 wrmsrl(msrs->controls[i].addr, val);
145 static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
149 /* functions for op_amd_spec */
151 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
155 for (i = 0; i < NUM_COUNTERS; i++) {
156 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
157 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
159 msrs->counters[i].addr = 0;
162 for (i = 0; i < NUM_CONTROLS; i++) {
163 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
164 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
166 msrs->controls[i].addr = 0;
169 op_mux_fill_in_addresses(msrs);
172 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
173 struct op_msrs const * const msrs)
178 /* setup reset_value */
179 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
180 if (counter_config[i].enabled)
181 reset_value[i] = counter_config[i].count;
186 /* clear all counters */
187 for (i = 0; i < NUM_CONTROLS; ++i) {
188 if (unlikely(!msrs->controls[i].addr))
190 rdmsrl(msrs->controls[i].addr, val);
191 val &= model->reserved;
192 wrmsrl(msrs->controls[i].addr, val);
195 /* avoid a false detection of ctr overflows in NMI handler */
196 for (i = 0; i < NUM_COUNTERS; ++i) {
197 if (unlikely(!msrs->counters[i].addr))
199 wrmsrl(msrs->counters[i].addr, -1LL);
202 /* enable active counters */
203 for (i = 0; i < NUM_COUNTERS; ++i) {
204 int virt = op_x86_phys_to_virt(i);
205 if (!counter_config[virt].enabled)
207 if (!msrs->counters[i].addr)
210 /* setup counter registers */
211 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
213 /* setup control registers */
214 rdmsrl(msrs->controls[i].addr, val);
215 val &= model->reserved;
216 val |= op_x86_get_ctrl(model, &counter_config[virt]);
217 wrmsrl(msrs->controls[i].addr, val);
222 * 16-bit Linear Feedback Shift Register (LFSR)
225 * Feedback polynomial = X + X + X + X + 1
227 static unsigned int lfsr_random(void)
229 static unsigned int lfsr_value = 0xF00D;
232 /* Compute next bit to shift in */
233 bit = ((lfsr_value >> 0) ^
236 (lfsr_value >> 5)) & 0x0001;
238 /* Advance to next register value */
239 lfsr_value = (lfsr_value >> 1) | (bit << 15);
245 op_amd_handle_ibs(struct pt_regs * const regs,
246 struct op_msrs const * const msrs)
249 struct op_entry entry;
254 if (ibs_config.fetch_enabled) {
255 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
256 if (ctl & IBS_FETCH_VAL) {
257 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
258 oprofile_write_reserve(&entry, regs, val,
259 IBS_FETCH_CODE, IBS_FETCH_SIZE);
260 oprofile_add_data64(&entry, val);
261 oprofile_add_data64(&entry, ctl);
262 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
263 oprofile_add_data64(&entry, val);
264 oprofile_write_commit(&entry);
266 /* reenable the IRQ */
267 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
268 ctl |= IBS_FETCH_ENABLE;
269 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
273 if (ibs_config.op_enabled) {
274 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
275 if (ctl & IBS_OP_VAL) {
276 rdmsrl(MSR_AMD64_IBSOPRIP, val);
277 oprofile_write_reserve(&entry, regs, val,
278 IBS_OP_CODE, IBS_OP_SIZE);
279 oprofile_add_data64(&entry, val);
280 rdmsrl(MSR_AMD64_IBSOPDATA, val);
281 oprofile_add_data64(&entry, val);
282 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
283 oprofile_add_data64(&entry, val);
284 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
285 oprofile_add_data64(&entry, val);
286 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
287 oprofile_add_data64(&entry, val);
288 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
289 oprofile_add_data64(&entry, val);
290 oprofile_write_commit(&entry);
292 /* reenable the IRQ */
293 ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
294 ctl |= IBS_OP_ENABLE;
295 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
300 static inline void op_amd_start_ibs(void)
307 if (ibs_config.fetch_enabled) {
308 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
309 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
310 val |= IBS_FETCH_ENABLE;
311 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
314 if (ibs_config.op_enabled) {
315 val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
316 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
317 val |= IBS_OP_CNT_CTL;
318 val |= IBS_OP_ENABLE;
319 wrmsrl(MSR_AMD64_IBSOPCTL, val);
323 static void op_amd_stop_ibs(void)
328 if (ibs_config.fetch_enabled)
329 /* clear max count and enable */
330 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
332 if (ibs_config.op_enabled)
333 /* clear max count and enable */
334 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
337 static int op_amd_check_ctrs(struct pt_regs * const regs,
338 struct op_msrs const * const msrs)
343 for (i = 0; i < NUM_COUNTERS; ++i) {
344 int virt = op_x86_phys_to_virt(i);
345 if (!reset_value[virt])
347 rdmsrl(msrs->counters[i].addr, val);
348 /* bit is clear if overflowed: */
349 if (val & OP_CTR_OVERFLOW)
351 oprofile_add_sample(regs, virt);
352 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
355 op_amd_handle_ibs(regs, msrs);
357 /* See op_model_ppro.c */
361 static void op_amd_start(struct op_msrs const * const msrs)
366 for (i = 0; i < NUM_COUNTERS; ++i) {
367 if (!reset_value[op_x86_phys_to_virt(i)])
369 rdmsrl(msrs->controls[i].addr, val);
370 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
371 wrmsrl(msrs->controls[i].addr, val);
377 static void op_amd_stop(struct op_msrs const * const msrs)
383 * Subtle: stop on all counters to avoid race with setting our
386 for (i = 0; i < NUM_COUNTERS; ++i) {
387 if (!reset_value[op_x86_phys_to_virt(i)])
389 rdmsrl(msrs->controls[i].addr, val);
390 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
391 wrmsrl(msrs->controls[i].addr, val);
397 static void op_amd_shutdown(struct op_msrs const * const msrs)
401 for (i = 0; i < NUM_COUNTERS; ++i) {
402 if (msrs->counters[i].addr)
403 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
405 for (i = 0; i < NUM_CONTROLS; ++i) {
406 if (msrs->controls[i].addr)
407 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
411 static u8 ibs_eilvt_off;
413 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
415 ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
418 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
420 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
423 static int init_ibs_nmi(void)
425 #define IBSCTL_LVTOFFSETVAL (1 << 8)
427 struct pci_dev *cpu_cfg;
432 on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
437 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
438 PCI_DEVICE_ID_AMD_10H_NB_MISC,
443 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
444 | IBSCTL_LVTOFFSETVAL);
445 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
446 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
447 pci_dev_put(cpu_cfg);
448 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
449 "IBSCTL = 0x%08x", value);
455 printk(KERN_DEBUG "No CPU node configured for IBS");
462 /* uninitialize the APIC for the IBS interrupts if needed */
463 static void clear_ibs_nmi(void)
466 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
469 /* initialize the APIC for the IBS interrupts if available */
470 static void ibs_init(void)
472 ibs_caps = get_ibs_caps();
477 if (init_ibs_nmi()) {
482 printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
486 static void ibs_exit(void)
494 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
496 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
501 /* architecture specific files */
502 if (create_arch_files)
503 ret = create_arch_files(sb, root);
511 /* model specific files */
513 /* setup some reasonable defaults */
514 ibs_config.max_cnt_fetch = 250000;
515 ibs_config.fetch_enabled = 0;
516 ibs_config.max_cnt_op = 250000;
517 ibs_config.op_enabled = 0;
518 ibs_config.dispatched_ops = 0;
520 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
521 oprofilefs_create_ulong(sb, dir, "enable",
522 &ibs_config.fetch_enabled);
523 oprofilefs_create_ulong(sb, dir, "max_count",
524 &ibs_config.max_cnt_fetch);
525 oprofilefs_create_ulong(sb, dir, "rand_enable",
526 &ibs_config.rand_en);
528 dir = oprofilefs_mkdir(sb, root, "ibs_op");
529 oprofilefs_create_ulong(sb, dir, "enable",
530 &ibs_config.op_enabled);
531 oprofilefs_create_ulong(sb, dir, "max_count",
532 &ibs_config.max_cnt_op);
533 if (ibs_caps & IBS_CAPS_OPCNT)
534 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
535 &ibs_config.dispatched_ops);
540 static int op_amd_init(struct oprofile_operations *ops)
543 create_arch_files = ops->create_files;
544 ops->create_files = setup_ibs_files;
548 static void op_amd_exit(void)
553 struct op_x86_model_spec op_amd_spec = {
554 .num_counters = NUM_COUNTERS,
555 .num_controls = NUM_CONTROLS,
556 .num_virt_counters = NUM_VIRT_COUNTERS,
557 .reserved = MSR_AMD_EVENTSEL_RESERVED,
558 .event_mask = OP_EVENT_MASK,
561 .fill_in_addresses = &op_amd_fill_in_addresses,
562 .setup_ctrs = &op_amd_setup_ctrs,
563 .check_ctrs = &op_amd_check_ctrs,
564 .start = &op_amd_start,
565 .stop = &op_amd_stop,
566 .shutdown = &op_amd_shutdown,
567 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
568 .switch_ctrl = &op_mux_switch_ctrl,