2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/sort.h>
20 #include <asm/pci_x86.h>
23 #define PREFIX "PCI: "
25 /* aperture is up to 256MB but BIOS may reserve less */
26 #define MMCONFIG_APER_MIN (2 * 1024*1024)
27 #define MMCONFIG_APER_MAX (256 * 1024*1024)
29 /* Indicate if the mmcfg resources have been placed into the resource table. */
30 static int __initdata pci_mmcfg_resources_inserted;
32 static __init int extend_mmcfg(int num)
34 struct acpi_mcfg_allocation *new;
35 int new_num = pci_mmcfg_config_num + num;
37 new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
41 if (pci_mmcfg_config) {
42 memcpy(new, pci_mmcfg_config,
43 sizeof(pci_mmcfg_config[0]) * new_num);
44 kfree(pci_mmcfg_config);
46 pci_mmcfg_config = new;
51 static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
53 int i = pci_mmcfg_config_num;
55 pci_mmcfg_config_num++;
56 pci_mmcfg_config[i].address = addr;
57 pci_mmcfg_config[i].pci_segment = segment;
58 pci_mmcfg_config[i].start_bus_number = start;
59 pci_mmcfg_config[i].end_bus_number = end;
62 static const char __init *pci_mmcfg_e7520(void)
65 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
68 if (win == 0x0000 || win == 0xf000)
71 if (extend_mmcfg(1) == -1)
74 fill_one_mmcfg(win << 16, 0, 0, 255);
76 return "Intel Corporation E7520 Memory Controller Hub";
79 static const char __init *pci_mmcfg_intel_945(void)
81 u32 pciexbar, mask = 0, len = 0;
83 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
90 switch ((pciexbar >> 1) & 3) {
107 /* Errata #2, things break when not aligned on a 256Mb boundary */
108 /* Can only happen in 64M/128M mode */
110 if ((pciexbar & mask) & 0x0fffffffU)
113 /* Don't hit the APIC registers and their friends */
114 if ((pciexbar & mask) >= 0xf0000000U)
117 if (extend_mmcfg(1) == -1)
120 fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
122 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
125 static const char __init *pci_mmcfg_amd_fam10h(void)
127 u32 low, high, address;
130 unsigned segnbits = 0, busnbits;
132 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
135 address = MSR_FAM10H_MMIO_CONF_BASE;
136 if (rdmsr_safe(address, &low, &high))
143 /* mmconfig is not enable */
144 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
147 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
149 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
150 FAM10H_MMIO_CONF_BUSRANGE_MASK;
153 * only handle bus 0 ?
160 segnbits = busnbits - 8;
164 if (extend_mmcfg(1 << segnbits) == -1)
167 for (i = 0; i < (1 << segnbits); i++)
168 fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
170 return "AMD Family 10h NB";
173 static bool __initdata mcp55_checked;
174 static const char __init *pci_mmcfg_nvidia_mcp55(void)
177 int mcp55_mmconf_found = 0;
179 static const u32 extcfg_regnum = 0x90;
180 static const u32 extcfg_regsize = 4;
181 static const u32 extcfg_enable_mask = 1<<31;
182 static const u32 extcfg_start_mask = 0xff<<16;
183 static const int extcfg_start_shift = 16;
184 static const u32 extcfg_size_mask = 0x3<<28;
185 static const int extcfg_size_shift = 28;
186 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
187 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
188 static const int extcfg_base_lshift = 25;
191 * do check if amd fam10h already took over
193 if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
196 mcp55_checked = true;
197 for (bus = 0; bus < 256; bus++) {
201 int start, size_index, end;
203 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
205 device = (l >> 16) & 0xffff;
207 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
210 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
211 extcfg_regsize, &extcfg);
213 if (!(extcfg & extcfg_enable_mask))
216 if (extend_mmcfg(1) == -1)
219 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
220 base = extcfg & extcfg_base_mask[size_index];
221 /* base could > 4G */
222 base <<= extcfg_base_lshift;
223 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
224 end = start + extcfg_sizebus[size_index] - 1;
225 fill_one_mmcfg(base, 0, start, end);
226 mcp55_mmconf_found++;
229 if (!mcp55_mmconf_found)
232 return "nVidia MCP55";
235 struct pci_mmcfg_hostbridge_probe {
240 const char *(*probe)(void);
243 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
244 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
245 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
246 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
247 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
248 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
249 0x1200, pci_mmcfg_amd_fam10h },
250 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
251 0x1200, pci_mmcfg_amd_fam10h },
252 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
253 0x0369, pci_mmcfg_nvidia_mcp55 },
256 static int __init cmp_mmcfg(const void *x1, const void *x2)
258 const typeof(pci_mmcfg_config[0]) *m1 = x1;
259 const typeof(pci_mmcfg_config[0]) *m2 = x2;
262 start1 = m1->start_bus_number;
263 start2 = m2->start_bus_number;
265 return start1 - start2;
268 static void __init pci_mmcfg_check_end_bus_number(void)
271 typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
273 /* sort them at first */
274 sort(pci_mmcfg_config, pci_mmcfg_config_num,
275 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
278 if (pci_mmcfg_config_num > 0) {
279 i = pci_mmcfg_config_num - 1;
280 cfg = &pci_mmcfg_config[i];
281 if (cfg->end_bus_number < cfg->start_bus_number)
282 cfg->end_bus_number = 255;
285 /* don't overlap please */
286 for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
287 cfg = &pci_mmcfg_config[i];
288 cfgx = &pci_mmcfg_config[i+1];
290 if (cfg->end_bus_number < cfg->start_bus_number)
291 cfg->end_bus_number = 255;
293 if (cfg->end_bus_number >= cfgx->start_bus_number)
294 cfg->end_bus_number = cfgx->start_bus_number - 1;
298 static int __init pci_mmcfg_check_hostbridge(void)
309 pci_mmcfg_config_num = 0;
310 pci_mmcfg_config = NULL;
312 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
313 bus = pci_mmcfg_probes[i].bus;
314 devfn = pci_mmcfg_probes[i].devfn;
315 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
317 device = (l >> 16) & 0xffff;
320 if (pci_mmcfg_probes[i].vendor == vendor &&
321 pci_mmcfg_probes[i].device == device)
322 name = pci_mmcfg_probes[i].probe();
325 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
329 /* some end_bus_number is crazy, fix it */
330 pci_mmcfg_check_end_bus_number();
332 return pci_mmcfg_config_num != 0;
335 static void __init pci_mmcfg_insert_resources(void)
337 #define PCI_MMCFG_RESOURCE_NAME_LEN 24
339 struct resource *res;
343 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
344 pci_mmcfg_config_num, GFP_KERNEL);
346 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
350 names = (void *)&res[pci_mmcfg_config_num];
351 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
352 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
353 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
355 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
356 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
357 cfg->start_bus_number, cfg->end_bus_number);
358 res->start = cfg->address + (cfg->start_bus_number << 20);
359 res->end = res->start + (num_buses << 20) - 1;
360 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
361 insert_resource(&iomem_resource, res);
362 names += PCI_MMCFG_RESOURCE_NAME_LEN;
365 /* Mark that the resources have been inserted. */
366 pci_mmcfg_resources_inserted = 1;
369 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
372 struct resource *mcfg_res = data;
373 struct acpi_resource_address64 address;
376 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
377 struct acpi_resource_fixed_memory32 *fixmem32 =
378 &res->data.fixed_memory32;
381 if ((mcfg_res->start >= fixmem32->address) &&
382 (mcfg_res->end < (fixmem32->address +
383 fixmem32->address_length))) {
385 return AE_CTRL_TERMINATE;
388 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
389 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
392 status = acpi_resource_to_address64(res, &address);
393 if (ACPI_FAILURE(status) ||
394 (address.address_length <= 0) ||
395 (address.resource_type != ACPI_MEMORY_RANGE))
398 if ((mcfg_res->start >= address.minimum) &&
399 (mcfg_res->end < (address.minimum + address.address_length))) {
401 return AE_CTRL_TERMINATE;
406 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
407 void *context, void **rv)
409 struct resource *mcfg_res = context;
411 acpi_walk_resources(handle, METHOD_NAME__CRS,
412 check_mcfg_resource, context);
415 return AE_CTRL_TERMINATE;
420 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
422 struct resource mcfg_res;
424 mcfg_res.start = start;
425 mcfg_res.end = end - 1;
428 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
431 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
434 return mcfg_res.flags;
437 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
439 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
440 u64 addr, u64 size, int i,
441 typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
446 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
448 if (size < (16UL<<20))
452 if (size >= (16UL<<20) || size == old_size) {
454 "PCI: MCFG area at %Lx reserved in %s\n",
455 addr, with_e820?"E820":"ACPI motherboard resources");
458 if (old_size != size) {
459 /* update end_bus_number */
460 cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
461 printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
462 "segment %hu buses %u - %u\n",
463 i, (unsigned long)cfg->address, cfg->pci_segment,
464 (unsigned int)cfg->start_bus_number,
465 (unsigned int)cfg->end_bus_number);
472 static void __init pci_mmcfg_reject_broken(int early)
474 typeof(pci_mmcfg_config[0]) *cfg;
477 if ((pci_mmcfg_config_num == 0) ||
478 (pci_mmcfg_config == NULL) ||
479 (pci_mmcfg_config[0].address == 0))
482 for (i = 0; i < pci_mmcfg_config_num; i++) {
486 cfg = &pci_mmcfg_config[i];
487 addr = cfg->start_bus_number;
489 addr += cfg->address;
490 size = cfg->end_bus_number + 1 - cfg->start_bus_number;
492 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
493 "segment %hu buses %u - %u\n",
494 i, (unsigned long)cfg->address, cfg->pci_segment,
495 (unsigned int)cfg->start_bus_number,
496 (unsigned int)cfg->end_bus_number);
498 if (!early && !acpi_disabled)
499 valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
505 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
506 " reserved in ACPI motherboard resources\n",
509 /* Don't try to do this check unless configuration
510 type 1 is available. how about type 2 ?*/
512 valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
521 printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
522 pci_mmcfg_arch_free();
523 kfree(pci_mmcfg_config);
524 pci_mmcfg_config = NULL;
525 pci_mmcfg_config_num = 0;
528 static int __initdata known_bridge;
530 static int acpi_mcfg_64bit_base_addr __initdata = FALSE;
532 /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */
533 struct acpi_mcfg_allocation *pci_mmcfg_config;
534 int pci_mmcfg_config_num;
536 static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg)
538 if (!strcmp(mcfg->header.oem_id, "SGI"))
539 acpi_mcfg_64bit_base_addr = TRUE;
544 static int __init pci_parse_mcfg(struct acpi_table_header *header)
546 struct acpi_table_mcfg *mcfg;
553 mcfg = (struct acpi_table_mcfg *)header;
555 /* how many config structures do we have */
556 pci_mmcfg_config_num = 0;
557 i = header->length - sizeof(struct acpi_table_mcfg);
558 while (i >= sizeof(struct acpi_mcfg_allocation)) {
559 ++pci_mmcfg_config_num;
560 i -= sizeof(struct acpi_mcfg_allocation);
562 if (pci_mmcfg_config_num == 0) {
563 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
567 config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
568 pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
569 if (!pci_mmcfg_config) {
570 printk(KERN_WARNING PREFIX
571 "No memory for MCFG config tables\n");
575 memcpy(pci_mmcfg_config, &mcfg[1], config_size);
577 acpi_mcfg_oem_check(mcfg);
579 for (i = 0; i < pci_mmcfg_config_num; ++i) {
580 if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) &&
581 !acpi_mcfg_64bit_base_addr) {
582 printk(KERN_ERR PREFIX
583 "MMCONFIG not in low 4GB of memory\n");
584 kfree(pci_mmcfg_config);
585 pci_mmcfg_config_num = 0;
593 static void __init __pci_mmcfg_init(int early)
595 /* MMCONFIG disabled */
596 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
599 /* MMCONFIG already enabled */
600 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
603 /* for late to exit */
608 if (pci_mmcfg_check_hostbridge())
613 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
615 pci_mmcfg_reject_broken(early);
617 if ((pci_mmcfg_config_num == 0) ||
618 (pci_mmcfg_config == NULL) ||
619 (pci_mmcfg_config[0].address == 0))
622 if (pci_mmcfg_arch_init())
623 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
626 * Signal not to attempt to insert mmcfg resources because
627 * the architecture mmcfg setup could not initialize.
629 pci_mmcfg_resources_inserted = 1;
633 void __init pci_mmcfg_early_init(void)
638 void __init pci_mmcfg_late_init(void)
643 static int __init pci_mmcfg_late_insert_resources(void)
646 * If resources are already inserted or we are not using MMCONFIG,
647 * don't insert the resources.
649 if ((pci_mmcfg_resources_inserted == 1) ||
650 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
651 (pci_mmcfg_config_num == 0) ||
652 (pci_mmcfg_config == NULL) ||
653 (pci_mmcfg_config[0].address == 0))
657 * Attempt to insert the mmcfg resources but not with the busy flag
658 * marked so it won't cause request errors when __request_region is
661 pci_mmcfg_insert_resources();
667 * Perform MMCONFIG resource insertion after PCI initialization to allow for
668 * misprogrammed MCFG tables that state larger sizes but actually conflict
669 * with other system resources.
671 late_initcall(pci_mmcfg_late_insert_resources);