2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
20 #include <asm/pci_x86.h>
23 #define PREFIX "PCI: "
25 /* Indicate if the mmcfg resources have been placed into the resource table. */
26 static int __initdata pci_mmcfg_resources_inserted;
28 LIST_HEAD(pci_mmcfg_list);
30 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
33 release_resource(&cfg->res);
38 static __init void free_all_mmcfg(void)
40 struct pci_mmcfg_region *cfg, *tmp;
42 pci_mmcfg_arch_free();
43 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
44 pci_mmconfig_remove(cfg);
47 static __init void list_add_sorted(struct pci_mmcfg_region *new)
49 struct pci_mmcfg_region *cfg;
51 /* keep list sorted by segment and starting bus number */
52 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
53 if (cfg->segment > new->segment ||
54 (cfg->segment == new->segment &&
55 cfg->start_bus >= new->start_bus)) {
56 list_add_tail(&new->list, &cfg->list);
60 list_add_tail(&new->list, &pci_mmcfg_list);
63 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
66 struct pci_mmcfg_region *new;
73 new = kzalloc(sizeof(*new), GFP_KERNEL);
78 new->segment = segment;
79 new->start_bus = start;
84 num_buses = end - start + 1;
86 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
87 res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
88 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
89 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
90 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
91 res->name = new->name;
93 printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
94 "%pR (base %#lx)\n", segment, start, end, &new->res,
95 (unsigned long) addr);
100 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
102 struct pci_mmcfg_region *cfg;
104 list_for_each_entry(cfg, &pci_mmcfg_list, list)
105 if (cfg->segment == segment &&
106 cfg->start_bus <= bus && bus <= cfg->end_bus)
112 static const char __init *pci_mmcfg_e7520(void)
115 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
118 if (win == 0x0000 || win == 0xf000)
121 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
124 return "Intel Corporation E7520 Memory Controller Hub";
127 static const char __init *pci_mmcfg_intel_945(void)
129 u32 pciexbar, mask = 0, len = 0;
131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
138 switch ((pciexbar >> 1) & 3) {
155 /* Errata #2, things break when not aligned on a 256Mb boundary */
156 /* Can only happen in 64M/128M mode */
158 if ((pciexbar & mask) & 0x0fffffffU)
161 /* Don't hit the APIC registers and their friends */
162 if ((pciexbar & mask) >= 0xf0000000U)
165 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
168 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
171 static const char __init *pci_mmcfg_amd_fam10h(void)
173 u32 low, high, address;
176 unsigned segnbits = 0, busnbits, end_bus;
178 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
181 address = MSR_FAM10H_MMIO_CONF_BASE;
182 if (rdmsr_safe(address, &low, &high))
189 /* mmconfig is not enable */
190 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
193 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
195 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
196 FAM10H_MMIO_CONF_BUSRANGE_MASK;
199 * only handle bus 0 ?
206 segnbits = busnbits - 8;
210 end_bus = (1 << busnbits) - 1;
211 for (i = 0; i < (1 << segnbits); i++)
212 if (pci_mmconfig_add(i, 0, end_bus,
213 base + (1<<28) * i) == NULL) {
218 return "AMD Family 10h NB";
221 static bool __initdata mcp55_checked;
222 static const char __init *pci_mmcfg_nvidia_mcp55(void)
225 int mcp55_mmconf_found = 0;
227 static const u32 extcfg_regnum = 0x90;
228 static const u32 extcfg_regsize = 4;
229 static const u32 extcfg_enable_mask = 1<<31;
230 static const u32 extcfg_start_mask = 0xff<<16;
231 static const int extcfg_start_shift = 16;
232 static const u32 extcfg_size_mask = 0x3<<28;
233 static const int extcfg_size_shift = 28;
234 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
235 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
236 static const int extcfg_base_lshift = 25;
239 * do check if amd fam10h already took over
241 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
244 mcp55_checked = true;
245 for (bus = 0; bus < 256; bus++) {
249 int start, size_index, end;
251 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
253 device = (l >> 16) & 0xffff;
255 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
258 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
259 extcfg_regsize, &extcfg);
261 if (!(extcfg & extcfg_enable_mask))
264 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
265 base = extcfg & extcfg_base_mask[size_index];
266 /* base could > 4G */
267 base <<= extcfg_base_lshift;
268 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
269 end = start + extcfg_sizebus[size_index] - 1;
270 if (pci_mmconfig_add(0, start, end, base) == NULL)
272 mcp55_mmconf_found++;
275 if (!mcp55_mmconf_found)
278 return "nVidia MCP55";
281 struct pci_mmcfg_hostbridge_probe {
286 const char *(*probe)(void);
289 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
290 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
291 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
292 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
293 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
294 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
295 0x1200, pci_mmcfg_amd_fam10h },
296 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
297 0x1200, pci_mmcfg_amd_fam10h },
298 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
299 0x0369, pci_mmcfg_nvidia_mcp55 },
302 static void __init pci_mmcfg_check_end_bus_number(void)
304 struct pci_mmcfg_region *cfg, *cfgx;
307 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
308 if (cfg->end_bus < cfg->start_bus)
311 /* Don't access the list head ! */
312 if (cfg->list.next == &pci_mmcfg_list)
315 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
316 if (cfg->end_bus >= cfgx->start_bus)
317 cfg->end_bus = cfgx->start_bus - 1;
321 static int __init pci_mmcfg_check_hostbridge(void)
334 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
335 bus = pci_mmcfg_probes[i].bus;
336 devfn = pci_mmcfg_probes[i].devfn;
337 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
339 device = (l >> 16) & 0xffff;
342 if (pci_mmcfg_probes[i].vendor == vendor &&
343 pci_mmcfg_probes[i].device == device)
344 name = pci_mmcfg_probes[i].probe();
347 printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
351 /* some end_bus_number is crazy, fix it */
352 pci_mmcfg_check_end_bus_number();
354 return !list_empty(&pci_mmcfg_list);
357 static void __init pci_mmcfg_insert_resources(void)
359 struct pci_mmcfg_region *cfg;
361 list_for_each_entry(cfg, &pci_mmcfg_list, list)
362 insert_resource(&iomem_resource, &cfg->res);
364 /* Mark that the resources have been inserted. */
365 pci_mmcfg_resources_inserted = 1;
368 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
371 struct resource *mcfg_res = data;
372 struct acpi_resource_address64 address;
375 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
376 struct acpi_resource_fixed_memory32 *fixmem32 =
377 &res->data.fixed_memory32;
380 if ((mcfg_res->start >= fixmem32->address) &&
381 (mcfg_res->end < (fixmem32->address +
382 fixmem32->address_length))) {
384 return AE_CTRL_TERMINATE;
387 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
388 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
391 status = acpi_resource_to_address64(res, &address);
392 if (ACPI_FAILURE(status) ||
393 (address.address_length <= 0) ||
394 (address.resource_type != ACPI_MEMORY_RANGE))
397 if ((mcfg_res->start >= address.minimum) &&
398 (mcfg_res->end < (address.minimum + address.address_length))) {
400 return AE_CTRL_TERMINATE;
405 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
406 void *context, void **rv)
408 struct resource *mcfg_res = context;
410 acpi_walk_resources(handle, METHOD_NAME__CRS,
411 check_mcfg_resource, context);
414 return AE_CTRL_TERMINATE;
419 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
421 struct resource mcfg_res;
423 mcfg_res.start = start;
424 mcfg_res.end = end - 1;
427 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
430 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
433 return mcfg_res.flags;
436 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
438 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
439 struct pci_mmcfg_region *cfg, int with_e820)
441 u64 addr = cfg->res.start;
442 u64 size = resource_size(&cfg->res);
444 int valid = 0, num_buses;
446 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
448 if (size < (16UL<<20))
452 if (size >= (16UL<<20) || size == old_size) {
453 printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
455 with_e820 ? "E820" : "ACPI motherboard resources");
458 if (old_size != size) {
460 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
461 num_buses = cfg->end_bus - cfg->start_bus + 1;
462 cfg->res.end = cfg->res.start +
463 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
464 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
465 "PCI MMCONFIG %04x [bus %02x-%02x]",
466 cfg->segment, cfg->start_bus, cfg->end_bus);
467 printk(KERN_INFO PREFIX
468 "MMCONFIG for %04x [bus%02x-%02x] "
469 "at %pR (base %#lx) (size reduced!)\n",
470 cfg->segment, cfg->start_bus, cfg->end_bus,
471 &cfg->res, (unsigned long) cfg->address);
478 static void __init pci_mmcfg_reject_broken(int early)
480 struct pci_mmcfg_region *cfg;
482 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
485 if (!early && !acpi_disabled)
486 valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
492 printk(KERN_ERR FW_BUG PREFIX
493 "MMCONFIG at %pR not reserved in "
494 "ACPI motherboard resources\n", &cfg->res);
496 /* Don't try to do this check unless configuration
497 type 1 is available. how about type 2 ?*/
499 valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
508 printk(KERN_INFO PREFIX "not using MMCONFIG\n");
512 static int __initdata known_bridge;
514 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
515 struct acpi_mcfg_allocation *cfg)
519 if (cfg->address < 0xFFFFFFFF)
522 if (!strcmp(mcfg->header.oem_id, "SGI"))
525 if (mcfg->header.revision >= 1) {
526 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
531 printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
532 "is above 4GB, ignored\n", cfg->pci_segment,
533 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
537 static int __init pci_parse_mcfg(struct acpi_table_header *header)
539 struct acpi_table_mcfg *mcfg;
540 struct acpi_mcfg_allocation *cfg_table, *cfg;
547 mcfg = (struct acpi_table_mcfg *)header;
549 /* how many config structures do we have */
552 i = header->length - sizeof(struct acpi_table_mcfg);
553 while (i >= sizeof(struct acpi_mcfg_allocation)) {
555 i -= sizeof(struct acpi_mcfg_allocation);
558 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
562 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
563 for (i = 0; i < entries; i++) {
565 if (acpi_mcfg_check_entry(mcfg, cfg)) {
570 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
571 cfg->end_bus_number, cfg->address) == NULL) {
572 printk(KERN_WARNING PREFIX
573 "no memory for MCFG entries\n");
582 static void __init __pci_mmcfg_init(int early)
584 /* MMCONFIG disabled */
585 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
588 /* MMCONFIG already enabled */
589 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
592 /* for late to exit */
597 if (pci_mmcfg_check_hostbridge())
602 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
604 pci_mmcfg_reject_broken(early);
606 if (list_empty(&pci_mmcfg_list))
609 if (pci_mmcfg_arch_init())
610 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
613 * Signal not to attempt to insert mmcfg resources because
614 * the architecture mmcfg setup could not initialize.
616 pci_mmcfg_resources_inserted = 1;
620 void __init pci_mmcfg_early_init(void)
625 void __init pci_mmcfg_late_init(void)
630 static int __init pci_mmcfg_late_insert_resources(void)
633 * If resources are already inserted or we are not using MMCONFIG,
634 * don't insert the resources.
636 if ((pci_mmcfg_resources_inserted == 1) ||
637 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
638 list_empty(&pci_mmcfg_list))
642 * Attempt to insert the mmcfg resources but not with the busy flag
643 * marked so it won't cause request errors when __request_region is
646 pci_mmcfg_insert_resources();
652 * Perform MMCONFIG resource insertion after PCI initialization to allow for
653 * misprogrammed MCFG tables that state larger sizes but actually conflict
654 * with other system resources.
656 late_initcall(pci_mmcfg_late_insert_resources);