2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/sfi_acpi.h>
16 #include <linux/bitmap.h>
17 #include <linux/dmi.h>
18 #include <linux/slab.h>
19 #include <linux/mutex.h>
20 #include <linux/rculist.h>
22 #include <asm/pci_x86.h>
25 #define PREFIX "PCI: "
27 /* Indicate if the mmcfg resources have been placed into the resource table. */
28 static bool pci_mmcfg_running_state;
29 static bool pci_mmcfg_arch_init_failed;
30 static DEFINE_MUTEX(pci_mmcfg_lock);
32 LIST_HEAD(pci_mmcfg_list);
34 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
37 release_resource(&cfg->res);
42 static void __init free_all_mmcfg(void)
44 struct pci_mmcfg_region *cfg, *tmp;
46 pci_mmcfg_arch_free();
47 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
48 pci_mmconfig_remove(cfg);
51 static void list_add_sorted(struct pci_mmcfg_region *new)
53 struct pci_mmcfg_region *cfg;
55 /* keep list sorted by segment and starting bus number */
56 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
57 if (cfg->segment > new->segment ||
58 (cfg->segment == new->segment &&
59 cfg->start_bus >= new->start_bus)) {
60 list_add_tail_rcu(&new->list, &cfg->list);
64 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
67 static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
70 struct pci_mmcfg_region *new;
76 new = kzalloc(sizeof(*new), GFP_KERNEL);
81 new->segment = segment;
82 new->start_bus = start;
86 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
87 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
88 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
89 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
90 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
91 res->name = new->name;
96 static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
99 struct pci_mmcfg_region *new;
101 new = pci_mmconfig_alloc(segment, start, end, addr);
103 mutex_lock(&pci_mmcfg_lock);
104 list_add_sorted(new);
105 mutex_unlock(&pci_mmcfg_lock);
108 "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
110 segment, start, end, &new->res, (unsigned long)addr);
116 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
118 struct pci_mmcfg_region *cfg;
120 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
121 if (cfg->segment == segment &&
122 cfg->start_bus <= bus && bus <= cfg->end_bus)
128 static const char *__init pci_mmcfg_e7520(void)
131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
134 if (win == 0x0000 || win == 0xf000)
137 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
140 return "Intel Corporation E7520 Memory Controller Hub";
143 static const char *__init pci_mmcfg_intel_945(void)
145 u32 pciexbar, mask = 0, len = 0;
147 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
154 switch ((pciexbar >> 1) & 3) {
171 /* Errata #2, things break when not aligned on a 256Mb boundary */
172 /* Can only happen in 64M/128M mode */
174 if ((pciexbar & mask) & 0x0fffffffU)
177 /* Don't hit the APIC registers and their friends */
178 if ((pciexbar & mask) >= 0xf0000000U)
181 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
184 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
187 static const char *__init pci_mmcfg_amd_fam10h(void)
189 u32 low, high, address;
192 unsigned segnbits = 0, busnbits, end_bus;
194 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
197 address = MSR_FAM10H_MMIO_CONF_BASE;
198 if (rdmsr_safe(address, &low, &high))
205 /* mmconfig is not enable */
206 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
209 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
211 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
212 FAM10H_MMIO_CONF_BUSRANGE_MASK;
215 * only handle bus 0 ?
222 segnbits = busnbits - 8;
226 end_bus = (1 << busnbits) - 1;
227 for (i = 0; i < (1 << segnbits); i++)
228 if (pci_mmconfig_add(i, 0, end_bus,
229 base + (1<<28) * i) == NULL) {
234 return "AMD Family 10h NB";
237 static bool __initdata mcp55_checked;
238 static const char *__init pci_mmcfg_nvidia_mcp55(void)
241 int mcp55_mmconf_found = 0;
243 static const u32 extcfg_regnum __initconst = 0x90;
244 static const u32 extcfg_regsize __initconst = 4;
245 static const u32 extcfg_enable_mask __initconst = 1 << 31;
246 static const u32 extcfg_start_mask __initconst = 0xff << 16;
247 static const int extcfg_start_shift __initconst = 16;
248 static const u32 extcfg_size_mask __initconst = 0x3 << 28;
249 static const int extcfg_size_shift __initconst = 28;
250 static const int extcfg_sizebus[] __initconst = {
251 0x100, 0x80, 0x40, 0x20
253 static const u32 extcfg_base_mask[] __initconst = {
254 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
256 static const int extcfg_base_lshift __initconst = 25;
259 * do check if amd fam10h already took over
261 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
264 mcp55_checked = true;
265 for (bus = 0; bus < 256; bus++) {
269 int start, size_index, end;
271 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
273 device = (l >> 16) & 0xffff;
275 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
278 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
279 extcfg_regsize, &extcfg);
281 if (!(extcfg & extcfg_enable_mask))
284 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
285 base = extcfg & extcfg_base_mask[size_index];
286 /* base could > 4G */
287 base <<= extcfg_base_lshift;
288 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
289 end = start + extcfg_sizebus[size_index] - 1;
290 if (pci_mmconfig_add(0, start, end, base) == NULL)
292 mcp55_mmconf_found++;
295 if (!mcp55_mmconf_found)
298 return "nVidia MCP55";
301 struct pci_mmcfg_hostbridge_probe {
306 const char *(*probe)(void);
309 static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
310 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
311 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
312 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
313 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
314 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
315 0x1200, pci_mmcfg_amd_fam10h },
316 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
317 0x1200, pci_mmcfg_amd_fam10h },
318 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
319 0x0369, pci_mmcfg_nvidia_mcp55 },
322 static void __init pci_mmcfg_check_end_bus_number(void)
324 struct pci_mmcfg_region *cfg, *cfgx;
327 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
328 if (cfg->end_bus < cfg->start_bus)
331 /* Don't access the list head ! */
332 if (cfg->list.next == &pci_mmcfg_list)
335 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
336 if (cfg->end_bus >= cfgx->start_bus)
337 cfg->end_bus = cfgx->start_bus - 1;
341 static int __init pci_mmcfg_check_hostbridge(void)
354 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
355 bus = pci_mmcfg_probes[i].bus;
356 devfn = pci_mmcfg_probes[i].devfn;
357 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
359 device = (l >> 16) & 0xffff;
362 if (pci_mmcfg_probes[i].vendor == vendor &&
363 pci_mmcfg_probes[i].device == device)
364 name = pci_mmcfg_probes[i].probe();
367 pr_info(PREFIX "%s with MMCONFIG support\n", name);
370 /* some end_bus_number is crazy, fix it */
371 pci_mmcfg_check_end_bus_number();
373 return !list_empty(&pci_mmcfg_list);
376 static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
378 struct resource *mcfg_res = data;
379 struct acpi_resource_address64 address;
382 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
383 struct acpi_resource_fixed_memory32 *fixmem32 =
384 &res->data.fixed_memory32;
387 if ((mcfg_res->start >= fixmem32->address) &&
388 (mcfg_res->end < (fixmem32->address +
389 fixmem32->address_length))) {
391 return AE_CTRL_TERMINATE;
394 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
395 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
398 status = acpi_resource_to_address64(res, &address);
399 if (ACPI_FAILURE(status) ||
400 (address.address.address_length <= 0) ||
401 (address.resource_type != ACPI_MEMORY_RANGE))
404 if ((mcfg_res->start >= address.address.minimum) &&
405 (mcfg_res->end < (address.address.minimum + address.address.address_length))) {
407 return AE_CTRL_TERMINATE;
412 static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
413 void *context, void **rv)
415 struct resource *mcfg_res = context;
417 acpi_walk_resources(handle, METHOD_NAME__CRS,
418 check_mcfg_resource, context);
421 return AE_CTRL_TERMINATE;
426 static int is_acpi_reserved(u64 start, u64 end, unsigned not_used)
428 struct resource mcfg_res;
430 mcfg_res.start = start;
431 mcfg_res.end = end - 1;
434 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
437 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
440 return mcfg_res.flags;
443 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
445 static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
446 struct pci_mmcfg_region *cfg,
447 struct device *dev, int with_e820)
449 u64 addr = cfg->res.start;
450 u64 size = resource_size(&cfg->res);
453 char *method = with_e820 ? "E820" : "ACPI motherboard resources";
455 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
457 if (size < (16UL<<20))
461 if (size < (16UL<<20) && size != old_size)
465 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
468 pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
471 if (old_size != size) {
473 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
474 num_buses = cfg->end_bus - cfg->start_bus + 1;
475 cfg->res.end = cfg->res.start +
476 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
477 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
478 "PCI MMCONFIG %04x [bus %02x-%02x]",
479 cfg->segment, cfg->start_bus, cfg->end_bus);
484 "at %pR (base %#lx) (size reduced!)\n",
485 &cfg->res, (unsigned long) cfg->address);
488 "MMCONFIG for %04x [bus%02x-%02x] "
489 "at %pR (base %#lx) (size reduced!)\n",
490 cfg->segment, cfg->start_bus, cfg->end_bus,
491 &cfg->res, (unsigned long) cfg->address);
497 static int __ref pci_mmcfg_check_reserved(struct device *dev,
498 struct pci_mmcfg_region *cfg, int early)
500 if (!early && !acpi_disabled) {
501 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
505 dev_info(dev, FW_INFO
506 "MMCONFIG at %pR not reserved in "
507 "ACPI motherboard resources\n",
510 pr_info(FW_INFO PREFIX
511 "MMCONFIG at %pR not reserved in "
512 "ACPI motherboard resources\n",
517 * e820_all_mapped() is marked as __init.
518 * All entries from ACPI MCFG table have been checked at boot time.
519 * For MCFG information constructed from hotpluggable host bridge's
520 * _CBA method, just assume it's reserved.
522 if (pci_mmcfg_running_state)
525 /* Don't try to do this check unless configuration
526 type 1 is available. how about type 2 ?*/
528 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
533 static void __init pci_mmcfg_reject_broken(int early)
535 struct pci_mmcfg_region *cfg;
537 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
538 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
539 pr_info(PREFIX "not using MMCONFIG\n");
546 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
547 struct acpi_mcfg_allocation *cfg)
551 if (cfg->address < 0xFFFFFFFF)
554 if (!strncmp(mcfg->header.oem_id, "SGI", 3))
557 if (mcfg->header.revision >= 1) {
558 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
563 pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
564 "is above 4GB, ignored\n", cfg->pci_segment,
565 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
569 static int __init pci_parse_mcfg(struct acpi_table_header *header)
571 struct acpi_table_mcfg *mcfg;
572 struct acpi_mcfg_allocation *cfg_table, *cfg;
579 mcfg = (struct acpi_table_mcfg *)header;
581 /* how many config structures do we have */
584 i = header->length - sizeof(struct acpi_table_mcfg);
585 while (i >= sizeof(struct acpi_mcfg_allocation)) {
587 i -= sizeof(struct acpi_mcfg_allocation);
590 pr_err(PREFIX "MMCONFIG has no entries\n");
594 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
595 for (i = 0; i < entries; i++) {
597 if (acpi_mcfg_check_entry(mcfg, cfg)) {
602 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
603 cfg->end_bus_number, cfg->address) == NULL) {
604 pr_warn(PREFIX "no memory for MCFG entries\n");
613 #ifdef CONFIG_ACPI_APEI
614 extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
615 void *data), void *data);
617 static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
618 void *data), void *data)
620 struct pci_mmcfg_region *cfg;
623 if (list_empty(&pci_mmcfg_list))
626 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
627 rc = func(cfg->res.start, resource_size(&cfg->res), data);
634 #define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
636 #define set_apei_filter()
639 static void __init __pci_mmcfg_init(int early)
641 pci_mmcfg_reject_broken(early);
642 if (list_empty(&pci_mmcfg_list))
645 if (pcibios_last_bus < 0) {
646 const struct pci_mmcfg_region *cfg;
648 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
651 pcibios_last_bus = cfg->end_bus;
655 if (pci_mmcfg_arch_init())
656 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
659 pci_mmcfg_arch_init_failed = true;
663 static int __initdata known_bridge;
665 void __init pci_mmcfg_early_init(void)
667 if (pci_probe & PCI_PROBE_MMCONF) {
668 if (pci_mmcfg_check_hostbridge())
671 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
678 void __init pci_mmcfg_late_init(void)
680 /* MMCONFIG disabled */
681 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
687 /* MMCONFIG hasn't been enabled yet, try again */
688 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
689 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
694 static int __init pci_mmcfg_late_insert_resources(void)
696 struct pci_mmcfg_region *cfg;
698 pci_mmcfg_running_state = true;
700 /* If we are not using MMCONFIG, don't insert the resources. */
701 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
705 * Attempt to insert the mmcfg resources but not with the busy flag
706 * marked so it won't cause request errors when __request_region is
709 list_for_each_entry(cfg, &pci_mmcfg_list, list)
710 if (!cfg->res.parent)
711 insert_resource(&iomem_resource, &cfg->res);
717 * Perform MMCONFIG resource insertion after PCI initialization to allow for
718 * misprogrammed MCFG tables that state larger sizes but actually conflict
719 * with other system resources.
721 late_initcall(pci_mmcfg_late_insert_resources);
723 /* Add MMCFG information for host bridges */
724 int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
728 struct resource *tmp = NULL;
729 struct pci_mmcfg_region *cfg;
731 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
737 mutex_lock(&pci_mmcfg_lock);
738 cfg = pci_mmconfig_lookup(seg, start);
740 if (cfg->end_bus < end)
741 dev_info(dev, FW_INFO
743 "domain %04x [bus %02x-%02x] "
744 "only partially covers this bridge\n",
745 cfg->segment, cfg->start_bus, cfg->end_bus);
746 mutex_unlock(&pci_mmcfg_lock);
751 mutex_unlock(&pci_mmcfg_lock);
756 cfg = pci_mmconfig_alloc(seg, start, end, addr);
758 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
760 } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
761 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
764 /* Insert resource if it's not in boot stage */
765 if (pci_mmcfg_running_state)
766 tmp = insert_resource_conflict(&iomem_resource,
771 "MMCONFIG %pR conflicts with "
773 &cfg->res, tmp->name, tmp);
774 } else if (pci_mmcfg_arch_map(cfg)) {
775 dev_warn(dev, "fail to map MMCONFIG %pR.\n",
778 list_add_sorted(cfg);
779 dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
780 &cfg->res, (unsigned long)addr);
788 release_resource(&cfg->res);
792 mutex_unlock(&pci_mmcfg_lock);
797 /* Delete MMCFG information for host bridges */
798 int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
800 struct pci_mmcfg_region *cfg;
802 mutex_lock(&pci_mmcfg_lock);
803 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
804 if (cfg->segment == seg && cfg->start_bus == start &&
805 cfg->end_bus == end) {
806 list_del_rcu(&cfg->list);
808 pci_mmcfg_arch_unmap(cfg);
810 release_resource(&cfg->res);
811 mutex_unlock(&pci_mmcfg_lock);
815 mutex_unlock(&pci_mmcfg_lock);