2 * numaq_32.c - Low-level PCI access for NUMA-Q machines
6 #include <linux/init.h>
7 #include <linux/nodemask.h>
9 #include <asm/mpspec.h>
10 #include <asm/pci_x86.h>
11 #include <asm/numaq.h>
13 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
15 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
17 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
19 #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
20 (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
22 static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
24 unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
26 writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
31 static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
32 unsigned int devfn, int reg, int len, u32 *value)
35 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
37 if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
40 spin_lock_irqsave(&pci_config_lock, flags);
42 write_cf8(bus, devfn, reg);
47 *value = readb(adr + (reg & 3));
49 *value = inb(0xCFC + (reg & 3));
53 *value = readw(adr + (reg & 2));
55 *value = inw(0xCFC + (reg & 2));
65 spin_unlock_irqrestore(&pci_config_lock, flags);
70 static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
71 unsigned int devfn, int reg, int len, u32 value)
74 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
76 if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
79 spin_lock_irqsave(&pci_config_lock, flags);
81 write_cf8(bus, devfn, reg);
86 writeb(value, adr + (reg & 3));
88 outb((u8)value, 0xCFC + (reg & 3));
92 writew(value, adr + (reg & 2));
94 outw((u16)value, 0xCFC + (reg & 2));
98 writel(value, adr + reg);
100 outl((u32)value, 0xCFC);
104 spin_unlock_irqrestore(&pci_config_lock, flags);
109 #undef PCI_CONF1_MQ_ADDRESS
111 static struct pci_raw_ops pci_direct_conf1_mq = {
112 .read = pci_conf1_mq_read,
113 .write = pci_conf1_mq_write
117 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
120 * i450NX -- Find and scan all secondary buses on all PXB's.
123 u8 busno, suba, subb;
124 int quad = BUS2QUAD(d->bus->number);
126 dev_info(&d->dev, "searching for i450NX host bridges\n");
128 for(pxb=0; pxb<2; pxb++) {
129 pci_read_config_byte(d, reg++, &busno);
130 pci_read_config_byte(d, reg++, &suba);
131 pci_read_config_byte(d, reg++, &subb);
132 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
133 pxb, busno, suba, subb);
136 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
140 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
143 pcibios_last_bus = -1;
145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
147 int __init pci_numaq_init(void)
154 raw_pci_ops = &pci_direct_conf1_mq;
156 if (pcibios_scanned++)
159 pci_root_bus = pcibios_scan_root(0);
161 pci_bus_add_devices(pci_root_bus);
162 if (num_online_nodes() > 1)
163 for_each_online_node(quad) {
166 printk("Scanning PCI bus %d for quad %d\n",
167 QUADLOCAL2BUS(quad,0), quad);
168 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));