2 * mrst.c: Intel Moorestown platform specific setup code
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) "mrst: " fmt
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/scatterlist.h>
19 #include <linux/sfi.h>
20 #include <linux/intel_pmic_gpio.h>
21 #include <linux/spi/spi.h>
22 #include <linux/i2c.h>
23 #include <linux/i2c/pca953x.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/platform_device.h>
27 #include <linux/irq.h>
28 #include <linux/module.h>
29 #include <linux/notifier.h>
30 #include <linux/mfd/intel_msic.h>
32 #include <asm/setup.h>
33 #include <asm/mpspec_def.h>
34 #include <asm/hw_irq.h>
36 #include <asm/io_apic.h>
38 #include <asm/mrst-vrtc.h>
40 #include <asm/i8259.h>
41 #include <asm/intel_scu_ipc.h>
42 #include <asm/apb_timer.h>
43 #include <asm/reboot.h>
46 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
47 * cmdline option x86_mrst_timer can be used to override the configuration
48 * to prefer one or the other.
49 * at runtime, there are basically three timer configurations:
50 * 1. per cpu apbt clock only
51 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
52 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
54 * by default (without cmdline option), platform code first detects cpu type
55 * to see if we are on lincroft or penwell, then set up both lapic or apbt
57 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
58 * config #3 is supported but not recommended on medfield.
60 * rating and feature summary:
61 * lapic (with C3STOP) --------- 100
62 * apbt (always-on) ------------ 110
63 * lapic (always-on,ARAT) ------ 150
66 __cpuinitdata enum mrst_timer_options mrst_timer_options;
68 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
69 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
70 enum mrst_cpu_type __mrst_cpu_chip;
71 EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
75 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
76 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
79 static void mrst_power_off(void)
81 if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
82 intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1);
85 static void mrst_reboot(void)
87 if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
88 intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
90 intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
93 /* parse all the mtimer info to a static mtimer array */
94 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
96 struct sfi_table_simple *sb;
97 struct sfi_timer_table_entry *pentry;
98 struct mpc_intsrc mp_irq;
101 sb = (struct sfi_table_simple *)table;
102 if (!sfi_mtimer_num) {
103 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
104 struct sfi_timer_table_entry);
105 pentry = (struct sfi_timer_table_entry *) sb->pentry;
106 totallen = sfi_mtimer_num * sizeof(*pentry);
107 memcpy(sfi_mtimer_array, pentry, totallen);
110 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
111 pentry = sfi_mtimer_array;
112 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
113 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
114 " irq = %d\n", totallen, (u32)pentry->phys_addr,
115 pentry->freq_hz, pentry->irq);
118 mp_irq.type = MP_INTSRC;
119 mp_irq.irqtype = mp_INT;
120 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
122 mp_irq.srcbus = MP_BUS_ISA;
123 mp_irq.srcbusirq = pentry->irq; /* IRQ */
124 mp_irq.dstapic = MP_APIC_ALL;
125 mp_irq.dstirq = pentry->irq;
126 mp_save_irq(&mp_irq);
132 struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
135 if (hint < sfi_mtimer_num) {
136 if (!sfi_mtimer_usage[hint]) {
137 pr_debug("hint taken for timer %d irq %d\n",\
138 hint, sfi_mtimer_array[hint].irq);
139 sfi_mtimer_usage[hint] = 1;
140 return &sfi_mtimer_array[hint];
143 /* take the first timer available */
144 for (i = 0; i < sfi_mtimer_num;) {
145 if (!sfi_mtimer_usage[i]) {
146 sfi_mtimer_usage[i] = 1;
147 return &sfi_mtimer_array[i];
154 void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
157 for (i = 0; i < sfi_mtimer_num;) {
158 if (mtmr->irq == sfi_mtimer_array[i].irq) {
159 sfi_mtimer_usage[i] = 0;
166 /* parse all the mrtc info to a global mrtc array */
167 int __init sfi_parse_mrtc(struct sfi_table_header *table)
169 struct sfi_table_simple *sb;
170 struct sfi_rtc_table_entry *pentry;
171 struct mpc_intsrc mp_irq;
175 sb = (struct sfi_table_simple *)table;
177 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
178 struct sfi_rtc_table_entry);
179 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
180 totallen = sfi_mrtc_num * sizeof(*pentry);
181 memcpy(sfi_mrtc_array, pentry, totallen);
184 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
185 pentry = sfi_mrtc_array;
186 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
187 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
188 totallen, (u32)pentry->phys_addr, pentry->irq);
189 mp_irq.type = MP_INTSRC;
190 mp_irq.irqtype = mp_INT;
191 mp_irq.irqflag = 0xf; /* level trigger and active low */
192 mp_irq.srcbus = MP_BUS_ISA;
193 mp_irq.srcbusirq = pentry->irq; /* IRQ */
194 mp_irq.dstapic = MP_APIC_ALL;
195 mp_irq.dstirq = pentry->irq;
196 mp_save_irq(&mp_irq);
201 static unsigned long __init mrst_calibrate_tsc(void)
203 unsigned long flags, fast_calibrate;
204 if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
205 u32 lo, hi, ratio, fsb;
207 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
208 pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
209 ratio = (hi >> 8) & 0x1f;
210 pr_debug("ratio is %d\n", ratio);
212 pr_err("read a zero ratio, should be incorrect!\n");
213 pr_err("force tsc ratio to 16 ...\n");
216 rdmsr(MSR_FSB_FREQ, lo, hi);
217 if ((lo & 0x7) == 0x7)
218 fsb = PENWELL_FSB_FREQ_83SKU;
220 fsb = PENWELL_FSB_FREQ_100SKU;
221 fast_calibrate = ratio * fsb;
222 pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
223 lapic_timer_frequency = fsb * 1000 / HZ;
224 /* mark tsc clocksource as reliable */
225 set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
227 local_irq_save(flags);
228 fast_calibrate = apbt_quick_calibrate();
229 local_irq_restore(flags);
233 return fast_calibrate;
238 static void __init mrst_time_init(void)
240 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
241 switch (mrst_timer_options) {
242 case MRST_TIMER_APBT_ONLY:
244 case MRST_TIMER_LAPIC_APBT:
245 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
246 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
249 if (!boot_cpu_has(X86_FEATURE_ARAT))
251 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
252 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
255 /* we need at least one APB timer */
256 pre_init_apic_IRQ0();
260 static void __cpuinit mrst_arch_setup(void)
262 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
263 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
264 else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
265 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
267 pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
268 boot_cpu_data.x86, boot_cpu_data.x86_model);
269 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
271 pr_debug("Moorestown CPU %s identified\n",
272 (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
273 "Lincroft" : "Penwell");
276 /* MID systems don't have i8042 controller */
277 static int mrst_i8042_detect(void)
283 * Moorestown does not have external NMI source nor port 0x61 to report
284 * NMI status. The possible NMI sources are from pmu as a result of NMI
285 * watchdog or lock debug. Reading io port 0x61 results in 0xff which
286 * misled NMI handler.
288 static unsigned char mrst_get_nmi_reason(void)
294 * Moorestown specific x86_init function overrides and early setup
297 void __init x86_mrst_early_setup(void)
299 x86_init.resources.probe_roms = x86_init_noop;
300 x86_init.resources.reserve_resources = x86_init_noop;
302 x86_init.timers.timer_init = mrst_time_init;
303 x86_init.timers.setup_percpu_clockev = x86_init_noop;
305 x86_init.irqs.pre_vector_init = x86_init_noop;
307 x86_init.oem.arch_setup = mrst_arch_setup;
309 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
311 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
312 x86_platform.i8042_detect = mrst_i8042_detect;
313 x86_init.timers.wallclock_init = mrst_rtc_init;
314 x86_platform.get_nmi_reason = mrst_get_nmi_reason;
316 x86_init.pci.init = pci_mrst_init;
317 x86_init.pci.fixup_irqs = x86_init_noop;
319 legacy_pic = &null_legacy_pic;
321 /* Moorestown specific power_off/restart method */
322 pm_power_off = mrst_power_off;
323 machine_ops.emergency_restart = mrst_reboot;
325 /* Avoid searching for BIOS MP tables */
326 x86_init.mpparse.find_smp_config = x86_init_noop;
327 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
328 set_bit(MP_BUS_ISA, mp_bus_not_pci);
332 * if user does not want to use per CPU apb timer, just give it a lower rating
333 * than local apic timer and skip the late per cpu timer init.
335 static inline int __init setup_x86_mrst_timer(char *arg)
340 if (strcmp("apbt_only", arg) == 0)
341 mrst_timer_options = MRST_TIMER_APBT_ONLY;
342 else if (strcmp("lapic_and_apbt", arg) == 0)
343 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
345 pr_warning("X86 MRST timer option %s not recognised"
346 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
352 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
355 * Parsing GPIO table first, since the DEVS table will need this table
356 * to map the pin name to the actual pin.
358 static struct sfi_gpio_table_entry *gpio_table;
359 static int gpio_num_entry;
361 static int __init sfi_parse_gpio(struct sfi_table_header *table)
363 struct sfi_table_simple *sb;
364 struct sfi_gpio_table_entry *pentry;
369 sb = (struct sfi_table_simple *)table;
370 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
371 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
373 gpio_table = (struct sfi_gpio_table_entry *)
374 kmalloc(num * sizeof(*pentry), GFP_KERNEL);
377 memcpy(gpio_table, pentry, num * sizeof(*pentry));
378 gpio_num_entry = num;
380 pr_debug("GPIO pin info:\n");
381 for (i = 0; i < num; i++, pentry++)
382 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
384 pentry->controller_name,
390 static int get_gpio_by_name(const char *name)
392 struct sfi_gpio_table_entry *pentry = gpio_table;
397 for (i = 0; i < gpio_num_entry; i++, pentry++) {
398 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
399 return pentry->pin_no;
405 * Here defines the array of devices platform data that IAFW would export
406 * through SFI "DEVS" table, we use name and type to match the device and
410 char name[SFI_NAME_LEN + 1];
413 void *(*get_platform_data)(void *info);
416 /* the offset for the mapping of global gpio pin to irq */
417 #define MRST_IRQ_OFFSET 0x100
419 static void __init *pmic_gpio_platform_data(void *info)
421 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
422 int gpio_base = get_gpio_by_name("pmic_gpio_base");
426 pmic_gpio_pdata.gpio_base = gpio_base;
427 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
428 pmic_gpio_pdata.gpiointr = 0xffffeff8;
430 return &pmic_gpio_pdata;
433 static void __init *max3111_platform_data(void *info)
435 struct spi_board_info *spi_info = info;
436 int intr = get_gpio_by_name("max3111_int");
438 spi_info->mode = SPI_MODE_0;
441 spi_info->irq = intr + MRST_IRQ_OFFSET;
445 /* we have multiple max7315 on the board ... */
446 #define MAX7315_NUM 2
447 static void __init *max7315_platform_data(void *info)
449 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
451 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
452 struct i2c_board_info *i2c_info = info;
454 char base_pin_name[SFI_NAME_LEN + 1];
455 char intr_pin_name[SFI_NAME_LEN + 1];
457 if (nr == MAX7315_NUM) {
458 pr_err("too many max7315s, we only support %d\n",
462 /* we have several max7315 on the board, we only need load several
463 * instances of the same pca953x driver to cover them
465 strcpy(i2c_info->type, "max7315");
467 sprintf(base_pin_name, "max7315_%d_base", nr);
468 sprintf(intr_pin_name, "max7315_%d_int", nr);
470 strcpy(base_pin_name, "max7315_base");
471 strcpy(intr_pin_name, "max7315_int");
474 gpio_base = get_gpio_by_name(base_pin_name);
475 intr = get_gpio_by_name(intr_pin_name);
479 max7315->gpio_base = gpio_base;
481 i2c_info->irq = intr + MRST_IRQ_OFFSET;
482 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
485 max7315->irq_base = -1;
490 static void *tca6416_platform_data(void *info)
492 static struct pca953x_platform_data tca6416;
493 struct i2c_board_info *i2c_info = info;
495 char base_pin_name[SFI_NAME_LEN + 1];
496 char intr_pin_name[SFI_NAME_LEN + 1];
498 strcpy(i2c_info->type, "tca6416");
499 strcpy(base_pin_name, "tca6416_base");
500 strcpy(intr_pin_name, "tca6416_int");
502 gpio_base = get_gpio_by_name(base_pin_name);
503 intr = get_gpio_by_name(intr_pin_name);
507 tca6416.gpio_base = gpio_base;
509 i2c_info->irq = intr + MRST_IRQ_OFFSET;
510 tca6416.irq_base = gpio_base + MRST_IRQ_OFFSET;
513 tca6416.irq_base = -1;
518 static void *mpu3050_platform_data(void *info)
520 struct i2c_board_info *i2c_info = info;
521 int intr = get_gpio_by_name("mpu3050_int");
526 i2c_info->irq = intr + MRST_IRQ_OFFSET;
530 static void __init *emc1403_platform_data(void *info)
532 static short intr2nd_pdata;
533 struct i2c_board_info *i2c_info = info;
534 int intr = get_gpio_by_name("thermal_int");
535 int intr2nd = get_gpio_by_name("thermal_alert");
537 if (intr == -1 || intr2nd == -1)
540 i2c_info->irq = intr + MRST_IRQ_OFFSET;
541 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
543 return &intr2nd_pdata;
546 static void __init *lis331dl_platform_data(void *info)
548 static short intr2nd_pdata;
549 struct i2c_board_info *i2c_info = info;
550 int intr = get_gpio_by_name("accel_int");
551 int intr2nd = get_gpio_by_name("accel_2");
553 if (intr == -1 || intr2nd == -1)
556 i2c_info->irq = intr + MRST_IRQ_OFFSET;
557 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
559 return &intr2nd_pdata;
562 static void __init *no_platform_data(void *info)
567 static struct resource msic_resources[] = {
569 .start = INTEL_MSIC_IRQ_PHYS_BASE,
570 .end = INTEL_MSIC_IRQ_PHYS_BASE + 64 - 1,
571 .flags = IORESOURCE_MEM,
575 static struct intel_msic_platform_data msic_pdata;
577 static struct platform_device msic_device = {
578 .name = "intel_msic",
581 .platform_data = &msic_pdata,
583 .num_resources = ARRAY_SIZE(msic_resources),
584 .resource = msic_resources,
587 static inline bool mrst_has_msic(void)
589 return mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL;
592 static int msic_scu_status_change(struct notifier_block *nb,
593 unsigned long code, void *data)
595 if (code == SCU_DOWN) {
596 platform_device_unregister(&msic_device);
600 return platform_device_register(&msic_device);
603 static int __init msic_init(void)
605 static struct notifier_block msic_scu_notifier = {
606 .notifier_call = msic_scu_status_change,
610 * We need to be sure that the SCU IPC is ready before MSIC device
614 intel_scu_notifier_add(&msic_scu_notifier);
618 arch_initcall(msic_init);
621 * msic_generic_platform_data - sets generic platform data for the block
622 * @info: pointer to the SFI device table entry for this block
625 * Function sets IRQ number from the SFI table entry for given device to
626 * the MSIC platform data.
628 static void *msic_generic_platform_data(void *info, enum intel_msic_block block)
630 struct sfi_device_table_entry *entry = info;
632 BUG_ON(block < 0 || block >= INTEL_MSIC_BLOCK_LAST);
633 msic_pdata.irq[block] = entry->irq;
635 return no_platform_data(info);
638 static void *msic_battery_platform_data(void *info)
640 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_BATTERY);
643 static void *msic_gpio_platform_data(void *info)
645 static struct intel_msic_gpio_pdata pdata;
646 int gpio = get_gpio_by_name("msic_gpio_base");
651 pdata.gpio_base = gpio;
652 msic_pdata.gpio = &pdata;
654 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_GPIO);
657 static void *msic_audio_platform_data(void *info)
659 struct platform_device *pdev;
661 pdev = platform_device_register_simple("sst-platform", -1, NULL, 0);
663 pr_err("failed to create audio platform device\n");
667 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_AUDIO);
670 static void *msic_power_btn_platform_data(void *info)
672 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_POWER_BTN);
675 static void *msic_ocd_platform_data(void *info)
677 static struct intel_msic_ocd_pdata pdata;
678 int gpio = get_gpio_by_name("ocd_gpio");
684 msic_pdata.ocd = &pdata;
686 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_OCD);
689 static const struct devs_id __initconst device_ids[] = {
690 {"bma023", SFI_DEV_TYPE_I2C, 1, &no_platform_data},
691 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
692 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
693 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
694 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
695 {"tca6416", SFI_DEV_TYPE_I2C, 1, &tca6416_platform_data},
696 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
697 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
698 {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
699 {"mpu3050", SFI_DEV_TYPE_I2C, 1, &mpu3050_platform_data},
701 /* MSIC subdevices */
702 {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data},
703 {"msic_gpio", SFI_DEV_TYPE_IPC, 1, &msic_gpio_platform_data},
704 {"msic_audio", SFI_DEV_TYPE_IPC, 1, &msic_audio_platform_data},
705 {"msic_power_btn", SFI_DEV_TYPE_IPC, 1, &msic_power_btn_platform_data},
706 {"msic_ocd", SFI_DEV_TYPE_IPC, 1, &msic_ocd_platform_data},
711 #define MAX_IPCDEVS 24
712 static struct platform_device *ipc_devs[MAX_IPCDEVS];
713 static int ipc_next_dev;
715 #define MAX_SCU_SPI 24
716 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
717 static int spi_next_dev;
719 #define MAX_SCU_I2C 24
720 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
721 static int i2c_bus[MAX_SCU_I2C];
722 static int i2c_next_dev;
724 static void __init intel_scu_device_register(struct platform_device *pdev)
726 if(ipc_next_dev == MAX_IPCDEVS)
727 pr_err("too many SCU IPC devices");
729 ipc_devs[ipc_next_dev++] = pdev;
732 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
734 struct spi_board_info *new_dev;
736 if (spi_next_dev == MAX_SCU_SPI) {
737 pr_err("too many SCU SPI devices");
741 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
743 pr_err("failed to alloc mem for delayed spi dev %s\n",
747 memcpy(new_dev, sdev, sizeof(*sdev));
749 spi_devs[spi_next_dev++] = new_dev;
752 static void __init intel_scu_i2c_device_register(int bus,
753 struct i2c_board_info *idev)
755 struct i2c_board_info *new_dev;
757 if (i2c_next_dev == MAX_SCU_I2C) {
758 pr_err("too many SCU I2C devices");
762 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
764 pr_err("failed to alloc mem for delayed i2c dev %s\n",
768 memcpy(new_dev, idev, sizeof(*idev));
770 i2c_bus[i2c_next_dev] = bus;
771 i2c_devs[i2c_next_dev++] = new_dev;
774 BLOCKING_NOTIFIER_HEAD(intel_scu_notifier);
775 EXPORT_SYMBOL_GPL(intel_scu_notifier);
777 /* Called by IPC driver */
778 void intel_scu_devices_create(void)
782 for (i = 0; i < ipc_next_dev; i++)
783 platform_device_add(ipc_devs[i]);
785 for (i = 0; i < spi_next_dev; i++)
786 spi_register_board_info(spi_devs[i], 1);
788 for (i = 0; i < i2c_next_dev; i++) {
789 struct i2c_adapter *adapter;
790 struct i2c_client *client;
792 adapter = i2c_get_adapter(i2c_bus[i]);
794 client = i2c_new_device(adapter, i2c_devs[i]);
796 pr_err("can't create i2c device %s\n",
799 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
801 intel_scu_notifier_post(SCU_AVAILABLE, 0L);
803 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
805 /* Called by IPC driver */
806 void intel_scu_devices_destroy(void)
810 intel_scu_notifier_post(SCU_DOWN, 0L);
812 for (i = 0; i < ipc_next_dev; i++)
813 platform_device_del(ipc_devs[i]);
815 EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
817 static void __init install_irq_resource(struct platform_device *pdev, int irq)
819 /* Single threaded */
820 static struct resource __initdata res = {
822 .flags = IORESOURCE_IRQ,
825 platform_device_add_resources(pdev, &res, 1);
828 static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *entry)
830 const struct devs_id *dev = device_ids;
831 struct platform_device *pdev;
834 while (dev->name[0]) {
835 if (dev->type == SFI_DEV_TYPE_IPC &&
836 !strncmp(dev->name, entry->name, SFI_NAME_LEN)) {
837 pdata = dev->get_platform_data(entry);
844 * On Medfield the platform device creation is handled by the MSIC
845 * MFD driver so we don't need to do it here.
850 /* ID as IRQ is a hack that will go away */
851 pdev = platform_device_alloc(entry->name, entry->irq);
853 pr_err("out of memory for SFI platform device '%s'.\n",
857 install_irq_resource(pdev, entry->irq);
859 pdev->dev.platform_data = pdata;
860 intel_scu_device_register(pdev);
863 static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
865 const struct devs_id *dev = device_ids;
868 while (dev->name[0]) {
869 if (dev->type == SFI_DEV_TYPE_SPI &&
870 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
871 pdata = dev->get_platform_data(spi_info);
876 spi_info->platform_data = pdata;
878 intel_scu_spi_device_register(spi_info);
880 spi_register_board_info(spi_info, 1);
883 static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
885 const struct devs_id *dev = device_ids;
888 while (dev->name[0]) {
889 if (dev->type == SFI_DEV_TYPE_I2C &&
890 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
891 pdata = dev->get_platform_data(i2c_info);
896 i2c_info->platform_data = pdata;
899 intel_scu_i2c_device_register(bus, i2c_info);
901 i2c_register_board_info(bus, i2c_info, 1);
905 static int __init sfi_parse_devs(struct sfi_table_header *table)
907 struct sfi_table_simple *sb;
908 struct sfi_device_table_entry *pentry;
909 struct spi_board_info spi_info;
910 struct i2c_board_info i2c_info;
913 struct io_apic_irq_attr irq_attr;
915 sb = (struct sfi_table_simple *)table;
916 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
917 pentry = (struct sfi_device_table_entry *)sb->pentry;
919 for (i = 0; i < num; i++, pentry++) {
920 int irq = pentry->irq;
922 if (irq != (u8)0xff) { /* native RTE case */
923 /* these SPI2 devices are not exposed to system as PCI
924 * devices, but they have separate RTE entry in IOAPIC
925 * so we have to enable them one by one here
927 ioapic = mp_find_ioapic(irq);
928 irq_attr.ioapic = ioapic;
929 irq_attr.ioapic_pin = irq;
930 irq_attr.trigger = 1;
931 irq_attr.polarity = 1;
932 io_apic_set_pci_routing(NULL, irq, &irq_attr);
934 irq = 0; /* No irq */
936 switch (pentry->type) {
937 case SFI_DEV_TYPE_IPC:
938 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
939 "irq = 0x%2x\n", i, pentry->name, pentry->irq);
940 sfi_handle_ipc_dev(pentry);
942 case SFI_DEV_TYPE_SPI:
943 memset(&spi_info, 0, sizeof(spi_info));
944 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
946 spi_info.bus_num = pentry->host_num;
947 spi_info.chip_select = pentry->addr;
948 spi_info.max_speed_hz = pentry->max_freq;
949 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
950 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
954 spi_info.max_speed_hz,
955 spi_info.chip_select);
956 sfi_handle_spi_dev(&spi_info);
958 case SFI_DEV_TYPE_I2C:
959 memset(&i2c_info, 0, sizeof(i2c_info));
960 bus = pentry->host_num;
961 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
963 i2c_info.addr = pentry->addr;
964 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
965 "irq = 0x%2x, addr = 0x%x\n", i, bus,
969 sfi_handle_i2c_dev(bus, &i2c_info);
971 case SFI_DEV_TYPE_UART:
972 case SFI_DEV_TYPE_HSI:
980 static int __init mrst_platform_init(void)
982 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
983 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
986 arch_initcall(mrst_platform_init);
989 * we will search these buttons in SFI GPIO table (by name)
990 * and register them dynamically. Please add all possible
991 * buttons here, we will shrink them if no GPIO found.
993 static struct gpio_keys_button gpio_button[] = {
994 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
995 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
996 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
997 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
998 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
999 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
1000 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
1001 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
1002 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
1003 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
1006 static struct gpio_keys_platform_data mrst_gpio_keys = {
1007 .buttons = gpio_button,
1009 .nbuttons = -1, /* will fill it after search */
1012 static struct platform_device pb_device = {
1013 .name = "gpio-keys",
1016 .platform_data = &mrst_gpio_keys,
1021 * Shrink the non-existent buttons, register the gpio button
1022 * device if there is some
1024 static int __init pb_keys_init(void)
1026 struct gpio_keys_button *gb = gpio_button;
1027 int i, num, good = 0;
1029 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
1030 for (i = 0; i < num; i++) {
1031 gb[i].gpio = get_gpio_by_name(gb[i].desc);
1032 if (gb[i].gpio == -1)
1041 mrst_gpio_keys.nbuttons = good;
1042 return platform_device_register(&pb_device);
1046 late_initcall(pb_keys_init);