2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <asm/proto.h>
39 #include <asm/calgary.h>
41 #include <asm/pci-direct.h>
42 #include <asm/system.h>
46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
47 int use_calgary __read_mostly = 1;
49 int use_calgary __read_mostly = 0;
50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
53 #define PCI_VENDOR_DEVICE_ID_CALGARY \
54 (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
56 /* we need these for register space address calculation */
57 #define START_ADDRESS 0xfe000000
58 #define CHASSIS_BASE 0
59 #define ONE_BASED_CHASSIS_NUM 1
61 /* register offsets inside the host bridge space */
62 #define CALGARY_CONFIG_REG 0x0108
63 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
64 #define PHB_PLSSR_OFFSET 0x0120
65 #define PHB_CONFIG_RW_OFFSET 0x0160
66 #define PHB_IOBASE_BAR_LOW 0x0170
67 #define PHB_IOBASE_BAR_HIGH 0x0180
68 #define PHB_MEM_1_LOW 0x0190
69 #define PHB_MEM_1_HIGH 0x01A0
70 #define PHB_IO_ADDR_SIZE 0x01B0
71 #define PHB_MEM_1_SIZE 0x01C0
72 #define PHB_MEM_ST_OFFSET 0x01D0
73 #define PHB_AER_OFFSET 0x0200
74 #define PHB_CONFIG_0_HIGH 0x0220
75 #define PHB_CONFIG_0_LOW 0x0230
76 #define PHB_CONFIG_0_END 0x0240
77 #define PHB_MEM_2_LOW 0x02B0
78 #define PHB_MEM_2_HIGH 0x02C0
79 #define PHB_MEM_2_SIZE_HIGH 0x02D0
80 #define PHB_MEM_2_SIZE_LOW 0x02E0
81 #define PHB_DOSHOLE_OFFSET 0x08E0
84 #define PHB_TCE_ENABLE 0x20000000
85 #define PHB_SLOT_DISABLE 0x1C000000
86 #define PHB_DAC_DISABLE 0x01000000
87 #define PHB_MEM2_ENABLE 0x00400000
88 #define PHB_MCSR_ENABLE 0x00100000
89 /* TAR (Table Address Register) */
90 #define TAR_SW_BITS 0x0000ffffffff800fUL
91 #define TAR_VALID 0x0000000000000008UL
92 /* CSR (Channel/DMA Status Register) */
93 #define CSR_AGENT_MASK 0xffe0ffff
94 /* CCR (Calgary Configuration Register) */
95 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
97 #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
98 #define MAX_NUM_CHASSIS 8 /* max number of chassis */
99 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
100 #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
101 #define PHBS_PER_CALGARY 4
103 /* register offsets in Calgary's internal register space */
104 static const unsigned long tar_offsets[] = {
111 static const unsigned long split_queue_offsets[] = {
112 0x4870 /* SPLIT QUEUE 0 */,
113 0x5870 /* SPLIT QUEUE 1 */,
114 0x6870 /* SPLIT QUEUE 2 */,
115 0x7870 /* SPLIT QUEUE 3 */
118 static const unsigned long phb_offsets[] = {
125 /* PHB debug registers */
127 static const unsigned long phb_debug_offsets[] = {
128 0x4000 /* PHB 0 DEBUG */,
129 0x5000 /* PHB 1 DEBUG */,
130 0x6000 /* PHB 2 DEBUG */,
131 0x7000 /* PHB 3 DEBUG */
135 * STUFF register for each debug PHB,
136 * byte 1 = start bus number, byte 2 = end bus number
139 #define PHB_DEBUG_STUFF_OFFSET 0x0020
141 #define EMERGENCY_PAGES 32 /* = 128KB */
143 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
144 static int translate_empty_slots __read_mostly = 0;
145 static int calgary_detected __read_mostly = 0;
147 static struct rio_table_hdr *rio_table_hdr __initdata;
148 static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
149 static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
151 struct calgary_bus_info {
153 unsigned char translation_disabled;
158 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
160 static void tce_cache_blast(struct iommu_table *tbl);
162 /* enable this to stress test the chip's TCE cache */
163 #ifdef CONFIG_IOMMU_DEBUG
164 int debugging __read_mostly = 1;
166 static inline unsigned long verify_bit_range(unsigned long* bitmap,
167 int expected, unsigned long start, unsigned long end)
169 unsigned long idx = start;
171 BUG_ON(start >= end);
174 if (!!test_bit(idx, bitmap) != expected)
179 /* all bits have the expected value */
182 #else /* debugging is disabled */
183 int debugging __read_mostly = 0;
185 static inline unsigned long verify_bit_range(unsigned long* bitmap,
186 int expected, unsigned long start, unsigned long end)
190 #endif /* CONFIG_IOMMU_DEBUG */
192 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
196 npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
197 npages >>= PAGE_SHIFT;
202 static inline int translate_phb(struct pci_dev* dev)
204 int disabled = bus_info[dev->bus->number].translation_disabled;
208 static void iommu_range_reserve(struct iommu_table *tbl,
209 unsigned long start_addr, unsigned int npages)
213 unsigned long badbit;
215 index = start_addr >> PAGE_SHIFT;
217 /* bail out if we're asked to reserve a region we don't cover */
218 if (index >= tbl->it_size)
221 end = index + npages;
222 if (end > tbl->it_size) /* don't go off the table */
225 badbit = verify_bit_range(tbl->it_map, 0, index, end);
226 if (badbit != ~0UL) {
227 if (printk_ratelimit())
228 printk(KERN_ERR "Calgary: entry already allocated at "
229 "0x%lx tbl %p dma 0x%lx npages %u\n",
230 badbit, tbl, start_addr, npages);
233 set_bit_string(tbl->it_map, index, npages);
236 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
239 unsigned long offset;
243 offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
244 tbl->it_size, npages);
245 if (offset == ~0UL) {
246 tce_cache_blast(tbl);
247 offset = find_next_zero_string(tbl->it_map, 0,
248 tbl->it_size, npages);
249 if (offset == ~0UL) {
250 printk(KERN_WARNING "Calgary: IOMMU full.\n");
251 if (panic_on_overflow)
252 panic("Calgary: fix the allocator.\n");
254 return bad_dma_address;
258 set_bit_string(tbl->it_map, offset, npages);
259 tbl->it_hint = offset + npages;
260 BUG_ON(tbl->it_hint > tbl->it_size);
265 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
266 unsigned int npages, int direction)
268 unsigned long entry, flags;
269 dma_addr_t ret = bad_dma_address;
271 spin_lock_irqsave(&tbl->it_lock, flags);
273 entry = iommu_range_alloc(tbl, npages);
275 if (unlikely(entry == bad_dma_address))
278 /* set the return dma address */
279 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
281 /* put the TCEs in the HW table */
282 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
285 spin_unlock_irqrestore(&tbl->it_lock, flags);
290 spin_unlock_irqrestore(&tbl->it_lock, flags);
291 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
292 "iommu %p\n", npages, tbl);
293 return bad_dma_address;
296 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
300 unsigned long badbit;
301 unsigned long badend;
303 /* were we called with bad_dma_address? */
304 badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
305 if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
306 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
307 "address 0x%Lx\n", dma_addr);
312 entry = dma_addr >> PAGE_SHIFT;
314 BUG_ON(entry + npages > tbl->it_size);
316 tce_free(tbl, entry, npages);
318 badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
319 if (badbit != ~0UL) {
320 if (printk_ratelimit())
321 printk(KERN_ERR "Calgary: bit is off at 0x%lx "
322 "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
323 badbit, tbl, dma_addr, entry, npages);
326 __clear_bit_string(tbl->it_map, entry, npages);
329 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
334 spin_lock_irqsave(&tbl->it_lock, flags);
336 __iommu_free(tbl, dma_addr, npages);
338 spin_unlock_irqrestore(&tbl->it_lock, flags);
341 static void __calgary_unmap_sg(struct iommu_table *tbl,
342 struct scatterlist *sglist, int nelems, int direction)
346 dma_addr_t dma = sglist->dma_address;
347 unsigned int dmalen = sglist->dma_length;
352 npages = num_dma_pages(dma, dmalen);
353 __iommu_free(tbl, dma, npages);
358 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
359 int nelems, int direction)
362 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
364 if (!translate_phb(to_pci_dev(dev)))
367 spin_lock_irqsave(&tbl->it_lock, flags);
369 __calgary_unmap_sg(tbl, sglist, nelems, direction);
371 spin_unlock_irqrestore(&tbl->it_lock, flags);
374 static int calgary_nontranslate_map_sg(struct device* dev,
375 struct scatterlist *sg, int nelems, int direction)
379 for (i = 0; i < nelems; i++ ) {
380 struct scatterlist *s = &sg[i];
382 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
383 s->dma_length = s->length;
388 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
389 int nelems, int direction)
391 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
398 if (!translate_phb(to_pci_dev(dev)))
399 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
401 spin_lock_irqsave(&tbl->it_lock, flags);
403 for (i = 0; i < nelems; i++ ) {
404 struct scatterlist *s = &sg[i];
407 vaddr = (unsigned long)page_address(s->page) + s->offset;
408 npages = num_dma_pages(vaddr, s->length);
410 entry = iommu_range_alloc(tbl, npages);
411 if (entry == bad_dma_address) {
412 /* makes sure unmap knows to stop */
417 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
419 /* insert into HW table */
420 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
423 s->dma_length = s->length;
426 spin_unlock_irqrestore(&tbl->it_lock, flags);
430 __calgary_unmap_sg(tbl, sg, nelems, direction);
431 for (i = 0; i < nelems; i++) {
432 sg[i].dma_address = bad_dma_address;
433 sg[i].dma_length = 0;
435 spin_unlock_irqrestore(&tbl->it_lock, flags);
439 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
440 size_t size, int direction)
442 dma_addr_t dma_handle = bad_dma_address;
445 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
447 uaddr = (unsigned long)vaddr;
448 npages = num_dma_pages(uaddr, size);
450 if (translate_phb(to_pci_dev(dev)))
451 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
453 dma_handle = virt_to_bus(vaddr);
458 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
459 size_t size, int direction)
461 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
464 if (!translate_phb(to_pci_dev(dev)))
467 npages = num_dma_pages(dma_handle, size);
468 iommu_free(tbl, dma_handle, npages);
471 void* calgary_alloc_coherent(struct device *dev, size_t size,
472 dma_addr_t *dma_handle, gfp_t flag)
476 unsigned int npages, order;
477 struct iommu_table *tbl;
479 tbl = to_pci_dev(dev)->bus->self->sysdata;
481 size = PAGE_ALIGN(size); /* size rounded up to full pages */
482 npages = size >> PAGE_SHIFT;
483 order = get_order(size);
485 /* alloc enough pages (and possibly more) */
486 ret = (void *)__get_free_pages(flag, order);
489 memset(ret, 0, size);
491 if (translate_phb(to_pci_dev(dev))) {
492 /* set up tces to cover the allocated range */
493 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
494 if (mapping == bad_dma_address)
497 *dma_handle = mapping;
498 } else /* non translated slot */
499 *dma_handle = virt_to_bus(ret);
504 free_pages((unsigned long)ret, get_order(size));
510 static const struct dma_mapping_ops calgary_dma_ops = {
511 .alloc_coherent = calgary_alloc_coherent,
512 .map_single = calgary_map_single,
513 .unmap_single = calgary_unmap_single,
514 .map_sg = calgary_map_sg,
515 .unmap_sg = calgary_unmap_sg,
518 static inline void __iomem * busno_to_bbar(unsigned char num)
520 return bus_info[num].bbar;
523 static inline int busno_to_phbid(unsigned char num)
525 return bus_info[num].phbid;
528 static inline unsigned long split_queue_offset(unsigned char num)
530 size_t idx = busno_to_phbid(num);
532 return split_queue_offsets[idx];
535 static inline unsigned long tar_offset(unsigned char num)
537 size_t idx = busno_to_phbid(num);
539 return tar_offsets[idx];
542 static inline unsigned long phb_offset(unsigned char num)
544 size_t idx = busno_to_phbid(num);
546 return phb_offsets[idx];
549 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
551 unsigned long target = ((unsigned long)bar) | offset;
552 return (void __iomem*)target;
555 static void tce_cache_blast(struct iommu_table *tbl)
560 void __iomem *bbar = tbl->bbar;
561 void __iomem *target;
563 /* disable arbitration on the bus */
564 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
568 /* read plssr to ensure it got there */
569 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
572 /* poll split queues until all DMA activity is done */
573 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
577 } while ((val & 0xff) != 0xff && i < 100);
579 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
580 "continuing anyway\n");
582 /* invalidate TCE cache */
583 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
584 writeq(tbl->tar_val, target);
586 /* enable arbitration */
587 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
589 (void)readl(target); /* flush */
592 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
595 unsigned int numpages;
597 limit = limit | 0xfffff;
600 numpages = ((limit - start) >> PAGE_SHIFT);
601 iommu_range_reserve(dev->sysdata, start, numpages);
604 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
606 void __iomem *target;
607 u64 low, high, sizelow;
609 struct iommu_table *tbl = dev->sysdata;
610 unsigned char busnum = dev->bus->number;
611 void __iomem *bbar = tbl->bbar;
613 /* peripheral MEM_1 region */
614 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
615 low = be32_to_cpu(readl(target));
616 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
617 high = be32_to_cpu(readl(target));
618 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
619 sizelow = be32_to_cpu(readl(target));
621 start = (high << 32) | low;
624 calgary_reserve_mem_region(dev, start, limit);
627 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
629 void __iomem *target;
631 u64 low, high, sizelow, sizehigh;
633 struct iommu_table *tbl = dev->sysdata;
634 unsigned char busnum = dev->bus->number;
635 void __iomem *bbar = tbl->bbar;
638 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
639 val32 = be32_to_cpu(readl(target));
640 if (!(val32 & PHB_MEM2_ENABLE))
643 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
644 low = be32_to_cpu(readl(target));
645 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
646 high = be32_to_cpu(readl(target));
647 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
648 sizelow = be32_to_cpu(readl(target));
649 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
650 sizehigh = be32_to_cpu(readl(target));
652 start = (high << 32) | low;
653 limit = (sizehigh << 32) | sizelow;
655 calgary_reserve_mem_region(dev, start, limit);
659 * some regions of the IO address space do not get translated, so we
660 * must not give devices IO addresses in those regions. The regions
661 * are the 640KB-1MB region and the two PCI peripheral memory holes.
662 * Reserve all of them in the IOMMU bitmap to avoid giving them out
665 static void __init calgary_reserve_regions(struct pci_dev *dev)
669 struct iommu_table *tbl = dev->sysdata;
671 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
672 iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
674 /* avoid the BIOS/VGA first 640KB-1MB region */
675 start = (640 * 1024);
676 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
677 iommu_range_reserve(tbl, start, npages);
679 /* reserve the two PCI peripheral memory regions in IO space */
680 calgary_reserve_peripheral_mem_1(dev);
681 calgary_reserve_peripheral_mem_2(dev);
684 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
688 void __iomem *target;
690 struct iommu_table *tbl;
692 /* build TCE tables for each PHB */
693 ret = build_tce_table(dev, bbar);
698 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
699 tce_free(tbl, 0, tbl->it_size);
701 calgary_reserve_regions(dev);
703 /* set TARs for each PHB */
704 target = calgary_reg(bbar, tar_offset(dev->bus->number));
705 val64 = be64_to_cpu(readq(target));
707 /* zero out all TAR bits under sw control */
708 val64 &= ~TAR_SW_BITS;
711 table_phys = (u64)__pa(tbl->it_base);
714 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
715 val64 |= (u64) specified_table_size;
717 tbl->tar_val = cpu_to_be64(val64);
718 writeq(tbl->tar_val, target);
719 readq(target); /* flush */
724 static void __init calgary_free_bus(struct pci_dev *dev)
727 struct iommu_table *tbl = dev->sysdata;
728 void __iomem *target;
729 unsigned int bitmapsz;
731 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
732 val64 = be64_to_cpu(readq(target));
733 val64 &= ~TAR_SW_BITS;
734 writeq(cpu_to_be64(val64), target);
735 readq(target); /* flush */
737 bitmapsz = tbl->it_size / BITS_PER_BYTE;
738 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
744 /* Can't free bootmem allocated memory after system is up :-( */
745 bus_info[dev->bus->number].tce_space = NULL;
748 static void calgary_watchdog(unsigned long data)
750 struct pci_dev *dev = (struct pci_dev *)data;
751 struct iommu_table *tbl = dev->sysdata;
752 void __iomem *bbar = tbl->bbar;
754 void __iomem *target;
756 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
757 val32 = be32_to_cpu(readl(target));
759 /* If no error, the agent ID in the CSR is not valid */
760 if (val32 & CSR_AGENT_MASK) {
761 printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, "
762 "CSR = %#x\n", dev->bus->number, val32);
765 /* Disable bus that caused the error */
766 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
767 PHB_CONFIG_RW_OFFSET);
768 val32 = be32_to_cpu(readl(target));
769 val32 |= PHB_SLOT_DISABLE;
770 writel(cpu_to_be32(val32), target);
771 readl(target); /* flush */
773 /* Reset the timer */
774 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
778 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
779 unsigned char busnum, unsigned long timeout)
782 void __iomem *target;
783 unsigned int phb_shift = ~0; /* silence gcc */
786 switch (busno_to_phbid(busnum)) {
787 case 0: phb_shift = (63 - 19);
789 case 1: phb_shift = (63 - 23);
791 case 2: phb_shift = (63 - 27);
793 case 3: phb_shift = (63 - 35);
796 BUG_ON(busno_to_phbid(busnum));
799 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
800 val64 = be64_to_cpu(readq(target));
802 /* zero out this PHB's timer bits */
803 mask = ~(0xFUL << phb_shift);
805 val64 |= (timeout << phb_shift);
806 writeq(cpu_to_be64(val64), target);
807 readq(target); /* flush */
810 static void __init calgary_handle_quirks(struct pci_dev* dev)
812 unsigned char busnum = dev->bus->number;
813 struct iommu_table *tbl = dev->sysdata;
816 * Give split completion a longer timeout on bus 1 for aic94xx
817 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
820 calgary_set_split_completion_timeout(tbl->bbar, busnum,
824 static void __init calgary_enable_translation(struct pci_dev *dev)
827 unsigned char busnum;
828 void __iomem *target;
830 struct iommu_table *tbl;
832 busnum = dev->bus->number;
836 /* enable TCE in PHB Config Register */
837 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
838 val32 = be32_to_cpu(readl(target));
839 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
841 printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum);
842 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
845 writel(cpu_to_be32(val32), target);
846 readl(target); /* flush */
848 init_timer(&tbl->watchdog_timer);
849 tbl->watchdog_timer.function = &calgary_watchdog;
850 tbl->watchdog_timer.data = (unsigned long)dev;
851 mod_timer(&tbl->watchdog_timer, jiffies);
854 static void __init calgary_disable_translation(struct pci_dev *dev)
857 unsigned char busnum;
858 void __iomem *target;
860 struct iommu_table *tbl;
862 busnum = dev->bus->number;
866 /* disable TCE in PHB Config Register */
867 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
868 val32 = be32_to_cpu(readl(target));
869 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
871 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
872 writel(cpu_to_be32(val32), target);
873 readl(target); /* flush */
875 del_timer_sync(&tbl->watchdog_timer);
878 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
882 dev->bus->self = dev;
885 static int __init calgary_init_one(struct pci_dev *dev)
890 BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
892 bbar = busno_to_bbar(dev->bus->number);
893 ret = calgary_setup_tar(dev, bbar);
898 dev->bus->self = dev;
900 calgary_handle_quirks(dev);
902 calgary_enable_translation(dev);
910 static int __init calgary_locate_bbars(void)
913 int rioidx, phb, bus;
915 void __iomem *target;
916 unsigned long offset;
917 u8 start_bus, end_bus;
921 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
922 struct rio_detail *rio = rio_devs[rioidx];
924 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
927 /* map entire 1MB of Calgary config space */
928 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
932 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
933 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
934 target = calgary_reg(bbar, offset);
936 val = be32_to_cpu(readl(target));
937 start_bus = (u8)((val & 0x00FF0000) >> 16);
938 end_bus = (u8)((val & 0x0000FF00) >> 8);
939 for (bus = start_bus; bus <= end_bus; bus++) {
940 bus_info[bus].bbar = bbar;
941 bus_info[bus].phbid = phb;
949 /* scan bus_info and iounmap any bbars we previously ioremap'd */
950 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
951 if (bus_info[bus].bbar)
952 iounmap(bus_info[bus].bbar);
957 static int __init calgary_init(void)
960 struct pci_dev *dev = NULL;
962 ret = calgary_locate_bbars();
967 dev = pci_get_device(PCI_VENDOR_ID_IBM,
968 PCI_DEVICE_ID_IBM_CALGARY,
972 if (!translate_phb(dev)) {
973 calgary_init_one_nontraslated(dev);
976 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
979 ret = calgary_init_one(dev);
988 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
989 PCI_DEVICE_ID_IBM_CALGARY,
993 if (!translate_phb(dev)) {
997 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1000 calgary_disable_translation(dev);
1001 calgary_free_bus(dev);
1002 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1008 static inline int __init determine_tce_table_size(u64 ram)
1012 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1013 return specified_table_size;
1016 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1017 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1018 * larger table size has twice as many entries, so shift the
1019 * max ram address by 13 to divide by 8K and then look at the
1020 * order of the result to choose between 0-7.
1022 ret = get_order(ram >> 13);
1023 if (ret > TCE_TABLE_SIZE_8M)
1024 ret = TCE_TABLE_SIZE_8M;
1029 static int __init build_detail_arrays(void)
1032 int i, scal_detail_size, rio_detail_size;
1034 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1036 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1037 "but system has %d nodes.\n",
1038 MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1042 switch (rio_table_hdr->version){
1044 scal_detail_size = 11;
1045 rio_detail_size = 13;
1048 scal_detail_size = 12;
1049 rio_detail_size = 15;
1053 "Calgary: Invalid Rio Grande Table Version: %d\n",
1054 rio_table_hdr->version);
1058 ptr = ((unsigned long)rio_table_hdr) + 3;
1059 for (i = 0; i < rio_table_hdr->num_scal_dev;
1060 i++, ptr += scal_detail_size)
1061 scal_devs[i] = (struct scal_detail *)ptr;
1063 for (i = 0; i < rio_table_hdr->num_rio_dev;
1064 i++, ptr += rio_detail_size)
1065 rio_devs[i] = (struct rio_detail *)ptr;
1070 void __init detect_calgary(void)
1075 int calgary_found = 0;
1077 unsigned int offset, prev_offset;
1081 * if the user specified iommu=off or iommu=soft or we found
1082 * another HW IOMMU already, bail out.
1084 if (swiotlb || no_iommu || iommu_detected)
1090 if (!early_pci_allowed())
1093 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1095 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1097 rio_table_hdr = NULL;
1101 * The next offset is stored in the 1st word.
1102 * Only parse up until the offset increases:
1104 while (offset > prev_offset) {
1105 /* The block id is stored in the 2nd word */
1106 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1107 /* set the pointer past the offset & block id */
1108 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1111 prev_offset = offset;
1112 offset = *((unsigned short *)(ptr + offset));
1114 if (!rio_table_hdr) {
1115 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1116 "in EBDA - bailing!\n");
1120 ret = build_detail_arrays();
1122 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1126 specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1128 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1130 struct calgary_bus_info *info = &bus_info[bus];
1132 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
1135 if (info->translation_disabled)
1139 * Scan the slots of the PCI bus to see if there is a device present.
1140 * The parent bus will be the zero-ith device, so start at 1.
1142 for (dev = 1; dev < 8; dev++) {
1143 val = read_pci_config(bus, dev, 0, 0);
1144 if (val != 0xffffffff || translate_empty_slots) {
1145 tbl = alloc_tce_table();
1148 info->tce_space = tbl;
1155 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1156 calgary_found ? "found" : "not found");
1158 if (calgary_found) {
1160 calgary_detected = 1;
1161 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1162 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1163 "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1164 debugging ? "enabled" : "disabled");
1169 for (--bus; bus >= 0; --bus) {
1170 struct calgary_bus_info *info = &bus_info[bus];
1172 if (info->tce_space)
1173 free_tce_table(info->tce_space);
1177 int __init calgary_iommu_init(void)
1181 if (no_iommu || swiotlb)
1184 if (!calgary_detected)
1187 /* ok, we're trying to use Calgary - let's roll */
1188 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1190 ret = calgary_init();
1192 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1193 "falling back to no_iommu\n", ret);
1194 if (end_pfn > MAX_DMA32_PFN)
1195 printk(KERN_ERR "WARNING more than 4GB of memory, "
1196 "32bit PCI may malfunction.\n");
1201 bad_dma_address = 0x0;
1202 dma_ops = &calgary_dma_ops;
1207 static int __init calgary_parse_options(char *p)
1209 unsigned int bridge;
1214 if (!strncmp(p, "64k", 3))
1215 specified_table_size = TCE_TABLE_SIZE_64K;
1216 else if (!strncmp(p, "128k", 4))
1217 specified_table_size = TCE_TABLE_SIZE_128K;
1218 else if (!strncmp(p, "256k", 4))
1219 specified_table_size = TCE_TABLE_SIZE_256K;
1220 else if (!strncmp(p, "512k", 4))
1221 specified_table_size = TCE_TABLE_SIZE_512K;
1222 else if (!strncmp(p, "1M", 2))
1223 specified_table_size = TCE_TABLE_SIZE_1M;
1224 else if (!strncmp(p, "2M", 2))
1225 specified_table_size = TCE_TABLE_SIZE_2M;
1226 else if (!strncmp(p, "4M", 2))
1227 specified_table_size = TCE_TABLE_SIZE_4M;
1228 else if (!strncmp(p, "8M", 2))
1229 specified_table_size = TCE_TABLE_SIZE_8M;
1231 len = strlen("translate_empty_slots");
1232 if (!strncmp(p, "translate_empty_slots", len))
1233 translate_empty_slots = 1;
1235 len = strlen("disable");
1236 if (!strncmp(p, "disable", len)) {
1242 bridge = simple_strtol(p, &endp, 0);
1246 if (bridge < MAX_PHB_BUS_NUM) {
1247 printk(KERN_INFO "Calgary: disabling "
1248 "translation for PHB %#x\n", bridge);
1249 bus_info[bridge].translation_disabled = 1;
1253 p = strpbrk(p, ",");
1261 __setup("calgary=", calgary_parse_options);