2 * linux/arch/x86-64/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
11 * This file handles the architecture-dependent parts of initialization
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
18 #include <linux/stddef.h>
19 #include <linux/unistd.h>
20 #include <linux/ptrace.h>
21 #include <linux/slab.h>
22 #include <linux/user.h>
23 #include <linux/a.out.h>
24 #include <linux/screen_info.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/initrd.h>
29 #include <linux/highmem.h>
30 #include <linux/bootmem.h>
31 #include <linux/module.h>
32 #include <asm/processor.h>
33 #include <linux/console.h>
34 #include <linux/seq_file.h>
35 #include <linux/crash_dump.h>
36 #include <linux/root_dev.h>
37 #include <linux/pci.h>
38 #include <linux/acpi.h>
39 #include <linux/kallsyms.h>
40 #include <linux/edd.h>
41 #include <linux/mmzone.h>
42 #include <linux/kexec.h>
43 #include <linux/cpufreq.h>
44 #include <linux/dmi.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/ctype.h>
49 #include <asm/uaccess.h>
50 #include <asm/system.h>
55 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/bootsetup.h>
61 #include <asm/proto.h>
62 #include <asm/setup.h>
63 #include <asm/mach_apic.h>
65 #include <asm/sections.h>
72 struct cpuinfo_x86 boot_cpu_data __read_mostly;
73 EXPORT_SYMBOL(boot_cpu_data);
75 unsigned long mmu_cr4_features;
77 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
80 unsigned long saved_video_mode;
86 char dmi_alloc_data[DMI_MAX_DATA];
91 struct screen_info screen_info;
92 EXPORT_SYMBOL(screen_info);
93 struct sys_desc_table_struct {
94 unsigned short length;
95 unsigned char table[0];
98 struct edid_info edid_info;
99 EXPORT_SYMBOL_GPL(edid_info);
101 extern int root_mountflags;
103 char __initdata command_line[COMMAND_LINE_SIZE];
105 struct resource standard_io_resources[] = {
106 { .name = "dma1", .start = 0x00, .end = 0x1f,
107 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
108 { .name = "pic1", .start = 0x20, .end = 0x21,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "timer0", .start = 0x40, .end = 0x43,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "timer1", .start = 0x50, .end = 0x53,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "keyboard", .start = 0x60, .end = 0x6f,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "pic2", .start = 0xa0, .end = 0xa1,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "dma2", .start = 0xc0, .end = 0xdf,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "fpu", .start = 0xf0, .end = 0xff,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
126 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
128 struct resource data_resource = {
129 .name = "Kernel data",
132 .flags = IORESOURCE_RAM,
134 struct resource code_resource = {
135 .name = "Kernel code",
138 .flags = IORESOURCE_RAM,
141 #define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
143 static struct resource system_rom_resource = {
144 .name = "System ROM",
147 .flags = IORESOURCE_ROM,
150 static struct resource extension_rom_resource = {
151 .name = "Extension ROM",
154 .flags = IORESOURCE_ROM,
157 static struct resource adapter_rom_resources[] = {
158 { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
159 .flags = IORESOURCE_ROM },
160 { .name = "Adapter ROM", .start = 0, .end = 0,
161 .flags = IORESOURCE_ROM },
162 { .name = "Adapter ROM", .start = 0, .end = 0,
163 .flags = IORESOURCE_ROM },
164 { .name = "Adapter ROM", .start = 0, .end = 0,
165 .flags = IORESOURCE_ROM },
166 { .name = "Adapter ROM", .start = 0, .end = 0,
167 .flags = IORESOURCE_ROM },
168 { .name = "Adapter ROM", .start = 0, .end = 0,
169 .flags = IORESOURCE_ROM }
172 static struct resource video_rom_resource = {
176 .flags = IORESOURCE_ROM,
179 static struct resource video_ram_resource = {
180 .name = "Video RAM area",
183 .flags = IORESOURCE_RAM,
186 #define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
188 static int __init romchecksum(unsigned char *rom, unsigned long length)
190 unsigned char *p, sum = 0;
192 for (p = rom; p < rom + length; p++)
197 static void __init probe_roms(void)
199 unsigned long start, length, upper;
204 upper = adapter_rom_resources[0].start;
205 for (start = video_rom_resource.start; start < upper; start += 2048) {
206 rom = isa_bus_to_virt(start);
207 if (!romsignature(rom))
210 video_rom_resource.start = start;
212 /* 0 < length <= 0x7f * 512, historically */
213 length = rom[2] * 512;
215 /* if checksum okay, trust length byte */
216 if (length && romchecksum(rom, length))
217 video_rom_resource.end = start + length - 1;
219 request_resource(&iomem_resource, &video_rom_resource);
223 start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
228 request_resource(&iomem_resource, &system_rom_resource);
229 upper = system_rom_resource.start;
231 /* check for extension rom (ignore length byte!) */
232 rom = isa_bus_to_virt(extension_rom_resource.start);
233 if (romsignature(rom)) {
234 length = extension_rom_resource.end - extension_rom_resource.start + 1;
235 if (romchecksum(rom, length)) {
236 request_resource(&iomem_resource, &extension_rom_resource);
237 upper = extension_rom_resource.start;
241 /* check for adapter roms on 2k boundaries */
242 for (i = 0; i < ARRAY_SIZE(adapter_rom_resources) && start < upper;
244 rom = isa_bus_to_virt(start);
245 if (!romsignature(rom))
248 /* 0 < length <= 0x7f * 512, historically */
249 length = rom[2] * 512;
251 /* but accept any length that fits if checksum okay */
252 if (!length || start + length > upper || !romchecksum(rom, length))
255 adapter_rom_resources[i].start = start;
256 adapter_rom_resources[i].end = start + length - 1;
257 request_resource(&iomem_resource, &adapter_rom_resources[i]);
259 start = adapter_rom_resources[i++].end & ~2047UL;
263 #ifdef CONFIG_PROC_VMCORE
264 /* elfcorehdr= specifies the location of elf core header
265 * stored by the crashed kernel. This option will be passed
266 * by kexec loader to the capture kernel.
268 static int __init setup_elfcorehdr(char *arg)
273 elfcorehdr_addr = memparse(arg, &end);
274 return end > arg ? 0 : -EINVAL;
276 early_param("elfcorehdr", setup_elfcorehdr);
281 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
283 unsigned long bootmap_size, bootmap;
285 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
286 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
288 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
289 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
290 e820_register_active_regions(0, start_pfn, end_pfn);
291 free_bootmem_with_active_regions(0, end_pfn);
292 reserve_bootmem(bootmap, bootmap_size);
296 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
298 #ifdef CONFIG_EDD_MODULE
302 * copy_edd() - Copy the BIOS EDD information
303 * from boot_params into a safe place.
306 static inline void copy_edd(void)
308 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
309 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
310 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
311 edd.edd_info_nr = EDD_NR;
314 static inline void copy_edd(void)
319 #define EBDA_ADDR_POINTER 0x40E
321 unsigned __initdata ebda_addr;
322 unsigned __initdata ebda_size;
324 static void discover_ebda(void)
327 * there is a real-mode segmented pointer pointing to the
328 * 4K EBDA area at 0x40E
330 ebda_addr = *(unsigned short *)EBDA_ADDR_POINTER;
333 ebda_size = *(unsigned short *)(unsigned long)ebda_addr;
335 /* Round EBDA up to pages */
339 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
340 if (ebda_size > 64*1024)
344 void __init setup_arch(char **cmdline_p)
346 printk(KERN_INFO "Command line: %s\n", boot_command_line);
348 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
349 screen_info = SCREEN_INFO;
350 edid_info = EDID_INFO;
351 saved_video_mode = SAVED_VIDEO_MODE;
352 bootloader_type = LOADER_TYPE;
354 #ifdef CONFIG_BLK_DEV_RAM
355 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
356 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
357 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
359 setup_memory_region();
362 if (!MOUNT_ROOT_RDONLY)
363 root_mountflags &= ~MS_RDONLY;
364 init_mm.start_code = (unsigned long) &_text;
365 init_mm.end_code = (unsigned long) &_etext;
366 init_mm.end_data = (unsigned long) &_edata;
367 init_mm.brk = (unsigned long) &_end;
369 code_resource.start = virt_to_phys(&_text);
370 code_resource.end = virt_to_phys(&_etext)-1;
371 data_resource.start = virt_to_phys(&_etext);
372 data_resource.end = virt_to_phys(&_edata)-1;
374 early_identify_cpu(&boot_cpu_data);
376 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
377 *cmdline_p = command_line;
381 finish_e820_parsing();
383 e820_register_active_regions(0, 0, -1UL);
385 * partially used pages are not usable - thus
386 * we are rounding upwards:
388 end_pfn = e820_end_of_ram();
389 num_physpages = end_pfn;
395 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
403 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
404 * Call this early for SRAT node setup.
406 acpi_boot_table_init();
409 /* How many end-of-memory variables you have, grandma! */
410 max_low_pfn = end_pfn;
412 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
414 /* Remove active ranges so rediscovery with NUMA-awareness happens */
415 remove_all_active_ranges();
417 #ifdef CONFIG_ACPI_NUMA
419 * Parse SRAT to discover nodes.
425 numa_initmem_init(0, end_pfn);
427 contig_initmem_init(0, end_pfn);
430 /* Reserve direct mapping */
431 reserve_bootmem_generic(table_start << PAGE_SHIFT,
432 (table_end - table_start) << PAGE_SHIFT);
435 reserve_bootmem_generic(__pa_symbol(&_text),
436 __pa_symbol(&_end) - __pa_symbol(&_text));
439 * reserve physical page 0 - it's a special BIOS page on many boxes,
440 * enabling clean reboots, SMP operation, laptop functions.
442 reserve_bootmem_generic(0, PAGE_SIZE);
444 /* reserve ebda region */
446 reserve_bootmem_generic(ebda_addr, ebda_size);
448 /* reserve nodemap region */
450 reserve_bootmem_generic(nodemap_addr, nodemap_size);
455 * But first pinch a few for the stack/trampoline stuff
456 * FIXME: Don't need the extra page at 4K, but need to fix
457 * trampoline before removing it. (see the GDT stuff)
459 reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
461 /* Reserve SMP trampoline */
462 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
465 #ifdef CONFIG_ACPI_SLEEP
467 * Reserve low memory region for sleep support.
469 acpi_reserve_bootmem();
472 * Find and reserve possible boot-time SMP configuration:
475 #ifdef CONFIG_BLK_DEV_INITRD
476 if (LOADER_TYPE && INITRD_START) {
477 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
478 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
479 initrd_start = INITRD_START + PAGE_OFFSET;
480 initrd_end = initrd_start+INITRD_SIZE;
483 printk(KERN_ERR "initrd extends beyond end of memory "
484 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
485 (unsigned long)(INITRD_START + INITRD_SIZE),
486 (unsigned long)(end_pfn << PAGE_SHIFT));
492 if (crashk_res.start != crashk_res.end) {
493 reserve_bootmem_generic(crashk_res.start,
494 crashk_res.end - crashk_res.start + 1);
505 * set this early, so we dont allocate cpu0
506 * if MADT list doesnt list BSP first
507 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
509 cpu_set(0, cpu_present_map);
512 * Read APIC and some other early information from ACPI tables.
520 * get boot-time SMP configuration:
522 if (smp_found_config)
524 init_apic_mappings();
527 * Request address space for all standard RAM and ROM resources
528 * and also for regions reported as reserved by the e820.
531 e820_reserve_resources();
532 e820_mark_nosave_regions();
534 request_resource(&iomem_resource, &video_ram_resource);
538 /* request I/O space for devices used on all i[345]86 PCs */
539 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
540 request_resource(&ioport_resource, &standard_io_resources[i]);
546 #if defined(CONFIG_VGA_CONSOLE)
547 conswitchp = &vga_con;
548 #elif defined(CONFIG_DUMMY_CONSOLE)
549 conswitchp = &dummy_con;
554 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
558 if (c->extended_cpuid_level < 0x80000004)
561 v = (unsigned int *) c->x86_model_id;
562 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
563 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
564 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
565 c->x86_model_id[48] = 0;
570 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
572 unsigned int n, dummy, eax, ebx, ecx, edx;
574 n = c->extended_cpuid_level;
576 if (n >= 0x80000005) {
577 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
578 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
579 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
580 c->x86_cache_size=(ecx>>24)+(edx>>24);
581 /* On K8 L1 TLB is inclusive, so don't count it */
585 if (n >= 0x80000006) {
586 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
587 ecx = cpuid_ecx(0x80000006);
588 c->x86_cache_size = ecx >> 16;
589 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
591 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
592 c->x86_cache_size, ecx & 0xFF);
596 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
597 if (n >= 0x80000008) {
598 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
599 c->x86_virt_bits = (eax >> 8) & 0xff;
600 c->x86_phys_bits = eax & 0xff;
605 static int nearby_node(int apicid)
608 for (i = apicid - 1; i >= 0; i--) {
609 int node = apicid_to_node[i];
610 if (node != NUMA_NO_NODE && node_online(node))
613 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
614 int node = apicid_to_node[i];
615 if (node != NUMA_NO_NODE && node_online(node))
618 return first_node(node_online_map); /* Shouldn't happen */
623 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
624 * Assumes number of cores is a power of two.
626 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
631 int cpu = smp_processor_id();
633 unsigned apicid = hard_smp_processor_id();
635 unsigned ecx = cpuid_ecx(0x80000008);
637 c->x86_max_cores = (ecx & 0xff) + 1;
639 /* CPU telling us the core id bits shift? */
640 bits = (ecx >> 12) & 0xF;
642 /* Otherwise recompute */
644 while ((1 << bits) < c->x86_max_cores)
648 /* Low order bits define the core id (index of core in socket) */
649 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
650 /* Convert the APIC ID into the socket ID */
651 c->phys_proc_id = phys_pkg_id(bits);
654 node = c->phys_proc_id;
655 if (apicid_to_node[apicid] != NUMA_NO_NODE)
656 node = apicid_to_node[apicid];
657 if (!node_online(node)) {
658 /* Two possibilities here:
659 - The CPU is missing memory and no node was created.
660 In that case try picking one from a nearby CPU
661 - The APIC IDs differ from the HyperTransport node IDs
662 which the K8 northbridge parsing fills in.
663 Assume they are all increased by a constant offset,
664 but in the same order as the HT nodeids.
665 If that doesn't result in a usable node fall back to the
666 path for the previous case. */
667 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
668 if (ht_nodeid >= 0 &&
669 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
670 node = apicid_to_node[ht_nodeid];
671 /* Pick a nearby node */
672 if (!node_online(node))
673 node = nearby_node(apicid);
675 numa_set_node(cpu, node);
677 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
682 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
690 * Disable TLB flush filter by setting HWCR.FFDIS on K8
691 * bit 6 of msr C001_0015
693 * Errata 63 for SH-B3 steppings
694 * Errata 122 for all steppings (F+ have it disabled by default)
697 rdmsrl(MSR_K8_HWCR, value);
699 wrmsrl(MSR_K8_HWCR, value);
703 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
704 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
705 clear_bit(0*32+31, &c->x86_capability);
707 /* On C+ stepping K8 rep microcode works well for copy/memset */
708 level = cpuid_eax(1);
709 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
710 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
712 /* Enable workaround for FXSAVE leak */
714 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
716 level = get_model_name(c);
720 /* Should distinguish Models here, but this is only
721 a fallback anyways. */
722 strcpy(c->x86_model_id, "Hammer");
726 display_cacheinfo(c);
728 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
729 if (c->x86_power & (1<<8))
730 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
732 /* Multi core CPU? */
733 if (c->extended_cpuid_level >= 0x80000008)
736 /* Fix cpuid4 emulation for more */
737 num_cache_leaves = 3;
739 /* RDTSC can be speculated around */
740 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
743 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
746 u32 eax, ebx, ecx, edx;
747 int index_msb, core_bits;
749 cpuid(1, &eax, &ebx, &ecx, &edx);
752 if (!cpu_has(c, X86_FEATURE_HT))
754 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
757 smp_num_siblings = (ebx & 0xff0000) >> 16;
759 if (smp_num_siblings == 1) {
760 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
761 } else if (smp_num_siblings > 1 ) {
763 if (smp_num_siblings > NR_CPUS) {
764 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
765 smp_num_siblings = 1;
769 index_msb = get_count_order(smp_num_siblings);
770 c->phys_proc_id = phys_pkg_id(index_msb);
772 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
774 index_msb = get_count_order(smp_num_siblings) ;
776 core_bits = get_count_order(c->x86_max_cores);
778 c->cpu_core_id = phys_pkg_id(index_msb) &
779 ((1 << core_bits) - 1);
782 if ((c->x86_max_cores * smp_num_siblings) > 1) {
783 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
784 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
791 * find out the number of processor cores on the die
793 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
797 if (c->cpuid_level < 4)
800 cpuid_count(4, 0, &eax, &t, &t, &t);
803 return ((eax >> 26) + 1);
808 static void srat_detect_node(void)
812 int cpu = smp_processor_id();
813 int apicid = hard_smp_processor_id();
815 /* Don't do the funky fallback heuristics the AMD version employs
817 node = apicid_to_node[apicid];
818 if (node == NUMA_NO_NODE)
819 node = first_node(node_online_map);
820 numa_set_node(cpu, node);
822 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
826 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
831 init_intel_cacheinfo(c);
832 if (c->cpuid_level > 9 ) {
833 unsigned eax = cpuid_eax(10);
834 /* Check for version and the number of counters */
835 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
836 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
841 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
843 set_bit(X86_FEATURE_BTS, c->x86_capability);
845 set_bit(X86_FEATURE_PEBS, c->x86_capability);
848 n = c->extended_cpuid_level;
849 if (n >= 0x80000008) {
850 unsigned eax = cpuid_eax(0x80000008);
851 c->x86_virt_bits = (eax >> 8) & 0xff;
852 c->x86_phys_bits = eax & 0xff;
853 /* CPUID workaround for Intel 0F34 CPU */
854 if (c->x86_vendor == X86_VENDOR_INTEL &&
855 c->x86 == 0xF && c->x86_model == 0x3 &&
857 c->x86_phys_bits = 36;
861 c->x86_cache_alignment = c->x86_clflush_size * 2;
862 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
863 (c->x86 == 0x6 && c->x86_model >= 0x0e))
864 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
866 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
868 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
870 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
871 c->x86_max_cores = intel_num_cpu_cores(c);
876 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
878 char *v = c->x86_vendor_id;
880 if (!strcmp(v, "AuthenticAMD"))
881 c->x86_vendor = X86_VENDOR_AMD;
882 else if (!strcmp(v, "GenuineIntel"))
883 c->x86_vendor = X86_VENDOR_INTEL;
885 c->x86_vendor = X86_VENDOR_UNKNOWN;
888 struct cpu_model_info {
891 char *model_names[16];
894 /* Do some early cpuid on the boot CPU to get some parameter that are
895 needed before check_bugs. Everything advanced is in identify_cpu
897 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
901 c->loops_per_jiffy = loops_per_jiffy;
902 c->x86_cache_size = -1;
903 c->x86_vendor = X86_VENDOR_UNKNOWN;
904 c->x86_model = c->x86_mask = 0; /* So far unknown... */
905 c->x86_vendor_id[0] = '\0'; /* Unset */
906 c->x86_model_id[0] = '\0'; /* Unset */
907 c->x86_clflush_size = 64;
908 c->x86_cache_alignment = c->x86_clflush_size;
909 c->x86_max_cores = 1;
910 c->extended_cpuid_level = 0;
911 memset(&c->x86_capability, 0, sizeof c->x86_capability);
913 /* Get vendor name */
914 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
915 (unsigned int *)&c->x86_vendor_id[0],
916 (unsigned int *)&c->x86_vendor_id[8],
917 (unsigned int *)&c->x86_vendor_id[4]);
921 /* Initialize the standard set of capabilities */
922 /* Note that the vendor-specific code below might override */
924 /* Intel-defined flags: level 0x00000001 */
925 if (c->cpuid_level >= 0x00000001) {
927 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
928 &c->x86_capability[0]);
929 c->x86 = (tfms >> 8) & 0xf;
930 c->x86_model = (tfms >> 4) & 0xf;
931 c->x86_mask = tfms & 0xf;
933 c->x86 += (tfms >> 20) & 0xff;
935 c->x86_model += ((tfms >> 16) & 0xF) << 4;
936 if (c->x86_capability[0] & (1<<19))
937 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
939 /* Have CPUID level 0 only - unheard of */
944 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
949 * This does the hard work of actually picking apart the CPU stuff...
951 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
956 early_identify_cpu(c);
958 /* AMD-defined flags: level 0x80000001 */
959 xlvl = cpuid_eax(0x80000000);
960 c->extended_cpuid_level = xlvl;
961 if ((xlvl & 0xffff0000) == 0x80000000) {
962 if (xlvl >= 0x80000001) {
963 c->x86_capability[1] = cpuid_edx(0x80000001);
964 c->x86_capability[6] = cpuid_ecx(0x80000001);
966 if (xlvl >= 0x80000004)
967 get_model_name(c); /* Default name */
970 /* Transmeta-defined flags: level 0x80860001 */
971 xlvl = cpuid_eax(0x80860000);
972 if ((xlvl & 0xffff0000) == 0x80860000) {
973 /* Don't set x86_cpuid_level here for now to not confuse. */
974 if (xlvl >= 0x80860001)
975 c->x86_capability[2] = cpuid_edx(0x80860001);
978 c->apicid = phys_pkg_id(0);
981 * Vendor-specific initialization. In this section we
982 * canonicalize the feature flags, meaning if there are
983 * features a certain CPU supports which CPUID doesn't
984 * tell us, CPUID claiming incorrect flags, or other bugs,
985 * we handle them here.
987 * At the end of this section, c->x86_capability better
988 * indicate the features this CPU genuinely supports!
990 switch (c->x86_vendor) {
995 case X86_VENDOR_INTEL:
999 case X86_VENDOR_UNKNOWN:
1001 display_cacheinfo(c);
1005 select_idle_routine(c);
1009 * On SMP, boot_cpu_data holds the common feature set between
1010 * all CPUs; so make sure that we indicate which features are
1011 * common between the CPUs. The first time this routine gets
1012 * executed, c == &boot_cpu_data.
1014 if (c != &boot_cpu_data) {
1015 /* AND the already accumulated flags with these */
1016 for (i = 0 ; i < NCAPINTS ; i++)
1017 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1020 #ifdef CONFIG_X86_MCE
1023 if (c == &boot_cpu_data)
1028 numa_add_cpu(smp_processor_id());
1033 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1035 if (c->x86_model_id[0])
1036 printk("%s", c->x86_model_id);
1038 if (c->x86_mask || c->cpuid_level >= 0)
1039 printk(" stepping %02x\n", c->x86_mask);
1045 * Get CPU information for use by the procfs.
1048 static int show_cpuinfo(struct seq_file *m, void *v)
1050 struct cpuinfo_x86 *c = v;
1053 * These flag bits must match the definitions in <asm/cpufeature.h>.
1054 * NULL means this bit is undefined or reserved; either way it doesn't
1055 * have meaning as far as Linux is concerned. Note that it's important
1056 * to realize there is a difference between this table and CPUID -- if
1057 * applications want to get the raw CPUID data, they should access
1058 * /dev/cpu/<cpu_nr>/cpuid instead.
1060 static char *x86_cap_flags[] = {
1062 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1063 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1064 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1065 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
1068 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1069 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1070 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1071 NULL, "fxsr_opt", NULL, "rdtscp", NULL, "lm", "3dnowext", "3dnow",
1073 /* Transmeta-defined */
1074 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1075 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1076 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1077 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1079 /* Other (Linux-defined) */
1080 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
1081 "constant_tsc", NULL, NULL,
1082 "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1084 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1086 /* Intel-defined (#2) */
1087 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1088 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1089 NULL, NULL, "dca", NULL, NULL, NULL, NULL, NULL,
1090 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1092 /* VIA/Cyrix/Centaur-defined */
1093 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1094 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1098 /* AMD-defined (#2) */
1099 "lahf_lm", "cmp_legacy", "svm", NULL, "cr8_legacy", NULL, NULL, NULL,
1100 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1104 static char *x86_power_flags[] = {
1105 "ts", /* temperature sensor */
1106 "fid", /* frequency id control */
1107 "vid", /* voltage id control */
1108 "ttp", /* thermal trip */
1112 /* nothing */ /* constant_tsc - moved to flags */
1117 if (!cpu_online(c-cpu_data))
1121 seq_printf(m,"processor\t: %u\n"
1123 "cpu family\t: %d\n"
1125 "model name\t: %s\n",
1126 (unsigned)(c-cpu_data),
1127 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1130 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1132 if (c->x86_mask || c->cpuid_level >= 0)
1133 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1135 seq_printf(m, "stepping\t: unknown\n");
1137 if (cpu_has(c,X86_FEATURE_TSC)) {
1138 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1141 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1142 freq / 1000, (freq % 1000));
1146 if (c->x86_cache_size >= 0)
1147 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1150 if (smp_num_siblings * c->x86_max_cores > 1) {
1151 int cpu = c - cpu_data;
1152 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1153 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
1154 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1155 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1161 "fpu_exception\t: yes\n"
1162 "cpuid level\t: %d\n"
1169 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1170 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1171 seq_printf(m, " %s", x86_cap_flags[i]);
1174 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1175 c->loops_per_jiffy/(500000/HZ),
1176 (c->loops_per_jiffy/(5000/HZ)) % 100);
1178 if (c->x86_tlbsize > 0)
1179 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1180 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1181 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1183 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1184 c->x86_phys_bits, c->x86_virt_bits);
1186 seq_printf(m, "power management:");
1189 for (i = 0; i < 32; i++)
1190 if (c->x86_power & (1 << i)) {
1191 if (i < ARRAY_SIZE(x86_power_flags) &&
1193 seq_printf(m, "%s%s",
1194 x86_power_flags[i][0]?" ":"",
1195 x86_power_flags[i]);
1197 seq_printf(m, " [%d]", i);
1201 seq_printf(m, "\n\n");
1206 static void *c_start(struct seq_file *m, loff_t *pos)
1208 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1211 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1214 return c_start(m, pos);
1217 static void c_stop(struct seq_file *m, void *v)
1221 struct seq_operations cpuinfo_op = {
1225 .show = show_cpuinfo,
1228 #if defined(CONFIG_INPUT_PCSPKR) || defined(CONFIG_INPUT_PCSPKR_MODULE)
1229 #include <linux/platform_device.h>
1230 static __init int add_pcspkr(void)
1232 struct platform_device *pd;
1235 pd = platform_device_alloc("pcspkr", -1);
1239 ret = platform_device_add(pd);
1241 platform_device_put(pd);
1245 device_initcall(add_pcspkr);