2 * linux/arch/x86-64/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
11 * This file handles the architecture-dependent parts of initialization
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
18 #include <linux/stddef.h>
19 #include <linux/unistd.h>
20 #include <linux/ptrace.h>
21 #include <linux/slab.h>
22 #include <linux/user.h>
23 #include <linux/a.out.h>
24 #include <linux/screen_info.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/initrd.h>
29 #include <linux/highmem.h>
30 #include <linux/bootmem.h>
31 #include <linux/module.h>
32 #include <asm/processor.h>
33 #include <linux/console.h>
34 #include <linux/seq_file.h>
35 #include <linux/crash_dump.h>
36 #include <linux/root_dev.h>
37 #include <linux/pci.h>
38 #include <linux/acpi.h>
39 #include <linux/kallsyms.h>
40 #include <linux/edd.h>
41 #include <linux/mmzone.h>
42 #include <linux/kexec.h>
43 #include <linux/cpufreq.h>
44 #include <linux/dmi.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/ctype.h>
49 #include <asm/uaccess.h>
50 #include <asm/system.h>
55 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/bootsetup.h>
61 #include <asm/proto.h>
62 #include <asm/setup.h>
63 #include <asm/mach_apic.h>
65 #include <asm/sections.h>
72 struct cpuinfo_x86 boot_cpu_data __read_mostly;
73 EXPORT_SYMBOL(boot_cpu_data);
75 unsigned long mmu_cr4_features;
77 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
80 unsigned long saved_video_mode;
86 char dmi_alloc_data[DMI_MAX_DATA];
91 struct screen_info screen_info;
92 EXPORT_SYMBOL(screen_info);
93 struct sys_desc_table_struct {
94 unsigned short length;
95 unsigned char table[0];
98 struct edid_info edid_info;
99 EXPORT_SYMBOL_GPL(edid_info);
101 extern int root_mountflags;
103 char __initdata command_line[COMMAND_LINE_SIZE];
105 struct resource standard_io_resources[] = {
106 { .name = "dma1", .start = 0x00, .end = 0x1f,
107 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
108 { .name = "pic1", .start = 0x20, .end = 0x21,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "timer0", .start = 0x40, .end = 0x43,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "timer1", .start = 0x50, .end = 0x53,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "keyboard", .start = 0x60, .end = 0x6f,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "pic2", .start = 0xa0, .end = 0xa1,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "dma2", .start = 0xc0, .end = 0xdf,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "fpu", .start = 0xf0, .end = 0xff,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
126 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
128 struct resource data_resource = {
129 .name = "Kernel data",
132 .flags = IORESOURCE_RAM,
134 struct resource code_resource = {
135 .name = "Kernel code",
138 .flags = IORESOURCE_RAM,
141 #ifdef CONFIG_PROC_VMCORE
142 /* elfcorehdr= specifies the location of elf core header
143 * stored by the crashed kernel. This option will be passed
144 * by kexec loader to the capture kernel.
146 static int __init setup_elfcorehdr(char *arg)
151 elfcorehdr_addr = memparse(arg, &end);
152 return end > arg ? 0 : -EINVAL;
154 early_param("elfcorehdr", setup_elfcorehdr);
159 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
161 unsigned long bootmap_size, bootmap;
163 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
164 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
166 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
167 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
168 e820_register_active_regions(0, start_pfn, end_pfn);
169 free_bootmem_with_active_regions(0, end_pfn);
170 reserve_bootmem(bootmap, bootmap_size);
174 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
176 #ifdef CONFIG_EDD_MODULE
180 * copy_edd() - Copy the BIOS EDD information
181 * from boot_params into a safe place.
184 static inline void copy_edd(void)
186 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
187 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
188 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
189 edd.edd_info_nr = EDD_NR;
192 static inline void copy_edd(void)
197 #define EBDA_ADDR_POINTER 0x40E
199 unsigned __initdata ebda_addr;
200 unsigned __initdata ebda_size;
202 static void discover_ebda(void)
205 * there is a real-mode segmented pointer pointing to the
206 * 4K EBDA area at 0x40E
208 ebda_addr = *(unsigned short *)EBDA_ADDR_POINTER;
211 ebda_size = *(unsigned short *)(unsigned long)ebda_addr;
213 /* Round EBDA up to pages */
217 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
218 if (ebda_size > 64*1024)
222 void __init setup_arch(char **cmdline_p)
224 printk(KERN_INFO "Command line: %s\n", boot_command_line);
226 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
227 screen_info = SCREEN_INFO;
228 edid_info = EDID_INFO;
229 saved_video_mode = SAVED_VIDEO_MODE;
230 bootloader_type = LOADER_TYPE;
232 #ifdef CONFIG_BLK_DEV_RAM
233 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
234 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
235 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
237 setup_memory_region();
240 if (!MOUNT_ROOT_RDONLY)
241 root_mountflags &= ~MS_RDONLY;
242 init_mm.start_code = (unsigned long) &_text;
243 init_mm.end_code = (unsigned long) &_etext;
244 init_mm.end_data = (unsigned long) &_edata;
245 init_mm.brk = (unsigned long) &_end;
247 code_resource.start = virt_to_phys(&_text);
248 code_resource.end = virt_to_phys(&_etext)-1;
249 data_resource.start = virt_to_phys(&_etext);
250 data_resource.end = virt_to_phys(&_edata)-1;
252 early_identify_cpu(&boot_cpu_data);
254 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
255 *cmdline_p = command_line;
259 finish_e820_parsing();
261 e820_register_active_regions(0, 0, -1UL);
263 * partially used pages are not usable - thus
264 * we are rounding upwards:
266 end_pfn = e820_end_of_ram();
267 num_physpages = end_pfn;
273 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
281 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
282 * Call this early for SRAT node setup.
284 acpi_boot_table_init();
287 /* How many end-of-memory variables you have, grandma! */
288 max_low_pfn = end_pfn;
290 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
292 /* Remove active ranges so rediscovery with NUMA-awareness happens */
293 remove_all_active_ranges();
295 #ifdef CONFIG_ACPI_NUMA
297 * Parse SRAT to discover nodes.
303 numa_initmem_init(0, end_pfn);
305 contig_initmem_init(0, end_pfn);
308 /* Reserve direct mapping */
309 reserve_bootmem_generic(table_start << PAGE_SHIFT,
310 (table_end - table_start) << PAGE_SHIFT);
313 reserve_bootmem_generic(__pa_symbol(&_text),
314 __pa_symbol(&_end) - __pa_symbol(&_text));
317 * reserve physical page 0 - it's a special BIOS page on many boxes,
318 * enabling clean reboots, SMP operation, laptop functions.
320 reserve_bootmem_generic(0, PAGE_SIZE);
322 /* reserve ebda region */
324 reserve_bootmem_generic(ebda_addr, ebda_size);
326 /* reserve nodemap region */
328 reserve_bootmem_generic(nodemap_addr, nodemap_size);
333 * But first pinch a few for the stack/trampoline stuff
334 * FIXME: Don't need the extra page at 4K, but need to fix
335 * trampoline before removing it. (see the GDT stuff)
337 reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
339 /* Reserve SMP trampoline */
340 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
343 #ifdef CONFIG_ACPI_SLEEP
345 * Reserve low memory region for sleep support.
347 acpi_reserve_bootmem();
350 * Find and reserve possible boot-time SMP configuration:
353 #ifdef CONFIG_BLK_DEV_INITRD
354 if (LOADER_TYPE && INITRD_START) {
355 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
356 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
357 initrd_start = INITRD_START + PAGE_OFFSET;
358 initrd_end = initrd_start+INITRD_SIZE;
361 printk(KERN_ERR "initrd extends beyond end of memory "
362 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
363 (unsigned long)(INITRD_START + INITRD_SIZE),
364 (unsigned long)(end_pfn << PAGE_SHIFT));
370 if (crashk_res.start != crashk_res.end) {
371 reserve_bootmem_generic(crashk_res.start,
372 crashk_res.end - crashk_res.start + 1);
383 * set this early, so we dont allocate cpu0
384 * if MADT list doesnt list BSP first
385 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
387 cpu_set(0, cpu_present_map);
390 * Read APIC and some other early information from ACPI tables.
398 * get boot-time SMP configuration:
400 if (smp_found_config)
402 init_apic_mappings();
405 * We trust e820 completely. No explicit ROM probing in memory.
407 e820_reserve_resources();
408 e820_mark_nosave_regions();
412 /* request I/O space for devices used on all i[345]86 PCs */
413 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
414 request_resource(&ioport_resource, &standard_io_resources[i]);
420 #if defined(CONFIG_VGA_CONSOLE)
421 conswitchp = &vga_con;
422 #elif defined(CONFIG_DUMMY_CONSOLE)
423 conswitchp = &dummy_con;
428 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
432 if (c->extended_cpuid_level < 0x80000004)
435 v = (unsigned int *) c->x86_model_id;
436 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
437 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
438 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
439 c->x86_model_id[48] = 0;
444 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
446 unsigned int n, dummy, eax, ebx, ecx, edx;
448 n = c->extended_cpuid_level;
450 if (n >= 0x80000005) {
451 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
452 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
453 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
454 c->x86_cache_size=(ecx>>24)+(edx>>24);
455 /* On K8 L1 TLB is inclusive, so don't count it */
459 if (n >= 0x80000006) {
460 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
461 ecx = cpuid_ecx(0x80000006);
462 c->x86_cache_size = ecx >> 16;
463 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
465 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
466 c->x86_cache_size, ecx & 0xFF);
470 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
471 if (n >= 0x80000008) {
472 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
473 c->x86_virt_bits = (eax >> 8) & 0xff;
474 c->x86_phys_bits = eax & 0xff;
479 static int nearby_node(int apicid)
482 for (i = apicid - 1; i >= 0; i--) {
483 int node = apicid_to_node[i];
484 if (node != NUMA_NO_NODE && node_online(node))
487 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
488 int node = apicid_to_node[i];
489 if (node != NUMA_NO_NODE && node_online(node))
492 return first_node(node_online_map); /* Shouldn't happen */
497 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
498 * Assumes number of cores is a power of two.
500 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
505 int cpu = smp_processor_id();
507 unsigned apicid = hard_smp_processor_id();
509 unsigned ecx = cpuid_ecx(0x80000008);
511 c->x86_max_cores = (ecx & 0xff) + 1;
513 /* CPU telling us the core id bits shift? */
514 bits = (ecx >> 12) & 0xF;
516 /* Otherwise recompute */
518 while ((1 << bits) < c->x86_max_cores)
522 /* Low order bits define the core id (index of core in socket) */
523 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
524 /* Convert the APIC ID into the socket ID */
525 c->phys_proc_id = phys_pkg_id(bits);
528 node = c->phys_proc_id;
529 if (apicid_to_node[apicid] != NUMA_NO_NODE)
530 node = apicid_to_node[apicid];
531 if (!node_online(node)) {
532 /* Two possibilities here:
533 - The CPU is missing memory and no node was created.
534 In that case try picking one from a nearby CPU
535 - The APIC IDs differ from the HyperTransport node IDs
536 which the K8 northbridge parsing fills in.
537 Assume they are all increased by a constant offset,
538 but in the same order as the HT nodeids.
539 If that doesn't result in a usable node fall back to the
540 path for the previous case. */
541 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
542 if (ht_nodeid >= 0 &&
543 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
544 node = apicid_to_node[ht_nodeid];
545 /* Pick a nearby node */
546 if (!node_online(node))
547 node = nearby_node(apicid);
549 numa_set_node(cpu, node);
551 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
556 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
564 * Disable TLB flush filter by setting HWCR.FFDIS on K8
565 * bit 6 of msr C001_0015
567 * Errata 63 for SH-B3 steppings
568 * Errata 122 for all steppings (F+ have it disabled by default)
571 rdmsrl(MSR_K8_HWCR, value);
573 wrmsrl(MSR_K8_HWCR, value);
577 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
578 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
579 clear_bit(0*32+31, &c->x86_capability);
581 /* On C+ stepping K8 rep microcode works well for copy/memset */
582 level = cpuid_eax(1);
583 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
584 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
586 /* Enable workaround for FXSAVE leak */
588 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
590 level = get_model_name(c);
594 /* Should distinguish Models here, but this is only
595 a fallback anyways. */
596 strcpy(c->x86_model_id, "Hammer");
600 display_cacheinfo(c);
602 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
603 if (c->x86_power & (1<<8))
604 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
606 /* Multi core CPU? */
607 if (c->extended_cpuid_level >= 0x80000008)
610 /* Fix cpuid4 emulation for more */
611 num_cache_leaves = 3;
613 /* RDTSC can be speculated around */
614 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
617 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
620 u32 eax, ebx, ecx, edx;
621 int index_msb, core_bits;
623 cpuid(1, &eax, &ebx, &ecx, &edx);
626 if (!cpu_has(c, X86_FEATURE_HT))
628 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
631 smp_num_siblings = (ebx & 0xff0000) >> 16;
633 if (smp_num_siblings == 1) {
634 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
635 } else if (smp_num_siblings > 1 ) {
637 if (smp_num_siblings > NR_CPUS) {
638 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
639 smp_num_siblings = 1;
643 index_msb = get_count_order(smp_num_siblings);
644 c->phys_proc_id = phys_pkg_id(index_msb);
646 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
648 index_msb = get_count_order(smp_num_siblings) ;
650 core_bits = get_count_order(c->x86_max_cores);
652 c->cpu_core_id = phys_pkg_id(index_msb) &
653 ((1 << core_bits) - 1);
656 if ((c->x86_max_cores * smp_num_siblings) > 1) {
657 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
658 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
665 * find out the number of processor cores on the die
667 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
671 if (c->cpuid_level < 4)
674 cpuid_count(4, 0, &eax, &t, &t, &t);
677 return ((eax >> 26) + 1);
682 static void srat_detect_node(void)
686 int cpu = smp_processor_id();
687 int apicid = hard_smp_processor_id();
689 /* Don't do the funky fallback heuristics the AMD version employs
691 node = apicid_to_node[apicid];
692 if (node == NUMA_NO_NODE)
693 node = first_node(node_online_map);
694 numa_set_node(cpu, node);
696 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
700 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
705 init_intel_cacheinfo(c);
706 if (c->cpuid_level > 9 ) {
707 unsigned eax = cpuid_eax(10);
708 /* Check for version and the number of counters */
709 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
710 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
715 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
717 set_bit(X86_FEATURE_BTS, c->x86_capability);
719 set_bit(X86_FEATURE_PEBS, c->x86_capability);
722 n = c->extended_cpuid_level;
723 if (n >= 0x80000008) {
724 unsigned eax = cpuid_eax(0x80000008);
725 c->x86_virt_bits = (eax >> 8) & 0xff;
726 c->x86_phys_bits = eax & 0xff;
727 /* CPUID workaround for Intel 0F34 CPU */
728 if (c->x86_vendor == X86_VENDOR_INTEL &&
729 c->x86 == 0xF && c->x86_model == 0x3 &&
731 c->x86_phys_bits = 36;
735 c->x86_cache_alignment = c->x86_clflush_size * 2;
736 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
737 (c->x86 == 0x6 && c->x86_model >= 0x0e))
738 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
740 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
742 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
744 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
745 c->x86_max_cores = intel_num_cpu_cores(c);
750 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
752 char *v = c->x86_vendor_id;
754 if (!strcmp(v, "AuthenticAMD"))
755 c->x86_vendor = X86_VENDOR_AMD;
756 else if (!strcmp(v, "GenuineIntel"))
757 c->x86_vendor = X86_VENDOR_INTEL;
759 c->x86_vendor = X86_VENDOR_UNKNOWN;
762 struct cpu_model_info {
765 char *model_names[16];
768 /* Do some early cpuid on the boot CPU to get some parameter that are
769 needed before check_bugs. Everything advanced is in identify_cpu
771 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
775 c->loops_per_jiffy = loops_per_jiffy;
776 c->x86_cache_size = -1;
777 c->x86_vendor = X86_VENDOR_UNKNOWN;
778 c->x86_model = c->x86_mask = 0; /* So far unknown... */
779 c->x86_vendor_id[0] = '\0'; /* Unset */
780 c->x86_model_id[0] = '\0'; /* Unset */
781 c->x86_clflush_size = 64;
782 c->x86_cache_alignment = c->x86_clflush_size;
783 c->x86_max_cores = 1;
784 c->extended_cpuid_level = 0;
785 memset(&c->x86_capability, 0, sizeof c->x86_capability);
787 /* Get vendor name */
788 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
789 (unsigned int *)&c->x86_vendor_id[0],
790 (unsigned int *)&c->x86_vendor_id[8],
791 (unsigned int *)&c->x86_vendor_id[4]);
795 /* Initialize the standard set of capabilities */
796 /* Note that the vendor-specific code below might override */
798 /* Intel-defined flags: level 0x00000001 */
799 if (c->cpuid_level >= 0x00000001) {
801 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
802 &c->x86_capability[0]);
803 c->x86 = (tfms >> 8) & 0xf;
804 c->x86_model = (tfms >> 4) & 0xf;
805 c->x86_mask = tfms & 0xf;
807 c->x86 += (tfms >> 20) & 0xff;
809 c->x86_model += ((tfms >> 16) & 0xF) << 4;
810 if (c->x86_capability[0] & (1<<19))
811 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
813 /* Have CPUID level 0 only - unheard of */
818 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
823 * This does the hard work of actually picking apart the CPU stuff...
825 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
830 early_identify_cpu(c);
832 /* AMD-defined flags: level 0x80000001 */
833 xlvl = cpuid_eax(0x80000000);
834 c->extended_cpuid_level = xlvl;
835 if ((xlvl & 0xffff0000) == 0x80000000) {
836 if (xlvl >= 0x80000001) {
837 c->x86_capability[1] = cpuid_edx(0x80000001);
838 c->x86_capability[6] = cpuid_ecx(0x80000001);
840 if (xlvl >= 0x80000004)
841 get_model_name(c); /* Default name */
844 /* Transmeta-defined flags: level 0x80860001 */
845 xlvl = cpuid_eax(0x80860000);
846 if ((xlvl & 0xffff0000) == 0x80860000) {
847 /* Don't set x86_cpuid_level here for now to not confuse. */
848 if (xlvl >= 0x80860001)
849 c->x86_capability[2] = cpuid_edx(0x80860001);
852 c->apicid = phys_pkg_id(0);
855 * Vendor-specific initialization. In this section we
856 * canonicalize the feature flags, meaning if there are
857 * features a certain CPU supports which CPUID doesn't
858 * tell us, CPUID claiming incorrect flags, or other bugs,
859 * we handle them here.
861 * At the end of this section, c->x86_capability better
862 * indicate the features this CPU genuinely supports!
864 switch (c->x86_vendor) {
869 case X86_VENDOR_INTEL:
873 case X86_VENDOR_UNKNOWN:
875 display_cacheinfo(c);
879 select_idle_routine(c);
883 * On SMP, boot_cpu_data holds the common feature set between
884 * all CPUs; so make sure that we indicate which features are
885 * common between the CPUs. The first time this routine gets
886 * executed, c == &boot_cpu_data.
888 if (c != &boot_cpu_data) {
889 /* AND the already accumulated flags with these */
890 for (i = 0 ; i < NCAPINTS ; i++)
891 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
894 #ifdef CONFIG_X86_MCE
897 if (c == &boot_cpu_data)
902 numa_add_cpu(smp_processor_id());
907 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
909 if (c->x86_model_id[0])
910 printk("%s", c->x86_model_id);
912 if (c->x86_mask || c->cpuid_level >= 0)
913 printk(" stepping %02x\n", c->x86_mask);
919 * Get CPU information for use by the procfs.
922 static int show_cpuinfo(struct seq_file *m, void *v)
924 struct cpuinfo_x86 *c = v;
927 * These flag bits must match the definitions in <asm/cpufeature.h>.
928 * NULL means this bit is undefined or reserved; either way it doesn't
929 * have meaning as far as Linux is concerned. Note that it's important
930 * to realize there is a difference between this table and CPUID -- if
931 * applications want to get the raw CPUID data, they should access
932 * /dev/cpu/<cpu_nr>/cpuid instead.
934 static char *x86_cap_flags[] = {
936 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
937 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
938 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
939 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
942 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
943 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
944 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
945 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
948 /* Transmeta-defined */
949 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
950 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
951 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
952 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
954 /* Other (Linux-defined) */
955 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
956 "constant_tsc", NULL, NULL,
957 "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
958 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
959 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
961 /* Intel-defined (#2) */
962 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
963 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
964 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
965 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
967 /* VIA/Cyrix/Centaur-defined */
968 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
969 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
970 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
973 /* AMD-defined (#2) */
974 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
975 "altmovcr8", "abm", "sse4a",
976 "misalignsse", "3dnowprefetch",
977 "osvw", "ibs", NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
979 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
981 static char *x86_power_flags[] = {
982 "ts", /* temperature sensor */
983 "fid", /* frequency id control */
984 "vid", /* voltage id control */
985 "ttp", /* thermal trip */
990 NULL, /* tsc invariant mapped to constant_tsc */
992 /* nothing */ /* constant_tsc - moved to flags */
997 if (!cpu_online(c-cpu_data))
1001 seq_printf(m,"processor\t: %u\n"
1003 "cpu family\t: %d\n"
1005 "model name\t: %s\n",
1006 (unsigned)(c-cpu_data),
1007 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1010 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1012 if (c->x86_mask || c->cpuid_level >= 0)
1013 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1015 seq_printf(m, "stepping\t: unknown\n");
1017 if (cpu_has(c,X86_FEATURE_TSC)) {
1018 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1021 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1022 freq / 1000, (freq % 1000));
1026 if (c->x86_cache_size >= 0)
1027 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1030 if (smp_num_siblings * c->x86_max_cores > 1) {
1031 int cpu = c - cpu_data;
1032 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1033 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
1034 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1035 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1041 "fpu_exception\t: yes\n"
1042 "cpuid level\t: %d\n"
1049 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1050 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1051 seq_printf(m, " %s", x86_cap_flags[i]);
1054 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1055 c->loops_per_jiffy/(500000/HZ),
1056 (c->loops_per_jiffy/(5000/HZ)) % 100);
1058 if (c->x86_tlbsize > 0)
1059 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1060 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1061 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1063 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1064 c->x86_phys_bits, c->x86_virt_bits);
1066 seq_printf(m, "power management:");
1069 for (i = 0; i < 32; i++)
1070 if (c->x86_power & (1 << i)) {
1071 if (i < ARRAY_SIZE(x86_power_flags) &&
1073 seq_printf(m, "%s%s",
1074 x86_power_flags[i][0]?" ":"",
1075 x86_power_flags[i]);
1077 seq_printf(m, " [%d]", i);
1081 seq_printf(m, "\n\n");
1086 static void *c_start(struct seq_file *m, loff_t *pos)
1088 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1091 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1094 return c_start(m, pos);
1097 static void c_stop(struct seq_file *m, void *v)
1101 struct seq_operations cpuinfo_op = {
1105 .show = show_cpuinfo,