2 * linux/arch/x86-64/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
11 * This file handles the architecture-dependent parts of initialization
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
18 #include <linux/stddef.h>
19 #include <linux/unistd.h>
20 #include <linux/ptrace.h>
21 #include <linux/slab.h>
22 #include <linux/user.h>
23 #include <linux/a.out.h>
24 #include <linux/screen_info.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/initrd.h>
29 #include <linux/highmem.h>
30 #include <linux/bootmem.h>
31 #include <linux/module.h>
32 #include <asm/processor.h>
33 #include <linux/console.h>
34 #include <linux/seq_file.h>
35 #include <linux/crash_dump.h>
36 #include <linux/root_dev.h>
37 #include <linux/pci.h>
38 #include <linux/acpi.h>
39 #include <linux/kallsyms.h>
40 #include <linux/edd.h>
41 #include <linux/mmzone.h>
42 #include <linux/kexec.h>
43 #include <linux/cpufreq.h>
44 #include <linux/dmi.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/ctype.h>
49 #include <asm/uaccess.h>
50 #include <asm/system.h>
55 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/bootsetup.h>
61 #include <asm/proto.h>
62 #include <asm/setup.h>
63 #include <asm/mach_apic.h>
65 #include <asm/sections.h>
72 struct cpuinfo_x86 boot_cpu_data __read_mostly;
73 EXPORT_SYMBOL(boot_cpu_data);
75 unsigned long mmu_cr4_features;
77 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
80 unsigned long saved_video_mode;
82 int force_mwait __cpuinitdata;
88 char dmi_alloc_data[DMI_MAX_DATA];
93 struct screen_info screen_info;
94 EXPORT_SYMBOL(screen_info);
95 struct sys_desc_table_struct {
96 unsigned short length;
97 unsigned char table[0];
100 struct edid_info edid_info;
101 EXPORT_SYMBOL_GPL(edid_info);
103 extern int root_mountflags;
105 char __initdata command_line[COMMAND_LINE_SIZE];
107 struct resource standard_io_resources[] = {
108 { .name = "dma1", .start = 0x00, .end = 0x1f,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "pic1", .start = 0x20, .end = 0x21,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "timer0", .start = 0x40, .end = 0x43,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "timer1", .start = 0x50, .end = 0x53,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "keyboard", .start = 0x60, .end = 0x6f,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "pic2", .start = 0xa0, .end = 0xa1,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "dma2", .start = 0xc0, .end = 0xdf,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "fpu", .start = 0xf0, .end = 0xff,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
128 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
130 struct resource data_resource = {
131 .name = "Kernel data",
134 .flags = IORESOURCE_RAM,
136 struct resource code_resource = {
137 .name = "Kernel code",
140 .flags = IORESOURCE_RAM,
143 #ifdef CONFIG_PROC_VMCORE
144 /* elfcorehdr= specifies the location of elf core header
145 * stored by the crashed kernel. This option will be passed
146 * by kexec loader to the capture kernel.
148 static int __init setup_elfcorehdr(char *arg)
153 elfcorehdr_addr = memparse(arg, &end);
154 return end > arg ? 0 : -EINVAL;
156 early_param("elfcorehdr", setup_elfcorehdr);
161 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
163 unsigned long bootmap_size, bootmap;
165 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
166 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
168 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
169 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
170 e820_register_active_regions(0, start_pfn, end_pfn);
171 free_bootmem_with_active_regions(0, end_pfn);
172 reserve_bootmem(bootmap, bootmap_size);
176 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
178 #ifdef CONFIG_EDD_MODULE
182 * copy_edd() - Copy the BIOS EDD information
183 * from boot_params into a safe place.
186 static inline void copy_edd(void)
188 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
189 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
190 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
191 edd.edd_info_nr = EDD_NR;
194 static inline void copy_edd(void)
199 #define EBDA_ADDR_POINTER 0x40E
201 unsigned __initdata ebda_addr;
202 unsigned __initdata ebda_size;
204 static void discover_ebda(void)
207 * there is a real-mode segmented pointer pointing to the
208 * 4K EBDA area at 0x40E
210 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
213 ebda_size = *(unsigned short *)__va(ebda_addr);
215 /* Round EBDA up to pages */
219 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
220 if (ebda_size > 64*1024)
224 void __init setup_arch(char **cmdline_p)
226 printk(KERN_INFO "Command line: %s\n", boot_command_line);
228 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
229 screen_info = SCREEN_INFO;
230 edid_info = EDID_INFO;
231 saved_video_mode = SAVED_VIDEO_MODE;
232 bootloader_type = LOADER_TYPE;
234 #ifdef CONFIG_BLK_DEV_RAM
235 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
236 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
237 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
239 setup_memory_region();
242 if (!MOUNT_ROOT_RDONLY)
243 root_mountflags &= ~MS_RDONLY;
244 init_mm.start_code = (unsigned long) &_text;
245 init_mm.end_code = (unsigned long) &_etext;
246 init_mm.end_data = (unsigned long) &_edata;
247 init_mm.brk = (unsigned long) &_end;
248 init_mm.pgd = __va(__pa_symbol(&init_level4_pgt));
250 code_resource.start = __pa_symbol(&_text);
251 code_resource.end = __pa_symbol(&_etext)-1;
252 data_resource.start = __pa_symbol(&_etext);
253 data_resource.end = __pa_symbol(&_edata)-1;
255 early_identify_cpu(&boot_cpu_data);
257 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
258 *cmdline_p = command_line;
262 finish_e820_parsing();
264 e820_register_active_regions(0, 0, -1UL);
266 * partially used pages are not usable - thus
267 * we are rounding upwards:
269 end_pfn = e820_end_of_ram();
270 num_physpages = end_pfn;
276 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
282 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
283 * Call this early for SRAT node setup.
285 acpi_boot_table_init();
288 /* How many end-of-memory variables you have, grandma! */
289 max_low_pfn = end_pfn;
291 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
293 /* Remove active ranges so rediscovery with NUMA-awareness happens */
294 remove_all_active_ranges();
296 #ifdef CONFIG_ACPI_NUMA
298 * Parse SRAT to discover nodes.
304 numa_initmem_init(0, end_pfn);
306 contig_initmem_init(0, end_pfn);
309 /* Reserve direct mapping */
310 reserve_bootmem_generic(table_start << PAGE_SHIFT,
311 (table_end - table_start) << PAGE_SHIFT);
314 reserve_bootmem_generic(__pa_symbol(&_text),
315 __pa_symbol(&_end) - __pa_symbol(&_text));
318 * reserve physical page 0 - it's a special BIOS page on many boxes,
319 * enabling clean reboots, SMP operation, laptop functions.
321 reserve_bootmem_generic(0, PAGE_SIZE);
323 /* reserve ebda region */
325 reserve_bootmem_generic(ebda_addr, ebda_size);
327 /* reserve nodemap region */
329 reserve_bootmem_generic(nodemap_addr, nodemap_size);
333 /* Reserve SMP trampoline */
334 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
337 #ifdef CONFIG_ACPI_SLEEP
339 * Reserve low memory region for sleep support.
341 acpi_reserve_bootmem();
344 * Find and reserve possible boot-time SMP configuration:
347 #ifdef CONFIG_BLK_DEV_INITRD
348 if (LOADER_TYPE && INITRD_START) {
349 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
350 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
351 initrd_start = INITRD_START + PAGE_OFFSET;
352 initrd_end = initrd_start+INITRD_SIZE;
355 printk(KERN_ERR "initrd extends beyond end of memory "
356 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
357 (unsigned long)(INITRD_START + INITRD_SIZE),
358 (unsigned long)(end_pfn << PAGE_SHIFT));
364 if (crashk_res.start != crashk_res.end) {
365 reserve_bootmem_generic(crashk_res.start,
366 crashk_res.end - crashk_res.start + 1);
377 * set this early, so we dont allocate cpu0
378 * if MADT list doesnt list BSP first
379 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
381 cpu_set(0, cpu_present_map);
384 * Read APIC and some other early information from ACPI tables.
392 * get boot-time SMP configuration:
394 if (smp_found_config)
396 init_apic_mappings();
399 * We trust e820 completely. No explicit ROM probing in memory.
401 e820_reserve_resources();
402 e820_mark_nosave_regions();
406 /* request I/O space for devices used on all i[345]86 PCs */
407 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
408 request_resource(&ioport_resource, &standard_io_resources[i]);
414 #if defined(CONFIG_VGA_CONSOLE)
415 conswitchp = &vga_con;
416 #elif defined(CONFIG_DUMMY_CONSOLE)
417 conswitchp = &dummy_con;
422 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
426 if (c->extended_cpuid_level < 0x80000004)
429 v = (unsigned int *) c->x86_model_id;
430 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
431 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
432 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
433 c->x86_model_id[48] = 0;
438 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
440 unsigned int n, dummy, eax, ebx, ecx, edx;
442 n = c->extended_cpuid_level;
444 if (n >= 0x80000005) {
445 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
446 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
447 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
448 c->x86_cache_size=(ecx>>24)+(edx>>24);
449 /* On K8 L1 TLB is inclusive, so don't count it */
453 if (n >= 0x80000006) {
454 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
455 ecx = cpuid_ecx(0x80000006);
456 c->x86_cache_size = ecx >> 16;
457 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
459 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
460 c->x86_cache_size, ecx & 0xFF);
464 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
465 if (n >= 0x80000008) {
466 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
467 c->x86_virt_bits = (eax >> 8) & 0xff;
468 c->x86_phys_bits = eax & 0xff;
473 static int nearby_node(int apicid)
476 for (i = apicid - 1; i >= 0; i--) {
477 int node = apicid_to_node[i];
478 if (node != NUMA_NO_NODE && node_online(node))
481 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
482 int node = apicid_to_node[i];
483 if (node != NUMA_NO_NODE && node_online(node))
486 return first_node(node_online_map); /* Shouldn't happen */
491 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
492 * Assumes number of cores is a power of two.
494 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
499 int cpu = smp_processor_id();
501 unsigned apicid = hard_smp_processor_id();
503 unsigned ecx = cpuid_ecx(0x80000008);
505 c->x86_max_cores = (ecx & 0xff) + 1;
507 /* CPU telling us the core id bits shift? */
508 bits = (ecx >> 12) & 0xF;
510 /* Otherwise recompute */
512 while ((1 << bits) < c->x86_max_cores)
516 /* Low order bits define the core id (index of core in socket) */
517 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
518 /* Convert the APIC ID into the socket ID */
519 c->phys_proc_id = phys_pkg_id(bits);
522 node = c->phys_proc_id;
523 if (apicid_to_node[apicid] != NUMA_NO_NODE)
524 node = apicid_to_node[apicid];
525 if (!node_online(node)) {
526 /* Two possibilities here:
527 - The CPU is missing memory and no node was created.
528 In that case try picking one from a nearby CPU
529 - The APIC IDs differ from the HyperTransport node IDs
530 which the K8 northbridge parsing fills in.
531 Assume they are all increased by a constant offset,
532 but in the same order as the HT nodeids.
533 If that doesn't result in a usable node fall back to the
534 path for the previous case. */
535 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
536 if (ht_nodeid >= 0 &&
537 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
538 node = apicid_to_node[ht_nodeid];
539 /* Pick a nearby node */
540 if (!node_online(node))
541 node = nearby_node(apicid);
543 numa_set_node(cpu, node);
545 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
550 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
558 * Disable TLB flush filter by setting HWCR.FFDIS on K8
559 * bit 6 of msr C001_0015
561 * Errata 63 for SH-B3 steppings
562 * Errata 122 for all steppings (F+ have it disabled by default)
565 rdmsrl(MSR_K8_HWCR, value);
567 wrmsrl(MSR_K8_HWCR, value);
571 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
572 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
573 clear_bit(0*32+31, &c->x86_capability);
575 /* On C+ stepping K8 rep microcode works well for copy/memset */
576 level = cpuid_eax(1);
577 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
578 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
580 /* Enable workaround for FXSAVE leak */
582 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
584 level = get_model_name(c);
588 /* Should distinguish Models here, but this is only
589 a fallback anyways. */
590 strcpy(c->x86_model_id, "Hammer");
594 display_cacheinfo(c);
596 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
597 if (c->x86_power & (1<<8))
598 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
600 /* Multi core CPU? */
601 if (c->extended_cpuid_level >= 0x80000008)
604 /* Fix cpuid4 emulation for more */
605 num_cache_leaves = 3;
607 /* RDTSC can be speculated around */
608 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
610 /* Family 10 doesn't support C states in MWAIT so don't use it */
611 if (c->x86 == 0x10 && !force_mwait)
612 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
615 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
618 u32 eax, ebx, ecx, edx;
619 int index_msb, core_bits;
621 cpuid(1, &eax, &ebx, &ecx, &edx);
624 if (!cpu_has(c, X86_FEATURE_HT))
626 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
629 smp_num_siblings = (ebx & 0xff0000) >> 16;
631 if (smp_num_siblings == 1) {
632 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
633 } else if (smp_num_siblings > 1 ) {
635 if (smp_num_siblings > NR_CPUS) {
636 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
637 smp_num_siblings = 1;
641 index_msb = get_count_order(smp_num_siblings);
642 c->phys_proc_id = phys_pkg_id(index_msb);
644 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
646 index_msb = get_count_order(smp_num_siblings) ;
648 core_bits = get_count_order(c->x86_max_cores);
650 c->cpu_core_id = phys_pkg_id(index_msb) &
651 ((1 << core_bits) - 1);
654 if ((c->x86_max_cores * smp_num_siblings) > 1) {
655 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
656 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
663 * find out the number of processor cores on the die
665 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
669 if (c->cpuid_level < 4)
672 cpuid_count(4, 0, &eax, &t, &t, &t);
675 return ((eax >> 26) + 1);
680 static void srat_detect_node(void)
684 int cpu = smp_processor_id();
685 int apicid = hard_smp_processor_id();
687 /* Don't do the funky fallback heuristics the AMD version employs
689 node = apicid_to_node[apicid];
690 if (node == NUMA_NO_NODE)
691 node = first_node(node_online_map);
692 numa_set_node(cpu, node);
694 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
698 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
703 init_intel_cacheinfo(c);
704 if (c->cpuid_level > 9 ) {
705 unsigned eax = cpuid_eax(10);
706 /* Check for version and the number of counters */
707 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
708 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
713 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
715 set_bit(X86_FEATURE_BTS, c->x86_capability);
717 set_bit(X86_FEATURE_PEBS, c->x86_capability);
720 n = c->extended_cpuid_level;
721 if (n >= 0x80000008) {
722 unsigned eax = cpuid_eax(0x80000008);
723 c->x86_virt_bits = (eax >> 8) & 0xff;
724 c->x86_phys_bits = eax & 0xff;
725 /* CPUID workaround for Intel 0F34 CPU */
726 if (c->x86_vendor == X86_VENDOR_INTEL &&
727 c->x86 == 0xF && c->x86_model == 0x3 &&
729 c->x86_phys_bits = 36;
733 c->x86_cache_alignment = c->x86_clflush_size * 2;
734 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
735 (c->x86 == 0x6 && c->x86_model >= 0x0e))
736 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
738 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
740 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
742 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
743 c->x86_max_cores = intel_num_cpu_cores(c);
748 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
750 char *v = c->x86_vendor_id;
752 if (!strcmp(v, "AuthenticAMD"))
753 c->x86_vendor = X86_VENDOR_AMD;
754 else if (!strcmp(v, "GenuineIntel"))
755 c->x86_vendor = X86_VENDOR_INTEL;
757 c->x86_vendor = X86_VENDOR_UNKNOWN;
760 struct cpu_model_info {
763 char *model_names[16];
766 /* Do some early cpuid on the boot CPU to get some parameter that are
767 needed before check_bugs. Everything advanced is in identify_cpu
769 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
773 c->loops_per_jiffy = loops_per_jiffy;
774 c->x86_cache_size = -1;
775 c->x86_vendor = X86_VENDOR_UNKNOWN;
776 c->x86_model = c->x86_mask = 0; /* So far unknown... */
777 c->x86_vendor_id[0] = '\0'; /* Unset */
778 c->x86_model_id[0] = '\0'; /* Unset */
779 c->x86_clflush_size = 64;
780 c->x86_cache_alignment = c->x86_clflush_size;
781 c->x86_max_cores = 1;
782 c->extended_cpuid_level = 0;
783 memset(&c->x86_capability, 0, sizeof c->x86_capability);
785 /* Get vendor name */
786 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
787 (unsigned int *)&c->x86_vendor_id[0],
788 (unsigned int *)&c->x86_vendor_id[8],
789 (unsigned int *)&c->x86_vendor_id[4]);
793 /* Initialize the standard set of capabilities */
794 /* Note that the vendor-specific code below might override */
796 /* Intel-defined flags: level 0x00000001 */
797 if (c->cpuid_level >= 0x00000001) {
799 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
800 &c->x86_capability[0]);
801 c->x86 = (tfms >> 8) & 0xf;
802 c->x86_model = (tfms >> 4) & 0xf;
803 c->x86_mask = tfms & 0xf;
805 c->x86 += (tfms >> 20) & 0xff;
807 c->x86_model += ((tfms >> 16) & 0xF) << 4;
808 if (c->x86_capability[0] & (1<<19))
809 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
811 /* Have CPUID level 0 only - unheard of */
816 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
821 * This does the hard work of actually picking apart the CPU stuff...
823 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
828 early_identify_cpu(c);
830 /* AMD-defined flags: level 0x80000001 */
831 xlvl = cpuid_eax(0x80000000);
832 c->extended_cpuid_level = xlvl;
833 if ((xlvl & 0xffff0000) == 0x80000000) {
834 if (xlvl >= 0x80000001) {
835 c->x86_capability[1] = cpuid_edx(0x80000001);
836 c->x86_capability[6] = cpuid_ecx(0x80000001);
838 if (xlvl >= 0x80000004)
839 get_model_name(c); /* Default name */
842 /* Transmeta-defined flags: level 0x80860001 */
843 xlvl = cpuid_eax(0x80860000);
844 if ((xlvl & 0xffff0000) == 0x80860000) {
845 /* Don't set x86_cpuid_level here for now to not confuse. */
846 if (xlvl >= 0x80860001)
847 c->x86_capability[2] = cpuid_edx(0x80860001);
850 c->apicid = phys_pkg_id(0);
853 * Vendor-specific initialization. In this section we
854 * canonicalize the feature flags, meaning if there are
855 * features a certain CPU supports which CPUID doesn't
856 * tell us, CPUID claiming incorrect flags, or other bugs,
857 * we handle them here.
859 * At the end of this section, c->x86_capability better
860 * indicate the features this CPU genuinely supports!
862 switch (c->x86_vendor) {
867 case X86_VENDOR_INTEL:
871 case X86_VENDOR_UNKNOWN:
873 display_cacheinfo(c);
877 select_idle_routine(c);
881 * On SMP, boot_cpu_data holds the common feature set between
882 * all CPUs; so make sure that we indicate which features are
883 * common between the CPUs. The first time this routine gets
884 * executed, c == &boot_cpu_data.
886 if (c != &boot_cpu_data) {
887 /* AND the already accumulated flags with these */
888 for (i = 0 ; i < NCAPINTS ; i++)
889 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
892 #ifdef CONFIG_X86_MCE
895 if (c == &boot_cpu_data)
900 numa_add_cpu(smp_processor_id());
905 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
907 if (c->x86_model_id[0])
908 printk("%s", c->x86_model_id);
910 if (c->x86_mask || c->cpuid_level >= 0)
911 printk(" stepping %02x\n", c->x86_mask);
917 * Get CPU information for use by the procfs.
920 static int show_cpuinfo(struct seq_file *m, void *v)
922 struct cpuinfo_x86 *c = v;
925 * These flag bits must match the definitions in <asm/cpufeature.h>.
926 * NULL means this bit is undefined or reserved; either way it doesn't
927 * have meaning as far as Linux is concerned. Note that it's important
928 * to realize there is a difference between this table and CPUID -- if
929 * applications want to get the raw CPUID data, they should access
930 * /dev/cpu/<cpu_nr>/cpuid instead.
932 static char *x86_cap_flags[] = {
934 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
935 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
936 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
937 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
940 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
941 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
942 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
943 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
946 /* Transmeta-defined */
947 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
948 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
949 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
950 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
952 /* Other (Linux-defined) */
953 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
954 "constant_tsc", NULL, NULL,
955 "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
957 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
959 /* Intel-defined (#2) */
960 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
961 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
962 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
963 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
965 /* VIA/Cyrix/Centaur-defined */
966 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
967 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
968 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
969 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
971 /* AMD-defined (#2) */
972 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
973 "altmovcr8", "abm", "sse4a",
974 "misalignsse", "3dnowprefetch",
975 "osvw", "ibs", NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
979 static char *x86_power_flags[] = {
980 "ts", /* temperature sensor */
981 "fid", /* frequency id control */
982 "vid", /* voltage id control */
983 "ttp", /* thermal trip */
988 "", /* tsc invariant mapped to constant_tsc */
994 if (!cpu_online(c-cpu_data))
998 seq_printf(m,"processor\t: %u\n"
1000 "cpu family\t: %d\n"
1002 "model name\t: %s\n",
1003 (unsigned)(c-cpu_data),
1004 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1007 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1009 if (c->x86_mask || c->cpuid_level >= 0)
1010 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1012 seq_printf(m, "stepping\t: unknown\n");
1014 if (cpu_has(c,X86_FEATURE_TSC)) {
1015 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1018 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1019 freq / 1000, (freq % 1000));
1023 if (c->x86_cache_size >= 0)
1024 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1027 if (smp_num_siblings * c->x86_max_cores > 1) {
1028 int cpu = c - cpu_data;
1029 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1030 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
1031 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1032 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1038 "fpu_exception\t: yes\n"
1039 "cpuid level\t: %d\n"
1046 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1047 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1048 seq_printf(m, " %s", x86_cap_flags[i]);
1051 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1052 c->loops_per_jiffy/(500000/HZ),
1053 (c->loops_per_jiffy/(5000/HZ)) % 100);
1055 if (c->x86_tlbsize > 0)
1056 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1057 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1058 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1060 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1061 c->x86_phys_bits, c->x86_virt_bits);
1063 seq_printf(m, "power management:");
1066 for (i = 0; i < 32; i++)
1067 if (c->x86_power & (1 << i)) {
1068 if (i < ARRAY_SIZE(x86_power_flags) &&
1070 seq_printf(m, "%s%s",
1071 x86_power_flags[i][0]?" ":"",
1072 x86_power_flags[i]);
1074 seq_printf(m, " [%d]", i);
1078 seq_printf(m, "\n\n");
1083 static void *c_start(struct seq_file *m, loff_t *pos)
1085 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1088 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1091 return c_start(m, pos);
1094 static void c_stop(struct seq_file *m, void *v)
1098 struct seq_operations cpuinfo_op = {
1102 .show = show_cpuinfo,