2 * linux/arch/x86-64/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
11 * This file handles the architecture-dependent parts of initialization
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
18 #include <linux/stddef.h>
19 #include <linux/unistd.h>
20 #include <linux/ptrace.h>
21 #include <linux/slab.h>
22 #include <linux/user.h>
23 #include <linux/a.out.h>
24 #include <linux/screen_info.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/initrd.h>
29 #include <linux/highmem.h>
30 #include <linux/bootmem.h>
31 #include <linux/module.h>
32 #include <asm/processor.h>
33 #include <linux/console.h>
34 #include <linux/seq_file.h>
35 #include <linux/crash_dump.h>
36 #include <linux/root_dev.h>
37 #include <linux/pci.h>
38 #include <linux/acpi.h>
39 #include <linux/kallsyms.h>
40 #include <linux/edd.h>
41 #include <linux/mmzone.h>
42 #include <linux/kexec.h>
43 #include <linux/cpufreq.h>
44 #include <linux/dmi.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/ctype.h>
49 #include <asm/uaccess.h>
50 #include <asm/system.h>
55 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/bootsetup.h>
61 #include <asm/proto.h>
62 #include <asm/setup.h>
63 #include <asm/mach_apic.h>
65 #include <asm/sections.h>
72 struct cpuinfo_x86 boot_cpu_data __read_mostly;
73 EXPORT_SYMBOL(boot_cpu_data);
75 unsigned long mmu_cr4_features;
77 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
80 unsigned long saved_video_mode;
86 char dmi_alloc_data[DMI_MAX_DATA];
91 struct screen_info screen_info;
92 EXPORT_SYMBOL(screen_info);
93 struct sys_desc_table_struct {
94 unsigned short length;
95 unsigned char table[0];
98 struct edid_info edid_info;
99 EXPORT_SYMBOL_GPL(edid_info);
101 extern int root_mountflags;
103 char __initdata command_line[COMMAND_LINE_SIZE];
105 struct resource standard_io_resources[] = {
106 { .name = "dma1", .start = 0x00, .end = 0x1f,
107 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
108 { .name = "pic1", .start = 0x20, .end = 0x21,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "timer0", .start = 0x40, .end = 0x43,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "timer1", .start = 0x50, .end = 0x53,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "keyboard", .start = 0x60, .end = 0x6f,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "pic2", .start = 0xa0, .end = 0xa1,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "dma2", .start = 0xc0, .end = 0xdf,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "fpu", .start = 0xf0, .end = 0xff,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
126 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
128 struct resource data_resource = {
129 .name = "Kernel data",
132 .flags = IORESOURCE_RAM,
134 struct resource code_resource = {
135 .name = "Kernel code",
138 .flags = IORESOURCE_RAM,
141 #ifdef CONFIG_PROC_VMCORE
142 /* elfcorehdr= specifies the location of elf core header
143 * stored by the crashed kernel. This option will be passed
144 * by kexec loader to the capture kernel.
146 static int __init setup_elfcorehdr(char *arg)
151 elfcorehdr_addr = memparse(arg, &end);
152 return end > arg ? 0 : -EINVAL;
154 early_param("elfcorehdr", setup_elfcorehdr);
159 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
161 unsigned long bootmap_size, bootmap;
163 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
164 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
166 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
167 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
168 e820_register_active_regions(0, start_pfn, end_pfn);
169 free_bootmem_with_active_regions(0, end_pfn);
170 reserve_bootmem(bootmap, bootmap_size);
174 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
176 #ifdef CONFIG_EDD_MODULE
180 * copy_edd() - Copy the BIOS EDD information
181 * from boot_params into a safe place.
184 static inline void copy_edd(void)
186 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
187 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
188 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
189 edd.edd_info_nr = EDD_NR;
192 static inline void copy_edd(void)
197 #define EBDA_ADDR_POINTER 0x40E
199 unsigned __initdata ebda_addr;
200 unsigned __initdata ebda_size;
202 static void discover_ebda(void)
205 * there is a real-mode segmented pointer pointing to the
206 * 4K EBDA area at 0x40E
208 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
211 ebda_size = *(unsigned short *)__va(ebda_addr);
213 /* Round EBDA up to pages */
217 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
218 if (ebda_size > 64*1024)
222 void __init setup_arch(char **cmdline_p)
224 printk(KERN_INFO "Command line: %s\n", boot_command_line);
226 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
227 screen_info = SCREEN_INFO;
228 edid_info = EDID_INFO;
229 saved_video_mode = SAVED_VIDEO_MODE;
230 bootloader_type = LOADER_TYPE;
232 #ifdef CONFIG_BLK_DEV_RAM
233 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
234 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
235 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
237 setup_memory_region();
240 if (!MOUNT_ROOT_RDONLY)
241 root_mountflags &= ~MS_RDONLY;
242 init_mm.start_code = (unsigned long) &_text;
243 init_mm.end_code = (unsigned long) &_etext;
244 init_mm.end_data = (unsigned long) &_edata;
245 init_mm.brk = (unsigned long) &_end;
247 code_resource.start = virt_to_phys(&_text);
248 code_resource.end = virt_to_phys(&_etext)-1;
249 data_resource.start = virt_to_phys(&_etext);
250 data_resource.end = virt_to_phys(&_edata)-1;
252 early_identify_cpu(&boot_cpu_data);
254 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
255 *cmdline_p = command_line;
259 finish_e820_parsing();
261 e820_register_active_regions(0, 0, -1UL);
263 * partially used pages are not usable - thus
264 * we are rounding upwards:
266 end_pfn = e820_end_of_ram();
267 num_physpages = end_pfn;
273 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
279 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
280 * Call this early for SRAT node setup.
282 acpi_boot_table_init();
285 /* How many end-of-memory variables you have, grandma! */
286 max_low_pfn = end_pfn;
288 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
290 /* Remove active ranges so rediscovery with NUMA-awareness happens */
291 remove_all_active_ranges();
293 #ifdef CONFIG_ACPI_NUMA
295 * Parse SRAT to discover nodes.
301 numa_initmem_init(0, end_pfn);
303 contig_initmem_init(0, end_pfn);
306 /* Reserve direct mapping */
307 reserve_bootmem_generic(table_start << PAGE_SHIFT,
308 (table_end - table_start) << PAGE_SHIFT);
311 reserve_bootmem_generic(__pa_symbol(&_text),
312 __pa_symbol(&_end) - __pa_symbol(&_text));
315 * reserve physical page 0 - it's a special BIOS page on many boxes,
316 * enabling clean reboots, SMP operation, laptop functions.
318 reserve_bootmem_generic(0, PAGE_SIZE);
320 /* reserve ebda region */
322 reserve_bootmem_generic(ebda_addr, ebda_size);
324 /* reserve nodemap region */
326 reserve_bootmem_generic(nodemap_addr, nodemap_size);
330 /* Reserve SMP trampoline */
331 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
334 #ifdef CONFIG_ACPI_SLEEP
336 * Reserve low memory region for sleep support.
338 acpi_reserve_bootmem();
341 * Find and reserve possible boot-time SMP configuration:
344 #ifdef CONFIG_BLK_DEV_INITRD
345 if (LOADER_TYPE && INITRD_START) {
346 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
347 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
348 initrd_start = INITRD_START + PAGE_OFFSET;
349 initrd_end = initrd_start+INITRD_SIZE;
352 printk(KERN_ERR "initrd extends beyond end of memory "
353 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
354 (unsigned long)(INITRD_START + INITRD_SIZE),
355 (unsigned long)(end_pfn << PAGE_SHIFT));
361 if (crashk_res.start != crashk_res.end) {
362 reserve_bootmem_generic(crashk_res.start,
363 crashk_res.end - crashk_res.start + 1);
374 * set this early, so we dont allocate cpu0
375 * if MADT list doesnt list BSP first
376 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
378 cpu_set(0, cpu_present_map);
381 * Read APIC and some other early information from ACPI tables.
389 * get boot-time SMP configuration:
391 if (smp_found_config)
393 init_apic_mappings();
396 * We trust e820 completely. No explicit ROM probing in memory.
398 e820_reserve_resources();
399 e820_mark_nosave_regions();
403 /* request I/O space for devices used on all i[345]86 PCs */
404 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
405 request_resource(&ioport_resource, &standard_io_resources[i]);
411 #if defined(CONFIG_VGA_CONSOLE)
412 conswitchp = &vga_con;
413 #elif defined(CONFIG_DUMMY_CONSOLE)
414 conswitchp = &dummy_con;
419 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
423 if (c->extended_cpuid_level < 0x80000004)
426 v = (unsigned int *) c->x86_model_id;
427 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
428 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
429 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
430 c->x86_model_id[48] = 0;
435 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
437 unsigned int n, dummy, eax, ebx, ecx, edx;
439 n = c->extended_cpuid_level;
441 if (n >= 0x80000005) {
442 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
443 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
444 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
445 c->x86_cache_size=(ecx>>24)+(edx>>24);
446 /* On K8 L1 TLB is inclusive, so don't count it */
450 if (n >= 0x80000006) {
451 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
452 ecx = cpuid_ecx(0x80000006);
453 c->x86_cache_size = ecx >> 16;
454 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
456 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
457 c->x86_cache_size, ecx & 0xFF);
461 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
462 if (n >= 0x80000008) {
463 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
464 c->x86_virt_bits = (eax >> 8) & 0xff;
465 c->x86_phys_bits = eax & 0xff;
470 static int nearby_node(int apicid)
473 for (i = apicid - 1; i >= 0; i--) {
474 int node = apicid_to_node[i];
475 if (node != NUMA_NO_NODE && node_online(node))
478 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
479 int node = apicid_to_node[i];
480 if (node != NUMA_NO_NODE && node_online(node))
483 return first_node(node_online_map); /* Shouldn't happen */
488 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
489 * Assumes number of cores is a power of two.
491 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
496 int cpu = smp_processor_id();
498 unsigned apicid = hard_smp_processor_id();
500 unsigned ecx = cpuid_ecx(0x80000008);
502 c->x86_max_cores = (ecx & 0xff) + 1;
504 /* CPU telling us the core id bits shift? */
505 bits = (ecx >> 12) & 0xF;
507 /* Otherwise recompute */
509 while ((1 << bits) < c->x86_max_cores)
513 /* Low order bits define the core id (index of core in socket) */
514 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
515 /* Convert the APIC ID into the socket ID */
516 c->phys_proc_id = phys_pkg_id(bits);
519 node = c->phys_proc_id;
520 if (apicid_to_node[apicid] != NUMA_NO_NODE)
521 node = apicid_to_node[apicid];
522 if (!node_online(node)) {
523 /* Two possibilities here:
524 - The CPU is missing memory and no node was created.
525 In that case try picking one from a nearby CPU
526 - The APIC IDs differ from the HyperTransport node IDs
527 which the K8 northbridge parsing fills in.
528 Assume they are all increased by a constant offset,
529 but in the same order as the HT nodeids.
530 If that doesn't result in a usable node fall back to the
531 path for the previous case. */
532 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
533 if (ht_nodeid >= 0 &&
534 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
535 node = apicid_to_node[ht_nodeid];
536 /* Pick a nearby node */
537 if (!node_online(node))
538 node = nearby_node(apicid);
540 numa_set_node(cpu, node);
542 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
547 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
555 * Disable TLB flush filter by setting HWCR.FFDIS on K8
556 * bit 6 of msr C001_0015
558 * Errata 63 for SH-B3 steppings
559 * Errata 122 for all steppings (F+ have it disabled by default)
562 rdmsrl(MSR_K8_HWCR, value);
564 wrmsrl(MSR_K8_HWCR, value);
568 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
569 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
570 clear_bit(0*32+31, &c->x86_capability);
572 /* On C+ stepping K8 rep microcode works well for copy/memset */
573 level = cpuid_eax(1);
574 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
575 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
577 /* Enable workaround for FXSAVE leak */
579 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
581 level = get_model_name(c);
585 /* Should distinguish Models here, but this is only
586 a fallback anyways. */
587 strcpy(c->x86_model_id, "Hammer");
591 display_cacheinfo(c);
593 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
594 if (c->x86_power & (1<<8))
595 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
597 /* Multi core CPU? */
598 if (c->extended_cpuid_level >= 0x80000008)
601 /* Fix cpuid4 emulation for more */
602 num_cache_leaves = 3;
604 /* RDTSC can be speculated around */
605 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
608 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
611 u32 eax, ebx, ecx, edx;
612 int index_msb, core_bits;
614 cpuid(1, &eax, &ebx, &ecx, &edx);
617 if (!cpu_has(c, X86_FEATURE_HT))
619 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
622 smp_num_siblings = (ebx & 0xff0000) >> 16;
624 if (smp_num_siblings == 1) {
625 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
626 } else if (smp_num_siblings > 1 ) {
628 if (smp_num_siblings > NR_CPUS) {
629 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
630 smp_num_siblings = 1;
634 index_msb = get_count_order(smp_num_siblings);
635 c->phys_proc_id = phys_pkg_id(index_msb);
637 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
639 index_msb = get_count_order(smp_num_siblings) ;
641 core_bits = get_count_order(c->x86_max_cores);
643 c->cpu_core_id = phys_pkg_id(index_msb) &
644 ((1 << core_bits) - 1);
647 if ((c->x86_max_cores * smp_num_siblings) > 1) {
648 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
649 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
656 * find out the number of processor cores on the die
658 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
662 if (c->cpuid_level < 4)
665 cpuid_count(4, 0, &eax, &t, &t, &t);
668 return ((eax >> 26) + 1);
673 static void srat_detect_node(void)
677 int cpu = smp_processor_id();
678 int apicid = hard_smp_processor_id();
680 /* Don't do the funky fallback heuristics the AMD version employs
682 node = apicid_to_node[apicid];
683 if (node == NUMA_NO_NODE)
684 node = first_node(node_online_map);
685 numa_set_node(cpu, node);
687 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
691 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
696 init_intel_cacheinfo(c);
697 if (c->cpuid_level > 9 ) {
698 unsigned eax = cpuid_eax(10);
699 /* Check for version and the number of counters */
700 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
701 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
706 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
708 set_bit(X86_FEATURE_BTS, c->x86_capability);
710 set_bit(X86_FEATURE_PEBS, c->x86_capability);
713 n = c->extended_cpuid_level;
714 if (n >= 0x80000008) {
715 unsigned eax = cpuid_eax(0x80000008);
716 c->x86_virt_bits = (eax >> 8) & 0xff;
717 c->x86_phys_bits = eax & 0xff;
718 /* CPUID workaround for Intel 0F34 CPU */
719 if (c->x86_vendor == X86_VENDOR_INTEL &&
720 c->x86 == 0xF && c->x86_model == 0x3 &&
722 c->x86_phys_bits = 36;
726 c->x86_cache_alignment = c->x86_clflush_size * 2;
727 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
728 (c->x86 == 0x6 && c->x86_model >= 0x0e))
729 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
731 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
733 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
735 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
736 c->x86_max_cores = intel_num_cpu_cores(c);
741 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
743 char *v = c->x86_vendor_id;
745 if (!strcmp(v, "AuthenticAMD"))
746 c->x86_vendor = X86_VENDOR_AMD;
747 else if (!strcmp(v, "GenuineIntel"))
748 c->x86_vendor = X86_VENDOR_INTEL;
750 c->x86_vendor = X86_VENDOR_UNKNOWN;
753 struct cpu_model_info {
756 char *model_names[16];
759 /* Do some early cpuid on the boot CPU to get some parameter that are
760 needed before check_bugs. Everything advanced is in identify_cpu
762 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
766 c->loops_per_jiffy = loops_per_jiffy;
767 c->x86_cache_size = -1;
768 c->x86_vendor = X86_VENDOR_UNKNOWN;
769 c->x86_model = c->x86_mask = 0; /* So far unknown... */
770 c->x86_vendor_id[0] = '\0'; /* Unset */
771 c->x86_model_id[0] = '\0'; /* Unset */
772 c->x86_clflush_size = 64;
773 c->x86_cache_alignment = c->x86_clflush_size;
774 c->x86_max_cores = 1;
775 c->extended_cpuid_level = 0;
776 memset(&c->x86_capability, 0, sizeof c->x86_capability);
778 /* Get vendor name */
779 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
780 (unsigned int *)&c->x86_vendor_id[0],
781 (unsigned int *)&c->x86_vendor_id[8],
782 (unsigned int *)&c->x86_vendor_id[4]);
786 /* Initialize the standard set of capabilities */
787 /* Note that the vendor-specific code below might override */
789 /* Intel-defined flags: level 0x00000001 */
790 if (c->cpuid_level >= 0x00000001) {
792 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
793 &c->x86_capability[0]);
794 c->x86 = (tfms >> 8) & 0xf;
795 c->x86_model = (tfms >> 4) & 0xf;
796 c->x86_mask = tfms & 0xf;
798 c->x86 += (tfms >> 20) & 0xff;
800 c->x86_model += ((tfms >> 16) & 0xF) << 4;
801 if (c->x86_capability[0] & (1<<19))
802 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
804 /* Have CPUID level 0 only - unheard of */
809 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
814 * This does the hard work of actually picking apart the CPU stuff...
816 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
821 early_identify_cpu(c);
823 /* AMD-defined flags: level 0x80000001 */
824 xlvl = cpuid_eax(0x80000000);
825 c->extended_cpuid_level = xlvl;
826 if ((xlvl & 0xffff0000) == 0x80000000) {
827 if (xlvl >= 0x80000001) {
828 c->x86_capability[1] = cpuid_edx(0x80000001);
829 c->x86_capability[6] = cpuid_ecx(0x80000001);
831 if (xlvl >= 0x80000004)
832 get_model_name(c); /* Default name */
835 /* Transmeta-defined flags: level 0x80860001 */
836 xlvl = cpuid_eax(0x80860000);
837 if ((xlvl & 0xffff0000) == 0x80860000) {
838 /* Don't set x86_cpuid_level here for now to not confuse. */
839 if (xlvl >= 0x80860001)
840 c->x86_capability[2] = cpuid_edx(0x80860001);
843 c->apicid = phys_pkg_id(0);
846 * Vendor-specific initialization. In this section we
847 * canonicalize the feature flags, meaning if there are
848 * features a certain CPU supports which CPUID doesn't
849 * tell us, CPUID claiming incorrect flags, or other bugs,
850 * we handle them here.
852 * At the end of this section, c->x86_capability better
853 * indicate the features this CPU genuinely supports!
855 switch (c->x86_vendor) {
860 case X86_VENDOR_INTEL:
864 case X86_VENDOR_UNKNOWN:
866 display_cacheinfo(c);
870 select_idle_routine(c);
874 * On SMP, boot_cpu_data holds the common feature set between
875 * all CPUs; so make sure that we indicate which features are
876 * common between the CPUs. The first time this routine gets
877 * executed, c == &boot_cpu_data.
879 if (c != &boot_cpu_data) {
880 /* AND the already accumulated flags with these */
881 for (i = 0 ; i < NCAPINTS ; i++)
882 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
885 #ifdef CONFIG_X86_MCE
888 if (c == &boot_cpu_data)
893 numa_add_cpu(smp_processor_id());
898 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
900 if (c->x86_model_id[0])
901 printk("%s", c->x86_model_id);
903 if (c->x86_mask || c->cpuid_level >= 0)
904 printk(" stepping %02x\n", c->x86_mask);
910 * Get CPU information for use by the procfs.
913 static int show_cpuinfo(struct seq_file *m, void *v)
915 struct cpuinfo_x86 *c = v;
918 * These flag bits must match the definitions in <asm/cpufeature.h>.
919 * NULL means this bit is undefined or reserved; either way it doesn't
920 * have meaning as far as Linux is concerned. Note that it's important
921 * to realize there is a difference between this table and CPUID -- if
922 * applications want to get the raw CPUID data, they should access
923 * /dev/cpu/<cpu_nr>/cpuid instead.
925 static char *x86_cap_flags[] = {
927 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
928 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
929 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
930 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
933 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
934 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
935 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
936 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
939 /* Transmeta-defined */
940 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
941 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
942 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
943 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
945 /* Other (Linux-defined) */
946 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
947 "constant_tsc", NULL, NULL,
948 "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
949 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
950 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
952 /* Intel-defined (#2) */
953 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
954 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
955 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
956 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
958 /* VIA/Cyrix/Centaur-defined */
959 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
960 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
961 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
962 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
964 /* AMD-defined (#2) */
965 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
966 "altmovcr8", "abm", "sse4a",
967 "misalignsse", "3dnowprefetch",
968 "osvw", "ibs", NULL, NULL, NULL, NULL,
969 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
970 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
972 static char *x86_power_flags[] = {
973 "ts", /* temperature sensor */
974 "fid", /* frequency id control */
975 "vid", /* voltage id control */
976 "ttp", /* thermal trip */
981 NULL, /* tsc invariant mapped to constant_tsc */
983 /* nothing */ /* constant_tsc - moved to flags */
988 if (!cpu_online(c-cpu_data))
992 seq_printf(m,"processor\t: %u\n"
996 "model name\t: %s\n",
997 (unsigned)(c-cpu_data),
998 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1001 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1003 if (c->x86_mask || c->cpuid_level >= 0)
1004 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1006 seq_printf(m, "stepping\t: unknown\n");
1008 if (cpu_has(c,X86_FEATURE_TSC)) {
1009 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1012 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1013 freq / 1000, (freq % 1000));
1017 if (c->x86_cache_size >= 0)
1018 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1021 if (smp_num_siblings * c->x86_max_cores > 1) {
1022 int cpu = c - cpu_data;
1023 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1024 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
1025 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1026 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1032 "fpu_exception\t: yes\n"
1033 "cpuid level\t: %d\n"
1040 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1041 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1042 seq_printf(m, " %s", x86_cap_flags[i]);
1045 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1046 c->loops_per_jiffy/(500000/HZ),
1047 (c->loops_per_jiffy/(5000/HZ)) % 100);
1049 if (c->x86_tlbsize > 0)
1050 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1051 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1052 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1054 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1055 c->x86_phys_bits, c->x86_virt_bits);
1057 seq_printf(m, "power management:");
1060 for (i = 0; i < 32; i++)
1061 if (c->x86_power & (1 << i)) {
1062 if (i < ARRAY_SIZE(x86_power_flags) &&
1064 seq_printf(m, "%s%s",
1065 x86_power_flags[i][0]?" ":"",
1066 x86_power_flags[i]);
1068 seq_printf(m, " [%d]", i);
1072 seq_printf(m, "\n\n");
1077 static void *c_start(struct seq_file *m, loff_t *pos)
1079 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1082 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1085 return c_start(m, pos);
1088 static void c_stop(struct seq_file *m, void *v)
1092 struct seq_operations cpuinfo_op = {
1096 .show = show_cpuinfo,