arch/xtensa/kernel/setup.c

   1 /*
   2  * arch/xtensa/kernel/setup.c
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995  Linus Torvalds
   9  * Copyright (C) 2001 - 2005  Tensilica Inc.
  10  *
  11  * Chris Zankel <chris@zankel.net>
  12  * Joe Taylor   <joe@tensilica.com, joetylr@yahoo.com>
  13  * Kevin Chea
  14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/mm.h>
  20 #include <linux/proc_fs.h>
  21 #include <linux/screen_info.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_fdt.h>
  25 #include <linux/of_platform.h>
  26
  27 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  28 # include <linux/console.h>
  29 #endif
  30
  31 #ifdef CONFIG_RTC
  32 # include <linux/timex.h>
  33 #endif
  34
  35 #ifdef CONFIG_PROC_FS
  36 # include <linux/seq_file.h>
  37 #endif
  38
  39 #include <asm/bootparam.h>
  40 #include <asm/pgtable.h>
  41 #include <asm/processor.h>
  42 #include <asm/timex.h>
  43 #include <asm/platform.h>
  44 #include <asm/page.h>
  45 #include <asm/setup.h>
  46 #include <asm/param.h>
  47 #include <asm/traps.h>
  48
  49 #include <platform/hardware.h>
  50
  51 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  52 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
  53 #endif
  54
  55 #ifdef CONFIG_BLK_DEV_FD
  56 extern struct fd_ops no_fd_ops;
  57 struct fd_ops *fd_ops;
  58 #endif
  59
  60 extern struct rtc_ops no_rtc_ops;
  61 struct rtc_ops *rtc_ops;
  62
  63 #ifdef CONFIG_BLK_DEV_INITRD
  64 extern void *initrd_start;
  65 extern void *initrd_end;
  66 int initrd_is_mapped = 0;
  67 extern int initrd_below_start_ok;
  68 #endif
  69
  70 #ifdef CONFIG_OF
  71 extern u32 __dtb_start[];
  72 void *dtb_start = __dtb_start;
  73 #endif
  74
  75 unsigned char aux_device_present;
  76 extern unsigned long loops_per_jiffy;
  77
  78 /* Command line specified as configuration option. */
  79
  80 static char __initdata command_line[COMMAND_LINE_SIZE];
  81
  82 #ifdef CONFIG_CMDLINE_BOOL
  83 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  84 #endif
  85
  86 sysmem_info_t __initdata sysmem;
  87
  88 #ifdef CONFIG_MMU
  89 extern void init_mmu(void);
  90 #else
  91 static inline void init_mmu(void) { }
  92 #endif
  93
  94 extern int mem_reserve(unsigned long, unsigned long, int);
  95 extern void bootmem_init(void);
  96 extern void zones_init(void);
  97
  98 /*
  99  * Boot parameter parsing.
 100  *
 101  * The Xtensa port uses a list of variable-sized tags to pass data to
 102  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
 103  * to be recognised. The list is terminated with a zero-sized
 104  * BP_TAG_LAST tag.
 105  */
 106
 107 typedef struct tagtable {
 108         u32 tag;
 109         int (*parse)(const bp_tag_t*);
 110 } tagtable_t;
 111
 112 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn           \
 113         __attribute__((used, section(".taglist"))) = { tag, fn }
 114
 115 /* parse current tag */
 116
 117 static int __init add_sysmem_bank(unsigned long type, unsigned long start,
 118                 unsigned long end)
 119 {
 120         if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
 121                 printk(KERN_WARNING
 122                                 "Ignoring memory bank 0x%08lx size %ldKB\n",
 123                                 start, end - start);
 124                 return -EINVAL;
 125         }
 126         sysmem.bank[sysmem.nr_banks].type  = type;
 127         sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(start);
 128         sysmem.bank[sysmem.nr_banks].end   = end & PAGE_MASK;
 129         sysmem.nr_banks++;
 130
 131         return 0;
 132 }
 133
 134 static int __init parse_tag_mem(const bp_tag_t *tag)
 135 {
 136         meminfo_t *mi = (meminfo_t *)(tag->data);
 137
 138         if (mi->type != MEMORY_TYPE_CONVENTIONAL)
 139                 return -1;
 140
 141         return add_sysmem_bank(mi->type, mi->start, mi->end);
 142 }
 143
 144 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
 145
 146 #ifdef CONFIG_BLK_DEV_INITRD
 147
 148 static int __init parse_tag_initrd(const bp_tag_t* tag)
 149 {
 150         meminfo_t* mi;
 151         mi = (meminfo_t*)(tag->data);
 152         initrd_start = __va(mi->start);
 153         initrd_end = __va(mi->end);
 154
 155         return 0;
 156 }
 157
 158 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
 159
 160 #ifdef CONFIG_OF
 161
 162 static int __init parse_tag_fdt(const bp_tag_t *tag)
 163 {
 164         dtb_start = __va(tag->data[0]);
 165         return 0;
 166 }
 167
 168 __tagtable(BP_TAG_FDT, parse_tag_fdt);
 169
 170 void __init early_init_dt_setup_initrd_arch(u64 start, u64 end)
 171 {
 172         initrd_start = (void *)__va(start);
 173         initrd_end = (void *)__va(end);
 174         initrd_below_start_ok = 1;
 175 }
 176
 177 #endif /* CONFIG_OF */
 178
 179 #endif /* CONFIG_BLK_DEV_INITRD */
 180
 181 static int __init parse_tag_cmdline(const bp_tag_t* tag)
 182 {
 183         strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
 184         return 0;
 185 }
 186
 187 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
 188
 189 static int __init parse_bootparam(const bp_tag_t* tag)
 190 {
 191         extern tagtable_t __tagtable_begin, __tagtable_end;
 192         tagtable_t *t;
 193
 194         /* Boot parameters must start with a BP_TAG_FIRST tag. */
 195
 196         if (tag->id != BP_TAG_FIRST) {
 197                 printk(KERN_WARNING "Invalid boot parameters!\n");
 198                 return 0;
 199         }
 200
 201         tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
 202
 203         /* Parse all tags. */
 204
 205         while (tag != NULL && tag->id != BP_TAG_LAST) {
 206                 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
 207                         if (tag->id == t->tag) {
 208                                 t->parse(tag);
 209                                 break;
 210                         }
 211                 }
 212                 if (t == &__tagtable_end)
 213                         printk(KERN_WARNING "Ignoring tag "
 214                                "0x%08x\n", tag->id);
 215                 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
 216         }
 217
 218         return 0;
 219 }
 220
 221 #ifdef CONFIG_OF
 222 bool __initdata dt_memory_scan = false;
 223
 224 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 225 {
 226         if (!dt_memory_scan)
 227                 return;
 228
 229         size &= PAGE_MASK;
 230         add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL, base, base + size);
 231 }
 232
 233 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 234 {
 235         return __alloc_bootmem(size, align, 0);
 236 }
 237
 238 void __init early_init_devtree(void *params)
 239 {
 240         if (sysmem.nr_banks == 0)
 241                 dt_memory_scan = true;
 242
 243         early_init_dt_scan(params);
 244
 245         if (!command_line[0])
 246                 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 247 }
 248
 249 static int __init xtensa_device_probe(void)
 250 {
 251         of_platform_populate(NULL, NULL, NULL, NULL);
 252         return 0;
 253 }
 254
 255 device_initcall(xtensa_device_probe);
 256
 257 #endif /* CONFIG_OF */
 258
 259 /*
 260  * Initialize architecture. (Early stage)
 261  */
 262
 263 void __init init_arch(bp_tag_t *bp_start)
 264 {
 265         sysmem.nr_banks = 0;
 266
 267         /* Parse boot parameters */
 268
 269         if (bp_start)
 270                 parse_bootparam(bp_start);
 271
 272 #ifdef CONFIG_OF
 273         early_init_devtree(dtb_start);
 274 #endif
 275
 276         if (sysmem.nr_banks == 0) {
 277                 sysmem.nr_banks = 1;
 278                 sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
 279                 sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
 280                                      + PLATFORM_DEFAULT_MEM_SIZE;
 281         }
 282
 283 #ifdef CONFIG_CMDLINE_BOOL
 284         if (!command_line[0])
 285                 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
 286 #endif
 287
 288         /* Early hook for platforms */
 289
 290         platform_init(bp_start);
 291
 292         /* Initialize MMU. */
 293
 294         init_mmu();
 295 }
 296
 297 /*
 298  * Initialize system. Setup memory and reserve regions.
 299  */
 300
 301 extern char _end;
 302 extern char _stext;
 303 extern char _WindowVectors_text_start;
 304 extern char _WindowVectors_text_end;
 305 extern char _DebugInterruptVector_literal_start;
 306 extern char _DebugInterruptVector_text_end;
 307 extern char _KernelExceptionVector_literal_start;
 308 extern char _KernelExceptionVector_text_end;
 309 extern char _UserExceptionVector_literal_start;
 310 extern char _UserExceptionVector_text_end;
 311 extern char _DoubleExceptionVector_literal_start;
 312 extern char _DoubleExceptionVector_text_end;
 313 #if XCHAL_EXCM_LEVEL >= 2
 314 extern char _Level2InterruptVector_text_start;
 315 extern char _Level2InterruptVector_text_end;
 316 #endif
 317 #if XCHAL_EXCM_LEVEL >= 3
 318 extern char _Level3InterruptVector_text_start;
 319 extern char _Level3InterruptVector_text_end;
 320 #endif
 321 #if XCHAL_EXCM_LEVEL >= 4
 322 extern char _Level4InterruptVector_text_start;
 323 extern char _Level4InterruptVector_text_end;
 324 #endif
 325 #if XCHAL_EXCM_LEVEL >= 5
 326 extern char _Level5InterruptVector_text_start;
 327 extern char _Level5InterruptVector_text_end;
 328 #endif
 329 #if XCHAL_EXCM_LEVEL >= 6
 330 extern char _Level6InterruptVector_text_start;
 331 extern char _Level6InterruptVector_text_end;
 332 #endif
 333
 334
 335
 336 #ifdef CONFIG_S32C1I_SELFTEST
 337 #if XCHAL_HAVE_S32C1I
 338
 339 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
 340
 341 /*
 342  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
 343  *
 344  * If *v == cmp, set *v = set.  Return previous *v.
 345  */
 346 static inline int probed_compare_swap(int *v, int cmp, int set)
 347 {
 348         int tmp;
 349
 350         __asm__ __volatile__(
 351                         "       movi    %1, 1f\n"
 352                         "       s32i    %1, %4, 0\n"
 353                         "       wsr     %2, scompare1\n"
 354                         "1:     s32c1i  %0, %3, 0\n"
 355                         : "=a" (set), "=&a" (tmp)
 356                         : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
 357                         : "memory"
 358                         );
 359         return set;
 360 }
 361
 362 /* Handle probed exception */
 363
 364 void __init do_probed_exception(struct pt_regs *regs, unsigned long exccause)
 365 {
 366         if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
 367                 regs->pc += 3;          /* skip the s32c1i instruction */
 368                 rcw_exc = exccause;
 369         } else {
 370                 do_unhandled(regs, exccause);
 371         }
 372 }
 373
 374 /* Simple test of S32C1I (soc bringup assist) */
 375
 376 void __init check_s32c1i(void)
 377 {
 378         int n, cause1, cause2;
 379         void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
 380
 381         rcw_probe_pc = 0;
 382         handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
 383                         do_probed_exception);
 384         handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
 385                         do_probed_exception);
 386         handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
 387                         do_probed_exception);
 388
 389         /* First try an S32C1I that does not store: */
 390         rcw_exc = 0;
 391         rcw_word = 1;
 392         n = probed_compare_swap(&rcw_word, 0, 2);
 393         cause1 = rcw_exc;
 394
 395         /* took exception? */
 396         if (cause1 != 0) {
 397                 /* unclean exception? */
 398                 if (n != 2 || rcw_word != 1)
 399                         panic("S32C1I exception error");
 400         } else if (rcw_word != 1 || n != 1) {
 401                 panic("S32C1I compare error");
 402         }
 403
 404         /* Then an S32C1I that stores: */
 405         rcw_exc = 0;
 406         rcw_word = 0x1234567;
 407         n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
 408         cause2 = rcw_exc;
 409
 410         if (cause2 != 0) {
 411                 /* unclean exception? */
 412                 if (n != 0xabcde || rcw_word != 0x1234567)
 413                         panic("S32C1I exception error (b)");
 414         } else if (rcw_word != 0xabcde || n != 0x1234567) {
 415                 panic("S32C1I store error");
 416         }
 417
 418         /* Verify consistency of exceptions: */
 419         if (cause1 || cause2) {
 420                 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
 421                 /* If emulation of S32C1I upon bus error gets implemented,
 422                    we can get rid of this panic for single core (not SMP) */
 423                 panic("S32C1I exceptions not currently supported");
 424         }
 425         if (cause1 != cause2)
 426                 panic("inconsistent S32C1I exceptions");
 427
 428         trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
 429         trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
 430         trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
 431 }
 432
 433 #else /* XCHAL_HAVE_S32C1I */
 434
 435 /* This condition should not occur with a commercially deployed processor.
 436    Display reminder for early engr test or demo chips / FPGA bitstreams */
 437 void __init check_s32c1i(void)
 438 {
 439         pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
 440 }
 441
 442 #endif /* XCHAL_HAVE_S32C1I */
 443 #else /* CONFIG_S32C1I_SELFTEST */
 444
 445 void __init check_s32c1i(void)
 446 {
 447 }
 448
 449 #endif /* CONFIG_S32C1I_SELFTEST */
 450
 451
 452 void __init setup_arch(char **cmdline_p)
 453 {
 454         strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 455         *cmdline_p = command_line;
 456
 457         check_s32c1i();
 458
 459         /* Reserve some memory regions */
 460
 461 #ifdef CONFIG_BLK_DEV_INITRD
 462         if (initrd_start < initrd_end) {
 463                 initrd_is_mapped = mem_reserve(__pa(initrd_start),
 464                                                __pa(initrd_end), 0);
 465                 initrd_below_start_ok = 1;
 466         } else {
 467                 initrd_start = 0;
 468         }
 469 #endif
 470
 471         mem_reserve(__pa(&_stext),__pa(&_end), 1);
 472
 473         mem_reserve(__pa(&_WindowVectors_text_start),
 474                     __pa(&_WindowVectors_text_end), 0);
 475
 476         mem_reserve(__pa(&_DebugInterruptVector_literal_start),
 477                     __pa(&_DebugInterruptVector_text_end), 0);
 478
 479         mem_reserve(__pa(&_KernelExceptionVector_literal_start),
 480                     __pa(&_KernelExceptionVector_text_end), 0);
 481
 482         mem_reserve(__pa(&_UserExceptionVector_literal_start),
 483                     __pa(&_UserExceptionVector_text_end), 0);
 484
 485         mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
 486                     __pa(&_DoubleExceptionVector_text_end), 0);
 487
 488 #if XCHAL_EXCM_LEVEL >= 2
 489         mem_reserve(__pa(&_Level2InterruptVector_text_start),
 490                     __pa(&_Level2InterruptVector_text_end), 0);
 491 #endif
 492 #if XCHAL_EXCM_LEVEL >= 3
 493         mem_reserve(__pa(&_Level3InterruptVector_text_start),
 494                     __pa(&_Level3InterruptVector_text_end), 0);
 495 #endif
 496 #if XCHAL_EXCM_LEVEL >= 4
 497         mem_reserve(__pa(&_Level4InterruptVector_text_start),
 498                     __pa(&_Level4InterruptVector_text_end), 0);
 499 #endif
 500 #if XCHAL_EXCM_LEVEL >= 5
 501         mem_reserve(__pa(&_Level5InterruptVector_text_start),
 502                     __pa(&_Level5InterruptVector_text_end), 0);
 503 #endif
 504 #if XCHAL_EXCM_LEVEL >= 6
 505         mem_reserve(__pa(&_Level6InterruptVector_text_start),
 506                     __pa(&_Level6InterruptVector_text_end), 0);
 507 #endif
 508
 509         bootmem_init();
 510
 511         unflatten_and_copy_device_tree();
 512
 513         platform_setup(cmdline_p);
 514
 515         paging_init();
 516         zones_init();
 517
 518 #ifdef CONFIG_VT
 519 # if defined(CONFIG_VGA_CONSOLE)
 520         conswitchp = &vga_con;
 521 # elif defined(CONFIG_DUMMY_CONSOLE)
 522         conswitchp = &dummy_con;
 523 # endif
 524 #endif
 525
 526 #ifdef CONFIG_PCI
 527         platform_pcibios_init();
 528 #endif
 529 }
 530
 531 void machine_restart(char * cmd)
 532 {
 533         platform_restart();
 534 }
 535
 536 void machine_halt(void)
 537 {
 538         platform_halt();
 539         while (1);
 540 }
 541
 542 void machine_power_off(void)
 543 {
 544         platform_power_off();
 545         while (1);
 546 }
 547 #ifdef CONFIG_PROC_FS
 548
 549 /*
 550  * Display some core information through /proc/cpuinfo.
 551  */
 552
 553 static int
 554 c_show(struct seq_file *f, void *slot)
 555 {
 556         /* high-level stuff */
 557         seq_printf(f,"processor\t: 0\n"
 558                      "vendor_id\t: Tensilica\n"
 559                      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
 560                      "core ID\t\t: " XCHAL_CORE_ID "\n"
 561                      "build ID\t: 0x%x\n"
 562                      "byte order\t: %s\n"
 563                      "cpu MHz\t\t: %lu.%02lu\n"
 564                      "bogomips\t: %lu.%02lu\n",
 565                      XCHAL_BUILD_UNIQUE_ID,
 566                      XCHAL_HAVE_BE ?  "big" : "little",
 567                      ccount_freq/1000000,
 568                      (ccount_freq/10000) % 100,
 569                      loops_per_jiffy/(500000/HZ),
 570                      (loops_per_jiffy/(5000/HZ)) % 100);
 571
 572         seq_printf(f,"flags\t\t: "
 573 #if XCHAL_HAVE_NMI
 574                      "nmi "
 575 #endif
 576 #if XCHAL_HAVE_DEBUG
 577                      "debug "
 578 # if XCHAL_HAVE_OCD
 579                      "ocd "
 580 # endif
 581 #endif
 582 #if XCHAL_HAVE_DENSITY
 583                      "density "
 584 #endif
 585 #if XCHAL_HAVE_BOOLEANS
 586                      "boolean "
 587 #endif
 588 #if XCHAL_HAVE_LOOPS
 589                      "loop "
 590 #endif
 591 #if XCHAL_HAVE_NSA
 592                      "nsa "
 593 #endif
 594 #if XCHAL_HAVE_MINMAX
 595                      "minmax "
 596 #endif
 597 #if XCHAL_HAVE_SEXT
 598                      "sext "
 599 #endif
 600 #if XCHAL_HAVE_CLAMPS
 601                      "clamps "
 602 #endif
 603 #if XCHAL_HAVE_MAC16
 604                      "mac16 "
 605 #endif
 606 #if XCHAL_HAVE_MUL16
 607                      "mul16 "
 608 #endif
 609 #if XCHAL_HAVE_MUL32
 610                      "mul32 "
 611 #endif
 612 #if XCHAL_HAVE_MUL32_HIGH
 613                      "mul32h "
 614 #endif
 615 #if XCHAL_HAVE_FP
 616                      "fpu "
 617 #endif
 618 #if XCHAL_HAVE_S32C1I
 619                      "s32c1i "
 620 #endif
 621                      "\n");
 622
 623         /* Registers. */
 624         seq_printf(f,"physical aregs\t: %d\n"
 625                      "misc regs\t: %d\n"
 626                      "ibreak\t\t: %d\n"
 627                      "dbreak\t\t: %d\n",
 628                      XCHAL_NUM_AREGS,
 629                      XCHAL_NUM_MISC_REGS,
 630                      XCHAL_NUM_IBREAK,
 631                      XCHAL_NUM_DBREAK);
 632
 633
 634         /* Interrupt. */
 635         seq_printf(f,"num ints\t: %d\n"
 636                      "ext ints\t: %d\n"
 637                      "int levels\t: %d\n"
 638                      "timers\t\t: %d\n"
 639                      "debug level\t: %d\n",
 640                      XCHAL_NUM_INTERRUPTS,
 641                      XCHAL_NUM_EXTINTERRUPTS,
 642                      XCHAL_NUM_INTLEVELS,
 643                      XCHAL_NUM_TIMERS,
 644                      XCHAL_DEBUGLEVEL);
 645
 646         /* Cache */
 647         seq_printf(f,"icache line size: %d\n"
 648                      "icache ways\t: %d\n"
 649                      "icache size\t: %d\n"
 650                      "icache flags\t: "
 651 #if XCHAL_ICACHE_LINE_LOCKABLE
 652                      "lock "
 653 #endif
 654                      "\n"
 655                      "dcache line size: %d\n"
 656                      "dcache ways\t: %d\n"
 657                      "dcache size\t: %d\n"
 658                      "dcache flags\t: "
 659 #if XCHAL_DCACHE_IS_WRITEBACK
 660                      "writeback "
 661 #endif
 662 #if XCHAL_DCACHE_LINE_LOCKABLE
 663                      "lock "
 664 #endif
 665                      "\n",
 666                      XCHAL_ICACHE_LINESIZE,
 667                      XCHAL_ICACHE_WAYS,
 668                      XCHAL_ICACHE_SIZE,
 669                      XCHAL_DCACHE_LINESIZE,
 670                      XCHAL_DCACHE_WAYS,
 671                      XCHAL_DCACHE_SIZE);
 672
 673         return 0;
 674 }
 675
 676 /*
 677  * We show only CPU #0 info.
 678  */
 679 static void *
 680 c_start(struct seq_file *f, loff_t *pos)
 681 {
 682         return (void *) ((*pos == 0) ? (void *)1 : NULL);
 683 }
 684
 685 static void *
 686 c_next(struct seq_file *f, void *v, loff_t *pos)
 687 {
 688         return NULL;
 689 }
 690
 691 static void
 692 c_stop(struct seq_file *f, void *v)
 693 {
 694 }
 695
 696 const struct seq_operations cpuinfo_op =
 697 {
 698         start:  c_start,
 699         next:   c_next,
 700         stop:   c_stop,
 701         show:   c_show
 702 };
 703
 704 #endif /* CONFIG_PROC_FS */